# Patent

## Title
Active polyphase inverter filter for quadrature signal generation

## Abstract

A quadrature signal generator receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature generator includes a coarse stage and a plurality of refinement stages. The coarse stage generates quadrature signals that may have some phase error, and the refinement stages process the quadrature signals to reduce any phase error. The refinement stages receive quadrature signals from the output of the coarse stage, and processes the quadrature signals to reduce the phase errors. The coarse stage and the refinement stages are configured using delay circuits that can be implemented with inverter circuits, such as, for example, CMOS inverter circuits. In the refinement stages, corresponding outputs of the delay stages are averaged together to reduce the quadrature phase error.

## Background
The present application claims the benefit of U.S. Provisional Patent Application No. 60/386,484, filed on Jun. 7, 2002, which is incorporated herein by reference in its entirety.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to signal generation, and more specifically to quadrature signal generation using an active polyphase inverter filter.
2. Background Art
In electronic communications, it is often useful to send and receive information using two or more signals that have a quadrature relationship. For instance, one information signal is designated the in-phase signal (I), and the other information signal is designated the quadrature signal (Q), where the Q signal is 90 degrees out of phase with the I signal. More specifically, the Q signal is delayed (or advanced) relative to the I signal (in-time) by 90 degrees.
Quadrature amplitude modulation (QAM) and quadrature phase shift keying (QPSK) are two well known specific examples of quadrature modulation.
The advantage of the quadrature signal transmission is that the bandwidth of a transmission medium is effectively doubled. In other words, if a particular transmission medium has a bandwidth of B (Hz), then quadrature modulation permits 2B (Hz) of information to be effectively transmitted through the medium without signal interference. This occurs because the I and Q signals occupy the transmission medium simultaneously, but are phase shifted with respect to each. At the receiver, the I and Q information can be discerned from each other by sampling the I and Q signals at the proper time based on the known 90 degree phase delay. However, the I and Q sampling times must be properly timed. Any error in sampling time will cause signal distortion and/or interference between the I and Q channels.
What is needed is a circuit and method to generate control signals that have precise timing to control sampling of I and Q signals. Furthermore, the circuit that generates the control signals should be able to be integrated on an integrated circuit.
BRIEF SUMMARY OF THE INVENTION
The present invention is related to a quadrature signal generator that receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature signal generator is an open-loop architecture that utilizes active inverters for delay elements. The invention is also related to subcomponents and methods related to the same.
The quadrature signal generator includes a coarse stage and a plurality of refinement stages. The coarse stage receives a differential input signal and generates a plurality of quadrature signals that are substantially phase-shifted by 90 degrees with respect to each other, but which may have some phase errors. The refinement stages receive quadrature signals from the output of the coarse stage, and process the quadrature signals to reduce the phase error between the quadrature signals. Any number of refinement stages can be utilized. The greater the number of refinement stages, the more the phase error is reduced, but subject to a point of diminishing returns.
Each coarse stage includes a pair of 90/180 delay circuits that delay the differential signal, and generate quadrature output signals that may have some phase error.
Each refinement stage includes a plurality of 0/180 delay circuits that each receive a corresponding quadrature output signal from the coarse stage generator, and have a 0-degree output and a 180-degree output. The 0-degree output of a first 0/180 delay circuit is averaged with a 180 degree output of a second 0/180 delay circuit. Likewise, a 0-degree output of a third 0/180 delay circuit is averaged with a 180 degree output of a fourth 0/180 delay circuit. The averaging of the delay circuit outputs has the effect of reducing the phase error. Furthermore, the refinement stage also includes a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of the 0/180 delay circuits. The 90-degree output of a first 90/180 delay circuit is averaged with a 180 degree output of a second 90/180 delay circuit. Likewise, the 90-degree output of a third 90/180 delay circuit is coupled to a 180 degree output of a fourth 90/180 delay circuit.
Each delay circuit 0/180 includes a first series of inverters and a second series of inverters, where the second series of inverters has an approximate total delay of 180 degrees relative to said first series of inverters. Each delay circuit 90/180 includes a third series of inverters and a fourth series of inverters, where the fourth series of inverters has a delay of 90 degrees relative to the third series of inverters.
An advantage of the quadrature generator described herein is that it is an open loop architecture that is not prone to oscillation because there is no feedback signal to cause an unwanted oscillation. Whereas, the conventional closed-loop architectures utilize at least one feedback signal that can result in unwanted signal oscillation. Furthermore, the delay circuits are implemented using active inverter circuits, which can be implemented in standard semiconductor processes, such as CMOS. CMOS inverters on a common substrate have similar semiconductor characteristics that are repeatable from inverter-to-inverter, which improves the phase accuracy of the quadrature output signals. Furthermore, CMOS inverters are more area efficient than passive capacitors and passive resistors. Therefore, the entire quadrature generator is more area efficient than a conventional phase generator, which increases overall chip-yield.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
FIG. 1 illustrates an example IQ transmitter 100 configured to transmit complex IQ waveforms in a balanced manner using quadrature control signals.
FIG. 2A illustrates an exemplary frequency spectrum for an I harmonically rich signal.
FIG. 2B illustrates an exemplary frequency spectrum for a Q harmonically rich signal.
FIG. 2C illustrates an exemplary frequency spectrum for an IQ harmonically rich signal, where a single IQ harmonic is selected from a number of IQ harmonics.
FIG. 3 illustrates the function of an exemplary generic phase generator.
FIG. 4 illustrates the function of an exemplary quadrature phase generator.
FIG. 5 illustrates a conventional polyphase filter configured using passive resistors and capacitors.
FIG. 6 illustrates a quadrature phase generator according to embodiments of the present invention.
FIG. 7 illustrates a coarse stage according to embodiments of the present invention.
FIG. 8 illustrates a refinement stage according to embodiments of the present invention.
FIG. 9 illustrates 0/180 delay circuit according to embodiments of the present invention.
FIG. 10 illustrates 90/180 delay circuit according to embodiments of the present invention.
FIG. 11 illustrates a flowchart related to the quadrature generator according to embodiments of the present invention.
FIG. 12 illustrates the functional operation of refinement stages according to embodiments of the present invention.
FIGS. 13A-13D illustrate the effect of averaging inverter outputs together according to embodiments of the present invention.
FIG. 14 illustrates an operational flowchart for the refinement stages according to embodiments of the present invention.
FIG. 15 illustrates pulsed signals according to embodiments of the present invention.
FIG. 16 illustrates an example LO generation circuit that generates quadrature pulsed control signals based on a differential input signal.
FIG. 17 illustrates phase error verses FET area for a representative 815 MHz application.
FIG. 18 illustrates a flowchart related to coarse quadrature signal generation according to embodiments of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
1. Example Transmitter Application
Before describing the invention in detail, it is useful to describe an example transmitter environment for the invention. The polyphase filter invention is not limited to the transmitter environment that is described here, as the polyphase filter invention is applicable to other transmitter and non-transmitter applications as will be understood to those skilled in the relevant arts based on the discussions given herein.
FIG. 1 illustrates an IQ transmitter 100 that is useful for transmitting complex IQ waveforms and does so in a balanced manner to control DC offset and carrier insertion. The IQ transmitter 100 includes an IQ balanced modulator 102, an optional filter 104, and an optional amplifier 106. In doing so, the modulator 102 receives an I baseband signal 110 and a Q baseband signal 112 and up-converts these signals to generate a combined harmonically rich signal 103. The harmonically rich signal 103 includes multiple harmonics images, where each image contains the baseband information in the I signal 110 and the Q signal 112. The optional bandpass filter 104 may be included to select a harmonic of interest (or subset of harmonics) from the signal 103 for transmission. The optional amplifier 106 may be included to amplify the selected harmonic prior to transmission, to generate the IQ output signal 107.
As stated above, the balanced IQ modulator 102 up-converts the I baseband signal 110 and the Q baseband signal 112 in a balanced manner to generate the combined harmonically rich signal 103 that carries the I and Q baseband information. To do so, the modulator 102 utilizes two balanced modulators 114a and 114b that have a common output node 138. The balanced modulator 114a receives the I baseband signal 110 and shunts the baseband signal 110 to ground in a differential and balanced fashion to generate a harmonically rich signal 136a. The harmonically rich signal 136a includes multiple harmonic images, where each image contains the baseband information in the baseband signal 110. In other words, each harmonic image includes the necessary amplitude, frequency, and phase information to reconstruct the baseband signal 110. Similarly, the balanced modulator 114b receives the Q baseband signal 112 and shunts the baseband signal 112 to ground in a differential and balanced fashion to generate a harmonically rich signal 136b. The harmonically rich signal 136b includes multiple harmonic images, where each image contains the baseband information in the baseband signal 112. In other words, each harmonic image includes the necessary amplitude, frequency, and phase information to reconstruct the Q baseband signal 112. The harmonically rich signal 136a and the harmonically rich signal 136b are then combined at the node 138 to generate the harmonically rich signal 103.
Each balanced modulator 114 includes the following components: a buffer/inverter 118; optional impedances 120, 122; controlled switches 126 and 130; blocking capacitors 124 and 132; and a terminal 128 that is tied to ground. During operation of the modulator 114a, the buffer/inverter 118a receives the I baseband signal 110 and generates I signal 119 and inverted I signal 121. I signal 119 is substantially similar to the baseband signal 110, and the inverted I signal 121 is an inverted version of signal 110. As such, the buffer/inverter 118 converts the (single-ended) baseband signal 110 into differential signals 119 and 121. The controlled switch 126a shunts the I signal 119a to the terminal 128a according to the control signal 108a, and the controlled switch 130a shunts the inverted I signal 121a to ground according to the control signal 108b. The control signals 108a and 108b are pulse trains that are 180 degrees out-of-phase so that only one of the switches 126a or 130a is closed at any given time. The periodic sampling of the I signal 119 and the inverted I signal 121 generates the I harmonically rich signal 136a. As shown, the terminal 128a is tied to ground and ties together the switches 126a and 128a. This prevents any DC offset voltages from developing between the switches 126a and 130a, which can lead to undesired carrier insertion in the harmonically rich signal 136a. 
In the modulator 114b, the buffer/inverter 118b receives the Q baseband signal 112 and generates Q signal 119b and inverted Q signal 121b. Q signal 119b is substantially similar to the Q baseband signal 112, and the inverted Q signal 121b is an inverted version of signal 110. As such, the buffer/inverter 118b converts the (single-ended) baseband signal 112 into differential signals 119b and 121b. The controlled switch 126b shunts the Q signal 119b to the ground terminal 128b according to the control signal 108c, and the controlled switch 130b shunts the inverted Q signal 121b to ground terminal 128b according to the control signal 108d. The control signals 108c and 108d are pulse trains that are 180 degrees out-of-phase so that only one of the switches 126b or 130b is closed at any given time. Furthermore, the control signals 108c and 108d are phase shifted by 90 relative to the control signals 108a and 108b. The periodic sampling of the Q signal 119b and the inverted Q signal 121b generates the Q harmonically rich signal 136b. The terminal 128b is tied to ground and prevents any DC offset voltages from developing between the switches 126b and 130b, which can lead to undesired carrier insertion in the harmonically rich signal 136b. 
FIG. 2A illustrates an exemplary frequency spectrum for the harmonically rich signal 136a having harmonic images 202a-n. The images 202 repeat at harmonics of the sampling frequency 1/Ts, at infinitum, where each image 202 contains the necessary amplitude, frequency, and phase information to reconstruct the baseband signal 110. Similarly, FIG. 2B illustrates an exemplary frequency spectrum for the harmonically rich signal 136b having harmonic images 204a-n. Each image 204 contains the necessary amplitude, frequency, and phase information to reconstruct the Q baseband signal 112. FIG. 2C illustrates an exemplary frequency spectrum for the IQ harmonically rich signal 103 having images 206a-n. Each image 206 carries the I baseband information and the Q baseband information from the corresponding images 202 and 204, respectively, without substantially increasing the frequency bandwidth occupied by each image 206.
As stated above, the control signals 108a and 108b are phased by 180 degrees relative to each other. Likewise, the control signals 108c and 108d are phase-shifted by 180 degrees relative to each other, and are phase-shifted by 90 degrees relative to the control signals 108a and 108b, respectively. As a result the control signals 108a-d have a relative phase relationship of 0, 180, 90, and 270 degrees, respectively.
2. Quadrature Signal Generation
FIG. 3 illustrates the function of a generalized phase generator 304. Phase generator 304 generates output signals 306a-d based on input signals 302a and 302b. The output signal 306a is arbitrarily chosen as a reference signal and the output signals 306b-306d are phase-shifted relative to signal 306a. In other words, the signal 306b is phase-shifted by φ1 degrees relative to signal 306a, the signal 306c is phase-shifted by φ2 degrees relative to signal 306a, and signal 306d is phase shifted by φ3 degrees relative to signal 306c. The phase shift angles φ are arbitrary in FIG. 3 and can be determined as desired.
FIG. 4 illustrates a quadrature generator 404 that generates signals 406a-d based on input signals 402a-b. Signal 406a is arbitrarily chosen as a reference signal and signals 406b-406d are phase shifted relative to signal 406a by increments of 90 degrees. In other words, signal 406b is phase-shifted by 90 relative to signal 406a. Signal 406c is phase-shifted by 180 degrees relative to signal 406a. Signal 406d is phase-shifted 270 degrees relative to signal 406a. 
The invention is directed to the quasi phase generator 304 of FIG. 3, and the specific quadrature generator 404 of FIG. 4.
3. Conventional Quadrature Generator
FIG. 5 illustrates a conventional quadarature generator 500 that is driven by a source 502. Quadrature generator 500 includes multiple parallel RC circuits 504, where each RC circuit 504 includes a capacitor 506 and a resistor 508. The quadrature generator 500 receives a sinusoidal signal from the source 502, and generates output signals 510a-d that have approximately a 90 degree phase relationship between the signals. In other words, the output signal 510b is phase shifted by 90 degrees relative to signal 510a, signal 510c is phase-shifted by 180 degrees relative to output signal 510a, and signal 510d is phase-shifted by 270 degrees relative to output signal 510a. 
As illustrated, the quadrature generator 500 includes multiple capacitors 506. More specifically, the quadrature generator 500 includes 12 capacitors 506. Capacitors in integrated circuit occupy substrate area that is proportional to the amount of capacitance. Therefore, the 12 capacitors 506 occupy significant substrate area, which increases the size and of an individual IC and reduces overall yield.
4. Quadrature Generator According to the Present Invention
FIG. 6 illustrates a quadrature generator 600 according to embodiments of the present invention. The quadrature generator 600 receives a differential signal 602 (having components 602a and 602b) and generates output signals 608a-d that have the desired 90 degree phase relationship between the output signals 406a-406d, with minimal phase error.
The quadrature generator 600 includes a coarse stage 604, and refinement stages 606a-n. The coarse stage 604 generates signals 605a-d that substantially have the desired quadratrure relationship, but which may not be in exact quadrature with each other. For instance, the signal 605b can be delayed relative to the signal 605a by 90 degrees +/− an error (E1). Likewise, the signal 605c can be delayed relative to the signal 605a by 180 degrees +/− an error (E2). Finally, the signal 605a can be delayed relative to the signal 605c by 270 degrees +/− an error (E3). The mentioned phase errors can result from component and/or process variations, or can result from noise voltage, including thermal noise. The error signals E1, E2, and E3 can be identical or they can be different from each other.
The refinement stages 606a receive the signals 605a-d and refine the quadrature relationship between the signals 605a-d so as to reduce the phase errors E1, E2, and E3. There can be any number of refinement stages 606, and the quadrature accuracy increases with the number of stages 606, up to a point. As a result, the output signals 608a-d have a more accurate quadrature relationship between them. In one embodiment of the invention, the number of refinement stages 606 is chosen so that the quadrature accuracy is equal to or less than 1 degree between the output signals 608. In other words, the signal 608b is delayed relative to signal 608a by 90 degrees +/−1 degree, the signal 608c is delayed relative to the signal 608a by 180 degree +/−1 degree, and the signal 608d is delayed relative to the signal 608a by 270+/−1 degree.
FIG. 11 illustrates a flowchart 1100 that further describes the operation of the quadrature generator 600, according to embodiments of the present invention.
Referring to flowchart 1100, in step 1102 a differential signal is received. For example, a differential signal 602 is received by the quadrature generator 600 having components 602a and 602b that are 180 degrees out-of-phase.
In step 1104, coarse quadrature signals are generated having an approximately 90 degree relationship relative to each and offset by some error. For example, the coarse stage 604 generates signals 605a-d that substantially have the desired quadratrure relationship, but have phase errors that offset the respective signals from perfect quadrature.
In step 1106, the coarse quadrature signals are refined to reduce the phase errors between the quadrature signals. For example, the output signals 605a-d are refined using the refinement stages 606 to reduce the phase error between the quadrature relationship. Step 1104 is repeated until the phase error is reduced below some desired threshold. For example, the refinement stages 606 can be added until the quadrature phase error falls below some threshold, for example +/−1 degree.
An advantage of the architecture for the quadrature generator 600 is that it is an open-loop architecture, which relies on component matching to achieve low phase error between signals. An open loop architecture is not prone to oscillation because there is no feedback signal to cause an unwanted oscillation. Whereas, conventional closed-loop architectures utilize at least one feedback signal that can result in unwanted signal oscillation.
FIG. 7 further illustrates the coarse stage 604 that generates the coarse quadrature signals 605a-d. As stated above, the coarse stage 604 receives differential input signals 602a and 602b that are 0 and 180 degrees out-of-phase, and generates quadrature output signals 605a-d. The coarse stage includes a first 90/180 delay circuit 702a and a second 90/180 delay circuit 702b. The first 90/180 delay circuit 702a receives the 0-degree signal 602a and generates output signals 605b and 605d. The second 90/180 delay circuit 702b receives the 180 degree signal 602b and generates output signals 605b and 605d. The signal 605a is arbitrarily chosen as a reference output signal at 0 degrees. The output signal 605b is phase shifted by 90 degrees relative to the reference signal 605a, plus some error signal E1. The output signal 605c is phase-shifted by 180 degrees relative to the reference signal 605a, plus some error signal E2. Finally, the output signal 605d is phase-shifted by 270 degrees relative to the reference signal 605a, plus some error signal E3.
FIG. 18 illustrates a flowchart 1800 that further describes coarse quadrature signal generation according to embodiments of the present invention. For instance, flowchart 1800 describes the operation of the coarse stage 604 in the generation of the coarse quadrature signals 605a-605d. 
In step 1802, a differential signal is received having a first component and a second component, where the second component is 180 degrees out-of-phase from the first component. The first component can be referred to as the positive component of a differential signal, and the second component can be referred to as the negative component of a differential signal. For example, referring to FIG. 7, the first component can be the 0-degree component 602a and the second component can be the 180-degree component 602b, as shown in FIG. 7.
In step 1804, the first component of the differential input signal is delayed by approximately 90 degrees and also by 180 degrees, to generate a 90 degree output signal and a 180 degree output signal, respectively. The 90 degree output signal is phase-shifted by 90 degrees relative to the first component of the differential input signal, plus some error signal. The 180 degree output signal is phase-shifted by 180 degrees relative to the first component of the differential input signal, plus some error signal. For example, in FIG. 7, the output signal 605b is phase-shifted by approximately 90 degrees relative to the input signal 602a, plus an error signal E1. The output signal 605c is phase-shifted by 180 degrees relative to the input signal 602a, plus an error signal E2.
In step 1806, the second component of the differential input signal is delayed by approximately 90 degrees and 180 degrees, to generate a 270 degree output signal and a 0 degree output signal, respectively. The 270 degree output signal is phase-shifted by approximately 270 degrees relative to the first component of the differential input signal, plus some error signal. The 0 degree output signal is phase shifted by approximately 0 degrees relative to the first component of the differential input signal, plus some error signal. For example, in FIG. 7, the output signal 605d is phase-shifted by approximately 270 degrees relative to the input signal 602a, plus an error signal E3. The output signal 605a is phase-shifted by 0 degrees relative to the input signal 602a. As mentioned above, the output signal 605a is arbitrarily chosen as the reference for the output signals 605a-d, so there is no error signal for the output signal 605a. 
FIG. 8 illustrates a refinement stage 606 that receives input signals 801-1 to 801-4 from a prior stage (e.g. the coarse stage 604 or another refinement stage 606), and generates output signals 805-1 to 805-4. The input signals 801-1 to 801-4 have a quadrature relationship, but have some input phase error EIN. For example, the signal 801-2 is phase-shifted relative to the signal 801-1 by 90 degrees +/− an error (EIN1). The signal 801-3 is phase-shifted relative to the signal 801-1 by 180 degrees +/− an error (EIN2). The signal 801-3 is phase-shifted relative to the signal 801-1 by 270 degrees +/− an error (EIN3). The output signals 805 also have a quadrature relationship, but have some output phase error EOUT. For example, the signal 801-2 is phase-shifted relative to the signal 801-1 by 90 degrees +/− an error (EOUT1). The signal 801-3 is phase-shifted relative to the signal 801-1 to by 180 degrees +/− an error (EOUT2). The output signal 801-4 is phase-shifted relative to the signal 801-1 by 270 degrees +/− an error (EOUT3). Preferably, EOUT for each output signal 805 is less than the EIN for each corresponding signal 801, so that the output of the refinement stage 606 has a more accurate quadrature relationship than the input signals 801. For example, preferably, EOUT1 is less than EIN, EOUT2 is less than EIN2, and EOUT3 is less than EIN3. Thus, as more and more refinement stages 606 are added, the quadrature phase error continues to reduce toward zero degrees.
The refinement stage 606 in FIG. 8 includes four 0/180 delay circuits 802-1 to 802-4, and four 90/180 delay circuits 702-1 to 702-4. The number of delay circuits 802 and 702 are determined by the number of input signals 801a-d, which is four in this case.
Each delay circuit 802 receives a corresponding input signal 801, and has a 0 degree output and a 180 degree output. The 0 degree output of the first delay circuit 802-1 is connected to the 180 degree output of the delay circuit 802-3. The 180 degree output of the delay circuit 801-1 is connected to the 0 degree output of the delay circuit 801-3. Similarly, the 0 degree output of the delay circuit 802-2 is connected to the 180 degree output of the delay circuit 802-4, and the 180 degree output of the delay circuit 802-2 is connected to the 0 degree output of the delay circuit 802-4. Stated another way, each odd numbered delay circuit 802 has its outputs connected together, but 180 degrees out-of-phase with each other. Likewise, each even-numbered delay circuit 801 has its outputs connected together, but is 180-degrees out-of-phase with each other.
The input of 90/180 delay circuits 702 receives the 0-degree output of the corresponding delay circuit 802. For example, the input of the delay circuit 702-1 is connected to the 0-degree output of the delay circuit 802-1, and the input of the delay circuit 702-2 is connected to the 0-degree output of the delay circuit 802-2, and so on.
Still referring to the delay circuits 702, the 180-degree output of the first delay circuit 702-1 is connected to the 90 degree output of the delay circuit 702-2. The 180-degree output of the delay circuit 702-2 is connected to the 90-degree output of the delay circuit 702-3. Similarly, 180-degree output of the delay circuit 702-3 is connected to the 90-degree output of the delay circuit 702-4. Stated another way, the 180-degree output of the nth delay circuit 702 is connected to the 90-degree output of the (n+1)th delay circuit 702. The 180-degree output of the 4th delay circuit 702-4 is connected back to the 90 degree output of the first delay circuit 702-1, as it is the last delay circuit 702 in the set.
FIG. 9 further illustrates the 0/180 degree delay circuit 802 that is utilized in the refinement stages 606, according to an embodiment of the invention. The 0/180 degree delay circuit 802 includes a first signal path 902 and a second signal path 904 that receive an input signal 901. The first signal path 902 includes inverters 906a and 906b. The inverters 906a and 906b receive the input signal 901, invert the signal twice, so that the output signal 909a is in-phase with the input signal 901. In other words, the signal 909a is phase-shifted by 0 degrees with respect to the input signal 901, except for the parasitic delay of the inverters 906a and 906b. Herein, parasitic delay or parasitic phase shift is the unintentional signal delay caused by the physical parameters of a semiconductor device(s) that make-up the inverter 906. For example, larger field effect transistors (FETs) are known to have a larger parasitic delay than smaller devices because they have a larger parasitic reactance, and because they have a longer channel that the signal must travel through.
The second signal path 904 includes a transmission gate 908 and an inverter 906c. The transmission gate 908 is a 0-degree phase-shifter, but is designed to have the same parasitic delay as an inverter 906. Therefore, the input signal 901 is phase shifted by 0 degrees and then is phase-shifted by 180 degrees to produce an output signal 909b that is delayed 180 degrees with respect to the output signal 909a. The transmission gate 908 replicates and copies the parasitic delay of the inverter 906a into the signal path 904. Without the transmission gate 908, the output signal 909b would be skewed-off the desired 180 degree phase shift by the parasitic delay of the inverter 906a. 
FIG. 10 further illustrates the 90/180 degree delay 702 according to an embodiment of the invention, which is used in both the coarse stage 604 and the fine stage 606. The 90/180 degree delay includes a first path 1002 that includes inverters 906a-906d, and a second path 1004 that only includes the inverter 906e. Ignoring any parasitic delay for the moment, the first path 1002 inverts the input signal 1001 four times, so that the output signal 1006a is in-phase with the input signal 1001. Likewise, the second path 1004 includes a single inverter 906e, so that the output signal 1006b is 180 degrees out-of-phase with the input signal 1001. Therefore, absent any parasitic delay, the output signal 1006b would be phase-shifted by 180 degrees relative to the output signal 1006a. However, the desired result is that the output signal 1006b should be delayed by only 90 degrees relative to the output signal 1006a. 
Now considering the parasitic delay of the inverters 906, the first path 1002 has 3 more inverters 906 than the second path 1004. Therefore, the inverters 906 are sized so that the parasitic delay of the 3 inverters 906 is equal to 90 degrees at the frequency of interest. In other words, the parasitic delay of the 3 additional inverters 906 in path 1002 causes an additional 90 degrees worth of phase shift at the frequency of interest, so that the output 1006b only lags the output 1006a by 90 degrees, as is desired.
In one embodiment, the frequency-of-interest for the input signal 1001 is 800 MHz, which has a period of 1250 pS. Therefore, 90 degrees of phase-shift equates to about 1250 pS/4, or 312 pS. Therefore, each of the three inverters 906 should provide approximately 104 pS of delay at 800 MHz, for this example.
The time delay for an inverter 906 can be shown to be equal to

tDELAY=ReqCLOAD

where Req and CLOAD are the equivalent resistance and capacitance for a digital FET. The equivalent resistance of a digital FET can be shown to be:





  
    
      
        
          R
          eq
        
        =
        
          
            
              V
              DD
            
            
              
                
                  K
                  ′
                
                2
              
              ⁢
              
                W
                L
              
              ⁢
              
                
                  (
                  
                    
                      V
                      DD
                    
                    -
                    
                      V
                      TH
                    
                  
                  )
                
                2
              
            
          
          =
          
            
              R
              eq
              ′
            
            ⁢
            
              L
              W
            
          
        
      
    
    
      
        (
        
          1
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          R
          
            o
            ⁢
            
              
            
            ⁢
            n
          
        
        =
        
          L
          
            
              K
              ′
            
            ⁢
            
              W
              ⁡
              
                (
                
                  
                    V
                    gs
                  
                  -
                  
                    V
                    T
                  
                
                )
              
            
          
        
      
    
    
      
        (
        
          1
          ⁢
          b
        
        )
      
    
  




wherein,

L=FET channel length,
W=FET channel width,
R′eq=is a constant dependent on the particular semiconductor process that is utilized.
The equivalent capacitance for a digital FET can be shown to be:




  
    
      
        
          C
          LOAD
        
        =
        
          
            
              C
              IN
            
            +
            
              C
              OUT
            
          
          =
          
            
              
                3
                2
              
              ⁢
              
                
                  C
                  OX
                  ′
                
                ⁡
                
                  (
                  
                    
                      
                        (
                        WL
                        )
                      
                      N
                    
                    +
                    
                      
                        (
                        WL
                        )
                      
                      P
                    
                  
                  )
                
              
            
            +
            
              
                C
                OX
                ′
              
              ⁡
              
                (
                
                  
                    
                      (
                      WL
                      )
                    
                    N
                  
                  +
                  
                    
                      (
                      WL
                      )
                    
                    P
                  
                
                )
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




wherein,

Cox is dependent on the gate oxide thickness of the digital FET.
By substituting the expression for Req and CLoad for the tDELAY equation:




  
    
      
        
          t
          DELAY
        
        =
        
          
            
              R
              eq
            
            ⁢
            
              C
              LOAD
            
          
          =
          
            
              
                
                  
                    
                      R
                      eqP
                      ′
                    
                    ⁡
                    
                      (
                      
                        L
                        W
                      
                      )
                    
                  
                  P
                
                ·
                
                  5
                  2
                
              
              ⁢
              
                
                  
                    C
                    OX
                    ′
                  
                  ⁡
                  
                    (
                    WL
                    )
                  
                
                P
              
              ⁢
              
                (
                
                  1
                  +
                  
                    
                      K
                      P
                      ′
                    
                    
                      K
                      N
                      ′
                    
                  
                
                )
              
            
            =
            
              
                5
                2
              
              ⁢
              
                R
                eqP
                ′
              
              ⁢
              
                
                  C
                  OX
                  ′
                
                ⁡
                
                  (
                  
                    1
                    +
                    
                      
                        K
                        P
                        ′
                      
                      
                        K
                        N
                        ′
                      
                    
                  
                  )
                
              
              ⁢
              
                
              
              ⁢
              
                L
                P
                2
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




Equation 3 can be solved for channel length to achieve a desired delay. Solving for a 104 pS delay results in channel length of L=0.62 um. Additionally, devices with a given length can be used in conjunction with a variable capacitive load to achieve a desired delay for a specific application. This will permit tuning of the filter.
As shown in Equation (3), the device width W is canceled out, and the device delay is largely independent of device width. Since the device delay is largely independent of device width, it is tempting to select minimum width devices to reduce layout area. Minimum width devices also result in lower power consumption due to a lower transconductance and lower current draw during moments of paralleled inverter output averaging. However, the quadrature generator 600 relies on stage-to-stage matching to achieve high phase accuracy. The CMOS process can be characterized for device-to-device variations in threshold voltage, transconductance, and other parameters. In most cases improved parameter matching is achieved by increasing the device area. As a result, the FET channel width is increased to achieve the necessary device-to-device uniformity required to meet the phase imbalance specification. Larger devices require more layout area and also more power, as will be understood by those skilled in the arts. As a result, power consumption and layout area are being traded for phase accuracy.
FIG. 17 illustrates the tradeoff between phase error and FET size and current. Curve 1702 depicts phase error vs. FET size, and illustrates that the phase error decreases as the FET size increases. Curve 1704 depicts drain current vs. FET size and illustrates that drain current increases with FET size. Therefore, in one embodiment, the FET size at 1706 is chosen as a compromise between low phase error and moderate power consumption.
It can be shown that a threshold voltage standard deviation/mean of about 1.8% would produce phase errors of less than 1 degree RMS. While a threshold voltage (VTH0) deviation can be assigned directly to the PSpice model, beta variations were included by allowing gate oxide thickness (tox) to vary. The variation of tox affects several parameters besides the transconductance (including threshold voltage), but provides a likely worst case analysis for phase sensitivity. A standard deviation/mean of 2% was assigned to tOX.
The course quadrature signals are further refined with each correction stage. However, at some point the phase error will be limited by the component matching of the final stage, and additional stages provide little or no improvement in phase error. For example, the quadrature generator in FIG. 6 includes 4 refinement stages. The phase error is rapidly reduced to less than 2 degrees (from an initial 15-20 degrees) by the first two stages 606a and 606b. The third stage 606c drops phase error to about 1.5 degrees, and the fourth stage provides enough improvement to the reduce phase error +/−1 degree, which is desired for one embodiment of the invention.
As discussed herein, the delay circuits 802 and 702 are implemented using active inverter circuits, which can be implemented in standard semiconductor processes, such as CMOS. CMOS inverters on a common substrate have similar semiconductor characteristics that are repeatable from inverter-to-inverter, which improves the phase accuracy of the quadrature output signals. Furthermore, CMOS inverters are more area efficient than passive capacitors and passive resistors. Therefore, the entire quadrature generator 600 is more area efficient than the conventional delay circuit 500, which increases overall chip-yield. Similar concepts can be applied using ECL (emitter coupled logic) for the inverters with improved matching and accuracy.
FIG. 12 further illustrates the operation of refinement stage 606. More specifically, FIG. 12 depicts a functional description of the refinement stage 606. Referring to FIG. 12, an input signal Vs 1208 is sub-divided into an in-phase signal 1206 and a quadrature signal 1212, producing an angle 1222 between the in-phase signal 1206 and the quadrature 1212. Due to the component inaccuracies in the refinement stage 606, the angle 1222 between the in-phase signal 1206 and the quadarature signal 1212 is not exactly 90 degrees, but is 90 degrees +/− some error. The in-phase signal 1206 is further sub-divided into an in-phase signal 1202 and a quadrature signal 1204, producing an angle 1220 between the signals 1202 and 1204. The quadrature signal 1212 is also further sub-divided into in-phase signal 1210 and quadrature signal 1216, producing an angle 1224 between the signals 1210 and 1216. The angles 1220 and 1224 are also not exactly 90, and have substantially the same error as the angle 1222. The error is substantially the same because component inaccuracies are substantially the same in the refinement stage 606, due to the repeated use of inverters 906.
The in-phase signals 1204 and 1210 are substantially in-phase with each other and are added together to produce a combined in-phase signal 1226. Likewise, the signal 1218 is subtracted from the signal 1216 to produce a combined quadrature signal 1228. The combined in-phase signal 1226 is substantially in quadrature with the combined quadrature signal 1228, so that the resulting angle 1230 is substantially 90 degrees, or at least has a final error component that is less than the error associated with the angles 1220 and 1224. The final error component is less because the corresponding inverters 906 in the 0/180 delay circuits are connected together. Therefore, any phase error signal at the output of the 0/180 delay circuits 802 is averaged together and reduced. For example, the 0-degree output of the delay circuit 802-1 is connected together with the 180 degree output of the delay circuit 802-3. Since the delay circuit 802-3 has a 180 degree input 801-3, the 180 degree output of the delay circuit 802-3 should be at 0 degree, and in-phase with the 0-degree output of the 0/180 delay circuit 802-1. Likewise, the 180 degree output of the delay circuit 802-1 is connected to the 0-degree output of the delay circuit 802-3, to average any phase error at these outputs. The outputs of the delay circuits 802-2 and 802-4 are connected together in a similar manner, to average any phase error at their outputs. Likewise, the corresponding outputs of the 90/180 delay circuits 702 are also connected together to average any phase error at their respective outputs.
FIGS. 13A-C further describe the signal averaging performed by the connecting the outputs of the inverters 906 together. FIG. 13A illustrates substantially identical inverters 906a and 906b that are output inverters of either a 0/180 delay circuit 802, or are the output of a 90/180 delay circuit 702. For example, the inverter 906a can be the output inverter 906 of the 0/180 degree delay circuit 802-1, and the inverter 906b can be the output inverter 906 of the 0/180 degree delay circuit 802-3. Inverter 906a has an output 1302a and the inverter 906b has an output 1302b. Referring to FIG. 13C, each output 1302a and 1302b has some phase error, but the output 1302a leads the output 1302b. 
FIG. 13B illustrates the inverters 906a and 906b having their outputs connected together at an output 1304. Referring again to FIG. 13C, the output 1304 is substantially an average of the signals 1302a and 1302b, which reduces the phase error compared with the outputs 1302a and 1302b. 
Still referring to FIG. 13B, the inverters 906a and 906b with corresponding outputs 1302a and 1302b produce the averaged output 1304 when their respective outputs are tied together because of the source impedance and the load impedance of the inverters. Referring to FIG. 13D, each inverter 906a possesses a finite source impedance and it can be viewed that each inverter 906 drives a load impedance. Accordingly,

















VA,B
Δ
voltage at inverter outputs



Z906A
Δ
output impedance of 906A inverter



Z906B
Δ
output impedance of 906B inverter



ZM1
Δ
branch impedance which may be distributed or





lumped and may be related to passive or active





circuitry associated with the load or matching





networks



ZM2

branch impedance which may be distributed or





lumped and may be related to passive or active





circuitry associated with the load or matching





networks



ZL
Δ
load impedance










The effective load from the perspective of inverter 906a is therefore;

ZLOAD-906AΔZM1+ZL//ZM2

Likewise, the effective load from the perspective of inverter 906b is

ZLOAD-906BΔZM2+ZL//ZM1

Now the voltages across ZL and the currents through ZL are proportioned to the outputs of the inverters and the values for Z906A,B and ZLOAD-906A,B. Therefore:





  
    
      
        
          V
          
            O
            ⁢
            
              
            
            ⁢
            
              (
              s
              )
            
          
        
        =
        
          
            
              V
              
                A
                ⁡
                
                  (
                  s
                  )
                
              
            
            ⁢
            
              
                Z
                L
              
              
                
                  Z
                  
                    906
                    ⁢
                    A
                  
                
                +
                
                  Z
                  
                    LOAD
                    -
                    
                      906
                      ⁢
                      A
                    
                  
                
              
            
          
          +
          
            
              V
              
                B
                ⁡
                
                  (
                  s
                  )
                
              
            
            ⁢
            
              
                Z
                L
              
              
                
                  Z
                  
                    906
                    ⁢
                    B
                  
                
                +
                
                  Z
                  
                    LOAD
                    -
                    
                      906
                      ⁢
                      B
                    
                  
                
              
            
          
        
      
    
    
      
        (
        
          3
          ⁢
          a
        
        )
      
    
  




This equation (3a) indicates the transfer function in the frequency domain using Laplace transforms. The transient response my be obtained from the inverse Laplace transform. It is evident that VO can be manipulated by tailoring a number of items such as:

    
    
        a) voltage swing of each inverter which could be accomplished via varying the power supply and a host of other techniques,
        b) changing the inverter source impedances,
        c) changing branch impedances ZM1, ZM2,
        d) altering the load impedance.

In summary, the averaging of the inverters 906 could be weighted equally or in an arbitrary manner. Furthermore, this weighting could be altered in situations to compensate for differing phase alignments. Moreover, N such circuits could be combined in parallel using the super position principles illustrated for the two branch circuit.

    
    


FIG. 14 illustrates a flowchart 1400 that further describes the operation of the refinement stages 606, and the phase error averaging performed by the refinement stages 606.
In step 1402, a first set of quadrature signals are received having some quadrature phase error. For example, referring to FIG. 8, input quadrature signals 801a-801d are received that have some quadrature phase error EIN.
In step 1404, a second set and a third set of quadrature signals are generated based on the first set of quadrature signals using inverters. The second set of quadrature signals are substantially in-phase with the first set of quadrature signals, and the third set of quadrature signals are substantially delayed by 180 degrees relative to the first set of quadrature signals. For example, 0-degree outputs of the 0/180 delay circuits 802 are generated based on the first set of signals 801, and represent the second set of quadrature signals. The 0-degree outputs of the delay circuit 802 are substantially in-phase with the inputs 801, and have a quadrature relationship with each other because the quadrature signals 801 have a quadrature relationship with each other. The 180 degree outputs of the 0/180 delay circuits 802 are based on the first set of quadrature signals, and represent the third set of quadrature signals. The 180 degree outputs of the 0/180 delay circuits 802 are substantially 180 degrees out of phase with the corresponding inputs 801.
In step 1406, the second set of quadrature signals and the third set of quadrature signals are averaged together, to generate a fourth set of quadrature signals that have less phase error than the first set of quadrature signals. More specifically, corresponding signals of the second set of quadrature signals and the third set of quadrature signals are averaged together, to reduce the phase error in the fourth set of quadrature signals. For example, the 0-degree outputs of the 0/180 delay circuits 802 are averaged with the corresponding 180 degree outputs of the delay circuit 802 to generate averaged signals 804. For example, the 0 degree output of the 0/180 delay circuit 802-1 is averaged with the 180 degree output of the delay circuit 802-3, to generate an averaged signal 804-1 that is the input to the 90/180 degree delay circuit 702-1. Likewise, the 0-degree output of the delay circuit 802-2 is averaged with the 180 degree output of the delay circuit 802-4, to generate an averaged signal 804-2. Likewise, the 0-degree output of the delay circuit 802-3 is averaged with the 180 degree output of the delay circuit 802-1, to generate an averaged signal 804-3. Likewise, the 0-degree output of the delay circuit 802-4 is averaged with the 180 degree output of the delay circuit 802-2, to generate an averaged signal 804-4.
In step 1408, a fifth set and a sixth set of quadrature signals is generated based on the fourth set of quadrature signals. The fifth set of quadrature signals is delayed by 90 degrees relative to the fourth set of quadrature signals. The sixth set of quadrature signals is delayed by 180 degrees relative to the fourth set of quadrature signals, and therefore is delayed by 90 degrees relative to the fifth set of quadrature signals. For example, 90-degree outputs of the 90/180 delay circuits 702 represent the fifth set of quadrature signals, and are delayed by 90 degrees relative to the corresponding averaged signals 804-1 to 804-4. The 180 degree outputs of the 90/180 delay circuits 702 are also based on the fourth set of quadrature signals, and are delayed by 180 degrees relative to the corresponding averaged signals 804-1 to 804-4.
In step 1410, the fifth set of quadrature signals and the sixth set of quadrature signals are averaged together, to generate a seventh set of quadrature signals that have less phase error than the fourth set of quadrature signals. More specifically, corresponding signals of the fifth set of quadrature signals and the sixth set of quadrature signals are averaged together, to reduce the phase error in the seventh set of quadrature signals. For example, the 0-degree outputs of the 90/180 delay circuits 702 are averaged with the corresponding 180 degree outputs of the delay circuits 702, to generate averaged output signals 805. For example, the 90 degree output of the 90/180 delay circuit 702-1 is averaged with the 180 degree output of the delay circuit 702-3, to generate the quadrature output signal 805-1. Likewise, the 90-degree output of the delay circuit 702-2 is averaged with the 180 degree output of the delay circuit 702-1, to generate the quadrature output signal 805-2. Likewise, the 90-degree output of the delay circuit 702-3 is averaged with the 180 degree output of the delay circuit 702-4, to generate the quadrature output signal 804-3. Likewise, the 90-degree output of the delay circuit 702-4 is averaged with the 180 degree output of the delay circuit 702-3, to generate the quadrature output signal 805-4.
The phase error of the quadrature output signals 805 is less than the phase error of the quadrature input signals 801, due to the averaging performed by steps 1406 and 1408. In embodiments, phase error is less than 1 degree at the frequency of interest.
5. Mathematical Description
A system level mathematical description of the operation of the refinement stage 606 is given as follows. In order to facilitate the equation manipulation in the following description, the delay circuits 802-1 to 802-4 in FIG. 8 will be referred to as delay circuits A-1 to A-n, respectively. Likewise, the delay circuits 702-1 to 702-4 in FIG. 8 will be referred to as delay circuits B-1 to B-n. This is in accordance with the “A” placed over the row of delay circuit 802, and the “B” placed over the row of delay circuits 702 in FIG. 8. Furthermore, the input signals 801-1 to 801-4 will be referred to as in0, in90, in180, and in 270, respectively. Furthermore, the output signals 805-1 through 805-4 will be referred to as out0, out90, out180, and out270.
The four input and output waveforms of the refinement stage 606 can be approximately modeled as square waves although this is not strictly required. A Fourier decomposition can also be used to compare spectral components and their relative phases. The phase accuracy of the refinement stage 606 is measured by the relative time delay between rising or falling edges of each of the four output waveforms 805. Timing uncertainties result from input phase error and variability of propagation delay through each of the delay circuit 802 and 702 of the refinement stages 606. A mathematical model is constructed and described below that preserves the individual timing errors and demonstrates the self-regulating nature of the refinement stage 606.
A unit rectangular pulse is defined as:




  
    
      
        
          
            ∏
            
              
            
          
          ⁢
          
            (
            t
            )
          
        
        =
        
          {
          
            1
            ,
            
              
                
                  
                  t
                  
                
                <
                
                  1
                  2
                
              
              ;
              
                0
                ⁢
                
                  
                
                ⁢
                otherwise
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Each of the input waveforms can be described by periodic rectangular pulse functions of fixed amplitude, A, and distinct timing with a periodicity of T, a pulse width of T/2, and first rising edge occurring at time t0, as shown in FIG. 15. The equations for the input waveforms 801 based on this unit pulse description are as follows:




  
    
      
        
          i
          ⁢
          
            
          
          ⁢
          n
          ⁢
          
            
          
          ⁢
          0
        
        =
        
          
            ∑
            
              n
              =
              0
            
            ∞
          
          ⁢
          
            
          
          ⁢
          
            A
            ⁢
            
              
                ∏
                
                  
                
              
              ⁢
              
                (
                
                  
                    2
                    ⁢
                    
                      (
                      
                        t
                        -
                        nT
                        -
                        
                          t
                          0
                        
                      
                      )
                    
                  
                  T
                
                )
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  
  
    
      
        
          i
          ⁢
          
            
          
          ⁢
          n
          ⁢
          
            
          
          ⁢
          90
        
        =
        
          
            ∑
            
              n
              =
              0
            
            ∞
          
          ⁢
          
            
          
          ⁢
          
            A
            ⁢
            
              
                ∏
                
                  
                
              
              ⁢
              
                (
                
                  
                    2
                    ⁢
                    
                      (
                      
                        t
                        -
                        nT
                        -
                        
                          t
                          90
                        
                      
                      )
                    
                  
                  T
                
                )
              
            
          
        
      
    
    
      
        (
        6
        )
      
    
  
  
    
      
        
          i
          ⁢
          
            
          
          ⁢
          n
          ⁢
          
            
          
          ⁢
          180
        
        =
        
          
            ∑
            
              n
              =
              0
            
            ∞
          
          ⁢
          
            
          
          ⁢
          
            A
            ⁢
            
              
                ∏
                
                  
                
              
              ⁢
              
                (
                
                  
                    2
                    ⁢
                    
                      (
                      
                        t
                        -
                        nT
                        -
                        
                          t
                          180
                        
                      
                      )
                    
                  
                  T
                
                )
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  
  
    
      
        
          i
          ⁢
          
            
          
          ⁢
          n
          ⁢
          
            
          
          ⁢
          270
        
        =
        
          
            ∑
            
              n
              =
              0
            
            ∞
          
          ⁢
          
            
          
          ⁢
          
            A
            ⁢
            
              
                ∏
                
                  
                
              
              ⁢
              
                (
                
                  
                    2
                    ⁢
                    
                      (
                      
                        t
                        -
                        nT
                        -
                        
                          t
                          270
                        
                      
                      )
                    
                  
                  T
                
                )
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




wherein,

in0 represents the 0 degree waveform 801-1,
in90 represents the 90 degree waveform 801-2,
in180 represents the 180 degree waveform 801-3, and
in270 represents the 270 degree waveform 801-4.
The primary function of each of the individual delay circuits A1-AN and B1-BN in FIG. 8 is to provide an approximate delay to each signal and combine the two hard-wired outputs, creating timing characteristics which are an average of the individual waveforms, where the averaging effect is shown in FIG. 13B. For example, the input to the delay circuit B-1 comes from two hardwired outputs with inputs of in0 and in180 from the delay circuits A-1 and A-3, respectively. Assuming that in0 is defined as the zero degree reference, the timing of inB1 will be determined by the following:

    
    
        in-to-out0 propagation delay of the delay circuit A-1 (where the delay is referenced as DA1:0 in the equations below)
        Timing uncertainties associated with in180 (where the timing is represented in t180 in the equations below)
        in-to-out180 propagation delay of delay circuit A3 (where the delay is referenced as DA3:180 in the equations below)
    
    


The input signals and delays are viewed as random variables whose probability density functions (PDF) are uniformily distributed (in a worst case) over some range about their expected values or means. In some applications, the PDFs may be much more complex but the uniform assumption contemplates a worst case scenario of practical concern. Since components of the delays and waveforms are random variables, we may employ ideas from probability and statistics to address the method by which averaged phase values are obtained at the circuit output. For arbitrary PDFs associated with sums of random variables, the central limit theorm may be invoked to facilitate an understanding of how final averages or expected values of phases can be extracted.
Understanding the periodic nature of the rectangular pulse function where a delay of integer periods (T) produces like timing and amplitudes, and dropping the amplitude (A), the out0 rising edge of the delay circuit A-3 in FIG. 8 can be described in a modified notation as:

A1out0=ΠRE(in0+DA1:0)  (9)

This represents a unity amplitude pulse whose rising edge occurs at a time determined by the input timing (i0) and the effective delay through delay circuit A1(DA1:0), which in turn is related to the driving point and load impedances as well as the branch impedances of the circuit. Likewise, the other component of inB1 is derived from in180:

A3out180=ΠRE(in180+DA3:180)  (10)

The hard-wired combination of these two signals is a unity amplitude pulse whose rising edge occurs at the average time of the two components. Also, since this is actually a periodic pulse with period T, the subtraction or addition of integer periods will not alter the edge timing, but assists in the analysis using the modified pulse notation. One period is subtracted from any single delay path which produces an approximate delay of 1 period (360 degrees) or more. The following expressions are therefore equivalent:

A3out180=ΠRE(in180+DA3:180)=ΠRE(in180+DA3:180−T)  (11)

The input to the delay circuit B1 can now be described as averaging A1out0 with A3out 180:





  
    
      
        
          inB
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            ∏
            RE
          
          ⁢
          
            
              (
              
                
                  (
                  
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      n
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                    +
                    
                      DA1
                      :
                      0
                    
                  
                  )
                
                +
                
                  (
                  
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      n
                      ⁢
                      
                        
                      
                      ⁢
                      180
                    
                    +
                    
                      DA3
                      :
                      
                        180
                        -
                        T
                      
                    
                  
                  )
                
              
              )
            
            2
          
        
      
    
    
      
        (
        12
        )
      
    
  




This is a unit amplitude pulse whose rising edge occurs at a time:





  
    
      
        t
        =
        
          
            (
            
              
                (
                
                  
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      n
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                    +
                    
                      DA
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  :
                  0
                
                )
              
              +
              
                (
                
                  
                    
                      i
                      ⁢
                      
                        
                      
                      ⁢
                      n
                      ⁢
                      
                        
                      
                      ⁢
                      180
                    
                    +
                    
                      DA
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  :
                  
                    180
                    -
                    T
                  
                
                )
              
            
            )
          
          2
        
      
    
    
      
        (
        13
        )
      
    
  




where:
in0, in180=edge timing of the inputs in0 and in180
DA1:0, DA3:180=propagation delay through the blocks A1 and A3
T=period of the input waveforms
The timing associated with in180 would ideally be shifted by 180 degrees (T/2) from in0. If in0 were defined as zero for an 800 MHz system:




  
    
      
        
          i
          ⁢
          
            
          
          ⁢
          n
          ⁢
          
            
          
          ⁢
          180
        
        =
        
          
            
              i
              ⁢
              
                
              
              ⁢
              n
              ⁢
              
                
              
              ⁢
              0
            
            +
            
              T
              2
            
          
          =
          
            
              0
              +
              
                
                  1.25
                  ⁢
                  
                    
                  
                  ⁢
                  n
                  ⁢
                  
                    
                  
                  ⁢
                  S
                
                2
              
            
            =
            
              625
              ⁢
              pS
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




The actual timing of in180 will vary due to timing inaccuracies, noise, and temperature/process variations. Referring to FIG. 8, the inputs to each of the delay circuits in column B can be defined:




  
    
      
        
          inB
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            ∏
            RE
          
          ⁢
          
            
              (
              
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        0
                      
                      +
                      
                        DA
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    :
                    0
                  
                  )
                
                +
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        1
                        ⁢
                        
                          
                        
                        ⁢
                        80
                      
                      +
                      
                        D
                        ⁢
                        
                          
                        
                        ⁢
                        A
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    :
                    
                      180
                      -
                      T
                    
                  
                  )
                
              
              )
            
            2
          
        
      
    
    
      
        (
        15
        )
      
    
  
  
    
      
        
          inB
          ⁢
          
            
          
          ⁢
          2
        
        =
        
          
            ∏
            RE
          
          ⁢
          
            
              (
              
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        90
                      
                      +
                      
                        DA
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    :
                    0
                  
                  )
                
                +
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n2
                        ⁢
                        
                          
                        
                        ⁢
                        70
                      
                      +
                      
                        D
                        ⁢
                        
                          
                        
                        ⁢
                        A
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                    
                    :
                    
                      180
                      -
                      T
                    
                  
                  )
                
              
              )
            
            2
          
        
      
    
    
      
        (
        16
        )
      
    
  
  
    
      
        
          inB
          ⁢
          
            
          
          ⁢
          3
        
        =
        
          
            ∏
            RE
          
          ⁢
          
            
              (
              
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        18
                        ⁢
                        
                          
                        
                        ⁢
                        0
                      
                      +
                      
                        DA
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    :
                    0
                  
                  )
                
                +
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        0
                      
                      +
                      
                        DA
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    :
                    180
                  
                  )
                
              
              )
            
            2
          
        
      
    
    
      
        (
        17
        )
      
    
  
  
    
      
        
          inB
          ⁢
          
            
          
          ⁢
          4
        
        =
        
          
            ∏
            RE
          
          ⁢
          
            
              (
              
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        270
                      
                      +
                      
                        DA
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                    
                    :
                    0
                  
                  )
                
                +
                
                  (
                  
                    
                      
                        i
                        ⁢
                        
                          
                        
                        ⁢
                        n
                        ⁢
                        
                          
                        
                        ⁢
                        90
                      
                      +
                      
                        DA
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    :
                    180
                  
                  )
                
              
              )
            
            2
          
        
      
    
    
      
        (
        18
        )
      
    
  




Hard-wiring the appropriate outputs of the blocks in column B and time averaging the edge transitions produces the final outputs of the refinement stage, out0, out90, out180, and out270:




  
    
      
        out90
        =
        
          
            
              
                ∏
                RE
              
              ⁢
              
                {
                
                  
                    
                      (
                      
                        
                          (
                          
                            i0
                            +
                            
                              DA1
                              :
                              0
                            
                          
                          )
                        
                        +
                        
                          (
                          
                            i180
                            +
                            
                              DA3
                              :
                              
                                180
                                -
                                T
                              
                            
                          
                          )
                        
                      
                      )
                    
                    2
                  
                  +
                  
                    DB1
                    :
                    
                      90
                      +
                      
                        
                          (
                          
                            
                              (
                              
                                i270
                                +
                                
                                  DA4
                                  :
                                  0
                                
                              
                              )
                            
                            +
                            
                              (
                              
                                i90
                                +
                                
                                  DA2
                                  :
                                  
                                    180
                                    -
                                    T
                                  
                                
                              
                              )
                            
                          
                          )
                        
                        2
                      
                      +
                      
                        DB4
                        :
                        
                          180
                          -
                          T
                        
                      
                    
                  
                
                }
              
            
            ⁢
            
              
            
          
          2
        
      
    
  
  
    
      
        out180
        =
        
          
            
              
                ∏
                RE
              
              ⁢
              
                {
                
                  
                    
                      (
                      
                        
                          (
                          
                            i90
                            +
                            
                              DA2
                              :
                              0
                            
                          
                          )
                        
                        +
                        
                          (
                          
                            i270
                            +
                            
                              DA4
                              :
                              
                                180
                                -
                                T
                              
                            
                          
                          )
                        
                      
                      )
                    
                    2
                  
                  +
                  
                    
                      (
                      
                        
                          (
                          
                            i90
                            +
                            
                              DA2
                              :
                              0
                            
                          
                          )
                        
                        +
                        
                          (
                          
                            i270
                            +
                            
                              DA4
                              :
                              
                                180
                                -
                                T
                              
                            
                          
                          )
                        
                      
                      )
                    
                    2
                  
                
                }
              
            
            ⁢
            
              
            
          
          2
        
      
    
  




In one embodiment, the out90 and out180 are random variables also since their components can be viewed as random variables. A significant number of processing stages will result in the observable possessing a Gaussian-like random variable which implies that the expected value is easily extracted by averaging, which also reduces the variance of the final estimate.

Ideally, the time difference between rising edges of these two signals should be one fourth the period or 90 degrees. Subtracting the time difference between the 180 and 90 degree output results in:




  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          t
        
        =
        
          
            
              
                
                  (
                  
                    
                      (
                      
                        i0
                        +
                        
                          DA1
                          :
                          0
                        
                      
                      )
                    
                    +
                    
                      (
                      
                        i180
                        +
                        
                          DA3
                          :
                          
                            180
                            -
                            T
                          
                        
                      
                      )
                    
                  
                
                2
              
              +
              
                DB1
                :
                
                  90
                  +
                  
                    
                      (
                      
                        
                          (
                          
                            i270
                            +
                            
                              DA4
                              :
                              0
                            
                          
                          )
                        
                        +
                        
                          (
                          
                            i90
                            +
                            
                              DA2
                              :
                              180
                            
                          
                          )
                        
                      
                      )
                    
                    2
                  
                  +
                  
                    DB4
                    :
                    
                      180
                      -
                      T
                    
                  
                
              
            
            2
          
          -
        
      
    
  
  
    
      
        
          
            
              (
              
                
                  (
                  
                    i90
                    +
                    
                      DA2
                      :
                      0
                    
                  
                  )
                
                +
                
                  (
                  
                    i270
                    +
                    
                      DA4
                      :
                      
                        180
                        -
                        T
                      
                    
                  
                  )
                
              
              )
            
            2
          
          +
          
            
              (
              
                
                  (
                  
                    i90
                    +
                    
                      DA2
                      :
                      0
                    
                  
                  )
                
                +
                
                  (
                  
                    i270
                    +
                    
                      DB4
                      :
                      
                        180
                        -
                        T
                      
                    
                  
                  )
                
              
              )
            
            2
          
        
        2
      
    
  




Assuming the delay circuits in column and column B are well matched (DA1:0=DA2:0=DA3:0=DA4:0 and DB1:0=DB2:0=DB3:0=DB4:0) and simplifying:





  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          t
        
        =
        
          -
          
            
              T
              4
            
            .
          
        
      
    
    
      
        (
        22
        )
      
    
  




Equation 22 indicates the relative phase between output signals 805 is substantially close to 90 degrees. The statistical mean of the result is a weak function of the initial phase error at the inputs 801. Furthermore, the result is also a statistical mean of individual delays through the delay circuits 802 and 702 in FIG. 8. Whereas, conventional quadrature generators need to have identical delay circuits in order to produce perfect phase. From the equations above, it is seen that the timing imperfections (all inputs and delay blocks) that form the outputs are summed and averaged and applied equally to each output. Although the absolute delay from the input to the output of the refinement stage will still vary with temperature, process, etc., the difference in delays between adjacent outputs is forced to T/4 by the circuit architecture.
Furthermore, the refinement stage 606 has a wide bandwidth since any of the individual delays (802 or 702) are not significant unless it affects the systems ability to perform waveform averaging. The ability to accurately perform averaging breaks down if the delay circuits are not in the neighborhood of the ideal delay. In one embodiment, for example, the bandwidth of a 4 stage 800 MHz quadrature generator was found to be over 500 MHz. Additional refinement stages can provide additional bandwidth.
FIG. 16 illustrates an example LO generation circuit 1600, capable of generating quadrature pulsed control signals 1614, based a differential input signal 1601. A differential amplifier 1602 receives the input signal 1601 and amplifies the input signal 1601, to generate an amplified signal 1603. The differential amplifier 1602 is included because the differential input signal 1601 can have a variable amplitude, and it is desirable to have a constant amplitude signal 1603 during quadrature signal generation. A divide-by-two circuit 1604 frequency divides the differential amplified signal 1603 by two, to generate a frequency divided signal 1605. For example, in one embodiment, the differential input signal has a frequency of 1.6 GHz, and the divide by two circuit divides the frequency down to 800 MHz. A level-shift circuit 1606 DC level shifts the signal 1605 to generate a level-shifted output signal 1607 that is appropriate for the quadrature generator 600. The quadrature generator 600 generates quadrature signals 1609 based on the level-shifted signal 1607. The pulse generator 1610 receives the signals 1609, and generates output pulses 1614 that have a quadrature relationship and have a desired pulse width. The differential amplifier 1602 and the divide-by-two circuit 1604 are biased using the bias regulator 1612.
The output pulses 1614 can be used as the control signals 108a-d that control the switches 126 in the balanced modulator 100 of FIG. 1. The pulse width of the output pulses 1614 can be set to provide a desired sampling period for the switches 126 in the balanced modulator 100 to improve energy transfer to a desired harmonic in the harmonically rich signal 103.
6. Performance
Operating on 800 MHz signals, the quadrature signal generator in FIG. 6 has shown to produce quadrature signals with less than +/−1 degree of phase error. Furthermore, the quadrature generator 600 is also resistant to input phase error. Experiments have shown that the phase error can vary from +/−12 degrees, and the output phase error only varies from +/−150 milli-degree. Still further, the quadrature generator 600 is also resistant to input frequency error. Experiments have shown that the input frequency can vary can vary 1.2 GHz to 2.2 GHz, and the output phase error varies minimally.
7. Conclusion
Example embodiments of the methods, systems, and components of the present invention have been described herein. As noted elsewhere, these example embodiments have been described for illustrative purposes only, and are not limiting. Other embodiments are possible and are covered by the invention. Such other embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

## Claims

1. A quadrature signal generator, comprising:
a coarse stage for generating output signals that have substantially a quadrature phase relationship, said coarse stage having at least one 90/180 delay circuit having a first set of inverters and a second set of inverters, said second set of inverters having an approximate delay of 90 degrees relative to said first set of inverters; and
at least one refinement stage for refining said quadrature phase relationship of said output signals from said coarse stage, said refinement stage having at least one 0/180 delay circuit, said 0/180 delay circuit having a third series of inverters and a fourth series of inverters, said fourth series of inverters having an approximate delay of 180 degrees relative to said third series of inverters.

2. The quadrature signal generator of claim 1, wherein said at least one refinement stage comprises four refinement stages, each of said four refinement stages further refining said 90 degree phase relationship between said output signals.

3. The quadrature signal generator of claim 1, wherein said at least one refinement stage includes a second 90/180 delay circuit.

4. The quadrature signal generator of claim 1, wherein at least one of said first, second, third, and fourth series of inverters are CMOS inverters.

5. A quadrature signal generator, comprising:
a coarse stage capable of generating quadrature output signals that have substantially a 90-degree phase relationship based on a differential input signal; and
at least one refinement stage for refining said 90 degree phase relationship of said output signals from said coarse stage, said refinement stage having,
a plurality of 0/180 delay circuits each receiving a corresponding quadrature output signal and having a 0-degree output and a 180-degree output, wherein a 0-degree output of a first 0/180 delay circuit is coupled to a 180 degree output of a second 0/180 delay circuit, and
a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of said plurality of 0/180 delay circuits, wherein a 90-degree output of a first 90/180 delay circuit is coupled to a 180 degree output of a second 90/180 delay circuit.

6. The quadrature signal generator of claim 5, wherein said first 0/180 delay circuit and said second 0/180 delay circuit are separated by a third 0/180 delay circuit.

7. The quadrature signal generator of claim 5, wherein said first 0/180 delay circuit is a mth delay circuit in said plurality of 0/180 delay circuits, and wherein said second 0/180 delay circuit is a (m+2)th delay circuit in said plurality of 0/180 delay circuits.

8. The quadrature signal generator of claim 5, wherein said first 90/180 delay circuit is adjacent to said second 90/180 delay circuit.

9. The quadrature signal generator of claim 5, wherein said first 90/180 delay circuit is a mth delay circuit in said plurality of 90/180 delay circuits, and wherein said second 90/180 delay circuit is a (m+1)th delay circuit in said plurality of 90/180 delay circuits.

10. The quadrature signal generator of claim 5, wherein each 0/180 delay circuit includes:
a first set of inverters, that have an input that receives said corresponding quadrature output signal and an output connected to said 0 degree output of said 0/180 delay circuit; and
a second set of inverters, that have an input that receives said corresponding quadrature output signal and an output connected to said 180 degree output of said 0/180 delay circuit;
wherein second set of inverters have an approximate delay of 180 degrees relative said first set of inverters.

11. The quadrature signal generator of claim 5, wherein said 0-degree output of said first 0/180 delay circuit is averaged with said 180 degree output of said second 0/180 delay circuit.

12. The quadrature signal generator of claim 5, wherein said 180-degree output of said first 0/180 delay circuit is averaged with said 0 degree output of said second 0/180 delay circuit.

13. The quadrature signal generator of claim 5, wherein said 90-degree output of a first 90/180 delay circuit is averaged with said 180 degree output of a second 90/180 delay circuit.

14. A quadrature signal generator, comprising:
a coarse stage capable generating quadrature output signals that have substantially a 90 degree phase relationship; and
at least one refinement stage for refining said 90 degree phase relationship of said output signals, said at least one refinement stage including,
a first 0/180 delay circuit having an input that receives a first output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,
a second 0/180 delay circuit having an input that receives a second output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,
a third 0/180 delay circuit having an input that receives a third output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,
a fourth 0/180 delay circuit having an input that receives a fourth output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,
a first 90/180 delay circuit having an input coupled to said 0 degree output of said first 0/180 delay circuit, and having a 90 degree output and a 180 degree output,
a second 90/180 delay circuit having an input coupled to said 0 degree output of said second 0/180 delay circuit, and having a 90 degree output and a 180 degree output,
a third 90/180 delay circuit having an input coupled to said 0 degree output of said third 0/180 delay circuit, and having a 90 degree output and a 180 degree output,
a fourth 90/180 delay circuit having an input coupled to said 0 degree output of said fourth 0/180 delay circuit, and having a 90 degree output and a 180 degree output,
wherein said 0 degree output of said first 0/180 delay circuit is coupled to said 180 degree output of said third 0/180 delay circuit,
wherein said 180 degree output of said first 0/180 delay circuit is coupled to a 0 degree output of said third 0/180 delay circuit,
wherein said 0 degree output of said second 0/180 delay circuit is coupled to said 180 output of said fourth 0/180 delay circuit,
wherein a 180 degree output of said second 0/180 delay circuit is coupled to a 0 degree output of said fourth 0/180 delay circuit,
wherein said 90 degree output of said first 90/180 delay circuit is coupled to said 180 degree output of said fourth 0/180 delay circuit,
wherein said 180 degree output of said first 90/180 delay circuit is coupled to said 90 degree output of said second 90/180 delay circuit,
wherein a 180 degree output of said second 90/180 delay circuit is coupled to said 90 degree output of said third 0/180 delay circuit, and
wherein a 180 degree output of said third 90/180 delay circuit is coupled to said 90 degree output of said fourth 0/180 delay circuit.

15. A quadrature signal generator, comprising:
a coarse stage capable of generating quadrature output signals that have substantially a 90-degree phase relationship based on a differential input signal; and
at least one refinement stage for refining said quadrature phase relationship of said output signals from said coarse stage, said refinement stage having,
a plurality of 0/180 delay circuits each receiving a corresponding quadrature output signal and having a 0-degree output and a 180-degree output, wherein a 0-degree output of a first 0/180 delay circuit is averaged with a 180 degree output of a second 0/180 delay circuit, said first 0/180 delay circuit and said second 0/180 delay circuit separated by a third 0/180 delay circuit,
a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of said plurality of 0/180 delay circuits, wherein a 90-degree output of a first 90/180 delay circuit is averaged with a 180 degree output of a second 90/180 delay circuit, said first 90/180 delay circuit adjacent to said second 90/180 delay circuit.

16. A method of quadrature signal generation, comprising:
receiving a differential input signal;
delaying first and second components of said differential input signal to produce a first set of quadrature signals; and
refining said first set of quadrature signals to reduce phase errors, including
generating second and third sets of quadrature signals based on said first set of quadrature signals, said second set of quadrature signals substantially in-phase with said first set of quadrature signals, said third set of quadrature signals substantially delayed by 180 degrees relative to said first set of quadrature signals,
averaging said second set of quadrature signals with corresponding signals in said third set of quadrature signals, so as to produce a fourth set of quadrature signals,
generating fifth and six sets of quadrature signals based on said fourth set of quadrature signals, said fifth set of quadrature signals delayed by approximately 90 degrees relative to said fourth set of quadrature signals, and said six set of quadrature signals delayed by approximately 180 degrees relative to said first set of quadrature signals,
averaging said fifth set of quadrature signals with corresponding signals in said six set of quadrature signals, so as to produce a seventh set of quadrature signals, whereby said seventh set of quadrature signals has less phase error than said first set of quadrature signals.

17. The method of claim 16, further comprising the step of converting said seventh set of quadrature signals to a set of pulse signals having a quadrature relationship.

18. The method of claim 16, further comprising the step of dividing the frequency of said differential signal by a factor of 2.

19. The method of claim 18, further comprising the step of level shifting said differential signal so as adjust a DC level of said differential signal.

20. The method of claim 16, wherein said step of generating said second and third sets of quadrature signals includes the steps of:
delaying said first set of quadrature signals by approximately 0 degrees to produce said second set of quadrature signals; and
delaying said second set of quadrature signals by approximately 180 degrees to produce said third set of quadrature signals.

21. The method of claim 16, wherein said step of generating said fifth and six sets of quadrature signals includes the steps of:
delaying said fourth set of quadrature signals by approximately 90 degrees to produce said fifth set of quadrature signals; and
delaying said fourth set of quadrature signals by approximately 180 degrees to produce said sixth set of quadrature signals.

22. A quadrature signal generator, comprising:
a differential input having a first and second terminals;
a coarse stage including a first 90/180 delay circuit coupled to said first terminal of said differential input, and a second 90/180 degree delay circuit coupled to said second terminal of said differential input; and
a refinement stage coupled to an output of said coarse stage including,
a plurality of 0/180 delay circuits having inputs coupled to corresponding outputs of said first and second 90/180 delay circuits, each 0/180 delay circuit having a 0 degree output and a 180 degree output, said 0 degree output of each delay circuit connected with said 180 degree output of another 0/180 delay circuit that is substantially in-phase with said 0 degree output, and
a plurality of 90/180 delay circuits having inputs coupled to corresponding outputs of said 0/180 delay circuits, each 90/180 degree delay circuit having a 90 degree output and a 180 degree output, said 90 degree output of each delay circuit connected with said 180 degree output of another 0/180 delay circuit that is substantially in-phase with said 90 degree output.