# Patent

## Title
Phase and amplitude modulator

## Abstract

The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupled to said input signal and having a control input for delay adjustment, a first amplitude control device in series with the first variable delay device, providing at its output an amplitude controlled signal and having a control input for adjusting the output amplitude, a phase detector with linear characteristic having its two inputs connected to the output of the fixed-delay device and the output of the first amplitude control device, an error measurement device having its negative input connected to the output of the phase detector and its positive input connected to a control signal, an amplifier with low-pass characteristic having its input connected to the output of the error measurement device and its output to the control input of the first variable delay device.

## Background
The invention relates to a phase and amplitude modulator. It is especially suited for implementation in electronic integrated circuits and allows precise adjustment of phase and amplitude independent of process, voltage, and temperature variances. Depending on the embodiment amplitude and phase can be controlled by analog or digital signals. Also depending on the embodiment the phase and amplitude modulator can be used as a precise variable delay.
In many technical areas devices for phase and amplitude modulation as well as for precise variable signal delay are needed. Applications for phase and amplitude modulators are modulators for wireless or wireline communication systems or radar. Applications for precise variable delays are delay circuits for the synchronisation of receive signals in communications systems, generation of signals with precise mutual signal delay, such as quadrature signals, and the stabilization of signal delays against process, voltage, and temperature variances.
In wireless communication systems amplitude- and phase-modulation techniques are used for transmission of lower frequency signals over high-frequency bands. Among the multitude of modulation schemes combined phase- and amplitude modulation schemes are particularly interesting because they allow to transmit data with a high bit-to-bandwidth density.
A typical modulation technique is the QAM (QAM, quadrature amplitude modulation) technique which is shown in FIG. 1. It uses mixers and complex baseband signals in conjunction with in-phase and quadrature local oscillator signals in order to generate a modulated signal in an intermediate or transmit frequency band. The QAM technique can be used for phase, amplitude and combined phase-amplitude modulation. Drawbacks of this technique are that precise phase relationship between in-phase and quadrature signal and accurate analog components for good side-band suppression and precise modulation, as well as complex digital or analog circuitry for the generation of the complex baseband signal are needed.
FIG. 2 shows another modulation technique where the modulated signal is generated by direct modulation of the local osillator frequency tuning input. This technique is applicable to FM (FM, frequency modulation) and PM (PM, phase modulation). Since the local oscillator frequency is usually controlled by a Synthesizer-PLL (PLL, Phase-Locked Loop), low-frequency modulation of the control voltage of the VCO (VCO, Voltage-Controlled Oscillator) is totally or in part cancelled by the PLL causing the phase modulation to be inaccurate. This can be circumvented by making the PLL loop bandwidth much smaller than the lower corner frequency of the modulation signal spectrum. A drawback is that modulation takes place inside the PLL loop which restricts PLL parameter range. In addition modulation at the sensitive control input of the local oscillator can deteriorate phase noise performance of the local oscillator. Another drawback is that no amplitude modulation is feasible and that some sort of calibration is needed because the VCO tuning characteristic depends on PVT (PVT, Process, Voltage, Temperature) variances.
In principle it is also possible to modulate amplitude of the local oscillator signal in the modulation scheme according to FIG. 2 outside of the PLL by means of an amplitude control device. FIG. 3 shows a potential realization of an amplitude control device for electronic integrated circuits by means of a differential amplifier with adjustable bias current. The signal for bias current adjustment can be analog nature or, if an analog-to-digital-converter with a current output is used, of digital nature. A major drawback of such an amplitude control device is that phase shift of the output signal depends on bias current, i.e. on the amplitude of the output signal. This leads to inaccurate phase modulation.
In conclusion it can be stated that phase- and amplitude modulators using QAM technique suffer from high circuit complexity and require accurate local oscillator in-phase and quadrature signals. If direct modulation of the local oscillator is used, PLL parameter range is limited and potentially noise performance of the local oscillator is deteriorated. In addition for accurate modulation calibration is required due to PVT variances of the local oscillator tuning characteristic. Modulating the amplitude by means of an amplitude control device also adds to phase inaccuracy.
Therefore it is an object of the present invention to provide a phase- and amplitude modulator with reduced complexity and precise phase- and amplitude control independent from PVT variances. In addition a modulation technique that avoids direct modulation at the local oscillator control input inside the Synthesizer-PLL is also required and calibration should be avoided.
The above object is achieved by an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising:
a first fixed-delay device having its input coupled to an input signal,
a first variable delay device having its input coupled to said input signal and having a control input for delay adjustment,
a first amplitude control device in series with the first variable delay device, providing at its output an amplitude controlled signal and having a control input for adjusting the output amplitude,
a phase detector with linear characteristic having its two inputs connected to the output of the fixed-delay device and the output of the first amplitude control device,
an error measurement device having its negative input connected to the output of the phase detector and its positive input connected to a control signal,
an amplifier with low-pass characteristic having its input connected to the output of the error measurement device and its output to the control input of the first variable delay device.
According to another embodiment of the apparatus according to the present invention described above, the error measurement device is a subtractor and the amplifier with low-pass characteristic comprises an amplifier having its input connected to the output of the subtractor and a low-pass filter having its input connected to the output of the amplifier and its output to the control input of the first variable delay device.
According to an alternative embodiment of the apparatus according to the present invention, the error measurement device is a comparator and the amplifier with low-pass characteristic comprises an up-down-counter and a first digital-to-analog-converter, wherein the comparator's negative input is coupled to the output of the phase detector, its positive input is coupled to the control signal, and its output is coupled to the up-down-control input of the counter, wherein the counter's clock input is coupled to a clock signal and the counter's output is coupled to the input of the first digital-to-analog-converter which is connected to the control input of the first variable delay device.
According to another embodiment of the apparatus according to the present invention described in the above paragraphs, a second digital-to-analog-converter provides a control signal to the positive input of the error measurement device, e.g. to the subtractor.
According to another embodiment of the apparatus according to the present invention described in the above paragraphs, the apparatus comprises:
a plurality of further variable delay devices which have a plurality of input signals and are identical in construction with the first variable delay element, wherein the control inputs of said further variable delays are coupled to the same signal as the control input of the first variable delay device, and wherein the plurality of input signals can be of non-periodic or periodic nature, and
a plurality of further amplitude control devices which have a plurality of output signals and are identical in construction with the first amplitude control device, wherein each device of said plurality of variable delay devices provides an input signal to one device of said plurality of amplitude control devices and wherein the control inputs of said amplitude control devices are coupled to the same control signal as the control input of the first amplitude control device.
According to another embodiment of the apparatus according to the present invention described in the above paragraphs, the error measurement device is a subtractor with one positive and multiple negative inputs,
wherein a plurality of serially coupled elements is used each element consisting of an input which is coupled to a variable delay device and a fixed-delay device, an amplitude control device which is serially connected to the variable delay device, a phase detector which is coupled at its inputs to the output of the fixed-delay device and the amplitude control device,
wherein the elements of said plurality elements are serially coupled in such a way that the output of an amplitude control device of one element is coupled to the input of a variable delay device of another element,
wherein the first element of said plurality of serially coupled elements is coupled at its input to the output of the first amplitude control device,
wherein the outputs of the phase detectors in said plurality of serially coupled elements are coupled to the negative inputs of the subtractor,
wherein all variable delay devices in said plurality of serially coupled elements are identical in construction with the first variable delay device and are connected at their control inputs to the same signal as the control input of the first variable delay device,
wherein all fixed-delay devices in said plurality of serially coupled elements are identical in construction with the first fixed-delay device,
wherein all amplitude control devices in said plurality of serially coupled elements are identical in construction with the first amplitude control device and are coupled at their control inputs to the same signal as the control input of the first amplitude control device.



The invention is explained in greater detail hereinafter on the basis of preferred embodiments with reference to the enclosed drawings, in which:
FIG. 1 illustrates the QAM technique (state of the art);
FIG. 2 illustrates the direct local oscillator modulation technique (state of the art);
FIG. 3 illustrates the realization of an amplitude control device (state of the art);
FIG. 4 illustrates an embodiment of the present invention;
FIG. 5 illustrates an example of a linear phase detector characteristic;
FIG. 6 illustrates an example of a non-linear variable delay characteristic;
FIG. 7 illustrates an overall phase tuning characteristic according to an embodiment of the present invention;
FIG. 8 illustrates a preferred embodiment with parallel branches; and
FIG. 9 illustrates a preferred embodiment with an extended phase range.



A preferred embodiment of the apparatus according to the present invention is shown in FIG. 4. An input signal I, e.g. from a local oscillator, is fed to a variable delay device (1) and a fixed-delay device (3). An amplitude control device (2) with control input A for amplitude control is connected in series with the variable delay (1) and provides an output signal O. The output signal O and the output signal of the fixed-delay device (3) are fed to a linear phase detector (4). The output of the linear phase detector (4) is fed to the negative input of a subtractor (5). The positive input of the subtractor (5) is coupled to a phase control signal P. The output of the subtractor (5) is coupled to the input of an amplifier (6) with high gain which provides a signal to the low-pass filter (7). The output of the low-pass filter (7) is coupled to the control input of the variable delay device (1).
The circuit according to FIG. 4 operates as follows. Phase rsp. amplitude of the incoming signal I are modulated by means of the variable delay device (1) rsp. the amplitude control device (2). The input signal I is also fed to a fixed-delay device (3). For the explanation of the basic circuit principle at this point it is assumed that the delay of the fixed-delay device (3) is zero. In this case the linear phase detector (4) directly measures the delay rsp. phase shift between signals I and provides precise phase information. Since the phase detector output is connected to the negative input of the subtractor (5), the open loop gain of the control loop is negative resulting in a negative feedback system. If the amplifier (6) exhibits sufficiently high gain, the difference between phase control signal P and phase detector output at the subtractor input is driven to zero. The low-pass filter (7) is added to ensure loop stability and supress noise.
For further explanation of the operational principle and advantages the tuning characteristics of the circuit elements in FIG. 4 are used. Let jIO denote the phaseshift of signal O relative to periodic signal I. Again the delay rsp. phase shift of the fixed-delay device (3) is assumed to be zero. It is also assumed that within an intervall of 0 to 360 degree the phase detector (4) exhibits a precise linear characteristic according to FIG. 5 whereas VPD denotes the averaged phase detector output voltage. A typical non-linear tuning characteristic jIO(P′) of an integrated electronic version of the variable delay (1) might be looking like the solid line in FIG. 6 whereas P′ is the delay tuning signal. The dashed lines show the tuning characteristic with additional phase shift for different values of the amplitude control signal A. Under the assumption that the amplifier (6) has sufficient gain the resulting overall tuning characteristic jIO(P) can be depicted as in FIG. 7 whereas P is the phase control signal at the positive input of the subtractor in FIG. 4. As can be seen in FIG. 7 the overall tuning characteristic is solely determined by the characteristic of the linear phase detector (4) which allows to linearize non-linear tuning characteristic of the variable delay (1) as well as compensate phase shift variations of the amplitude control device (2).
Linear phase detectors have a linear characteristic between −180 to +180 degree, −90 to +90 degree, 0 to 180 degree, or 0 to 360 degree depending on the implementation. At the minimum and maximum value of the phase detector linear region linearity is deteriorated e.g. due to limited switching speed of logic gates in the case of a digital phase detector. Since a delay can only produce positive delays rsp. phase shifts, the fixed-delay (3) in FIG. 4 can be used to extend the range of phase difference seen at the phase detector input to negative values. For phase detectors with a characteristic which is symmetric to 0 degree the phase difference range is extended to negative values which extends the linear range of the circuit according to FIG. 4.
Variable delay realizations in integrated circuits such as e.g. a capacitively loaded inverter in CMOS (CMOS, Complementary Metal-Oxide Semiconductor) technology typically exhibits delay variations of over +−25% over PVT variances and non-linear tuning characteristic. An advantage of the invention according to claim 1 is therefore that delay tolerances are cancelled out and non-linear tuning characteristics can be linearized.
In contrast to inaccurate and non-linear delays, precise linear phase detectors are available in integrated microelectronic circuits in the form of digital phase detectors. A digital phase detector is a phase detector which uses digital devices such as logic gates and flip-flops. There are many different possibilities to realize digital phase detectors with linear characteristic [cf. Roland E. Best: “Phase-Locked Loops”, McGraw-Hill Professional Publishing, June 2003]. A simple example is an exclusive-or gate of which the averaged output voltage can be used for phase detection. The averaged output voltage of this phase detector depends only on phase shift of the input signals, switching speed of the transistors, and the supply voltage. In modern CMOS technologies sufficiently high switching speed can be guaranteed up to high phase detector input frequencies which ensures very good linearity.
The use of linear phase detection for phase rsp. delay control in the circuit according to FIG. 4 allows to use simple variable delay circuits for integrated circuits with poor accuracy and linearity as well as amplitude control devices with inaccurate phase without sacrificing high linearity and precision. At the same time the linear digital phase detector is a very simple digital device. Therefore the invention according to FIG. 4 has the advantage that at the same time circuit complexity is reduced and accuracy improved.
In comparison to the QAM technique the invention has the advantage that circuit complexity and accuracy requirements of analog components are greatly reduced. In addition no in-phase and quadrature signal, mixers or complex baseband signal generation circuits are required.
An advantage in comparison to direct modulation of the local oscillator in the synthesizer-PLL is that modulation takes place outside of the PLL and that the local oscillator frequency is not modulated. Hence PLL bandwidth is not limited by the low frequency content of the modulation signal spectrum and can be chosen with regard to other optimization criteria. Further oscillator phase noise can't be deteriorated due to modulation of the oscillator control input signal.
A preferred embodiment of the invention according to FIG. 4 is the replacement of the subtractor (5), the amplifier (6), and the low-pass filter (7) by a comparator, an up-down-counter, and a digital-to-analog-converter. The positive input of the comparator is coupled to the phase control signal P and the negative input is coupled to the output of the phase detector (4). The up-down control input of the up-down-counter is coupled to the output of the comparator and the clock input of the up-down-counter is coupled to a clock signal. The digital-to-analog-converter is connected to the up-down-counter output and provides at its analog output the control signal P′ to the variable delay element (1) in FIG. 4.
Another preferred embodiment of the invention is the use of a digital-to-analog-converter for the generation of the control signal P in FIG. 4. By this means phase can be controlled with a digital control word enabling digital phase modulation schemes.
Since the output of a digital phase detector in CMOS technology switches between supply voltage and ground, the averaged output voltage of a digital phase detector is proportional to the average supply voltage value. Another preferred embodiment of the invention is therefore to make the phase control signal P from FIG. 4 in the same way dependent from supply voltage as the digital phase detector output voltage. By this means it is possible to make the overall tuning characteristic jIO(P) of the circuit according to FIG. 4 independent of supply variations. One practical way to do this is by means of a digital-to-analog converter which generates the phase control signal P and uses the supply voltage as reference voltage. In this case the digital-to-analog-converter might be providing a phase control voltage of e.g. (supply voltage)/Z with Z being the value of the digital-to-analog-converter input word. By this means the phase- and amplitude modulator according to FIG. 4 is fully insensitive to PVT variances.
A further preferred embodiment of the invention is shown in FIG. 8. The invention according to FIG. 4 is extended in such a way that one or more parallel branches are added wherein each branch is made of a variable delay in series with an amplitude control device. All variable delays are identical in construction, share the same delay control signal P′ but have different input signals. Accordingly all amplitude control devices share the same control signal A, are identical in construction but have different output signals. By this means parallel signals such as digital busses can be precisely delayed with little extra hardware. Advantageously the fixed-delay device should be by-passed or set to a delay of zero.
Another embodiment of the invention is depicted in FIG. 9. The circuit according to FIG. 4 is extended in such a way that one or more branches are added which are serially connected to each other. Each of said branches is made of a variable delay device in series with an amplitude control device and a fixed-delay device with the same input signal as the variable delay device. All fixed-delay devices are identical in construction. All variable delays are identical in construction and share the same delay control signal P′. Accordingly all amplitude control devices share the same control signal A and are identical in construction. Further each branch has a separate phase detector which measures the phase difference between the output of the fixed-delay device and output of the amplitude control device. The subtractor according to the circuit from FIG. 4 is replaced by a subtracter with one positive and multiple negative inputs. All phase detector outputs are coupled to negative inputs of the subtractor and the phase control signal P is connected to the positive input of the subtractor. The circuit according to FIG. 9 has the advantage that phase ranges which extend the linear range of a single phase detector can be accomplished.
The technique in FIG. 9 can also advantageously be used for improving linearity. The linearity of digital phase detectors decreases near the upper and lower limit of the total phase range. For a specified phase shift range the use of multiple phase detectors and serially connected branches allows to reduce the phase shift that is seen by a single phase detector. Hence precision and linearity of phase measurement are improved.

## Claims

1. An apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising:
a first fixed-delay device having its input coupled to an input signal,
a first variable delay device having its input coupled to said input signal and having a control input for delay adjustment,
a first amplitude control device in series with the first variable delay device, providing at its output an amplitude controlled signal and having a control input for adjusting the output amplitude,
a phase detector with linear characteristic having its two inputs connected to the output of the fixed-delay device and the output of the first amplitude control device,
an error measurement device having its negative input connected to the output of the phase detector and its positive input connected to a control signal,
an amplifier with low-pass characteristic having its input connected to the output of the error measurement device and its output to the control input of the first variable delay device.

2. The apparatus of claim 1, wherein the error measurement device is a subtractor and wherein the amplifier with low-pass characteristic comprises an amplifier having its input connected to the output of the subtractor and a low-pass filter having its input connected to the output of the amplifier and its output to the control input of the first variable delay device.

3. The apparatus of claim 1, wherein the error measurement device is a comparator and wherein the amplifier with low-pass characteristic comprises an up-down-counter and a first digital-to-analog-converter, wherein the comparator's negative input is coupled to the output of the phase detector, its positive input is coupled to the control signal, and its output is coupled to the up-down-control input of the counter, wherein the counter's clock input is coupled to a clock signal and the counter's output is coupled to the input of the first digital-to-analog-converter which is connected to the control input of the first variable delay device.

4. The apparatus of claim 1, wherein a second digital-to-analog-converter provides a control signal to the positive input of the error measurement device.

5. The apparatus of claim 1, comprising:
a plurality of further variable delay devices which have a plurality of input signals and are identical in construction with the first variable delay element, wherein the control inputs of said further variable delays are coupled to the same signal as the control input of the first variable delay device, and wherein the plurality of input signals can be of non-periodic or periodic nature,
a plurality of further amplitude control devices which have a plurality of output signals and are identical in construction with the first amplitude control device, wherein each device of said plurality of variable delay devices provides an input signal to one device of said plurality of amplitude control devices and wherein the control inputs of said amplitude control devices are coupled to the same control signal as the control input of the first amplitude control device.

6. The apparatus of claim 1,
wherein the error measurement device is a subtractor with one positive and multiple negative inputs,
wherein a plurality of serially coupled elements is used each element consisting of an input which is coupled to a variable delay device and a fixed-delay device, an amplitude control device which is serially connected to the variable delay device, a phase detector which is coupled at its inputs to the output of the fixed-delay device and the amplitude control device,
wherein the elements of said plurality elements are serially coupled in such a way that the output of an amplitude control device of one element is coupled to the input of a variable delay device of another element,
wherein the first element of said plurality of serially coupled elements is coupled at its input to the output of the first amplitude control device,
wherein the outputs of the phase detectors in said plurality of serially coupled elements are coupled to the negative inputs of the subtractor,
wherein all variable delay devices in said plurality of serially coupled elements are identical in construction with the first variable delay device and are connected at their control inputs to the same signal as the control input of the first variable delay device,
wherein all fixed-delay devices in said plurality of serially coupled elements are identical in construction with the first fixed-delay device,
wherein all amplitude control devices in said plurality of serially coupled elements are identical in construction with the first amplitude control device and are coupled at their control inputs to the same signal as the control input of the first amplitude control device.