# Patent

## Title
Foldback free capacitance-to-digital modulator

## Abstract

A capacitance-to-digital (CD) modulator converts capacitance of a differential pressure sensor to a pulse code modulation output signal. The first stage of the CD modulator is a sigma-delta integrator having an auto-zero capacitor connected between an integrator input node and an amplifier input. During an auto-zero phase, a feedback capacitor is connected between the amplifier input and output, and the auto-zero capacitor stores a voltage that is a function of leakage resistance of the sensor capacitor connected to the integrator input node. During an integration phase, the feedback capacitor is connected to the integrator input node. If an overpressure/short circuit condition exists, the stored voltage on the auto-zero capacitor induces a current to flow to the feedback capacitor to drive the integrator to saturation and suppress foldback anomaly.

## Background
CROSS REFERENCE TO RELATED APPLICATION
Reference is made to a commonly assigned co-pending application filed on even date entitled “Capacitance-to-Digital Interface Circuit For Differential Pressure Sensor”.
BACKGROUND OF THE INVENTION
The present invention relates to a measurement system. In particular, the present invention relates to a capacitance-to-digital modulator for use with a capacitive differential pressure sensor.
A field transmitter is a device that is used to monitor the operation of an industrial process. The field transmitter includes a transducer that responds to a measured process variable with a sensing element and converts the variable to a standardized transmission signal that is a function of the measured variable. The term “process variable” refers to a physical or chemical state of matter or conversion of energy. Examples of process variables include pressure, temperature, flow, conductivity, and pH.
One such transmitter is described in U.S. Pat. No. 6,295,875 by Roger L. Frick and David A. Broden. This transmitter employs a capacitive sensor having a deflectable sensing diaphragm and three or more capacitor electrodes which form separate capacitive sensing elements with the diaphragm. Two of the capacitor elements are primary sensing capacitors that are arranged differentially so that the capacitances of the primary sensing capacitors charge oppositely in proportion to the process variable.
The third and fourth capacitor elements are compensation capacitors that provide signals representing offset errors or hysteresis associated with the primary capacitors. As pressure is applied to one or both sides of the diaphragm, the diaphragm deflects. The deflection of the diaphragm can be detected by measuring a change in a ratio of electrical capacitance related to the deflection. This capacitance ratio is converted into a digital format using an analog-to-digital converter.
One particularly advantageous form of analog-to-digital converter uses a sigma-delta (or delta-sigma) modulator. The use of sigma-delta modulators in transmitters is described in U.S. Pat. No. 5,083,091 by Roger L. Frick and John P. Schulte; U.S. Pat. No. 6,140,952 by Michael Gaboury; U.S. Pat. No. 6,509,746 by Rongtai Wang; and U.S. Pat. No. 6,516,672 by Rongtai Wang.
In a transmitter having a sigma-delta modulator acting as a capacitance-to-digital (CD) converter, an excitation circuit provides charge packets to the capacitive sensor elements. The sensor elements are charged by an amount based on the capacitance value of that capacitive element. The charges are transferred to an integrator/amplifier of the sigma-delta modulator to produce a one-bit binary output which is a function of a capacitance ratio.
The basic function of the CD modulator is to convert the capacitance ratio into a PCM (pulse code modulation) signal. The capacitance ratio under measurement is defined as: η=(CX−CY)/(CX+CY), where CX and CY represent capacitance of two sensor capacitors with a common plate.
For a CD modulator using sigma-delta architecture, the actual process involves converting a charge ratio into a PCM signal. Under normal operating conditions, since the charge is proportional to the capacitance, the charge ratio is equal to the capacitance ratio.
However, this equivalent relation is not true under certain abnormal operating conditions. One such operating condition is overpressure in conjunction with a short circuit in one of the sensor capacitors. Due to the leakage caused by the short circuit, the charge that is transferred from the sensor capacitor may be very small. As a result of this, the digital reading provided by PCM signal is not equal to the capacitance ratio. Not only is the magnitude of the reading not correct, in many cases even the polarity of the reading is wrong. This kind of phenomena is called “fold-back anomaly”. There is a need for improved circuitry that eliminates the fold-back anomaly.
BRIEF SUMMARY OF THE INVENTION
A capacitance-to-digital (CD) modulator converts capacitance of a pressure sensor to a pulse code modulation output signal. The first stage of the CD modulator is a sigma-delta integrator having an auto-zero capacitor connected between an integrator input node and an amplifier input. During an auto-zero phase, a feedback capacitor is connected between the amplifier input and output, and the auto-zero capacitor stores a voltage that is a function of leakage resistance of the sensor capacitor connected to the integrator input node. During an integration phase, the feedback capacitor is connected to the integrator input node. If an overpressure/short circuit condition exists, the stored voltage on the auto-zero capacitor induces a current to flow to the feedback capacitor to drive the integrator to saturation and suppress foldback anomaly.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a differential pressure transmitter.
FIG. 2 is a block diagram of a capacitance-to-digital (CD) modulator of the transmitter of FIG. 1.
FIG. 3 is a schematic diagram of one embodiment of a first stage integrator of the CD modulator of FIG. 2.
FIG. 4 is a diagram showing an example of VOUT1, auto-zero (Z) and integration (I) signals of the first stage integrator of FIG. 3.
FIG. 5 is a schematic diagram of a second stage integrator of the CD modulator of FIG. 2.
FIG. 6 is a schematic diagram of a quantizer of the CD modulator of FIG. 2.
FIGS. 7A and 7B show waveforms of first stage output voltage VOUT1 and pulse code modulation pressure signal PCMP from a computer simulation of normal operation of the CD modulator of FIGS. 2–6.
FIGS. 8A and 8B show waveforms of first stage output voltage VOUT1 and pulse code modulation pressure signal PCMP from a computer simulation of overpressure/short circuit operation of the CD modulator of FIGS. 2–6.
FIG. 9 is a schematic diagram of another embodiment of a first stage integrator of CD modulator of FIG. 2.
FIGS. 10A and 10B show output current and output voltage, respectively, as a function of load resistance for an operational transconductance amplifier (OTA) buffer.
FIGS. 11A and 11B show a computer simulation of output current and output voltage characteristics of the OTA buffer used in the first stage integrator of FIG. 9.
FIGS. 12A and 12B show waveforms of first stage output voltage VOUT1 and pressure signal PCMP from a computer simulation of overpressure/short circuit operation of a CD modulator without anti-foldback circuitry.
FIGS. 13A and 13B show waveforms of first stage output voltage VOUT1 and pressure signal PCMP from a computer simulation of overpressure/short circuit operation of a CD modulator including the first stage integrator of FIG. 9.



DETAILED DESCRIPTION
FIG. 1 shows pressure transmitter 10, which is a capacitance-based differential pressure transmitter that includes main sensor capacitors CMX and CMY, linear compensation capacitors CLX and CLY, resistors RX and RY, analog section 12 (which includes second order capacitance to digital (CD) modulator 14, first order voltage to digital (VD) modulator 16, and digital interface unit 18), digital section 20, microprocessor 22, and interface 24. Communication between transmitter 10 and a control room is provided through interface 24. The communication may be through a two-wire loop or network over which analog, digital, or a combination of analog and digital signals are transmitted, or may be via wireless transmission.
Analog section 12 and digital section 20 may be incorporated in a mixed signal application specific integrated circuit (ASIC) chip. Digital interface unit 18 of analog section 12 receives digital clock signals and other control signals from digital section 20. Digital interface unit 18 provides a level shift function between the signal levels required for digital section 20 and those required for analog section 12. It also generates timing signals and other control signals for CD modulator 14 and VD modulator 16.
The timing signals provided by digital interface unit 18 include zero phase signals Z and ZD, integration phase signals I and ID, quantizer timing signals SCK and DCK, and a reset signal.
Second order CD modulator 14 is a sigma-delta converter that receives capacitance inputs CX and CY at input nodes 30 and 32 and produces a pulse code modulation pressure (PCMP) signal that is a function of the difference of capacitances CX and CY divided by the sum of capacitances CX and CY. CD modulator 14 receives timing and control signals from digital interface unit 18 and generates excitation signals SENEX and LINEX.
Components CMX and CMY represent the sensor capacitors, with their common plate connected to receive sensor excitation signal SENEX. Components CLX and CLY are linear compensation capacitors having their common plate connected to a linearization excitation signal LINEX.
Input capacitances CX and CY are defined as:

CX=CMX−CLX 

CY=CMY−CLY 

The differential capacitance ratio ηP is:





  
    η
    p
  
  =
  
    
      
        C
        X
      
      -
      
        C
        Y
      
    
    
      
        C
        X
      
      +
      
        C
        Y
      
    
  




The transfer function for CD modulator 14 is:

ηp=2·DP−1

where DP is the pulse density of PCMP signal. For normal operation, the dynamic range of the ratio ηP is:

−0.8≦ηp≦0.8,

where CX and CY can each reach a maximum effective capacitance of about 100 pF. CD modulator 14 must be fold-back free in the case of overpressure with a short circuit.

VD modulator 16 is a first order sigma-delta converter or integrator which receives a voltage input VTIN from the voltage divider performed by resistor RO and temperature sensing resistor RTD at its input node 34. The output of VD modulator 16 is a pulse code modulation temperature (PCMT) signal.
The PCMP and PCMT outputs from CD modulator 14 and VD modulator 16 are provided to digital section 20 where they are filtered. Pressure and temperature data based on the filtered PCMP and PCMT signals is stored in digital section 20 for use by microprocessor 22 and for transmission through interface circuit 24.
FIG. 2 shows a block diagram of CD modulator 14, which includes first stage integrator 40, second stage integrator 42, quantizer 44, control unit 46, and bias circuit 48. First stage integrator 40 is a sigma-delta integrator that produces a first stage output that is a function of capacitances CX and CY. Integrator 40 operates in an auto-zeroing mode during a first (or auto-zero) phase defined by the timing signals Z and ZD, where ZD is slightly delayed with respect to Z. Integrator 40 operates in an integration mode during a second (or integration) phase defined by the integration timing signals I and ID, where ID is slightly delayed with respect to I. The selection of which input (CX or CY) is connected to integrator 40 is based upon the state of output signal Y from quantizer 44.
Second stage integrator 42 is a sigma-delta integrator that samples the output of first stage integrator 40, and produces an output that is supplied to quantizer 44. Because first stage integrator 40 is not reset during the auto-zero phase, a two phase second order CD modulation is possible. Second stage integrator 42 performs its auto-zero and integration phases at the same time as first stage integrator 40, using the Z, ZD, I, and ID timing signals. In addition, second stage integrator 42 receives a reset signal.
The function of quantizer 44 is to convert the output signal of second stage integrator 42 to pulse code modulation signal PCMP, which is delivered to digital section 20. Quantizer 44 also provides signal Y, which is the inverse of signal PCMP. Y is used by CD control unit 46 and first stage integrator 40.
The main function of control unit 46 is to generate the SENEX signal and the LINEX signal. These signals are generated as a function of Y and the ZD and ID timing signals. The SENEX and LINEX signals are switched between a midlevel excitation voltage source VMID and a low side excitation voltage source VSSA. The LINEX signal is the inverse of the SENEX signal.
CD bias circuit 48 provides source current for the amplifiers of integrators 40 and 42 and the comparator of quantizer 44. It also generates bias voltages for the amplifiers, and provides a source current for the bias circuitry of VD modulator 16.
FIG. 3 is a circuit schematic diagram of first stage integrator 40. Also shown in FIG. 3 are sensor capacitors CX and CY, leakage resistors RXL and RYL, and resistors RX and RY, and a simplified diagram of CD control unit 46.
First stage integrator 40 includes amplifier A1, feedback capacitor CF1, auto-zero capacitor CZ1, switches SW1–SW7 and on chip resistors R1–R3. In one embodiment, feedback capacitor CFI is 150 pF, auto-zero capacitor CZ1 is 30 pF, resistors R1 and R2 are 10 kΩ each, and resistor R3 is 4 kΩ.
The switch control signals for switches S1–S7, SWA and SWB are:

SW1=SW4=Y

SW2=SW3= Y

SW5=I

SW6=Z

SW7=ZD

SWA=Y·ID+ Y·ZD 

SWB=Y·ZD+ Y·ID 

The operation of first stage integrator 40 is as follows. During the auto-zero phase, switch SW5 is off and switches SW6 and SW7 are on. The offset of amplifier A1 is stored in capacitor CZ1 without first stage integrator 40 being reset (i.e., without feedback capacitor CF1 being discharged). At the same time, the sensor capacitor (either CX or CY) is charged or discharged.
In the case where Y is high, sensor CX is selected with its input node connected by SW1 to common node A of integrator 40. With Y high and ZD high, switch SWB of CD control unit 46 is on and the SENEX signal applied to sensor CX is VSSA. As a result, a voltage drop is built across CX, since integrator input node A of integrator 40 is connected through switch SW7 and resistor R3 to VMID.
In the case where Y is low, sensor CY is connected by SW3 to integrator input node A of integrator 40. In that case, switch SWA is on and SWB is off so that the SENEX node is connected to VMID. Voltage drop across CY is zero, because switches SW3 and SW7 are closed and CY has voltage VMID applied to both of its plates.
During the integration phase, switch SW5 is on and switches SW6 and SW7 are off. Integrator 40 is in an integration mode.
In the case where Y is high, the SENEX node will have suddenly changed from VSSA to VMID as a result of switch SWB turning off and SWA turning on. A positive charge package is transferred from CX through SW1 to integrator input node A of integrator 40. As a result, a negative voltage step is created at VOUT1.
In the case where Y is low, the SENEX node is suddenly switched from VMID to VSSA. A negative charge package is transferred from CY through SW3 to integrator input node A. As a result, a positive voltage step is created at VOUT1.
The excitation voltage ΔVEX is the voltage difference between VMID and VSSA. The amount of charge transferred into first stage integrator 40 from CX or CY in each operation can be expressed as AQX=CX·ΔVEX or ΔQY=CY·ΔVEX respectively. By denoting N0 as the number CX operations, N1 as the number CY operations, and N=N0+N1 as the total number of operations, the charge balancing equation for first stage integrator 40 can be written as:

N0·CX·ΔVEX−N1CY·ΔVEX=0.

This gives the required measurement relation:





  
    
      
        
          C
          X
        
        -
        
          C
          Y
        
      
      
        
          C
          X
        
        +
        
          C
          Y
        
      
    
    =
    
      
        2
        ⁢
        
          
            N
            1
          
          N
        
      
      -
      1
    
  
  ,




where the ratio N1/N is the pulse density of the PCMP signal.

FIG. 4 shows an example waveform of VOUT1 for first stage integrator 40, along with the auto-zero phase signal Z and the integration phase signal I. In this example, CX=75 pF, CY=25 pF, Cn=150 pF, CZ=30 pF, and VDDA=4.8V, VSSA=0 and VMID=2.4V.
As seen in FIG. 4, the output VOUT1 of first stage integrator 40 is on hold during the auto-zero phase (when Z is high). In other words, VOUT1 is not reset to zero during each auto-zero phase. This allows two phase second order operation, in which second stage integrator 42 uses the same auto-zero and integration phases as first stage integrator 40. As a result, the number of switches and control signals required for CD modulator 14 is reduced, circuit complexity and layout complexity is reduced, and the settling of integrators 40 and 42 is improved.
FIG. 5 shows a circuit schematic diagram of second stage integrator 42, which includes amplifier 82, feedback capacitor CF2, auto-zero capacitor CZ2, two sampling capacitors C1 and C2, and switches SW8–SW15. In one embodiment, CF2=40Pf, CZ=10PF, C1=20Pf and C2=10PF.
The switch control signals for SW8–SW15 are:

SW8=SW11=ID

SW9=SW10=ZD

SW12=I

SW13=Z

SW14=ZD

SW15=RESET

FIG. 6 is a simplified circuit schematic of CD quantizer 44, which compares VOUT2 to VMID and produces the pulse code modulated pressure signal PCMP as well as control signal Y. CD quantizer 44 includes comparator 50, D flip-flop 52 and inverters 54 and 56.
The positive input node of comparator 50 is connected to VMID, while the negative input node is connected to the output VOUT2 of second stage integrator 42. Timing signal SCK provides an active low trigger for comparator 50.
D flip-flop 52 serves a synchronization purpose. It is triggered by the front edge of the DCK signal. That front edge is located between the falling edge of the integration phase timing signal ID and the rising edge of the auto-zero phase timing signal Z.
Two stage CD modulator 14 provides an automatic fold-back feature, without the need for a short circuit detector or other auxiliary circuitry in order to suppress the fold-back anomaly. Two cases need to be considered: CX side overpressure with a short circuit; and CY side overpressure with a short circuit. In both cases, first stage integrator 40 prevents fold-back.
In the case of CX side overpressure together with a short circuit, auto-zero capacitor CZ1 also serves as a short circuit adapter. During auto-zero phase, switches SW6 and SW7 are closed, and SWB is closed, applying VSSA to CX. Current flows from VMID, through R3 and SW7 to node A, and through SW1, RX and RXL to VSSA. Due to the small leakage resistance RXL across CX (i.e. a short circuit), the voltage at integrator input node A becomes much lower than VMID during the auto-zero phase. This lower voltage is sampled in the auto-zero phase, and is held by first integrator 40 in the integration phase.
During the integration phase, SW5 is closed, SW6 and SW7 are open, and SWA is closed to apply VMID to CX. The lower voltage at node A induces a current during the integration phase from VMID through RXL, RX, and SW1 and SW5 into CF1. It is this induced current that keeps integrator 40 in saturation. As a result, no fold-back anomaly occurs.
In the case of CY side overpressure with a short circuit, the voltage drop on CY is discharged to zero in the auto-zero phase because it has VMID applied to both plates of CY when Y is low and ZD is high. Therefore, the leakage resistor RYL across CY has no effect on the voltage across CY. In the integration phase with Y low, the SENEX node is connected to VSSA. The short circuit across CY will make integrator saturation even deeper, and no fold-back anomaly will occur.
In order to protect the VMID voltage source from an overpressure short circuit, resistors R1–R3 are provided in integrator 40 shown in FIG. 3. Resistor R1 is placed between switch SW2 and VMID. Resistor R2 is placed between switch SW4 and VMID. Resistor R3 is placed between switch SW7 and VMID. The values of the resistors are chosen in such a way that the average DC current leak from VMID to VSSA is always below 100 microamps. At the same time, the RC time constant is reasonably small, so that first stage integrator 40 will settle as required.
In order to demonstrate the automatic fold-back suppression, a simulation of circuit operation was performed using HSPICE software. The results are illustrated in FIGS. 7A and 7B and FIGS. 8A and 8B.
FIGS. 7A and 7B are an example of the operations of CD modulator 14 with a normal input. In this example, CX=75 pF, CY=25 pF, CF1=150 pF, Cz1=30 pF, and VDDA=4.8V, VSSA=0 and VMID=2.4V. FIG. 7A shows a waveform of output VOUT1 from first stage integrator 40. FIG. 7B shows corresponding pulse code modulation output signal PCMP.
FIGS. 8A and 8B show an example in which X side overpressure and a short circuit have occurred. In this example, CX=2,000 pF, CY=10 pF, CF1=150 pF, CZ1=30 pF, VDDA=4.8V, VSSA=0 and VMID=2.4V. The leakage resistor RXL across Cx is 1 ohm, while the leakage resistor RYL across CY is 1 Gohm. FIG. 8A is a waveform of output VOUT1 of first stage integrator 40. FIG. 7B shows the waveform of the corresponding pulse code modulation output signal PCMP. As can be seen, despite the combined effects of X side overpressure and a short circuit, output signal PCMP indicates a high or overpressure condition.
FIG. 9 shows another embodiment of first stage integrator 40′, which is generally similar to the embodiment shown in FIG. 3, except that protection resistors R1–R3 have been replaced by operational transconductance amplifier (OTA) buffer 70, which converts midlevel supply voltage (VMID) to a variable voltage VMIDA that varies as a function of load resistance at the output of OTA buffer 70. The positive input of OTA buffer 70 is connected at VMID. The negative input and the output of OTA buffer 70 are connected together.
FIGS. 10A and 10B illustrate the output current and output voltage characteristics, respectively, of OTA buffer 70. In FIG. 10A, output current IOUT of OTA buffer 70 is shown as a function of load resistance RL. In the region where load resistance RL is greater than characteristic resistance RO, the buffer output current IOUT decreases as load resistance RL increases. The relationship is approximately IOUT=VREF/RL. In the region where load resistance RL is less than RO, the buffer output current IOUT remains a constant approximately. This constant current is equal to the maximum slew current IO of OTA buffer 70.
As shown in FIG. 10B, output voltage VOUT also varies as a function of load resistance RL. In the region where load resistance RL is greater than RO, output voltage VOUT of OTA buffer 70 is determined by the output current IOUT and the transconductance GM of OTA buffer 70. That is,

VOUT≈VREF+VOFFSET−IOUT1GM.

In the region where load resistance RL is less than RO, the buffer output voltage VOUT decreases as load resistance decreases:

VOUT≈IOUT·RL.

The characteristic resistance value RO can be estimated by RO≈VREF/IOUT.

Under normal operating conditions without a short circuit, leakage resistance RXL of sensor capacitor CX is very high. During the auto-zero phase, since the load resistance seen by OTA buffer 70 is RX+RXL (and therefore is very high) buffer 70 serves as a constant voltage source. VMIDA at the output of buffer 70 differs from VMID by small offset.
The voltage difference VMIDA−VSSA is fully dropped across sensor capacitor of CX during the auto-zero phase, and a desired charge package is stored in sensor capacitor CX. During the integration phase, an expected voltage step is created at the integrator output node during normal operation. In the case of overpressure without a short circuit, since the value of the input capacitor CX exceeds the value of feedback capacitor CF1, integrator 40′ becomes saturated.
During an abnormal operating condition involving an overpressure of CX with a short circuit, leakage resistance RXL across sensor capacitor CX is very small. During auto-zero phase, since the effective load resistance seen by OTA buffer 70 is much smaller than RO, buffer 70 serves as a current source through switch SW1, RX, and RXL and switch SWB to voltage supply VSSA. The buffer output voltage VMIDA becomes lower than VMID. The lower buffer output voltage VMIDA causes a lower voltage at node A. The voltage difference between node A and the negative input of amplifier A1 is stored in auto-zero capacitor CZ1.
During integration phase, due to the stored voltage in auto-zero capacitor CZ1, a current is induced. This current flows from VMID, through SWA, RXL, RX, SW1, and SW5 into feedback capacitor CF1. It is this current that forces integrator 40′ to be fully saturated.
In summary, with the embodiment shown in FIG. 9, during the auto-zero phase the leakage resistance RXL (an analog variable) is converted into an input node A voltage (another analog variable) and is stored in auto-zero capacitor CZ1. During the integration phase, the voltage stored in auto-zero capacitor CZ1 will control integrator operation. In the case of overpressure with a short circuit, integrator 40′ will become saturated.
In order to demonstrate the automatic fold back suppression of the circuit shown in FIG. 9, a simulation of circuit operation was performed using HSPICE software. The results are illustrated in FIGS. 11A and 11B, 12A and 12B, and 13A and 13B.
FIGS. 11A and 11B show the HSPICE simulation results of the characteristics of OTA buffer 70 with a variable resistance load. FIG. 11A shows output current, and FIG. 11B shows output voltage.
In the simulation results shown in FIGS. 11A and 11B, the supply of the buffer circuit is 4.8V, and the reference input VMID is 2.4V. In this simulation, a linear voltage control load resistor is employed. That is, when the control voltage is 1 VC, the load resistor value is 100K. When the control voltage is 500V, the load resistor value is 50K. The characteristic load resistance in the simulation was RO=45.4K.
FIG. 11A shows output current IOUT as a function of the control voltage VC. In the region RL is less than RO, the output current is close to a constant (about 58μA). In the region where load resistance RL is greater than the characteristic load resistance RO, the output current decreases as RL increases.
FIG. 11B shows output voltage VOUT versus the control voltage VC. In the region where load resistance RL is less than characteristic load resistance RO, the output voltage VOUT decreases as load resistor value (control voltage) decreases. In the region where load resistance RL exceeds characteristic load resistance RO, the buffer output voltage VOUT is close to a constant.
FIGS. 12A and 12B show the HSPICE simulation results of a CD modulator without anti-fold-back circuitry. FIG. 12A shows waveform of output voltage VOUT1 representing the output of first stage integrator 40′. FIG. 12B shows a waveform of the PCMP output signal.
In this simulation, the input sensor capacitance size is CX=2,000 pF and CY=10 pF. The leakage resistor for the X side is RXL=500 ohm, and for the Y side RYL=100 Gohm. The input series resistor RX and RY are 12.1K.
Based upon the input, the calculated capacitance ratio for this simulation is above 0.90. However, based upon the PCMP signal, the capacitance ratio produced by the CD modulator is about 0.65. This illustrates the inaccuracy produced by fold-back anomaly.
FIGS. 13A and 13B show the HSPICE simulation results of the two phase CD modulator with the anti-foldback feature using OTA buffer 70 as shown in FIG. 9. FIG. 13A shows the output of first stage integrator 40′, while FIG. 13B shows the waveform of the PCMP output signal.
For the simulation shown in FIGS. 13A and 13B, the capacitances are CX=2,000 pF and CY=10 pF. The leakage resistors are RXL=5000 hms and RY=100 Gohm. The input series resistors RX and RY are 12.1K. Thus the capacitance and resistance values are the same as used for the simulation in FIGS. 12A and 12B. The OTA characteristics used for buffer 70 are the ones shown in FIGS. 11A and 11B.
Based upon the input, the calculated capacitance ratio is above 0.90. Based on the PCMP signal shown in FIG. 13B, capacitance ratio reading is about 0.90. Thus, the fold-back anomaly has been suppressed.
Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

## Claims

1. A sigma-delta integrator comprising:
a sensor excitation node;
an integrator input node;
an amplifier having a first input, a second input and an output;
an auto-zero capacitor connected between the integrator input node and the first input of the amplifier;
a feedback capacitor having a first terminal connected to the output of the amplifier, and having a second terminal that is connected to the first input of the amplifier during an auto-zero phase and is connected to the integrator input node during an integration phase;
a first sensor capacitor connected to the sensor excitation node and selectively connected to the integrator input node;
a sensor excitation signal source connected to the sensor excitation node for providing to the first sensor capacitor a sensor excitation signal having a first supply voltage level during the auto-zero phase and a second supply voltage level during the integration phase; and
a circuit for providing to the integrator input node, during the auto-zero phase, a voltage that is a function of leakage resistance of the first sensor capacitor.

2. The sigma-delta integrator of claim 1, wherein the circuit comprises an operational transconductance amplifier (OTA) buffer.

3. The sigma-delta integrator of claim 2, wherein the OTA buffer has a first input for receiving the second supply voltage level, and a second input connected to an output.

4. The sigma-delta integrator of claim 3, wherein the circuit further comprises a switch for connecting the output of the OTA buffer and the integrator input node during the auto-zero phase, and disconnecting the output of the OTA buffer from the integrator input node during the integration phase.

5. The sigma-delta integrator of claim 1, wherein the second input of the amplifier is connected to the second supply voltage level.

6. The sigma-delta integrator of claim 1, wherein during the auto-zero phase, the auto-zero capacitor stores a voltage representing a difference between a voltage at the first input of the amplifier and the voltage at the integrator input node.

7. The sigma-delta integrator of claim 6, wherein during the auto-zero phase, the voltage at the first input of the amplifier is a function of voltage across the feedback capacitor.

8. The sigma-delta integrator of claim 1, and further comprising:
a second sensor capacitor connected to the sensor excitation node and selectively connected to the integrator input node; and
wherein the sensor excitation signal source provides to the second sensor capacitor the second supply voltage level during the auto-zero phase and the first supply voltage level during the integration phase.

9. The sigma-delta integrator of claim 1, wherein the first supply voltage level is lower than the second supply voltage level.

10. A sigma-delta integrator for selectively forming charge packets as a function of sensor capacitance during an auto-zero phase, and integrating the charge packets during an integration phase to produce an integrator output voltage, the sigma-delta integrator comprising:
an integrator input node;
an amplifier having a first input, a second input and an output;
a feedback capacitor connected to the output of the amplifier; and
an auto-zero capacitor connected to the integrator input node for storing voltage that is a function of sensor leakage resistance during the auto-zero phase.

11. The sigma-delta integrator of claim 10 wherein the voltage stored by the auto-zero capacitor during the auto-zero phase causes the integrator to saturate during the integration phase in an overpressure and short circuit condition.

12. The sigma-delta integrator of claim 10 and further comprising:
an operational transconductance amplifier (OTA) buffer having first input for receiving the second supply voltage level, and a second input connected to an output; and
a switch for connecting the output of the OTA buffer and the integrator input node during the auto-zero phase, and disconnecting the output of the OTA buffer from the integrator input node during the integration phase.

13. A capacitance-to-digital modulator comprising:
a first capacitance pressure sensor;
a second capacitance pressure sensor;
a first integrator for selectively forming charge packets as a function of capacitance of one of the first and second capacitance pressure sensors during a first phase, and integrating charge during a second phase to produce an integrator output voltage;
an integrator input node;
an amplifier having a first input, a second input and an output;
a feedback capacitor connected to the output of the amplifier;
a switching circuit for selectively connecting the first capacitance pressure sensor and the second capacitance pressure sensor to the integrator input node, for connecting the feedback capacitor to the first input during the first phase, and for connecting the feedback capacitor to the integrator input node during the second phase; and
an auto-zero capacitor connected between the integrator input node and the first input of the amplifier, wherein the auto-zero capacitor stores a voltage that is a function of sensor leakage resistance during the first phase.

14. The capacitance-to-digital modulator of claim 13 wherein an excitation signal source connected to the first and second capacitance pressure sensors switches between a midlevel supply voltage and a low level supply voltage as a function of the first and second phases.

15. The capacitance-to-digital modulator of claim 14 wherein the second input of the amplifier is connected to receive the midlevel supply voltage.

16. The capacitance-to-digital modulator of claim 13 wherein the voltage stored by the auto-zero capacitor induces current flow to the feedback capacitor that causes the amplifier to saturate during the integration phase if an overpressure and short circuit condition exists.