# Patent

## Title
System for detecting current in an output stage of a power amplifier

## Abstract

A system for detecting current in an output stage of power amplifier circuitry in a transmitter of a mobile terminal is provided. In general, the mobile terminal includes power amplifier circuitry, power control circuitry, current detection circuitry, and an inductor that essentially prevents radio frequency coupling between the power control circuitry and the power amplifier circuitry. Based on a voltage across the inductor, the current detection circuitry generates a voltage detection signal indicative of a current in the inductor and thus the current in an output stage of the power amplifier.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of provisional patent application Ser. No. 60/603,129, filed Aug. 20, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
This U.S. patent application is related to the concurrently filed U.S. patent application Ser. No. 60/603,130 entitled SYSTEM FOR LIMITING CURRENT IN AN OUTPUT STAGE OF A POWER AMPLIFIER by Madsen et al., which is hereby incorporated by reference in its entirety.


FIELD OF THE INVENTION
The present invention relates to power amplifiers and particularly relates to sensing current in an output stage of a power amplifier.
BACKGROUND OF THE INVENTION
One of the primary goals in designing mobile telephones is to reduce power consumption in order to increase battery-life. In large part, the power consumption of a mobile telephone is dependent upon the amount of current drawn by a power amplifier in the transmit chain that operates to amplify a transmit signal prior to sending the signal to the antenna for transmission. In general, the power amplifier is designed to operate based on an ideal load at the antenna. However, due to factors such as how a user is holding the phone and the distance between the antenna and the user's body, the load seen by the power amplifier varies. Thus, a mismatch is created between the power amplifier and the antenna. For example, the power amplifier may be designed to operate with an ideal load of 50 ohms. However, a user may hold a phone such that the load seen at the antenna is 25 ohms, thereby creating a 2:1 mismatch. This mismatch can be as large as 10:1 and causes a large amount of current to flow through the power amplifier, thereby reducing the battery-life of the mobile telephone. Accordingly, there remains a need for a system that limits the current in the power amplifier in order to prevent large amounts of current from flowing through the power amplifier due to load mismatch.
A system that limits current in the power amplifier must detect the current in the power amplifier. Thus, there remains a need for current detection circuitry that detects the current in the power amplifier and that does not substantially affect the efficiency of the power amplifier.
SUMMARY OF THE INVENTION
The present invention provides a system for detecting current in an output stage of power amplifier circuitry in a transmitter of a mobile terminal. In general, the mobile terminal includes power amplifier circuitry, power control circuitry, current detection circuitry, and an inductor that essentially prevents radio frequency coupling between the power control circuitry and the power amplifier circuitry. Based on a voltage across the inductor, the current detection circuitry generates a voltage detection signal indicative of a current in the inductor and thus the current in an output stage of the power amplifier.
The power amplifier circuitry operates to amplify a transmit signal based on a supply voltage generated by the power control circuitry. The power control circuitry generates the supply voltage based on a source voltage and an adjustable power control signal from the control system. The adjustable power control signal selects a power level of the power amplifier circuitry and may, in one embodiment, be used to control amplitude modulation of the transmit signal by the power amplifier circuitry. In one embodiment, the current detection circuitry operates to provide the voltage detection signal that is indicative of the current in the output stage of the power amplifier circuitry to a control system of the mobile terminal. The control system may then determine the current in the output stage of the power amplifier and operate to provide the adjustable power control signal such that the current in the output stage of the power amplifier is limited to a predetermined threshold value.
Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.



BRIEF DESCRIPTION OF THE DRAWING FIGURES
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.
FIG. 1 illustrates a mobile terminal having power control and current detection circuitry according to one embodiment of the present invention;
FIG. 2 illustrates the current detection circuitry for detecting the current in power amplifier circuitry based on sensing a voltage across a feed inductor between the power control circuitry and the power amplifier circuitry according to one embodiment of the present invention;
FIG. 3A is a detailed illustration of one embodiment of the power amplifier circuitry, the power control circuitry, and the current detection circuitry of FIG. 2;
FIG. 3B is a detailed illustration of another embodiment of the power amplifier circuitry, the power control circuitry, and the current detection circuitry of FIG. 3A;
FIG. 4 is another embodiment of the power amplifier circuitry, the power control circuitry, and the current detection circuitry according to the present invention;
FIG. 5 is a flow chart illustrating a current limiting scheme for limiting current in the power amplifier circuitry of the mobile terminal of FIG. 1 according to one embodiment of the present invention; and
FIG. 6 illustrates an exemplary method for determining error correction values for limiting the current of the power amplifier circuitry for a power level in real-time during ramp-up for a transmit burst according to one embodiment of the present invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
With reference to FIG. 1, the present invention is preferably incorporated in a mobile terminal 10, such as a mobile telephone, personal digital assistant, or the like. The basic architecture of the mobile terminal 10 may include a receiver front end 12, a radio frequency transmitter section 14, an antenna 16, a duplexer or switch 18, a baseband processor 20, a control system 22, a frequency synthesizer 24, and an interface 26. The receiver front end 12 receives information bearing radio frequency signals from one or more remote transmitters provided by a base station. A low noise amplifier 28 amplifies the signal. A filter circuit 30 minimizes broadband interference in the received signal, while a downconverter 32 downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams. The receiver front end 12 typically uses one or more mixing frequencies generated by the frequency synthesizer 24.
On the transmit side, the baseband processor 20 receives digitized data from the control system 22, which it encodes for transmission. The encoded data is output to the radio frequency transmitter section 14, where it is used by a modulator 34 to modulate a carrier signal from the frequency synthesizer 24 that is at a desired transmit frequency. Power amplifier circuitry 36 amplifies the modulated carrier signal to a level appropriate for transmission from the antenna 16.
As described in further detail below, the power amplifier circuitry 36 provides gain for the signal to be transmitted under control of the power control and current detection circuitry 38, which is preferably controlled by the control system 22 using an adjustable power control signal (VRAMP). Preferably, the bias for the power amplifier circuitry 36 is relatively stable regardless of power, and varying the voltage supplied to the power amplifier circuitry 36 controls actual power levels. The control system 22 may also provide a transmit enable signal (TX ENABLE) to effectively turn the power amplifier circuitry 36 and power control and current detection circuitry 38 on during periods of transmission. Further, according to the present invention, the power control and current detection circuitry 38 provides a detection signal (VDET) to the control system 22 that is indicative of a current through an output stage of the power amplifier circuitry 36. It should be noted that the detection signal (VDET) is described herein as a voltage detection signal. Alternatively, the detection signal (VDET) may be a current signal detection signal.
A user interacts with the mobile terminal 10 via the interface 26, which may include interface circuitry 40 associated with a microphone 42, a speaker 44, a keypad 46, and a display 48. The interface circuitry 40 typically includes analog-to-digital converters, digital-to-analog converters, amplifiers, and the like. Additionally, it may include a voice encoder/decoder, in which case it may communicate directly with the baseband processor 20.
The microphone 42 will typically convert audio input, such as the user's voice, into an electrical signal, which is then digitized and passed directly or indirectly to the baseband processor 20. Audio information encoded in the received signal is recovered by the baseband processor 20, and converted into an analog signal suitable for driving speaker 44 by the I/O and interface circuitry 40. The keypad 46 and display 48 enable the user to interact with the mobile terminal 10, input numbers to be dialed, add or view address book information, or the like, as well as monitor call progress information.
Turning now to FIG. 2, the power amplifier circuitry 36 is associated with the power control and current detection circuitry 38. According to one embodiment of the present invention, the power control and current detection circuitry 38 includes power control circuitry 50, current detection circuitry 52, and an inductor 54. The power control circuitry 50 operates to provide a supply voltage (VCC) based on a source voltage (VBAT), the adjustable power control signal (VRAMP), and a transmitter control signal (TX ENABLE). The current detection circuitry 52 operates to measure a voltage across the inductor 54, which is indicative of a current in the power amplifier circuitry 36, and generate the detection signal (VDET) based on the voltage across the inductor 54. The inductor 54 also operates as a DC feed inductor that allows only DC current to flow between the power control circuitry 50 and power amplifier circuitry 36. The inductor 54 is preferably configured to ensure that essentially no radio frequency components are coupled between the power amplifier circuitry 36 and the power control circuitry 50. Further, the inductor 54 has an inductance L and a small inherent resistance. The inductance L is selected such that only the supply voltage VCC, which is a DC voltage, is coupled between the power amplifier circuitry 36 and the power control circuitry 50.
As indicated, the current in the power amplifier circuitry 36 is based on the voltage across the inductor 54, which is a desirable component that improves the performance of the power amplifier circuitry 36. Accordingly, the present invention avoids the need to place additional, undesirable resistive components between the source voltage (VBAT) and the power amplifier circuitry 36. Further, by avoiding the need for additional resistive components between the source voltage (VBAT) and the power amplifier circuitry 36, the present invention also avoids reducing the overall efficiency of the power amplifier circuitry 36 due to the additional resistive components.
FIG. 3A is a more detailed illustration of one embodiment of the power amplifier circuitry 36, the power control circuitry 50, and the current detection circuitry 52. In this embodiment, the power amplifier circuitry 36 includes three amplifier stages, a first amplifier stage 56, a second amplifier stage 58, and a third amplifier stage 60, as well as a bias network 62 providing bias for each of the three amplifier stages 56, 58, and 60.
The rail 64 of first amplifier stage 56 is connected directly to a fixed voltage such as the source voltage (VBAT). The source voltage (VBAT) may be a voltage supplied by the positive potential of a battery. As noted, the bias network 62 preferably supplies a fixed bias to the three power amplifier stages 56, 58, 60, regardless of the collector/drain voltage supplied to the second and third amplifier stages 58, 60. The fixed bias incorporates traditional VAPC signals, which are configured to maintain a constant bias.
The power control circuitry 50 includes an error amplifier 66, a voltage regulator 68, and a feedback network 70. In the illustrated embodiment, the voltage regulator 68 is a PFET transistor. However, other embodiments of the voltage regulator 68 will be apparent to one of ordinary skill in the art. An input terminal 72 of the voltage regulator is connected to the source voltage (VBAT). The adjustable power control signal (VRAMP) is received by a negative input 74 of an operational amplifier forming the error amplifier 66. The output 76 of the voltage regulator 68 is fed back through the feedback network 70 and received by positive input 78 of the error amplifier 66. An output signal 80 from the error amplifier 66 is provided to a control input 82 of the voltage regulator 68 that controls the supply voltage (VCC) at the regulated output 76 of voltage regulator 68. The voltage regulator 68 regulates the supply voltage (VCC) supplied to the rails 84, 86 of the second and third amplifier stages 58, 60, respectively. These rails 84, 86 will typically be the collectors or drains of bipolar or field effect transistors forming the respective amplifier stages, as will be appreciated by those skilled in the art.
The transmitter control signal (TX ENABLE) is a logic signal used to simultaneously enable or disable the power control circuitry 50 by disabling the error amplifier 66 and the power amplifier circuitry 36 by removing the bias from each of the three amplifier stages 56, 58, 60. A radio frequency signal to be amplified (RFIN) is provided at the input 88 of the first stage amplifier 56 and amplified by the three amplifier stages 56, 58, 60 to provide an amplified output signal 90 (RFOUT) from the third amplifier stage 60.
According to one embodiment of the present invention, the current detection circuitry 52 operates to generate the detection signal (VDET) based on the voltage across the inductor 54. In this embodiment, the current detection circuitry 52 includes a differential amplifier 92 and an analog-to-digital (A/D) converter 93. It should be noted that the A/D converter 93 is an optional component and that the detection signal (VDET) may be provided to the control system 22 as an analog signal. In this embodiment, the differential amplifier 92 is an operational amplifier. A positive terminal 94 of the differential amplifier 92 is coupled to an input terminal of the inductor 54 via resistor R1. A negative terminal 96 of the differential amplifier 92 is coupled to an output terminal of the inductor 54 via resistors R2 and R3. The resistor R1 and capacitor C1 form a low pass filter that operates to filter any high frequency components from the voltage at the input terminal of the inductor 54 such that only the DC component of the voltage is provided to the positive terminal 94. The resistor R2 and capacitor C2 form another low pass filter that operates to filter any high frequency components from the voltage at the output terminal of the inductor 54 such that only the DC component of the voltage is provided to the negative terminal 96. The resistor R3 and resistor R4 along with capacitor C3 provide additional low-pass filtering of the voltage from the output terminal of the inductor 54. Resistor R5 is selected such that the differential amplifier 92 provides a desired gain.
In operation, the power control circuitry 50 provides the supply voltage (Vcc) based on the adjustable power control signal (VRAMP) and the source voltage (VBAT). The supply voltage generates a current (ICC) through the inductor 54. Since the inductor 54 includes a small amount of inherent resistance, a voltage drop occurs across the inductor 54. Based on the voltage across the inductor 54, the differential amplifier 92 generates the detection signal (VDET), which is indicative of the current ICC in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36. More specifically, the differential amplifier 92 amplifies the voltage across the inductor 54 to provide the detection signal (VDET).
It should also be noted that when fabricating the power control and current detection circuitry 38 and the power amplifier circuitry 36, the inductor 54 may be external to both the power control and current detection circuitry 38 and the power amplifier circuitry 36. Accordingly, as illustrated in FIG. 3B, bond wires 97 may be used to couple the inductor 54 to the power control and current detection circuitry 38 and the power amplifier circuitry 36. Thus, in one embodiment of the present invention, the current detection circuitry 52 may alternatively measure the voltage across the two bond wires 97 and the inductor 54.
FIG. 4 illustrates the power control and current detection circuitry 38 according to another embodiment of the present invention. In this embodiment, the power control and current detection circuitry 38 includes the power amplifier circuitry 36 and the power control circuitry 50 operating as described above and another embodiment of the current detection circuitry 52′. As described with respect to FIGS. 3A and 3B, in one embodiment, the power amplifier circuitry 36 includes the first amplifier stage 56, the second amplifier stage 58, and the third amplifier stage 60, as well as the bias network 62 for providing bias for each of the three amplifier stages 56, 58, and 60.
The power control circuitry 50 includes the error amplifier 66, the voltage regulator 68, and the feedback network 70. In operation, the voltage regulator 68 regulates the supply voltage (VCC) supplied to the rails 84, 86 of the second and third amplifier stages 58, 60, respectively, based on the source voltage (VBAT) and the adjustable power control signal (VRAMP). The rails 84, 86 will typically be the collectors or drains of bipolar or field effect transistors forming the respective amplifier stages, as will be appreciated by those skilled in the art.
The transmitter control signal (TX ENABLE) is a logic signal used to enable or disable the power amplifier circuitry 36 and the power control circuitry 50, as described above. The radio frequency signal to be amplified (RFIN) is provided at the input 88 of the first stage amplifier 56 and amplified by the three amplifier stages 56, 58, 60 to provide the amplified output signal 90 (RFOUT) from the third amplifier stage 60.
The current detection circuitry 52′ operates to generate the detection signal (VDET) based on a voltage across a resistor 98 and an inductor 100 coupled between the source voltage (VBAT) and the voltage regulator 68. The voltage across the resistor 98 and the inductor 100 is indicative of the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36. In one embodiment, the resistor 98 and the inductor 100 represent a resistance and inductance of a bond wire used to connect a positive terminal of a battery providing the source voltage (VBAT) to a lead on a semiconductor die including the power control circuitry 50. In another embodiment, the resistor 98 and the inductor 100 are elements placed between the positive terminal of a battery providing the source voltage (VBAT) and the voltage regulator 68.
As illustrated, the current detection circuitry 52′ includes an analog-to-digital (A/D) converter 102, a reference current source 104, a reference resistor 106, and switching circuitry 108. In general, the A/D converter 102 is a differential A/D converter and operates to measure, or digitize, the voltage across the resistor 98 and the inductor 100. In the embodiment where the resistor 98 and the inductor 100 are the resistance and inductance of a bond wire, the resistance is typically 10-20 mΩ. In other embodiments, the resistance of the resistor 98 is desirably small to reduce losses. Thus, for a one or two ampere current, the voltage across the resistor 98 may be in the range of 10-40 mV.
In order to accurately measure small voltages across the resistor 98 and the inductor 100, it may be desirable to calibrate the A/D converter 102 using a reference voltage (VREF) to compensate for offset and gain drifts. In this embodiment, the reference voltage (VREF) is generated by the reference current source 104 and the reference resistor 106. In one embodiment, the A/D converter 102 operates to perform self-calibration based on the reference voltage (VREF). In another embodiment, calibration is performed by digitizing the reference voltage (VREF) and providing the digitized reference voltage (VREF) to the control system 22 (FIG. 1). The control system 22 then operates to calculate a correction value based on the actual digitized reference voltage (VREF) and an ideal value of the digitized reference voltage (VREF). Thereafter, the control system 22 uses the correction value to correct the output of the A/D converter 102.
The switching circuitry 108 operates to provide the reference voltage (VREF) or a sense voltage (VSENSE) to the A/D converter 102. During calibration, the switching circuitry 108 provides the reference voltage (VREF) to the A/D converter 102. When it is desirable to measure the current through the resistor 98 and inductor 100, the switching circuitry 108 provides the sense voltage (VSENSE) to the A/D converter 102. The operation of the switching circuitry 108 may be controlled by the control system 22.
Referring to FIGS. 2, 3A, 3B, and 4, the detection signal (VDET) is indicative of the current in the power amplifier circuitry 36. As mention above, the control system 22 (FIG. 1) may use the detection signal (VDET) to limit the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 according to one embodiment of the present invention. However, it should be noted that the detection signal (VDET) may be used by the control system 22 for various other reasons as will be apparent to one of ordinary skill in the art after reading this disclosure.
FIG. 5 is a flow chart illustrating the operation of the control system 22 (FIG. 1) to limit the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 according to one embodiment of the present invention. Prior to discussing the details of the operation of the control system 22, it may be beneficial to mathematically describe the operation of the control system 22 in limiting the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 based on determining error correction values for each value of the adjustable power control signal (VRAMP).
The control system 22 operates to provide the adjustable power control signal (VRAMP) such that the signal (VRAMP) can have any one of a number of values. Each value of the signal (VRAMP) corresponds to one of a number of power levels for the power amplifier circuitry 36. The value of the signal (VRAMP) is selected by the control system 22 based on the desired power level of the power amplifier circuitry 36, which corresponds to the output power of the mobile terminal 10. The ideal values of VRAMP (VRAMP,IDEAL) for the number of power levels can be described as:




  
    
      V
      
        RAMP
        ,
        IDEAL
      
    
    =
    
      {
      
        
          
            1
          
          
            762
          
        
        
          
            2
          
          
            608
          
        
        
          
            3
          
          
            494
          
        
        
          
            ⋮
          
          
            ⋮
          
        
        
          
            N
          
          
            88
          
        
      
      }
    
  
  ,




where the first column defines the number (N) of different power levels for the power amplifier circuitry 36 and the second column gives exemplary 10-bit decimal values of VRAMP,IDEAL corresponding to each power level.

Alternatively, the ideal values of VRAMP (VRAMP,IDEAL) may be expressed in matrix form to include ideal values of VRAMP during ramp-up and ramp-down including a peak value. It should be noted that the adjustable power control signal (VRAMP) is ramped-up from a minimum value, such as zero, to the peak value for the transmit burst prior to providing data to the power amplifier circuitry 36 for each transmit burst. Similarly, the power control signal (VRAMP) is ramped-down from the peak value to the minimum value at the end of each transmit burst. Accordingly, ideal values of VRAMP (VRAMP,IDEAL) may alternatively be expressed in matrix form as:




  
    
      V
      
        RAMP
        ,
        IDEAL
      
    
    =
    
      {
      
        
          
            1
          
          
            
              
                η
                1
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                1
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                1
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            762
          
        
        
          
            2
          
          
            
              
                η
                2
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                2
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                2
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            608
          
        
        
          
            3
          
          
            
              
                η
                3
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                3
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                3
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            494
          
        
        
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ...
          
          
            ⋮
          
        
        
          
            N
          
          
            
              
                η
                N
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                N
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                N
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            88
          
        
      
      }
    
  
  ,




where the values ηi(0), ηi(1), ηi(2), . . . are the ideal values of VRAMP during ramp-up, and, when reversed, are the ideal values of VRAMP during ramp-down. Each of the values ηi(0), ηi(1), ηi(2) corresponds to a time step during ramp-up or, when reversed, ramp-down. The values in the last column of the matrix are the peak values of VRAMP,IDEAL for each of the output power levels.

In either case, the ideal values (VRAMP,IDEAL) are the ideal values of VRAMP when the load at the antenna 16 is equal to the ideal load, which may be, for example, 50 ohms. It should be noted that the values of the ideal adjustable power control signal VRAMP,IDEAL corresponding to each power level are determined prior to step 500 of FIG. 5 and for purposes of the present invention are to be considered known values. According to the present invention, error correction values ε are determined for each power level and can be defined as:




  
    ɛ
    =
    
      {
      
        
          
            0
          
          
            170
          
        
        
          
            0
          
          
            28
          
        
        
          
            0
          
          
            0
          
        
        
          
            ⋮
          
          
            ⋮
          
        
        
          
            0
          
          
            0
          
        
      
      }
    
  
  ,




where the second column defines exemplary decimal values for the error correction values corresponding to each power level. Alternatively, where the ideal values of VRAMP include values during ramp-up and ramp-down, there may be a set of error correction values for each power level, and the error correction values ε can be defined as:





  
    ɛ
    =
    
      {
      
        
          
            0
          
          
            
              ɛ
              
                1
                ,
                1
              
            
          
          
            
              ɛ
              
                1
                ,
                2
              
            
          
          
            
              ɛ
              
                1
                ,
                3
              
            
          
          
            ...
          
          
            170
          
        
        
          
            0
          
          
            
              ɛ
              
                2
                ,
                1
              
            
          
          
            
              ɛ
              
                2
                ,
                2
              
            
          
          
            
              ɛ
              
                2
                ,
                3
              
            
          
          
            ...
          
          
            28
          
        
        
          
            0
          
          
            
              ɛ
              
                3
                ,
                1
              
            
          
          
            
              ɛ
              
                3
                ,
                2
              
            
          
          
            
              ɛ
              
                3
                ,
                3
              
            
          
          
            ...
          
          
            0
          
        
        
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ...
          
          
            ⋮
          
        
        
          
            0
          
          
            
              ɛ
              
                N
                ,
                1
              
            
          
          
            
              ɛ
              
                N
                ,
                2
              
            
          
          
            
              ɛ
              
                N
                ,
                3
              
            
          
          
            ...
          
          
            0
          
        
      
      }
    
  
  ,




where each row corresponds to a set of error correction values for a particular power level. Each of the error correction values corresponds to one of the ideal values for VRAMP above.

As described below in more detail, the adjustable power control signal VRAMP is a corrected version of the ideal adjustable power control signal VRAMP,IDEAL and is determined based on the ideal adjustable power control signal VRAMP,IDEAL and the error correction values ε. Thus, in this example, the adjustable power control signal VRAMP is defined as:

VRAMP=VRAMP,IDEAL−ε.

Thus, when VRAMP,IDEAL includes only the peak value for each power level, the adjustable power control signal VRAMP is defined as:





  
    V
    RAMP
  
  =
  
    
      
        {
        
          
            
              1
            
            
              762
            
          
          
            
              2
            
            
              608
            
          
          
            
              3
            
            
              494
            
          
          
            
              ⋮
            
            
              ⋮
            
          
          
            
              N
            
            
              88
            
          
        
        }
      
      -
      
        {
        
          
            
              0
            
            
              170
            
          
          
            
              0
            
            
              28
            
          
          
            
              0
            
            
              0
            
          
          
            
              ⋮
            
            
              ⋮
            
          
          
            
              0
            
            
              0
            
          
        
        }
      
    
    =
    
      
        {
        
          
            
              1
            
            
              592
            
          
          
            
              2
            
            
              580
            
          
          
            
              3
            
            
              494
            
          
          
            
              ⋮
            
            
              ⋮
            
          
          
            
              N
            
            
              88
            
          
        
        }
      
      .
    
  




Alternatively, when VRAMP,IDEAL includes values for ramp-up/ramp-down including the peak value for each power level, the adjustable power control signal VRAMP is defined as:





  
    
      
        
          V
          RAMP
        
        =
        
          
            {
            
              
                
                  1
                
                
                  
                    
                      η
                      1
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      1
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      1
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  762
                
              
              
                
                  2
                
                
                  
                    
                      η
                      2
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      2
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      2
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  608
                
              
              
                
                  3
                
                
                  
                    
                      η
                      3
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      3
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      3
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  494
                
              
              
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ...
                
                
                  ⋮
                
              
              
                
                  N
                
                
                  
                    
                      η
                      N
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      N
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      N
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  88
                
              
            
            }
          
          -
          
            {
            
              
                
                  0
                
                
                  
                    ɛ
                    
                      1
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      1
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      1
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  170
                
              
              
                
                  0
                
                
                  
                    ɛ
                    
                      2
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      2
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      2
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  28
                
              
              
                
                  0
                
                
                  
                    ɛ
                    
                      3
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      3
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      3
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  0
                
              
              
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ...
                
                
                  ⋮
                
              
              
                
                  0
                
                
                  
                    ɛ
                    
                      N
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      N
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      N
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  0
                
              
            
            }
          
        
      
      ⁢
      
        

      
      ⁢
      
        
          V
          RAMP
        
        =
      
    
     
  
  ⁢
  
     
    
      
        {
        
          
            
              1
            
            
              
                
                  
                    η
                    1
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    1
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    1
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
                -
                
                  ɛ
                  
                    1
                    ,
                    2
                  
                
              
            
            
              
                
                  
                    η
                    1
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
                -
                
                  ɛ
                  
                    1
                    ,
                    3
                  
                
              
            
            
              ...
            
            
              592
            
          
          
            
              2
            
            
              
                
                  
                    η
                    2
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    2
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    2
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
                -
                
                  ɛ
                  
                    2
                    ,
                    2
                  
                
              
            
            
              
                
                  
                    η
                    2
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
                -
                
                  ɛ
                  
                    2
                    ,
                    3
                  
                
              
            
            
              ...
            
            
              580
            
          
          
            
              3
            
            
              
                
                  
                    η
                    3
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    3
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    3
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
                -
                
                  ɛ
                  
                    3
                    ,
                    2
                  
                
              
            
            
              
                
                  
                    η
                    3
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
                -
                
                  ɛ
                  
                    3
                    ,
                    2
                  
                
              
            
            
              ...
            
            
              494
            
          
          
            
              ⋮
            
            
              ⋮
            
            
              ⋮
            
            
              ⋮
            
            
              ...
            
            
              ⋮
            
          
          
            
              N
            
            
              
                
                  
                    η
                    N
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    N
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    N
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
                -
                
                  ɛ
                  
                    N
                    ,
                    2
                  
                
              
            
            
              
                
                  
                    η
                    N
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
                -
                
                  ɛ
                  
                    N
                    ,
                    3
                  
                
              
            
            
              ...
            
            
              88
            
          
        
        }
      
      ⁢
      
        
      
      ⁢
      
        
          {
          
            
              
                1
              
              
                592
              
            
            
              
                2
              
              
                580
              
            
            
              
                3
              
              
                494
              
            
            
              
                ⋮
              
              
                ⋮
              
            
            
              
                N
              
              
                88
              
            
          
          }
        
        .
      
    
  




Returning to FIG. 5, the control system 22 operates to receive the signal (VDET) indicative of the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 for a particular value of the adjustable power control signal (VRAMP). During a transmission burst by the mobile terminal 10, the control system 22 determines the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 via the signal (VDET) (step 500). The control system 22 determines the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 based on the detection signal (VDET) and known values of the inductor 54, the inductor 54 and bond wires 97, or the resistor 98 and inductor 100 depending on the embodiment of the current detection circuitry 52 or 52′.
If the mobile terminal 10 is operating in a mode where the power amplifier circuitry 36 operates to control the output power of the mobile terminal 10, such as when the mobile terminal 10 is operating according to the GSM standard, the current is determined based on the signal (VDET) generated by the current detection circuitry 52 or 52′ at essentially any point during the transmit burst. Also, if the power amplifier circuitry 36 operates to provide amplitude modulation, such as when the mobile terminal 10 is operating according to the EDGE standard, the current may be determined based on the signal (VDET) generated by the current detection circuitry 52 or 52′ at any point during the transmit burst using a known relationship between the output power and the adjustable power control signal (VRAMP). Alternatively, the current may be determined based on the signal (VDET) generated by the current detection circuitry 52 or 52′ at a point during the transmit burst when it is known that the amplitude modulation is essentially zero. As another alternative, the current may be determined at numerous points during the transmit burst and time averaged to provide an average current.
If the current (I) in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 exceeds a predetermined threshold (step 502), the control system 22 determines the error correction value ε (step 504) for the corresponding value of the signal (VRAMP), and thus the corresponding power level and, optionally, time step during ramp-up or ramp-down, based on a difference between the sampled current and the predetermined current threshold. More specifically, the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 is defined by the current versus adjustable power control signal characteristic:

I(t)=aVRAMP,IDEAL(t)+K, 

where “a” is a known value that is essentially equal to a change in the current I with respect to a change in the ideal adjustable power control signal VRAMP,IDEAL when the load at the antenna 16 is at its ideal value. Thus, the term “a” is the slope, or derivative, of the current versus adjustable power control signal characteristic. K is a constant essentially equal to the current I when VRAMP,IDEAL is zero.

The error correction value ε for the particular value of VRAMP is defined as:

ε=εPREV+εCURRENT, where

εCURRENT=(I−ITHRESHOLD)/a, such that

ε=εPREV+(I−ITHRESHOLD)/a, 

where εPREV is a previous value of the error correction value for the particular value of VRAMP and ITHRESHOLD is the predetermined threshold value. It should be noted that when the load at the antenna is not equal to its ideal value, the actual value of a, or the change in the current per change in the signal VRAMP, may be different than its ideal value used to calculate the error correction value ε. Accordingly, more than one iteration of the method of FIG. 5 may be required to determine an optimum error correction value ε.

Based on the error correction value E and the ideal value VRAMP,IDEAL, the corrected adjustable power control signal (VRAMP) is determined prior to the next transmission by the mobile terminal 10 (step 506). As described above, the signal VRAMP is determined based on subtracting the error correction value ε from the corresponding value of VRAMP,IDEAL. The corrected adjustable power control signal (VRAMP) is a value of the signal VRAMP that would have limited the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 to the predetermined threshold in the transmission burst of step 500. The corrected VRAMP value is provided to the power control circuitry 50 during the next transmission burst at the corresponding power level (step 508).
It should be noted that where there is a set of error correction values for each power level, step 500 may occur during ramp-up, ramp-down, or any other point during the transmit burst. Then, step 504 may determine each of the set of error correction values for the power level based on the detection signal (VDET) and the threshold value, where there may be different threshold values for each time step during ramp-up and ramp-down. Similarly, step 506 determines corrected values for VRAMP for ramp-up, ramp-down, and the peak value of VRAMP for the power level, and step 508 provides the corrected values of VRAMP for the next transmit burst.
If the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 does not exceed the predetermined threshold value (step 502), and a current error correction value for the corresponding value of VRAMP is zero (step 510), then steps 504 and 508 may be skipped, and the control system may return to step 500. If the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 does not exceed the predetermined threshold value (step 502), and a current error correction value for the corresponding value of VRAMP is not equal to zero (step 510), then the control system 22 proceeds to step 504. The process is repeated for each transmit burst by the mobile terminal 10.
As an example, assume that the power amplifier circuitry 36 has 5 power levels and the ideal adjustable power control signal VRAMP,IDEAL for each of the power levels is:




  
    V
    
      RAMP
      ,
      IDEAL
    
  
  =
  
    
      {
      
        
          
            1
          
          
            762
          
        
        
          
            2
          
          
            608
          
        
        
          
            3
          
          
            494
          
        
        
          
            4
          
          
            409
          
        
        
          
            5
          
          
            336
          
        
      
      }
    
    .
  




Further assume that the current error correction values are:





  ɛ
  =
  
    
      {
      
        
          
            0
          
          
            170
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
      
      }
    
    .
  




If a transmit burst occurs at power level 2, the adjustable power control signal VRAMP during the transmit burst has the decimal value 608. The current detection circuitry 52 or 52′ provides the signal VDET that is indicative of the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36. The control system 22 determines the current in the second and third amplifier stages 58, 60 based on the signal VDET. Now assume that a=1.25, the current detected is 2A, and the predetermined threshold is 1.8A. According to the equation given above, the error correction value for the signal (VRAMP) at power level 2 is:

ε=εPREV+(I−ITHRESHOLD)/a=0+(2−1.8)/1.25=160 mV.

Using the equation:





  
    decimal_value
    =
    
      
        value
        *
        
          2
          B
        
      
      threshold_value
    
  
  ,




where B is the bit resolution of the A/D converter 102 (FIG. 4), the error correction value of 160 mV has a decimal value of 91 for 10-bit resolution. Accordingly, the new error correction values are:





  
    ɛ
    =
    
      {
      
        
          
            0
          
          
            170
          
        
        
          
            0
          
          
            91
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
      
      }
    
  
  ,




and the corrected adjustable power control signal VRAMP is:





  
    V
    RAMP
  
  =
  
    
      {
      
        
          
            1
          
          
            592
          
        
        
          
            2
          
          
            517
          
        
        
          
            3
          
          
            494
          
        
        
          
            4
          
          
            409
          
        
        
          
            5
          
          
            336
          
        
      
      }
    
    .
  




Thus, the next time a transmit burst occurs at power level 2, the adjustable power control signal VRAMP will have a decimal value of 517 rather than 608, thereby reducing the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 to essentially the predefined threshold value of 1.8A.

Now assume that a transmit burst occurs at power level 1, which corresponds to VRAMP having the decimal value 592. The current detection circuitry 52 or 52′ provides the signal VDET that is indicative of the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36. The control system 22 determines the current in the second and third amplifier stages 58, 60 based on the signal VDET. Now assume that a=1.25, the current is 1.7A, and the predetermined threshold is 1.8A, where the reduced current is due to a change in the load at the antenna 16. According to the equation given above, the error correction value for VRAMP at power level 1 is:

ε=εPREV+(I−ITHRESHOLD)/a=0.299+(1.7−1.8)/1.25=219 mV,

which has a decimal value of 125 using 10-bit resolution. The εPREV value of 0.299 is the base-10 value corresponding to the decimal value 592. Accordingly, the new error correction values are:





  
    ɛ
    =
    
      {
      
        
          
            0
          
          
            125
          
        
        
          
            0
          
          
            91
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
        
          
            0
          
          
            0
          
        
      
      }
    
  
  ,




and the corrected adjustable power control signal VRAMP is:





  
    V
    RAMP
  
  =
  
    
      {
      
        
          
            1
          
          
            637
          
        
        
          
            2
          
          
            517
          
        
        
          
            3
          
          
            494
          
        
        
          
            4
          
          
            409
          
        
        
          
            5
          
          
            336
          
        
      
      }
    
    .
  




Thus, the next time a transmit burst occurs at power level 1, the adjustable power control signal VRAMP will have a decimal value of 637 rather than 592, thereby increasing the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 to essentially the predefined threshold value of 1.8A. It should be noted that in respect to power level 1, this example has shown the operation of the control system 22 in determining the optimum error correction value ε for power level 1. Thus, the control system 22 operates to provide the optimum error correction value ε for each power level that limits the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 to the predetermined threshold value.

Although the example above determines only one error correction value and one corrected value of VRAMP for each power level, the method may determine the set of error correction values for each power level using a single value of the detection signal (VDET) for each power level or multiple values of the detection signal (VDET) for each power level.
FIG. 6 illustrates an exemplary method for determining the set of error correction values ε for a power level in real-time during ramp-up of the adjustable power control signal (VRAMP) for a transmit burst. Variations of this method will be apparent to one of ordinary skill in the art upon reading this disclosure. As stated above, in one embodiment, VRAMP,IDEAL can be defined as:




  
    
      V
      
        RAMP
        ,
        IDEAL
      
    
    =
    
      {
      
        
          
            1
          
          
            
              
                η
                1
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                1
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                1
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            762
          
        
        
          
            2
          
          
            
              
                η
                2
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                2
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                2
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            608
          
        
        
          
            3
          
          
            
              
                η
                3
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                3
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                3
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            494
          
        
        
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ...
          
          
            ⋮
          
        
        
          
            N
          
          
            
              
                η
                N
              
              ⁡
              
                (
                0
                )
              
            
          
          
            
              
                η
                N
              
              ⁡
              
                (
                1
                )
              
            
          
          
            
              
                η
                N
              
              ⁡
              
                (
                2
                )
              
            
          
          
            ...
          
          
            88
          
        
      
      }
    
  
  ,




where the last column of the matrix is merely exemplary. Also, the error correction values may be defined as:





  
    ɛ
    =
    
      {
      
        
          
            0
          
          
            
              ɛ
              
                1
                ,
                1
              
            
          
          
            
              ɛ
              
                1
                ,
                2
              
            
          
          
            
              ɛ
              
                1
                ,
                3
              
            
          
          
            ...
          
          
            170
          
        
        
          
            0
          
          
            
              ɛ
              
                2
                ,
                1
              
            
          
          
            
              ɛ
              
                2
                ,
                2
              
            
          
          
            
              ɛ
              
                2
                ,
                3
              
            
          
          
            ...
          
          
            28
          
        
        
          
            0
          
          
            
              ɛ
              
                3
                ,
                1
              
            
          
          
            
              ɛ
              
                3
                ,
                2
              
            
          
          
            
              ɛ
              
                3
                ,
                3
              
            
          
          
            ...
          
          
            0
          
        
        
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ⋮
          
          
            ...
          
          
            ⋮
          
        
        
          
            0
          
          
            
              ɛ
              
                N
                ,
                1
              
            
          
          
            
              ɛ
              
                N
                ,
                2
              
            
          
          
            
              ɛ
              
                N
                ,
                3
              
            
          
          
            ...
          
          
            0
          
        
      
      }
    
  
  ,




where again the last column of the matrix is exemplary. As such, the corrected VRAMP may be defined as:





  
    
      
        
          V
          RAMP
        
        =
        
          
            {
            
              
                
                  1
                
                
                  
                    
                      η
                      1
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      1
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      1
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  762
                
              
              
                
                  2
                
                
                  
                    
                      η
                      2
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      2
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      2
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  608
                
              
              
                
                  3
                
                
                  
                    
                      η
                      3
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      3
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      3
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  494
                
              
              
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ...
                
                
                  ⋮
                
              
              
                
                  N
                
                
                  
                    
                      η
                      N
                    
                    ⁡
                    
                      (
                      0
                      )
                    
                  
                
                
                  
                    
                      η
                      N
                    
                    ⁡
                    
                      (
                      1
                      )
                    
                  
                
                
                  
                    
                      η
                      N
                    
                    ⁡
                    
                      (
                      2
                      )
                    
                  
                
                
                  ...
                
                
                  88
                
              
            
            }
          
          -
          
            {
            
              
                
                  0
                
                
                  
                    ɛ
                    
                      1
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      1
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      1
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  170
                
              
              
                
                  0
                
                
                  
                    ɛ
                    
                      2
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      2
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      2
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  28
                
              
              
                
                  0
                
                
                  
                    ɛ
                    
                      3
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      3
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      3
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  0
                
              
              
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ⋮
                
                
                  ...
                
                
                  ⋮
                
              
              
                
                  0
                
                
                  
                    ɛ
                    
                      N
                      ,
                      1
                    
                  
                
                
                  
                    ɛ
                    
                      N
                      ,
                      2
                    
                  
                
                
                  
                    ɛ
                    
                      N
                      ,
                      3
                    
                  
                
                
                  ...
                
                
                  0
                
              
            
            }
          
        
      
      ⁢
      
        

      
      ⁢
      
        
          V
          RAMP
        
        =
      
    
     
  
  ⁢
  
     
    
      
        {
        
          
            
              1
            
            
              
                
                  
                    η
                    1
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    1
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    1
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
                -
                
                  ɛ
                  
                    1
                    ,
                    2
                  
                
              
            
            
              
                
                  
                    η
                    1
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
                -
                
                  ɛ
                  
                    1
                    ,
                    3
                  
                
              
            
            
              ...
            
            
              592
            
          
          
            
              2
            
            
              
                
                  
                    η
                    2
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    2
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    2
                  
                  ⁡
                  
                    (
                    1
                    )
                  
                
                -
                
                  ɛ
                  
                    2
                    ,
                    2
                  
                
              
            
            
              
                
                  
                    η
                    2
                  
                  ⁡
                  
                    (
                    2
                    )
                  
                
                -
                
                  ɛ
                  
                    2
                    ,
                    3
                  
                
              
            
            
              ...
            
            
              580
            
          
          
            
              3
            
            
              
                
                  
                    η
                    3
                  
                  ⁡
                  
                    (
                    0
                    )
                  
                
                -
                
                  ɛ
                  
                    3
                    ,
                    1
                  
                
              
            
            
              
                
                  
                    η
                    3
                  
                  ⁡
                  
                    (
                    1
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      ⁢
      
        
      
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        {
        
          
            
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It should be noted that the second column of these matrices is referred to as time step 0 during ramp-up, the third column is referred to as time step 1 during ramp-up, etc.

According to one embodiment of the present invention, the set of error correction values for any particular power level may be determined in real-time during ramp-up for a transmit burst. First, the control system 22 determines the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36 via the signal (VDET) at a predetermined time during ramp-up (step 600). The predetermined time may be any time step during ramp-up, such as time step 0 or time step 8, for example. It should be noted that the threshold value may be different for each time step.
If the detected current is greater than the threshold value, then the error correction value for the current time step is determined (step 604). Then, the error correction value determined in step 604 is used as the error correction value for the next time step in order to provide the corrected VRAMP for the next time step (step 606). The current is then determined for the next time step (step 608), and the process returns to step 602 where the detected current is compared to a threshold value for that time step. If the detected current is greater than the threshold, then the process proceeds to step 604 where the error correction value for the current time step is determined. It should be noted that the error correction value for the current time step is equal to the error correction value for the previous time step plus the current error correction value. Steps 602-608 are repeated until ramp-up is complete and the detected current no longer exceeds the threshold value (step 610). Alternatively, the process may end as soon as the detected current is no longer greater than the threshold.
As an example, assume that there are 16 time steps (time step 0-time step 15), and that the predetermined time is time step 8. It should be noted that time steps 0-14 define ramp-up, and time step 15 defines the time at which ramp-up is complete, which is the time at which VRAMP is equal to its peak value. The process begins by determining the current at time step 8 (step 600). Next, the detected current is compared to a threshold value for time step 8 (step 602). Assume that the detected current is greater than the threshold value, such that the process determines an error correction value ε for time step 8. Next, the error correction value ε for time step 8 is used to provide the corrected VRAMP for time step 9. Thus, at time step 9, VRAMP is provided using the error correction value ε for time step 8. The process then determines the current at time step 9 (step 608), and compares the detected current to a threshold value for time step 9 (step 602).
Steps 602, 604, 606, and 608 are repeatedly performed for time steps 9-15. However, if at any time the detected current no longer exceeds the threshold, then the process may stop (step 610), and the error correction values for the remaining time steps can be set equal to the error correction value for the last processed time step. For example, if error correction values are determined for time steps 8-13 and at time step 14 the detected current is not greater than the threshold for time step 14, then the error correction values for time steps 14-16 can be set equal to the error correction value for time step 13.
The current detection circuits 52 and 52′ and the current limiting scheme of the present invention provide substantial opportunity for variation without departing from the spirit or scope of the present invention. For example, although the current detection circuitry 52′ of FIG. 4 includes the reference current source 104 and the reference resistor 106 for calibration of the A/D converter 102, depending on the accuracy of the A/D converter 102 and the fabrication process used to fabricate the A/D converter, calibration may not be necessary. As another example, although the operation of the control system 22 with respect to FIG. 5 is described as using a single predetermined threshold value for all power levels, in an alternative embodiment, there may be a different threshold value for each of the power levels. As yet another example, although the examples above describe a single predetermined threshold value for all power levels, it should be noted that there may be a different threshold value for each of the power levels. As yet another example, the current detection circuitry 52 and 52′ may be interchanged such that the current detection circuitry 52 detects the current across the resistor 98 and the inductor 100 in one embodiment and the current detection circuitry 52′ detects the current across the inductor 54 in another embodiment. As yet another example, although a recursive adaptive approach is described above, other algorithms such as the Newton Raphson algorithm or a step control with forced threshold may be used to find the value for the adjustable power control signal (VRAMP) that prevents the current in the second and third amplifier stages 58, 60 of the power amplifier circuitry 36. As yet another example, the current detection circuitry 52 may be a mirror circuit, which is commonly known in the art, that mirrors the current through the voltage regulator 68 to provide the detection signal.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

## Claims

1. A mobile terminal comprising:
amplifier circuitry adapted to amplify a transmit signal based on a supply voltage;
power control circuitry adapted to provide the supply voltage based on a source voltage and an adjustable power control signal;
an inductor having a first terminal adapted to receive the supply voltage from the power control circuitry and a second terminal adapted to provide the supply voltage to the amplifier circuitry; and
current detection circuitry adapted to determine a voltage across the inductor and generate a voltage detection signal that is indicative of a current in the inductor and thus the current in the amplifier circuitry.

2. The mobile terminal of claim 1 wherein the inductor operates to essentially prevent coupling of high frequencies between the power control circuitry and the amplifier circuitry.

3. The mobile terminal of claim 1 wherein the current detection circuitry comprises a differential amplifier having a positive input coupled to a first terminal of the inductor and a negative input coupled to a second terminal of the inductor and adapted to amplify the voltage across the inductor to provide the voltage detection signal.

4. The mobile terminal of claim 3 wherein the current detection circuitry further comprises an analog-to-digital converter adapted to digitize the voltage detection signal and provide a digitized voltage detection signal to a control system of the mobile terminal.

5. The mobile terminal of claim 1 wherein the mobile terminal further comprises a first bond wire adapted to couple a first terminal of the inductor to the power control circuitry and a second bond wire adapted to couple a second terminal of the inductor to the amplifier circuitry, and the current detection circuitry is adapted to provide the voltage detection signal based on a voltage across the first bond wire, the inductive circuitry, and the second bond wire.

6. The mobile terminal of claim 1 wherein the current detection circuitry comprises a differential analog-to-digital converter adapted to measure the voltage across the inductor and provide the voltage detection signal as a digital signal.

7. The mobile terminal of claim 1 further comprising a control system adapted to determine the current in the amplifier circuitry based on the voltage detection signal and to adjust the adjustable power control signal based on the current in the amplifier circuitry such that the current is limited to a predefined threshold value.

8. A mobile terminal comprising:
means for amplifying a transmit signal based on a supply voltage;
means for providing the supply voltage based on a source voltage and an adjustable power control signal;
means for essentially preventing coupling of high frequencies between the means for amplifying and the means for providing the supply voltage; and
means for determining a voltage across the means for essentially preventing coupling of high frequencies between the means for amplifying and the means for providing the supply voltage and generating a voltage detection signal that is indicative of the current in the means for amplifying.

9. The mobile terminal of claim 1 wherein the means for determining the voltage and generating the voltage detection signal comprises a means for amplifying the voltage across the means for essentially preventing coupling of high frequencies between the means for amplifying and the means for providing the supply voltage to provide the voltage detection signal.

10. The mobile terminal of claim 9 wherein the determining the voltage and generating the voltage detection signal further comprises a means for digitizing the voltage detection signal and providing a digitized voltage detection signal.

11. The mobile terminal of claim 8 wherein the means for determining the voltage and generating the voltage detection signal comprises a means for digitizing the voltage across the means for essentially preventing coupling of high frequencies between the means for amplifying and the means for providing the supply voltage and providing the voltage detection signal as a digital signal.

12. The mobile terminal of claim 8 further comprising means for determining the current in the means for amplifying based on the voltage detection signal and adjusting the adjustable power control signal based on the current in the means for amplifying such that the current is limited to a predefined threshold value.