Third Amendment and Restatement of "S" Process Development Agreement




			
	 EXECUTION VERSION
	  	Exhibit 10.36

 Confidential Treatment Requested 
 under 17 C.F.R. §§ 200.80(b)(94), 
 200.83 and 240.24-b-2

 Third Amendment and Restatement of 
 “S” PROCESS DEVELOPMENT AGREEMENT 
 (effective as of December 28, 2002)

 between 
 INTERNATIONAL BUSINESS MACHINES CORP. 
 And 
 ADVANCED MICRO DEVICES, INC. 
 Confidential treatment has been requested for portions of this
exhibit. The copy filed herewith omits the information subject to the confidentiality request. Omissions are designated as ***. A complete version of this exhibit has been filed with the Securities and Exchange Commission. 
  

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 This Agreement is made effective as of the 28th day of December, 2002 (hereinafter referred to as the “Effective
Date”) by and between International Business Machines Corporation (“IBM”), incorporated under the laws of the State of New York, U.S.A. and having an office for the transaction of business at 2070 Route 52, Hopewell Junction, NY
12533, U.S.A, and Advanced Micro Devices having an office for the transaction of business at One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 “(AMD)”. IBM and AMD may be individually referred to herein as a “Party,” or
collectively as the “Parties.” 
 WHEREAS, IBM has been developing leading edge semiconductor manufacturing processes with Sony and Toshiba,
and the Parties hereto desire to continue to participate in development efforts under this Agreement; 
 WHEREAS, the Parties possess complementary
skills and know-how, which the Parties wish to contribute toward such process development; 
 WHEREAS, each Party agrees to provide certain personnel
and grant the other Parties certain technology licenses in support of such process development; 
 WHEREAS, through the use of such complementary
skills and know-how the Parties desire to achieve resource efficiencies and cost savings, and reduce the technical risk associated with the development of high end semiconductor processes in order to complete development of and put into production,
leading edge high end semiconductor manufacturing processes sooner than would be possible with any of the Parties acting independently; 
 NOW
THEREFORE, in consideration of the premises and mutual covenants contained herein, as well as for other good and valuable consideration, the receipt and sufficiency of which is hereby acknowledged, the Parties agree as follows. For avoidance of
doubt, the Agreement as defined below covers its subject matter after its Effective Date including matters provided for in the “S” Process Development Agreement (Effective as of December 28, 2002) as amended and restated on
September 15, 2004 and on August 22, 2005 and as set forth herein. 
 SECTION 1 – DEFINITIONS 
 Unless expressly defined and used with an initial capital letter in this Agreement, words shall have their normally accepted meanings. The headings contained in this
Agreement or in any exhibit, attachment or appendix hereto are for reference purposes only and shall not affect in any way the meaning or interpretation of this Agreement. The word “shall” is mandatory, the word “may” is
permissive, the word “or” is not exclusive, the words “includes” and “including” are not limiting, and the singular includes the plural. The following terms shall have the described meanings: 
 “Agreement” means the terms and conditions of this Third Amendment and Restatement of “S” Process Development Agreement together with any exhibits,
attachments and appendices hereto. 
 “AMD Bump Project Leader” means the individual, if any, appointed by AMD pursuant to Section 4.4 below.

  


			
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“AMD Project Leader” means the individual, if any, appointed by AMD pursuant to Section 4.5 below. 
 “AMD FMV” means a single AMD flash memory venture at any point in time, in which AMD has an ownership interest representing a right to participate in making
decisions for such flash memory venture (i.e. a shareholder’s right to vote), which is the lesser of (i) *** percent (***%) or (ii) the largest single owner, but not less than *** percent (***%) of such flash memory venture, and which
produces flash memory products, provided, that such entity shall be considered an AMD FMV only so long as such ownership exists. 
 “AMD High
Performance Integrated Circuit” means an Integrated Circuit manufactured using an AMD High Performance Process. 
 “AMD High Performance
Process” means any 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process which incorporates portions of High Performance Device Information, which AMD uses exclusively to produce the highest performing *** percent (***%) of
wafers manufactured in the applicable technology generation (e.g. 32nm, 22nm) in any given quarter. Performance will be determined by AMD’s AC and DC transistor performance data, wherein any disputes will be resolved by the Management
Committee. 
 “AMD Non-High Performance Integrated Circuit” means an Integrated Circuit manufactured using an AMD Non-High Performance Process.

 “AMD Non-High Performance Process” means AMD’s 32nm, 22nm or subsequent node CMOS semiconductor manufacturing processes used by AMD to
manufacture Semiconductor Products other than AMD High Performance Integrated Circuits. 
 “AMD Pre-T0 Project Leader” means the individual, if
any, appointed by AMD pursuant to Section 4.3 below. 
 “AMD Pre-T0 Steering Committee Member” means the individual appointed by AMD pursuant
to Section 4.2 below, to provide technical guidance to the Management Committee for the Pre-T0 Activities. 
 “ASIC Product” shall mean an SOI
Integrated Circuit or AMD High Performance Integrated Circuit that is not a Foundry Product and wherein all of the following conditions are met: (i) at least one of (a) the functional requirements, or (b) the design, for such SOI
Integrated Circuit or AMD High Performance Integrated Circuit product is provided to a Party from a Third Party; (ii) such Party participated in an aspect of the definition and design of such product; and (iii) such Party is contractually
bound to manufacture such product solely for, and to sell such product solely to, such Third Party or its distributor or other recipient solely for the benefit of such Third Party, provided that ASIC products shall not include SOI Integrated
Circuits or AMD High Performance Integrated Circuits in which the Party modifies its product designs to add or modify a feature or function required by the Third Party, such modifications comprising a change of less than *** percent (***%) of the
logical functions of the product, even if said product design is only made available to the Third Party. 
  

 ***Confidential Treatment Requested. 
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“Background Know-How” means methods, techniques, designs, structures, software, and specifications developed or acquired by a Party outside the performance
of the Process Development Projects, which such Party provides to the other Party for use in a Process Development Project pursuant to Section 3. Such Background Know-How shall not include, Packaging Technology, Mask Fabrication and Photoresist
Technology, Stand Alone Memory, SiGe Technology, Chip Designs or Post-Silicon Devices. 
 “BEOL” (Back End of Line) shall mean those aspects of
Background Know-How and Specific Results that are directed to methods and processes of interconnecting the source, gate, or drain electrodes of FET transistors formed on a wafer, including initial passivation of such FET transistors with a
dielectric, up to and including polyimide passivation and final via formation but not including Bump Technology and Packaging Technology. For the avoidance of doubt, “BEOL” shall not include local interconnects made of tungsten.

 “Bulk CMOS” means 90nm, 65nm and 45nm CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer. 

“Bulk CMOS Information” means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or
(ii) selected by IBM either for incorporation into an IBM Bulk CMOS process or otherwise pursuant to Section 3.4. For the avoidance of doubt, Bulk CMOS Information shall not include any eDRAM Technology derived from or used in CMOS 12SeD.

 “Bump Technology” means the technology associated with connecting an Integrated Circuit to a chip carrier including IBM’s collapsible chip
carrier connection (“C4”) interconnect technology as further defined in Exhibit A that is developed during the term if this Agreement for use with, but not limited to, the semiconductor process technologies also developed under this
Agreement. Bump Technology shall include the following process steps: bump limiting metallurgy deposition, photolithography, solder deposition, etching, solder reflow and cleaning, and non-solder interconnect technology. 
 “***” shall mean *** and its subsidiaries located in ***. 
 “***-AMD Manufacturing Facility” shall mean any facility for the manufacture of Integrated Circuits located in *** or Dresden, Germany and either owned entirely by *** and AMD or owned by ***, AMD and all of the remaining such
ownership interest is solely owned or controlled, directly or indirectly, by a government entity or one or more corporations, companies or other entities which are purely financial investors who are not engaged in the design, development,
manufacture, marketing or sale of Semiconductor Products. 
 “Chip Design(s)” means any design of one or more Integrated Circuits and/or
Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that “Chip Designs”
shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including


  

 ***Confidential Treatment Requested. 
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SRAM macro cells and eDRAM macros) as well as such test chips themselves used for the development work of the Process Development Projects unless
specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs (including eDRAM
macros) as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual.
For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project. 
 “CMOS 10S” means a 90 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further
defined in Exhibit A.1, attached hereto. 
 “CMOS 10SE” means a 90 nanometer CMOS logic fabrication process currently under development by IBM, the
development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 10S, as further defined in Exhibit A.2. 
 “CMOS 11S” means a 65 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further
defined in Exhibit A.3. 
 “CMOS 11S2” means a 65 nanometer CMOS logic fabrication process currently under development by IBM, the development of
which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 11S, as further defined in Exhibit A.4. 
 “CMOS
12S” means a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit
A.5. 
 “CMOS 12S2” means a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be
continued pursuant to this Agreement, which is a performance enhanced version of CMOS 12S, as further defined in Exhibit A.6. 
 “CMOS 12SeD” means
a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement. CMOS 12SeD is a version of CMOS 12S including eDRAM Technology, as further defined in Exhibit
A.15. 
 “CMOS 13S” means a 32 nanometer CMOS logic fabrication process researched and evaluated for feasibility in the Pre-T0 Activities and/or
thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.7. 
 “CMOS 13SeD” means a 32 nanometer CMOS logic
fabrication process currently under development by IBM, the development of which is intended to be continued pursuant to this Agreement. CMOS 13SeD is a version of CMOS 13S including eDRAM Technology. 
  


			
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“CMOS 13S2” means a 32 nanometer CMOS logic fabrication process, which is a performance enhanced version of CMOS13S, and which is researched and evaluated
for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.8. 
 “CMOS 14S” means a 22 nanometer CMOS logic fabrication process researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit
A.9. 
 “Designated Invention” means an Invention for which a patent application has been filed by one or more of the Parties pursuant to Sections
11.1 or 11.2. 
 “Derivative Process(es)” shall have the meaning ascribed to it in Section 8.1 
 “Development Facilities” means the (i) IBM Development Facilities and (ii) any other facilities agreed to by the Parties in writing. 
 “Embedded DRAM” or “eDRAM” means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access
memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the
same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders). 
 “eDRAM Licensed
Product” means Integrated Circuits that include Bulk CMOS Information, Industry Standard Information, High Performance Device Information, SOI Device Information, or any combination thereof, and eDRAM Technology, or any portion thereof, other
than Foundry Products. 
 “eDRAM Technology” means semiconductor fabrication processes, designs and design techniques specifically developed for or
directed to Embedded DRAM, regardless of the application to which it is applied. 
 “Foundry Company(ies)” means an entity having a majority of its
revenue arising from the sale of Integrated Circuits wherein all the following conditions are met: (i) the ***, or *** and/or ***, for such Integrated Circuit product are ***; (ii) ***; and (iii) *** is contractually bound to ***.
Foundry Company also includes any other entity that has as its ***, wherein at least *** percent (***%) of the ownership interest in such entity is held by a *** (as defined in the first sentence of this paragraph), and wherein such ***. 

“Foundry Product” shall mean an Integrated Circuit wherein all the following conditions are met: (i) the ***, or *** and/or ***, for such Integrated
Circuit product *** ***; (ii) *** of such product (except for providing standard design libraries, design enablement tools or other intellectual property to the Third Party to specifically assist with the design of the product); and
(iii) *** is contractually bound to ***. 
  

 ***Confidential Treatment Requested. 
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“High Performance Device Information” means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on
substrates, not including *** or ***. 
 “High Performance Integrated Circuit” means an Integrated Circuit manufactured in a 32nm, 22nm or
subsequent node CMOS semiconductor manufacturing process using High Performance Device Information. 
 “High Sensitivity Pre-T0 Information” shall
have the meaning ascribed to it in Section 8.18. 
 “IBM Bump Technology Project Leader” means the individual appointed by IBM pursuant to
section 4.4 below. 
 “IBM Development Facilities” means the (i) IBM 200mm or 300mm wafer process development facility used for conducting the
Process Development Projects; (ii) the IBM Thomas J. Watson Research Center: and (iii) any other IBM facilities agreed to by the Parties in writing. 
 “IBM Pre-T0 Activities” means the activities conducted by IBM on the CMOS 13S, CMOS 13S2 and CMOS 14S logic fabrication processes researched and evaluated for feasibility by IBM prior to the Commencement Date. 
 “IBM Pre-T0 Information” means all information and items developed or acquired by IBM pursuant to the IBM Pre-T0 Activities and delivered by IBM, in its sole
discretion, to the Pre-T0 Activities. 
 “IBM Pre-T0 Project Leader” means the individual appointed by IBM pursuant to Section 4.3, below, to
provide day-to-day oversight for the Pre-T0 Activities. 
 “IBM Project Leader” means the individual appointed by IBM pursuant to Section 4.5,
below, to provide day-to-day oversight for the Process Development Projects. 
 “IBM Pre-T0 Steering Committee Member” means the individual
appointed by IBM pursuant to Section 4.2, below, to provide technical guidance to the Management Committee for the Pre-T0 Activities. 
 “Industry
Standard CMOS” means a 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process for high volume foundry manufacturing of Semiconductor Products *** whose price and performance characteristics are similar to ***. 
 “Industry Standard Information” means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, or
(ii) applicable to Industry Standard CMOS and selected by IBM either for incorporation into an IBM Industry Standard CMOS process or otherwise selected pursuant to Section 3.4. For the avoidance of doubt, Industry Standard Information
shall not include any eDRAM Technology derived from or used in CMOS 13SeD. 
  

 ***Confidential Treatment Requested. 
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 “Integrated Circuit” means an integral unit formed on a semiconductor substrate including a plurality of
active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, “Integrated Circuit” shall include charge-coupled devices (“CCDs”). 
 “Invention” means any invention, discovery, design or improvement, conceived or first actually reduced to practice solely or jointly by one or more
Representatives of one or more of the Parties or their respective contractors during the term of this Agreement and in the performance of the Process Development Projects. 
 “Licensed Product” means Integrated Circuits that include Bulk CMOS Information, Industry Standard Information, High Performance Device Information (excluding eDRAM Technology), SOI Device Information
(excluding eDRAM Technology), or any combination thereof, other than Foundry Products. 
 “Lithography” shall mean those aspects of Background
Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and
qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such
photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in
the Process Development Projects. 
 “Management Committee” shall have the meaning ascribed to it in Section 4.1. 
 “Mask Fabrication and Photoresist Technology” shall mean any process, procedure, Proprietary Tools (e.g. the Niagara software developed by IBM), or hardware
tool used in the fabrication of photomasks, as well as the photomasks themselves, and/or the formulation and/or manufacture of photoresist; provided, however, that “Mask Fabrication and Photoresist Technology” shall not include Lithography
or the evaluation of photomasks or photoresists for use in the technologies developed and researched hereunder. 
 “Net Selling Price” for each
unit of a particular ASIC Product or wafers (only pursuant to Section 5.7) means the net revenue recorded by AMD (including Wholly Owned Subsidiaries and Related Subsidiaries of AMD) with respect to an ASIC Product or such wafers (only pursuant
to Section 5.7) less (a) shipping, (b) insurance, and (c) sales, value added, use or excise taxes, to the extent to which they are actually paid or allowed, and less allowances to the extent they are actually allowed. If ASIC
Products or such wafers (only pursuant to Section 5.7) are sold, leased or otherwise transferred in a higher level of assembly or in the course of a transaction that includes other products or services with no separate bona fide price to be
charged for the ASIC Products, the applicable Net Selling Price for the purpose of calculating royalties shall be the fair market value of the ASIC Product or such wafers (only pursuant to Section 5.7), but no less than the average Net Selling
Price of all such units of other ASIC Products or such wafers (only pursuant to Section 5.7) sold, leased, or otherwise transferred to a Third Party by AMD (and/or by Wholly Owned Subsidiaries and Related Subsidiaries of AMD), whichever the
case may be, during the preceding half year. 
  


			
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“Packaging Technology” means any process, procedure, software, or hardware tools used in the packaging of integrated circuit products into single-chip
packages, multi-chip packages, or any other higher levels of assembly,; provided, however “Packaging Technology” shall not include the formation of layers on a wafer up to and including the final via layer (referred to as LV, TV, or FV
level) and shall not include Bump Technology, but shall include any process, procedure, or practice subsequent to any such steps included in Bump Technology. 
 “Post-Silicon Devices” means transistors on substrates other than silicon or transistors with critical dimensions less than *** nm which are not *** or ***, unless otherwise set forth in this Agreement (e.g. Exhibit A.10, which
may be updated from time to time by the Parties). 
 “Pre-T0 Activities” means the IBM Pre-T0 Activities and the activities conducted on the CMOS
13S, CMOS 13S2 and CMOS 14S logic fabrication processes researched and evaluated for feasibility under this Agreement pursuant to the technical objectives, and the Pre-T0 In-Scope Technical Subjects, as further defined in Exhibit A and the schedule
set forth in Exhibit B. 
 “Pre-T0 Exit” means the point in time where development work begins on the Process Development Project. At this point in
the program the Management Committee has determined the Strategic Technology Objectives, Technology Implementation Options and the T-Bulk, T1 and T2 dates for the applicable technology. 
 “Pre-T0 In-Scope Technical Subjects” means the subjects listed in Exhibit A.10, as updated from time to time by agreement of the Management Committee. 
 “Pre-T0 Information” means the IBM Pre-T0 Information and all information and items developed or acquired pursuant to the Pre-T0 Activities. 
 “Pre-T0 Steering Committee” shall have the meaning ascribed in Section 4.2. 
 “Process Development Project(s)” means the CMOS 10S, CMOS 10SE, CMOS 11S, CMOS 11S2, CMOS 12S, CMOS 12S2, CMOS 12SeD, CMOS 13S, CMOS13 SeD, CMOS 13S2 and if its development is continued pursuant to this
Agreement, CMOS14S, development work and any Bump Technology development work conducted jointly by Representatives of the Parties pursuant to the terms and conditions of this Agreement, as more fully set forth in Section 3.1, below. 

“Project Leaders” means the IBM Project Leader and the AMD Project Leader. 
 “Proprietary Tools” means software (in source code form or in object code form), models and/or data, and other instrumentalities that are not commercially available and are either owned by a Party or under
which a Party has the right to grant royalty-free licenses, and that are used in Process Development Projects. 
  

 ***Confidential Treatment Requested. 
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 “Qualification” means the T2 date identified in the schedule for each Process Development Project, as set
forth in Exhibit B. 
 “Related Subsidiary” shall mean a corporation, company or other entity: 
  

	 	(a)	one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing
authority) are, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto; or 

  

	 	(b)	which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity one hundred percent
(100%) of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body,
managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto; 

 provided that in either case, such entity shall be considered a Related Subsidiary, and shall be entitled to retain the licenses and other benefits
provided by this Agreement to the Related Subsidiary, only so long as such ownership or control exists. 
 “Representative(s)” means, a
Party’s employees and employees of a Party’s Wholly Owned Subsidiaries. 
 “Semiconductor Product” means a component that contains an
Integrated Circuit on a single or multichip module that incorporates a means of connecting those Integrated Circuits with other electronic elements (active or passive) and/or means to make external electrical connections to such elements, but which
excludes any means for a user to operate the functions therein (e.g., buttons, switches, sensors). 
 “Server” means an electronic device
performing information processing functions that primarily provides shared applications, resources, information, or services to other systems or collections of systems or multiple end-users/clients through an internal or external communications
connection or network, or through the Internet and is designed to support either AIX or another UNIX operating system. 
 “Silicon-Germanium
Technology” or “SiGe Technology” means semiconductor fabrication processes and design techniques incorporating silicon and germanium layers, including those processes and design techniques for use in HEMTs, photodetectors, HBTs or any
other applications of bipolar transistors, provided, however, “SiGe Technology” shall not include strained silicon channel MOSFET or any mobility enhancement techniques for FETs techniques carried out on SOI Wafers or High Performance
Integrated Circuit wafers. Furthermore, “SiGe Technology” shall not include material and device learning out of “SiGe Technology” that is applicable to the items outlined in Exhibit A.10 of this Agreement under the
“FEOL” section of Pre-T0 In-Scope Technical Subjects. 
  


			
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 “Silicon-On-Insulator Wafer” or “SOI
Wafer” shall mean a, single-crystal silicon wafer bearing a horizontally-disposed isolating silicon dioxide (SiO2) layer, in turn bearing a single-crystal silicon layer or a polysilicon layer, which is separated from the underlying silicon by the silicon dioxide layer and in which one or more active or passive integrated circuit structures are
formed. 
 “SOI Device Information” means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created
on commercially available SOI Wafers other than Bulk CMOS or Industry Standard Information. 
 “SOI Integrated Circuit” shall mean an Integrated
Circuit fabricated utilizing SOI Device Information and built on SOI Wafers. 
 “Specific Results” shall mean information and items, other than i)
Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Stand Alone Memory, v) SiGe Technology, vi) Chip Designs, and vii) Post-Silicon Devices, developed and/or contributed to the Process Development
Projects by the Parties pursuant to the development work of the Process Development Projects as follows: 
 The documentation produced for the
Process Development Projects as set forth in Exhibit J attached hereto (“Documentation”); 
 All information and items resulting
from the Process Development Projects and results of the Pre-T0 Activities selected by the Management Committee for inclusion in the CMOS 13S, CMOS 13S2 or CMOS 14S process, including but not limited to methods, techniques, unit processes, process
flows, structures in silicon, test software, and specifications for equipment, chemicals, masks and consumables; 
 Any Background Know-How
provided to the Process Development Project(s) by a Party pursuant to Section 3, below. 
 “Stand Alone Memory” means Chip Designs and
fabrication processes specifically related to read only memory (ROM), dynamic random access memory (DRAM), programmable ROMs, magnetic RAM (MRAM), and ferroelectric RAM. For the avoidance of doubt, “Stand Alone Memory” shall not include
static RAM (SRAM) macros utilized in the Process Development Projects as test vehicles or elements of eDRAM Technology which are included in Specific Results. 
 “Subsidiary” means a corporation, company or other entity: 
  

	 	(a)	more than fifty percent (50%) of whose outstanding shares or securities (representing the right to vote for the election of directors or other managing authority) are, now or
hereafter, owned or controlled, directly or indirectly, by a Party hereto, or 

  

	 	(b)	 which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, but more than fifty percent




  


			
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(50%) of whose ownership interest representing the right to make the decisions for such corporation, company or other entity is now or hereafter, owned or
controlled, directly or indirectly, by a Party hereto, 


 provided that in either case such entity shall be considered a
Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Subsidiaries, only so long as such ownership or control exists. 
 “Technical Coordinators” means the individuals referred to in Section 4.7, below. 
 “Term” means
the period of time from the Effective Date and ending in accordance with the terms of Section 12.1. 
 “Test Site” means a device or circuit
evaluation site on a wafer. 
 “Third Party” or “Third Parties” means an entity or entities other than the Parties or their Wholly Owned
Subsidiaries or Related Subsidiaries. 
 “Wholly Owned Subsidiary” shall mean 1) a corporation, company or other entity: 
 (a) one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election
of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party; or 
 (b) which does
not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity but one hundred percent of whose ownership interest representing the right to (i) make the decisions
for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or
other entity is, now or hereafter, owned or controlled, directly or indirectly, by a Party; 
 provided that in either case such entity shall
be considered a Wholly Owned Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Wholly Owned Subsidiaries, only so long as such ownership or control exists; or 2) a corporation, company or other
entity: 
 (c) at least seventy five percent (75%) of whose outstanding shares or securities (such shares or securities representing the
right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party; or 
 (d) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity but at least seventy five percent (75%) of whose
ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or 

  


			
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otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated
association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by a Party 
 provided, that in either case
(c) or (d) above, (i) all of the remaining such ownership interest is solely owned or controlled, directly or indirectly, by one or more corporations, companies or other entities which are purely financial investors who are not
engaged in the design, development, manufacture, marketing or sale of Semiconductor Products, and (ii) such entity shall be considered a Wholly Owned Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this
Agreement to Wholly Owned Subsidiaries, only so long as such ownership or control exists. 
 SECTION 2 – IBM Development Facilities

  

	2.1	IBM has established the IBM Development Facilities, wherein its 200mm and 300mm wafer process development facility used for conducting the Process Development Projects is located in
East Fishkill, New York. 

  

	2.2	IBM shall be responsible for the operations of the IBM Development Facilities, including, but not limited to capacity, staffing, and capital purchases. Process Development Projects
shall be conducted primarily at the IBM Development Facilities and the Parties agree that the development work performed under this Agreement after Pre-T0 Exit will be conducted primarily in IBM’s 300mm East Fishkill Facility. In addition to
the IBM Development Facilities, IBM may utilize other facilities to conduct elements of the development work associated with the Process Development Projects. In addition, the Parties may mutually agree to utilize AMD development facilities for
specifically defined elements of the Process Development Projects. If the Management Committee members so agree, such agreement shall be documented in writing and signed by the Parties. 

  

	2.3	Should IBM desire, at its own discretion, that the Process Development Projects performed under this Agreement after Pre-T0 Exit be primarily conducted at facilities other than
IBM’s 300mm East Fishkill facility, it shall provide notice of such desire to AMD no later than one (1) year prior to the intended change. The Parties will meet to discuss and attempt to agree on such a move. If the Parties are unable to
reach agreement, the Management Committee shall negotiate a mutually agreeable reasonable wind down plan to terminate (for convenience and without liability to either Party) the development relationship set forth in this Agreement. In the event of
such termination, AMD shall be entitled to immediately exercise its rights in accordance with Section 8.9 below, with payment under Section 5.8.a or Section 5.8.b, as mutually agreed upon by the Parties at that time.


 SECTION 3 – SCOPE OF PROCESS DEVELOPMENT PROJECTS/OTHER PROJECTS 
  

	3.1	 The Parties agree to jointly develop semiconductor manufacturing process technology based on IBM’s “S” high performance technology roadmap on
commercially available wafers that meet the requirements set forth as “Strategic Technology Objectives” in 



  


			
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Exhibit A (hereinafter referred to as “Strategic Technology Objectives”) in accordance with the schedule set forth in Exhibit B (hereinafter
referred to as “Development Schedule”). The Parties agree that the process technology so developed, shall be high performance, leading edge technology and, to the extent consistent with the Strategic Technology Objectives, shall be cost
efficient. Any modification to such Strategic Technology Objectives or Development Schedule requires the mutual agreement of the Parties. For the avoidance of doubt, none of the Process Development Projects shall include the development of i)
Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Stand Alone Memory, v) SiGe Technology, vi) Chip Designs, or vii) Post-Silicon Devices. 


  

	3.2	The Parties agree that Exhibit A also sets forth the Pre-T0 In-Scope Technical Subjects and the potential technology implementation options for each Process Development Project. The
Parties shall work together to evaluate the various options available, including individual process module feasibility, integration, characterization and qualification. The goal of such evaluation is to agree on an integrated process technology that
meets the Strategic Technology Objectives. If the Project Leaders are unable to agree on a particular process module to be developed, or should they disagree as to the continued development of a process module that was previously selected, the
process module preferred by IBM shall be pursued in the applicable Process Development Project. 

  

	3.3	For information other than that developed by the Parties in a given Process Development Project to be considered Specific Results for that Project, including Background Know-How, it
must be either deliberately provided to the Process Development Projects by the owner of such information, or be evaluated by the Project Leaders, pursuant to Section 3.2, for possible use in a Process Development Project. In the event
such item of information is provided, and the Party owning such information notifies the Project Leaders within thirty (30) days after such owning Party’s disclosure or the initiation of such evaluation that such information should be
withdrawn, such owning Party may withdraw such information from use in the Process Development Projects and all such information in tangible form associated therewith shall be returned to such owning Party and such tangible information shall not
become Specific Results. In the event of such withdrawal, any non-tangible information related to such information retained in the minds of the non-owning Party’s employees shall be treated as Specific Results by the non-owning Parties. Absent
such notice and withdrawal within thirty (30) days, all information deliberately provided by the owner of such information or evaluated by the Project Leaders shall be treated as Specific Results. 

  

	 	3.3.1	Any issue as to whether information was deliberately provided to the Process Development Projects shall be resolved by the Project Leaders based on either of the following criteria:


  

	 	3.3.1.1	whether the information was deliberately exposed to the other Parties by a Representative of the owner of such information; or 

  


			
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	 	3.3.1.2	whether the evaluation of the information by the Representatives was validly considered for incorporation into the Process Development Projects. 

 If the Project Leaders cannot agree, such issue shall be resolved by the Management Committee in accordance with the criteria in Sections 3.3.1.1 and
3.3.1.2. 
  

	 	3.3.2	Each Party shall be responsible for instructing its Representatives on methods of proper introduction of information into the Process Development Projects, and the consequences
under Section 7.10, below, of information that is inadvertently obtained. 

  

	3.4	During a given Process Development Project, the IBM Project Leader shall designate elements of the Specific Results and Background Know-How thereof that IBM will be applying toward
development of its applicable Bulk CMOS or its applicable Industry Standard CMOS process. IBM shall provide an initial designation of such elements at the completion of its initial feasibility studies for the applicable Process Development Project
(set forth in Exhibit B as the “T-Bulk date”), and IBM shall provide a final designation of such elements no later than the “T1” date for the applicable Process Development Project, as set forth in Exhibit B. AMD agrees that IBM
reserves the right to change such designations between its initial designation and its final designation. In either case, prior to making such determinations IBM shall consult with AMD, who shall provide its input as to the applicability of such
elements to a Bulk CMOS or Industry Standard CMOS process; provided, however, that IBM shall have the right to make any and all final decisions as to designation and application of such elements to its Bulk CMOS or its Industry Standard CMOS
process. The Project Leaders shall agree upon a specific process by which IBM will make this designation and by which IBM will address any requests for clarification by AMD within reasonable time periods. For the avoidance of doubt, in addition to
Specific Results designated as Bulk CMOS Information or Industry Standard Information as described in this section 3.4, Bulk CMOS Information and Industry Standard Information shall include those items listed in Exhibit K attached hereto. Exhibit K
may be updated from time to time by written mutual agreement of the Management Coordinators. 

  

	3.5	 Each Party shall have access to all Specific Results and shall be solely responsible, including the cost therefor, for the transfer of Specific Results to its own
facilities. In addition to Representatives, AMD may assign additional personnel to IBM facilities to assist with such transfer. The number of additional personnel and the duration of their assignment shall be mutually agreed to by the Management
Committee. As part of each Process Development Project, the Project Leaders shall coordinate the completion of the Documentation for such Process Development Project and each Party shall have access to all such Documentation. Notwithstanding the
foregoing, subsequent to the Parties establishing the Strategic Technology Objectives (at Pre-T0 Exit ) for CMOS14S, only a subset of the Documentation shall be prepared for the CMOS 14S Process Development Project, as determined by the Project
Leaders. Should AMD have any questions regarding the Documentation as they are transferring such Specific Results to their own 



  


			
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facilities, IBM agrees to provide reasonable telephonic, videoconference or email support through its Technical Coordinator to address such questions during
normal business hours. Each Party shall be solely responsible for obtaining any and all regulatory approvals as may be required to utilize Specific Results at its facilities, and shall be solely responsible for the cost of equipment and consumables
as may be required to utilize the Specific Results at its facilities. 


  

	3.6	Without liability to the other Parties for breach hereof, to the extent known by a Party disclosing information for use in any Process Development Project, prior to such disclosure,
such disclosing Party agrees to promptly notify the other Parties of any limitations on the uses of such information, whether such use would violate or whether such information is protected by any copyright or mask work or similar right of any Third
Party. Upon such notification, the Parties may agree to accept such information into the Process Development Project subject to such limitations. Upon the failure to make such notification, or if any such limitation arises after disclosure by the
disclosing Party, then the Parties shall attempt to work together to find a mutually agreeable solution. Each Party further agrees to use reasonable efforts to ensure that it will not design or develop the Process Development Projects in such a way
that requires the use of any Third Party confidential information, which is not available to the other Parties for their use as aforesaid. Each Party further agrees to use reasonable efforts to ensure that it will not disclose to the other Parties
any information considered confidential by it or by any Third Party which information does not relate to the Process Development Projects. 

  

	3.7	To the extent that either Party enters into a development agreement with its equipment, design, and materials suppliers and elects to disclose the results of any such development to
the other Party as Background Know-How under a Process Development Project or Pre-T0 Activity, and to the extent the disclosing Party has the right to do so, the disclosing Party agrees to notify the other Party of such development agreement.
Furthermore, the disclosing Party will consent to include a reasonable number of Representatives of the other Party in technical discussions with each such supplier. The Parties will use reasonable efforts to accommodate such technical discussions
at either Party’s facilities or via teleconference. Any additional information generated at such meetings shall be the Background Know-How of the Party who has entered into such development agreement. 

  

	3.8	Bump Technology. 

  

	 	3.8.1	The Parties agree that all terms and conditions of the “C-4 Agreements” shall continue in full force and effect, and shall not be superseded by this Agreement. For
purposes of this Agreement, the “C-4 Agreements” shall mean collectively (1) the C-4 Plating Technology Transfer and Licensing Agreement between AMD and IBM having a last signature date of April 29, 1999; (2) the C-4 Tighter
Pitch Workshop Agreement between AMD and IBM having a last signature date of March 23, 2001; (3) the C-4 Technical Assistance and Short Loop Support Agreement between AMD and IBM having a last signature date of July 16, 2001; and
(4) the Letter Agreement having a signature date of September 13, 2004. 

  


			
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	 	3.8.2	The Parties agree that if IBM, in its sole discretion, continues to develop Bump Technology any time after *** and during the remainder of the Term of this Agreement, the Parties
have established Bump Technology Process Development Projects in this Agreement and may establish new Bump Technology Process Development Project(s) in signed amendment(s) to this Agreement. In either case, IBM agrees that AMD will not be required
to pay any additional fees to IBM for access to and a license to said technology. If a separate Bump Technology development agreement is entered between IBM and any Third Party(ies), IBM will use reasonable efforts to include AMD in such development
efforts, subject to the negotiation of mutually agreeable terms and conditions between AMD and the participants in such development efforts. 

  

	 	a.	If Bump Technology is established as a Process Development Project under this Section 3.8.2: (i) the Parties agree that AMD may exercise at least the same rights to use
and implement and have the same obligations with regard to said Bump Technology as AMD currently exercises and has under the C-4 Agreements and (ii) if the Parties, thereafter, mutually agree to expand the scope of a Bump Technology Process
Development Project, such expansion will be governed by the terms and conditions of Section 14. 

  

	 	3.8.3	If Bump Technology is established as a Process Development Project, the Parties will provide, to the extent a Party has the right to do so without the payment of additional
compensation to any Third Party, to the Bump Technology Process Development Project any relevant information as Background Know-How. Additionally, to the extent that IBM does enter a separate Bump Technology development agreement with a Third Party
and IBM has the right to do so without the payment of additional compensation to any Third Party, IBM will grant a sublicense to AMD to the technology developed thereunder without requiring any additional fees, which sublicense shall be consistent
with the licenses granted to AMD under this Agreement and the C-4 Agreements. 

 SECTION 4 – MANAGEMENT AND STAFFING OF THE PROCESS
DEVELOPMENT PROJECTS 
  

	4.1	The Parties hereby create a Management Committee, with equal representation from each Party. The responsibilities of the Management Committee are set forth in Exhibit D, attached
hereto. All decisions of the Management Committee shall be by mutual consent. 

 The Management Committee is comprised
initially of the following individuals: 
  

					
	 (i)
	  	For AMD:	  	***
		  		  	One AMD Place
		  		  	P.O. Box 3453, MS79
		  		  	Sunnyvale, CA 94088-3453
		  		  	Tel: ***

  

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	 (ii)
	  	For IBM:	  	***
		  		  	2070 Route 52
		  		  	Hopewell Junction, New York 12533
		  		  	***
		  		  	Tel: ***
		  		  	Fax: ***

 Either Party may change its member of the Management Committee by written notice to the other
Party. The Management Committee will conduct regular meetings on dates and at locations determined by the Management Committee. Meetings of the Management Committee may be held in person, by teleconference or by videoconference. 
  

	 	4.1.1	The Management Committee shall establish a regular review process with the appropriate senior business executives of each of the Parties of at least the level of Vice President or
other comparable level. Such review shall include review of an overall progress report to be prepared by the Project Leaders. The responsibilities of the Management Committee are set forth in Exhibit D. In addition, the Management Committee shall
establish a Pre-T0 Steering Committee to oversee the Pre-T0 Activities. 

  

	 	4.1.2	Should either Party reasonably determine that the process technology to be developed under the Process Development Projects is no longer meeting the Strategic Technology Objectives
or the Development Schedule, or brings forth empirical evidence of changes in the competitive marketplace for semiconductor technology such that the Strategic Technology Objectives and/or the Development Schedule are no longer competitive, or if the
Parties cannot agree upon the Strategic Technology Objectives or Development Schedule for CMOS 13S or CMOS13S2 prior to Pre-T0 Exit, such Party may present such problem to the Management Committee for discussion. If the Management Committee, after
the exercise of reasonable efforts in the conduct of such discussions, fails to reach mutual agreement as to a resolution of such Party’s concerns then any Party may refer such concerns to the senior executives described in Section 4.1.1,
above, which senior executives shall discuss and meet in person, if necessary, in order to attempt to resolve such Party’s concerns. If such senior executives are unable to resolve such Party’s concern the senior executives agree to
instruct the Management Committee to negotiate a mutually agreeable reasonable wind down plan (which may include negotiation of fees) to terminate the development relationship set forth in this Agreement for any or all Process Development
Project(s). In the event of such termination, AMD shall be entitled to immediately exercise its rights in accordance with Section 8.9 below, subject to the payment terms of Section 5.8.a. 

  

	4.2	 Each Party shall appoint a Pre-T0 Steering Committee member within thirty (30) days after the Effective Date. It is the intent of the Parties that Pre-T0
Steering Committee 



  

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members be assigned to the Pre-T0 Activities for no less than two (2) year terms. The Pre-T0 Steering Committee members shall oversee Pre-T0 Activities
and provide technical guidance to the Management Committee on Pre-T0 Activities definition. A Party may replace its Pre-T0 Steering Committee member, named below, by giving written notice to the other Party of such replacement. The responsibilities
of the Pre-T0 Steering Committee members are set forth in Exhibit G. 


 The Pre-T0 Steering Committee is comprised
initially of the following individuals: 
  

					
	 (i)
	  	For AMD:	  	***
		  		  	One AMD Place
		  		  	P.O. Box 3453, MS79
		  		  	Sunnyvale, CA 94088-3453
		  		  	Tel: ***

  

					
	 (ii)
	  	For IBM:	  	***
		  		  	255 Fuller Road
		  		  	Albany, NY 12203-3698
		  		  	Tel: ***

  

	4.3	Each Party shall appoint a Pre-T0 Project Leader within thirty (30) days after the Effective Date or in AMD’s case, a temporary Pre-T0 Project Leader, if needed, until an
ongoing AMD Pre-T0 Project Leader is identified. It is the intent of the Parties that Pre-T0 Project Leaders be assigned to the Pre-T0 Activities for no less than two (2) year terms. The IBM Pre-T0 Project Leader shall be in charge of the day-
to-day operations of the Pre-T0 Activities. A Party may replace its Pre-T0 Project Leader, named below, by giving written notice to the other Party of such replacement. The responsibilities of the Pre-T0 Project Leaders are set forth in Exhibit H.


 The Pre-T0 Project Leaders shall be: 
  

					
	 (i)
	  	For AMD:	  	***
			
	 (ii)
	  	For IBM:	  	***

  

	4.4	If Bump Technology is established as a Process Development Project, each Party shall appoint a Bump Technology Project Leader within thirty (30) days after the Effective Date.
It is the intent of the Parties that Bump Technology Project Leaders be assigned to the Bump Technology Process Development Projects for no less than two (2) year terms. The IBM Project Leader shall be in charge of the day- to-day operations of
the Bump Technology Process Development Projects. A Party may replace its Bump Technology Project Leader, named below, by giving written notice to the other Party of such replacement. The responsibilities of the Bump Technology Project Leaders are
set forth in Exhibit I. 

  

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The Bump Technology Project Leaders shall be: 
  

											
	(i)	  	For AMD:	  	***	 		  		  	
						
	(ii)	  	For IBM:	  	***	 		  		  	

  

	4.5	Each Party shall appoint a Project Leader within thirty (30) days after the Effective Date. It is the intent of the Parties that Project Leaders be assigned to the Process
Development Projects for no less than two (2) year terms. The IBM Project Leader shall be in charge of the day- to-day operations of the Process Development Projects. A Party may replace its Project Leader, named below, by giving written notice
to the other Party of such replacement. The responsibilities of the Project Leaders are set forth in Exhibit E. 

 The
Project Leaders shall be: 
  

									
	(i)	  	For AMD:	  	***	  		  	
		  		  	2070 Route 52	  		  	
		  		  	Hopewell Junction, New York 12533	  	
		  		  	***	  		  	
		  		  	Tel: ***	  		  	
		  		  	Fax: ***	  		  	
					
	(ii)	  	For IBM:	  	***	  		  	
		  		  	2070 Route 52	  		  	
		  		  	Hopewell Junction, New York 12533	  	
		  		  	***	  		  	
		  		  	Tel: ***	  		  	
		  		  	Fax: ***	  		  	

  

	4.6	AMD will provide Representatives to work on the Process Development Projects and the Pre-T0 Activities at the Development Facilities. Exhibit C, attached hereto, shows the minimum
staffing expected for such Representatives. If IBM so requests, AMD shall make a compensating payment to IBM at a rate of *** ($***) U.S. Dollars per person month for each headcount below the minimum staffing level set forth in Exhibit C. AMD may,
at its sole option, provide up to *** (***) Representatives to work in the Development Facilities. The assignment of such Representatives shall be mutually agreed to by the Project Leaders 

 It is the intent of the Parties that such Representatives be assigned to the Process Development Projects, Pre-T0 Activities, development and other
projects contemplated under this Agreement at the Development Facilities for no less than two (2) year terms. AMD may change the number of Representatives with a minimum of three (3) months prior written notice to the other Parties and may
reassign Representatives with a minimum of one (1) month prior written notice to the other Parties. 
  

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The Parties will provide sufficient technical personnel on the Process Development Projects with the appropriate skills and experience to accomplish
the Strategic Technology Objectives. 
 Each Party will identify one of its employees to coordinate the efforts of that party with regard to
the design related elements of eDRAM Technology (“eDRAM Design Coordinator”). A party may change its eDRAM Design Coordinator by providing prior written notice to the other Party. 
  

	4.7	Each Party shall appoint a Technical Coordinator within thirty (30) days after the Effective Date. The Technical Coordinators shall be: 

  

									
	(i)	  	For AMD:	  	***	  		  	
		  		  	2070 Route 52	  		  	
		  		  	Hopewell Junction, New York 12533	  	
		  		  	***	  		  	
		  		  	Tel: ***	  		  	
		  		  	Fax: ***	  		  	
					
	(ii)	  	For IBM:	  	***	  		  	
		  		  	2070 Route 52	  		  	
		  		  	Hopewell Junction, New York 12533	  	
		  		  	***	  		  	
		  		  	Tel: ***	  		  	
		  		  	Fax: ***	  		  	

 The Technical Coordinators shall be responsible for supervising exchanges of information among the
Parties pursuant to Section 7.2, below. A Project Leader for a Party may replace the Technical Coordinator for such Party, named above, by giving written notice to the other Parties’ Project Leaders of such replacement. 
  

	4.8	Each Party agrees that its Representatives shall comply in all material respects with all personnel, human resources, security and safety rules, procedures and guidelines of the
other Party applicable to contractors resident at or visiting the premises of such Party or its Subsidiary while such Representatives are on the other Party’s or its Subsidiary’s premises, including those set forth in Exhibit F. In
particular, AMD agrees to abide by security requirements as may apply to their Representatives while at the Development Facilities. Each Party shall provide to the other in advance a set of documents setting forth all such rules, procedures and
guidelines, including any updated versions thereof. 

  

	4.9	 Each Party shall be responsible for the selection of its Representatives who will be assigned to work in the Development Facilities on the Process Development
Projects. Personnel supplied by each Party who are Representatives of the supplying Party shall not for any 



  

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purpose be considered employees or agents of any other Party. Each Party shall be responsible for the supervision, direction and control, payment of salary
(including withholding of taxes), travel and living expenses (if any), worker’s compensation insurance, disability benefits and the like of its own Representatives. In addition, each Party may reassign any of its Representatives as such Party
deems necessary, subject to Section 4.3, above. 


  

	4.10	If any Party should become aware of the existence of any hazardous conditions, property, or equipment which are under the control of another Party it shall so advise the other
Party; however, it shall remain that Party’s responsibility to take all necessary precautions against injury to persons or damage to property from such hazards, property, or equipment until corrected by the other Party. Each Party agrees to
comply with the Occupational Safety and Health Act (“OSHA”), applicable OSHA standards, applicable New York safety and health laws and regulations, any applicable municipal ordinances, and applicable facility safety rules of which the
Party has notice, regarding the Representatives it assigns to the Process Development Project(s). 

  

	4.11	The Parties agree that the Parties and any Subsidiaries shall refrain from making any payment or gift of any value to any Representatives of any other Party assigned to the
Development Facilities without the employing Party’s prior written approval. No Party (or any of its Subsidiaries) may make any representation that might cause a Representative of another Party to believe that an employment relationship exists
between such Representative and the other Party. 

  

	4.12	Each Party assumes no liability to the other Parties for any injury (including death) to persons or damage to or loss of property suffered on or about the Development Facilities
unless caused by the gross misconduct or gross negligence of such Party, its Representatives or invitees. 

  

	4.13	To the extent permitted by law, during the term of this Agreement, each Party agrees neither to directly or indirectly solicit for employment purposes the Representatives of any
other Party engaged in semiconductor development in IBM’s East Fishkill or Yorktown Research facilities or AMD’s Sunnyvale, Austin or Dresden facilities or other Representatives working on the Process Development Projects until at least
one (1) year has passed between the date such employee stopped being engaged in semiconductor development, and the date of solicitation, without the prior written permission of such other Party. However, the foregoing does not preclude general
(i.e., non-targeted) recruitment advertising. In addition, to the extent permitted by law, during the term of this Agreement, each Party agrees that its units, divisions, line of business or other comparable organizational structures, involved in
the development of semiconductor process technologies shall not hire Representatives of any other Party engaged in the Process Development Projects, without the prior written permission of such other Party. 

  

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SECTION 5 – AMD FUNDING CONTRIBUTIONS AND ROYALTY PAYMENTS 
  

	5.1	AMD shall pay to IBM for the Term of this Agreement for its respective share of the costs of the Process Development Projects; such payments shall be made as follows (in millions of
US dollars): 

  

																									
	 	  	1Q03	 	2Q	 	3Q	 	4Q	 	1Q04	 	2Q	 	3Q	 	4Q	 	1Q05	 	2Q	 	3Q	 	4Q
	 AMD
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***



	 *
	 Notwithstanding the foregoing, if the Commencement Date is in the 3rd calendar quarter of 2005, AMD will pay to IBM $*** (*** dollars) on or before September 30, 2005. Such payment will not be considered an overdue payment
pursuant to Section 5.2. If the Commencement Date is in the 4th calendar quarter of 2005, AMD’s
3rd quarter 2005 payment above will be reduced to $*** (*** dollars), and the 4th quarter 2005 payment will be increased to $*** (*** dollars), which amount will be payable on or before October 31, 2005. Such payment will not
be considered an overdue payment pursuant to Section 5.2. For avoidance of doubt if the Commencement Date is in the 3rd quarter of 2005, payments in the 4th quarter of 2005 and later will be made in accordance with
Section 5.1 without this asterisked provision. For further avoidance of doubt if the Commencement Date is in the 4th quarter of 2005, payments in 2006 and later will be made in accordance with Section 5.1 without this asterisked provision. 


  

																					
	 	  	1Q06	 	2Q	 	3Q	 	4Q	 	1Q07	 	2Q	 	3Q	 	4Q	 	1Q08	 	2Q
	 AMD
 (4 total partners)
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 AMD
 (3 total partners)
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 AMD
 (2 total partners)
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***

  

																													
	 	  	3Q08	 	4Q08	 	1Q09	 	2Q	 	3Q	 	4Q	 	1Q10	 	2Q	 	3Q	 	4Q	 	1Q11	 	2Q	 	3Q	 	4Q
	 AMD
 (4 total partners)
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 AMD
 (3 total partners)
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 AMD
 (2 total partners)
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***

 Through the term of this Agreement, AMD will pay IBM according to the tables above, where the
applicable row of the table will be determined based upon the total number of partners, including IBM and AMD, participating in S Process Development in the Development Facilities. If the number of partners changes during the Term, then the new


  

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quarterly rate will take effect beginning in the quarter after such change in the number of partners occurs. The amounts described in this paragraph will be
due in quarterly installments commencing with the first calendar quarter of 2006. 
 Such payments shall be made on the fifteenth of the first
month of each calendar year quarter. This Agreement will serve as an invoice for such payments. 
  

	5.2	AMD shall be liable for interest on any overdue payment under this Agreement commencing on the date such payment becomes due at an annual rate equal to eighteen percent
(18%) per year. If such interest rate exceeds the maximum legal rate in the jurisdiction where a claim therefor is being asserted, the interest rate shall be reduced to such maximum legal rate. 

  

	5.3	IBM shall apply the payments of Section 5.1 above towards Process Development Project costs and not for any license rights granted by any Party to any other Party for
Background Know-How. Notwithstanding Section 5.1, AMD shall be required to share the incremental costs of any changes in scope in the Process Development Projects agreed to pursuant to Section 14. 

  

	5.4	Moreover, AMD shall pay IBM a royalty on all ASIC Products, at the rate of *** percent (***%) of the Net Selling Price of each unit of ASIC Product sold, leased or otherwise
transferred directly or indirectly prior to five (5) years from *** for the technology used in said ASIC Product; provided that for ASIC Product using technology that did not complete T1 qualification (as set forth in Exhibit B) during the term
of this Agreement, AMD shall not be liable for any royalty to IBM. It is expressly understood that all royalties for ASIC Products are paid on a per unit basis (e.g., Integrated Circuit or wafer) and no other royalties shall be due under this
Agreement. Such royalty payments are to be paid by AMD for each ASIC Product sold, leased or otherwise transferred at the time of such sale, lease or transfer to a Third party. For clarity, such royalty obligation does not extend to transactions
between or among the Parties and such Wholly Owned Subsidiaries or Related Subsidiaries that do not involve a Third Party. AMD shall pay IBM all royalties owed within forty-five (45) days after the end of each calendar quarter. AMD shall
provide a royalty report to IBM within forty-five (45) days after the end of each calendar quarter. All payments shall be made by wire transfer to the IBM account listed in Section 13.1.1 below, in U.S. dollars. The following information
shall be included in the wire detail: 

 Company Name 
 Reason for Payment 
 License Reference No.
*** 
  

	5.5	 AMD shall maintain a complete, clear and accurate record of the quantity of ASIC Products sold, leased or otherwise transferred and any other relevant information
to the extent it is required to determine whether they are paying the correct royalty amount hereunder. To ensure compliance with the terms and conditions of this Agreement, IBM shall have the right to audit all relevant accounting, technical and
sales books and records 



  

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of AMD. The audit will be conducted by a mutually acceptable audit firm, and shall be conducted following reasonable prior written notice (at least
forty-five (45) days in advance) during regular business hours at an office where such records are normally maintained and in such a manner as not to interfere with AMD’s normal business activities and shall be restricted only to those
records necessary to verify AMD’s obligations hereunder. The audit report provided to IBM may only include the information necessary to determine whether or not any underpayment or overpayment exists, and if it exists, the amount of such
underpayment or overpayment. IBM shall instruct the auditor to include only business information in the audit report to IBM. IBM shall use the business information reported by the auditor only for the purpose of determining royalty payments and for
no other purpose. In no event shall audits be made hereunder more frequently than once in every twelve (12) months and the audit shall not cover any records from a period of time previously audited. If any audit should disclose any underpayment
or overpayment, the owing Party shall within forty-five (45) days pay the difference. The cost of such audit will be borne by IBM. AMD shall be provided with a copy of the audit report within a reasonable period of time after its completion.
The independent audit firm shall not be hired on a contingent fee basis and shall have confidentiality agreements in place sufficient to protect AMD’s confidential information. 


  

	5.6	If AMD exercises its option under Section 8.7, below, AMD agrees to pay IBM a royalty of (a) *** (***) percent for each 65nm SOI Wafer provided to, or purchased by, ***,
and (b) *** (***) percent for each 45nm SOI Wafer and 32nm or 22nm AMD High Performance Integrated Circuit wafer provided to, or purchased by, a *** for the lesser of a period of four (4) years beginning on the initial date of *** of the
applicable technology or the expiration of the confidentiality period for the applicable technology. If a *** is also a ***, the royalty rates will be *** (***) percent for 65 nm SOI Wafers and *** (***) percent for 45 nm SOI Wafers and 32nm or 22nm
AMD High Performance Integrated Circuit wafers. The revenue basis for such qualified SOI Wafers and AMD High Performance Integrated Circuit wafers shall be the lesser of *** for processed SOI Wafers and AMD High Performance Integrated Circuit wafers
of the respective technology generation. If AMD exercises its rights under the second paragraph of Section 8.7, then for the combined maximum capacity thereunder that IBM refuses pursuant to Section 8.7, AMD will pay IBM a royalty of
***percent for each SOI Wafer and *** percent of each Bulk CMOS wafer for 65 nm technology; *** percent for each SOI Wafer for 45nm and AMD High Performance Integrated Circuit wafer for 32nm or 22nm and *** percent for each Bulk CMOS wafer for 45
nm, and AMD Non-High Performance Integrated Circuit wafer for 32nm or 22nm technology provided to, or purchased by, a Third Party and the obligation to pay this royalty will terminate the lesser of *** years from the initial date of *** of the
applicable technology or the expiration of the confidentiality period for the applicable technology. Other than as expressly recited in this Sections 5, 8.19 and 8.20, no royalties will be due for any products. Section 5.2, the payment
procedures of Section 5.4, and the audit provisions of Section 5.5 will apply to the aforementioned wafer royalty payments. Notwithstanding the foregoing, AMD shall not owe any royalties under this Section 5.6 to IBM for use of
technology that did not complete T1 qualification (as set forth in Exhibit B) during the term of this Agreement. 

  

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	5.7	If AMD exercises its license under Section 8.17, below, AMD agrees to pay IBM a royalty of *** percent (***%) for each wafer provided to, or purchased by, a Third Party
pursuant to Section 8.17. The revenue basis for such wafers shall be the Net Selling Price of such wafers. Section 5.2, the payment procedures of Section 5.4, and the audit provisions of Section 5.5 will apply to the
aforementioned wafer royalty payments. 

  

	5.8	If AMD becomes licensed under Section 8.9, below, AMD agrees to pay IBM as follows: 

 a. If IBM does not offer an extension to this Agreement that is consistent with Section 8.8 or if this Agreement is terminated as provided in Sections 4.1.2 and 2.3 (as agreed by the Parties in Section 2.3),
then AMD will pay IBM $*** for each of the ***; and 
 b. If AMD does not request an extension to this Agreement or if the Parties fail to
reach agreement on the extension or if this Agreement is terminated as provided in Section 2.3 (as agreed by the Parties in Section 2.3), AMD will pay IBM $*** for each ***, provided however, if one of the ***, AMD will pay IBM $***.

 Section 5.2 and the payment procedures of Section 5.4 will apply to these payments. IBM agrees that if AMD becomes licensed under
Section 8.9, this Section 5.8 shall be payment in full for all fees payable by AMD or a *** for and only for the licenses granted in Section 8.9. IBM further agrees that (1) if AMD does not establish a *** for a period of greater
than *** years after termination of this Agreement, neither AMD nor its *** will be required to pay royalties or fees for their use of the technology developed under this Agreement, and (2) if AMD establishes a *** within *** to *** years after
termination of this Agreement, the payments owed by AMD in accordance with this Section 5.8 will be diminished by one-half. All amounts payable under this Section 5.8 will be due upon disclosure to the ***. 
  

	5.9	In consideration for the licenses granted by IBM to AMD pursuant to Sections 8.10, 8.11 and 8.12 of this Agreement, AMD has paid to IBM (a) *** US Dollars (US$***) on or before
September 17, 2004, and (b) *** US Dollars (US$***) on or before March 13, 2005, which obligation shall be irrevocable and which payment when made shall be non-refundable. This Agreement served as an invoice for such payments.


  

	5.10	Each Party shall bear and pay all taxes (including, without limitation, sales and value added taxes) imposed upon it by the national government or political subdivision thereof, of
any country in which they are doing business as a result of the existence of this Agreement or the exercise of its rights hereunder. For clarity, IBM shall not be responsible for any taxes, duties or fees resulting from AMD’s exercise of its
rights under Section 8.10. 

  

	5.11	Except as expressly provided in this Agreement, neither Party shall be entitled to any payment, cost reimbursement, or other compensation from the other for services, deliverables
and rights granted to the other Party hereunder. Each Party shall bear all its own expenses incurred in the performance of this Agreement. 

  

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	5.12	In consideration for the licenses granted by IBM to AMD in and to eDRAM Technology and in addition to any other amounts payable hereunder, AMD shall pay to IBM amounts as follows
(a) *** on or before December 15, 2006, (b) *** dollars (US***) on or before January 15, 2007, (c) *** dollars (US$***) on or before April 15, 2007, and (d) two million five hundred thousand dollars (US***) on or
before July 15, 2007; each payment when made shall be non-refundable and irrevocable. This Agreement shall serve as an invoice for such payments. Section 5.2 and the payment procedures of Section 5.4 will apply to all such payments.


  

	5.13	In the event of a termination pursuant to Section 12.8, AMD agrees to pay IBM a royalty of *** percent (***%) of the Net Selling Price for each eDRAM Licensed Product that
embodies eDRAM Technology developed under this Agreement and is provided to, or purchased by, a Third Party if the total of such Net Selling Price is in excess of *** dollars ($***) of cumulative revenue for all such eDRAM Licensed Products. Once
the total cumulative royalty received by IBM pursuant to this Section 5.13 equals *** dollars (US***), AMD shall owe no further royalties pursuant to this Section 5.13. Payments made under this Section 5.13 when made shall be
non-refundable and irrevocable. Section 5.2, the payment procedures of Section 5.4, and the audit provisions of Section 5.5 will apply to all such royalty payments. 

 SECTION 6 – INSURANCE, RESPONSIBILITY FOR RESULTS AND WARRANTIES 
  

	6.1	Although the Parties will use commercially reasonable efforts in performing the Process Development Projects, the Parties acknowledge that the results of the development work to be
performed are uncertain and cannot be guaranteed by any Party. The risk of success or failure of the Process Development Projects shall be shared by all the Parties equally. If a Party has exerted such efforts in the performance of its
responsibilities under a Process Development Project, the failure to achieve performance objectives or schedules within a Process Development Project shall not constitute a breach of this Agreement. 

  

	6.2	All items furnished by a Party to the Process Development Projects will be produced or provided by said Party in the same manner as it produces or provides such items for its own
use and will be furnished on an “AS IS” BASIS WITHOUT WARRANTY OF ANY KIND, including, without limitation, i) ANY WARRANTY THAT THE SPECIFIC RESULTS WILL BE FREE OF THIRD PARTY CLAIMS OF INFRINGEMENT OF PATENTS, COPYRIGHTS, TRADE SECRET,
OR MASK WORK RIGHTS and ii) ANY IMPLIED WARRANTIES OR TERMS OF MERCHANTABILITY AND FITNESS OR USE FOR A PARTICULAR PURPOSE. 

  

	6.3	Each Party shall maintain for the benefit of each of the others, comprehensive general liability insurance of not less than fifteen million dollars ($15,000,000) per occurrence
which covers bodily injury (including death) and property damage (including, to the extent such insurance is reasonably available therefor, environmental damage), and which applies to any such liability the Party may have under this Agreement.
Purchase and maintenance of such insurance shall in no way be interpreted as relieving any Party of any of its responsibilities hereunder, and each Party may carry, at its expense, such additional insurance amounts and coverage as it deems
necessary. In no event shall any such insurance be cancelled without prior written notice by the insured Party’s insurance carrier to the other Party. 

  

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	6.4	IBM represents and warrants that the agreement with its Third Party development partners grants IBM the right to transfer the proprietary information of its Third Party development
partners to AMD and to sublicense such information consistent with Section 8 hereof. Such sublicense is hereby granted pursuant to the terms and conditions of this Agreement. IBM agrees that prior to amending such agreement inconsistent with
this representation and warranty, it shall notify AMD. For clarity, any such Third Party development partners, who are jointly developing with IBM eDRAM Technology compatible with SOI Integrated Circuits or High Performance Integrated Circuits,
shall also be jointly developing with IBM the manufacturing processes for SOI Integrated Circuits or High Performance Integrated Circuits which are applicable to such eDRAM Technology. 

 SECTION 7 – INFORMATION TRANSFERS 
  

	7.1	Without any liability to the other Parties for patent infringement or failure to notify, each Party agrees to promptly notify the other Party in writing or provide oral
notification, as the case may be, of any patents or other intellectual property rights of Third Parties of which it becomes aware, which, in the sole opinion of said Party, may relate to the use of Specific Results. In such instance, the Parties
shall reasonably cooperate with each other to exchange information related to such potential Third Party intellectual property issues. However, no Party shall have any obligation hereunder to conduct patent searches or studies in relation to the
Process Development Projects or to notify the other Parties of any licenses it may have under any particular patent. The Parties recognize that each of them has patent license arrangements with Third Parties and that it is the individual
responsibility of each Party to secure any rights under the patents of Third Parties which may be needed to enable it to manufacture and/or market the product (including products manufactured using the process technology to be developed under the
Process Development Projects) at such time as it determines in its sole judgement that such action is required. 

  

	7.2	 Any confidential information disclosed by one Party to another in performance of the Process Development Projects shall be designated with an appropriate and
conspicuously obvious legend, such as “IBM Confidential” or “AMD Confidential”, as the case may be, such legends to clearly indicate to a person viewing or otherwise accessing such information that it is of a confidential nature
to the disclosing Party. Any such disclosure that is made orally shall be confirmed in writing under a like designation within thirty (30) days after the date of such disclosure. The Technical Coordinators shall monitor and keep records of all
such disclosures of confidential information and shall ensure that it is properly marked as confidential, and record the date of receipt. Specific Results generated pursuant to the Process Development Projects and any confidential information that
is included in Specific Results shall be clearly designated by the Technical Coordinators with an appropriate legend, such as “IBM/AMD Confidential”. Further, in the event that a Representative of any Party obtains information relating to
the Process 



  


			
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Development Projects in tangible form which is not designated as confidential in accordance with this Section 7.2, but which from its nature appears
likely to be confidential, such Representative will notify the Technical Coordinators who then will decide whether or not such information can and should be thereafter treated as confidential. The Technical Coordinators shall either mutually agree
that such information is non-confidential or have all copies of such information in tangible form promptly marked with the appropriate legend identifying its confidentiality. 


  

	7.3	Except as otherwise provided in this Agreement, with respect to Specific Results and any other confidential information of either Party, which is confidential pursuant to
Section 7.2 above, the Party receiving such information shall use the same efforts to avoid its publication or dissemination to Third Parties as it employs with respect to information of its own which it does not desire to be published or
disseminated. For Specific Results of each Process Development Project and Background Know-How, the obligations of confidentiality shall terminate *** for each applicable Process Development Project (if this Agreement is terminated or if for some
other reason a given Process Development Project is not pursued ***, such time period shall be *** of the applicable Process Development Project); in the case of Proprietary Tools, this obligation of confidentiality shall terminate *** after its
disclosure by the disclosing Party; and for all other confidential information this obligation of confidentiality shall terminate *** after its disclosure by the disclosing Party. This obligation shall not, however, apply to any information that is:


  

	 	7.3.1	already in or comes into the possession of the receiving Party or its Subsidiaries without obligation of confidence; 

  

	 	7.3.2	now, or hereafter becomes, publicly available without breach of this Agreement; 

  

	 	7.3.3	intentionally disclosed to or rightfully received from Third Parties without obligation of confidence; 

  

	 	7.3.4	independently developed by the receiving Party or its Subsidiaries; 

  

	 	7.3.5	approved for release by written agreement of the disclosing Party; or 

  

	 	7.3.6	inherently disclosed in the use, lease, sale or other distribution of any available product or service or publicly available supporting documentation therefor by the receiving Party
or any of its Subsidiaries. 

  

	7.4	The receiving Party’s obligations with respect to Specific Results or any other confidential information of the disclosing Party as specified in Section 7.3, above shall
not apply to any disclosure that is: 

  

	 	7.4.1	 in response to a valid order of a court or other governmental body of any country or group of countries or any political subdivision thereof; provided, however,
that the receiving Party shall first have notified the disclosing Party and made a good 



  

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faith effort to obtain a protective order requiring that the information and/or documents so disclosed be used only for the purposes for which the order was
issued; 


  

	 	7.4.2	otherwise required by law; or 

  

	 	7.4.3	reasonably necessary in order to establish the receiving Party’s rights, provided that such receiving Party shall provide the disclosing Party with prior written notice, except
notice shall not be required where the receiving Party is attempting to establish rights in a lawsuit under this Agreement against the disclosing Party or is filing a patent under Section 11 of this Agreement. 

  

	7.5	Each Party shall have the right to disclose and sublicense as specified in Section 8 Specific Results and Pre-T0 Information (including High Sensitivity Pre-T0 Information) to
any of its Wholly Owned Subsidiaries and its Related Subsidiaries at any time; provided however, that such Wholly Owned Subsidiaries and its Related Subsidiaries shall agree to be bound by substantially the same terms as are applicable to said Party
in Sections 7.2, 7.3, and 7.4 and the survival of same pursuant to Section 12. Further, each Party may authorize its Wholly Owned Subsidiaries and its Related Subsidiaries to whom such Party has disclosed Specific Results and Pre-T0 Information
pursuant to this Section 7.5 to exercise some or all of its rights to disclose Specific Results and Pre-T0 Information under and in accordance with Section 7.6. 

  

	7.6	Subject to provisions of this Section 7.6, AMD shall have the right to disclose the following portions of the Specific Results and Pre-T0 Information (except for High
Sensitivity Pre-T0 Information) to Third Parties, but solely for the purpose of enabling such party to assist AMD, in exercising the rights granted to it hereunder: 

  

	 	7.6.1	specifications for masks, materials, chemicals, consumables and/or equipment to contractors or suppliers; 

  

	 	7.6.2	wafers and/or information to have equipment maintained; or 

  

	 	7.6.3	equipment lists and simple process flow information, excluding detailed process flow information or detailed process specifications, as necessary in order to enable installation of
a process in a fabrication facility or to design and construct a facility to practice such process; or 

  

	 	7.6.4	spice models, design-related data (netlists, GDS), device models, verification decks other than to Third Party contractors who design eDRAM or Stand Alone Memory unless such
contractor is providing such assistance in an AMD or IBM facility. 

 Such disclosures will not be made without a written
agreement between the disclosing party and the recipient. Such written agreements shall be subject to the following: 
  


			
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	 	(a)	such agreements must obligate the recipient to utilize the disclosed information solely for the benefit of the discloser and for no other purpose, and solely in furtherance of the
purposes set forth in this Section 7.6; 

  

	 	(b)	such disclosures shall be subject to confidentiality terms and conditions that are the same or substantially similar to those set forth in this Agreement, and at a minimum must have
a confidentiality term that is no shorter than that set forth herein; and 

  

	 	(c)	the disclosing Party shall use reasonable efforts to negotiate a provision in the agreement whereby IBM would be granted third party beneficiary status (or the equivalent under
whatever law applies to the agreement), to the extent permitted by law, with an independent right to enforce the confidentiality and license provisions of the agreement. 

 For the avoidance of doubt, AMD shall have the right under this Section 7.6 to disclose portions of Specific Results and Pre-T0 Information
(excluding High Sensitivity Pre-T0 Information) as may be incorporated into a Derivative Process as set forth in Sections 7.7 and 8.1, for the same purposes and subject to the same limitations as set forth herein. 
 The following Pre-T0 Information (excluding High Sensitivity Pre-T0 Information) and/or information from the “S” Process Development Project may
be disclosed by IBM and AMD to their customers, or as AMD provides in the course of exercising its licenses under Section 8.7 and 8.17, solely for the purpose of enabling sales of Integrated Circuits embodying the Specific Results to such
customers and to their contractors for the purpose of enabling a Party to exercise its rights under this Section 7.6. Each of the disclosing Parties will have a written confidentiality agreement in place with its customers respectively having a
term of confidentiality of five years from the date of disclosure and limiting the use of such information to the purpose set forth herein: 
  

	 	-	process roadmap and development schedule for Process Development Projects 

  

	 	-	time schedule for development of device model library, and SPICE parameters 

  

	 	-	design rules for each Process Development Project 

  

	 	-	simplified process flow (indicative of rough number of process and mask steps) 

  

	 	-	design manual 

  

	 	-	device models 

  

	 	-	checking decks 

  

	 	-	electrical characterization / model information 

  

	 	-	model to hardware comparisons. 

  

	 	-	reliability data and specifications 

  

	 	-	eDRAM soft error rate data and specifications 

  

	 	-	eDRAM test methodology 

  

	7.7	 As set forth in Section 8.1, AMD has the right to utilize one or more aspects of Bulk CMOS or Industry Standard Information in their development of the
Derivative Process. AMD shall have the right to disclose and sublicense as specified in Section 8 such 



  


			
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Derivative Processes to its Wholly Owned Subsidiaries and their Related Subsidiaries at any time (such disclosures being subject to the conditions set forth
in Section 7.5). AMD shall also have the right to disclose and sublicense as specified in Section 8 such Derivative Processes to Third Parties, as follows: 


  

	 	(i)	to not more than *** Third Parties in total under this Agreement subject to Section 7.7(ii), wherein such disclosure and sublicense shall be *** of the applicable Process
Development Project for *** of such Third Parties, and wherein for the AMD FMV, such disclosure and sublicense shall be no earlier than *** of the applicable Process Development Project if AMD has an ownership interest of at least *** percent
(*(***%) at the *** or *** if AMD has an ownership interest of less than *** percent (***%) in the AMD FMV at the time of disclosure, provided in either case: 

  

	 	a.	The AMD FMV may not ***, provided that in no case shall the AMD FMV be prohibited from selling ***; and 

  

	 	b.	***; and 

  

	 	c.	Any other owners of the AMD FMV do not receive a license to any Bulk CMOS or Industry Standard Information under the AMD FMV license grants in this Section 7.7. AMD shall
contractually require the AMD FMV to put procedures in place to prevent the disclosure of any Bulk CMOS or Industry Standard Information to any other owners of the AMD FMV. It is understood that employees of AMD’s current flash memory partner
working within the AMD FMV might be exposed to such disclosed information and such exposure shall not constitute a disclosure under this Section nor a breach of any confidentiality obligations hereunder; and 

  

	 	(ii)	to *** no earlier than the *** of the applicable Process Development Project 

 Such sublicenses will not be granted without a written agreement between the disclosing party and the sublicensee. Such sublicenses and sublicense agreements shall be subject to the following: 
  

	 	(a)	Except for the AMD FMV for the purpose of producing flash memory products, such sublicenses must be for the entire Derivative Process, and not solely or primarily those portions of
the Derivative Process derived from the Specific Results. Furthermore, and with respect only to the AMD FMV, such sublicense and disclosure may be to portions of those Bulk CMOS and Industry Standard CMOS Specific Results identified in accordance
with Section 3.4; 

  

	 	(b)	 such sublicenses shall specifically exclude the right for the Third Party to utilize all or any aspect of the Derivative Process to develop, derive, or 



  

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otherwise create a fabrication process to fabricate SOI Integrated Circuits or High Performance Integrated Circuits. Furthermore, for Third Parties who are
Foundry Companies, such sublicense shall include the right for such Third Parties to manufacture Semiconductor Products only for sale to AMD until *** after Qualification of the applicable Process Development Project and thereafter to others;



  

	 	(c)	such sublicenses shall be subject to confidentiality terms that are the same or substantially similar to those set forth in this Agreement, and at a minimum must have a
confidentiality term that is no less than that set forth herein and include IBM as a third party beneficiary with respect to such confidentiality terms that may be disclosed under said sublicense so that IBM is enabled to enforce its rights with
respect to such confidentiality terms and to seek to obtain damages as may be appropriate; 

  

	 	(d)	such sublicense shall terminate, with immediate effect if the Third Party undergoes any of the following: 

 becomes insolvent, is dissolved or liquidated, files or has filed against it a petition in bankruptcy, reorganization, dissolution or liquidation or
similar action filed by or against it, is adjudicated as bankrupt, or has a receiver appointed for its business; 
 has all or a substantial
portion of its capital stock or assets expropriated or attached by any government entity; or 
 with the exception of the AMD FMV, the Third
Party undergoes a Change of Control (as such term is defined in Section 12.3 of this Agreement, as modified to apply to such sublicensee instead of AMD), but with regard to the AMD FMV, if a new entity formed from the former AMD FMV is no
longer an AMD FMV, such sublicense to the new entity shall survive; and 
  

	 	(e)	to the extent permitted by law, such agreement shall grant IBM third party beneficiary status (or the equivalent under whatever law applies to the sublicense agreement) with an
independent right to enforce the confidentiality and license term of the agreement. If AMD fails to reach an agreement with its disclosee(s) on such third party beneficiary status, then IBM shall discuss and negotiate with AMD for a possible
alternative to this sub-section (e). 

  

	7.8	 Notwithstanding any other provision of this Agreement, AMD shall not be prevented from furnishing or disclosing technical information whether or not included in
Specific Results developed solely by AMD, or by AMD and Third Parties to any Third Party. For the avoidance of doubt, AMD agrees that it shall not engage with Third Parties to develop technical information within the scope of this Agreement for the
purpose of 



  


			
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circumventing the terms and conditions of this Section 7. Further, disclosure of such technical information shall not be prevented even if a minor
portion of Bulk CMOS or Industry Standard CMOS Information embodied in Specific Results is commingled with and constitutes an inseparable element of such technical information. Additionally, the Parties agree that, subject to the terms of this
Section 7.8, AMD reserves the right to use AMD Background Know-How and to disclose such Background Know-How to Third Parties, without limitation even if a minor portion of Pre-T0 Information (excluding High Sensitivity Pre-T0 Information) is
commingled with and constitutes an inseparable element of such technical information. Prior to disclosing any such commingled Pre-T0 Information to Third Parties, AMD must obtain written approval of IBM’s Management Committee member, which
approval shall not be unreasonably withheld. In addition, AMD agrees that, to the extent it has the right to do so, AMD will submit as AMD Background Know-How any improvements or enhancements made by AMD or a Third Party to such commingled Pre-T0
Information. AMD further agrees that it will exercise reasonable efforts to obtain the right to submit such improvements or enhancements as AMD Background Know-How. AMD’s failure to provide such submissions due to administrative reasons shall
not be considered a breach of this Agreement. For clarity, any information that substantially alters the fundamental nature of the commingled Pre-T0 Information shall not be considered a “minor portion”. If any dispute arises with regard
to the definition of “minor portion” prior to disclosure, the Management Committee shall resolve such dispute. No royalties shall be payable in connection with the disclosures permitted by this Section 7.8.



 In addition, AMD may request permission in writing from IBM to disclose Specific Results and/or Pre-T0 Information, in
addition to that set forth in Sections 7.5, 7.6, 7.7 and 7.8 to Third Parties. IBM will consider and respond in writing within four weeks to each such request. 
  

	7.9	IBM shall have the right to disclose Specific Results to any Subsidiary or any Third Party, at any time and for any purpose, and such recipients shall have the right to disclose
Specific Results to their Subsidiaries, provided that such disclosures shall be subject to appropriate confidentiality terms that, at a minimum, shall have a term of confidentiality no shorter than that set forth herein. 

  

	7.10	With respect to information that does not relate to the Process Development Projects and which is considered confidential by either Party, it is not the intention of either Party to
disclose to or obtain from the other Party any such information. In particular, the Parties acknowledge that IBM has other development projects and relationships being conducted in the Development Facilities, and the Parties shall take reasonable
precautions to limit the disclosure and receipt of information unrelated to Process Development Projects. In the event that a Representative of one Party obtains any such information of the other Party that is designated as confidential or which
should from its nature be understood to be confidential, the Technical Coordinators of both Parties shall be informed, and any such information in tangible form shall promptly be returned to said originating Party. Nothing in this Agreement shall
convey any right to said Party to use said tangible information for any purpose. However, any non-tangible information related to said information which is retained in the minds of the Party’s employees will be treated as Specific Results.


  


			
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 SECTION 8 – LICENSES TO BACKGROUND KNOW-HOW 
  

	8.1	IBM hereby grants to AMD, and AMD hereby grants to IBM, under their respective trade secret/know-how rights in and to Background Know-How that becomes part of Specific Results
pursuant to Section 3 or is part of the Pre-T0 Information (including High Sensitivity Pre-T0 Information), a non-exclusive, perpetual, worldwide, irrevocable (subject to all the terms and conditions of this Agreement) license, to use such
Background Know-How for the purpose of researching, developing, engineering, manufacturing, using, marketing, selling, servicing and otherwise disposing of Licensed Products. AMD shall have no obligation under this Agreement to pay any royalty for
the licenses set forth in this Section 8, except as provided in Sections 5, 8.19 and 8.20. 

 For clarification, the
foregoing license shall include the right for AMD to utilize one or more aspects of Bulk CMOS and Industry Standard CMOS Information for the development and qualification of its own, proprietary Bulk CMOS and Industry Standard CMOS process(es)
(“Derivative Process(es)”) and for developing, engineering, manufacturing, using, marketing, selling, servicing and otherwise disposing of Integrated Circuits other than SOI Integrated Circuits or High Performance Integrated Circuits
utilizing such Derivative Process, such Integrated Circuits being designed by any party. It is expressly confirmed that such license shall include the right for AMD to develop Derivative Process(es). 
  

	8.2	IBM hereby grants to AMD, and AMD hereby grants to IBM, under their respective copyright rights in and to Background Know-How , that becomes part of Specific Results pursuant to
Section 3 or is part of the Pre-T0 Information (including High Sensitivity Pre-T0 Information), a non-exclusive, perpetual, worldwide, irrevocable (subject to all the terms and conditions of this Agreement) license to copy documentation and
other written expression, to make derivative works of such written expression, to distribute such documentation and derivatives as set forth elsewhere in this Section 8, and to execute, display, and perform to the extent consistent with the
provisions of Section 7; provided however, that AMD shall make only such numbers of copies and create such derivative works as are reasonably necessary for them to carry out the license rights set forth in Sections 8.1, 8.5, 8.7, 8.8 and 8.9.


  

	8.3	IBM hereby grants to AMD, and AMD hereby grants to IBM, under their respective mask work rights in and to Background Know-How, that becomes part of Specific Results pursuant to
Section 3 or is part of the Pre-T0 Information (including High Sensitivity Pre-T0 Information), a non-exclusive, perpetual, worldwide, irrevocable (subject to all the terms and conditions of this Agreement) license to use any process-related
mask design information provided to a Process Development Project (e.g. kerf test structures) and create derivative works thereof, as reasonably necessary for the licensed Parties to carry out the license rights set forth in Section 8.1, 8.5,
8.7, 8.8, and 8.9. Unless otherwise authorized, this right shall not include any rights to utilize any product design information in such masks. 

  


			
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	8.4	AMD hereby grants to IBM, under AMD’s trade secret and know how rights in and to Background Know-How that becomes part of Specific Results pursuant to Section 3 or is a
part of Pre-T0 Information (including High Sensitivity Pre-T0 Information), a non-exclusive, perpetual, worldwide, fully paid-up, and irrevocable (subject to all the terms and conditions of this Agreement), license to use such Background Know-How
for the purpose of researching, developing, engineering, manufacturing, using, marketing, selling, servicing and otherwise disposing of Integrated Circuits, and to make derivatives of such information for such uses. In the case of copyrights, such
license is to copy documentation and other written expression, to make derivative works of such written expression, to distribute such documentation and derivatives, and execute, display, and perform to the extent consistent with the provisions of
Section 7; provided however, that IBM shall make only such numbers of copies and create such derivative works as are reasonably necessary for it to carry out the license rights set forth herein. In the case of mask work rights, such license is
to use any process-related mask design information provided to a Process Development Project (e.g. kerf test structures) and create derivative works thereof, as reasonably necessary for IBM to carry out the license rights set forth herein. Unless
otherwise authorized, this right shall not include any rights to utilize any product design information in such masks. The foregoing rights include the right for IBM to use such information and materials at facilities it solely owns or solely
controls and the Development Facilities, with the right to also utilize such information and materials (subject to the foregoing restrictions) at facilities of Subsidiaries to whom such information and materials have been disclosed pursuant to
Sections 7.9 and 8.5. 

  

	8.5	The licenses granted in Sections 8.1 through 8.4 shall include the right for each Party to sublicense consistent with their respective disclosure rights as set forth in
Section 7, subject to the terms and conditions set forth therein and as may be applicable pursuant to this Section 8. Each Party agrees to not unreasonably withhold the granting, upon request by a recipient to whom disclosure has been made
pursuant to Sections 7.5, 7.7, and 7.9, of a non-exclusive license under such Party’s patents, under reasonable and non-discriminatory terms and conditions, to the extent necessary for such recipient to utilize the disclosed information for the
purposes set forth in the applicable clause of Section 7, provided such recipient otherwise respects the intellectual property rights of the granting Party. 

  

	8.6	No license or other right is granted herein by any Party to the other Party, directly or indirectly, by implication, estoppel or otherwise, with respect to any trade secrets,
know-how, copyrights, mask works, patents, patent applications, utility models, or design patents except as expressly set forth in this Agreement, and no such license or other right shall arise from the consummation of this Agreement or from any
acts, statements or dealings leading to such consummation. The Parties expressly understand and acknowledge that any patent license rights that may be required to carry out the licenses set forth in this Agreement are set forth in separate patent
cross-license agreements between them. 

  


			
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	8.7	After September 30, 2003, AMD may exercise the sublicensing option in this Section 8.7. IBM hereby grants to AMD the right to disclose and sublicense the process
technology developed by IBM and AMD under this Agreement including SOI Device Information, High Performance Device Information and Bulk CMOS and Industry Standard CMOS Information and Pre-T0 Information (excluding High Sensitivity Pre-T0
Information) subject to the following requirements. AMD may sublicense no more than *** with a combined maximum of *** wafers per month for such technology consumed by, or supplied to the ***. Said combined maximum volume amount for a specific
technology will apply until the confidentiality period for that specific technology expires. AMD must own greater than *** (defined in the same manner as for Subsidiary except for the ownership percentage) *** and the *** own the *** except for ***.
The *** will derive no more than *** percent of its total revenue from ***. The *** will not be based in *** (which for purposes of this Section 8.7 *** does not include ***). The *** will not have the right to use the licensed technology to
provide ***. The *** will not have the right to use the licensed technology other than in ***. The *** will not be *** any sooner than *** after the later termination of either the ***. The *** will not be located in ***. 


If AMD builds or has built a 65 nm, 45 nm or 32nm manufacturing facility for the purpose of exercising AMD’s rights and performing AMD’s
obligations under the immediately proceeding paragraph of this Section 8.7 and AMD and a *** cannot utilize all of the combined maximum capacity of *** wafers per month, then six (6) months prior to start of installation of 65 nm, 45 nm
and 32nm technology for volume production for any unutilized combined maximum capacity, and yearly thereafter for any uncontracted, unutilized combined maximum capacity, AMD will so notify IBM in writing, and IBM will have the right of first refusal
of the unutilized combined maximum capacity at a price to IBM of the then current average market price for such wafers *** percent, but in no event will *** under substantially similar terms and conditions. For the capacity that IBM refuses, AMD may
sell *** including *** subject to this Section 8.7 to Third Parties (other than those that are not permitted to be a ***) provided AMD pays the royalty specified in Section 5.6. The foregoing notification obligation will cease when the
royalty payment obligation for a technology expires. 
  

	8.8	IBM and AMD will meet on or before June 30, 2010 to discuss the possibility of continuing “S” Process development for a period beginning upon the expiration of this
Agreement (“Extension Period”). The exact Strategic Technology Objectives for Process Development Projects during the Extension Period will be negotiated by IBM and AMD with the goal of industry leading performance. IBM will attempt to
recruit a third and fourth partner for participation in “S” Process development during the term of the Extension Period and AMD will assist IBM in these recruitment efforts and will be flexible in altering the terms and conditions of the
“S” Process development to accommodate such third and fourth partners, provided however, the third or fourth partner is not Intel and the Strategic Technology Objectives still seek industry leading performance. 

  

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	8.9	If IBM and AMD do not reach agreement by December 31, 2010 to an extension of this Agreement beyond December 31, 2011, then IBM will grant AMD the license and sublicense
rights in this Section 8.9 effective as of January 1, 2012. (See Section 5.8 for payment terms) 

 IBM hereby
grants to AMD a license to the process technology developed by IBM and AMD under this Agreement including Pre-T0 Information (including High Sensitivity Pre-T0 Information), SOI Device Information, High Performance Device Information, Industry
Standard CMOS Information and Bulk CMOS Information to complete development of the 32 nm technology and develop process technology below 32 nm. The license includes the right to sublicense no more than *** wherein AMD contributes at least *** and
the right for AMD and the *** to use and disclose the 32 nm technology and below to Wholly Owned Subsidiaries. The *** will derive no more than *** percent of its total revenue from ***. The *** will not be based in *** (which for purposes of this
Section 8.9 *** does not include ***). The *** will not have the right to use the licensed technology to provide ***, except to AMD or AMD Subsidiaries. The *** will not be *** any sooner than *** after termination of either the ***. The ***
will not be located in ***. 
  

	8.10	Notwithstanding any provisions to the contrary in this Agreement, IBM hereby grants to AMD a nonexclusive, nontransferable, worldwide, fully paid-up, royalty-free, irrevocable and
perpetual (except if terminated pursuant to Section 12.5) right and license under all copyrights, trade secrets and know-how, owned or licensable by IBM, contained in the IBM Background Know-How, and Specific Results to have Licensed Products
manufactured at *** for AMD in a 90, a 65 and 45 nanometer semiconductor manufacturing process. For clarity, the license grant in this Section 8.10 shall include the right of AMD to disclose IBM Background Know-How, Specific Results and Pre-T0
Information (excluding High Sensitivity Pre-T0 Information), received by or available to AMD under this Agreement, to ***, to the extent needed to exercise the license granted herein, provided *** agrees to be bound by substantially the same
confidentiality terms and conditions as are applicable to AMD in Sections 7.2, 7.3 and 7.4. For the avoidance of doubt, the license grant in this Section 8.10 shall not relieve AMD of its royalty obligations for ASIC Products under
Section 5.4. 

  

	8.11	Notwithstanding any provisions to the contrary in this Agreement, the licenses granted to AMD in Section 8.10 shall include the right of AMD to sublicense AMD Wholly Owned
Subsidiaries. Each sublicensed Wholly Owned Subsidiary shall be bound by the terms and conditions of this Agreement as if it were named in place of AMD. Any sublicense granted to a Wholly Owned Subsidiary shall automatically terminate on the date
each such Wholly Owned Subsidiary ceases to be a Wholly Owned Subsidiary of AMD, unless such cessation occurs after December 31, 2012 for 65nm or after December 31, 2015 for 45nm. 

  

	8.12	 Notwithstanding any provisions to the contrary in this Agreement, IBM shall grant to a ***-AMD Manufacturing Facility designated by AMD, a nonexclusive,
nontransferable, worldwide, fully paid-up royalty-free, irrevocable and perpetual (except if terminated 



  

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pursuant to Section 12.5) right and license under all copyrights, trade secrets and know-how, owned or licensable by IBM, contained in the IBM
Background Know-How, Specific Results and Pre-T0 Information (excluding High Sensitivity Pre-T0 Information) to make Licensed Products, in a 90, a 65 and 45 nanometer semiconductor manufacturing process for sale only to AMD and AMD Wholly Owned
Subsidiaries. For clarity, the license grant in this Section 8.12 shall include the right of AMD to disclose IBM Background Know-How, Specific Results, and Pre-T0 Information (excluding High Sensitivity Pre-T0 Information) received by or
available to AMD under this Agreement, to the ***-AMD Manufacturing Facility, to the extent needed to exercise the license granted herein, provided the ***-AMD Manufacturing Facility agrees to be bound by substantially the same confidentiality terms
and conditions as are applicable to AMD in Sections 7.2, 7.3 and 7.4. For the avoidance of doubt, the license grant in this Section 8.12 shall not relieve AMD of its royalty obligations for ASIC Products under Section 5.4.



  

	8.13	Pursuant to the patent cross license agreement entered into between IBM and AMD with an effective date of January 1, 1997, each Party has granted certain licenses to the other
under its patents based on patent applications filed prior to July 1, 2005, as more fully described in that patent cross license agreement. IBM and AMD acknowledge and agree that the licenses granted in this Section 8 of this Agreement do
not include licenses under the patents of either Party. 

  

	8.14	IBM shall not be responsible to AMD for the quality of Licensed Products manufactured by *** or the ***-AMD Manufacturing Facility for AMD. 

  

	8.15	All information materials provided by AMD to *** pursuant to Section 8.10 and 8.12 of this Agreement shall be furnished “as is.” IBM MAKES NO WARRANTY AS TO THIS
INFORMATION OR MATERIALS, OR AS TO THE RESULTS TO BE ATTAINED BY *** OR THE ***-AMD MANUFACTURING FACILITY FROM THE USE OF THE INFORMATION OR MATERIALS, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
PARTICULAR PURPOSE. IBM makes no representations or warranty that the use of the foregoing information or materials is sufficient for *** or the ***-AMD Manufacturing Facility to develop or manufacture any product or for anything else.


  

	8.16	Neither Party makes any representation or warranty, express or implied, or assumes any liability, with respect to the infringement of patents or other rights of Third Parties which
may arise out of the use of any of the information or materials furnished to *** or the ***-AMD Manufacturing Facility by AMD hereunder, or due to AMD’s operation under the licenses granted in Sections 8.10 and 8.12, notwithstanding that a
Party may be or may become licensed under the patents or other rights of third parties relating to inventions which may or may not be practiced in the information or materials furnished by AMD to *** or the ***-AMD Manufacturing Facility. Each Party
understands that no license or other right is extended to it or to its customers or to *** under any such third party patents or other intellectual property rights. 

  

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	8.17	IBM hereby grants to AMD a non-exclusive, perpetual, worldwide, irrevocable (subject to all the terms and conditions of this Agreement including the payment of royalties in
Section 5.7) license to use the Bulk CMOS Information and portions of Specific Results other than those portions which AMD uses *** manufactured in the applicable technology generation (e.g. 45nm, 32nm) in any given quarter for the purpose of
researching, developing, engineering and manufacturing up to *** wafers (other than SOI Wafers) per week in 65nm, 45nm and/or 32 nm technology, including the right to sell, market, distribute or otherwise dispose of such wafers to Third Parties,
provided that such licensed wafers manufactured using the aforementioned portions of Specific Results shall not include high performance microprocessors intended for use in high performance enterprise Servers. 

  

	8.18	IBM has identified in Exhibit L that Pre-T0 Information not yet selected by the Management Committee for use in a Process Development Project that IBM chooses, in its sole
discretion, to maintain as confidential information (“High Sensitivity Pre-T0 Information”). AMD agrees that IBM reserves the right to update Exhibit L when any of such information is no longer considered to be High Sensitivity Pre-T0
Information or when IBM provides AMD with significant data to support the addition of new High Sensitivity Pre-T0 Information to Exhibit L. If AMD does not believe that IBM has provided significant data to support such addition or if AMD believes
that items should be removed from Exhibit L, the issues shall be elevated to the Management Committee for resolution. Additionally, IBM agrees that any information on Exhibit L that is publicly disclosed, without breach of either Party’s
confidentiality agreements with each other or with a Third Party, shall no longer be considered High Sensitivity Pre-T0 Information. Any other update to Exhibit L shall require the approval of the AMD and IBM Representatives on the Management
Committee. 

 AMD may use Pre-T0 Information that is not High Sensitivity Pre-T0 Information for any purpose. AMD may not
transfer the High Sensitivity Pre-T0 Information to any Subsidiaries or Third Parties without written approval of the IBM Representative on the Management Committee. Pre-T0 Information (other than High Sensitivity Pre-T0 information) may be
disclosed to Third Parties, subject to AMD’s obligations under Section 7. In addition, AMD agrees at its sole discretion and to the extent it has the right to do so, to submit as AMD Background Know-How any improvements or enhancements
made by AMD or a Third Party to such Pre-T0 Information. 
 Additionally, AMD agrees that it will not sell commercially available products
that use High SensitivityPre-T0 Information prior to *** without IBM’s written approval, which IBM approval will not be unreasonably withheld. Notwithstanding the foregoing, AMD will not be prevented from selling such products using High
Sensitivity Pre-T0 information if (a) such High Sensitivity Pre-T0 information is not detectable through reverse engineering, and (b) AMD has not disclosed use of such High Sensitivity Pre-T0 Information. 
  

	8.19	 For the avoidance of doubt, as set forth in Section 3.9.2 a., AMD shall be permitted to perform bumping using the Bump Technology for up to *** semiconductor
wafers per 



  

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calendar quarter for Third Parties. For each *** wafer bumped for Third Parties in excess of *** per calendar quarter, AMD shall pay IBM a royalty of
*** percent (***%) of the bumping price charged by AMD to the Third Parties. AMD’s royalty obligation shall continue through the Term. After the Term, AMD may bump an unlimited number of wafers for third parties with no further royalty or
reporting obligations, including no additional fees for AMD or the Third Parties who have products Bumped by AMD. 


 For the
avoidance of doubt, as set forth in Section 3.9.2 a., AMD shall be permitted to perform bumping using the Bump Technology for up to *** semiconductor wafers per calendar quarter for Third Parties. For each ***mm wafer bumped for Third
Parties in excess of *** per calendar quarter, AMD shall pay IBM a royalty of *** (***%) of the bumping price charged by AMD to the Third Parties. AMD’s royalty obligation shall continue through the term of this Agreement. After the Term,
AMD may bump an unlimited number of wafers for third parties with no further royalty or reporting obligations, including no additional fees for AMD or the Third Parties who have products Bumped by AMD. 
 The licenses granted under, and other license related provisions of, Sections 8.1 through 8.3, 8.5, 8.7, 8.9 through 8.12, and 8.14 through 8.17 shall
apply to eDRAM Licensed Products in the same manner as such licenses and other provisions apply to Licensed Products, as follows: 
  

	 	(a)	for eDRAM Licensed Products manufactured in a 45nm CMOS logic fabrication process; and 

  


	 	(b)	for eDRAM Licensed Products manufactured in any CMOS logic fabrication process, except as altered by Section 12.8. 

 SECTION 9 – LICENSE TO RESIDUALS AND PROPRIETARY TOOLS  
  

	9.1	Notwithstanding any other provisions of this Agreement, to the extent that such use does not infringe the valid patents, patent applications, registered designs, or copyrights of
the other Party, and subject to the provisions of Section 7, each Party shall be free to use the residuals of Specific Results, the other Party’s Background Know-How, Proprietary Tools and Pre-T0 Information (including High Sensitivity
Pre-T0 Information), if any, and other confidential information received pursuant to Section 7.2, above, for any purpose, including use in the development, manufacture, marketing, and maintenance of any products and services. The term
“residuals” means that information in non-tangible form which may be mentally retained by those Representatives of a Party who have had access to Specific Results, the Background Know-How, Proprietary Tools and/or Pre-T0 Information
(including High Sensitivity Pre-T0 Information), if any, of the other Party, pursuant to this Agreement. The Parties agree that the receipt of Specific Results, the Background Know-How, Proprietary Tools and/or Pre-T0 Information (including High
Sensitivity Pre-T0 Information), if any, of another Party shall not create any obligation in any way limiting or restricting the assignment and/or reassignment of a Party’s Representatives within that Party. 

  

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	9.2	Each Party grants to the other Party under the Proprietary Tools provided by that Party for use in the Process Development Projects, an irrevocable, non-exclusive and royalty-free
license to use, execute, display, and perform such Proprietary Tools in the Development Facilities for the purpose of the Process Development Projects. Any Proprietary Tools that are introduced into the Development Facilities for the purpose of the
Process Development Projects may not be transferred from the Development Facilities or used by a Party outside the Development Facilities without the express written consent of the Party introducing the Proprietary Tool(s). Any Party providing
Proprietary Tools used in the Process Development Projects that are not available from another source or for which there is no reasonable substitute, will, to the extent it has the right to do so, and on terms and conditions (including reasonable
fees) to be negotiated, grant a non-exclusive license to the other Party to use such Proprietary Tools outside the Process Development Projects in furtherance of their respective license rights set forth in Section 8. 


SECTION 10 – OWNERSHIP OF SPECIFIC RESULTS 
  

	10.1	Except with respect to Designated Inventions, as set forth in Section 11 of this Agreement, and except with respect to Background Know-How, Specific Results shall be the
property of both Parties which shall own the mask works, copyright, trade secret, know-how and similar rights in all such material jointly without accounting to the other Party. For the avoidance of doubt, such joint ownership shall include
Inventions other than Designated Inventions. Moreover, for the avoidance of doubt, this Agreement shall constitute written consent of such joint owner for the disclosing Party to make the disclosures set forth in Section 7, to the extent such
joint consent is required in a given jurisdiction; provided, however, that such assent is subject to the terms and conditions of this Agreement. Before applying to register or record in any country any of the rights or material to which this
Section 10 relates, the Parties shall hold consultations and agree on whether this is appropriate and, if so, which of them shall make such application and in which countries. 

  

	10.2	The joint ownership by the Parties of all copyright and similar right in and to Specific Results shall be subject to Sections 7 and 8; the Parties understand and agree that their
status as joint owners does not grant them any rights to utilize Specific Results over and above their respective disclosure rights as set forth in Section 7 of this Agreement. 

 SECTION 11 – OWNERSHIP OF DESIGNATED INVENTIONS  
  

	11.1	Each Designated Invention made solely by one or more Representatives or contractors of one Party, and title to all patent applications filed thereon and all patents issued thereon,
shall be solely the property of the inventing Party, subject to a patent license granted in Section 11.3 below. It shall be in the sole discretion of the inventing party to determine whether or not to file a patent application on an Invention,
thereby creating a Designated Invention. 

  


			
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	11.2	Designated Inventions made jointly by one or more Representatives or contractors of one Party with one or more Representatives or contractors of any other Party, and title to all
patent applications filed thereon and all patents issued thereon, shall be jointly owned by the inventing Parties. Each inventing Party shall have the right to grant licenses (including the right of any licensee to grant sublicenses) to the
inventing Party’s Subsidiaries and/or to Third Parties under any patent issued on such a joint Designated Invention without compensation to the other inventing Party and/or its or their Representatives or contractors, which hereby give any
necessary consent for granting such licenses as may be required by the law of any country. All expenses, other than internal patent department expenses of the Parties, incurred in obtaining and maintaining such patents shall be equally shared by the
inventing Parties (except as provided hereinafter). Prior to filing any patent application in respect of any such joint Designated Inventions the inventing Parties shall hold consultations and agree on whether this is appropriate and, if so, which
of them shall file and prosecute such application and in which countries corresponding applications shall be filed and by whom. With respect to any joint Designated Invention, where one inventing Party elects not to seek or maintain such protection
thereon in any particular country or not to share equally in the expenses thereof, the other inventing Party shall have the right to seek or maintain such protection in said country at its or their own expense and shall have full control over the
prosecution and maintenance thereof even though title to any patent issued thereon shall be joint. 

  

	11.3	With respect to Designated Inventions under Sections 11.1, the owning Party hereby grants the other Party the same rights and obligations with respect to the relevant Specific
Results provided for in this Agreement to carry out the activities set forth in this Agreement (including, but not limited to, Sections 7, 8 and 9). With respect to patents issued on said Designated Inventions, the license granted by the owning
Party to the other Party shall be an irrevocable (subject to the terms and conditions of this Agreement), worldwide, non-exclusive, royalty-free, paid-up license to make, have made, use, lease, sell, offer to sell, import and otherwise transfer any
products and to practice and have practiced any process and shall include the right of such licensed Party to sublicense its Subsidiaries of the same or within the scope of the foregoing license. 

  

	11.4	Each Party shall give the other Party all reasonable assistance in connection with the preparation or prosecution of any patent application filed by said other Party and shall cause
to be executed all assignments and other instruments and documents as said other Party may consider necessary or appropriate to carry out the intent of this Section 11. 

  

	11.5	Nothing in this Agreement shall affect any patent license agreements between the Parties currently existing, but may confer rights on one or more Parties in addition to the rights
they may have under such existing agreements. 

  

	11.6	To the extent that a license grant under Sections 9 and 11 recites the right to make any product, apparatus and/or material, or practice any method or process in the manufacture of
same, such grant shall not be construed as conveying the right to a Party or other entity to “have made” such product apparatus and/or material, or “have practiced” any such method or process, unless such right is expressly
recited therein. 

  


			
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	11.7	The Project Leaders shall establish a procedure for reviewing Invention disclosures in order to determine which Inventions are subject to the provisions of Section 11.2 of this
Agreement relating to joint Inventions. 

 SECTION 12 – TERM AND TERMINATION 
  

	12.1	This Agreement shall be in effect from the Effective Date and, unless terminated prior to expiration as hereinafter set forth, shall remain in force until the earlier of
Qualification for CMOS13S2 or December 31, 2011. The term of this Agreement may be extended by the mutual agreement of the Parties. If the Parties do not agree to extend this Agreement and if the *** slips beyond December 31, 2011, this
Agreement shall be extended for an additional three (3) month period for the sole purpose of completing the ***. The Parties will mutually agree on the fees for such three (3) month period based upon the scope of work remaining on the ***
project, but in no case higher than fees paid by AMD in the fourth quarter of 2011. All other terms and conditions of the Agreement will remain in effect during such three (3) month period. If such slippage is greater than three
(3) months, this Agreement may be extended for additional three (3) month periods subject to mutually agreeable terms and conditions (for clarity, including fees based on the scope of work remaining on the *** project) to be negotiated by
the Parties. 

  

	12.2	At expiration of this Agreement, Sections 1; 3.8.1; 4.9 – 4.13, inclusive; 5.2, 5.4 – 5.8, inclusive; 5.10; 5.11; 5.13; 6; 7.1, 7.3-7.10 inclusive; 8; 9; 10; 11; 12; 13;
16; 17 and 18 shall survive and continue after the date of such expiration and shall bind the Parties and their legal representatives, successors and assigns. 

  

	12.3	Either Party shall have the right to immediately terminate this Agreement as to a breaching Party (as defined herein) by giving written notice of termination to the other Party if
the other Party (the “breaching Party”) 1) permanently ceases doing business; 2) is adjudged bankrupt or insolvent or files a petition for bankruptcy; 3) goes into liquidation; or 4) undergoes a Change of Control. 


A “Change of Control” shall be deemed to have occurred if (a) there shall be consummated (i) any consolidation or merger of a Party
in which such Party is not the continuing or surviving corporation, or pursuant to which shares of such Party’s common stock would be converted into cash, securities or other property, other than a merger of such Party in which the holders of
such Party’s common stock immediately prior to the merger have substantially the same proportionate ownership of common stock of the surviving corporation immediately after the merger, or (ii) any sale, lease, exchange or other transfer
(in one transaction or a series of related transactions) of all or substantially all the assets of such Party; (b) the stockholders of a Party shall approve any plan or proposal for the liquidation or dissolution of such Party, or (c) any
person (as such term is used in section 13(d) and 14(d) (2) of the Securities Exchange Act of 1934 (the Exchange Act”) other than a Party or any employee benefit plans sponsored by such Party, shall become the beneficial owner (within the
meaning of Rule 13d-3 under the Exchange Act) of securities of the company representing: (i) more than one third of voting securities 

  

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having the voting power of such Party’s then outstanding securities ordinarily (and apart from rights accruing in special circumstances) having the
right to vote in the election of directors, as a result of a tender or exchange offer, open market purchases, privately negotiated purchases, or otherwise, only if such person and its Subsidiaries exceeded ten billion US dollars in revenue from the
sale of microprocessor Semiconductor Products in calendar year 2001; or (ii) fifty percent (50%) or more of voting securities having the voting power of such Party’s then outstanding securities ordinarily (and apart from rights
accruing in special circumstances) having the right to vote in the election of directors, as a result of a tender or exchange offer, open market purchases, privately negotiated purchases, or otherwise. 


  

	12.4	If either Party to this Agreement fails to perform or violates any material obligation of this Agreement, then, upon thirty (30) days written notice to the breaching Party
specifying such failure or violation (the “Default Notice”), the non-breaching Party may terminate this Agreement as to the breaching Party, without liability, unless: 

 The failure or violation specified in the Default Notice has been cured within a thirty (30) day period; or 
 The failure or violation reasonably requires more than thirty (30) days to correct (specifically excluding any failure to pay money), and the
breaching Party has begun substantial corrective action to remedy the failure or violation within such thirty (30) day period and diligently pursues such action, in which event, termination shall not be effective unless ninety (90) days
has expired from the date of the Default Notice without such corrective action being completed and the failure or violation remedied. 
  

	12.5	Contingencies. 

  

	 	(i)	Intentionally left blank. 

  

	 	(ii)	Additionally, the Parties acknowledge that capital purchases necessary for the continued development of the Process Development Projects past December 31, 2008 are conditioned
upon the receipt of IBM corporate management and Board of Directors approval. If such approvals are not received by September 30, 2007, either Party shall have the right to terminate this Agreement effective December 31, 2008 without
liability to the non-terminating Party, provided, however, that if such approvals are received after September 30, 2007, but prior to either Party’s exercise of its above right to terminate, the above right to terminate shall lapse. The
survival provision of Section 12.2 (including the licenses set forth in Sections 8.9 – 8.12 shall apply to any such termination, provided however that no payments shall be due by AMD under Section 5.8 for such licenses.


  

	12.6	 Notwithstanding any provision to the contrary elsewhere in this Agreement, upon termination of this Agreement pursuant to Sections 12.3 or 12.4, the non-breaching
Party shall have the right to terminate all licenses and disclosure rights granted to the breaching Party pursuant to Sections 7, 8, 9, 10 and 11. If such licenses are terminated, the breaching Party shall immediately return to the non-breaching
Party, or destroy, any 



  


			
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documentation or materials embodying Specific Results and/or Background Know-How, and such return or destruction shall be certified to the non-breaching
Party, in writing, by an officer of the breaching Party. Other than any such termination of licenses and disclosure rights to the breaching Party, Sections 1; 3.8.1, 4.9 – 4.13, inclusive; 5.2, 5.4 – 5.8, inclusive; 5.10; 5.11; 5.12; 5.13;
6; 7.1, 7.3-7.10 inclusive; 8; 9; 10; 11; 12; 13; 16; 17 and 18 shall survive and remain in full force and effect. In addition, the breaching Party shall continue to be bound by the limitations and obligations set forth in Sections: 1; 4.9 and 4.10;
5.2, 5.4 – 5.8, inclusive; 5.10; 5.11; 5.12; 5.13; 6; 7.1, 7.3, 7.4; 8.6; 9.2; 12; 13; 16; 17; and 18. 


 Additionally,
AMD shall have the right to immediately terminate (for convenience and without liability to either Party) this Agreement by giving written notice of termination to IBM, if IBM sells, leases, exchanges or otherwise transfers (in one transaction or a
series of related transactions) the assets of its microelectronics business unit required to perform its obligations under this Agreement. Sections 1; 3.8.1; 4.9 – 4.13, inclusive; 5.2, 5.4 – 5.8, inclusive; 5.10; 5.11; 5.12; 5.13; 6; 7.1,
7.3-7.10 inclusive; 8; 9; 10; 11; 12; 13; 16; 17 and 18 shall survive and continue after the date of such termination and shall bind the Parties and their legal representatives, successors and assigns, provided however that no payments shall be due
by AMD under Section 5.8 for licenses granted under the surviving terms of the Agreement. 
 Additionally, AMD shall have the right to
terminate (for convenience and without liability to either Party) the development of eDRAM Technology effective December 31, 2008 by giving written notice of termination to IBM any time prior to June 30, 2008. In the event of such
termination the following will occur: (i) all Process Development Projects and other activities related to eDRAM Technology shall terminate effective December 31, 2008, (ii) the licenses granted by IBM to AMD under
Section 8.21(b) shall lapse effective December 31, 2008, (iii) AMD’s payments to IBM under Section 5.1 shall be decreased relative to the tables in Section 5.1 by *** ($***) for each of the third and fourth calendar
quarters of 2008 and by *** dollars ($***) for each calendar quarter between the first calendar quarter of 2009 through the second calendar quarter of 2010, inclusive, and (iv) the royalty provisions of Section 5.13 shall become effective.
In the event of such termination, the Parties may hold negotiations regarding the granting of some portion of the licenses under Section 8.21(b) subject to mutually agreeable terms and conditions (for clarity, including fees commensurate with
the scope of such portion of licenses to be granted) to be negotiated by the Parties. 
 SECTION 13 – FUNDS TRANSFER, NOTICES AND OTHER
COMMUNICATIONS 
  

	13.1	 Any notice or other communication required or permitted to be given to either Party pursuant to this Agreement shall be sent to such Party by facsimile or by
registered airmail, postage prepaid, addressed to it at its address set forth below, or to such other address as it may designate by written notice given to the other Party. All payments due hereunder to IBM shall be made to IBM by telegraphic
transfer or other equally expeditious means and IBM shall notify the other Party within thirty (30) days of the date of this Agreement of the account and other details needed by the other Party in order to 



  

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effect such transfer. Any such payment, invoice, notice or other communication shall be effective on the date of receipt. The addresses are as follows:



  

	13.1.1	In the case of IBM, 

 for mailing notices
and other communications to IBM: 
 IBM Corporation 
 2070 Route 52 
 Hopewell Junction, NY 12533 
 Fax: *** 
 Attention: *** 
 With a copy to: 
 IBM Corporation 
 Drop 92B 
 2070 Route 52 
 Hopewell Junction, NY 12533 
 Fax: *** 
 Attention: *** 
 for electronic funds transfer to IBM: 
 IBM Director of Licensing 
 International Business Machines Corporation 
 *** 
 *** 
 ***

 Bank Account Number: *** 
 ABA Routing Number: *** 
  

	13.1.2	In the case of AMD, 

 for mailing notices
and other communications to AMD: 
 AMD 
 One AMD Place 
 PO Box 3453, MS150 
 Sunnyvale, CA 94088 
 Tel: (408)*** 
 Fax: (408)*** 
 Attention: General Counsel 
  

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 SECTION 14 – POTENTIAL EXPANSION OF PROCESS DEVELOPMENT PROJECTS 
 Either Party may submit a request to the Management Committee to expand the scope of the Process Development Projects as set forth in Section 3.1 and
Section 3.8. In order to expand the scope of the Process Development Projects the Management Committee must mutually agree and submit such proposal to the senior executives of the Parties, as defined in Section 4.1.1 for review. If the
Parties agree to a change of scope, any such agreement must be set forth in a signed amendment to this Agreement. In determining whether or not to expand the scope of the Process Development Projects, the Parties shall evaluate each such request in
light of the overall impact such modification would have on the Strategic Technology Objectives and Development Schedule of the Process Development Projects, set forth in Exhibits A and B, as well as cost, schedule, and other business objectives.

 SECTION 15 – FORCE MAJEURE 
  

	15.1	Either Party hereto shall be excused from the fulfilment of any Process Development Project obligation, except for payment obligations, under this Agreement for so long as such
fulfilment may be hindered or prevented by any circumstances of force majeure such as but not limited to acts of God, war, riot, strike, lockout, labor unrest, fire, flood, other natural catastrophe, shortage of materials or transportation, national
or local government regulations or any other circumstance outside its control, provided that the Party seeking to be excused shall make every reasonable effort to minimize the hindrance of such fulfilment. 

  

	15.2	Upon the ending of such circumstance, the Party excused shall without undue delay resume the fulfilment of obligations affected. 

 SECTION 16 – TAXES 
 Each Party shall bear and pay all
taxes (including, without limitation, sales and value added taxes but excluding income tax as specified below) imposed by its own national government, including any political subdivision thereof, as the result of the existence of this Agreement or
the exercise of rights hereunder. If either Party is required by its national government to pay income tax in respect of the payments and/or royalties made by it to either or both of the other Parties, said Party shall pay such income tax on behalf
of said other Party. Said Party may deduct such income tax from said payments and/or royalties otherwise due and shall furnish said other Party, within a reasonable time after its receipt of tax certificates from the applicable government entity
such certificates and other evidence of deduction and payment thereof as said Party may properly require. In addition, each Party may independently pursue any applicable tax credit for its share of expenses related to the Process Development
Projects. 
 SECTION 17 – LIMITATION OF LIABILITY 
  

	17.1	 In no event shall either Party be liable to the other Party for incidental damages, punitive damages, lost profits, lost savings or any other such damages,
including consequential 



  


			
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damages, regardless of whether the claim is for breach of contract, breach of warranty, tort (including negligence), failure of a remedy to accomplish its
purpose or otherwise, even if such Party (or any Subsidiary) has been advised of the possibility of such damages. 
  

	17.2	In no event shall either Party’s (or its respective Subsidiaries’) aggregate liability to the other Party for actual direct damages in connection with any claim or claims
relating to this Agreement exceed the amount of *** United States dollars (US ***), regardless of the form of action, provided that this limitation will not apply to: i) any claim for payment of a sum or sums properly due under this Agreement; ii)
breach of confidentiality or license; or iii) death, personal injury or physical damage to real property or tangible personal property resulting from a Party’s own negligence, or that of its employees, agents or subcontractors.


  

	17.3	Nothing contained herein shall limit either Party’s right to seek a preliminary injunction, temporary restraining order or any other equitable relief in order to avoid material
harm to its property, rights or other interests. The Parties agree that for breaches of confidentiality or license provisions the Party whose license grant or confidential information has been breached (“non-breaching Party”) shall suffer
irreparable harm and that remedies at law may be insufficient; therefore, the non-breaching Party may seek any remedy at law or in equity, including but not limited to, preliminary injunction, injunction, and/or a temporary restraining order,
without having to prove either failure of a remedy at law or irreparable harm. 

  

	17.4	In no event shall either Party (or its respective Subsidiaries) be liable for any damages claimed by the other Party based on any Third Party claim, except as specifically set forth
in Section 17.2 (iii) above. 

 SECTION 18 – GENERAL 
  

	18.1	Nothing contained in this Agreement shall be construed as conferring any right to use in advertising, publicity or other promotional activities any name, trade name, trademark or
other designation of either Party hereto (including any contraction, abbreviation or simulation of any of the foregoing); and each Party hereto agrees not to disclose to other than its Subsidiaries the terms and conditions of this Agreement except
as may be required by law or government rule or regulation, without the express written consent of the other Party. Notwithstanding the foregoing, 1) the Parties shall be permitted to disclose a summary of pertinent Sections of this Agreement that
are reasonably necessary for disclosing and/or licensing under this Agreement, and 2) each Party shall be permitted to disclose pertinent Sections of this Agreement to such Party’s independent accounting firm and outside attorneys; provided,
however, that any such disclosure is under a written agreement containing restrictions of confidentiality at least as stringent as those contained herein. 

  


	18.2	 This Agreement shall be construed, and the legal relations created herein between the Parties shall be determined exclusively, in accordance with the laws of the
United States 



  

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of America and, specifically, the State of New York, without regard to conflicts of law, as if said Agreement were executed in, and fully performed within,
the State of New York. Any proceeding to enforce, or to resolve disputes relating to, this Agreement shall be brought before a court of competent jurisdiction in the State of New York, including a Federal District Court, sitting within such State.
Parties hereby expressly waive any right to a jury trial and agree that any proceeding hereunder shall be tried by a judge without a jury. In any proceedings no Party shall assert that such court lacks jurisdiction over it or the subject matter of
the proceeding. 


  

	18.3	In the event of any dispute under this Agreement, and as a condition precedent to any Party filing suit, instituting a proceeding or seeking other judicial or governmental
resolution in connection therewith, the Parties will attempt to resolve such dispute by negotiation in accordance with the following dispute resolution process. Excepting only that a Party may institute a proceeding seeking an order for payment of
any sum properly due and unpaid, a preliminary injunction, temporary restraining order, or other equitable relief, if necessary in the opinion of that Party to avoid material harm to its property, rights or other interests, before commencing or at
any time during the course of, the dispute procedure in this Section 18.3. 

  

	 	18.3.1	Such negotiations shall first involve the individuals in the Management Committee. These individuals will exercise reasonable efforts to resolve such dispute.


  

	 	18.3.2	If such negotiations do not result within thirty (30) calendar days of their receipt of a written referral to them in a resolution of the dispute, the dispute will be referred
in writing to the senior executives named in Section 4.1.1, above, which senior executives shall discuss and meet in person, if necessary, in order to attempt to negotiate a resolution to the dispute. 

  

	 	18.3.3	Except as set forth above, no Party shall file suit, institute a proceeding or seek other judicial or governmental resolution of the dispute until at least sixty (60) calendar
days after the first meeting between the senior executives. 

  

	18.4	In the event that any litigation occurs between or among the Parties pertaining to this Agreement and any technical issues arise in the course thereof, the Parties shall make good
faith efforts to select one or more neutral mutually acceptable technical experts with expertise in the pertinent technical issues to assist the court in understanding and evaluating such issues. 

  

	18.5	Nothing contained in this Agreement shall be construed as conferring on any Party any license or other right to copy the exterior design of any product of the other Party.


  

	18.6	 No Party shall assign any of its rights or obligations under this Agreement without prior written permission from the other Party. If any Party reorganizes its
business so as to set up a Related Subsidiary or Wholly Owned Subsidiary that shall include the entire business and assets responsible for such Party’s performance of its obligations under this 



  


			
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Agreement then the other Party agrees that the permission to assign to such Related Subsidiary or Wholly Owned Subsidiary shall not be unreasonably withheld.
Any attempted such assignment without such permission shall be null and void. 


  

	18.7	No actions, regardless of form, arising out of this Agreement, except for non-payment actions or intellectual property actions, may be brought by either Party more than two
(2) years after the cause of action has arisen. 

  

	18.8	Each Party shall be responsible for compliance with all applicable laws, regulations and ordinances. In addition, no Party and none of its agents or employees acting on behalf of
said Party will export or re-export any confidential information of the other Party, or any process, product or service that is produced as a result of the use of such confidential information, to any country specified in the applicable laws and
regulations of the United States as a prohibited destination, without first obtaining the relevant government’s approval, if required. As of the Effective Date the countries and nationals excluded for Specific Results and Proprietary Tools
under the United States export laws and regulations are: Cuba, Iran, Iraq, Libya, North Korea, Sudan, and Syria. 

  

	18.9	All monetary amounts specified herein are in lawful money of the United States of America. Any action required herein to be taken by a specified calendar month shall be taken by the
last day of said month. 

  

	18.10	Neither this Agreement nor any activities hereunder shall impair any right of any Party to design, develop, manufacture, sell, market, service, or otherwise deal in, directly or
indirectly, manufacturing processes, products or services developed by such Party completely independent of this Agreement, including those which are competitive with those offered by any Party. Subject to the confidentiality and license limitations
set forth in this Agreement, each Party may pursue activities independently with any Third Party even if similar to the activities under this Agreement. 

  

	18.11	Each Party is an independent contractor and not an agent, employee or fiduciary of any other Party for any purpose whatsoever. No Party shall make any warranties or representations
on any other’s behalf, nor shall it assume or create any other obligations on any other’s behalf. Nothing herein shall be taken to constitute a partnership or joint venture between or among the Parties hereto. 

  

	18.12	Press releases and other like publicity or advertising relating to this Agreement and/or which mentions the other Party by name shall be agreed upon by the Parties in writing prior
to any release, such agreement not to be unreasonably withheld. 

  

	18.13	 If any section or subsection of this Agreement is found by competent judicial authority to be invalid, illegal or unenforceable in any respect, the validity,
legality and enforceability of any such section or subsection in every other respect and the remainder of the terms of this Agreement shall continue in effect so long as the amended Agreement still expresses the intent of the Parties. If the intent
of the Parties cannot be preserved, the Agreement shall be renegotiated with the Parties substituting for any invalid or unenforceable 



  


			
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+provision a valid or enforceable provision that achieves to the greatest extent possible the same effect as would have been achieved by the invalid or
unenforceable provision. 


  

	18.14	Any waiver by either Party of any breach of, or failure to enforce at any time, any of the provisions of any of this Agreement, shall not be construed as or constitute a continuing
waiver of such provision, or a waiver of any other provision of this Agreement, nor shall it in any way affect the validity of any of this Agreement or any part thereof, or the right of either Party thereafter to enforce each and every provision of
any of this Agreement. 

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	18.15	This Agreement will not be binding upon the Parties until it has been signed herein below by or on behalf of each Party in which event it shall be effective as of the date first
above written. This Agreement constitutes the entire agreement between the Parties with respect to the subject matter hereof and shall supersede all previous communications, representations, understandings and agreements, whether oral or written,
made in the course of discussions and/or negotiations between the Parties or any officer or representative thereof with respect to the subject matter of this Agreement. No amendment or modification of this Agreement shall be valid or binding upon
the Parties unless made in writing and signed on behalf of each of such Parties by their respective representatives thereunto duly authorized. The requirement of written form may only be waived in writing. 

  

	18.16	This Agreement may be executed in two (2) counterparts, each of which shall be deemed an original, but each of which together shall constitute one and the same agreement. Fax
or scanned signatures will have the same legal effect as original signatures. 

  

	18.17	Other contractual documents signed between AMD and IBM that refer to the Second Amendment and Restatement of the “S” Process Development Agreement (Effective as of
December 28, 2002) are agreed hereby to refer, after execution hereof, to this Agreement. 

 IN WITNESS WHEREOF, the Parties hereto have
caused this Agreement to be executed by their duly authorized representatives as of the Effective Date. 
  

									
	 Advanced Micro Devices, Inc.
	 		 	International Business Machines Corporation
					
	 By:
	 	 /s/ Hector Ruiz
	 		 	By:	 	 /s/ Adalio Sanchez

					
	 Name:
	 	Hector Ruiz	 		 	Name:	 	Adalio Sanchez
					
	 Title:
	 	CEO	 		 	Title:	 	 General Manager,
 Technology Collaboration
Solutions

					
	 Date:
	 	12/15/06	 		 	Date:	 	12/15/06

  


			
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 EXECUTION VERSION 
  

 EXHIBIT A: TECHNICAL OBJECTIVES 
 EXHIBIT B: PROJECTED SCHEDULE 
 EXHIBIT C: MINIMUM STAFFING PARTICIPATION 
 EXHIBIT D: RESPONSIBILITIES OF THE MANAGEMENT COMMITTEE 
 EXHIBIT E: RESPONSIBILITIES OF THE PROJECT LEADERS 
 EXHIBIT F: VISITATION GUIDELINES 
 EXHIBIT G: RESPONSIBILITIES OF THE PRE-T0
STEERING COMMITTEE 
 EXHIBIT H: RESPONSIBILITIES OF THE PRE-T0 PROJECT LEADERS 
 EXHIBIT I: RESPONSIBILITIES OF THE BUMP TECHNOLOGY PROJECT LEADERS 
 EXHIBIT J: DOCUMENTATION 
 EXHIBIT K: BULK CMOS AND INDUSTRY STANDARD CMOS LIST 
 EXHIBIT L: HIGH
SENSITIVITY PRE-T0 INFORMATION 
  


			
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 EXECUTION VERSION 
  

 EXHIBIT A 
 A.1 CMOS 10S TECHNICAL OBJECTIVES 
 Strategic Technology Objectives 
 *** 
 Technology Implementation Options 
 The CMOS-10S technology may include the following features if needed and technically feasible: 
 -  *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.2 CMOS10SE TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The
CMOS-10SE technology may include the following features if needed and technically feasible: 
 ***  
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.3 CMOS-11S TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The CMOS-11S
technology may include the following features if needed and technically feasible: 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.4 CMOS-11S2 TECHNICAL
OBJECTIVES 
 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The
CMOS-11S2 technology may include the following features, if needed and technically feasible: 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.5 CMOS-12S TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The CMOS-12S
technology may include the following features if needed and technically feasible: 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.6 CMOS-12S2 TECHNICAL
OBJECTIVES 
 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The
CMOS-12S2 technology may include the following features if needed and technically feasible: 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.7 CMOS-13S TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 ***

  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.8 CMOS-13S2 TECHNICAL
OBJECTIVES 
 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 ***

  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.9 CMOS-14S TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 ***

  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.10 Pre-T0 In-scope Technical
Subjects 
 *** 
 *** 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.10 Pre-T0 In-scope Technical
Subjects 
 *** 
 *** 
 *** 
  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.10 Pre-T0 In-scope Technical
Subjects 
 *** 
  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.11 *** AND/OR *** TECHNICAL
OBJECTIVES 
 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The
technology may include the following features if needed and technically feasible: 
 *** 
  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.12 *** TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The
technology may include the following features if needed and technically feasible: 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.13 *** TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 The
technology may include the following features if needed and technically feasible: 
 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.14 *** TECHNICAL OBJECTIVES

 Strategic Technology Objectives 
 ***

 Technology Implementation Options 
 ***

  

 ***Confidential Treatment Requested. 
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 EXECUTION VERSION 
  

EXHIBIT A 
 A.15 CMOS 12SeD Technical
Objectives 
 Strategic Technology Objectives 
 ***

 Estimated targets (within 10%) 
  

					
	 Parameter
	 	 ***
	 	 ***

			
	 Area
	 	***	 	***
	 VDD
	 	***	 	***
	 VPP
	 	***	 	***
	 Standby Power
 (Vdd=1.0V, VPP=1.8V
 Typical Corner, 95C)
	 	***	 	***
	 Cycle Time
 (VDD=0.9V, VPP=1.6V
 Typical Corner, 95C)
	 	***	 	***
	 Access time
 (Same as above)
	 	***	 	***
	 Refresh, 105C
	 	***	 	***
	 Refresh, 95C
	 	***	 	***
	 Pump Area
	 	***	 	***

 *** 
 Technology Implementation Options 
 The CMOS 12SeD technology may include the following features, if needed and technically feasible:

 *** 
  

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 EXECUTION VERSION 
  

EXHIBIT A 
 A.16 CMOS 13SeD Technical
Objectives 
 Strategic Technology Objectives 
 ***

 Specifications to be determined 
 Technology
Implementation Options 
 Technology Implementation Options to be determined 
  

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 EXECUTION VERSION 
  

EXHIBIT B 
 PROJECTED SCHEDULE 
  

																							
	PROJECT	  	10S	 	10SE	 	11S	 	11S2	 	12S	 	12SeD	 	12S2	 	13S	 	13SeD	 	13S2	 	14S
	 Pre-T0 Exit
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 T-Bulk
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 T1
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	 T2**
	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***

 Bump Technology 
  

									
	PROJECT	  	A.11	  	A.12	  	A.13	  	A.14
	 Pre-T0 Exit
	  	***	  	***	  	***	  	***
	 T0
	  	***	  	***	  	***	  	***
	 T1
	  	***	  	***	  	***	  	***
	 T2
	  	***	  	***	  	***	  	***



	 	**	T2 date is based on a ***, otherwise on a ***. 

 T1 and T2
Dates in the table above for 13S, 13S2 and 14S are target dates and will be confirmed at the time of Pre-T0 Exit. 
 Checkpoint Definitions:

 Pre-T0 Exit date: As defined in Section 1 
 T–Bulk date: Initially identify elements of the relevant Process Development Project that IBM plans to use in IBM’s Bulk CMOS and Industry Standard CMOS 
 T1: yield process and reliability demonstration on an integrated process Test Site 
 T2: meets functional requirements for an SOI Integrated Circuit product (not Test Site) 
  

 ***Confidential Treatment Requested. 
 Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM 

			
	IBM - AMD Confidential	 	Page 73 of 90









 EXECUTION VERSION 
  

Preliminary Schedule for work supporting 12SeD: 
  

					
	 •     ***
	  		  	
	 •     ***
	  		  	***
	 ***
	  	***	  	
	 •     ***:
	  		  	
	 •     ***
	  		  	***
	 •     ***
	  		  	***
	 –    ***
	  		  	
	 •     ***
	  		  	***
	 •     ***
	  		  	***

 Key CMOS 12SeD Design Milestones 
  

					
	 Milestone
	  	 Comment
	  	 
			
	 D0.0
	  	***	  	***
	 D0.3
	  	***	  	***
	 D1.0
	  	***	  	***
	 D1.3
	  	***	  	***
	 D2.0
	  	***	  	***
	 D2.3
	  	***	  	***
	 D3.0
	  	***	  	***

 Definitions: 
 D0.0
– *** 
 D0.3 – *** 
 D1.0 – *** 
 D1.3 – *** 
 D2.0 – *** 
 D2.3 – *** 
 D3.0 – *** 
  

 ***Confidential Treatment Requested. 
 Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM 

			
	IBM - AMD Confidential	 	Page 74 of 90









 EXECUTION VERSION 
  

EXHIBIT C 
 MINIMUM STAFFING PARTICIPATION

 (Average Annual Staffing Level) 
  

																			
	 	  	2003	 	2004	 	2005	 	2006	 	2007	 	2008	 	2009	 	2010	 	2011
	CMOS + eDRAM	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***
	Bump	  	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***	 	***



	*	The Staffing Allocation will be determined by the mutual agreement of the IBM Project Leaders and AMD Project Leaders. 


	**	These engineers are expected to be productive immediately and should have enough experience in the given technology area to work independently and lead sub teams.



	***	If AMD exercises its termination right pursuant to Section 12.8, AMD’s minimum staffing participation for CMOS + eDRAM will be reduced by 5 during 2009 and 2010.


  

 ***Confidential Treatment Requested. 
 Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM 

			
	IBM - AMD Confidential	 	Page 75 of 90










 EXECUTION VERSION 
  

 EXHIBIT D 
 RESPONSIBILITIES OF THE MANAGEMENT COMMITTEE 
  

	 	 -
	 Approve changes in Strategic Technical Objectives as set forth in Exhibit A* 


  

	 	 -
	 Approve changes of schedules of the Projects set forth in Exhibit B* 


  

	 	-	Establish a regular review process on no more than a quarterly basis with business executives of each of the Parties of at least the level of Vice President or other comparable
level. 

  

	 	 -
	 Approve external communications about the goals of the Projects and external publications* 


  

	 	-	Resolve such other items as the Management Committee deems appropriate or as indicated elsewhere in the Agreement as requiring the agreement of the Management Committee.




	*	Items marked require unanimous approval of the Management Committee 

 All other responsibilities, including day-to-day management responsibility for the results to be achieved under the Agreement, shall reside with the IBM Project Leader with the help of the AMD Project Leader.

  


			
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	IBM - AMD Confidential	  	Page 76 of 90










 EXECUTION VERSION 
  

 EXHIBIT E 
 RESPONSIBILITIES OF THE IBM PROJECT LEADER 
 Project organization and coordination 
  

	 	-	Responsible for implementation of directives from the Management Committee for the Process Development Projects 

  

	 	-	Responsible for identification and presentation to Management Committee of those items which need Management Committee approval 

  

	 	-	Responsible for Project reporting at Management Committee reviews 

  

	 	-	Responsible for quarterly reports (technology status, milestones). 

  

	 	-	Responsible for allocation of Project resources 

  

	 	-	Responsible for review and approval of technical publications 

  

	 	-	Responsible for determining the organizational structure of the Project Team and appointing key technical leaders and project managers to execute Projects 


 

	 	-	Responsible for managing the IBM infrastructure to support the Project Activities 

  

	 	-	Responsible for Project schedule planning 

  

	 	-	Responsible for management of IBM Personnel 

  

	 	-	Responsible for completion of Documentation for each Process Development Projects 

  


			
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	IBM - AMD Confidential	  	Page 77 of 90










 EXECUTION VERSION 
  

 EXHIBIT E 
 RESPONSIBILITIES OF THE AMD PROJECT LEADER 
  

	 	-	Responsible for implementation of directives from the Management Committee for the Projects 

  

	 	-	Responsible for identification and presentation to Management Committee of those items which need Management Committee approval 

  

	 	-	Responsible for Project reporting at Management Committee reviews 

  

	 	-	Responsible for quarterly reports (technology status, milestones) 

  

	 	-	Responsible for review and approval of technical publications 

  

	 	-	Responsible for management of respective Party’s personnel 

  

	 	-	Responsible for completion of Documentation for each Process Development Projects 

  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 78 of 90










 EXECUTION VERSION 
  

 EXHIBIT F 
 VISITATION GUIDELINES 
  

	1.0	IBM shall issue security badges to visitors. Security badges must be returned by visitors at the end of each assignment. Security badges must be visibly displayed at all times by
visitors while on IBM premises. If the security badge is lost or stolen, the IBM Technical Coordinator shall be immediately advised. Security badges shall not be loaned or interchanged. 

  

	2.0	Visitors shall only enter those buildings, departments, or areas which are specifically designated by the IBM Technical Coordinator and for which entry is required under this
Agreement. 

  

	3.0	Visitors shall comply with all log-in/log-out requirements when entering or leaving IBM buildings and/or designated work areas. 

  

	4.0	Visitors shall comply with all security and safety guidelines which are posted on IBM premises and/or are otherwise specified by IBM. 

  

	5.0	IBM copying equipment and/or other IBM equipment (such as data processing equipment and word processing equipment) shall not be used by visitors except with prior approval of the
IBM Technical Coordinator. 

  

	6.0	Visitors shall not disturb materials lying on IBM desks, mounted on easels or displayed on chalkboards. 

  

	7.0	Visitors shall promptly leave buildings and department areas after completing work assignments. 

  

	8.0	Visitors shall not leave IBM external doors propped open. No IBM materials shall be removed from buildings without prior written approval. 

  

	9.0	Alcoholic beverages, illegal drugs, guns and ammunition, cameras, and recording devices are not permitted on IBM premises. 

  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 79 of 90










 EXECUTION VERSION 
  

 EXHIBIT G 
 RESPONSIBILITIES OF THE PRE-T0 STEERING COMMITTEE 
  

	8	Responsible for providing technical guidance to the Management Committee for defining Pre-T0 Activities and Technical Objectives (Exh. A) 

  

	9	Responsible for assisting the Project Leaders in the implementation of the Pre-T0 Activities 

  

	10	Approve changes in Pre-T0 Technical In-Scope Technical Subjects and projects as set forth in Exhibit A, with final approval to be provided from the Management Committee


  

	11	Actively participate in the review and approval process regarding external communication about the goals of the projects and external publications 

  

	12	Responsible for reporting on Pre-T0 Activities 

  

	13	Responsible for working with the Management Committee and appropriate development and Pre-T0 Project leaders to define 32 and 22nm Technology Objectives and Technology
Implementation Options. Preliminary Objectives and Options should be defined 5 quarters prior to Pre-T0 exit. Updated Objectives and Options should be provided at Pre-T0 Exit (start of T0). 

  

	 	•	Establish an appropriate regular review process of Pre-T0 Activities. Quarterly updates on key Pre-T0 projects should be formally added to the MCM meeting Agenda starting no later
than 5 quarters before Pre-T0 exit. 

  

	14	Resolve such other items as the Pre-T0 Steering Committee deems appropriate or as indicated elsewhere in the Agreement as requiring the agreement of the Pre-T0 Steering Committee.


 All other responsibilities, including day-to-day management responsibility for the results to be achieved under the Agreement, shall reside
with the IBM Pre-T0 Project Leader with the help of the AMD Pre-T0 Project Leader. 
  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 80 of 90










 EXECUTION VERSION 
  

 EXHIBIT H 
 RESPONSIBILITIES OF THE IBM PRE-T0 PROJECT LEADER 
 Project organization and coordination 
  

	 	-	Responsible for implementation of directives from the Pre-T0 Steering Committee and/or Management Committee for the Pre-T0 Activities 

  

	 	-	Responsible for identification and presentation to the Pre-T0 Steering Committee and/or Management Committee, as appropriate, of those items which need their approval


  

	 	-	Responsible for Project reporting of Pre-T0 Activities to the Pre-T0 Steering Committee 

  

	 	-	Responsible for quarterly reports (technology status, milestones). 

  

	 	-	Responsible for allocation of Pre-T0 Activities resources 

  

	 	-	Responsible for review and approval of technical publications 

  

	 	-	Responsible for determining the organizational structure of the Pre-T0 Activities teams and appointing key technical leaders and project managers to execute Pre-T0 Activities


  

	 	-	Responsible for managing the IBM infrastructure to support the Pre-T0 Project Activities 

  

	 	-	Responsible for Pre-T0 Activities schedule planning 

  

	 	-	Responsible for management of IBM Pre-T0 personnel 

  

	 	-	Responsible for completion of appropriate Pre-T0 documentation 

  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 81 of 90










 EXECUTION VERSION 
  

 EXHIBIT H 
 RESPONSIBILITIES OF THE AMD PRE-T0 PROJECT LEADER 
  

	 	-	Responsible for implementation of directives from the Pre-T0 Steering Committee and/or Management Committee for the Pre-T0 Activities 

  

	 	-	Responsible for identification and presentation to the Pre-T0 Steering Committee and/or Management Committee, as appropriate, of those items which need their approval


  

	 	-	Responsible for Pre-T0 Activities reporting at Steering Committee reviews 

  

	 	-	Responsible for quarterly reports (technology status, milestones) 

  

	 	-	Responsible for review and approval of technical publications 

  

	 	-	Responsible for management of respective Party’s personnel 

  

	 	-	Responsible for completion of appropriate Pre-T0 documentation 

  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 82 of 90










 EXECUTION VERSION 
  

 EXHIBIT I 
 RESPONSIBILITIES OF THE IBM BUMP TECHNOLOGY PROJECT LEADER 
 Project organization and coordination 
  

	 	-	Responsible for implementation of directives from the Management Committee for any Bump Technology Process Development Projects 

  

	 	-	Responsible for identification and presentation to the Management Committee of those items which need their approval 

  

	 	-	Responsible for project reporting of any Bump Technology Process Development Projects to the Management Committee 

  

	 	-	Responsible for quarterly reports (technology status, milestones). 

  

	 	-	Responsible for allocation of any Bump Technology Process Development Projects resources 

  

	 	-	Responsible for review and approval of technical publications 

  

	 	-	Responsible for determining the organizational structure of any Bump Technology Process Development Projects teams and appointing key technical leaders and project managers to
execute any Bump Technology Process Development Projects 

  

	 	-	Responsible for managing the IBM infrastructure to support any Bump Technology Process Development Projects 

  

	 	-	Responsible for any Bump Technology Process Development Projects schedule planning 

  

	 	-	Responsible for management of any IBM Bump Technology Process Development Projects personnel 

  

	 	-	Responsible for completion of any appropriate Bump Technology Process Development Projects documentation 

  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 83 of 90










 EXECUTION VERSION 
  

 EXHIBIT I 
 RESPONSIBILITIES OF THE AMD BUMP TECHNOLOGY PROJECT LEADER 
  

	 	-	Responsible for implementation of directives from the Management Committee for any Bump Technology Process Development Projects 

  

	 	-	Responsible for identification and presentation to the Management Committee of those items which need their approval 

  

	 	-	Responsible for quarterly reports (technology status, milestones) 

  

	 	-	Responsible for review and approval of technical publications 

  

	 	-	Responsible for management of respective Party’s Bump Technology Process Development Projects personnel 

  

	 	-	Responsible for completion of any applicable Bump Technology Process Development Projects documentation 

  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
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 EXECUTION VERSION 
  

 EXHIBIT J 
 DOCUMENTATION 
 Wafer Process And Characterization Documentation 
 Process routing 
 Process of Record (POR) 
 - Process change history 
 Process assumptions 
 Process engineering specifications 
 Unit process descriptions and characterization (rate, uniformity, selectivity,
particle, etc.) 
 Process recipes for critical unit processes 
 Specification Sheets for critical dimensions, overlay 
 ED analysis data of critical layers (litho process widow) 
 Cp/Cpk for critical measurements 
 List of critical tools including QC tools 
 Critical Equipment specifications 
 - Critical maintenance procedures 
 TEM Cross Sections (both center and edge) 
 Finished wafer: STI, GC, CS, LI, Interconnect
spacer edge, LI bottom on STI, CS bottom, Via bottom 
 In Line wafer: After GC etch, after spacer-1 etch, after spacer-2
etch, after CS etch, after V2 etch, after M2 etch 
 Tool control/monitor data for critical tools 
 Material Specifications for critical materials 
 Defect Catalog 
 SOI Wafer or High Performance Integrated Circuit wafer Specification 
 Bill Of Materials For wafers 
 SIMS data (as available) 
 Device design and modeling: 
 - SOI or High Performance Integrated Circuit device model

 - Parameter extraction 
 - AC Performance Verification 
 - Tolerance data 
 - Compact model 
  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
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 EXECUTION VERSION 
  

 - Device-level library 
 - HSpice convergence 
 - Body contact modeling 
 - SOI Resistor and capacitor 
 - ESD circuitry at I/O pads 
 Technology Qualification Vehicle Documentation 
 Technology Design Manual 
 Test Site description 
 - Groundrule waivers 
 Kerf description document 
 In-Line Electrical Specification document 
 Layout & mask information (for Test Site) in GDSII format 
 Reliability Documentation 

Qualification plan 
 Early reliability stress results on Test Site (devices, interconnects, capacitor) including NBTI 
 Physical failure
analysis data after E, SM reliability tests 
 Electrical Results 
 Test programs (for IBM Proprietary Tool – electrical tester) 
 Functional test 
 Burn-In/reliability 
 T2 Product Characterization data for SOI Integrated Circuit or High Performance Integrated Circuit product

 (dependent on availability of common IBM / AMD product) 
 Lithography Documentation 
 - Mask fabrication specifications 
  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 86 of 90










 EXECUTION VERSION 
  

 - Mask data processing sequence including OPC/PPC 
 - Method of process characterization to extract OPC/PPC data correction paramaters for the correction software 
 - Mask qualification procedure 
 - Specific mask making tool selection and its derived mask fabrication specification if exists 
 Bump Documentation

 Process routing 
 Process of Record (POR) 
 - Process change history (after T2 process freeze) 
 Process assumptions, if available 
 Process engineering specifications 
 Unit process descriptions and characterization (rate,
uniformity, selectivity, particle, etc.) 
 Process recipes for critical unit processes 
 Process window definition and define process limitations 
 Specification Sheets for critical dimensions, overlay 
 Cp/Cpk for critical measurements 
 List of critical tools including QC tools 
 Critical Equipment specifications 
 - Critical maintenance procedures 
 TEM Cross Sections (both center and edge) 
 Cross section data of bump geometries 

Physical characterization results (e.g., SEM, EDX, SIMS, etc.) 
 Reliability measurement methodology and applicable results including fatigue and electromigration 
 Tool control/monitor data for critical tools 
 Material Specifications for critical materials 
 - plating baths, sputtering targets and
suppliers 
 - Contamination effects 
 Defect Catalog 
 Bill Of Materials For bumps 
 Technology Qualification Vehicle Documentation 
 Technology Design Manual, if available 
  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 87 of 90










 EXECUTION VERSION 
  

 In-Line Specification document, if available 
 Reliability Documentation 
 Qualification plan for T0, T1 and T2 
 Early reliability stress results 
 Physical failure analysis data 
 eDRAM
Documentation 
 eDRAM Design Manual Addendum 
 eDRAM Macro (hard core) Documentation and Design Kit, including specifications, product description, Schematics, VHDL, GDS, CDL netlist, timing cross
sections 
 eDRAM Pump Macro (hard core) Documentation and Design Kit, including product description, Schematics, VHDL, GDS, CDL netlist

 eDRAM BIST Macro (soft core) Documentation and Design Kit, including product descriptions, Schematics, VHDL (soft core) 
 Memory Subsystem Test Chip Documentation 
 Functional Test Specifications and Test Programs 
 Additional requests for Documentation shall be by the mutual agreement of the Project Leaders,
which agreement shall not be unreasonably withheld. If, however, the Project Leaders do not agree, such Party may escalate the lack of agreement among the Project Leaders to the Management Committee for resolution. In addition, such Party may access
information available during the Process Development Projects and document such information for the purpose of transferring such information to its own manufacturing facilities. All such documentation shall be made available to all three
(3) Parties. 
  


			
	Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
	IBM - AMD Confidential	  	Page 88 of 90









 EXECUTION VERSION 
  

EXHIBIT K 
 BULK CMOS AND INDUSTRY
STANDARD CMOS LIST 
 Ø *** 
  

 ***Confidential Treatment Requested. 
 Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM 

			
	IBM - AMD Confidential	 	Page 89 of 90









 EXECUTION VERSION 
  

EXHIBIT L 
 HIGH SENSITIVITY PRE-T0
INFORMATION 
 *** 
  

 ***Confidential Treatment Requested. 
 Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM 

			
	IBM - AMD Confidential	 	Page 90 of 90