# Patent

## Title
Inverter-based flash analog-to-digital converter using floating resistor ladder

## Abstract

An analog-to-digital converter device for converting an analog signal into a digital signal includes a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter, a resistor string including a plurality of resistors connected in series, each of the resistors corresponding to one of the plurality of comparators, and a current generator for providing a constant current flowing through the resistor string.

## Background
BACKGROUND OF THE INVENTION
The present invention generally relates to an analog-to-digital converter (“ADC”) and, more particularly, to an inverter-based flash ADC including a floating resistor ladder for use, for example, in ultra wideband (“UWB”) transceivers.
An analog-to-digital converter (“ADC”) is a device for converting an input analog signal, either in the form of a voltage or current, into a digital signal. ADCs are typically divided into successive approximation ADCs and flash ADCs. A successive approximation ADC functions to sequentially determine bits of a digital code corresponding to an analog input. Generally, a successive approximation ADC requires one clock cycle per bit of resolution. On the other hand, a flash ADC, which includes a more complicated hardware structure than the successive approximation ADC, is able to complete the entire analog-to-digital conversion process simultaneously rather than sequentially, generally in only one clock cycle.
Of the flash ADCs, an inverter-based flash ADC, which employs the TIQ (threshold-inverter-quantization) technique, meets the requirements of low power consumption and low supply voltage in SOC (system-on-chip) designs. The TIQ technique is advantageous in that it can be integrated with other digital circuits while reducing total power consumption. Such an advantage renders the TIQ technique suitable for use in UWB (ultra wideband) transceivers, in which low power consumption is a matter of concern. However, conventional flash ADCs generally suffer from inverter mismatch, which may occur due to unsymmetry in the fabrication of the inverters of the ADC, disadvantageously resulting in variations in the switching threshold voltages of the inverters. The switching threshold voltage Vm of an inverter is given below.

Vm=[r(VDD−|VTp|)+VTn]/(1+r)

where VDD is the supply voltage of the inverter-based flash ADC, VTp and VTn are the threshold voltages of the PMOS and NMOS transistors of the inverter, respectively, and r is further defined below.

r=[μP×COX×(W/L)P)]1/2/[μN×COX×(W/L)N)]1/2

where μP and μN are the mobility of hole and electron, respectively, COX refers to a capacitance of an oxide film, and (W/L)P and (W/L)N are the channel width to channel length ratios of the PMOS and NMOS transistors of the inverter, respectively.
To overcome the inverter mismatch issue, conventional techniques have been proposed to adjust the factors of Vm, including VDD, VTp, VTn and the W/L ratio. In a first approach of the conventional techniques, a supply voltage VDD to be connected to each of the comparators of a flash ADC varies as the Vm varies such that the supply voltage level at one comparator may be different from that at another comparator. In a second approach, the doping density in the transistors of each of the comparators varies such that doping density may be different from comparator to comparator. In a third approach, the W/L ratio in the transistors varies such that the size may be different from comparator to comparator. The first and second approaches, which may have proposed a linear solution, have difficulty in implementation. The third approach may be disadvantageous in layout design and has difficulty in providing transistors with individual threshold voltages.
It is desirable to have a flash ADC that addresses inverter mismatch without changing the size or parameters of the inverters, while retaining the features of an inverter-based flash ADC such as low power consumption as required by a UWB transceiver.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to an analog-to-digital converter (“ADC”) that obviates one or more problems resulting from the limitations and disadvantages of the prior art.
In accordance with an embodiment of the present invention, there is provided an analog-to-digital converter device for converting an analog signal into a digital signal that comprises a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter, a resistor string including a plurality of resistors connected in series, each of the resistors corresponding to one of the plurality of comparators, and a current generator for providing a constant current flowing through the resistor string.
Also in accordance with the present invention, there is provided an analog-to-digital converter device for converting an analog signal into a digital signal that comprises a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter, a resistor string including a plurality of resistors, each of the resistors corresponding to one of the plurality of comparators, a receiving comparator selected from one of the plurality of comparators for receiving the analog signal at a node of the resistor string without passing through any resistors of the resistor string, a first sub-string of the resistor string being separated from a second sub-string of the resistor string at the node, a first current generator for providing a first constant current flowing through the first resistor sub-string, and a second current generator for providing a second constant current flowing through the second resistor sub-string having a same value as the first constant current.
Still in accordance with the present invention, there is provided a signal processing system including an analog-to-digital converter for converting an analog signal into a digital signal that comprises an input analog signal, a plurality of resistors connected in series for receiving the analog signal, each of the plurality of resistors including a tap end, a plurality of comparators, each of the comparators including a first inverter connected to one of the plurality of resistors at the tap end of the one resistor, and a second inverter connected in series with the first inverter, and a current generator for providing a constant current flowing through the plurality of resistors.
Further in accordance with the present invention, there is provided a method for converting an analog signal into a digital signal that comprises providing a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter, serially connecting a plurality of resistors in a resistor string, the resistor string including a plurality of nodes, electrically connecting the plurality of comparators to the resistor string at the plurality of nodes such that each of the plurality of resistors corresponds to one of the plurality of comparators, and flowing a constant current through the resistor string.
Still in accordance with the present invention, there is provided a method for converting an analog signal into a digital signal that comprises providing a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter, serially connecting a plurality of resistors in a resistor string, the resistor string including a plurality of nodes, electrically connecting the plurality of comparators to the resistor string at the plurality of nodes such that each of the plurality of resistors corresponds to one of the plurality of comparators, selecting a receiving comparator from one of the plurality of comparators for receiving the analog signal at a node of the resistor string without passing through any resistors of the resistor string, separating a first sub-string of the resistor string from a second sub-string of the resistor string at the node, flowing a first constant current through the first sub-string, and flowing a second constant current through the second sub-string having a same value as the first constant current.



BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. For the purposes of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It is understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In the drawings:
FIG. 1A is a diagram of an inverter used in an analog-to-digital converter (“ADC”) in accordance with one embodiment of the present invention;
FIG. 1B is a circuit symbol of the inverter shown in FIG. 1A;
FIG. 1C is a diagram illustrating the transfer function of the inverter shown in FIG. 1A;
FIG. 2A is a diagram of a comparator used in an ADC in accordance with one embodiment of the present invention;
FIG. 2B is a circuit symbol of the comparator shown in FIG. 2A;
FIG. 2C is a diagram illustrating the transfer function of the comparator shown in FIG. 2A;
FIG. 3A is a circuit diagram of an ADC in accordance with one embodiment of the present invention;
FIG. 3B is a circuit diagram of an ADC in accordance with another embodiment of the present invention;
FIG. 3C is a diagram illustrating an equivalent circuit of the ADC shown in FIG. 3A;
FIG. 3D is a diagram illustrating a dynamic transfer function of an inverter of the ADC shown in FIG. 3A;
FIG. 3E is a diagram illustrating a dynamic transfer function of a comparator of the ADC shown in FIG. 3A;
FIG. 4A is a circuit diagram of an ADC in accordance with another embodiment of the present invention;
FIG. 4B is a diagram illustrating an equivalent circuit of the ADC shown in FIG. 4A; and
FIG. 4C is a circuit diagram of an ADC in accordance with still another embodiment of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 1A is a diagram of an inverter 10 used in an analog-to-digital converter (“ADC”) in accordance with one embodiment of the present invention. Referring to FIG. 1A, inverter 10 includes a p-type metal-oxide-semiconductor (“PMOS”) transistor 12 and an n-type metal-oxide-semiconductor (“NMOS”) transistor 14. When an input signal VIN is greater than a switching threshold voltage Vm of inverter 10, PMOS transistor 12 is turned off and NMOS transistor 14 is turned on. The voltage level of an output voltage VO is pulled to low (VO=0). When the input signal VIN is smaller than the switching threshold voltage Vm, PMOS transistor 12 is turned on and NMOS transistor 14 is turned off. The voltage level of the output voltage VO is pushed to high (VO=VDD). FIG. 1B is a circuit symbol of inverter 10, and FIG. 1C is a diagram illustrating the transfer function of inverter 10 shown in FIG. 1A.
FIG. 2A is a diagram of a comparator 20 used in an ADC in accordance with one embodiment of the present invention. Referring to FIG. 2A, comparator 20 includes a first inverter 22 and a second inverter 24 connected in series with first inverter 22. First inverter 22 has a first switching threshold voltage Vm1, and second inverter 24 has a second switching threshold voltage Vm2. In one embodiment according to the present invention, first inverter 22 and second inverter 24 are fabricated in a complementary metal-oxide-semiconductor (“CMOS”) process and have substantially the same size and parameters such as the W/L ratio and the threshold voltages VTp and VTn. As a result, Vm1 is substantially equal to Vm2. In another embodiment, in a comparator array including a plurality of comparators, each of the first and second inverters of the plurality of comparators has substantially the same switching threshold voltage.
In operation, in response to a low-voltage VIN, smaller than the switching threshold voltage Vm1, the output signal VO of first inverter 22 is VDD, which is greater than the switching threshold voltage Vm2, resulting in an output VOUT of comparator 20 at a ground level. On the contrary, in response to a high-voltage VIN, greater than the switching threshold voltage Vm1, the output signal VO of first inverter 22 is ground, which is smaller than the switching threshold voltage Vm2, resulting in an output VOUT of comparator 20 at a VDD level. FIG. 2B is a circuit symbol of comparator 20, and FIG. 2C is a diagram illustrating the transfer function of comparator 20 shown in FIG. 2A.
FIG. 3A is a circuit diagram of an ADC 30 in accordance with one embodiment of the present invention. Referring to FIG. 3A, ADC 30 includes a comparator array 32, a resistor string 34, an encoder 36 and a current generator 31 providing a current flowing through resistor string 34. The number of comparators in comparator array 32 and the number of resistors in resistor string 34 required for an N-bit ADC 30 is 2N, N being an integer. Comparator array 32 includes a plurality of comparators C1 to C(2N), given an N-bit ADC 30. Each of the comparators C1 to C(2N) includes a first inverter and a second inverter connected in series, as shown in FIG. 2A. Resistor string 34 includes a plurality of resistors R1 to R(2N) connected in series. Each of the resistors R1 to R(2N) includes a first end and a second end, and corresponds to one of the comparators C1 to C(2N). Specifically, a first end 34-1 of a first resistor R1 is electrically connected to a first comparator C1, a first end 34-2 of a second resistor R2 is electrically connected to a second comparator C2, and so on. Current generator 31 provides a constant current I flowing through resistor string 34. Encoder 36 encodes the outputs from comparator array 32 to generate an N-bit encoded digital signal. The N-bit digital signal includes binary bit coefficients B1 to BN, each of which has a binary value of either 0 or 1, where B1, represents the most significant bit and BN represents the least significant bit. ADC 30 may further include a sample-and-hold circuit 38 for receiving an input analog signal VIN, and holding the input signal VIN to avoid changing the input signal during the conversion process.
Skilled persons in the art will realize that the number of comparators or resistor may not be limited to 2N, as long as encoder 36 is able to generate an N-bit encoded digital signal. FIG. 3B is a circuit diagram of an ADC 50 in accordance with another embodiment of the present invention. Referring to FIG. 3B, ADC 50 has a similar circuit structure to ADC 30 shown in FIG. 3A except a comparator array 52 and a resistor string 54. Specifically, ADC 30 includes a total number of (2N−1) comparators C2 to C2N in comparator array 52, and a total number of (2N−1) resistors R1 to R(2N−1) in resistor string 54 corresponding to the comparators C2 to C2N, respectively. In still another embodiment, an ADC according to the present invention includes a total number of (2N−1) comparators C1 to C(2N−1) and a total number of (2N−1) resistors R1 to R(2N−1) corresponding to the comparators C1 to C(2N−1), respectively.
FIG. 3C is a diagram illustrating an equivalent circuit of ADC 30 shown in FIG. 3A. Referring to FIG. 3C, given the resistance of each of the resistors R1 to R(2N−1) being R, the voltage levels fed into comparators C1, C2 . . . and C(2N) are VIN, VIN−IR . . . and VIN−(2N−1) IR, respectively. The first comparator C1 then compares the corresponding input voltage level VIN with the switching threshold voltage Vm1 and then Vm2 to determine an output voltage level. Simultaneously, the second comparator C2 compares the corresponding input voltage level VIN−IR with the switching threshold voltage Vm1 and then Vm2. For a comparator disposed downstream with respect to the comparator C1 in the direction of resistor string 34 from resistors R1 to R(2N) and separated from the comparator C1 by a number of M comparators, M being an integer equal to or greater than zero, the corresponding voltage level fed to the comparator is VIN−(M+1) IR. For example, for the comparator C2 disposed immediately adjacent to the comparator C1 and separated from one another by no comparator, i.e., M equals zero, the corresponding voltage level fed to the comparator C2 is VIN−IR. Likewise, for the comparator C(2N) separated from the comparator C1 by a number of (2N−2) comparators, the corresponding voltage level fed to the comparator C2 is VIN−(2N−1) IR.
Referring again to FIG. 3B, for a comparator disposed downstream with respect to a first comparator in the direction of resistor string 54, i.e., the comparator C2, and separated from the comparator C2 by a number of M comparators, the voltage level fed to the comparator is VIN−(M+2) IR.
FIG. 3D is a diagram illustrating a dynamic transfer function of an inverter of ADC 30 shown in FIG. 3A. Referring to FIG. 3D, also referring to FIG. 3A, due to the function of current generator 31 and resistor string 34, the first comparator C1 compares the input voltage level VIN and the switching threshold voltage Vm1 of the first inverter of comparator C1 to determine a voltage level of an output voltage VO. The comparison result for the first inverter of comparator C1 is illustrated in a curve A1. Likewise, the last comparator C(2N) compares the input voltage level (VIN−(2N−1) IR) and Vm1 to determine a voltage level of the output voltage VO. The comparison result for the first inverter of comparator C(2N) is illustrated in a curve A2. For a comparator disposed downstream with respect to the comparator C1 and separated from the comparator C1 by a number of M comparators, an input voltage level (VIN−(M+1) IR) is compared with Vm1. The comparison result of the first inverter of this comparator results in a curve (not shown) dynamically changeable between the curves A1 and A2, depending on the value of M.
FIG. 3E is a diagram illustrating a dynamic transfer function of a comparator of ADC 30 shown in FIG. 3A. Referring to FIG. 3E, the first comparator C1 compares the voltage level VO, which is a function of the input voltage level VIN, and the switching threshold voltage Vm2 of the second inverter of comparator C1, to determine a voltage level of an output voltage VOUT. The comparison result for comparator C1 is illustrated in a curve D1. Likewise, the last comparator C(2N) compares the voltage level VO, which is a function of the input voltage level (VIN−(2N−1) IR), and Vm2 to determine a voltage level of the output voltage VOUT. The comparison result for comparator C(2N) is illustrated in a curve D2. For a comparator disposed downstream with respect to the comparator C1 and separated from the comparator C1 by a number of M comparators, the voltage level VO, which is a function of the input voltage level (VIN−(M+1) IR), is compared with Vm2. The comparison result for the comparator results in a curve (not shown) dynamically changeable between the curves D1 and D2, depending on the value of M.
FIG. 4A is a circuit diagram of an ADC 40 in accordance with another embodiment of the present invention. Referring to FIG. 4A, ADC 40 includes a comparator array 42, a resistor string further including a first sub-string 44 and a second sub-string 45, an encoder 46, a first current generator 41 providing a first current flowing through first sub-string 44, and a second current generator 49 providing a second current flowing through second sub-string 45. The number of comparators in comparator array 42 and the number of resistors in the resistor string required for an N-bit ADC 40 is 2N, N being an integer. Comparator array 42 includes a plurality of comparators C1 to C(2N), given an N-bit ADC 40. Each of the comparators C1 to C(2N) includes a first inverter and a second inverter connected in series, as shown in FIG. 2A. A receiving comparator C(2N−1), which receives an input analog signal VIN through a sample-and-hold circuit 48, divides the resistor string into first sub-string 44 and second sub-string 45. First sub-string 44 is disposed upstream with respect to a point P where the input signal VIN is fed into receiving comparator C(2N−1+1). Second sub-string 45 is disposed downstream with respect to the point P. First sub-string 44 includes a plurality of resistors R1 to R(2N-1) connected in series. Second sub-string 45 includes a plurality of resistors R(2N−1+1) to R(2N) connected in series, and further connected in series with the plurality of resistors of first sub-string 44. Each of the resistors R1 to R(2N) corresponds to one of the comparators C1 to C(2N). First current generator 41 provides a first constant current having an magnitude of I flowing through first sub-string 44. Second current generator 49 provides a second constant current having the magnitude of I flowing through second sub-string 45.
FIG. 4B is a diagram illustrating an equivalent circuit of ADC 40 shown in FIG. 4A. Referring to FIG. 4B, given the resistance of each of the resistors R1 to R(2N) being R, the voltage levels fed to the receiving comparator C(2N−1+1), and comparators C(2N−1) and C(2N−1+2) are VIN, (VIN+IR) and (VIN−IR), respectively. Likewise, the voltage levels fed to comparators C1 and C(2N) are (VIN+C(2N−1) IR) and (VIN−C(2N−1−1) IR), respectively. That is, for a comparator disposed upstream with respect to the receiving comparator C(2N−1+1) and separated from the receiving comparator C(2N−1+1) by a number of T comparators, the voltage level fed thereto is (VIN+T×IR), T being an integer equal to or greater than zero. On the other hand, for a comparator disposed downstream with respect to the receiving comparator C(2N−1+1) and separated from the receiving comparator C(2N−1+1) by a number of T comparators, the voltage level fed thereto is (VIN−T×IR).
FIG. 4C is a circuit diagram of an ADC 60 in accordance with still another embodiment of the present invention. Referring to FIG. 4C, ADC 60 has a similar circuit structure to ADC 40 shown in FIG. 4A except a comparator array 62, first sub-string 64 and second sub-string 65. Specifically, ADC 60 includes a total number of (2N−1) comparators C2 to C2N in comparator array 62, and a total number of (2N−1) resistors R1 to R(2N−1) in first sub-string 64 and second sub-string 65 corresponding to the comparators C2 to C2N, respectively. The comparator C(2N−1) is chosen to receive the input signal VIN through sample-and-hold circuit 48. As a result, the number of upstream resistors is equal to that of downstream resistors. For a comparator disposed upstream with respect to the receiving comparator C(2N−1) and separated from the receiving comparator C(2N−1) by a number of T comparators, the voltage level fed thereto is (VIN+T×IR). Furthermore, for a comparator disposed downstream with respect to the receiving comparator C(2N−1) and separated from the receiving comparator C(2N−1) by a number of T comparators, the voltage level fed thereto is (VIN−T×IR).
It will be appreciated by those skilled in the art that changes could be made to the preferred embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but is intended to cover modifications within the spirit and scope of the present application as defined by the appended claims.

## Claims

1. An analog-to-digital converter device for converting an analog signal into a digital signal, comprising:
a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter;
a resistor string including a plurality of resistors connected in series, each of the resistors corresponding to one of the plurality of comparators; and
a current generator for providing a constant and equal current flowing through each resistor of the resistor string.

2. The device of claim 1, wherein the first inverters of the plurality of comparators have the same switching threshold voltage.

3. The device of claim 1, wherein the second inverters of the plurality of comparators have the same switching threshold voltage.

4. The device of claim 1, wherein each of the first inverters has the same a same switching threshold voltage as each of the second inverters of the plurality of comparators.

5. The device of claim 1, wherein one of the plurality of comparators is disposed most upstream with respect to other comparators in a direction of the constant current flow, and wherein for a comparator of the plurality of comparators separated from the most upstream comparator by a number of M comparators, M being an integer equal to or greater than zero, a voltage level fed to the comparator is VIN−(M+1) IR, where VIN is a voltage level of the analog signal, I is the magnitude of the constant current, and R is the resistance of each of the resistors.

6. The device of claim 5, wherein the digital signal is an N-bit signal, N being an integer, and wherein the comparator compares a switching threshold voltage level Vm with a voltage level of the analog signal ranging from Vm to Vm+(2N−1) IR.

7. The device of claim 1, wherein one of the plurality of comparators is disposed most upstream with respect to other comparators in a direction of the constant current flow, and wherein for a comparator of the plurality of comparators separated from the most upstream comparator by a number of M comparators, M being an integer equal to or greater than zero, a voltage level fed to the comparator is VIN−(M+2) IR, where VIN is a voltage level of the analog signal, I is the magnitude of the constant current, and R is the resistance of each of the resistors.

8. The device of claim 7, wherein the digital signal is an N-bit signal, N being an integer, and wherein the comparator compares a switching threshold voltage level Vm with a voltage level of the analog signal ranging from Vm to Vm+(2N−1) IR.

9. An analog-to-digital converter device for converting an analog signal into a digital signal, comprising:
a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter;
a resistor string including a plurality of resistors, each of the resistors corresponding to one of the plurality of comparators;
a receiving comparator selected from one of the plurality of comparators for receiving the analog signal at a node of the resistor string without passing through any resistors of the resistor string;
a first sub-string of the resistor string being separated from a second sub-string of the resistor string at the node;
a first current generator for providing a first constant current flowing through the first sub-string; and
a second current generator for providing a second constant current flowing through the second sub-string, the second constant current having the same value as the first constant current.

10. The device of claim 9, wherein the first inverters of the plurality of comparators have the same switching threshold voltage.

11. The device of claim 9, wherein the second inverters of the plurality of comparators have the same switching threshold voltage.

12. The device of claim 9, wherein each of the first inverters has the same switching threshold voltage as each of the second inverters of the plurality of comparators.

13. The device of claim 9, wherein the number of resistors of the first sub-string is equal to the number of the resistors of the second sub-string.

14. The device of claim 9, wherein for a comparator disposed upstream with respect to the receiving comparator in a direction of the first or second constant current flow and separated from the receiving comparator by a number of T comparators, a voltage level fed to the comparator is VIN+T×IR, where VIN is a voltage level of the analog signal, T is an integer equal to or greater than zero, I is the value of the first or second constant current, and R is the resistance of each of the resistors of the resistor string.

15. The device of claim 9, wherein for a comparator disposed downstream with respect to the receiving comparator in a direction of the first or second constant current flow and separated from the receiving comparator by a number of T comparators, a voltage level fed to the comparator is VIN−T×IR, where VIN is a voltage level of the analog signal, T is an integer equal to or greater than zero, I is the value of the first or second constant current, and R is the resistance of each of the resistors of the resistor string.

16. A signal processing system including an analog-to-digital converter for converting an analog signal into a digital signal, comprising:
an input analog signal;
a plurality of resistors connected in series for receiving the analog signal, each of the plurality of resistors including a tap end;
a plurality of comparators, each of the comparators including a first inverter connected to one of the plurality of resistors at the tap end of the one resistor, and a second inverter connected in series with the first inverter; and
a current generator for providing a constant and equal current flowing through each of the plurality of resistors.

17. The system of claim 16, wherein each of the first inverters and each of the second inverters have substantially the same switching threshold voltage.

18. The system of claim 16, wherein one of the plurality of comparators is disposed most upstream with respect to other comparators in a direction of the constant current flow, and wherein for a comparator of the plurality of comparators separated from the most upstream comparator by a number of M comparators, M being an integer equal to or greater than zero, a voltage level fed to the comparator is VIN−(M+1) IR, where VIN is a voltage level of the analog signal, I is the magnitude of the constant current, and R is the resistance of each of the resistors.

19. The system of claim 16, wherein the digital signal is an N-bit signal, N being an integer, and wherein the comparator compares a switching threshold voltage level Vm with a voltage level of the analog signal ranging from Vm to Vm+(2N−1) IR.

20. The system of claim 16, wherein one of the plurality of comparators is disposed most upstream with respect to other comparators in a direction of the constant current flow, and wherein for a comparator of the plurality of comparators separated from the most upstream comparator by a number of M comparators, M being an integer equal to or greater than zero, a voltage level fed to the comparator is VIN−(M+2) IR, where VIN is a voltage level of the analog signal, I is the magnitude of the constant current, and R is the resistance of each of the resistors.

21. A method for converting an analog signal into a digital signal, comprising:
providing a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter;
serially connecting a plurality of resistors in a resistor string, the resistor string including a plurality of nodes;
electrically connecting the plurality of comparators to the resistor string at the plurality of nodes such that each of the plurality of resistors corresponds to one of the plurality of comparators; and
flowing a constant and equal current through each resistor of the resistor string.

22. The method of claim 21, further comprising providing the plurality of comparators with the same first inverters.

23. The method of claim 21, further comprising providing the plurality of comparators with the same second inverters.

24. The method of claim 21, further comprising providing the first inverters and second inverters of the plurality of comparators with the same switching threshold voltage.

25. The method of claim 21, further comprising:
determining that one of the plurality of comparators is disposed most upstream with respect to other comparators in a direction of the constant current flow; wherein
for a comparator of the plurality of comparators separated from the most upstream comparator by a number of M comparators, M being an integer equal to or greater than zero, feeding a voltage level of (VIN−(M+2) IR) to the comparator, where VIN is a voltage level of the analog signal, I is the value of the constant current, and R is the resistance of each of the resistors.

26. A method for converting an analog signal into a digital signal, comprising:
providing a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter;
serially connecting a plurality of resistors in a resistor string, the resistor string including a plurality of nodes;
electrically connecting the plurality of comparators to the resistor string at the plurality of nodes such that each of the plurality of resistors corresponds to one of the plurality of comparators;
selecting a receiving comparator from one of the plurality of comparators for receiving the analog signal at a node of the resistor string without passing through any resistors of the resistor string;
separating a first sub-string of the resistor string from a second sub-string of the resistor string at the node;
flowing a first constant current through the first sub-string; and
flowing a second constant current through the second sub-string, the second constant current having the same value as the first constant current.

27. The method of claim 26, further comprising providing the plurality of comparators with the same first inverters.

28. The method of claim 26, further comprising providing the plurality of comparators with the same second inverters.

29. The method of claim 26, further comprising providing the first inverters and second inverters of the plurality of comparators with the same switching threshold voltage.

30. The method of claim 26, further comprising providing the same number of resistors to the first sub-string and the second sub-string.

31. The method of claim 26, wherein
for a comparator disposed upstream with respect to the receiving comparator in a direction of the first or second constant current flow and separated from the receiving comparator by a number of T comparators, feeding a voltage level of (VIN+T×IR) to the comparator, where VIN is a voltage level of the analog signal, T is an integer equal to or greater than zero, I is the value of the first or second constant current, and R is the resistance of each of the resistors of the resistor string.

32. The method of claim 26, wherein
for a comparator disposed downstream with respect to the receiving comparator in a direction of the first or second constant current flow and separated from the receiving comparator by a number of T comparators, feeding a voltage level of (VIN−T×IR) to the comparator, where VIN is a voltage level of the analog signal, T is an integer equal to or greater than zero, I is the value of the first or second constant current, and R is the resistance of each of the resistors of the resistor string.