# Patent

## Title
Method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device

## Abstract

A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device is disclosed. According to the method of measuring flat-band status capacitance of gate oxide in MOS transistor device, flat-band status capacitance of gate oxide in MOS transistor device can be automatically measured and immediately analyzed by using a characteristics measuring system that changes in accordance with a gate voltage.

## Background
RELATED APPLICATION 
This application is based upon and claims the benefit of priority to Korean Application No. 10-2005-0133222 filed on Dec. 29, 2005, the entire contents of which are incorporated herein by reference.
BACKGROUND
1. Technical Field
The present invention relates to a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device.
2. Discussion of Related Art
Flat-band status in a MOS transistor device structure refers to a state wherein the voltage is supplied at a gate so that the band is not bent and the charge of a spatial area is “0” in an energy band structure between a gate electrode, a gate oxide, and a channel area of a MOS transistor device.
Gate voltage for forming flat-band status is “0” in an ideal MOS transistor device structure, but the real result are different.
Flat-band status of an energy band of a MOS transistor device is determined to be flat through the measurement of a capacitance of a gate. In the related art, a method of measuring flat-band status capacitance is based on a passive measurement result.
But capacitance may not always be accurately identified and the malfunction status thereof may be tested during a semiconductor manufacturing process because the method may not be applied in a DC parametric measurement among controlled semiconductor manufacturing processes. Accordingly, there is a problem that because malfunction situations were identified through malfunction analysis only after all of the manufacturing processes were completed and the malfunction status was generated, it took a long time to cope with the malfunction situations.
BRIEF SUMMARY
Consistent with the present invention there is provided a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device that is capable of using and applying general test pattern for measuring the depth of a gate oxide regardless of designing a new measuring pattern and performing measurement and analysis operations by using an automatic measuring unit.
Consistent with the present invention there is provided a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device where analysis can be performed in a DC parametric measurement test implemented in a production step of semiconductor products if a program using control test unit of a DC parametric system is applied therefore, malfunction of wafer at an early semiconductor process can be detected.
Consistent with the present invention, there is provided a method of measuring flat-band status capacitance of gate oxide in MOS transistor device comprising, mounting a measurement object wafer in a probe station connected to a capacitance measuring unit; measuring accumulation capacitance (Cox) of a gate oxide of the wafer using the capacitance measuring unit; measuring capacitance (Cmeas) from the gate while changing a gate voltage (Vgs) of the wafer using the capacitance measuring unit; computing the thickness of a depletion layer (Winv) using the measured accumulation capacitance (Cox) and the measured gate capacitance (Cmeas); computing bulk density (Nx) on the basis of the gate voltage (Vgs) in the case that depth of a depletion layer is 90% of a predetermined reference depth; computing debye length LD using the bulk density (Nx); and computing flat-band status capacitance using the accumulation capacitance (Cox) of the gate oxide and the debye length LD.
It is to be understood that both the foregoing general description and the following detailed description consistent with the present invention are exemplary and explanatory and are intended to provide further explanation consistent with the invention as claimed.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are included to provide a further understanding consistent with the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) consistent with the invention and together with the description serve to explain the principle consistent with the invention. In the drawings:
FIGS. 1a and 1b are diagrams showing a characteristic measuring system of a MOS transistor device used in a measuring method consistent with the present invention.



DETAILED DESCRIPTION
Reference will now be made in detail to the preferred embodiments consistent with the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.
Hereinafter, a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device in accordance with an exemplary embodiment consistent with the present invention will be explained with reference to the accompanying drawings.
In an explanation in accordance with an exemplary embodiment consistent with the present invention, an expression “on” means that something is formed directly on another thing or indirectly formed by intervening in another layer in case of disclosing the formation “on” respective layers.
FIGS. 1a and 1b are diagrams showing a characteristic measuring system of a MOS transistor device used in a measuring method consistence with the present invention.
FIG. 1a is an example of a system for measuring carrier density distribution of a MOS transistor device using an Automatic Test System in a Manual Test System. In the case of measurement and analysis, except for mechanical operations such as loading a wafer at a Probe Station in the Manual Test System, the present invention can be applied and thus the procedure can be automated.
In addition, FIG. 1b is an example embodying a system for measuring carrier density distribution of a MOS transistor device using an Automatic Test System in an automatic DC Parametric Test System.
Referring to FIGS. 1a and 1b, a measurement object wafer 10 is positioned on a chuck 21 inside of a probe station 20. A high frequency terminal 31 of a capacitance measuring unit 30 (specifically, LCR meter) is connected to a gate 11 of wafer 10, and a low frequency terminal 32 is connected to a substrate 12 of wafer 10. Probe station 20 and capacitance measuring unit 30 are respectively connected to a control computer 40.
Probe station 20 of FIG. 1a is connected to a measuring device (not shown) using a probe, and probe station 20 of FIG. 1b uses a probe card 22.
Probe station 20 is shielded from external influences using a dark box or a shielding box in order to prevent distortion of data measured by an external light or by electromagnetic waves.
The following is a description of a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device in accordance with an exemplary embodiment consistent with the present invention.
Wafer 10 is mounted inside of probe station 20, and an electrical connection by the probe or the probe card is achieved.
A high frequency (10 KHz ̃1 MHz) is adjusted as a reference frequency of capacitance measuring unit 30. A gate channel area becomes in an accumulation state by DC voltage and the capacitance (Cox) of a gate oxide 13 is measured.
While changing a high frequency terminal voltage (Vgs) of the capacitance measuring unit in order to enable the gate channel area to be in an inversion state through a depletion state from an accumulation state.
Capacitance (Cmeas) corresponding to gate voltages (Vgs) is measured and recorded at gate 11 while changing a high frequency terminal voltage of capacitance measuring unit 30 in order to enable the gate channel of the MOS transistor device to be an inversion state through a depletion state from an accumulation state.
Depth Winv of depletion layer is obtained by the measured capacitance (Cmeas). The depth Winv of the depletion layer is computed by Equations 1 and 2.




  
    
      
        
          1
          
            C
            meas
          
        
        =
        
          
            1
            
              C
              ox
            
          
          +
          
            1
            
              C
              siinv
            
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          1
        
        ]
      
    
  
  
    
      
        
          
            W
            inv
          
          =
          
            A
            ⁢
            
              
            
            ⁢
            
              ɛ
              si
            
            ⁢
            
              
                ɛ
                0
              
              ⁡
              
                (
                
                  
                    1
                    
                      C
                      meas
                    
                  
                  -
                  
                    1
                    
                      C
                      ox
                    
                  
                
                )
              
            
          
        
        ,
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          2
        
        ]
      
    
  




In Equations 1 and 2, Cmeas denotes capacitance measured at a gate terminal regarding gate voltages, Csiinv and Winv respectively denote the capacitance and the thickness of a depletion layer washed off the silicon surface by a gate voltage and εsi denotes relative dielectric constant of a silicon.
The doping density of substrate 12 and bulk doping density (Nx) is defined as a value measured in the case that depth of a depletion layer is 90% of a reference when maximum value of the depth of the depletion layer serves as the reference. Therefore, the bulk doping density (Nx) is computed on the basis of the gate voltage (Vgs) in the case that depth of a depletion layer is 90% of a reference.
The bulk doping density (Nx) is obtained by Equation 3.




  
    
      
        
          N
          x
        
        =
        
          
            
              
                
                  -
                  2
                
                ⁢
                
                  
                    (
                    
                      1
                      -
                      
                        
                          C
                          q
                        
                        /
                        
                          C
                          ox
                        
                      
                    
                    )
                  
                  /
                  
                    (
                    
                      1
                      -
                      
                        
                          C
                          meas
                        
                        /
                        
                          C
                          ox
                        
                      
                    
                    )
                  
                
              
              
                
                  A
                  2
                
                ⁢
                q
                ⁢
                
                  
                
                ⁢
                
                  ɛ
                  si
                
                ⁢
                
                  ɛ
                  0
                
              
            
            ⁡
            
              [
              
                
                  partial
                  
                    partialV
                    gs
                  
                
                ⁢
                
                  (
                  
                    1
                    
                      C
                      meas
                      2
                    
                  
                  )
                
              
              ]
            
          
          
            -
            1
          
        
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        ]
      
    
  




In Equation 3, a debye length LD is computed using the computed bulk doping density (Nx).




  
    
      
        
          
            L
            D
          
          =
          
            
              (
              
                1
                ×
                
                  10
                  4
                
              
              )
            
            ⁢
            
              
                
                  
                    ɛ
                    0
                  
                  ⁢
                  
                    ɛ
                    si
                  
                  ×
                  kT
                
                
                  
                    q
                    2
                  
                  ⁢
                  
                    N
                    x
                  
                
              
            
          
        
        ,
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          4
        
        ]
      
    
  




In Equation 4, kT denotes the heat energy at room temperature and q denotes the quantity of an electric charge (1.60219×10−19 C) of an electron.
Flat-band capacitance (Cfb, units in picofarads) is computed using the data. That is, it is obtained by Equation 5 using the measured accumulation capacitance (Cox, unit of pF) of a gate oxide and the debye length LD.




  
    
      
        
          
            C
            fb
          
          =
          
            
              
                C
                ox
              
              ×
              
                ɛ
                0
              
              ⁢
              
                ɛ
                si
              
              ×
              
                A
                /
                
                  (
                  
                    1
                    ×
                    
                      10
                      
                        -
                        4
                      
                    
                  
                  )
                
              
              ⁢
              
                L
                D
              
            
            
              
                
                  (
                  
                    1
                    ×
                    
                      10
                      
                        -
                        12
                      
                    
                  
                  )
                
                ⁢
                
                  C
                  ox
                
              
              +
              
                
                  ɛ
                  0
                
                ⁢
                
                  ɛ
                  si
                
                ×
                
                  A
                  /
                  
                    (
                    
                      1
                      ×
                      
                        10
                        
                          -
                          4
                        
                      
                    
                    )
                  
                
                ⁢
                
                  L
                  D
                
              
            
          
        
        ,
      
    
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          5
        
        ]
      
    
  




In Equation 5, A denotes an area of the gate oxide.
As described above, according to a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device, the flat-band status capacitance of a gate oxide in a MOS transistor device can be automatically measured and immediately analyzed by using a characteristic measuring system that changes in accordance with a gate voltage.
Thus, according to a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device, because carrier density distribution of a channel area can be analyzed not through physical property or chemical analysis but an electrical nondestructive inspection, embodying the measurement pattern of a MOS structure having a proper area, loss of wafer specimen can be prevented.
In addition, according to a method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device consistent with the present invention, because analysis can be performed in a DC parametric measurement test implemented in a production step of semiconductor, malfunction of wafer at an early semiconductor process can be detected.
It will be apparent to those skilled in the art that various modifications may be made without departing from the spirit and scope consistent with the invention as defined by the appended claims.

## Claims

1. A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device, comprising:
mounting a measurement object wafer in a probe station connected to a capacitance measuring unit;
measuring accumulation capacitance (Cox) of a gate oxide of the wafer using the capacitance measuring unit;
measuring capacitance (Cmeas) from the gate while changing a gate voltage (Vgs) of the wafer using the capacitance measuring unit;
computing the thickness of a depletion layer (Winv) using the measured accuulation capacitance (Cox) and the measured gate capacitance (Cmeas);
computing bulk density (Nx) on the basis of the gate voltage (Vgs) in the case that the depth of a depletion layer is 90% of a predetermined reference depth;
computing debye length LD using the bulk density (Nx); and
computing flat-band status capacitance using the accumulation capacitance (Cox) of the gate oxide and the debye length LD.

2. The method according to claim 1, wherein measuring accumulation capacitance (Cox) of a gate oxide is performed by adjusting a reference frequency of the capacitance measuring unit as a high frequency and enabling a gate channel area to be in an accumulation state by DC voltage.

3. The method according to claim 1, wherein measuring capacitance (Cmeas) from the gate is performed by changing a high frequency terminal voltage Vgs of the capacitance measuring unit in order to enable the gate channel area to be in an inversion state through a depletion state from an accumulation state.

4. The method according to claim 1, wherein computing the thickness of a depletion layer (Winv) is computed by the equation,




  
    
      1
      
        C
        meas
      
    
    =
    
      
        
          1
          
            C
            ox
          
        
        +
        
          
            1
            
              C
              siinv
            
          
          ⁢
          
            
          
          ⁢
          and
          ⁢
          
            
          
          ⁢
          
            W
            inv
          
        
      
      =
      
        A
        ⁢
        
          
        
        ⁢
        
          ɛ
          si
        
        ⁢
        
          
            ɛ
            0
          
          ⁡
          
            (
            
              
                1
                
                  C
                  meas
                
              
              -
              
                1
                
                  C
                  ox
                
              
            
            )
          
        
      
    
  
  ,



wherein, Csiinv denotes capacitance of a depletion layer washed off a surface of the wafer by a gate voltage, A denotes an area of the gate oxide, εsi denotes relative dielectric constant of silicon, and ε0 denotes dielectric constant in a vacuum state.

5. The method according to claim 1, wherein computing bulk density (Nx) is computed by an equation below,




  
    
      N
      x
    
    =
    
      
        
          
            
              -
              2
            
            ⁢
            
              
                (
                
                  1
                  -
                  
                    
                      C
                      q
                    
                    /
                    
                      C
                      ox
                    
                  
                
                )
              
              /
              
                (
                
                  1
                  -
                  
                    
                      C
                      meas
                    
                    /
                    
                      C
                      ox
                    
                  
                
                )
              
            
          
          
            
              A
              2
            
            ⁢
            q
            ⁢
            
              
            
            ⁢
            
              ɛ
              si
            
            ⁢
            
              ɛ
              0
            
          
        
        ⁡
        
          [
          
            
              partial
              
                partialV
                gs
              
            
            ⁢
            
              (
              
                1
                
                  C
                  meas
                  2
                
              
              )
            
          
          ]
        
      
      
        -
        1
      
    
  
  ,



wherein, q denotes the quantity of electric charge (1.60219×10−9 C) of an electron and Cq is a quasi-static capacitance of the gate oxide.

6. The method according to claim 1, wherein computing debye length LD is computed by an equation below,




  
    
      L
      D
    
    =
    
      
        (
        
          1
          ×
          
            10
            4
          
        
        )
      
      ⁢
      
        
          
            
              ɛ
              0
            
            ⁢
            
              ɛ
              si
            
            ×
            kT
          
          
            
              q
              2
            
            ⁢
            
              N
              x
            
          
        
      
    
  
  ,



wherein, kT denotes the heat energy at room temperature.

7. The method according to claim 1, wherein flat-band status capacitance is computed by the following equation below,




  
    
      C
      fb
    
    =
    
      
        
          C
          ox
        
        ×
        
          ɛ
          0
        
        ⁢
        
          ɛ
          si
        
        ×
        
          A
          /
          
            (
            
              1
              ×
              
                10
                
                  -
                  4
                
              
            
            )
          
        
        ⁢
        
          L
          D
        
      
      
        
          
            (
            
              1
              ×
              
                10
                
                  -
                  12
                
              
            
            )
          
          ⁢
          
            C
            ox
          
        
        +
        
          
            ɛ
            0
          
          ⁢
          
            ɛ
            si
          
          ×
          
            A
            /
            
              (
              
                1
                ×
                
                  10
                  
                    -
                    4
                  
                
              
              )
            
          
          ⁢
          
            L
            D
          
        
      
    
  
  ,



wherein, A denotes an area of the gate oxide, Cox denotes accumulation capacitance of a gate oxide, LD denotes debye length, εsi denotes relative dielectric constant of a silicon and ε0 denotes dielectric constant in a vacuum state.