# Patent

## Title
Voltage regulator which provides sequentially and arbitrarrily shaped regulated voltage and related method

## Abstract

A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a voltage regulator and related method, and more particularly, to a voltage regulator which provides sequentially and arbitrarily shaped regulated voltage and related method.
2. Description of the Prior Art
In electronic products, voltage regulators are usually disposed between a power supply circuit and a load circuit. The function of a voltage regulator is to provide a stable output voltage and a wide-ranged output current. When the load current suddenly changes, the output voltage can then be stabilized at its original level for providing efficient voltage conversion. For portable devices such as mobile phones, personal digital assistants (PDAs) and notebook computers, the voltage of the battery drops with time and is unable to maintain at a stable level. A low dropout (LDO) regulator can continuously provide a stable output voltage to the load circuit of an electronic device as long as the voltage difference between the input voltage provided by the battery and the estimated output voltage of the LDO regulator is larger than a dropout voltage.
Reference is made to FIG. 1 for a diagram illustrating a prior art LDO regulator 10. The LDO regulator 10 includes an error amplifier 110, a power device 120, a voltage-dividing circuit 130, and an output capacitor Co. The LDO regulator 10 is configured to convert an input voltage VIN into an output voltage VOUT for driving a load (represented by a resistor RL) through which a current IL flows. The voltage-dividing circuit 130, including resistors R1 and R2, is configured to generate a feedback voltage VFB corresponding to the output voltage VOUT by voltage-dividing the output voltage VOUT. The error amplifier 110 is configured to generate a control signal VSW by comparing the feedback voltage VFB with a reference voltage VREF. The output capacitor Co, coupled in parallel with the load RL, provides the load RL with current compensation when the load current IL suddenly changes, thereby improving the transient response of the output voltage VOUT. The power device 120 may be a P-channel metal oxide semiconductor (PMOS) switch having a gate for receiving the control signal VSW from the error amplifier 110, a source for receiving the input voltage VIN, and a drain for receiving the output voltage VOUT. When the feedback voltage VFB is smaller than the reference voltage VREF, the control signal VSW generated by the error amplifier 110 increases the output current of the power device 120; when the feedback voltage VFB is larger than the reference voltage VREF, the control signal VSW generated by the error amplifier 110 decreases the output current of the power device 120. Therefore, the LDO regulator can stabilize the output voltage VOUT at a predetermined value VOUT—NON. The relationship between the output voltage VOUT and the reference voltage VREF is depicted as follows:

VOUT=(R1+R2)*VREF/R1 

where (R1+R2)/R1 has a constant value.
In a modern wireless transceiver, its receiver RX and transmitter TX operate alternatively, in which only one of the receiver RX and the transmitter TX is activated at a specific time. The transmitter TX is activated only during the transmitting bursts of communication packages, and is otherwise deactivated in order to reduce power consumption. The transmitter TX is required to provide output signal of unvarying characteristics (such as constant output power and phase) anytime during a transmitting burst. However, the circuit of the transmitter TX (such as a power amplifier) has a certain turn-on response time and a certain turn-off response time, both of which normally vary with temperature. In order to maintain unvarying signal characteristics, the time response of the transmitter needs to be compensated by, for instance, adjusting the bias voltage of the transmitter TX or the supply voltage of the receiver RX as the time elapses. In both cases, the bias voltage and the supply voltage are normally generated by the voltage regulator.
Reference is made to FIG. 2 for a diagram illustrating the operation of a prior art wireless transceiver. The waveforms depicted in FIG. 2 represent the bias voltage of the transmitter TX or the supply voltage of the receiver RX provided by the LDO regulator 10. The transmitting bursts of the transmitter TX are represented by BT1-BTn, while the receiving bursts of the receiver RX are represented by BR1-BRn. As previously stated, the turn-on response time and the turn-off response time of the transmitter TX and the receiver RX vary with temperature. Since the prior art LDO regulator 10 does not provide compensation, the prior art wireless transceiver may not be able to provide unvarying signal characteristics during the transmitting/receiving bursts of different communication packages.
SUMMARY OF THE INVENTION
The present invention provides a voltage regulator which provides sequentially and arbitrarily shaped regulated voltage. The voltage regulator comprises an amplifier, a power device, and a voltage-generating circuit. The amplifier is coupled to a reference voltage and a feedback voltage for generating a control signal, the amplifier comprising a first input end coupled to the reference voltage; a second input end coupled to the feedback voltage; and an output end for outputting the control signal. The power device comprises a first input end coupled to an input voltage; a second input end coupled to the output voltage; and a control end coupled to the control signal. The delay signal generator is coupled to an externally applied power-on burst signal for generating a plurality of sequential delay signals each having distinct delay time with respect to the power-on burst signal. The voltage-generating circuit is coupled to the output voltage and the plurality of sequential delay signals for generating the feedback voltage.
The present invention further provides a method for sequentially and arbitrarily regulating an output voltage. The method comprises generating a plurality of sequential delay signals according to an externally applied power-on burst signal, wherein each sequential delay signal has a distinct delay time with respect to the power-on burst signal; adjusting an equivalent resistance according to the plurality of sequential delay signals; generating a feedback voltage by voltage-dividing the output voltage according to the equivalent resistance; and regulating the output voltage according to the feedback voltage.
The present invention further provides a voltage regulator which sequentially and arbitrarily regulates an output voltage. The voltage regulator generates a plurality of sequential delay signals according to an externally applied power-on burst signal, each sequential delay signal having a distinct delay time with respect to the power-on burst signal. And the voltage regulator regulates the output voltage according to the plurality of sequential delay signals so as to maintain the output voltage at a predetermined level at a specific time.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a prior art LDO regulator 10.
FIG. 2 is a diagram illustrating the operation of a prior art wireless transceiver.
FIG. 3 is a diagram illustrating an LDO regulator according to the present invention.
FIG. 4 is a diagram illustrating a voltage-generating circuit according to present invention.
FIG. 5 is a diagram illustrating a delay signal generator according to the present invention.
FIG. 6 is a timing diagram illustrating the operation of the LDO regulator in FIG. 3.



DETAILED DESCRIPTION
Reference is made to FIG. 3 for a diagram illustrating an LDO regulator 30 according to the present invention. The LDO regulator 30 includes an error amplifier 310, a power device 320, a voltage-generating circuit 330, a delay signal generator 340, and an output capacitor Co. The LDO regulator 30 is configured to convert an input voltage VIN into an output voltage VOUT for driving a load (represented by a resistor RL) through which a current IL flows. The output capacitor Co, coupled in parallel with the load RL, provides the load RL with current compensation when the load current IL suddenly changes, thereby improving the transient response of the output voltage VOUT. The voltage-generating circuit 330 is configured to generate a feedback voltage VFB corresponding to the output voltage VOUT (VOUT=K*VREF) by voltage-dividing the output voltage VOUT. The error amplifier 310 is configured to generate a control signal VSW by comparing the feedback voltage VFB with a reference voltage VREF. The power device 320 may be, but not limited to, a PMOS switch having a gate for receiving the control signal VSW from the error amplifier 310, a source for receiving the input voltage VIN, and a drain for receiving the output voltage VOUT. The power device 320 operates according to the control signal VSW: when the feedback voltage VFB is smaller than the reference voltage VREF, the control signal VSW generated by the error amplifier 310 increases the output current of the power device 320; when the feedback voltage VFB is larger than the reference voltage VREF, the control signal VSW generated by the error amplifier 310 decreases the output current of the power device 320.
The delay signal generator 340, which operates according to an externally applied power-on burst signal POWER_ON_BURST, is configured to generate a plurality of delay signals DLY1-DLYn each having distinct delay time with respect to the power-on burst signal POWER_ON_BURST. The voltage-generating circuit 330 can adjust the predetermined value of the output voltage Vour at different time by varying the value of K according to the delay signals DLY1-DLYn, thereby regulating the waveform of the output voltage VOUT.
Reference is made to FIG. 4 for a diagram illustrating the voltage-generating circuit 330 according to present invention. In this embodiment, the voltage-generating circuit 330, including two resistor circuits 331 and 332, is configured to receive the output voltage Vour at a node N1, voltage-divide the output voltage VOUT, and output the corresponding feedback voltage VFB at a node N2. With REQ1 and REQ2 respectively representing the equivalent resistance of the resistor circuits 331 and 332, the relationship between the output voltage VOUT and the reference voltage VREF is depicted as follows:

VOUT=(R1+R2)*VREF/REQ1=K*VREF,

where K=(REQ1+REQ2)*REQ1 
The resistor circuit 331, coupled between the nodes N1 and N2, includes a resistor R1 which determines the equivalent resistance REQ1 of the resistor circuits. The resistor circuit 332, coupled between the node N2 and ground, includes (n+1) resistors R20-R2n and n switches SW1-SWn. The switches SW1-SWn respectively operate according to the delay signals DLY1-DLYn received from the delay signal generator 240. The equivalent resistance REQ2 of the resistor circuit 332 is determined by the resistors R20-R2n, as well as by the number of turned-on switches in the switches SW1-SWn. For example, if all of the switches SW1-SWn are turned off (open-circuited), the value of the equivalent resistance REQ2 is infinite; if all of the switches SW1-SWn are turned on (short-circuited), the value of the equivalent resistance REQ2 is equal to




  
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Therefore, the present invention can adjust the predetermined value of the output voltage Vour at different time by varying the value of K according to the delay signals DLY1-DLYn, thereby regulating the waveform of the output voltage VOUT. In the embodiment depicted in FIG. 4, the resistor circuit 331 provides a constant equivalent resistance REQ1, while the resistor circuit 332 provides an adjustable equivalent resistance REQ2. In another embodiment of the present invention, the resistor circuit 331 may provide an adjustable equivalent resistance REQ1, while the resistor circuit 332 may provide a constant equivalent resistance REQ2. Or, the resistor circuit 331 may provide an adjustable equivalent resistance REQ1, and the resistor circuit 332 may also provide an adjustable equivalent resistance REQ2. The circuit depicted in FIG. 4 is only for illustrative purpose and does not limit the scope of the present invention.

Reference is made to FIG. 5 for a diagram illustrating the delay signal generator 340 according to the present invention. In this embodiment, the delay signal generator 340 includes n inverters INV1-INVn coupled in series, thereby capable of generating n delay signals DLY1-DLYn each having distinct delay time with respect to the power-on burst signal POWER_ON_BURST. The circuit depicted in FIG. 5 is only for illustrative purpose and does not limit the scope of the present invention.
Reference is made to FIG. 6 for a timing diagram illustrating the operation of the LDO regulator 30 according to the present invention. FIG. 6 shows the power-on burst signal POWER_ON_BURST, the delay signals DLY1-DLYn, the equivalent resistance REQ2 and the output voltage VOUT. For ease of illustration, assume that a constant delay time ΔT exists between two consecutive delay signals among the delay signals DLY1-DLYn, and each resistor in the voltage-generating circuit 330 has an identical resistance R. In the embodiment illustrated in FIG. 6, the delay signals DLY1-DLYn sequentially turn on the switches SW1-SWn: when the delay signal DLY1 switches from low level to high level, REQ2=2R; when the delay signal DLY2 switches from low level to high level, REQ2=3R/2; when the delay signal DLY3 switches from low level to high level, REQ2=4R/3; . . . ; when the delay signal DLYn switches from low level to high level, REQ2=(1+1/n) R. In other words, the output voltage VOUT, having a highest initial value, reaches a stable level as the value of K gradually decreases, thereby capable of regulating the output voltage VOUT with different delay time.
The LDO regulator of the present invention operates according to an externally applied power-on burst signal, and is configured to generate a plurality of delay signals each having distinct delay time with respect to the power-on burst signal. The predetermined value of the output voltage at different time can be adjusted accordingly for providing a stable output voltage or an arbitrarily shaped regulated output voltage.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

## Claims

1. A voltage regulator which provides sequentially and arbitrarily shaped regulated voltage, the voltage regulator comprising:
an amplifier coupled to a reference voltage and a feedback voltage for generating a control signal, the amplifier comprising:
a first input end coupled to the reference voltage;
a second input end coupled to the feedback voltage; and
an output end for outputting the control signal;

a power device comprising:
a first input end coupled to an input voltage;
a second input end coupled to the output voltage; and
a control end coupled to the control signal;

a delay signal generator coupled to an externally applied power-on burst signal for generating a plurality of sequential delay signals each having distinct delay time with respect to the power-on burst signal; and
a voltage-generating circuit coupled to the output voltage and the plurality of sequential delay signals for generating the feedback voltage.

2. The voltage regulator of claim 1 wherein the voltage-generating circuit comprises:
a first node for receiving the output voltage;
a second node for outputting the feedback voltage;
a first resistor circuit coupled between the first node and the second node of the voltage-generating circuit; and
a second resistor circuit coupled between the second node of the voltage-generating circuit and a bias voltage for adjusting an equivalent resistance of the voltage-generating circuit according to the plurality of sequential delay signals.

3. The voltage regulator of claim 2 wherein the second resistor circuit comprises:
a first resistor having a first end coupled to the second node of the voltage-generating circuit;
a plurality of second resistors each having a first end coupled to the second end of the first resistor and a second end coupled to the bias voltage; and
a plurality of delay switches respectively coupled to corresponding second ends of the plurality of second resistors for controlling signal transmission paths between the corresponding second resistors and the bias voltage according to corresponding delay signals.

4. The voltage regulator of claim 1 wherein the voltage-generating circuit comprises:
a first node for outputting the output voltage;
a second node for receiving the feedback voltage;
a first resistor circuit coupled between the first node and the second node of the voltage-generating circuit for adjusting an equivalent resistance of the voltage-generating circuit according to the plurality of sequential delay signals; and
a second resistor circuit coupled between the second node of the voltage-generating circuit and a bias voltage.

5. The voltage regulator of claim 4 wherein the first resistor circuit comprises:
a first resistor having a first end coupled to the first node of the voltage-generating circuit;
a plurality of second resistors each having a first end coupled to the second end of the first resistor; and
a plurality of delay switches respectively coupled to corresponding second ends of the plurality of second resistors for controlling signal transmission paths between the corresponding second resistors and the voltage-generating circuit according to corresponding delay signals.

6. The voltage regulator of claim 1 wherein the voltage-generating circuit comprises:
a first node for receiving the output voltage;
a second node for outputting the feedback voltage;
a first resistor circuit coupled between the first node and the second node of the voltage-generating circuit for adjusting an equivalent resistance of the voltage-generating circuit according to the plurality of sequential delay signals; and
a second resistor circuit coupled between the second node of the voltage-generating circuit and a bias voltage for adjusting the equivalent resistance of the voltage-generating circuit according to the plurality of sequential delay signals.

7. The voltage regulator of claim 6 wherein:
the first resistor circuit comprises:
a first resistor having a first end coupled to the first node of the voltage-generating circuit;
a plurality of second resistors each having a first end coupled to the second end of the first resistor; and
a plurality of first delay switches respectively coupled to corresponding second ends of the plurality of second resistors for controlling signal transmission paths between the corresponding second resistors and the second node of the voltage-generating circuit according to corresponding delay signals; and

the second resistor circuit comprises:
a third resistor having a first end coupled to the second node of the voltage-generating circuit;
a plurality of fourth resistors each having a first end coupled to the second end of the third resistor and a second end coupled to the bias voltage; and
a plurality of delay switches respectively coupled to corresponding second ends of the plurality of second resistors for controlling signal transmission paths between the corresponding fourth resistors and the bias voltage according to corresponding delay signals.

8. The voltage regulator of claim 1 wherein the delay signal generator comprises a plurality of inverters coupled in series.

9. The voltage regulator of claim 1 wherein the power device is a P-channel metal oxide semiconductor (PMOS) switch.

10. A method for sequentially and arbitrarily regulating an output voltage comprising:
generating a plurality of sequential delay signals according to an externally applied power-on burst signal, wherein each sequential delay signal has a distinct delay time with respect to the power-on burst signal;
adjusting an equivalent resistance according to the plurality of sequential delay signals;
generating a feedback voltage by voltage-dividing the output voltage according to the equivalent resistance; and
regulating the output voltage according to the feedback voltage.

11. The method of claim 10 further comprising:
comparing a difference between the feedback voltage and a reference voltage.

12. The method of claim 11 further comprising:
regulating the output voltage according to the difference between the feedback voltage and the reference voltage.

13. The method of claim 10 wherein a constant delay time exists between two consecutive sequential delay signals among the plurality of sequential delay signals.

14. A voltage regulator which sequentially and arbitrarily regulates an output voltage, wherein the voltage regulator generates a plurality of sequential delay signals according to an externally applied power-on burst signal, each sequential delay signal having a distinct delay time with respect to the power-on burst signal, and the voltage regulator regulates the output voltage according to the plurality of sequential delay signals so as to maintain the output voltage at a predetermined level at a specific time.