# Patent

## Title
Adjusting a current threshold of a power supply in response to a portion of a current-pulse period

## Abstract

An embodiment of a power-supply controller includes switching circuitry and an adjuster circuit. The switching circuitry is configured to cause a charging current to flow until the charging current has a predetermined relationship to a threshold, and to cause a discharging current to flow after the charging current. The adjuster circuit is configured to adjust the threshold in response to at least one of a charging period during which the charging current flows and a discharging period during which the discharging current flows. For example, a power supply may include such a power-supply controller to maintain a length of a current pulse, or of a portion thereof, within a particular range, such as approximately at a particular value, during a pulse-frequency-modulation (PFM) mode despite variations in one or more parameters such as input voltage, output voltage, filter capacitance, phase inductance, charging-current-sense impedance, and load, from their respective nominal values.

## Background
PRIORITY CLAIM
The present application is a Continuation of copending U.S. patent application Ser. No. 14/231,691, filed 31 Mar. 2014; which application claims priority to U.S. Provisional Patent Application Nos. 61/922,259, filed 31 Dec. 2013, and 61/874,351 filed 5 Sep. 2013; all of the foregoing applications are incorporated herein by reference in their entireties.
RELATED APPLICATION DATA
This application is related to U.S. patent application Ser. No. 14/479,076, entitled “ADJUSTING A CURRENT THRESHOLD OF A POWER SUPPLY SUCH THAT AN OUTPUT RIPPLE VOLTAGE IS WITHIN A SET RANGE”, filed 5 Sep. 2014; and Ser. No. 14/479,112, entitled “TRANSITIONING A POWER SUPPLY FROM A MODE TO ANOTHER MODE IN RESPONSE TO A LENGTH OF A PORTION OF A CURRENT PULSE”, all of the foregoing applications are incorporated herein by reference in their entireties.


TECHNICAL FIELD
The patent application relates generally to electronic circuits, and an embodiment disclosed in the patent application more particularly relates to a power-supply controller that is configured to maintain a length of a current pulse, or of a portion thereof, within a particular range during a pulse-frequency-modulation (PFM) mode of operation.
SUMMARY
An embodiment of a power-supply controller includes switching circuitry and an adjuster circuit. The switching circuitry is configured to cause a charging current to flow until the charging current has a predetermined relationship to a threshold, and to cause a discharging current to flow after the charging current. The adjuster circuit is configured to adjust the threshold in response to at least one of a charging period during which the charging current flows and a discharging period during which the discharging current flows.
For example, a power supply may include such a power-supply controller to maintain a length of a current pulse, or of a portion thereof, within a particular range, such as approximately at a particular value, during a pulse-frequency-modulation (PFM) mode despite variations in one or more parameters such as input voltage, output voltage, filter capacitance, phase inductance, charging-current-sense impedance, and load, from their respective nominal values; so maintaining the length of the current pulse, or a portion thereof, within a particular range may maintain the charge delivered to the load per pulse within a particular range, and, therefore, may maintain the output ripple voltage within a particular range. These variations may be dynamic variations that occur during the operation of a respective power supply (e.g., caused by changes in temperature, input voltage, and load). Or, these variations may be comparative variations from power supply to power supply (e.g., process variations, and different design parameters such as different output voltages, input voltages, and frequency responses).



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a power supply, and of a load that receives power from the power supply.
FIG. 2 is a plot of the inductor current of the power supply of FIG. 1 versus time during a continuous pulse-width-modulation (PWM) mode of operation.
FIG. 3 is a plot of the inductor current of the power supply of FIG. 1 versus time during a discontinuous PWM mode of operation.
FIG. 4 is a plot of the inductor current of the power supply of FIG. 1 versus time during a pulse-frequency-modulation (PFM) mode of operation.
FIG. 5 diagram of a power supply that can transition more smoothly from the PFM mode to a PWM mode than the power supply of FIG. 1 can, and of a load that receives power from the power supply, according to an embodiment.
FIG. 6 is a plot of the inductor current of the power supply of FIG. 5 versus time just before and just after a transition from PFM mode to a discontinuous PWM mode, according to an embodiment.
FIG. 7 is a plot of the inductor current of the power supply of FIG. 5 versus time just before and just after a transition from a PFM mode to a discontinuous PWM mode, and of a virtual inductor current that the power supply of FIG. 5 uses to poise a portion of the power supply for the transition, according to an embodiment.
FIG. 8 is a number of plots of the inductor current of the power supply of FIG. 1 versus time during a PFM mode for a number of input-signal levels, according to an embodiment.
FIG. 9 is a plot of the normalized amount of charge that the power supply of FIG. 1 delivers to the load per cycle in a PFM mode versus the input-signal level, according to an embodiment.
FIG. 10 is diagram of a power supply that can transition from the PWM mode to the PFM mode more accurately than the power supplies of FIGS. 1 and 5 can, and of a load that receives power from the power supply, according to an embodiment.
FIG. 11 is a number of plots of the inductor current of the power supply of FIG. 10 versus time during a PFM mode for a number of input-signal levels, according to an embodiment.
FIG. 12 is a plot of the normalized amount of charge that the power supply of FIG. 10 delivers to the load per cycle in a PFM mode versus the input-signal level, according to an embodiment.
FIG. 13 is a plot of the normalized amount of charge that the power supply of FIG. 10 delivers to the load per cycle in a PFM mode versus the input-signal level, according to another embodiment.
FIG. 14 is a diagram of a ripple control circuit that the power supplies of FIGS. 5 and 10 can include to set the magnitude of the ripple on the regulated output signal, according to an embodiment.
FIG. 15 is a diagram of ripple control circuit that the power supplies of FIGS. 5 and 10 can include to set the magnitude of the ripple on the regulated output signal, according to another embodiment.
FIG. 16 is a plot of the inductor current of the power supply of FIG. 10 versus time just before and just after a transition from a discontinuous PWM mode to a PFM mode, according to an embodiment.
FIG. 17 is a diagram of a system that can include one or more of the power supplies of FIGS. 5 and 10, according to an embodiment.



DETAILED DESCRIPTION
FIG. 1 is a schematic diagram of a power supply, here a boost converter (sometimes called a boost regulator) 10, and a load 12, which receives power from the boost converter, according to an embodiment. The boost converter 10 converts an input signal, here an input voltage Vin, into a regulated output signal, here a regulated output voltage Vout, where Vout>Vin; for example, Vin=3.3 Volts (V) and Vout=5.0 V. And the load 12 may include any type of load, for example, an integrated computing circuit such as a microprocessor or microcontroller. One may model the load 12 as a purely resistive impedance, although it is contemplated that the load can include capacitive and inductive impedance components (i.e., can be modeled as a complex impedance), can change its state (e.g., transition from an “awake” state to a “sleep” state and vice-versa), and thus can change its impedance and current consumption. Consequently, the boost converter 10 is configured to regulate Vout to a set voltage level over a range of load impedances and load current consumptions.
The boost converter 10 is configured to operate in at least the following three modes: a continuous pulse-width-modulation (PWM) mode, a discontinuous PWM mode, and a pulse-frequency-modulation (PFM) mode. During a continuous PWM mode, the load 12 draws a relatively high current (e.g., the load is “awake”), and the boost converter 10 switches at a constant switching frequency fs_PWM having a duty cycle DPWM, which the boost converter adjusts to regulate Vout to a set voltage level. During a discontinuous PWM mode, the load 12 draws a lower current (e.g., the load is in an intermediate state such as “idle”), and the boost converter 10 continues to switch at a constant switching frequency fs_PWM having a duty cycle DPWM, which the boost converter adjusts to regulate Vout to a set voltage level. Sometimes the continuous and discontinuous PWM modes are collectively referred to as a “PWM mode”. And during a PFM mode, the load 12 draws a lower current than it does in the continuous PWM mode, and may draw an even lower current than it does in discontinuous PWM mode (e.g., the load is light or “asleep”), and the boost converter 10 switches at a variable frequency fs_PFM, which depends on the level of the load current ILoad that the load draws. The continuous and discontinuous PWM modes, and the PFM mode, are described further below.
The boost converter 10 includes power-supply control circuitry 14, a filter inductor 16, a switching stage 18, and an output filter capacitor 20. The boost converter 10 can also include other components and circuitry that are omitted for brevity. In an embodiment, some of these components, or portions thereof, may be disposed on an integrated power-supply controller; for example, some or all of the components of the power-supply control circuitry 14 and the switching stage 18 may be disposed on such an integrated power-supply controller. Furthermore, the power-supply controller, and some or all of any other components that are not disposed on the power-supply controller, may be disposed within a packaged power-supply module.
The power-supply control circuitry 14 is configured to control the operation of the boost converter 10, to receive as feedback signals the output voltage Vout and the current IInductor through the filter inductor 16, and to generate one or more switching signals, here switching voltage signals SWITCH_CHARGE and SWITCH_DISCHARGE, which control the switching stage 18.
The power-supply control circuitry 14 includes an oscillator 21, a ramp generator 22, a summing comparator 24, a switching controller 26, first, second, third, and fourth control loops 28, 30, 32, and 33, and a comparator 35.
The oscillator 21 is configured to generate an oscillator signal, here a voltage OSC, having a frequency fosc, and to provide OSC to the ramp generator 22 and the switching controller 26 during continuous and discontinuous PWM modes of operation. In contrast, during a PFM mode, the oscillator 21 may not be used, and, therefore, the control circuit 14 may be configured to deactivate the oscillator 21 to save power.
The ramp generator 22 is configured to generate a saw-tooth signal, here a voltage SAWTOOTH, having a frequency fsawtooth, which equals the oscillator frequency fosc, and which also equals the frequency fs_PWM of the switching signals, here voltages, SWITCH_CHARGE and SWITCH_DISCHARGE, during continuous and discontinuous PWM modes of operation such that:

fsawtooth=fs_PWM=fosc  (1)

In contrast, during a PFM mode the ramp generator 22 is not used, and the control circuit 14 may be configured to deactivate the ramp generator to save power.
The summing comparator 24 includes a summer 34 and a comparator 36, which, during continuous and discontinuous PWM modes, are configured to cooperate to generate a switching control signal, here a switching control voltage SWITCHING_CONTROL, in response to the voltage SAWTOOTH, from the ramp generator 22, and the signals, here voltages, LOOP_CONTROL_1 and LOOP_CONTROL_2, from the first and second control loops 28 and 30, respectively.
The switching controller 26 includes circuitry that is configured to generate the charge and discharge switching voltages SWITCH_CHARGE and SWITCH_DISCHARGE in response to the oscillator signal OSC and the voltage SWITCHING_CONTROL during a continuous PWM mode, in response to OSC, SWITCHING_CONTROL, and a signal, here a voltage, ZERO_CURRENT from the comparator 35 during a discontinuous PWM mode, and in response to ZERO_CURRENT and signals, here voltages, LOOP_CONTROL_3 from the control loop 32 and LOOP_CONTROL_4 from the control loop 33 during a PFM mode.
The first control loop 28 is configured to be active during continuous and discontinuous PWM modes and inactive during a PFM mode, and includes, in addition to the summing comparator 24, a low-gain transconductance (gm) amplifier 38, a feedback network 40, and a low-pass-filter network 42. The amplifier 38 has a noninverting input node coupled to receive a stable reference signal, here a band-gap-derived reference voltage Vref (although not shown, the boost converter 10 may include a generator, such as a band-gap generator, configured to generate Vref), and includes an inverting input node coupled to receive a divided-down, e.g., scaled, version of Vout through the feedback network 40, which here is a voltage divider that includes resistors 44 and 46. And the low-pass-filter network 42 includes capacitors 48 and 50 and a resistor 52, which provide second-order compensation to the first control loop 28. During continuous and discontinuous PWM modes, the amplifier 38 and networks 40 and 42 of the first control loop 28 are configured to cooperate to generate the signal, here a voltage, LOOP_CONTROL_1 in response to Vout; conversely, during a PFM mode, the first control loop is disabled (e.g., by the control circuit 14 effectively causing the switching controller 26 to “ignore” LOOP_CONTROL_1) and the control circuit may be configured to disable the amplifier 38, the summing comparator 24, the ramp generator 22, and possibly the oscillator 21, to save power.
The second control loop 30 is configured to be active during continuous and discontinuous PWM modes and inactive during a PFM mode, and includes, in addition to the summing comparator 24, a sense component, here a sense resistor 54, which provides feedback of the inductor-current information to the second control loop during the charging phase of the filter inductor 16. During continuous and discontinuous PWM modes, the sense resistor 54 is configured to convert the current Iinductor through the inductor 16 into the signal, here a voltage, LOOP_CONTROL_2. Conversely, during a PFM mode, the control loop 30 is disabled (e.g., by the control circuit 14 effectively causing the switching controller 26 to “ignore” LOOP_CONTROL_2).
The third control loop 32 is configured to be active during continuous and discontinuous PWM modes and active during a PFM mode, and includes, in addition to the sense resistor 54, a comparator 56, which has a noninverting input node coupled to receive the voltage LOOP_CONTROL_2 and has an inverting node coupled to receive a stable reference signal, such as a band-gap-derived reference voltage, IPEAK_REF. During continuous and discontinuous PWM modes, the comparator 56 is configured to generate LOOP_CONTROL_3 in response to LOOP_CONTROL_2 and IPEAK_REF so as to allow the switching controller 26 to provide fault protection by limiting the peak of the inductor current IInductor to a configurable level set by IPEAK_REF Similarly, during a PFM mode, the comparator 56 is configured to generate LOOP_CONTROL_3 in response to LOOP_CONTROL_2 and IPEAK_REF to set the peak of the PFM inductor current IInductor to a configurable level set by IPEAK_REF. Therefore, IPEAK_REF may have different values in PWM and PFM modes; for example, IPEAK_REF is almost always lower in PFM mode than it is in continuous or discontinuous PWM mode. Although not shown in FIG. 1, the power-supply control circuitry 14 may include a multiplexer having an output node that provides IPEAK_REF to the inverting input node of the amplifier 56, having multiple input nodes each coupled to a respective voltage levels IPEAK_REF_PWM_CONTINUOUS, IPEAK_REF_PWM_DISCONTINUOUS, and IPEAK_REF_PFM, and having a control node coupled to the switching controller 26. While the boost converter 10 is operating in a continuous PWM mode, the switching controller 26 controls the multiplexer to couple IPEAK_REF_PWM_CONTINOUS to the multiplexer output node such that IPEAK_REF=IPEAK_REF_PWM_CONTINOUS Similarly, while the boost converter 10 is operating in a discontinuous PWM mode, the switching controller 26 controls the multiplexer to couple IPEAK_REF_PWM_DISCONTINOUS to the multiplexer output node such that IPEAK_REF=IPEAK_REF_PWM_DISCONTINOUS, and while the boost converter 10 is operating in a PFM mode, the switching controller 26 controls the multiplexer to couple IPEAK_REF_PFM to the multiplexer output node such that IPEAK_REF=IPEAK_REF_PFM. Alternatively, IPEAK_REF_PWM_DISCONTINOUS=IPEAK_REF_PWM_CONTINOUS=IPEAK_REF_PWM such that the multiplexer has two input nodes each coupled to a respective voltage levels IPEAK_REF_PWM and IPEAK_REF_PFM While the boost converter 10 is operating in a continuous or discontinuous PWM mode, the switching controller 26 controls the multiplexer to couple IPEAK_REF_PWM to the multiplexer output node such that IPEAK_REF=IPEAK_REF_PWM, similarly, while the boost converter 10 is operating in a PFM mode, the switching controller 26 controls the multiplexer to couple IPEAK_REF_PFM to the multiplexer output node such that IPEAK_REF=IPEAK_REF_PFM.
Still referring to FIG. 1, the fourth control loop 33 is configured to be inactive during continuous and discontinuous PWM modes and active during a PFM mode, and includes a comparator 57, which has a noninverting input node coupled to receive the reference voltage Vref and has an inverting node coupled to receive the divided-down version of Vout from the feedback network 40. During continuous and discontinuous PWM modes, the control loop 33 is disabled (e.g., by the control circuit 14 effectively causing the switching controller 26 to “ignore” LOOP_CONTROL_4), and the control circuit may disable the comparator 57 to save power; conversely, during a PFM mode, the comparator 57 is configured to generate the signal, here a voltage, LOOP_CONTROL_4 in response to the voltages Vref and




  
    
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The comparator 35 includes an inverting input node coupled to receive Vout and a non-inverting input node coupled to the junction between the inductor 16 and the switching stage 18, and is configured to generate the signal, here a voltage, ZERO_CURRENT on an output node that is coupled to the switching controller 26; ZERO_CURRENT is valid (i.e., is “recognized” by the switching controller) only when a transistor 60 (described further below) is “on” (i.e., when SWITCH_DISCHARGE has a logic-low level in the case where MOSFET 60 is a PFET as shown in FIG. 1), and provides information to the switching controller regarding the direction of Iout. As described below, during a discontinuous PWM mode and a PFM mode, the comparator 35 is configured to generate ZERO_CURRENT having a logic-low level to indicate that the current Iout is zero or less than zero; and in response to ZERO_CURRENT having a logic-low level, the switching controller 26 configures the switching stage 18 so that Iout does not flow in a reverse direction from the capacitor 20 back through the switching stage.
Still referring to FIG. 1, the switching stage 18 includes an inductor-charging switch, here an NMOS transistor 58, which includes a control node that is coupled to receive the signal SWITCH_CHARGE from the switching controller 26, and includes an inductor-discharging switch, here the PMOS transistor 60, which includes a control node that is coupled to receive the signal SWITCH_DISCHARGE from the switching controller. Although not shown in FIG. 1, there may be respective buffers disposed between logic circuitry within the switching controller 26 and the transistors 58 and 60; these buffers may be located within, or outside of, the switching controller.
FIG. 2 is a plot of the inductor current Iinductor through the inductor 16 of the boost converter 10 of FIG. 1 versus time during a continuous PWM mode of operation, according to an embodiment.
FIG. 3 is a plot of the inductor current Iinductor through the inductor 16 of the boost converter 10 of FIG. 1 versus time during a discontinuous PWM mode of operation, according to an embodiment.
FIG. 4 is a plot of the inductor current IInductor through the inductor 16 of the boost converter 10 of FIG. 1 versus time during a PFM mode of operation, according to an embodiment.
Referring to FIGS. 1 and 2, operation of the boost converter 10 is described during a continuous PWM mode of operation, according to an embodiment.
During a continuous PWM mode, the inductor current IInductor(t)>0 during the entire switching period TPWM_continuous.
In response to an active edge of the oscillator signal OSC from the oscillator 21, the ramp generator 22 transitions the signal SAWTOOTH to its lowest voltage level, and the switching controller 26 generates a logic-high level for the voltage signal SWITCH_CHARGE, and generates a logic-high level typically equal to, but possibly greater than, Vout for the voltage signal SWITCH_DISCHARGE such that the transistor 58 is conducting (i.e., “on”) and the transistor 60 is nonconducting (i.e., “off”). Therefore, in response to the active edge of OSC, both SAWTOOTH and Iinductor(t) begin to ramp upward from their respective lowest levels.
While the sum of the voltage signals SAWTOOTH and LOOP_CONTROL 2 output from the summer 34 is less than the voltage signal LOOP_CONTROL_1, the comparator 36 generates a logic-low level for the voltage signal SWITCHING_CONTROL.
In response to the logic-low level for SWITCHING_CONTROL, the switching controller 26 maintains a logic-high level for the voltage signal SWITCH_CHARGE, and maintains a logic-high level equal to, or greater than, Vout for the voltage signal SWITCH_DISCHARGE such that the transistor 58 remains conducting (i.e., “on”) and the transistor 60 remains nonconducting (i.e., “off”).
The respective “on” and “off” states of the transistors 58 and 60 cause the inductor current IInductor to flow from Vin and through the inductor 16, transistor 58, and sense resistor 54. The rate of change, dlInductor/dt, of the current IInductor through the inductor 16 is related to the inductance L of the inductor and to the voltage VInductor across the inductor according to the following equation:

dlInductor/dt=VInductor/L  (2)

Therefore, while the transistor 58 is “on” and the transistor 60 is “off”, the current IInductor(t) (the variable “t” indicates that the inductor current is a function of time) is given by the following equation, for which it is assumed that the “on” voltage of the transistor 58, the voltage across the sense resistor 54, and the equivalent series resistance (ESR) of the inductor 16 are negligible:

IInductor(t)=Io+(Vin/L)·t  (3)

where Io is the initial value of the inductor current IInductor(t) when the transistor 58 turns on, L is the inductance of the inductor 16, and t is time in seconds. Therefore, while the transistor 58 is “on”, IIinductor(t) linearly ramps upward from Io at a constant rate of Vin/L.

In response to the linear ramping current IInductor(t), the sense resistor 54 effectively converts this ramping inductor current to a ramping voltage LOOP_CONTROL_2 according to the following equation:

LOOP_CONTROL_2(t)=IInductor(t)·Rsense=(Io+Vin/L·t)·Rsense  (4)

where Rsense is the resistance of the sense resistor 54.

In response to the sum of the ramping voltage signals SAWTOOTH and LOOP_CONTROL_2 from the summer 34 being greater than the voltage signal LOOP_CONTROL_1, the comparator 36 transitions the voltage signal SWITCHING_CONTROL to a logic-high level.
In response to the logic-high level for SWITCHING_CONTROL, the switching controller 26 generates a logic-low level (e.g., zero voltage or the ground voltage level) for the voltage signal SWITCH_CHARGE, and generates a logic-low level on SWITCH_DISCHARGE, such that the transistor 58 is nonconducting (i.e., “off”) and the transistor 60 is conducting (i.e., “on”).
The respective “off” and “on” states of the transistors 58 and 60 cause the inductor current IInductor(t)=Iout(t) to flow from Vin, through the inductor 16 and the transistor 60, and into the output capacitor 20 and the load 12.
Therefore, while the transistor 58 is “off” and the transistor 60 is “on”, the current IInductor(t)=Iout(t) is given by the following equation, for which it is assumed that the “on” voltage of the transistor 60 and the ESR of the inductor 16 are negligible:

IInductor(t)=Iout(t)=Ipeak_PWM_continuous−((Vout−Vin)/L)·t  (5)

where Ipeak_PWM_continuous is the initial (peak) value of the current IInductor(t)=Iout(t) when the transistor 58 turns off. Therefore, while the transistor 58 is “off” and the transistor 60 is “on,” IInductor(t)=Iout(t) linearly ramps downward at a rate of (Vout−Vin)/L. Furthermore, while the transistor 58 is “off”, LOOP_CONTROL_2=0 because there is no current flowing through the sense resistor 54.

Next, in response to the next active edge of the oscillator signal OSC from the oscillator 21, the switching controller 26 generates a logic-low level for SWITCH_DISCHARGE and a logic-high level for SWITCH_CHARGE, and the ramp generator 22 restarts the sawtooth wave SAWTOOTH (these actions cause SWITCHING_CONTROL to transition to a logic-low level) such that the above-described cycle repeats.
In summary, during a continuous PWM mode, in a steady state, the ramp generator 22 and the second control loop 30 cause the inductor current IInductor(t) to rise from an initial value Io to a peak value Ipeak_PWM_continuous during a portion Ton_PWM_continuous of the continuous PWM switching period TPWM_continuous, and cause the current IInductor(t) to fall from Ipeak_PWM_continuous to Io during a portion Toff_PWM_continuous=TPWM_continuous−Ton_PWM_continuous of the switching period TPWM_continuous. And, because during Ton_PWM_continuous IInductor(t) is increasing, it is sometimes said that this is charging the magnetic field generated in the core of the inductor 16; therefore, during Ton_PWM_continuous, one may refer to the current IInductor(t) as a “charge” or “charging” current. Likewise, because during Toff_PWM_continuous IInductor(t) is decreasing, it is sometimes said that this is discharging the magnetic field generated in the core of the inductor 16; therefore, during Toff_PWM_continuous, one may refer to the current IInductor(t) as a “discharge” or “discharging” current.
Furthermore, during a continuous PWM mode, the boost converter 10 switches with a duty cycle DPWM_continuous given by the following equation:

DPWM_continuous=Ton_PWM_continuous/(Ton_PWM_continuous+Toff_PWM_continuous)=(Vout−Vin)/Vout  (6)

Moreover, during a continuous PWM mode, the boost gain Vout/Vin of the boost converter 10 is given by the following equation:

Vout/Vin=1/(1−DPWM_continuous)  (7)

Still referring to FIGS. 1 and 2, during the above-described continuous-PWM-mode switching cycle, the first control loop 28 of the boost converter 10 acts to drive Vout toward




  
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during load transients, and to maintain the average value of Vout during each cycle to be equal to





  
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during a steady-state condition of the load 12.

For example, suppose that during a continuous PWM mode, the load 12 significantly reduces the current ILoad(t) that it draws over a relatively short period of time; this is sometimes called a load-release transient. Because the control loop 28 has a finite bandwidth and the inductor current takes time to slew to a new level, the control circuitry 14 cannot generate Iout(t) so that it instantaneously tracks this reduction in ILoad(t); therefore, the excess amount of Iout(t) flows into and charges the filter capacitor 20, and thus causes Vout to rise above




  
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This increase in Vout causes the voltage at the inverting node of the amplifier 38 to increase above Vref, and, therefore, causes the amplifier to sink a current into its output node, thus discharging the capacitors 48 and 50 of the network 42, generating a negative voltage across resistor 52, and causing the level of the voltage LOOP_CONTROL_1 to fall. This decrease in LOOP_CONTROL_1 allows the sum of the voltage signals SAWTOOTH and LOOP_CONTROL_2 to exceed LOOP_CONTROL_1 in a shorter time during the continuous-PWM-mode switching period TPWM_continuous, and, therefore, causes a reduction in the duty cycle DPWM_continuous; and because TPWM_continuous is fixed, a reduction in DPWM_continuous causes a reduction in the on time Ton_PWM_continuous of the transistor 58. And this reduction in the duty cycle DPWM_continuous also reduces the peak of the inductor current IInductor(t)=Iout(t), and increases the amount of time during which the inductor current can discharge before the end of the cycle. Together with the load, which will act to pull Vout down, this allows Vout to decrease toward





  
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When Vout approximately equals





  
    
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the first control loop 28 will recover, with the amplifier 38 ultimately holding the level of the voltage LOOP_CONTROL_1 steady at a new value, to maintain Vout approximately equal to





  
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Conversely, suppose that the load 12 significantly increases the current ILoad(t) that it draws over a relatively short period of time; this is sometimes called a load-insertion transient. Because the control loop 28 has a finite bandwidth, and because the inductor current takes time to ramp to the new level, the control circuitry 14 cannot generate Iout(t) so that it instantaneously tracks this increase in ILoad(t); therefore, the filter capacitor 20 sources the excess amount of ILoad(t), and, therefore, discharges, thus causing Vout to fall below




  
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This decrease in Vout causes the voltage at the inverting node of the amplifier 38 to fall below Vref, and, therefore, causes the amplifier to source a current from its output node, thus charging the capacitors 48 and 50 of the network 42 and forming a positive voltage across resistor 52, which causes the level of the voltage LOOP_CONTROL_1 to rise. This increase in LOOP_CONTROL_1 increases the portion of the switching period TPWM_continuous required for the sum of the voltage signals SAWTOOTH and LOOP_CONTROL_2 to exceed the voltage signal LOOP_CONTROL_1, and, therefore, increases the duty cycle DPWM_continuous, i.e., the on time Ton_PWM_continuous of the transistor 58. And this increase in the duty cycle DPWM_continuous increases the peak inductor current Ipeak_PWM_continuous and, therefore, increases the peak of the inductor current IInductor(t)=Iout(t). Once the increase is sufficient, this causes Vout to increase toward





  
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When Vout approximately equals





  
    
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the first control loop 28 will recover, the amplifier 38 will stop sourcing an output current, and the control voltage LOOP_CONTROL_1 will ultimately stabilize and maintain Vout approximately equal to





  
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          R
          44
        
        +
        
          R
          46
        
      
      
        R
        46
      
    
    .
  




In summary, during a continuous PWM mode, in response to a transient in the load current ILoad(t), the first control loop 28 drives Vout toward




  
    
      V
      ref
    
    ·
    
      
        
          R
          44
        
        +
        
          R
          46
        
      
      
        R
        46
      
    
  
  ,




and in response to a steady-state load current ILoad(t), the first control loop maintains Vout approximately equal to





  
    V
    ref
  
  ·
  
    
      
        
          R
          44
        
        +
        
          R
          46
        
      
      
        R
        46
      
    
    .
  




Referring to FIGS. 1 and 3, operation of the boost converter 10 is described during a discontinuous PWM mode of operation, according to an embodiment.
During a discontinuous PWM mode, the inductor current Iinductor(t)=0 for at least a portion Tzero_inductor_current of the switching period TPWM_discontinuous=TPWM_continuous.
The operation of the boost converter 10 during a discontinuous PWM mode is similar to the operation of the boost converter during a continuous PWM mode as described above, with at least the following four differences.
First, the inductor current IInductor(t) equals zero for the time Tzero-inductor_current before the switching controller 26, in response to the oscillator signal OSC, turns the transistor 58 on again; the current IInductor(t) equaling zero typically indicates that ILoad(t) is less than it is during a continuous PWM mode.
Second, in response to IInductor(t) falling to zero (or even slightly below zero for a relatively short period of time), the output of the comparator 35 transitions from a logic-high level to a logic-low level.
Third, to prevent a reverse current from flowing from the filter capacitor 20 back through the transistor 60, the switching controller 26 turns off the transistor 60 in response to the logic-high-to-logic-low transition of the output of the comparator 35, which, per above, indicates that Iout(t)=0 such that both of the transistors 58 and 60 are off during the time Tzero_inductor_current.
And fourth, despite the zero-inductor-current time Tzero_inductor_current, the following equations, which are the counterparts to equations (6) and (7) above, hold true:

DPWM_discontinuous=Ton_PWM_discontinuous/(Ton_PWM_discontinuous+Toff_PWM_discontinous)=(Vout−Vin)/Vout  (8)

Moreover, during a discontinuous PWM mode, the boost gain Vout/Vin of the boost converter 10 is given by the following equation:

Vout/Vin=1/(1−DPWM_discontinuous)  (9)

The boost converter 10 may remain in a discontinuous PWM mode during steady-state operation while the load 12 is too light for a continuous PWM mode but too heavy for a PFM mode. If the boost converter 10 is in a discontinuous PWM mode when the load 12 becomes light enough for a PFM mode, then the boost converter may transition from the discontinuous PWM mode to the PFM mode. And if the boost converter 10 is in a continuous PWM mode when the load 12 becomes light enough for a PFM mode, then the boost converter may transition from the continuous PWM mode, through a discontinuous PWM mode, and to the PFM mode. Similarly, if the boost converter 10 is in a PFM mode and the load 12 becomes heavy enough for the boost converter to operate in a discontinuous PWM mode, then the boost converter may transition from the PFM mode to the PWM mode. And if the boost converter 10 is in a PFM mode and the load 12 becomes heavy enough for the boost converter to operate in a continuous PWM mode, then the boost converter may transition from the PFM mode, through a discontinuous PWM mode, and to the continuous PWM mode.
Referring to FIGS. 1 and 4, operation of the boost converter 10 is described during a PFM mode of operation, according to an embodiment.
During a PFM mode, the switching frequency fs_PFM and, therefore, the switching period TPFM=1/fs_PFM, depend on the load 12; that is, as the load current ILoad(t) increases, the switching frequency fs_PFM increases and the switching period TPFM decreases, and as ILoad(t) decreases, fs_PFM decreases and TPFM increases.
As described above, the boost converter 10 is configured to enter the PFM mode during light-load conditions to increase conversion efficiency. Furthermore, the first and second control loops 28 and 30, and the oscillator 21, ramp generator 22, and summing comparator 24 may be disabled, e.g., to save power.
During TPFM, while both the transistors 58 and 60 are off, the comparator 57 effectively monitors Vout.
Next, in response to Vout falling below




  
    
      V
      ref
    
    ·
    
      
        
          R
          44
        
        +
        
          R
          46
        
      
      
        R
        46
      
    
  
  ,




the comparator 57 transitions its output from a logic-low level to a logic-high level.

Then, in response to the logic-low-level-to-logic-high-level transition of the output of the comparator 57, the switching controller 26 turns on the transistor 58 and maintains the transistor 60 off such that a charging current IInductor(t) flows through the inductor 16, the on transistor 58, and the sense resistor 54; the charging inductor current IInductor(t) ramps upward per equation (3) with Io=0.
While the voltage signal LOOP_CONTROL_2=R54·IInductor<Ipeak_ref, the comparator 56 generates a logic-low level for LOOP_CONTROL_3, in response to which the switching controller 26 maintains the transistor 58 on and maintains the transistor 60 off.
Next, in response to LOOP_CONTROL_2≧Ipeak_ref, which will occur when IInductor exceeds Ipeak_PFM=Ipeak_ref/R54, the comparator 56 generates a logic-high level for LOOP_CONTROL_3, in response to which the switching controller 26 turns off the transistor 58 and turns on the transistor 60 for a time Toff_PFM such that the inductor current IInductor(t)=Iout(t) ramps downward according to the following equation:

IInductor(t)=Ipeak_PFM−((Vout−Vin)/L)·t  (10)

Then, in response to IInductor(t)≦0, the comparator 35 transitions its output from a logic-high level to a logic-low level, and in response to this logic-high-level-to-logic-low-level transition, the switching controller 26 turns off the transistor 60 to prevent a reverse discharge current −Iout(t) from flowing from the capacitor 20, and back through the transistor 60.
The switching controller 26 maintains the transistors 58 and 60 off until the comparator 57 detects that Vout has fallen below




  
    
      V
      ref
    
    ·
    
      
        
          R
          44
        
        +
        
          R
          46
        
      
      
        R
        46
      
    
  
  ,




at which point the boost converter 10 repeats the above-described PFM cycle.

Consequently, because in a PFM mode the inductor current Iinductor maintains a fixed waveform, the switching frequency fs_PFM at which the switching controller 26 switches the transistors 58 and 60 is proportional to the load current ILoad(t) such that fs_PFM reduces with ILoad(t), and, therefore, the boost converter 10 is more efficient because it delivers more energy per switching event than it would do in a discontinuous PWM mode at the same load level. The reduction in switching cycles results in less switching losses while taking advantage of the fact that at low inductor currents, conduction losses are small, which allows the boost converter 10 to operate with a higher conversion efficiency.
Referring to FIGS. 1-4, operation of the boost converter 10 is described during a transition from a continuous or discontinuous PWM mode to a PFM mode, and from a PFM mode to a continuous or discontinuous PWM mode, according to an embodiment. In the described embodiment, it is assumed that to transition from a continuous PWM mode to a PFM mode, the boost converter 10 first transitions to a discontinuous PWM mode and then transitions to the PFM mode; therefore, only a transition from a discontinuous PWM mode to a PFM mode is described below in detail. Likewise, it is assumed that to transition from a PFM mode to a continuous PWM mode, the boost converter 10 first transitions to a discontinuous PWM mode and then transitions to the continuous PWM mode; therefore, only a transition from a PFM mode to a discontinuous PWM mode is described below in detail.
During a discontinuous PWM mode, the control circuitry 14, using conventional circuitry that is omitted from FIG. 1, monitors either the peak Ipeak_PWM_discontinuous of the inductor current IInductor or the average Iavg_PWM_discontinuous of the inductor current IInductor, and transitions the boost converter 10 to the PFM mode when the monitored current is less than or equal to a set PWM-to-PFM threshold.
And during a PFM mode, the control circuitry 14, using conventional circuitry that is omitted from FIG. 1, monitors the PFM switching frequency fs_PFM, and transitions the boost converter 10 to a discontinuous PWM mode when fs_PFM is greater than or equal to a set maximum PFM switching frequency threshold fs_PFM_max Alternatively, the control circuitry 14, using conventional circuitry that is omitted from FIG. 1, monitors Vout, and transitions the boost converter 10 to a discontinuous PWM mode when Vout is less than or equal to a set minimum threshold.
Still referring to FIGS. 1-4, alternate embodiments of the boost converter 10 are contemplated. For example, the control loops 28, 30, 32, and 33 may include components other than those shown to stabilize these loops and the overall boost converter 10. Furthermore, the control circuit 14 may include a current-sense circuit other than the sense resistor 54.
Referring again to FIGS. 1-4, there may be some problems with the boost converter 10 and the way in which it operates.
For example, a first problem may be that upon a transition from a PFM mode to a discontinuous PWM mode, Vout may experience a transient “glitch” while the first control loop 28, which the control circuitry 14 may deactivate during a PFM mode, reacquires a voltage level for LOOP_CONTROL_1 that causes Vout to approximately equal




  
    V
    ref
  
  ·
  
    
      
        
          R
          44
        
        +
        
          R
          46
        
      
      
        R
        46
      
    
    .
  




(or some other multiple of Vref).

A second problem may be that the output ripple voltage Vripple (not shown in FIGS. 1-4), which is superimposed on Vout and is caused by the inductor current Iinductor(t) ramping up and down and the effect of Iload discharging Gout during the time when Iinductor is not delivering current to Vout, may depend heavily on quantities such as Vin and Vout, and, therefore, may vary significantly with changes in Vin and Vout.
And a third problem may be that transitioning from a discontinuous PWM mode to a PFM mode in response to sensing a peak, average, or other attribute of the inductor current IInductor(t) may result in transitioning to a PFM mode at a relatively imprecise load point or a load point that varies from part to part, i.e., a load point that can be significantly different from a designed for or otherwise expected nominal transition load point, and may result in a varying hysteresis band, i.e., a band that is significantly different from a designed for or otherwise expected nominal hysteresis band. Because of this, the hysteresis band may need to be made larger than is theoretically needed. And, for a particular load, such a larger-than-needed hysteresis band may cause the boost converter 10 to sacrifice efficiency by remaining in a less-efficient mode at a load level within this larger-than-needed hysteresis band.
Referring to FIGS. 5-7, a boost converter and techniques for mitigating at least the above-described first problem are described, according to an embodiment.
FIG. 5 is a diagram of a boost converter 70, which, according to an embodiment, is configured to poise at least one of its portions (e.g., a control loop) so that after a transition from a PFM mode to a discontinuous PWM mode, Vout experiences little or no transition-induced transient amplitude change, or at least experiences a reduced transition-induced transient as compared to the boost converter 10 of FIG. 1.
FIG. 6 is a plot of an inductor current IInductor(t) 72 versus time during a PFM mode just before a transition to a discontinuous PWM mode, and of an inductor current IInductor(t) 74 versus time during a discontinuous PWM mode just after a transition from the PFM mode, according to an embodiment.
And FIG. 7 is the plot of FIG. 6 with the addition of a plot of a virtual discontinuous PWM inductor current IInductor(t) 76 versus time; the boost converter 70 effectively uses this virtual current to poise the level of at least one control signal of the boost converter at a respective value that reduces or eliminates an amplitude “glitch” or transient that Vout may otherwise experience in response to a PFM-to-discontinuous-PWM transition. The virtual discontinuous PWM inductor current IInductor(t) 76 is further described below.
Referring to FIG. 5, the boost converter 70 is similar to the boost converter 10 of FIG. 1, where like numbers refer to components common to the boost converters 10 and 70, according to an embodiment.
But in addition to the components included in the boost converter 10, the boost converter 70 includes a control-signal adjuster 80, multipliers 82 and 84, multiplexers 86 and 88, and a switch 90.
The control-signal adjuster 80 has an input node coupled to the switching controller 26 and an output node coupled to the network 42. During a PFM mode, the control-signal adjuster 80 is configured to impart to the network 42 a condition (here a voltage level) that the network would have if the boost converter 70 were operating in a discontinuous PWM mode just after a PFM-to-discontinuous-PWM transition. For example, the adjuster 80 can include a digital-to-analog converter (DAC) or a charge pump that is configured to impart to the network 42 a voltage level that the voltage signal LOOP_CONTROL_1 would approximately have if the boost converter 70 were operating in a discontinuous PWM mode at the load current ILoad(t) at which the PFM-to-discontinuous-PWM transition will occur (as will be described in more detail below). As described below, by maintaining the voltage level of LOOP_CONTROL_1 before a PFM-to-discontinuous-PWM transition approximately equal to the voltage level that LOOP_CONTROL_1 would have just after the PFM-to-discontinuous-PWM transition if the boost converter 70 were operating in a discontinuous PWM mode at the exit current, the first control loop 28 is poised to maintain Vout at its regulated level after a PFM-to-discontinuous-PWM transition with a reduction (as compared to the boost converter 10 of FIG. 1) or elimination of a transient caused by the first control loop needing to reacquire the full level of LOOP_CONTROL_1 in response to such a transition.
The multipliers 82 and 84 are respectively configured to scale the voltage signals SAWTOOTH and LOOP_CONTROL_2 by a scale factor S, and the multiplexers 86 and 88 are respectively configured to couple the unscaled versions of SAWTOOTH and LOOP_CONTROL_2 to the summing amplifier 24 during continuous and discontinuous PWM modes and to couple the scaled versions of SAWTOOTH and LOOP_CONTROL_2 to the summing amplifier during a PFM mode. The determination of a value of the scale factor S is described below in conjunction with FIG. 6, according to an embodiment.
And the switch 90 is configured to couple the amplifier 38 to the network 42 during continuous and discontinuous PWM modes, and to uncouple the network 42 from the amplifier 38 during a PFM mode. Such uncoupling allows the control-signal adjuster 80 to set the level of the voltage LOOP_CONTROL_1 during a PFM mode without interference from the amplifier 38 in continuous and discontinuous PWM modes, the control-signal adjuster is disabled, and has no impact on the level of the voltage LOOP_CONTROL_1.
According to an embodiment, the scale factor S is set to the ratio of the peak inductor current Ipeak_PWM_discontinuous to the peak inductor current Ipeak_PFM, where Ipeak_PWM_discontinuous is the peak current through the inductor 16 during a discontinuous PWM mode just after a PFM-to-discontinuous-PWM transition, and Ipeak_PFM is the peak current through the inductor during a PFM mode just before the PFM-to-discontinuous-PWM transition. That is:

S=Ipeak_PWM_discontinous/Ipeak_PFM  (11)

such that

S·LOOP_CONTROL_2@Ipeak_PFM=LOOP_CONTROL_2@Ipeak_PWM_discontinuous  (12)

By scaling both SAWTOOTH and LOOP_CONTROL_2 by S during a PFM mode, the control-signal adjuster 80, in response to the switching controller 26, can set the value of LOOP_CONTROL_1 such that LOOP_CONTROL_1 causes SWITCHING_CONTROL to transition at approximately the same time that it would have if the boost converter 70 were operating in a discontinuous PWM mode just after a PFM-to-discontinuous-PWM transition. That is, so scaling SAWTOOTH and LOOP_CONTROL_2 by S and so setting the value of LOOP_CONTROL_1 causes LOOP_CONTROL_1 to have approximately the amplitude, and SWITCHING_CONTROL to have approximately the transition timing, that these signals need to maintain Vout in regulation just after a PFM-to-discontinuous-PWM transition.
Referring to FIGS. 5-6, the determination of the value S is described, according to an embodiment.
Although throughout a PFM mode the value of the peak Ipeak_PFM of the inductor current IInductor(t) is known by inspection to be equal to Ipeak_ref/R54 [R54 is the value of resistor 54 and Ipeak_ref is a reference voltage that is input to the inverting input node of the comparator 56 during a PFM mode as described above in conjunction with FIGS. 1-4] the value of Ipeak_PWM_discontinuous depends on the load 12; therefore, because Ipeak_PWM_discontinuous may not have a known value, one typically cannot determine a value for S using equation (11) because the value of Ipeak_PWM_discontinous is not predictable while the boost converter 70 is in the PFM mode.
Consequently, to determine S, one can make the following assumptions.
First, the switching frequency fs_PWM_discontinuous of the boost converter 70 during a discontinuous PWM mode has a known fixed value; in contrast, the switching frequency fs_PFM during a PFM mode depends on the load 12 and, therefore, does not have a known fixed value.
Second, because fs_PWM is the switching frequency of the boost converter 70 during a PFM mode, just before a PFM-to-discontinuous-PWM transition fs_PWM has its highest frequency, which hereinafter is called the “maximum PFM frequency” fs_PFM_max.
Third, the load current ILoad(t) just before the PFM-to-discontinuous-PWM transition approximately equals ILoad(t) just after the PFM-to-discontinuous-PWM transition.
Fourth, because ILoad(t) is assumed to be approximately the same before and after the PFM-to-discontinuous-PWM transition, to provide a smooth transition with little or no transition-induced transient on Vout, the charge that the boost converter 70 delivers to the load 12 per PFM period TPFM at the max switching frequency fs_PFM_max immediately before the PFM-to-discontinuous-PWM transition is assumed to be approximately the same as the average charge delivered to the load per the same time TPFM immediately after the PFM-to-discontinuous-PWM transition.
Fifth, Vin, Vout, and L are assumed to have the same values just before and just after the PFM-to-discontinuous-PWM transition.
And sixth, fs_PWM_discontinuous and fs_PFM_max are related by the following equations:

fs_PWM_discontinuous=fs_PFM_max·N  (13)

fs_PWM_discontinuous/fs_PFM_max=N  (14)

where N is any real number that is greater than unity.

Based at least in part on these assumptions, one can derive a relationship between Ipeak_PFM immediately before the PFM-to-discontinuous-PWM transition and Ipeak_PWM_discontinuous immediately after the PFM-to-discontinuous-PWM transition as follows.
Due to the linear slewing of the inductor current, the charge delivered to the combination of the load 12 and the output capacitor 20 during a PFM pulse at fs_PFM_max is the average current Iavg_out that flows into the output capacitor and the load multiplied by the time toff_PFM that the output current Iout is flowing into the output capacitor and load. Therefore, this per-PFM-pulse charge QPFM_pulse is given by the following equation:

QPFM_pulse=1⁄2·Ipeak_PFM·toff_PFM  (15)

Therefore, the average charge per second, i.e., the average current, Iavg_PFM delivered to the combination of the output capacitor 20 and the load 12 during the PFM switching period TPFM is given by the following equation:

Iavg_PFM=QPFM_pulse/TPFM=1⁄2·Ipeak_PFM·toff_PFM/TPFM  (16)

Similarly, the average charge per second, i.e., the average current, Iavg_PWM_discontinuous delivered to the combination of the output capacitor 20 and the load 12 in a discontinuous PWM mode during a discontinuous-PWM switching period TPWM_discontinuous immediately after the PFM-to-discontinuous-PWM transition can be calculated using a similar approach, and is given by the following equation:




  
    
      
        
          I
          
            avg_PWM
            ⁢
            _discontinuous
          
        
        =
        
          
            
              Q
              
                PWM_pulse
                ⁢
                _discontinuous
              
            
            /
            
              T
              PWM_discontinuous
            
          
          =
          
            
              (
              
                
                  1
                  2
                
                ·
                
                  I
                  
                    peak_PWM
                    ⁢
                    _discontinuous
                  
                
                ·
                
                  t
                  
                    off_PWM
                    ⁢
                    _discontinuous
                  
                
              
              )
            
            /
            
              T
              PWM_discontinuous
            
          
        
      
    
    
      
        (
        17
        )
      
    
  




But from equation (14), equation (17) may be written as:

Iavg_PWM_discontinuous=QPWM_pulse_discontinuous/TPWM_discontinuous=(1⁄2·Ipeak_PWM_discontinuous·toff_PWM_discontinuous)/(TPFM/N)  (18)

As stated above, because it is assumed that Iavg_PFM just before a PFM-to-discontinuous-PWM transition equals Iavg_PWM_discontinuous just after such transition, one can obtain the following equality from equations (16) and (18):

1⁄2·Ipeak_PFM·toff_PFM/TPFM=1⁄2·Ipeak_PWM_discontinuous·toff_PWM_discontinuous/(TPFM/N)  (19)

Rearranging terms in equation (19) yields:

1⁄2·Ipeak_PFM·toff_PFM/TPFM=1⁄2·N·Ipeak_PWM_discontinuous·toff_PWM_discontinuous/TPFM  (20)

Because Vin, Vout, and L can be assumed to be the same just before and just after a PFM-to-discontinuous-PWM transition per above, toff_PFM and toff_PWM_discontinuous are represented, respectively, by the following equations:

toff_PFM=Ipeak_PFM·L/(Vout−Vin  (21)

toff_PWM_discontinuous=Ipeak_PWM_discontinuous·L/(Vout−Vin)  (22)

Substituting the values of toff_PFM and toff_PWM_discontinuous from equations (21) and (22) into equation (20) yields the following equation:

1⁄2·Ipeak_PFM·Ipeak_PFM·L/(Vout−Vin)/TPFM=1⁄2·N·Ipeak_PWM_discontinuous·peak_PWM_discontinuous·L/(Vout−Vin)/TPFM  (23)

Cancelling the common terms in equation (23) yields the following equation:

Ipeak_PFM2=N·Ipeak_PWM_discontinuous2  (24)

And taking the square root of both sides of equation (24) and rearranging the terms yields the following relations between Ipeak_PFM just before a PFM-to-discontinuous-PWM transition and Ipeak_PWM_discontinuous just after the PFM-to-discontinuous-PWM transition:




  
    
      
        
          I
          
            peak_PWM
            ⁢
            _discontinuous
          
        
        =
        
          
            I
            peak_PFM
          
          /
          
            N
          
        
      
    
    
      
        (
        25
        )
      
    
  
  
    
      
        
          I
          
            peak_PWM
            ⁢
            _discontinuous
          
        
        =
        
          
            I
            peak_PFM
          
          =
          
            S
            =
            
              1
              
                N
              
            
          
        
      
    
    
      
        (
        26
        )
      
    
  




Consequently, setting S equal to one over the square root of the ratio of the PFM_max and discontinuous-PWM frequencies just before and just after a PFM-to-discontinuous-PWM transition allows the boost converter 70 to poise itself, specifically to poise the voltage signal LOOP_CONTROL_1, for a smooth transition from a PFM mode to a discontinuous PWM mode such that there is minimal or no transition-induced transient on Vout. Such poising of LOOP_CONTROL_1 is described in more detail below.
Referring to FIGS. 5-7, the operations of the boost converter 70 during a PFM mode, and just before, during, and just after a PFM-to-discontinuous-PWM transition, are described, according to an embodiment.
During a PFM mode, the switching controller 26, in response to the control loops 32 and 33, maintains Vout at approximately its regulated value of




  
    V
    ref
  
  ·
  
    
      
        R
        44
      
      +
      
        R
        46
      
    
    
      R
      46
    
  




by driving the switching circuitry 18 at a switching frequency fs_PFM, which depends on the load 12, so as to generate to the inductor current IInductor(t) 72 in a manner similar to that described above in conjunction with FIGS. 1 and 4.

Furthermore, the control circuitry 14 opens the switch 90 to uncouple the loop-filter network 42 from the amplifier 38, and generates a signal MODE (e.g., the switching controller 26 may open the switch and generate the signal MODE as shown in FIG. 5), which causes the multiplexers 86 and 88 to couple to the summing comparator 24 the scaled voltage signals S·SAWTOOTH and S·LOOP_CONTROL_2 from the multipliers 82 and 84, respectively. Per equation (26),




  
    S
    =
    
      1
      
        N
      
    
  
  ,




where N=fs_PWM_discontinuous/fs_PFM_max per equation (14). Note that in an embodiment, fs_PWM_discontinuous is equal with the frequency of the oscillator (OSC) and N is a constant.

Referring to FIGS. 5 and 7, scaling the voltage signals SAWTOOTH and LOOP_CONTROL_2 by S causes, at least theoretically, the control loop 30 to “see” the inductor current IInductor(t) as being equal to Ipeak_PWM_discontinuous=Ipeak_PFM/√{square root over (N)} at a time tpeak when IInductor(t) actually equals Ipeak_PFM; therefore, at least theoretically (for example, when fs_PWM_discontinuous=fs_PFM_max), the control loop 30 “sees” IInductor (t) 76, the peak Ipeak_PWM_discontinuous of which occurs at the same time tpeak as the peak Ipeak_PFM of the actual PFM inductor current IInductor(t) 72. Because IInductor(t) 76 is not actually flowing through the filter inductor 16 (the inductor current IInductor(t) 72 is the current actually flowing through the filter inductor), IInductor(t) 76 is hereinafter referred to as a “virtual” inductor current.
If the virtual inductor current IInductor(t) 76 were the actual inductor current flowing through the filter inductor 16 at time tpeak, then the voltage signals LOOP_CONTROL_1, S·LOOP_CONTROL_2, and S·SAWTOOTH would have, at the time tpeak, respective values that would cause the signal SWITCHING_CONTROL to transition to a logic-high level so as to cause the switching controller 26 to turn off the transistor 58 and turn on the transistor 60 so that a discharging current Iinductor(t) (this discharging current is not shown in FIG. 7) could flow through the transistor 60 and toward the load 12.
Although the values of the voltage signals S·SAWTOOTH and S·LOOP_CONTROL_2 are set by the multipliers 82 and 84, respectively, the value of LOOP_CONTROL_1 is free to be set by the adjuster 80 by virtue of the switch 90 “breaking” the first control loop 28, i.e., by virtue of the switch 90 uncoupling the network 42 from the amplifier 38.
Consequently, in response to the switching controller 26, the adjuster 80 adjusts the level of the voltage signal LOOP_CONTROL_1 such that the voltage signal SWITCHING_CONTROL transitions from a logic-low level to a logic-high level at tpeak.
The switching controller 26 causes the adjuster 80 to adjust the value of LOOP_CONTROL_1, in an iterative, way depending on whether the logic-low-to-logic-high transition of SWITCHING_CONTROL occurs before, at the same time as, or after (theoretically) the time tpeak, which is the time that the comparator 56 of the control loop 32 transitions LOOP_CONTROL_3 from a logic-low level to a logic-high level.
If the logic-low-to-logic-high transition of SWITCHING_CONTROL occurs before the logic-low-to-logic-high transition of LOOP_CONTROL_3, then the switching controller 26 determines that the voltage level of LOOP_CONTROL_1 is too low, and causes the adjuster 80 to increase the voltage level of LOOP_CONTROL_1. For example, the switching controller 26 may include, or may have access to, a counter (not shown in FIG. 5), and may start the counter counting upward from a known initial value (e.g., 0) in response to the logic-low-to-logic-high transition of SWITCHING_CONTROL_, and stop the counter in response to the logic-low-to-logic-high transition of LOOP_CONTROL_3. Then, the switching controller 26 may cause the adjuster 80 to increase the value of LOOP_CONTROL_1 by an amount that is proportional to the count value. The factor of proportionality between the count value and the amount by which the adjuster 80 increases the value of LOOP_CONTROL_1 can be selected to impart a determined level of stability to the adjustment loop formed, in part, by the switching controller 26 and the adjuster 80. The switching controller 26 may continue to cause the adjuster 80 to increase the value of LOOP_CONTROL_1 once each PFM cycle until the logic-low-to-logic-high transition of SWITCHING_CONTROL no longer occurs before the logic-low-to-logic-high transition of LOOP_CONTROL_3.
If the logic-low-to-logic-high transition of SWITCHING_CONTROL occurs at approximately the same time as the logic-low-to-logic-high transition of LOOP_CONTROL_3, then the switching controller 26 determines that LOOP_CONTROL_1 has a proper level, and, therefore, causes the adjuster 80 to hold the level of LOOP_CONTROL_1 at its current value. For example, if the above-described count value is less than a selected threshold, then the switching controller 26 may “decide” not to alter the level of LOOP_CONTROL_1.
Because in response to the switching controller 26 turning off the transistor 58 the level of LOOP_CONTROL 2 drops to zero, if the level of LOOP_CONTROL_1 is too high, then the switching controller will not transition SWITCHING_CONTROL from a logic-low level to a logic-high level due to the sum S·LOOP_CONTROL_2 and S·SAWTOOTH never exceeding LOOP_CONTROL_1.
Consequently, if the switching controller 26 detects a logic-low-to-logic-high transition of LOOP_CONTROL_3 without detecting a corresponding logic-low-to-logic-high transition of SWITCHING_CONTROL, then the switching controller determines that the level of LOOP_CONTROL_1 is too high, and causes the adjuster 80 to decrease the level of LOOP_CONTROL_1. For example, the switching controller 26 may decrease the value of LOOP_CONTROL_1 by a fixed amount that is selected to impart a determined level of stability to the adjustment loop formed, in part, by the switching controller and the adjuster 80. The switching controller 26 may continue to cause the adjuster 80 to decrease the value of LOOP_CONTROL_1 once each PFM cycle until the logic-low-to-logic-high transition of SWITCHING_CONTROL occurs at the same time as, or slightly before, the logic-low-to-logic-high transition of LOOP_CONTROL_3.
By operating in the above-described iterative manner, the switching controller 26 and adjuster 80 poise the level of LOOP_CONTROL_1 for the correct inductor current Iinductor in the inductor 16 to maintain Vout approximately equal to




  
    V
    ref
  
  ·
  
    
      
        R
        44
      
      +
      
        R
        46
      
    
    
      R
      46
    
  




in a discontinuous PWM mode just after a PFM-to-discontinuous-PWM transition of the boost converter 70.

Still referring to FIGS. 5 and 7, the switching controller 26 monitors the switching frequency fs_PFM during a PFM mode. For example, the switching controller 26 may monitor fs_PFM by monitoring the frequency at which it switches the transistors 58 and 60, or may use an oscillator (which may be the same as, or different from, the oscillator 21 in FIG. 5) that limits the frequency to a known maximum value, corresponding to fs_PFM/N.
In response to fs_PFM approaching, equaling, or exceeding fs_PFM_max, the switching controller 26 causes the boost converter 70 to transition from a PFM mode to a discontinuous PWM mode. The switching controller 26 performs this transition, at least in part, by ignoring the signals LOOP_CONTROL_3 and LOOP_CONTROL_4, setting the multiplexers 82 and 84 so that they couple the unscaled versions of SAWTOOTH and LOOP_CONTROL_2, respectively, to the summing comparator 24, disabling the adjuster 80, closing the switch 90 so as to “close” the first control loop 28, and controlling the switching stage 18 in response to the signal SWITCHING_CONTROL.
Still referring to FIGS. 5-7, alternate embodiments of the boost converter 70 are contemplated. For example, alternate embodiments of the boost converter 10 of FIG. 1 may be applicable to the boost converter 70. Furthermore, the switching controller 26 may determine that the adjuster 80 is not to adjust the level of LOOP_CONTROL_1 every PFM cycle, but is to do so every m PFM cycles to reduce power consumption, where m is an integer and m>1. Moreover, the switching controller 26 may determine that the adjuster 80 is to adjust the level of LOOP_CONTROL_1 during the PFM mode regardless of the PFM switching frequency, or the switching controller may determine that the adjuster is to adjust the level of LOOP_CONTROL_1 during the PFM mode only when the PFM switching frequency is greater than a predetermined threshold, or is within a predetermined range of the maximum PFM switching frequency PFM_max (i.e., within a predetermined range of the PFM-to-discontinuous-PWM transition frequency). In addition, the scale factor S may have a suitable value other than




  
    1
    
      N
    
  
  .




Referring to FIGS. 8-13, described below is an embodiment of a technique for addressing the above-described second possible problem with the boost converter 10 of FIG. 1, which possible problem is that the output ripple voltage Vripple in PFM mode may depend heavily on quantities such as Vin and Vout, and thus may be relatively variable over a range of Vin, or from boost converter to boost converter with different Vout.
FIG. 8 is a plot of PFM pulses 100, 102, and 104 (i.e., a PFM pulse is the inductor current IIinductor(t) during the period ton_PFM+toff_PFM) generated by the boost converter 10 of FIG. 1 during a PFM mode for three different levels of Vin, according to an embodiment, where Ipeak_PFM is fixed as described above in conjunction with FIGS. 1 and 4, and where Vin is approximately 50% of Vout for the pulse 100, approximately 75% of Vout for the pulse 102, and approximately 92% of Vout for the pulse 104.
FIG. 9 is a plot of the charge per PFM pulse that the boost converter 10 of FIG. 1 delivers to the load 12 of FIG. 1 during a PFM mode versus Vin, according to an embodiment, where Ipeak_PFM is fixed as described above in conjunction with FIGS. 1 and 4.
FIG. 10 is a diagram of a boost converter 110, which is configured to reduce the dependency of Vripple on at least one of Vin and Vout, according to an embodiment.
FIG. 11 is a plot of PFM pulses 112, 114, and 116 generated by the boost converter 110 of FIG. 10 during a PFM mode for different levels of Vin, according to an embodiment, where Vin is approximately 50% of Vout for the pulse 112, approximately 75% of Vout for the pulse 114, and approximately 92% of Vout for the pulse 116.
FIG. 12 is a plot of the charge per PFM pulse that the boost converter 110 of FIG. 10 delivers during a PFM mode versus Vin, according to an embodiment, where the PFM pulse width ton_PFM+toff_PFM is approximately constant.
FIG. 13 is a plot of the charge per PFM pulse that the boost converter 110 of FIG. 10 delivers during a PFM mode versus Vin, according to another embodiment, where the PFM pulse width ton_PFM+toff_PFM is allowed to become longer at relatively high values of Vin so as to maintain ton_PFM at least as long a selected threshold time.
Referring to FIGS. 1 and 8, because the boost converter 10 limits the peak of the inductor current IInductor(t) to Ipeak_ref during a PFM mode, the amount of charge that the boost converter delivers to the combination of the output capacitor 20 and the load 12 during a PFM pulse may depend heavily on at least Vin and Vout.
Referring to FIG. 8, as described above in conjunction with FIGS. 1-7, the amount of charge that the boost converter 10 delivers per PFM pulse is proportional to the area under a right-angled triangle having a hypotenuse formed by the linear ramping down of IInductor(t) during toff_PFM.
It is evident from FIG. 8 that, for example, this area is inversely proportional to Vout−Vin.
Following is an explanation of the dependencies of the per-PFM-pulse charge on Vin and Vout.
The peak inductor current Ipeak_PFM during the PFM mode is known to be equal to IPeak_ref/R54 as described above in conjunction with FIGS. 1-4; therefore, from equation (2), one can derive the following equations:

(Vout−Vin)/L=(IPeak_PFM−0)/toff_PFM  (27)

toff_PFM=Ipeak_PFM·L(Vout−Vin)  (28)

Therefore, because Vin is less than Vout for the boost converter 10, toff_PFM increases/decreases with an increase/decrease in Vin (i.e., toff_PFM follows Vin), and increases/decreases with a decrease/increase in Vout (i.e., toff_PFM inversely follows Vout).
Although Vout is typically fixed for a particular instantiation of the boost converter 10 (except for boost converters, e.g., with digitally programmable output voltages), Vout may change from instantiation to instantiation, thus possibly causing Vripple to be significantly different from instantiation to instantiation having the same or similar Vin.
Vin, however, may change not only from instantiation to instantiation of the boost converter 10, but also may change over time for a single instantiation of the boost converter 10, particularly if Vin is supplied by a battery that alternately discharges and is charged, or is supplied alternately by a battery and a power supply or battery charger, such as an AC adapter.
Referring to FIGS. 1 and 9, it is evident that the amount of charge that the boost converter 10 delivers to the combination of the output capacitor 20 and the load 12 per PFM pulse increases exponentially as Vin increases, assuming that Vout is unchanging.
Unfortunately, changes in the amount of charge that the boost converter 10 delivers to the combination of the capacitor 20 and the load 12 per PFM pulse can cause a number of problems. For example, suppose that an instantiation of the boost converter 10 is designed to provide a particular output ripple voltage Vripple at a selected nominal input voltage Vin_nominal. If Vin increases significantly above Vin _nominal, then although the PFM switching frequency fs_PFM decreases, thus increasing the efficiency of the boost converter 10, Vripple increases significantly, and may become too large for some applications. Conversely, if Vin decreases significantly below Vin_nominal, then although Vripple decreases, the PFM switching frequency fs_PFM increases, thus decreasing the efficiency of the boost converter 10 during a PFM mode in which high efficiency is coveted; that is, an application may be able to tolerate a higher Vripple to increase boost-converter efficiency during a PFM mode at this lower input voltage Vin.
FIG. 10 is a diagram of a boost converter 110, which is configured to reduce the dependence of the output voltage ripple Vripple on at least Vin and Vout, according to an embodiment.
The boost converter 110 is similar to the boost converter 70 of FIG. 5, except that in the boost converter 110, the control circuit 14 is configured to adjust the level of the reference voltage Ipeak_ref at the inverting input node of the comparator 56, and includes a PFM pulse-width determiner (not shown in FIG. 10). In the embodiment described below, the switching controller 26 is configured to adjust Ipeak_ref and includes, or has access to, a counter (not shown in FIG. 10) that is configured to determine the PFM pulse width.
In operation during a PFM mode, the control circuitry 14 of the boost converter 110 uses the comparator 35 and the ability of the switching controller 26 to set Ipeak_ref to reduce the dependency of Vripple on at least Vin and Vout by maintaining the PFM pulse width ton_PFM+toff_PFM approximately constant. For example, a designer of the boost converter 110 can select the constant value of the PFM pulse width that provides a suitable Vripple at a suitable nominal input voltage Vin_nominal.
At some point before entering, or upon entering, a PFM mode, the switching controller 26 sets Ipeak_ref to an initial value. For example, the switching controller 26 may set Ipeak_ref=√{square root over (N)}·Ipeak_PWM_discontinous, where N has a value per equation (14), and Ipeak_PWM_discontinuous is the peak of the inductor current IInductor(t) just before the switching controller transitions the boost converter 110 from a discontinuous PWM mode to a PFM mode.
During the PFM mode after the discontinuous-PWM-to-PFM transition, in response to turning on the transistor 58 to begin a PFM pulse, the switching controller 26 starts the pulse-width counter counting (either up or down) from a selected initial count value. While the transistor 58 is on and the transistor 60 is off, the output of the comparator 35 is a logic-low level because the voltage across the transistor 60 is negative, Vout is higher than the voltage at the junction between the inductor 16 and the on transistor 58.
Next, in response to the inductor current IIinductor(t) equaling or exceeding Ipeak_ref/R54, the comparator 56 transitions the signal LOOP_CONTROL_3 from a logic-low level to a logic-high level.
Then, in response to LOOP_CONTROL_3 transitioning from a logic-low level to a logic-high level, the switching controller 26 turns off the transistor 58 and turns on the transistor 60 to end ton_PFM and to start toff_PFM.
Next, in response to the switching controller 26 turning on the transistor 60, the voltage across the transistor 60 transitions to a positive value due to Vout being lower than the voltage at the junction between the inductor 16 and the on transistor 58.
Then, in response to the voltage across the transistor 60 transitioning to a positive value, the output of the comparator 35 transitions from a logic-low level to a logic-high level.
In response to the logic-low-to-logic-high transition of the output of the comparator 35, the switching controller 26 causes the pulse-width counter to continue to count.
Next, in response to the inductor current IInductor(t) equaling zero, or being close to zero, at the end of toff_PFM, the comparator 35 transitions its output from a logic-high level to a logic-low level because Vout equals, or is greater than, the voltage at the junction between the inductor 16 and the transistor 58.
Then, in response to the logic-high-to-logic-low transition of the output of the comparator 35, the switching controller 26 turns off the transistor 60 and stops the pulse-width counter from counting.
Next, the switching controller 26 compares the value in the counter to the previously selected constant PFM pulse width.
If the value in the counter is greater than the constant PFM pulse width, then the switching controller 26 determines that the actual PFM pulse width is too long, and reduces Ipeak_ref by a first amount, which may be selected to impart stability to the pulse-width-adjustment loop (the pulse-width-adjustment loop may include, at least in part, the comparator 56, the pulse-width counter, and a comparator that the switching controller 26 may use to compare the count value to the selected constant PFM pulse width). For example, the first amount may be a constant value, or may be a variable value that the switching controller selects dynamically
If the value in the counter equals or is close to the constant PFM pulse width, then the switching controller 26 determines that the actual PFM pulse width is of a suitable length, and does not alter Ipeak_ref.
And if the value in the counter is less than the constant PFM pulse width, then the switching controller 26 determines that the actual PFM pulse width is too short, and increases Ipeak_ref by a second amount, which may be selected to impart stability to the pulse-width-adjustment loop. For example, the second amount may be a constant value, or may be a variable value that the switching controller dynamically selects. Furthermore, the second amount can equal, or differ from, the first amount.
The switching controller 26 repeats the above-described iterative procedure for each PFM pulse so as to drive the PFM pulse width toward, and to maintain the PFM pulse width approximately at, the selected constant value. Alternatively, the switching controller 26 may perform the above-described iterative procedure only during each nth PFM pulse to reduce the power consumption of the boost converter 110, where n is an integer greater than one, and where n may or may not equal m, which is described above in conjunction with FIGS. 5-7.
Referring to FIGS. 10-11, according to the above-described operations, the boost converter 110 is configured to generate PFM pulses 112, 114, and 116 for three different values of Vin (Vout is the same for all three pulses), according to an embodiment, where Vin is approximately 50% of Vout for the pulse 112, approximately 75% of Vout for the pulse 114, and approximately 92% of Vout for the pulse 116 (e.g., Vout=5.0 Volts). It is evident that the because the boost converter 110 allows the peak inductor current Ipeak_PFM to change with changes in Vin, the areas under the toff_PFM triangles, and thus the charges that the boost converter 110 delivers per PFM pulse, are more uniform as compared to the PFM pulses of FIG. 8 generated by the boost converter 10 of FIG. 1.
Referring to FIGS. 10 and 12, the charge delivered by the boost converter 110 per PFM pulse is relatively constant over a wider range of input voltage (with Vout remaining constant over this range) as compared to the exponentially increasing charge delivered per PFM pulse (FIG. 9) by the boost converter 10 of FIG. 1.
But still referring to FIGS. 10 and 12, the charge delivered per PFM pulse by the boost converter 110 is significantly flatter than that of FIG. 9, but tends to fall off as Vin approaches Vout (e.g., while Vin is greater than or equal to about 80% of Vout).
Referring to FIGS. 10 and 13, to reduce or reverse the delivered-charge fall off described above in conjunction with FIGS. 10 and 12, the switching controller 26 of the boost converter 110 is configured to allow an increase in the PFM pulse width ton_PFM+toff_PFM as Vin increases, according to an embodiment. For example, the switching controller 26 may increase the PFM pulse width in response to Vin being greater than or equal to, for example, about 80% or 90% of Vout. And the amount by which the switching controller 26 increases the PFM pulse width in an application may be any amount that is determined suitable for that application.
A technique for increasing the PFM pulse width that the switching controller 26 may be configured to implement is to prevent ton_PFM from falling below a selected threshold, e.g., approximately 60 nanoseconds (ns), so as to allow Ipeak_PFM and toff_PFM to increase beyond the values that they would have if the switching controller were to hold the PFM pulse width to a constant length.
Referring again to FIGS. 8-13, alternate embodiments of the boost converter 110 are contemplated. For example, alternate embodiments described above for the boost converters 10 and 70 of FIGS. 1 and 5 may also be applicable to the boost converter 110. Furthermore, instead of maintaining the PFM pulse width ton_PFM+toff_PFM constant, the boost converter 110 may maintain one of ton_PFM and toff_PFM, but not both of ton_PFM and toff_PFM, constant. Moreover, the above-described techniques may also be useful in maintaining Vripple relatively constant, or at least within a suitable range, over ranges of the values L and C of the inductor 16 and capacitor 20, respectively, if the PFM pulse width is adjusted to compensate for the known values of L and C.
Referring to FIGS. 14-15, described below is another embodiment of a technique for addressing the above-described second possible problem with the boost converter 10 of FIG. 1, which possible problem is that the output ripple voltage Vripple may depend heavily on quantities such as Vin and Vout, and thus may be relatively unpredictable over a range of Vin, or from boost converter to boost converter with different Vout. According to the below-described embodiment, one can modify any of the boost converters 10, 70, and 110 of FIGS. 1, 5, and 10, respectively, such that the boost converter sets and holds Vripple to an approximately constant amplitude. But for brevity, only such modification of the boost converter 110 is described, it being understood that such modifications to the boost converters 1 and 70 may be similar.
Referring to the boost converter 110 of FIG. 10, the following equation relates the current through the output capacitor 20 to the voltage Vout across this capacitor:

ICout(t)=Cout·dVout(t)/dt  (29)

Because during a PFM mode the load current ILoad(t) is relatively low, one can assume that the value of ILoad(t) contributes negligibly to Vripple, but sets the frequency of that ripple. Therefore, in view of this assumption, one can derive from equation (29) the following equation for Vripple:

Vripple≈Iout_avg·(TPFM/Cout).  (30)

where Iout_avg is given by the following equation (because of the theoretical triangle formed by the ramping-down inductor current IInductor(t) during toff_PFM):

Iout_avg=Ipeak_PFM/2(toff_PFM/TPFM)  (31)

and where toff_PFM is given by equation (28).

Therefore, from equations (28), (30), and (31) one can derive the following expressions for Vripple, Ipeak_PFM, and Ipeak_ref as a function of Vripple:




  
    
      
        
          
        
        ⁢
        
          
            V
            ripple
          
          =
          
            
              I
              peak_PFM
              2
            
            ·
            
              L
              /
              
                [
                
                  2
                  ·
                  
                    (
                    
                      
                        V
                        out
                      
                      -
                      
                        V
                        in
                      
                    
                    )
                  
                  ·
                  
                    C
                    out
                  
                
                ]
              
            
          
        
      
    
    
      
        (
        32
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          
            I
            peak_PFM
          
          =
          
            
              
                2
                ·
                Vripple
                ·
                
                  C
                  out
                
                ·
                
                  (
                  
                    
                      V
                      out
                    
                    -
                    
                      V
                      in
                    
                  
                  )
                
              
              L
            
          
        
      
    
    
      
        (
        33
        )
      
    
  
  
    
      
        
          I
          peak_ref
        
        =
        
          
            
              I
              peak_PFM
            
            ·
            
              R
              54
            
          
          =
          
            
              
                
                  2
                  ·
                  Vripple
                  ·
                  
                    C
                    out
                  
                  ·
                  
                    (
                    
                      
                        V
                        out
                      
                      -
                      
                        V
                        in
                      
                    
                    )
                  
                
                L
              
            
            ·
            
              R
              54
            
          
        
      
    
    
      
        (
        34
        )
      
    
  




Therefore, where Cout, Vout, Vin, L, and the desired value of Vripple are known, using equation (34) one can determine from these known quantities the value of Ipeak_ref that yields the desired amplitude of the output ripple voltage Vripple. And, as described below, one can modify the boost converter 110 of FIG. 10 to generate Vripple having this desired amplitude.
FIG. 14 is a diagram of a ripple-adjust circuit 120, which the control circuitry 14 of the boost converter 110 of FIG. 10 may include to set Vripple to an approximately constant desired level per equation (34), according to an embodiment.
The ripple-adjust circuit 120 includes a differential amplifier stage 122, an analog-to-digital converter (ADC) 124, a computing circuit 126 such as a microprocessor or microcontroller core, a memory 128, which is configured to store the values of R54, Cout, and L, and the selected value of Vripple, and a digital-to-analog converter (DAC) 130. The circuit 120 may also include a circuitry (not shown) for determining the values of R54, Cout, and L if these values are not stored in the memory 128.
In operation during a PFM mode, the differential amplifier stage 122 receives Vin on an inverting input node and Vout on a noninverting input node, and generates Vout−Vin on an output node.
The ADC 124 converts Vout−Vin from an analog value to a digital value, and provides this digital value to the computing circuit 126.
In addition to receiving the digital value of Vout−Vin from the ADC 124, the computing circuit 126 receives the values of R54, Cout, L, and Vripple from the memory 128, and computes a corresponding digital value of Ipeak_ref per equation (34).
The DAC 130 converts the computed digital value of Ipeak_ref into a corresponding analog voltage Ipeak_ref, which the DAC provides to the inverting input node of the comparator 56 of the boost converter 110 of FIG. 10.
The ripple-adjust circuit 120 can repeat the above procedure periodically (e.g., once each PFM cycle, or, to reduce power consumption, once every oth PFM cycles, where o may or may not equal n or m, which are described above) to account for changes in Vin or in Vout, although Vout is typically less likely to change than Vin.
Still referring to FIG. 14, alternate embodiments of the ripple-adjust circuitry 120 are contemplated. For example, the amplifier stage 122 may be omitted, the memory 128 may store the value of Vout (or Vout may be otherwise provided to the computing circuit 126), the ADC 124 may receive Vin, and the computing circuit may calculate Vout−Vin in addition to calculating Ipeak_ref as described above. Furthermore, the computing circuit could account for the value of R54 by including a settable scale factor that equals, or is otherwise equivalent to, the value of R54.
FIG. 15 is a diagram of a ripple-adjust circuit 140, which, like the ripple-adjust circuit 120 FIG. 14, any of the boost converters 10, 70, and 110 of FIGS. 1, 5, and 10 may include to set Vripple to an approximately constant value per equation (34), according to an embodiment. For example purposes, the ripple-adjust circuit 140 is hereinafter described as being part of the boost converter 110 of FIG. 10, although it is understood that the structure and operation of the ripple-adjust circuit may be similar if the ripple-adjust circuit is part of another boost circuit such as the boost circuit 10 of FIG. 1 or the boost circuit 70 of FIG. 5.
The ripple-adjust circuit 140 includes a look-up table (LUT) 142, which receives values for at least some of Vin, Vout, R54, Cout, L, and Vripple, generates from these values a value for Ipeak_ref, and provides a voltage level corresponding to this value of Ipeak_ref to the inverting input node of the comparator 56 of the boost converter 110 of FIG. 10. For example, the LUT 142 may receive Vin from the boost converter 110 via an ADC, and may receive values for R54, C, L, Vout, and Vripple from a memory (not shown in FIG. 15) such as the memory 128 of FIG. 14. Or, the LUT 142 may itself store values for R54, C, L, Vout, and Vripple. Alternatively, the LUT 142 may receive Vout from the boost converter 110 via an ADC.
The LUT 142 may store different values of Ipeak_ref for different ranges of any one or more of Vin, R54, C, L, Vout, and Vripple. For example, the LUT 142 may store a respective value of Ipeak_ref for each 0.5 V step of Vin from 0.5 V to Vout.
The ripple-adjust circuit 140 can repeat the above procedure periodically (e.g., once each PFM cycle, or, to reduce power consumption, once every pth PFM cycles, where p may or may not equal o, n, or m, which are described above) to account for changes in Vin.
Still referring to FIG. 15, alternate embodiments of the ripple-adjust circuitry 140 are contemplated. For example, the LUT 142 may be replaced by a computing circuit such as a microprocessor or microcontroller, or the ripple-adjust circuitry may include such a computing circuit in addition to the LUT.
Referring to FIGS. 10 and 16, described below is an embodiment of a technique for addressing the third above-described possible problem with the boost converter 10 (FIG. 1), which possible problem is that transitioning from a discontinuous PWM mode to a PFM mode in response to sensing an attribute (e.g., peak, average) of the inductor current IInductor(t) may result in transitioning to a PFM mode at a relatively imprecise load point, i.e., a load point that is significantly different from PWM-to-PFM transition to PWM-to-PFM transition, and may result in an imprecise hysteresis range, i.e., a range that is significantly different form PWM-to-PFM transition to PWM-to-PFM transition. For example, this imprecise (variable) hysteresis range can be caused by different levels of changing Vin and Vout, and by inaccuracies in sensing circuitry. According to the below-described embodiment, one can modify any of the boost converters 70 and 110 of FIGS. 5 and 10, respectively, such that the boost converter transitions from a discontinuous PWM mode to a PFM mode at a relatively precise load point and with a relatively precise hysteresis range. But for brevity, only such modification of the boost converter 110 is described, it being understood that such modification to the boost converter 70 may be similar.
In an embodiment where the boost converter 110 is configured such that fs_PWM_discontinuous/fs_PFM_max=N per equation (14) and to maintain the PFM pulse width approximately constant, or having a minimum ton_PFM as described above in conjunction with FIGS. 8-13, the control circuitry 14 can transition the boost converter from a discontinuous PWM mode to a PFM mode when the PWM pulse width Pulse_WidthPWM_discontinuous=ton_PWM_discontinuous+toff_PWM_discontinuous in discontinuous PWM mode is less than or equal to a selected length.
Per equations (2) and (21), the known PFM pulse width Pulse_WidthPFM=ton_PFM+toff_PFM is given by the following equation:

ton_PFM+toff_PFM=Ipeak_PFM·L/Vin+Ipeak_PFM·L/(Vout−Vin)  (35)

where Ipeak_PFM is the peak of the inductor current IInductor(t) during the PFM mode at the max PFM switching frequency fs_PFM_max.

Per equation (25), Ipeak_PFM is given by the following equation:

Ipeak_PFM=√{square root over (N)}·Ipeak_PWM_discontinuous  (36)

Therefore, using equation (36) to substitute for Ipeak_PFM in equation (35) yields the following equation:

ton_PFM+toff_PFM=√{square root over (N)}·Ipeak_PWM_discontinuous·L/Vin+√{square root over (N)}·Ipeak_PWM_discontinuous·L/(Vout−Vin)  (37)

where Ipeak_PWM_discontinuous is the peak current in a discontinuous PWM mode just prior to a discontinuous-PWM-to-PFM transition.

And per equations (2) and (22), Ipeak_PWM_discontinuous is given by the following equations:

Ipeak_PWM_discontinuous=ton_PWM_discontinuous·Vin/L  (38)

Ipeak_PWM_discontinuous=toff_PWM_discontinuous·(Vout−Vin)/L  (39)

Substituting for Ipeak_PWM_discontinuous in equation (37) per equations (38) and (39) yields the following equation:

ton_PFM+toff_PFM=√{square root over (N)}·ton_PWM_discontinuous·(Vin/L)·(L/Vin)+√{square root over (N)}·toff_PWM_discontinuous[(Vout−Vin)/L]·[L(Vout−Vin)]  (40)

Cancelling common terms, equation (40) reduces to the following equation:

ton_PFM+toff_PFM=√{square root over (N)}·(ton_PWM_discontinuous+toff_PWM_discontinuous)  (41)

And because ton_PFM+toff_PFM=Pulse-WidthpPFM and ton_PWM_discontinuous+toff_PWM_discontinuous=Pulse-WidthPWM_discontinuous, equation (41) yields the following relation between Pulse_WidthPFM and Pulse_WidthPWM_discontinuous:

Pulse_WidthPWM_discontinuous=Pulse_WidthPFM/√{square root over (N)}.  (42)

Therefore, during a discontinuous PWM mode, in response to the PWM pulse width Pulse_WidthPWM_discontinuous≦Pulse_WidthPFM/√{square root over (N)}, the control circuitry 14 (the switching controller 26 in the described embodiment) of the boost converter 110 “knows” that it can transition the boost converter to the PFM mode because the boost converter can, in the PFM mode at the maximum PFM switching frequency fs_PFM_max, provide the load 12 with the same level of power that it is providing to the load in the discontinuous PWM mode.
Furthermore, to provide a transition buffer, i.e., a hysteresis range, the switching controller 26 may not transition the boost converter 110 to the PFM mode until Pulse_WidthPWM_discontinuous<Pulse_WidthPFM/√{square root over (N)}. The PWM pulse 150 has a Pulse_WidthPWM_discontinuous_150 that is equal to Pulse_WidthPFM/√{square root over (N)}, where Pulse_WidthPFM is the width of the PFM pulse 152. But the switching controller 26 does not transition the boost converter 110 to the PFM mode until a PWM pulse 154 has a pulse width Pulse_WidthPWM_discontinuous_154 that is less than (e.g., approximately 10% less than) Pulse_WidthPFM/√{square root over (N)}. Such a transition hysteresis range helps to prevent a situation where the switching controller 26 is transitioning (or even oscillating) back and forth between discontinuous PWM mode and PFM mode because the load 12 is at or near a “line” that is both the discontinuous-PWM-to-PFM transition line and the PFM-to-discontinuous-PWM transition line.
Still referring to FIGS. 10 and 16, the boost converter 110 can monitor Pulse_WidthPWM_discontinuous using the comparator 35 and a counter (not shown in FIG. 10) in a manner similar to the manner described above in conjunction with FIGS. 8-13.
Referring to FIGS. 5-16, alternate embodiments are contemplated. For example, although boost converters 70 and 110 are described, some or all of the above-described embodiments may be applicable to power supplies other than boost converters, such as buck converters, flyback converters, inverting-boost converters, single-ended primary-inductor converters (SEPICs), and buck-boost converters.
FIG. 17 is a block diagram of an embodiment of a system or device 160, which incorporates one or more of the boost converters 10, 70 and 110 of FIGS. 1, 5, and 10, according to an embodiment; but for brevity, the device is described below as including only a single instance of the boost converter 110 of FIG. 10. Examples of the device 160 include, but are not limited to, a smart phone, pad computer, laptop computer, or personal computer. Furthermore, although the device 160 is described as a device, it may be any apparatus or system for which embodiments of one or more of the boost converters 10, 70, and 110 are suited.
The device 160 includes computing circuitry 162, which includes a processor 164; the device also includes at least one input device 166, at least one output device 168, and at least one data-storage device 170.
The at least one output device 168 includes a display 172 and the boost converter 110 of FIG. 10, which powers the display. For example, the display 172 may be a liquid-crystal display (LCD) for a smart phone.
In addition to processing data, the processor 164 may program or otherwise control the boost converter 110. For example, the functions of the boost converter's control circuitry 14 (FIG. 10) may be performed by the processor 164.
The input device (e.g., keyboard, mouse) 166 allows the providing of data, programming, and commands to the computing circuitry 162.
The display 172 (and any other included output device 168) allows the computing circuitry 162 to provide data in a form (e.g., still image or video) perceivable by a human operator.
And the data-storage device (e.g., flash drive, hard-disk drive, RAM, EPROM, EEPROM, optical drive) 170 allows for the storage of, e.g., programs and data.
Still referring to FIG. 17, alternate embodiments of the device 160 are contemplated. For example, the processor 164 may be a microprocessor or a microcontroller.
From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated. Moreover, the components described above may be disposed on a single or multiple IC dies to form one or more ICs, and these one or more ICs may be coupled to one or more other ICs. In addition, any described component or operation may be implemented/performed in hardware, software, firmware, or a combination of any two or more of hardware, software, and firmware. Furthermore, one or more components of a described apparatus or system may have been omitted from the description for clarity or another reason. Moreover, one or more components of a described apparatus or system that have been included in the description may be omitted from the apparatus or system.

## Claims

1. A power supply controller, comprising:
a comparator configured to compare a magnitude of a charging current to a magnitude of a threshold;
switching circuitry configured
to cause the charging current to flow until the comparator indicates that the magnitude of the charging current is greater than or equal to the magnitude of the threshold, and
to cause a discharging current to flow in response to the comparator indicating that the magnitude of the charging current is greater than or equal to the magnitude of the threshold; and

an adjuster circuit configured to adjust the magnitude of the threshold in response to at least one of a duration of a charging period during which the charging current flows and a duration of a discharging period during which the discharging current flows.

2. The power supply controller of claim 1 wherein the switching circuitry is configured:
to cause the discharging current to flow to an output node; and
to regulate an output voltage at the output node by controlling a frequency at which the charging and discharging currents occur.

3. The power supply controller of claim 1 wherein the switching circuitry is configured to cause the charging and discharging currents to flow through an inductor.

4. The power supply controller of claim 1 wherein the adjuster circuit is configured to adjust the magnitude of the threshold in response to the duration of the charging period.

5. The power supply controller of claim 1 wherein the adjuster circuit is configured to adjust the magnitude of the threshold in response to the duration of the discharging period.

6. The power supply controller of claim 1 wherein the adjuster circuit is configured to adjust the magnitude of the threshold in response to a sum of the durations of the charging and discharging periods.

7. A power supply controller, comprising:
a comparator configured to compare a magnitude of a charging current to a magnitude of a threshold:
switching circuitry configured
to cause the charging current to flow from an input voltage until the comparator indicates that the magnitude of the charging current is greater than or equal to the magnitude of the threshold,
to cause a discharging current to flow from the input voltage to an output node in response to the comparator indicating that the magnitude of the charging current is greater than or equal to the magnitude of the threshold, and
to regulate an output voltage at the output node by controlling a frequency at which the charging and discharging currents occur; and

an adjuster circuit configured to adjust the magnitude of the threshold in response to at least one of a charging period during which the charging current flows and a discharging period during which the discharging current flows such that an amount of charge that the discharging current delivers to the output node is approximately constant over a respective range of at least one of the input voltage and the output voltage.

8. A power supply, comprising:
an input node configured to receive an input voltage;
an output node configured to carry an output voltage;
a reference node;
an inductor coupled to the input node;
switching circuitry configured
to generate a charging current that flows from the input node, through the inductor, and to the reference node during a charging period,
to end the charging period and to begin a discharging period in response to a magnitude of the charging current equaling or exceeding a magnitude of a peak-current threshold, and
to generate a discharging current that flows from the input node, through the inductor, to the output node during the discharging period; and

an adjuster circuit configured to increase the magnitude of the peak-current threshold in response to a length of at least one of the charging period and the discharging period being less than a length threshold, and to decrease the magnitude of the peak-current threshold in response to the length being greater than the length threshold.

9. The power supply of claim 8 wherein the adjuster circuit is configured to regulate the output voltage by controlling a frequency at which the switching circuitry generates the charging and discharging currents.

10. The power supply of claim 8 wherein the adjuster circuit is configured to increase and to decrease the magnitude of the peak-current threshold in response to a length of the charging period.

11. The power supply of claim 8 wherein the adjuster circuit is configured to increase and to decrease the magnitude of the peak-current threshold in response to a length of the discharging period.

12. The power supply of claim 8 wherein the adjuster circuit is configured to increase and to decrease the magnitude of the peak-current threshold in response to a sum of lengths of the charging and discharging periods.

13. The power supply of claim 8 wherein the adjuster circuit is configured to increase and to decrease the magnitude of the peak-current threshold such that an amount of charge that the discharging current delivers to the output node is within a predetermined range.

14. A system, comprising:
a power supply, including
an input node configured to receive an input voltage,
an output node configured to carry an output voltage,
a reference node,
an inductor coupled to the input node,
a comparator configured to compare a magnitude of a threshold to a magnitude of a charging current that flows from the input node, through the inductor, and to the reference node,
switching circuitry configured
to generate the charging current during a charging period of a discontinuous mode of operation,
to end the charging period and to begin a discharging period during the discontinuous mode of operation in response to the comparator indicating that the magnitude of the charging current equals or exceeds the magnitude of the threshold, and
to generate a discharging current that flows from the input node, through the inductor, to the output node during the discharging period, and

an adjusting circuit configured to adjust the magnitude of the threshold in response to a length of at least one of the charging period and the discharging period; and

a load coupled to the output node.

15. The system of claim 14 wherein the power supply includes a boost power supply that is configured to generate the output voltage having a higher magnitude than the input voltage.

16. The system of claim 14 wherein the load includes at least one of a microprocessor and a microcontroller.

17. The system of claim 14 wherein the load includes a display.

18. A method, comprising:
generating a charging current until a magnitude of the charging current equals or exceeds the magnitude of a threshold;
generating a discharging current in response to the magnitude of the charging current equaling or exceeding the magnitude of the threshold; and
adjusting the magnitude of the threshold in response to a duration of at least one of a charging time during which the charging current flows and a discharging time during which the discharging current flows.

19. The method of claim 18, wherein generating the charging current includes starting the charging current from approximately zero.

20. The method of claim 18 wherein generating the discharging current includes generating the discharging current until the discharging current approximately equals zero.

21. The method of claim 18 wherein adjusting the magnitude of the threshold includes adjusting the magnitude of the threshold to cause the charging period to have an approximately constant length from charging period to charging period.

22. The method of claim 18 wherein adjusting the magnitude of the threshold includes adjusting the magnitude of the threshold to cause the discharging period to have an approximately constant length from discharging period to discharging period.

23. The method of claim 18 wherein adjusting the magnitude of the threshold includes adjusting the magnitude of the threshold to cause a combination of the charging and discharging periods to have an approximately constant length from charging and discharging period to charging and discharging period.

24. The method of claim 18, further comprising:
wherein generating the charging current includes generating the charging current in response to an input voltage;
wherein adjusting the magnitude of the threshold includes adjusting the magnitude of the threshold to cause the charging period to have a length that is approximately equal to a value; and
adjusting the value in response to the input voltage.

25. A non-transitory computer-readable medium storing instructions that, when executed by a computing apparatus, cause the computing apparatus or another apparatus under control of the computing apparatus:
to generate a charging current until a magnitude of the charging current equals or exceeds a magnitude of a threshold;
to generate a discharging current in response to the magnitude of the charging current equaling or exceeding the magnitude of the threshold; and
to adjust the magnitude of the threshold in response to a duration of at least one of a charging phase during which the charging current flows and a discharging phase during which the discharging current flows.