# Patent

## Title
Scheme for erasure locator polynomial calculation in error-and-erasure decoder

## Abstract

A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

## Background
FIELD OF THE INVENTION
The present invention relates to error-and-erasure decoders generally and, more particularly, to a scheme for erasure locator polynomial calculation in an error-and-erasure decoder.
BACKGROUND OF THE INVENTION
Reed-Solomon (RS) codes are a powerful class of multiple error-correcting codes. RS codes have a wide range of applications, such as optical communications, wireless communications and magnetic recording systems. When applying systematic Reed-Solomon encoding, data is transmitted in codewords that represent a combination of the original data symbols and a number of parity symbols. An RS code that uses 2t parity symbols is commonly correctable to t errors. An RS decoder uses the 2t parity symbols to correct a received message, even if the received message experiences up to t errors during transmission.
In many modern communication systems, RS decoders use extra information along with the received data. A reliability value is calculated for each received data symbol. Received data symbols with very small reliability are called erasures. If a particular data symbol in a received codeword is known to be an erasure, a value of the particular symbol is ignored when the RS decoder attempts to decode the codeword. If ν errors and ρ erasures occur during transmission of a codeword, the codeword can be corrected if and only if ν+ρ≦2t. RS decoders that use information about erasures are called error-and-erasure decoders. The error-and-erasure decoding techniques involve the construction of erasure locator polynomials. The erasure locator polynomials accumulate information about all of the erasures for use in the decoding process.
SUMMARY OF THE INVENTION
The present invention concerns a method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing a plurality of current values in a plurality of registers at a current one of a plurality of moments, (B) generating a plurality of first values by multiplying each one of the current values by a respective one of a plurality of constants, (C) generating a plurality of second values by gating at least all but one of the first values with a current one of plurality of erasure values of an erasure position vector, (D) generating a plurality of next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next one of the moments and (F) generating an output signal carrying the current values at a last of the moments such that the current values form a plurality of coefficients of the erasure locator polynomial.
The objects, features and advantages of the present invention include providing a method and/or apparatus implementing a scheme for erasure locator polynomial calculation in an error-and-erasure decoder that may (i) provide space-efficient implementations, (ii) use constant Galois field multipliers and/or (iii) have a smaller timing delay than conventional implementations.



BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
FIG. 1 is a first set of formulae;
FIG. 2 is a functional flow diagram of a system in accordance with a preferred embodiment of the present invention;
FIG. 3 is a detailed functional flow diagram of a first example embodiment of a reconstruction circuit;
FIG. 4 is a detailed functional flow diagram of a second example embodiment of the reconstruction circuit;
FIG. 5 is a second set of formulae;
FIG. 6 is a block diagram of a first example embodiment of an erasure polynomial calculator using constant Galois field multipliers; and
FIG. 7 is a block diagram of a second example embodiment of the erasure polynomial calculator.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention generally concerns a method and hardware scheme for calculating an erasure locator polynomial. Let Fq be a finite field with q=2d elements and primitive element αεFq. Let RS(n,k,t) be a primitive Reed-Solomon code over Fq with n=q−1 representing a code length, k representing a number of information symbols and t representing a number of errors. Consider a vector v=(v0, . . . , vn−1)εFqn identified with a polynomial v(x)=v0+v1x+ . . . +vn−1xn−1 εFq[x]. By the definition of Reed-Solomon codes, a codeword c(x)=c0+c1x+ . . . +cn−1xn−1εRS(n,k,t) if any only if c(α1)=c(α2)= . . . =c(α2t)=0.
Referring to FIG. 1, a first set of formulae is shown. The original codeword (polynomial) c(x)εRS(n,k,t) may be sent through a channel that may induce ν errors and ρ erasures, where 2ν+ρ≦2t. Therefore, a receiving end of the channel may generate the received codeword (polynomial) v(x)=c(x)+e(x), where e(x) is an errata polynomial. The errata polynomial e(x) is generally defined by formula (1), as shown in FIG. 1.
The received codeword v(x) may have a set of ν error positions (e.g., I={i1, . . . , iν}) that may be unknown at the time of reception. The received codeword v(x) may also have a set of ρ erasure positions (e.g., J={j1, . . . , jρ}) that may be determined ahead of the decoding by the receiver circuitry due to the low reliability of some of the received symbols. An error-and-erasure decoding generally calculates the erasure polynomial e(x) and thus may reconstruct the original codeword as c(x)=v(x)−e(x). In order to determine the set of error positions I, two polynomials may be introduces per the formulae (2) and (3), as shown in FIG. 1. The polynomial Λ(x) may be referred to as an error locator polynomial. The polynomial Ψ(x) may be referred to as an erasure locator polynomial.
Note 1: a set {0, 1, . . . , n−1} is generally denoted as [0,n). Furthermore, if iε[0,n), then (i) Λ(α−i)=0 if and only if iεI and (ii) Ψ(α−j)=0 if any only if jεJ.
A discrete Fourier transform Fn:Fqn→Fqn generally maps each vector u=(u0, . . . , un−1) into a vector U=(U0, . . . , Un−1) per formula (4), shown in FIG. 1. The map Fn:Fqn→Fqn is commonly a bijection (a transform which is one-to-one and a surjection) and the inverse discrete Fourier transform u=Fn−1(U) may be obtained by formula (5), shown in FIG. 1. The fact that U=Fn(u) and u=Fn−1(U) is generally denoted by uU. The maps Fn and Fn−1 are commonly linear maps. For example, from uU and wW, then au+bwaU+bW generally follows for any a,bεFq.
Note 2: for two given vectors u,wεFnq, (i) the vector u·wεFnq, where (u·w)i=uiwi, i=0, . . . , n−1, (ii) Fn(u·w)=U*W, where U=Fn(u), W=Fn(w) and (iii) U*W may be a convolution, see formula (6) in FIG. 1. Hence, from uU and wW, then u·wU*W generally follows.
Let cC, eE, λΛ, and ψΨ. From note 1, (i) λi=Λ(α−i)=0 generally follows if and only if iεI and (ii) ψj=Ψ(α−j)=0 if and only if jεJ. Furthermore, if ei≠0, then iεIÅJ. Therefore, e·ψ·λ=0, and also by note 2, E*Ψ*Λ=0, where 0=(0, . . . , 0)εFqn. The whole vector E may be unknown, but the 2t components may be obtained. By calculating syndromes Si=v(αi)=Vi=Ci+Ei for i=1, . . . , 2t, and using the fact that Ci=c(αi)=0 for i=1, . . . , 2t, then E1=S1, . . . , E2t=S2t. Thus, 2t subsequent elements of vector E may be known. By the fact that degΨ(x)=ρ≦2t, the 2t−ρ subsequent elements of a vector E*Ψ may be calculated per formula (7), shown in FIG. 1.
Elements S′1=(E*Ψ)ρ+1, . . . , S′2t−ρ=(E*Ψ)2t are commonly known as Forney modified syndromes. By the fact that degΛ(x)≦(2t−ρ)/2 and the relationship (E*Ψ)*Λ=0, the condition in formula (8) may be true, see FIG. 1. Hence, a custom Berlekamp-Massey technique may be used to find the error locator polynomial Λ(x) using Forney modified syndromes S1′, . . . , S′2t−ρ instead of ordinary syndromes S1, . . . , S2t.
Once the error locator polynomial Λ(x) and the erasure locator polynomial Ψ(x) are known, a set of error and erasure positions may be found using exhaustive search called a Chien search, I={iε[0,n)|Λ(α−i)=0} and J={iε[0,n)|Λ(α−i)=0}. To reconstruct the errata polynomial e(x), the error and erasure values ei1, . . . , eiν and ej1, . . . , ejρ may be sought.
Referring to FIG. 2, a functional flow diagram of a system 100 is shown in accordance with a preferred embodiment of the present invention. The system (or apparatus) 100 generally implements an error-and-erasure decoder. In some embodiments, the system 100 may implement a Reed-Solomon decoder. The system 100 generally comprises a circuit (or step) 102, a circuit (or step) 104, a circuit (or step) 106, a circuit (or step) 108 and a circuit (or step) 110. A signal (e.g., IS_ERASURE) may be generated by the circuit 102 and transferred to the circuit 104. A signal (e.g., CHANNEL) may be received by the circuit 102. A signal (e.g., INPUT) may be generated by the circuit 102 and presented to the circuit 104, the circuit 106 and the circuit 108. The circuit 110 may generate and present an output signal (e.g., OUTPUT). A signal (e.g., ELP) may be generated by the circuit 104 and presented to the circuit 110. A signal (e.g., SYN) may be generated by the circuit 106 and presented to the circuit 110. The circuit 108 may generate a signal (e.g., DELAY) presented from the circuit 108 to the circuit 110.
The signal IS_ERASURE generally carries an erasure location vector (e.g., θ). The vector θ=(θ0, θ1, . . . , θn−1)ε{0,1}n generally comprises a sequence of binary elements containing information about erasures, where θj=1 indicates an erasure at position jε[0,n). A set all erasure positions {jε[0,n)|θj=1} may be denoted by [θ]. The signal INPUT may convey a received codeword (or vector) v=(v0, v1, . . . , vn−1). The received codeword v(x) may have been encoded per the Reed-Solomon coding and transmitted through a noisy signal CHANNEL to the circuit 102. The signal ELP may carry an erasure locator polynomial (e.g., Ψ(x)). The signal SYN may carry syndromes (e.g., S(x)). The signal DELAY may carry a delayed copy (e.g., v2) of the codewords v(x). The signal OUTPUT may convey the reconstructed codeword (or vector) c(x).
The circuit 102 generally implements a receiver. The circuit 102 may be operational to covert a sequence of symbols receive through the signal CHANNEL into the signal IS_ERASURE and the signal INPUT. Generation of the signals IS_ERASURE and INPUT may be performed by common techniques.
The circuit 104 may implement an erasure polynomial calculator. The circuit 104 is generally operational to calculate the polynomial Ψ(x) based on the vector θ and the codeword v(x). A design of the circuit 104 may utilize constant Galois multipliers to aid in minimizing the circuit size (e.g., number of transistors) and maximize the circuit speed (e.g., reduce propagation delay).
The circuit 106 may implement a syndrome calculator. The circuit 106 is generally operational to calculate the syndromes S(x) from the codeword v(x). The syndrome calculations may be performed by common techniques.
The circuit 108 may implement a buffer. The circuit 108 may hold the codeword v(x) until the circuit 110 is ready to generate the reconstructed codeword c(x). A delay through the circuit 108 may be based on the delays through the circuits 104 and 106 plus a partial delay through the circuit 110.
The circuit 110 may implement a reconstruction circuit. The circuit 110 may be operational to generate the reconstructed codeword C using the polynomial Ψ(x) the syndromes S(x) and the delayed codewords v2(x).
Referring to FIG. 3, a detailed functional flow diagram of a first example embodiment 110a of the circuit 110 is shown. The circuit 110a generally comprises a circuit (or step) 112, a circuit (or step) 114 and a circuit (or step) 116. The polynomial Ψ(x) and the syndromes S(x) may be received by the circuit 112. A signal (e.g., ERR) may be generated by the circuit 112 and presented to the circuit 114. The circuit 112 may also generate a signal (e.g., EEP) presented to the circuit 114. A signal (e.g., ERRATA) may be generated by the circuit 114 and presented to the circuit 116. The circuit 116 may receive the signal ERRATA and the signal DELAY. The signal OUTPUT may be generated by the circuit 116.
The circuit 112 generally implements a calculation circuit. The circuit 112 may be operational to (i) calculate modified syndromes, (ii) generate the signal ERR using the Berlekamp-Massey technique and (iii) generate the signal EEP.
The circuit 114 generally implements a calculation circuit. The circuit 114 may be operational to (i) determine the error positions by the Chien search and (ii) determine the error and erasure values using the Forney technique. The results may be presented in the signal ERRATA.
The circuit 116 may implement a summation circuit. The circuit 116 is generally operational to create the codeword c(x) in the signal OUTPUT by summing the signal ERRATA and the signal DELAY.
In operation, the system 100 may calculate the syndromes S(x) in the circuit 106 in accordance with formula (9), shown in FIG. 1. The circuit 104 may calculate the erasure locator polynomial Ψ(x) in accordance with formula (10), shown in FIG. 1. The circuit 108 generally calculates the modified Forney syndromes (e.g., S′(x)) per the formula (11), see FIG. 1.
The circuit 112 may determine the error locator polynomial Λ(x) using the Berlekamp-Massey technique on the modified syndromes S1′, . . . , S′2t−ρ. The errata evaluator polynomial Ω(x) may be determined by the circuit 112 according to formula (12), where S(x) is a syndrome polynomial in accordance with formula (13), see FIG. 1. The circuit 114 may find the error positions I={iε[0,n)|Λ(α−i)=0} by a Chien search. The error and erasure values may be determined by the circuit 114 using the Forney formulae (14) and (15), as shown in FIG. 1. Finally, the circuit 116 may calculate the reconstructed codeword c(x)=v(x)+e(x) and present the codeword c(x) in the signal OUTPUT.
Referring to FIG. 4, a detailed functional flow diagram of a second example embodiment 110b of the circuit 110 is shown. The circuit 110b generally comprises a circuit (or step) 122, the circuit 114 and the circuit 116. The polynomial Ψ(x) and the syndromes S(x) may be received by the circuit 122. The signal ERR may be generated by the circuit 122 and presented to the circuit 114. The circuit 122 may also generate the signal EEP that is presented to the circuit 114. The signal ERRATA may be generated by the circuit 114 and presented to the circuit 116. The circuit 116 may receive the signal ERRATA and the signal DELAY. The signal OUTPUT may be generated by the circuit 116.
The circuit 122 may implement a Euclidian circuit. The circuit 122 is generally operational to calculate the signal ERRATA based on the signal ERR and the signal EEP using the extended Euclidian technique. The remaining circuits 114 and 116 may operate as described above.
Referring again to FIG. 2, the system generally receives (i) the input codeword v=(v0, v1, . . . , vn−1) and (ii) the erasure location vector θ=(θ0, θ1, . . . , θn−1)ε{0,1}n and generates the reconstructed codeword c=(c0, c1, . . . , cn−1).
A custom solution for calculating the erasure polynomial Ψ(x) for the vector θ may be in accordance with formula (16), shown in FIG. 5. A hardware scheme for calculating Ψ(x) “on the fly” (e.g., updating the polynomial Ψ(x) as each new element of the vector θ is received) may be implemented in the circuit 104. The circuit 114 may (i) update the polynomial Ψ(x) as new erasures occur and (ii) be implemented using only constant Galois field multipliers. Implementations of constant Galois field multipliers are generally more space efficient on the chips than implementation of non-constant Galois field multipliers. In particular, constant Galois field multipliers may have approximately ten times fewer gates than non-constant Galois field multipliers. Hence, constant multiplier applications may have less complexity, occupy less area and consume less power than a design that uses non-constant multipliers. For implementations of multipliers for Galois field having a large number of elements (e.g., 212 elements), the advantages of using constant multipliers may be considerable.
Referring to FIG. 6, a block diagram of a first example embodiment 104a of the circuit 104 using constant Galois field multipliers is shown. The circuit 104a generally comprises multiple registers (or modules) 140a-140n, several multipliers (or modules) 142a-142n, multiple gating circuits (or modules) 144a-144n, multiple summation circuits (or modules) 146a-146n and multiple gating circuits (or modules) 148a-148n. The signal IS_ERASURE may be received by each of the circuits 148a-148n. A signal (e.g., WORK) may be received by each of the circuits 144a-144n. Each of the registers 140a-140n may generate a portion of the signal ELP (e.g., Ψ0, Ψ1, . . . , Ψ2t). The first circuit 146a may (i) receive a first input from the circuit 144a and (ii) a constant value (e.g., 0) as a second input.
The circuit 104a generally contains 2t+1 registers 140a-140n, labeled R0, R1, . . . , R2t and may work as follows. Consider a moment kε{0, . . . , n−1} when the registers 140a-140n already buffer bits θn−1, θn−2, . . . , θn−k for kε{1, . . . , n−1} and the vector θ(k)=(θn−k, θn−k+1, . . . , θn−1, 0, . . . , 0)ε{0,1}n, where θ(0)=(0, . . . , 0)ε{0,1}n. The scheme generally works so that at the moment k, the register Ri may hold a current value of Ψi(k), for i=0, 1, . . . , 2t, where Ψ(x) may be defined by formula (17), shown in FIG. 5. Therefore, the registers 140a-140n may completely define the polynomial Ψ(k)(x) at the moment k. At a final moment (e.g., k=n) when all of the elements of the vectors θ and v have been entered into the circuit 104a, the registers 140a-140n generally contain the coefficients Ψ0, Ψ1, . . . , Ψ2t of erasure locator polynomial Ψ(x) because θ(n)=θ and therefore Ψ(n)(x)=Ψ(x). Furthermore, R0=Ψ0(k)=1 for any k=0, 1, . . . , n−1. Hence, R0 may be a constant (e.g., 1εFq).
At an initial moment (e.g., k=0), the signal IS_ERASURE may be set to a binary zero value (0) and the signal WORK may be deasserted to the binary zero value. Therefore, the initial values in the registers 140a-140n may be R0:=1, R1:=0, . . . , R2t:=0. The initial values generally correspond to the polynomial Ψ(0)(x)=1. After the initial moment, the signal WORK may be asserted to a binary one value (1) and the signal IS_ERASURE may be set to θn−k at each moment n≧k>0. Thus, at the moment k, the registers 140a-140n may contain Ψ0(k), Ψ1(k), . . . , Ψ2t(k).
Each of the registers 140a-140n may present the buffered current values to the corresponding multipliers 142a-142n. Each of the multipliers 142a-142n may perform a unique (e.g., α0, α1, . . . , α2t) constant Galois field multiplication to generate first intermediate values. The first intermediate values may be received by the corresponding modules 144a-144n and 148a-148n. Once the signal WORK has been asserted, the modules 144a-144n may pass the first intermediate values unaltered to the circuit 146a-146n, respectively. The circuits 148a-148n may selectively gate the first intermediate values with the signal IS_ERASURE to generate second intermediate values. The second intermediate values may provide a second input to the circuits 146b-146n. 
Each of the circuits 142a-142 generally has a single input X=(X1, . . . , Xd) and a single output Y=(Y1, . . . , Yd). Each αi for i=0, . . . , 2t, may be a constant Galois field multiplier, where α is known Galois field element. The output may be related to the input by Y=α*X in the Galois field.
Each of the circuits 144a-144n and 148a generally has two inputs. A first input may be a 1-bit input (e.g., W) connected to the signal IS_ERASURE or the signal WORK. A second input may be a d-bit input connected to an output signal (e.g., X=(X1, . . . , Xd)), where d is generally the width of the Galois field (e.g., the Galois field may have 2d elements). Each of the circuits 144a-144n and 148a-148n may generate a single d-bit output (e.g., Z=(Z1, . . . , Zd)). A function of the circuits 144a-144n and 148a-148n may be expressed as Z1=W AND X1, Z2=W AND X2, . . . , Zd=W AND Xd.
Each of the circuits 146a-146n generally has two inputs. Each Galois field element aεFq, where q=2d, may be represented as binary vector (e.g., a1, a2, . . . , ad). Likewise, another Galois field element bεFq may be represented as (b1, b2, . . . , bd). The circuits 146a-146 generally calculates the sum a+b in the Galois field arithmetic as another Galois field element represented as (a1 XOR b1, . . . , ad XOR bd).
Consider the following two cases to prove that at the moment k+1 the registers 140a-140n may contain Ψ0(k+1), Ψ1(k+1), . . . , Ψ2t(k+1). In a first case, let no erasure exist at the position k+1, (e.g., θn+k−1=0). Therefore, θ(k+1)=(0, θn−k, θn−k+1, . . . , θn−1, 0, . . . , 0). As such, the vector θ(k+1) is generally a “right shift” of the vector θ(k) and the polynomial Ψ(k+1)(x) may be defined by formula (18), shown in FIG. 5. In the first case, Ri:=Riαi for i=1, . . . , 2t.
In a second case, let an erasure exist at the position k+1, (e.g., θn+k−1=1). Therefore, θ(k+1)=(1, θn−k, θn−k+1, . . . , θn−1, 0, . . . , 0) and the polynomial Ψ(k+1)(x) may be defined by formula (19), shown in FIG. 5. In the second case, Ri:=Ri−1αi−1+Riαi for i=1, . . . , 2t.
Referring to FIG. 7, a block diagram of a second example embodiment 104b of the circuit 104 is shown. The circuit 104b may be similar to the circuit 104a with a few modifications. Consider that the register 140a stores a constant value (e.g., 1) and the circuit 142a is a multiplication by one (e.g., α0=1). Therefore, the circuits 142a, 144a and 146a may be eliminated in the circuit 104b and the current value of the register 140a may be presented directly to the input of the circuit 148a. Furthermore, a last of the circuits 148n may be eliminated as the corresponding signal generally does not feed into a next summation module. With the eliminations, the circuit 104b generally operates the same as the circuit 104a (and the circuit 104).
The functions performed by the diagrams of FIGS. 1-7 may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s). Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s).
The present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s).
The present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention. The storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.

## Claims

1. A method to generate an erasure locator polynomial in an error-and-erasure decoder, comprising the steps of:
(A) storing a plurality of current values in a plurality of registers;
(B) generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants;
(C) generating a plurality of second values by gating at least all but one of said first values with a current one of a plurality of erasure values of an erasure location vector;
(D) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values;
(E) loading said next values into said registers in place of said current values; and
(F) generating an output signal carrying said current values such that said current values form a plurality of coefficients of said erasure locator polynomial.

2. The method according to claim 1, wherein said constants comprise a plurality of constant Galois field multipliers.

3. The method according to claim 1, further comprising the step of:
initializing said current values with a binary one value in a first of said registers and a binary zero value in each of a remainder of said registers.

4. The method according to claim 1, wherein an initial value of said erasure values of said erasure location vector comprises a binary zero value at an initial moment such that all of said second values are generated as said binary zero value at said initial moment.

5. The method according to claim 1, further comprising the step of:
gating said first values under control of a work signal prior to combining with said second values, wherein said work signal is (i) deasserted at an initial one of a plurality of moments such that each of said first values as gated comprises a binary zero value and (ii) asserted at a remainder of said moments such that said first values are unaltered by said gating.

6. The method according to claim 1, wherein combining each one of said second values with said corresponding one of said first values comprises summing in Galois field arithmetic.

7. The method according to claim 1, wherein
said error-and-erasure decoder comprises a Reed-Solomon decoder.

8. The method according to claim 1, wherein (i) said current values are stored at a current one of a plurality of moments, (ii) said next values are loaded at a next one of said moments and (iii) said output signal is generated at a last of said moments.

9. A circuit comprising:
a plurality of registers (i) storing a plurality of current values and (ii) generating an output signal carrying said current values such that said current values form a plurality of coefficients of an erasure locator polynomial in an error-and-erasure decoder;
a plurality of multiplier modules generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants;
a plurality of first modules generating a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure elements of an erasure location vector; and
a plurality of summing modules (i) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values and (ii) loading said next values into said registers in place of said current values.

10. The circuit according to claim 9, wherein said constants comprise a plurality of constant Galois field multipliers.

11. The circuit according to claim 9, wherein said current values are initialized with a binary one value in a first of said registers and a binary zero value in each of a remainder of said registers.

12. The circuit according to claim 9, wherein an initial value of said erasure values of said erasure location vector comprises a binary zero value at an initial moment such that all of said second values are generated as said binary zero value at said initial moment.

13. The circuit according to claim 9, further comprising a plurality of second modules (i) disposed between said multiplier modules and said summing modules and (ii) gating said first values under control of a work signal prior to combining with said second values, wherein said work signal is (a) deasserted at an initial one of a plurality of moments such that each of said first values as gated comprises a binary zero value and (b) asserted at a remainder of said moments such that said first values are unaltered by said second modules.

14. The circuit according to claim 9, wherein combining each one of said second values with said corresponding one of said first values comprises summing in Galois field arithmetic.

15. The circuit according to claim 9, wherein said error-and-erasure decoder comprises a Reed-Solomon decoder.

16. A system comprising:
a first circuit configured to generate an erasure locator polynomial in response to all of (a) an erasure location vector and (b) a plurality of constants, wherein each of said constants is a multiplication factor in a respective one of a plurality of multiplier modules;
a second circuit configured to generate a plurality of syndromes in response to an input codeword; and
a third circuit configured to generate an output signal carrying a reconstructed codeword in response to all of (i) said erasure locator polynomial, (ii) said syndromes and (iii) said input codeword, wherein (a) said first circuit comprises a plurality of registers configured to (i) store a plurality of current values and (ii) generate an intermediate signal carrying said current values such that said current values form a plurality of coefficients of said erasure locator polynomial, (b) said multiplier modules are configured to generate a plurality of first values by multiplying said current values by said respective constants and (c) said first circuit further comprises a plurality of first modules configured to generate a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure values of said erasure location vector.

17. The system according to claim 16, wherein said first circuit further comprises a plurality of summing modules configured to (i) generate a plurality of next values by combining each one of said second values with a corresponding one of said first values and (ii) load said next values into said registers in place of said current values.

18. The system according to claim 17, wherein said first circuit further comprises a plurality of second modules (i) disposed between said multiplier modules and said summing modules and (ii) configured to gate said first values under control of a work signal prior to combining with said second values, wherein said work signal is (a) deasserted at an initial one of a plurality of moments such that each of said first values as gated comprises a binary zero value and (b) asserted at a remainder of said moments such that said first values are unaltered by said second modules.