# Patent

## Title
Shallow junction photodiode for detecting short wavelength light

## Abstract

The present invention is a photodiode or photodiode array having improved ruggedness for a shallow junction photodiode which is typically used in the detection of short wavelengths of light. In one embodiment, the photodiode has a relatively deep, lightly-doped P zone underneath a P+ layer. By moving the shallow junction to a deeper junction in a range of 2-5 μm below the photodiode surface, the improved device has improved ruggedness, is less prone to degradation, and has an improved linear current.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
The present specification is a continuation of U.S. patent application Ser. No. 13/749,616, of the same title, and filed on Jan. 24, 2013, which is herein incorporated by reference in its entirety.


FIELD
The present specification relates generally to the field of radiation detectors, and in particular, to a shallow junction photodiode having improved device performance characteristics. Specifically, the present specification discloses photodiodes having a doping profile P+P N N+ shallow junction for use in short wavelength light applications such as in CT scanning, X-ray scanning, and other light detection operations.
BACKGROUND
Active solid-state semiconductor devices, and in particular, silicon photodiodes, are among the most popular photodetectors having a sufficiently high performance over a large wavelength range and a sufficient ease of use. Silicon photodiodes are sensitive to light in the wide spectral range, extending from deep ultraviolet through visible to near infrared, which is approximately 200 nm to 1100 nm. Silicon photodiodes, by using their ability to detect the presence or absence of minute light intensities, facilitate the precise measurement of these minute light intensities upon appropriate calibration. For example, appropriately calibrated silicon photodiodes detect and measure light intensities varying over a wide range, from very minute light intensities of below 10−13 watts/cm2 to high intensities above 10−3 watts/cm2.
Silicon photodiodes can be employed in an assortment of applications including, but not limited to, spectroscopy, distance and speed measurement, laser ranging, laser guided missiles, laser alignment and control systems, optical free air communication, optical radar, radiation detection, optical position encoding, film processing, flame monitoring, scintillator read out, environmental applications such as spectral monitoring of earth ozone layer and pollution monitoring, low light-level imaging, such as night photography, nuclear medical imaging, photon medical imaging, and multi-slice computer tomography (CT) imaging, security screening and threat detection, thin photochip applications, and a wide range of computing applications.
Typically, photodiode arrays employ a scintillator material for absorbing high energy (ionizing) electromagnetic or charged particle radiation, which, in response, fluoresces photons at a characteristic wavelength. Scintillators are defined by their light output (number of emitted photons per unit absorbed energy) short fluorescence decay times, and optical transparency at wavelengths of their own specific emission energy. The lower the decay time of a scintillator, that is, the shorter the duration of its flashes of fluorescence are, the less so-called “dead time” the detector will have and the more ionizing events per unit of time it will be able to detect. Scintillators are used to detect electromagnetic waves or particles in many security and detection systems, including CT, X-ray, and gamma ray. There, a scintillator converts the energy to light of a wavelength which can be detected by photomultiplier tubes (PMTs) or P− N junction photodiodes.
Photodiodes are typically characterized by certain parameters, such as, among others, electrical characteristics, optical characteristics, current characteristics, voltage characteristics, and noise. Electrical characteristics predominantly comprise shunt resistance, series resistance, junction capacitance, rise or fall time and/or frequency response. Optical characteristics comprise responsivity, quantum efficiency, non-uniformity, and/or non-linearity. Photodiode noise may comprise, among others, thermal noise, quantum, photon or shot noise, and/or flicker noise.
Conventional shallow junction photodiodes are prone to junction degradation and yield loss during assembly due to a very shallow P+N junction, which is typically 0.3 μm. Therefore, what is needed is a photodiode that has improved ruggedness and is less prone to degradation or failure during assembly of scintillator crystals, thereby improving yield and reducing cost. What is also needed is a photodiode having an improved linear current.
SUMMARY
The present specification is directed toward a photodiode having a top surface defined by at least one SiO2 layer comprising: a low resistivity substrate; a high resistivity silicon layer positioned atop the low resistivity substrate and below the top surface of the photodiode; a first P doped zone within the high resistivity silicon layer, wherein the first P doped zone has a thickness of 2-5 μm; a first P+ doped zone positioned between the top of the first P doped zone and the top of the photodiode.
In one embodiment, the low resistivity substrate has a thickness in a range of 150 μm to 350 μm. In one embodiment, the low resistivity substrate is doped n+.
In one embodiment, the high resistivity silicon layer has a thickness in a range of 10 μm to 100 μm. In one embodiment, the high resistivity silicon layer is doped n.
In one embodiment, the first P+ doped zone and a portion of the first P doped zone is surrounded by P+ doped ring.
In one embodiment, the photodiode further comprises a first N+ region extending throughout the thickness of the high resistivity silicon layer. In one embodiment, the photodiode further comprises a second N+ region extending throughout the thickness of the high resistivity silicon layer, wherein the second N+ region is separated from the first N+ region by a third region and wherein the first P doped zone and first P+ doped zone is located in the third region. In one embodiment, the photodiode further comprises a third N+ region extending throughout the thickness of the high resistivity silicon layer, wherein the third N+ region is separated from the second N+ region by a fourth region. In one embodiment, the photodiode further comprises a second P doped zone within said fourth region in the high resistivity silicon layer, wherein the second P doped zone has a thickness of 2-5 μm. In one embodiment, the photodiode further comprises a second P+ doped zone positioned between the top of the second P doped zone and the top of the photodiode in the fourth region.
In one embodiment, all of the first P+ doped zone and a portion of the first P doped zone is surrounded by P+ doped ring. In one embodiment, all of the second P+ doped zone and a portion of the second P doped zone is surrounded by P+ doped ring.
In one embodiment, the photodiode further comprises an anode and a cathode on the top surface of the photodiode.
In one embodiment, the photodiode further comprises an anode on the top surface of the photodiode and a cathode on a backside of the photodiode.
In one embodiment, the photodiode further comprises an anode on the top surface of the photodiode, a cathode on the top surface of the photodiode, and a cathode on a backside of the photodiode.
The present specification is also directed toward a method of fabricating a photodiode on a substrate wafer having a high resistivity silicon layer front side and a low resistivity silicon substrate back side, said method comprising the steps of: providing an oxide layer on the front side of the wafer; implementing an etching process on the front side to define a first plurality of regions on the front side; filling the first plurality of regions with n+ dopant; depositing an oxide layer on the front side of the wafer; implementing a second etching process on the front side to define a second plurality of regions on the front side; filling the second plurality of regions with a p dopant; depositing an oxide layer on the front side of the wafer; performing a deep drive-in process to redistribute p dopant atoms and deposit them deeper into the wafer creating deep p active areas; implementing a third etching process on the front side to define a third plurality of regions on the front side, wherein the third plurality of regions is on a right side and a left side of each deep p active area; forming deep p+ ring zones in each of the third plurality of regions; depositing an oxide layer on the front side of the wafer; forming an anti-reflective layer on the front side and the back side of the wafer; forming shallow p+ active area regions on the front side of the wafer, on top of the deep p active area regions; forming at least one contact window on the wafer; and performing a metal deposition process to deposit metal on the device wafer, wherein said metal deposition process creates connections and wherein said metal deposition process forms a reflective metal shield.
In one embodiment, the metal deposition process is performed on the front side of the wafer to form both a cathode and an anode and on the back side to form an anode.
In another embodiment, the metal deposition process is performed on the front side of the wafer to form both an anode and a cathode on the front side, forming contacts only on the front side of the device.
In another embodiment, the metal deposition process is performed on the front side of the wafer to form an anode and on the back side of the wafer to form a cathode, forming contacts only on the back side of the device.
In one embodiment, the metal used for depositing metal on the front side for both the anode and cathode is aluminum and the metal used for forming the cathode on the backside is a Cr/Au alloy, forming contacts on both the front side and the back side of the device.
The present specification is also directed toward a photodiode having a top surface defined by at least one SiO2 layer comprising: a high resistivity bulk wafer positioned below the top surface of the photodiode; a first P doped zone within the high resistivity bulk wafer, wherein the first P doped zone has a thickness of 2-5 μm; a first P+ doped zone positioned between the top of the first P doped zone and the top of the photodiode.
In one embodiment, the high resistivity bulk wafer has a thickness in a range of 250 μm to 400 μm.
In one embodiment, the first P+ doped zone and a portion of the first P doped zone is surrounded by P+ doped ring.
In one embodiment, the photodiode further comprises a first N+ region extending throughout the thickness of the high resistivity bulk wafer. In one embodiment, the photodiode further comprises a second N+ region extending throughout the thickness of the high resistivity bulk wafer, wherein the second N+ region is separated from the first N+ region by a third region and wherein the first P doped zone and first P+ doped zone is located in the third region. In one embodiment, the photodiode further comprises a third N+ region extending throughout the thickness of the high resistivity bulk wafer, wherein the third N+ region is separated from the second N+ region by a fourth region. In one embodiment, the photodiode further comprises a second P doped zone within said fourth region in the high resistivity bulk wafer, wherein the second P doped zone has a thickness of 2-5 μm. In one embodiment, the photodiode further comprises a second P+ doped zone positioned between the top of the second P doped zone and the top of the photodiode in the fourth region.
In one embodiment, all of the first P+ doped zone and a portion of the first P doped zone is surrounded by P+ doped ring. In one embodiment, all of the second P+ doped zone and a portion of the second P doped zone is surrounded by P+ doped ring.
In one embodiment, the photodiode further comprises an anode and a cathode on the top surface of the photodiode.
In another embodiment, the photodiode further comprises an anode on the top surface of the photodiode and a cathode on a backside of the photodiode.
In another embodiment, the photodiode further comprises an anode on the top surface of the photodiode, a cathode on the top surface of the photodiode, and a cathode on a backside of the photodiode.



BRIEF DESCRIPTION OF THE DRAWINGS
These and other features and advantages of the present specification will be appreciated, as they become better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:
FIG. 1 illustrates a photodiode device, in accordance with an embodiment of the present specification;
FIG. 2 illustrates a cross-sectional view of a substrate wafer used as a starting material in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 3 illustrates a cross-sectional view of the wafer shown in FIG. 2, after a mask oxidation process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 4 illustrates a cross-sectional view of the wafer shown in FIG. 3, after a n+ photolithography process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 5 illustrates a cross-sectional view of the wafer shown in FIG. 4, after a n+ diffusion process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 6 illustrates a cross-sectional view of the wafer shown in FIG. 5, after an etching and lithography process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 7 illustrates a cross-sectional view of the wafer shown in FIG. 6, after a boron implant and annealing process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 8 illustrates a cross-sectional view of the wafer shown in FIG. 7, after a p diffusion process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 9 illustrates a cross-sectional view of the wafer shown in FIG. 8, after an etching and deep ring p+ masking process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 10 illustrates a cross-sectional view of the wafer shown in FIG. 9, after an etching process step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 11 illustrates a cross-sectional view of the wafer shown in FIG. 10, after a process for growing oxide and nitride layers on a front and backside step, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 12 illustrates a cross-sectional view of the wafer shown in FIG. 11, after a boron implant and annealing process step for forming shallow p+ active areas, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 13 is a cross-sectional view of the wafer shown in FIG. 12, illustrating a manufacturing step for a photodiode having both top and bottom contact devices whereby the wafer is subjected to an etching process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 14 is a cross-sectional view of the wafer shown in FIG. 13, illustrating a manufacturing step for a photodiode having both top and bottom contact devices whereby the wafer is subjected to a metal masking process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 15 is a cross-sectional view of the wafer shown in FIG. 14, illustrating manufacturing step for a photodiode having both top and bottom contact devices whereby the wafer is subjected to an additional metal masking process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 16 is a cross-sectional view of the wafer shown in FIG. 12, illustrating a manufacturing step for a photodiode having top contacts only whereby the wafer is subjected to an etching process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 17 is a cross-sectional view of the wafer shown in FIG. 16, illustrating a manufacturing step for a photodiode having top contacts only whereby the wafer is subjected to a metal masking process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 18 is a cross-sectional view of the wafer shown in FIG. 17, illustrating a manufacturing step for a photodiode having top contacts only whereby the wafer is subjected to an additional metal masking process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 19 is a cross-sectional view of the wafer shown in FIG. 12, illustrating a manufacturing step for a photodiode having bottom contacts only whereby the wafer is subjected to an etching process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 20 is a cross-sectional view of the wafer shown in FIG. 19, illustrating a manufacturing step for a photodiode having bottom contacts only whereby the wafer is subjected to a metal masking process, in one embodiment of the manufacture of the photodiode of the present specification; and
FIG. 21 is a cross-sectional view of the wafer shown in FIG. 20, illustrating a manufacturing step for a photodiode having bottom contacts only whereby the wafer is subjected to an additional metal masking process, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 22 illustrates a photodiode device, without a deep p ring, in accordance with another embodiment of the present specification;
FIG. 23 illustrates a cross-sectional view of a substrate wafer used as a starting material for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 24 illustrates a cross-sectional view of the wafer shown in FIG. 23, after a mask oxidation process step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 25 illustrates a cross-sectional view of the wafer shown in FIG. 24, after a n+ photolithography process step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 26 illustrates a cross-sectional view of the wafer shown in FIG. 25, after a n+ diffusion process step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 27 illustrates a cross-sectional view of the wafer shown in FIG. 26, after an etching and lithography process step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 28 illustrates a cross-sectional view of the wafer shown in FIG. 27, after a boron implant and annealing process step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 29 illustrates a cross-sectional view of the wafer shown in FIG. 28, after a p diffusion process step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 30 illustrates a cross-sectional view of the wafer shown in FIG. 29, after a process for growing oxide and nitride layers on a front and backside step, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 31 illustrates a cross-sectional view of the wafer shown in FIG. 30, after a boron implant and annealing process step for forming shallow p+ active areas, in one embodiment of the manufacture of the photodiode of the present specification;
FIG. 32 is a cross-sectional view of the wafer shown in FIG. 31, illustrating a manufacturing step for a photodiode having bottom contacts only whereby the wafer is subjected to an etching process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 33 is a cross-sectional view of the wafer shown in FIG. 32, illustrating a manufacturing step for a photodiode having bottom contacts only whereby the wafer is subjected to a metal masking process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification; and
FIG. 34 is a cross-sectional view of the wafer shown in FIG. 33, illustrating a manufacturing step for a photodiode having bottom contacts only whereby the wafer is subjected to an additional metal masking process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 35 is a cross-sectional view of the wafer shown in FIG. 31, illustrating a manufacturing step for a photodiode having top contacts only whereby the wafer is subjected to an etching process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 36 is a cross-sectional view of the wafer shown in FIG. 35, illustrating a manufacturing step for a photodiode having top contacts only whereby the wafer is subjected to a metal masking process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 37 is a cross-sectional view of the wafer shown in FIG. 36, illustrating a manufacturing step for a photodiode having top contacts only whereby the wafer is subjected to an additional metal masking process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 38 is a cross-sectional view of the wafer shown in FIG. 31, illustrating a manufacturing step for a photodiode having both top and bottom contact devices whereby the wafer is subjected to an etching process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 39 is a cross-sectional view of the wafer shown in FIG. 38, illustrating a manufacturing step for a photodiode having both top and bottom contact devices whereby the wafer is subjected to a metal masking process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 40 is a cross-sectional view of the wafer shown in FIG. 39, illustrating manufacturing step for a photodiode having both top and bottom contact devices whereby the wafer is subjected to an additional metal masking process, for the manufacture of the photodiode without a deep p ring in accordance with one embodiment the present specification;
FIG. 41 illustrates a photodiode fabricated on a bulk wafer material, in accordance with an embodiment of the present specification; and
FIG. 42 illustrates a photodiode fabricated on a bulk wafer material, in accordance with an embodiment of the present specification.



DETAILED DESCRIPTION
The present specification describes a photodiode having improved device characteristics, such as low capacitance, low dark current, improved signal-to-noise ratio, and lower fabrication and manufacturing costs.
In order to improve the ruggedness of the device, especially when scintillator crystals are mounted on the photodiodes, a new structure is provided whereby a lowly doped, deep P-zone is introduced underneath the shallow P+ layer. Thus, the PN junction is moved deep down underneath the silicon-oxide interface yielding photodiodes with increased ruggedness and stability.
While the present specification is described in detail with respect to an individual photodiode element, it should be understood to those of ordinary skill in the art that a plurality of such photodiode elements may be aggregated on a substrate to form a multi-element photodiode array. Further, while the photodiode and photodiode array of present specification is described with respect to p+ diffused active areas on an n-type silicon wafer, it should be noted and understood by those of ordinary skill in the art that the present specification can be designed and manufactured with reverse polarity, and more specifically, n+ diffused active areas on p-type silicon substrate wafers. Thus, the present specification is not limited to the polarity presented herein.
The present specification is directed towards multiple embodiments. The following disclosure is provided in order to enable a person having ordinary skill in the art to practice the invention. Language used in this specification should not be interpreted as a general disavowal of any one specific embodiment or used to limit the claims beyond the meaning of the terms used therein. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present specification is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
In one embodiment, the present specification is directed towards a shallow junction photodiode characterized by a doping profile P+ P N N+ used in the detection of short wavelength light such as that employed in CT scanning, X-ray scanning, etc.
A conventional structure of a shallow junction photodiode having a P+ N N+ profile comprises a shallow p+ region. In order to improve the ruggedness of a photodiode, especially when scintillator crystals are mounted on the photodiode, a new structure is provided whereby a lowly doped and deep P-zone is introduced underneath the shallow P+ layer.
The present specification provides a photodiode having improved ruggedness, stability and performance characteristics. The photodiode of the present specification is advantageous in that it provides improved ruggedness for a shallow junction photodiode which is typically used in the detection of short wavelengths of light. By the introduction of a relatively deep, lightly doped P zone underneath the P+ layer of a conventional shallow junction photodiode, the shallow junction (typically 0.3 μm deep) is moved to a deeper junction (on the order of 2-5 μm deep). This causes the improved photodiode to have a higher linear current since the integrated total boron dose of the P+ P layer is higher than the only P+ layer of a conventional shallow junction photodiode. Further, the improved, rugged photodiode of the present specification results in improved yield and reduced cost, since the photodiode is less prone to degradation and/or failure on shunt resistance during assembly of scintillator crystals.
In one embodiment, the improved P+ P N N+ photodiode device of the present specification is front-side illuminated. In one embodiment, the photodiode has bottom contacts only, wherein the anode is on the front side and the cathode is on the back side. In another embodiment, the photodiode has top contacts only, wherein the anode and cathode are on the top side. In yet another embodiment, the photodiode has both top and bottom contacts, wherein the anode is on the front side and the cathode is on both the front side and backside. In the cases where the devices have bottom contacts, a metal is also provided on the backside so that a contact can be made with the cathode on the backside. In one embodiment, the metal employed on the front side is aluminum. In one embodiment, the metal employed on the backside to create contacts is a Cr/Au alloy.
FIG. 1 illustrates a photodiode, in accordance with an embodiment of the present specification. The photodiode 100 comprises substrate wafer starting material further comprising a high resistivity silicon layer 102 on top of a relatively low resistivity wafer 104, which, in one embodiment is a silicon, n-type wafer (n+). In an embodiment, the resistivity of the silicon layer 102 ranges from 10 ohm cm to 10,000 ohm cm and that of the silicon n-type wafer 104 ranges from 0.001 ohm cm to 0.1 ohm cm. In an embodiment, the low resistivity substrate has a thickness in a range of 150 μm to 650 μm, and the high resistivity silicon layer has a thickness in a range of 10 μm to 100 μm. Thus, the overall thickness of the silicon substrate starting material ranges from 250 μm to 750 μm.
The photodiode 100 represents a two element array and further comprises a mask oxide layer 106 deposited on top of the silicon layer 102. The mask oxide layer 106 comprises silicon oxide (SiO2) and/or silicon nitride (Si3N4), whereby thermal oxidation is employed to achieve the mask oxidation. In one embodiment, the oxide layer 106 comprises SiO2 having a thickness of approximately 8,000 Å. In one embodiment the SiO2 layer defines a top surface of the photodiode 100.
The photodiode also comprises three n+ diffused zones 108 below the top surface of the photodiode 100 and positioned within the high resistivity silicon layer 102, on an extreme right edge and an extreme left edge, as well as in the center of the photodiode 100.
In multi-element photodiode arrays, crosstalk occurs as carriers generated in one element migrate to adjacent elements and cause crosstalk. The n+ diffused zones 108 function like a barrier, reflecting minority carriers and thus, do not let the minority carriers migrate to adjacent elements. In order to have a maximum blocking effect, the n+ diffused zones 108 need to extend to the low resistivity substrate layer 102, however, since there is a tradeoff with long diffusion time and cost, in an embodiment, while n+ diffused zones 108 are made deep, they do not extend all the way to the low resistivity substrate layer 102. In another embodiment, the three n+ diffused zones 108 are separated from each other and each n+ zone has a thickness extending through the entire depth of the low resistivity silicon layer 102.
The photodiode 100 further comprises two p diffused regions 110 positioned within the high resistivity silicon layer 102 as illustrated in FIG. 1. In an embodiment, the p diffused regions 110 have a thickness of approximately 2-5 μm. Also, in an embodiment, each p diffused region 110 is positioned between two n+ diffused regions 108. The photodiode 100 further comprises two shallow p+ diffused zones or regions 112 positioned within the high resistivity silicon layer 102 and directly on top of the p diffused regions 110 and below the top layer of the photodiode as illustrated in FIG. 1. In an embodiment, the depth of the shallow p+ zones 112 is approximately 0.3 μm.
In an embodiment, the p+ diffused zones 112 and a portion of the p doped zones is surrounded by p+ doped rings 114.
In one embodiment, as shown in FIGS. 1 and 19-21, the photodiode 100 further comprises anodes 116 on the top surface of the photodiode and a cathode 118 on a backside of the photodiode 100.
In another embodiment, the photodiode 100 comprises an anode on the top surface of the photodiode, a cathode on the top surface of the photodiode, and a cathode on a backside of the photodiode, as illustrated and described in greater detail with respect to FIGS. 13-15.
In yet another embodiment, the photodiode 100 comprises anodes and a cathode on the top surface of the photodiode, as is illustrated and described in greater detail with respect to FIGS. 16-18.
FIGS. 2 through 21 depict cross-sectional views of exemplary manufacturing steps of the photodiode of the present specification.
Referring now to FIG. 2, the starting material of the photodiode is a device wafer 200 comprising a high resistivity silicon layer 202 on top of a relatively low resistivity wafer 204, which, in one embodiment, is a silicon, n-type wafer. In an embodiment, the resistivity of the silicon layer 202 ranges from 10 ohm cm to 10,000 ohm cm and that of the silicon n type wafer 204 ranges from 0.001 ohm cm to 0.1 ohm cm. In an embodiment, the device wafer 200 has an overall thickness ranging from 250-750 μm and the silicon layer 202 has a thickness ranging from 10-100 μm. While it is preferred that the device wafer 200 be comprised of silicon, one of ordinary skill in the art would appreciate that any suitable semiconductor material, which can be processed in accordance with the manufacturing steps of the present specification, may be used. It should be understood by those of ordinary skill in the art, however, that the above specifications are not binding and that the type of material and resistivity can easily be changed to suit the design, fabrication, and functional requirements of the present specification.
Referring to FIG. 3, the silicon layer 202 is subjected to a standard mask oxidation process for growing a mask oxide layer 306 on the silicon layer 202. In one embodiment, the mask oxide layer 306 comprises silicon oxide (SiO2) and/or silicon nitride (Si3N4), and thermal oxidation is employed to achieve mask oxidation. In one embodiment, the oxide layer 306 comprises SiO2 having a thickness of approximately 8,000 Å. Standard mask oxidation is well known to those of ordinary skill in the art and will not be described in further detail herein.
As shown in FIG. 4, after the standard mask oxidation is complete, the device wafer 200 is subjected to n+ photolithography. After selecting a suitable material and creating a suitable photoresist pattern, a thin photoresist layer is applied to the front and back side of device wafer 200 to etch the pattern on the surfaces of the wafer. Generally, the photoresist layer is a photosensitive polymeric material for photolithography and photoengraving that can form a patterned coating on a surface. In one embodiment, the photoresist layer is applied via a spin coating technique. Spin coating is well known to those of ordinary skill in the art and will not be described in detail herein.
Next, the photoresist-coated device wafer 200 is aligned with an n+ mask. N+ masking techniques are employed to protect portions of device wafer 200. Generally, photographic masks are high precision plates containing microscopic images of preferred pattern or electronic circuits. They are typically fabricated from flat pieces of quartz or glass with a layer of chrome on one side. The mask geometry is etched in the chrome layer. In one embodiment, the n+ mask comprises a plurality of diffusion windows with appropriate geometrical and dimensional specifications. The n+ mask allows selective irradiation of the photoresist on the device wafer. Regions that are exposed to radiation are removed while those that are protected from diffusion remain shielded by the n+ mask.
An intense light, such as UV light, is projected through the mask, exposing portions of the photoresist layer in the pattern of the n+ mask. The exposed and remaining photoresist is then subjected to a suitable chemical or plasma etching process to reveal the pattern transfer from the mask to the photoresist layer. In one embodiment, the device wafer 200 is subjected to oxide etching to remove portions 408, 410 of the silicon dioxide layer 306.
Next as shown in FIG. 5 the device wafer 200 is subjected to n+ diffusion followed by drive-in oxidation after the previous n+ masking and etching steps. Generally, diffusion facilitates propagation of a diffusing material through a host material. An appropriate amount of dopant atoms, such as phosphorous, is deposited onto the device wafer 200 and fills the gaps left by the removed photoresist layer. Then, the wafer 200 is subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the wafer. In one embodiment, this process fills the regions 408, 410, via deep diffusion, with n+ dopant 511. In an embodiment, the width of the n+ diffused zones ranges from approximately 0.143 to 0.278 μm. In an embodiment, the n+ diffused zones are optional and are not present in the photodiode. The presence of the n+ diffused reduces surface leakage current and crosstalk, but will increases a furnace processing time. Therefore, inclusion of n+ deep diffused zones is a tradeoff between device performance and processing cost.
Next, the regions 408, 410 are covered with oxide layer 512. In one embodiment, oxide layer 512 has a thickness of approximately 4,000 Å.
Next as shown in FIG. 6 device wafer 200 is subjected to a lithography process, creating deep p diffused regions 614. In an embodiment, the exposed silicon surface of region 614 is approximately 1.75 μm wide and is subsequently oxidized. As with any conventional lithography process, p lithography comprises at least the following tasks, but not limited to such tasks: substrate preparation; photoresist application; soft baking; mask alignment; exposure; development; hard backing; and etching. In addition, various other chemical treatments may be performed.
The p masking and diffusion process is similar to that delineated with respect to the n+ masking process described earlier and will not be repeated in detail herein. The p masking process further comprises deposition and deep drive-in oxidation, allowing for predefined and/or predetermined thermal budget in accord with the principles of the present specification.
This is followed by boron implant and annealing, as shown in FIG. 7, to form a shallow p active area 716. Next, the regions 716 are covered with an oxide layer.
Next, as shown in FIG. 8 device wafer 200 is subjected to p diffusion followed by drive-in oxidation after the previous p masking and etching steps. An appropriate amount of dopant atoms, such as phosphorous, is deposited onto the substrate wafer and fills the gaps left by the removed photoresist layer. Then, the wafer 200 is subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the wafer creating deep p active areas 818. In an embodiment, the depth of the p type dopant ranges between 2 to 5 μm.
FIG. 9 illustrates the step of subjecting the device wafer 200 to etching and deep ring p+ masking process in order to create p+ deep ring zones 920, which are then covered with an oxide layer. The p+ deep ring zones 920 are created in order to ensure that the contact metal will not punch through the junction and degrade the dark current. In an embodiment, the photodiode of the present invention does not include p+ deep ring zones 920, described in greater detail below.
Next as shown in FIGS. 10 and 11 respectively, oxide layers covering the deep p active areas 818 are etched and layers of oxide such as silicon oxide 1122 and silicon nitride 1124 are grown on a front side 1126 and a backside 1128 of the wafer device 200. In an embodiment, the oxide layer 1122 has a thickness of approximately 150 Å and the nitride layer 1124 has a thickness of approximately 300 Å, forming an anti-reflective layer on the device wafer.
This is followed by boron implant and annealing, as shown in FIG. 12, to form shallow p+ active areas 1230. In an embodiment, the depth of the shallow p+ areas 1230 is approximately 0.3 μm. Thus, the PN junction is moved deep down underneath the oxide interface rendering the photodiodes increased ruggedness and stability, because when crystals are mounted on the surface of the silicon photodiode, it increases the likelihood of mechanical abrasion, scratches, etc. introduced on the silicon surface, resulting in degradation.
The improved P+ P N N+ junction photodiode of the present specification is front-side illuminated. The photodiode may be designed as having: top contacts with an anode and a cathode on a front/top side of the wafer device 200, or bottom contact with an anode on a front side and a cathode on a back side of the wafer device 200, or else both top and bottom contact devices with an anode on a front side, and a cathode on both front and back side of the wafer device 200.
FIGS. 13, 14, and 15 illustrate manufacturing steps for designing a photodiode having both top and bottom contact devices with an anode on a front side, and a cathode on both front and back side of the wafer device 200. Once shallow p+ active area 1230 is formed as illustrated in FIG. 12, the wafer device 200 is subjected to a contact masking process. As shown in FIG. 13, the nitride layer 1124 and the oxide layer 1122 are etched away from a front side 1126 and a backside 1128 of the wafer device 200. Contact mask areas 1332 approximately 0.02 μm wide are formed on the front side 1332. Next, as shown in FIGS. 14 and 15, the wafer device 200 is subjected to metal masking. A metal layer 1434 is deposited on the front side 1126 to form a cathode 1536 and an anode 1538 and on the back side to form a cathode 1540. In various embodiments, the metal used for forming the cathode and anode on the front side is aluminum; whereas that used for forming the cathode on the backside is a Cr/Au alloy. In various embodiments, an aluminum/nickel/gold alloy may be used for forming the cathode and anode on the front and backside of the photodiode. In other embodiments, a titanium/palladium/silver alloy may be used for forming the cathode and anode on the front and backside of the photodiode
FIGS. 16, 17 and 18 illustrate manufacturing steps for fabricating a photodiode having top contacts with an anode and a cathode on a front/top side of the wafer device 200. Once shallow p+ active area 1230 is formed as illustrated in FIG. 12, the wafer device 200 is subjected to a contact masking process. The nitride layer 1124 and the oxide layer 1122 are etched away from a front side 1332 of the wafer device 200. Referring to FIG. 16, contact mask areas 1642 approximately 0.02 μm wide are formed on the front side 1332. Next as shown in FIGS. 17 and 18, the wafer device 200 is subjected to metal masking. A metal layer 1744 is deposited on the front side 1332 to form a cathode 1846 and an anode 1848. In various embodiments, the metal used for forming the cathode and anode on the front side is aluminum.
FIGS. 19, 20 and 21 illustrate manufacturing steps for fabricating a photodiode having bottom contact with an anode on a front side and a cathode on a back side of the wafer device 200. Once shallow p+ active area 1230 is formed as illustrated in FIG. 12, the wafer device 200 is subjected to a contact masking process. The nitride layer 1324 and the oxide layer 1322 are etched off from a front side 1332 of the wafer device 200. Contact mask areas 1950 approximately 0.02 μm wide are formed on the front side 1332, as anode contacts are to be present on the front side. Next as shown in FIGS. 20 and 21, the wafer device 200 is subjected to metal masking. A metal layer 2052 is deposited on the front side 1332 to form an anode 2154 and on the backside to form a cathode 2156. In various embodiments, the metal used for forming the cathode on the back side is a backside is a Cr/Au alloy.
Conventional shallow junction photodiodes comprise deep p+ ring zones on which the anode metal contacts are located. During an aluminum-silicon alloying process (also called a sintering process), which is usually performed at approximately 425° C. for approximately 20 minutes, aluminum reacts with silicon and provides the photodiode device with a good ohmic contact. However, during the sintering process, aluminum penetrates the p+ shallow layer of the photodiode and may reach the depletion region, causing high dark currents in the photodiode. In order to avoid this, aluminum contact pads are placed on the deep p+ ring zones.
In an alternate embodiment of the present invention, a photodiode is manufactured without having a deep p+ ring zone. Since, the photodiode of the present invention comprises a deep p zone underneath a shallow p zone, the pn junction is now located a few microns below the surface, and aluminum cannot penetrate a few microns below to reach the depletion region. The photodiode without deep p+ rings, in one embodiment, has bottom contacts only, wherein an anode is provided on the front side of the photodiode and a cathode is provided on the back side. In another embodiment, the photodiode without deep p+ rings has top contacts only, wherein both anode and cathode are provided on the front side of the photodiode. In yet another embodiment, the photodiode without deep p+ rings has both top and bottom contacts, wherein an anode is provided on the front side and a cathode on both the front side and back side. In the cases where the photodiodes have bottom contacts, a metal is also provided on the back side so that a contact may be made with the cathode on the back side. In one embodiment, the metal employed on the front side is aluminum and, the metal employed on the back side to create contacts is a Chromium/Gold (Cr/Au) alloy.
FIG. 22 illustrates a photodiode without a deep p ring, in accordance with an embodiment of the present specification. The photodiode 2200 comprises substrate wafer starting material further comprising a high resistivity silicon layer 2202 on top of a relatively low resistivity wafer 2204, which, in one embodiment is a silicon, n-type wafer (n+). In an embodiment, the resistivity of the silicon layer 2202 ranges from 10 ohm cm to 10,000 ohm cm and that of the silicon n-type wafer 2204 ranges from 0.001 ohm cm to 0.1 ohm cm. In an embodiment, the low resistivity substrate has a thickness in a range of 150 μm to 350 μm, and the high resistivity silicon layer has a thickness in a range of 10 μm to 100 μm. Thus, the overall thickness of the silicon substrate starting material ranges from 250 μm to 400 μm.
The photodiode 2200 further comprises a mask oxide layer 2206 deposited on top of the silicon layer 2202. The mask oxide layer 2206 comprises silicon oxide (SiO2) and/or silicon nitride (Si3N4), whereby thermal oxidation is employed to achieve the mask oxidation. In one embodiment, the oxide layer 2206 comprises SiO2 having a thickness of approximately 4,000 Å. In one embodiment the SiO2 layer defines a top surface of the photodiode 2200.
The photodiode also comprises three n+ diffused zones 2208 below the top surface of the photodiode 2200 and positioned within the high resistivity silicon layer 2202, on an extreme right edge and an extreme left edge, as well as in the center of the photodiode 2200. In an embodiment, the three n+ diffused zones 2208 are separated from each other and each n+ zone has a thickness extending through the entire depth of the silicon layer 2202.
The photodiode 2200 further comprises two p diffused regions 2210 positioned within the high resistivity silicon layer 2202 as illustrated in FIG. 22. In an embodiment, the p diffused regions 2210 have a thickness of approximately 2-5 μm. Also, in an embodiment, each p diffused region 2210 is positioned between two n+ diffused regions 2208. The photodiode 2200 further comprises two shallow p+ diffused zones or regions 2212 positioned within the high resistivity silicon layer 2202 and directly on top of the p diffused regions 2210 and below the top layer of the photodiode as illustrated in FIG. 22. In an embodiment, the depth of the shallow p+ zones 2212 is approximately 0.3 μm.
In one embodiment, as shown in FIGS. 22 and 32-34, the photodiode 2200 further comprises anodes 2214 on the top surface of the photodiode and a cathode 2216 on a backside of the photodiode 2200.
In another embodiment, the photodiode 2200 comprises anodes and a cathode on the top surface of the photodiode, as is illustrated and described in greater detail with respect to FIGS. 35-37.
In yet another embodiment, the photodiode 2200 comprises an anode on the top surface of the photodiode, a cathode on the top surface of the photodiode, and a cathode on a backside of the photodiode, as illustrated and described in greater detail with respect to FIGS. 38-40.
FIGS. 23 through 40 depict cross-sectional views of exemplary manufacturing steps of the photodiode without deep p+ rings, in accordance with an embodiment of the present specification.
Referring now to FIG. 23, the starting material of the photodiode is a device wafer 2300 comprising a high resistivity silicon layer 2302 on top of a relatively low resistivity wafer 2304, which, in one embodiment, is a silicon, n-type wafer. In an embodiment, the resistivity of the silicon layer 2302 ranges from 10 ohm cm to 10,000 ohm cm and that of the silicon n type wafer 2304 ranges from 0.001 ohm cm to 0.1 ohm cm. In an embodiment, the device wafer 2300 has an overall thickness ranging from 250-400 μm and the silicon layer 2302 has a thickness ranging from 10-100 μm. While it is preferred that the device wafer 2300 be comprised of silicon, one of ordinary skill in the art would appreciate that any suitable semiconductor material, which can be processed in accordance with the manufacturing steps of the present specification, may be used. It should be understood by those of ordinary skill in the art, however, that the above specifications are not binding and that the type of material and resistivity can easily be changed to suit the design, fabrication, and functional requirements of the present specification.
Referring to FIG. 24, the silicon layer 2302 is subjected to a standard mask oxidation process for growing a mask oxide layer 2406 on the silicon layer 2302. In one embodiment, the mask oxide layer 2406 comprises silicon oxide (SiO2) and/or silicon nitride (Si3N4), and thermal oxidation is employed to achieve mask oxidation. In one embodiment, the oxide layer 2406 comprises SiO2 having a thickness of approximately 8,000 Å. Standard mask oxidation is well known to those of ordinary skill in the art and will not be described in further detail herein.
As shown in FIG. 25, after the standard mask oxidation is complete, the device wafer 2300 is subjected to n+ photolithography. After selecting a suitable material and creating a suitable photoresist pattern, a thin photoresist layer is applied to the front and back side of device wafer 2300 to etch the pattern on the surfaces of the wafer. Generally, the photoresist layer is a photosensitive polymeric material for photolithography and photoengraving that can form a patterned coating on a surface. In one embodiment, the photoresist layer is applied via a spin coating technique. Spin coating is well known to those of ordinary skill in the art and will not be described in detail herein.
Next, the photoresist-coated device wafer 2300 is aligned with an n+ mask. N+ masking techniques are employed to protect portions of device wafer 2300. Generally, photographic masks are high precision plates containing microscopic images of preferred pattern or electronic circuits. They are typically fabricated from flat pieces of quartz or glass with a layer of chrome on one side. The mask geometry is etched in the chrome layer. In one embodiment, the n+ mask comprises a plurality of diffusion windows with appropriate geometrical and dimensional specifications. The n+ mask allows selective irradiation of the photoresist on the device wafer. Regions that are exposed to radiation are removed while those that are protected from diffusion remain shielded by the n+ mask.
An intense light, such as UV light, is projected through the mask, exposing portions of the photoresist layer in the pattern of the n+ mask. The exposed and remaining photoresist is then subjected to a suitable chemical or plasma etching process to reveal the pattern transfer from the mask to the photoresist layer. In one embodiment, the device wafer 2300 is subjected to oxide etching to remove portions 2508, 2510 of the silicon dioxide layer 2406.
Next as shown in FIG. 26 the device wafer 2300 is subjected is subjected to a standard mask oxidation process for growing a mask oxide layer 2611 on the silicon layer 2302. In one embodiment, the mask oxide layer 2611 comprises silicon oxide (SiO2) and/or silicon nitride (Si3N4), and thermal oxidation is employed to achieve mask oxidation. In one embodiment, the oxide layer 2611 comprises SiO2 having a thickness of approximately 4,000 Å.
Next, referring to FIG. 26 the device wafer 2300 is subjected to n+ diffusion followed by drive-in oxidation after the previous n+ masking and etching steps. Generally, diffusion facilitates propagation of a diffusing material through a host material. An appropriate amount of dopant atoms, such as phosphorous, is deposited onto the device wafer 2300 and fills the gaps left by the removed photoresist layer. Then, the wafer 2300 is subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the wafer. In one embodiment, this process fills the regions 2508, 2510, via deep diffusion, with n+ dopant 2612. In an embodiment, the width of the n+ diffused zones ranges from approximately 0.143 to 0.278 μm. In an embodiment, the n+ diffused zones are optional may not be present in the photodiode.
Next, the regions 2508, 2510 are covered with oxide layer 2613. In one embodiment, oxide layer 2613 has a thickness of approximately 4,000 Å.
Next, as shown in FIG. 27, in a preferred embodiment, the device wafer 2300 is subjected to n+ masking and etching and n+ diffusion to create an n+ layer 2714 on a back side of the photodiode 2300, to provide an ohmic contact. In an embodiment, where the resistivity of the substrate being used to form the photodiode is very low, the n+ layer on the backside of the photodiode may be omitted. Further, as illustrated in FIG. 27, device wafer 2300 is subjected to a lithography process, creating deep p diffused regions 2715. In an embodiment, the exposed silicon surface of region 2715 is approximately 1.75 μm wide and is subsequently oxidized. As with any conventional lithography process, p lithography comprises at least the following tasks, but not limited to such tasks: substrate preparation; photoresist application; soft baking; mask alignment; exposure; development; hard backing; and etching. In addition, various other chemical treatments may be performed.
The p masking and diffusion process is similar to that delineated with respect to the n+ masking process described earlier and will not be repeated in detail herein. The p masking process further comprises deposition and deep drive-in oxidation, allowing for predefined and/or predetermined thermal budget in accord with the principles of the present specification.
This is followed by boron implant and annealing, as shown in FIG. 28, to form a shallow p active area 2816. The active area specifications, among other parameters, comprise significant performance characteristics of the photodiode. Next, the regions 2816 are covered with an oxide layer.
Next, as shown in FIG. 29 device wafer 2300 is subjected to p diffusion followed by drive-in oxidation after the previous p masking and etching steps. An appropriate amount of dopant atoms, such as phosphorous, is deposited onto the substrate wafer and fills the gaps left by the removed photoresist layer. Then, the wafer 2300 is subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the wafer creating deep p active areas 2918. In an embodiment, the depth of the p type dopant ranges between 2 to 5 μm.
Next as shown in FIG. 30 layers of oxide such as silicon oxide 3022 and silicon nitride 3024 are grown on a front side 1126 and a backside 1128 of the wafer device 200. In an embodiment, the oxide layer 3022 has a thickness of approximately 150 Å and the nitride layer 3024 has a thickness of approximately 300 Å, forming an anti-reflective layer on the device wafer.
This is followed by boron implant and annealing, as shown in FIG. 31, to form shallow p+ active areas 3126. In an embodiment, the depth of the shallow p+ areas 3126 is approximately 0.3 μm. The implant is formed through the silicon oxide 3022 and silicon nitride 3024 dual layer. Thus, the PN junction is moved deep down underneath the oxide interface rendering the photodiodes increased ruggedness and stability.
The improved P+ P N N+ junction photodiode of the present specification is front-side illuminated. The photodiode may be designed as having: top contacts with an anode and a cathode on a front/top side of the wafer device 2300, or bottom contact with an anode on a front side and a cathode on a back side of the wafer device 2300, or else both top and bottom contact devices with an anode on a front side, and a cathode on both front and back side of the wafer device 2300.
FIGS. 32, 33 and 34 illustrate manufacturing steps for fabricating a photodiode having bottom contact with an anode on a front side and a cathode on a back side of the wafer device 2300. Once shallow p+ active area 3126 is formed as illustrated in FIG. 31, the wafer device 2300 is subjected to a contact masking process. The nitride layer 3024 and the oxide layer 3022 are etched off from a front side of the wafer device 2300. Contact mask areas 3228 approximately 0.02 μm wide are formed on the front side. Next as shown in FIGS. 33 and 34, the wafer device 2300 is subjected to metal masking. A metal layer 3330 is deposited on the front side to form an anode 3432 and on the backside to form a cathode 3434. In various embodiments, the metal used for forming the cathode on the back side is a backside is a Cr/Au alloy.
FIGS. 35, 36 and 37 illustrate manufacturing steps for fabricating a photodiode having top contacts with an anode and a cathode on a front/top side of the wafer device 2300. Once shallow p+ active area 3126 is formed as illustrated in FIG. 31, the wafer device 2300 is subjected to a contact masking process. The nitride layer 3024 and the oxide layer 3022 are etched away from a front side of the wafer device 2300. Referring to FIG. 35, contact mask areas 3536 approximately 0.02 μm wide are formed on the front side. Next as shown in FIGS. 36 and 37, the wafer device 2300 is subjected to metal masking. A metal layer 3638 is deposited on the front side to form a cathode 3740 and an anode 3742. In various embodiments, the metal used for forming the cathode and anode on the front side is aluminum.
FIGS. 38, 39, and 40 illustrate manufacturing steps for fabricating a photodiode having both top and bottom contact devices with an anode on a front side, and a cathode on both front and back side of the wafer device 2300. Once shallow p+ active area 3126 is formed as illustrated in FIG. 31, the wafer device 2300 is subjected to a contact masking process. The nitride layer 3024 and the oxide layer 3022 are etched away from a front side and a backside of the wafer device 2300. Contact mask areas 3844 approximately 0.02 μm wide are formed on the front side. Next, as shown in FIGS. 39 and 40, the wafer device 2300 is subjected to metal masking. A metal layer 3946 is deposited on the front side to form a cathode 4048 and an anode 4050 and on the back side to form a cathode 4052. In various embodiments, the metal used for forming the cathode and anode on the front side is aluminum; whereas that used for forming the cathode on the backside is a Cr/Au alloy.
In an embodiment, the photodiode of the present invention is built on a high resistivity bulk wafer material instead of using a high resistivity layer over a low resistivity silicon wafer as the starting material. While a photodiode built on bulk wafer material is more structurally robust and therefore rugged, it has a lower shunt resistance and higher crosstalk when compared with devices made on a substrate having a high resistivity layer over a low resistivity silicon wafer. Typically, shunt resistance is tested as: 10 mV divided by the dark current (as measured at 10 mV), with respect to a photodiode. In order to obtain a high shunt resistance, the dark current is required to be as low as possible. Dark current, however, is generated throughout the volume of a high resistivity wafer layer. For example, a 250 μm thick high resistivity silicon bulk wafer generates more dark current than a 10 μm thick high resistivity layer on a 240 μm low resistivity substrate as the dark current generated in the low resistivity substrate is very small and negligible. In order to achieve low cross-talk on a multi-element array, the N+ region needs to extend throughout to reach the backside of the wafer. This is an expensive procedure as it would take a very long time to diffuse to have the N+ region 250 μm deep in a case of a 250 μm thick bulk wafer and thus, significantly increases the cost of the photodiode array.
FIG. 41 illustrates a photodiode fabricated on a bulk wafer material, in accordance with an embodiment of the present specification. The photodiode 4100 comprises bulk wafer starting material 4102 having a resistivity ranging from 10 ohm cm to 10,000 ohm cm. In an embodiment, the bulk wafer material 4102 has a thickness ranging from 250 μm to 400 μm.
The photodiode 4102 further comprises a mask oxide layer 4104 comprising silicon oxide (SiO2) and/or silicon nitride (Si3N4), whereby thermal oxidation is employed to achieve the mask oxidation. In one embodiment, the oxide layer 2204 comprises SiO2 having a thickness of approximately 4,000 Å. In one embodiment the SiO2 layer defines a top surface of the photodiode 4100.
The photodiode also comprises three n+ diffused zones 4106 below the top surface of the photodiode 4100 and positioned within the bulk wafer material 4102, on an extreme right edge and an extreme left edge, as well as in the center of the photodiode 4100.
The photodiode 4100 further comprises two p diffused regions 4108 positioned within the bulk wafer material 4102. In an embodiment, the p diffused regions 4108 have a thickness of approximately 2-5 μm. Also, in an embodiment, each p diffused region 4108 is positioned between two n+ diffused regions 4106. The photodiode 4100 further comprises two shallow p+ diffused zones or regions 4110 positioned directly on top of the p diffused regions 4108 and below the top layer of the photodiode as illustrated in FIG. 41. In an embodiment, the depth of the shallow p+ zones 4110 is approximately 0.3 μm. In one embodiment, as shown in FIG. 41 the photodiode 4100 further comprises anodes 4112 on the top surface of the photodiode and a cathode 4114 on a backside of the photodiode 4100. In another embodiment, the photodiode 4100 comprises both anodes and a cathode on the top surface of the photodiode.
FIG. 42 illustrates a photodiode built on a bulk wafer material, in accordance with an embodiment of the present specification. The photodiode 4200 comprises bulk wafer starting material 4202 having a resistivity ranging from 10 ohm cm to 10,000 ohm cm. In an embodiment, the bulk wafer material 4202 has a thickness ranging from 250 μm to 400 μm.
The photodiode 4200 represents a two element array and further comprises a mask oxide layer 4204 comprising silicon oxide (SiO2) and/or silicon nitride (Si3N4), whereby thermal oxidation is employed to achieve the mask oxidation. In one embodiment, the oxide layer 4204 comprises SiO2 having a thickness of approximately 8,000 Å. In one embodiment the SiO2 layer defines a top surface of the photodiode 4200.
The photodiode 4200 also comprises three n+ diffused zones 4206 below the top surface of the photodiode 4200 and positioned within the bulk wafer material 4202, on an extreme right edge and an extreme left edge, as well as in the center of the photodiode 4200. In an embodiment, the three n+ diffused zones 4206 are separated from each other. The photodiode 4200 further comprises two p diffused regions 4208 having a thickness of approximately 2-5 μm. Also, in an embodiment, each p diffused region 4208 is positioned between two n+ diffused regions 4206. The photodiode 4200 further comprises two shallow p+ diffused zones or regions 4210 positioned directly on top of the p diffused regions 4206 and below the top layer of the photodiode 4200 as illustrated in FIG. 42. In an embodiment, the depth of the shallow p+ zones 4210 is approximately 0.3 μm.
In an embodiment, the p+ diffused zones 4210 and a portion of the p doped zones 4208 is surrounded by p+ doped rings 4212. In one embodiment, as shown in FIG. 42 the photodiode 4200 further comprises anodes 4214 on the top surface of the photodiode 4200 and a cathode 4216 on a backside of the photodiode 4200.
The above examples are merely illustrative of the structure and manufacturing steps of the photodiode array of the present specification. Although only a few embodiments of the present specification have been described herein, it should be understood that the present specification might be embodied in many other specific forms without departing from the spirit or scope of the invention. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention may be modified within the scope of the appended claims.

## Claims

1. A photodiode having a top surface defined by at least one SiO2 layer comprising:
a bulk wafer positioned below the top surface of the photodiode;
a first P doped zone within the bulk wafer, wherein the first P doped zone has a thickness of 2-5 μm;
a first P+ doped zone positioned between the top of the first P doped zone and the top of the photodiode;
an anode on the top surface of the photodiode; and
a cathode on a backside of the photodiode.

2. The photodiode of claim 1 wherein the bulk wafer has a thickness in a range of 250 μm to 400 μm.

3. A photodiode having a top surface defined by at least one SiO2 layer comprising:
a bulk wafer positioned below the top surface of the photodiode;
a first P doped zone within the bulk wafer, wherein the first P doped zone has a thickness of 2-5 μm;
a first P+ doped zone positioned between the top of the first P doped zone and the top of the photodiode, wherein the first P+ doped zone and a portion of the first P doped zone is surrounded by P+ doped ring.

4. A photodiode having a top surface defined by at least one SiO2 layer comprising:
a bulk wafer positioned below the top surface of the photodiode;
a first P doped zone within the bulk wafer, wherein the first P doped zone has a thickness of 2-5 μm;
a first P+ doped zone positioned between the top of the first P doped zone and the top of the photodiode, and
a first N+ region extending throughout the thickness of the bulk wafer.

5. The photodiode of claim 4 further comprising a second N+ region extending throughout the thickness of the bulk wafer, wherein the second N+ region is separated from the first N+ region by a third region and wherein the first P doped zone and first P+ doped zone is located in the third region.

6. The photodiode of claim 5 further comprising a third N+ region extending throughout the thickness of the bulk wafer, wherein the third N+ region is separated from the second N+ region by a fourth region.

7. The photodiode of claim 6 further comprising a second P doped zone within said fourth region in the bulk wafer, wherein the second P doped zone has a thickness of 2-5 μm.

8. The photodiode of claim 7 further comprising a second P+ doped zone positioned between the top of the second P doped zone and the top of the photodiode in the fourth region.

9. The photodiode of claim 4 wherein all of the first P+ doped zone and a portion of the first P doped zone is surrounded by P+ doped ring.

10. The photodiode of claim 8 wherein all of the second P+ doped zone and a portion of the second P doped zone is surrounded by P+ doped ring.

11. A photodiode having a top surface defined by at least one SiO2 layer comprising:
a bulk wafer positioned below the top surface of the photodiode;
a first P doped zone within the bulk wafer, wherein the first P doped zone has a thickness of 2-5 μm;
a first P+ doped zone positioned between the top of the first P doped zone and the top of the photodiode;
an anode on the top surface of the photodiode;
a cathode on the top surface of the photodiode; and
a cathode on a backside of the photodiode.