# Patent

## Title
Device structure, layout and fabrication method for uniaxially strained transistors

## Abstract

A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

## Background
BACKGROUND
1. Technical Field
The present invention relates to semiconductor fabrication and more particularly to uniaxially strained transistors and methods for fabrication thereof.
2. Description of the Related Art
Epitaxially grown SiGe channels are being used to tune threshold voltages of p-type metal oxide semiconductor field effect transistors (PMOSFETs) in high-k/metal gate CMOS. If grown on a large Si island, the SiGe channel is under biaxial compressive strain. However, most transistors in a state-of-the-art integrated circuit are narrow, with a width typically less than 500 nm. When transistors are fabricated on individual active areas, the length of the active area is also small (typically 200 nm or less). So, the biaxial compressive strain in the SiGe is almost completely relaxed.
A typical state-of-the-art PMOSFET may contain an embedded SiGe structure in a source/drain (S/D) area to apply uniaxial compressive strain to the channel and to lower the parasitic resistance of the device. However, when used on individual SiGe-channel PMOSFETs, where the strain in the SiGe channel is already relaxed, the embedded SiGe process does not apply significant stress on the SiGe channel. Furthermore, the embedded SiGe process requires that a recess is made in the S/D area first, and then filled with epitaxially grown SiGe. However, once the channel SiGe is etched to form the recess, most of the built-in stress in this layer is relaxed.
In other words, with the embedded SiGe process, the strain relaxation of the SiGe channel is inevitable and due to the small difference in the lattice constant of the embedded SiGe and channel SiGe materials, the strain transferred to the channel is also small.
SUMMARY
A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
Another method for fabricating a semiconductor device includes providing a strained semiconductor layer having a first strained axis; forming an active region within a surface of the strained semiconductor layer by doping the active region for forming transistor channels where the active region has a longitudinal axis along the strained axis; forming gate structures over the active region; forming first spacers on the gate structures; forming raised source/drain regions on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to fowl transistor devices having a strained channel; and forming second spacers over the first spacers and a portion of the raised source/drain regions.
A semiconductor device includes a strained semiconductor layer having a first strained axis. An active region is formed within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis. Gate structures are formed over the active region. Raised source/drain regions are formed on the active region above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.



BRIEF DESCRIPTION OF DRAWINGS
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
FIG. 1 is a cross-sectional view of a SiGe-channel MOSFET for demonstrating the present principles;
FIG. 2A is a plot of transconductance versus gate voltage showing the impact of a narrow width on device performance;
FIG. 2B is a scatter plot of Ioff versus Ion showing the impact of a narrow width on device performance;
FIG. 3A is a cross-sectional view of a conventional device having recesses formed adjacent to a channel which relax the channel material;
FIG. 3B is a cross-sectional view of the conventional device of FIG. 3B having embedded source/drain regions formed in the recesses formed adjacent to the channel
FIG. 4A is a perspective view of a device having a substrate with a strained layer provided thereon in accordance with one illustrative embodiment;
FIG. 4B is a perspective view of the device of FIG. 4A having an active region patterned from the strained layer in accordance with one illustrative embodiment;
FIG. 4C is a perspective view of the device of FIG. 4B showing shallow trench isolation and gate structures formed of the active region in accordance with one illustrative embodiment;
FIG. 5 is a cross-sectional view of a device having raised source/drain regions formed on the channel layer in accordance with the present principles;
FIG. 6 is a layout showing two NAND gate devices sharing active areas in accordance with the present principles; and
FIG. 7 is a flow diagram showing an illustrative method for fabricating a transistor in accordance with the present principles.



DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
A device, layout and fabrication method are disclosed to transform a biaxial compressive strain in, e.g., a SiGe-channel p-type metal oxide semiconductor field effect transistor (PMOSFET) into a uniaxial compressive strain device by employing a proper layout design. To achieve uniaxial strain, PMOSFETs are fabricated on long and narrow active regions and the embedded source/drain SiGe process is replaced by a raised source/drain SiGe.
The present principles provide a method to fabricate SiGe-channel PMOSFETs on long and narrow active regions. The channel is under uniaxial compressive strain, with stress levels, e.g., reaching and even exceeding 2 GPa. The strain achieved is independent of transistor pitch, and is applicable and scalable for future technology nodes. The conventional embedded SiGe process is replaced by a raised SiGe to avoid strain relaxation and benefit from the lower contact resistance of the SiGe source/drain (S/D) regions. To minimize any parasitic capacitance penalty imposed by the raised SiGe structure, a faceted epitaxy is preferably employed to form this raised layer.
With a proper layout design, it is possible that many PMOSFETs can share a single active area, so that the active area can be made long enough (e.g., 2 microns or more) and the strain in the channel direction is preserved. In this way, SiGe-channel MOSFETs with significantly high uniaxial compressive strain can be made.
It is to be understood that the present invention will be described in terms of a given illustrative architecture formed on a semiconductor wafer; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
The devices and circuits as described herein may be part of a design for an integrated circuit chip. The chip design may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a cross-sectional view of a SiGe-channel metal oxide semiconductor field effect transistor (MOSFET) 10 is illustratively depicted. The transistor 10 includes a gate electrode 20 and a gate dielectric 22. The gate electrode 20 has spacers 24 formed on sidewalls thereof. Active areas included at a surface of source/drain regions 14 include a silicided layer 26 formed. Shallow trench isolation (STI) regions 28 are provided between devices to reduce parasitic current and charge buildup. For a logic transistor 10, a channel 12 has a very small width. So, for an individual transistor, the strain in the SiGe channel 12 is fully relaxed.
In accordance with the present principles, if an active area is made long enough, the strain in the transport direction is not relaxed. For a wide transistor, SiGe in a channel is under biaxial compressive strain. Although this strain configuration leads to a significant hole mobility increase, carrier velocity and in turn device drive current is not significantly increased. On the other hand, for narrow devices the strain perpendicular to the channel is relaxed. So, a SiGe channel is under uniaxial compressive strain, which leads to reduction in the transport effective mass and increases in the drive current.
Referring to FIG. 2A, a family of curves are plotted for transconductance (μS/μm) versus gate voltage (V). The curves show an increase in saturation transconductance with decreased channel width (e.g., a 55% increase). In FIG. 2B, a scatter plot of off current (Ioff(A/μm)) versus drive current (Ion(μA/μm)) for a device is illustratively shown. More than an 80% increase in the drive current is shown as the channel width is reduced.
Referring to FIG. 3A, an embedded SiGe process is illustratively described to provide comparisons. A cross-sectional view of a SiGe-channel MOSFET 30 is illustratively depicted. The transistor 30 includes a gate electrode 32 and a gate dielectric 34. The gate electrode 32 has spacers 36 formed on sidewalls thereof Shallow trench isolation (STI) regions 38 are provided between devices to reduce parasitic current and charge buildup. A first recess 40 is made in a source/drain area. During this step, the strain in a SiGe channel 42 is fully relaxed. When the recess 40 is filled with the embedded SiGe 44 in FIG. 3B, uniaxial compressive strain is applied to the channel 42. However, since the channel 42 is already relaxed and the lattice constant of the channel and embedded SiGe are not very different, the amount of strain transferred to the channel is not significant.
Referring to FIG. 4A, a perspective view of a semiconductor device 100 is illustratively depicted in accordance with the present principles. A substrate 101 may include a Semiconductor-on-Insulator (SOI) or bulk substrate that may include Gallium Arsenide, monocrystalline silicon, Germanium, or any other material or combination of materials where the present principles may be applied. In some embodiments, the substrate 101 further comprises other features or structures that are formed on or in the semiconductor substrate in previous process steps. A strained semiconductor layer 120 is formed in or on substrate 101 or is bonded to substrate 101.
Referring to FIG. 4B, a shallow trench isolation (STI) region is formed by conventional methods. This may include first forming a mask layer 111. The mask layer 111 may include growing a thin thermal oxide 113 of about 2-8 nm of the strained semiconductor layer 120, and then depositing a silicon nitride film 115 of about 40-80 nm thick (pad nitride). Layer 113 and 115 are formed over the entire surface of layer 120. Next, a photoresist material is deposited (not shown) and employed to pattern the mask layer 111, which is, in turn, employed to pattern an active region formed in the strained semiconductor layer 120. FIG. 4B shows a strained narrow and long region 121 formed for pFETs after etching layer 120 using the mask layer 111 (e.g., the pad nitride 115 and pad oxide 113 layers). The strained layer 120 and unstrained layer 101 are etched to form shallow trenches 105. Next, a thin oxide liner can be created followed by deposition of SiO2 and planarization by chemical mechanical polishing (CMP) to form the shallow trench regions 103 (shown in FIG. 4C).
Referring to FIG. 4C, layer 120 may include a biaxial compressive strain. In one embodiment, layer 120 includes SiGe strained in accordance with preferred performance criteria. In one embodiment, the strain in layer 120 corresponds to stresses in the GPa range and in particular up to about 2 GPa. The strain is preferably in a direction of a channel, especially in, e.g., a SiGe-channel p-type metal oxide semiconductor field effect transistor (PMOSFET). The strain is preferably a uniaxial compressive strain. To achieve uniaxial strain, PMOSFETs are fabricated on long and narrow active regions 120. The device 100 includes gate electrodes 102 and gate dielectric 104. The gate electrode 102 may include any suitable conductive material, e.g., polycrystalline or amorphous silicon, germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conducting metallic compound material (e.g., tantalum nitride, titanium nitride, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotube, conductive carbon, or any suitable combination of these materials. The gate electrode 102 may further comprise dopants that are incorporated during or after deposition.
The gate dielectric 104 may include a silicon oxide, silicon nitride, silicon oxynitride, organic dielectric, etc. In a preferred embodiment, gate dielectric 104 include a high dielectric constant material, such as, e.g., metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, any suitable combination of those high-k materials, or any suitable combination of any high-k material with silicon oxide, silicon nitride, and/or silicon oxynitride.
The gate structure includes spacers 106 formed on sidewalls thereof. The spacers 106 may include a nitride, for example. Regions 121 will form a transistor channel. Shallow trench isolation (STI) regions 103 are provided between devices to reduce parasitic current and charge buildup. STI regions 103 may include an oxide, e.g., a silicon oxide.
The present principles provide a method to fabricate SiGe-channel PMOSFETs on long and narrow active regions. The channel (formed in layer 120) is under uniaxial compressive strain, with stress levels, e.g., reaching and even exceeding 2 GPa. The strain achieved is independent of transistor pitch, and is applicable/scalable for future technology nodes.
With a proper layout design, many PMOSFETs can share a single active area in region 120, so that the active area can be made long enough (e.g., 2 microns or more) and the strain in the channel direction is preserved. In this way, SiGe-channel MOSFETs with significantly high uniaxial compressive strain can be made.
Referring to FIG. 5, a cross-sectional view of transistors 130 having strained channels and raised source/drain regions 132 is shown. The conventional embedded active area process (FIG. 3B) is eliminated. Raised source/drain regions 132 are grown on semiconductor layer 120 to avoid strain relaxation and benefit from lower contact resistance of the source/drain regions 132. To minimize any parasitic capacitance penalty imposed by the raised regions 132 structure, a faceted epitaxy is preferably employed to form this raised layer. Faceted epitaxy may include eptiaxially growing SiGe or other materials on layer 120 between transistors 130.
In one embodiment, SiGe-channel PMOSFETs are fabricated on the long and narrow active area 120, so that a channel 121 is naturally under uniaxial compressive strain. The width of the channel may be selected, but is preferably determine in accordance with a minimum features size achievable by the technology. The fabrication process may proceed as in conventional SiGe-channel process with the embedded SiGe step skipped to avoid strain relaxation in the channel SiGe. Instead, the raised layer 132 is epitaxially grown in the source/drain area.
In one embodiment, layer 132 may be in-situ doped with high boron concentration or could be implanted with boron, BF2, or another p-type dopant followed by an anneal process. The epitaxially grown material may include, e.g., SiGe, however other materials such as pure germanium, pure silicon or other semiconductor material, may be employed. To reduce any possible penalty in parasitic capacitance due to the raised source/drain structure, a faceted epitaxy process is preferably employed.
In one embodiment, the growth of SiGe raised source/drain regions 132 (optionally in-situ doped) on heavily doped SiGe of layer 120 is provided. Such a process has been a challenge for at least two reasons: 1) conventional epitaxy employs a hydrogen pre-bake at high temperatures, which may result in a poor SiGe surface; and 2) boron in heavily doped Si or SiGe diffuses to the native oxide and makes it difficult to remove native oxide with HF. Both problems can be resolved by a low-temperature in-situ clean process.
A second spacer 142 is formed, and then silicide 144 is formed on the raised regions 132. The spacer may include nitride. The rest of the process continues employing known processes. Other methods used in CMOS processes to apply mechanical stress to the channel, such as stress liners, can be used to further increase the strain in the channel and increase the device performance.
Referring to FIG. 6, to take advantage of a layout, multiple transistors 202 are preferably formed on a long and narrow active area 204 (e.g., including the features of active area 120). This can be achieved for a CMOS circuit 200, e.g., composed of NAND gates 203 and 205. NAND logic gates 203 and 205 with an even number of inputs 208 and 210 can be attached from both sides. NAND gates with an odd number of inputs and other logic gates can be attached at least from one side to the neighboring cells, to share a long active area.
In addition to active area 204, gates 203 and 205 include active areas 212, gate structures 214 and interconnection conductors 216. Contacts 218 make connections between a supply rail (VDD) and S/D regions of active areas 204 for inputs 208. Contacts 220 make connections between a ground rail (GND) and S/D regions of active areas 212 for inputs 210. Contacts 222 make connections between active areas 204 and active areas 212 for interconnection conductors 216.
Referring to FIG. 7, a flow diagram shows an illustrative method for fabricating a semiconductor device. In block 302, a strained semiconductor layer having a first strained axis is provided. This may include providing a strained SiGe layer having a uniaxial compressive strain along the first strained axis.
In block 304, an active region is formed within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis. The active region may include a length of 2 microns, but other lengths are also contemplated that provide the desired strain to yield sufficient performance of the device being fabricated. The active region is preferably shared among a plurality of transistors.
In block 306, gate structures are formed over the active region, e.g., gate dielectric, gate conductor, etc. In block 308, first spacers are formed on the gate structures. In block 312, raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices. The raised source/drain regions are preferably epitaxially grown and more preferably grown using a faceted epitaxial growth process. The epitaxial growth process may include in-situ doping, or doping may be performed after the formation of raised source/drain regions.
In block 314, second spacers are formed over the first spacers and a portion of the raised source/drain regions. In block 316, the raised source/drain regions are silicided. In block 318, processing continues to complete the semiconductor device and/or chip.
Having described preferred embodiments for a device structure, layout and fabrication method for uniaxially strained transistors (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

## Claims

1. A method for fabricating a semiconductor device, comprising:
providing a strained semiconductor layer having a first strained axis;
etching the strained semiconductor layer down to an underlying layer formed from a different material than the strained semiconductor layer to form a raised active region, wherein the active region has a longitudinal axis along the strained axis;
forming gate structures over the active region; and
forming raised source/drain regions on the active region above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

2. The method as recited in claim 1, further comprising forming first spacers on the gate structures.

3. The method as recited in claim 2, further comprising forming second spacers over the first spacers and a portion of the raised source/drain regions.

4. The method as recited in claim 1, wherein providing a strained semiconductor layer includes providing a strained SiGe layer having a uniaxial compressive strain along the first strained axis.

5. The method as recited in claim 1, wherein etching includes forming an active region having a length of at least 2 microns.

6. The method as recited in claim 1, wherein etching includes sharing the active region among a plurality of transistors.

7. The method as recited in claim 1, wherein forming raised source/drain regions includes epitaxially growing the raised source/drain regions.

8. The method as recited in claim 7, wherein epitaxially growing the raised source/drain regions includes a faceted epitaxial growth process.

9. The method as recited in claim 7, wherein epitaxially growing includes in-situ doping.

10. The method as recited in claim 1, further comprising siliciding the raised source/drain regions.

11. A method for fabricating a semiconductor device, comprising:
providing a strained semiconductor layer having a first strained axis;
etching the strained semiconductor layer down to an underlying layer formed from a different material than the strained semiconductor layer to form a raised active region, wherein the active region is formed by doping the active region for forming transistor channels and further wherein the active region has a longitudinal axis along the strained axis;
forming gate structures over the active region;
forming first spacers on the gate structures;
forming raised source/drain regions on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices having a strained channel; and
forming second spacers over the first spacers and a portion of the raised source/drain regions.

12. The method as recited in claim 11, wherein providing a strained semiconductor layer includes providing a strained SiGe layer having a uniaxial compressive strain along the first strained axis.

13. The method as recited in claim 11, wherein etching includes forming an active region having a length of at least 2 microns.

14. The method as recited in claim 11, wherein etching includes sharing the active region among a plurality of transistors.

15. The method as recited in claim 11, wherein forming raised source/drain regions includes epitaxially growing the raised source/drain regions.

16. The method as recited in claim 15, wherein epitaxially growing the raised source/drain regions includes a faceted epitaxial growth process.

17. The method as recited in claim 15, wherein epitaxially growing includes in-situ doping.

18. The method as recited in claim 11, further comprising siliciding the raised source/drain regions.