# Patent

## Title
Mixed signal controller

## Abstract

A mixed signal controller for a power quality compensator includes an analog circuit, an analog-to-digital converter (ADC), and a digital circuit. The analog circuit amplifies an input signal from the power quality compensator by a gain factor and outputs an analog signal, which is converted to a digital signal by the ADC. The digital circuit receives the digital signal, calculates the reference compensating current of each phase and then generates a trigger signal via hysteresis PWM to the power quality compensator. The digital circuit includes an evaluation circuit that calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the gain factor when the value of the system total harmonic distortion reaches a predetermined threshold.

## Background
FIELD OF THE INVENTION
The present invention relates to a method and system that includes a mixed signal controller that controls power quality compensators.
BACKGROUND
Nonlinear, inductive, and unbalanced loads cause power quality issues such as transmission losses and damages to electronic devices. Power quality compensators such as passive power filters (PPFs), active power filters (APFs), and hybrid active power filters (HAPFs) have been developed to solve these problems.
New methods and systems that improve the compensation performance of the power quality compensators will assist in advancing technological needs and solving technological problems.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a mixed signal controller in accordance with an example embodiment.
FIG. 2 shows a method executed by a mixed signal controller to control a power quality compensator in accordance with an example embodiment.
FIG. 3 shows a mixed signal controller in accordance with an example embodiment.
FIG. 4 shows a circuit diagram of a hybrid active power filter (HAPF) in accordance with an example embodiment.
FIG. 5 shows a control method of a voltage source inverter by hysteresis pulse width modulation (PWM) in accordance with an example embodiment.
FIG. 6A shows a current error waveform of the voltage source inverter by hysteresis PWM in accordance with an example embodiment.
FIG. 6B shows an approximate current error waveform of the voltage source inverter by hysteresis PWM in accordance with an example embodiment.
FIG. 7 shows simulated total harmonic distortion (THD) and approximate total harmonic distortion (ATHD) values in accordance with an example embodiment.
FIG. 8 shows simulated absolute percentage error |ΔATHD| of ATHD compared with THD in accordance with an example embodiment.
FIG. 9 shows a simulated current waveform at THD=4.92%, ATHD=5.1%, |ΔATHD|=3.72% in accordance with an example embodiment.
FIG. 10 shows a simulated current waveform at THD=16.08%, ATHD=16.33%, |ΔATHD|=1.55% in accordance with an example embodiment.
FIG. 11 shows a simulated current waveform at THD=67.56%, ATHD=69.99%, |ΔATHD|=3.44% in accordance with an example embodiment.
FIG. 12 shows a simulated current waveform at THD=124.8%, ATHD=142.9%, |ΔATHD|=14.5% in accordance with an example embodiment.
FIG. 13 shows simulated THD and ATHD curves in accordance with an example embodiment.
FIG. 14 lists simulated and experimental system parameters in accordance with an example embodiment.
FIG. 15 shows a mixed signal controller in accordance with another example embodiment.
FIG. 16 shows a connection configuration of a mixed signal controller in accordance with another example embodiment.
FIG. 17 shows a data stream of a mixed signal controller in accordance with another example embodiment.
FIG. 18 shows a graph of a simulated voltage and current of a system before compensation in accordance with an example embodiment.
FIG. 19 shows a graph of a simulated voltage and current of the system after HAPF compensation in accordance with an example embodiment.
FIG. 20A shows a graph of a voltage and current of a three-phase power system before compensation at 20% loading in accordance with an example embodiment.
FIG. 20B shows a graph of a voltage and current of a three-phase power system before compensation at 50% loading in accordance with an example embodiment.
FIG. 20C shows a graph of a voltage and current of a three-phase power system before compensation at 70% loading in accordance with an example embodiment.
FIG. 20D shows a graph of a voltage and current of a three-phase power system before compensation at 90% loading in accordance with an example embodiment.
FIG. 21A shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a digital controller at 20% loading in accordance with an example embodiment.
FIG. 21B shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a digital controller at 50% loading in accordance with an example embodiment.
FIG. 21C shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a digital controller at 70% loading in accordance with an example embodiment.
FIG. 21D shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a digital controller at 90% loading in accordance with an example embodiment.
FIG. 22A shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a mixed signal controller at 20% loading in accordance with an example embodiment.
FIG. 22B shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a mixed signal controller at 50% loading in accordance with an example embodiment.
FIG. 22C shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a mixed signal controller at 70% loading in accordance with an example embodiment.
FIG. 22D shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a mixed signal controller at 90% loading in accordance with an example embodiment.
FIG. 23 summarizes experimental compensation results of a three-phase power system after HAPF compensation with a digital controller compared with a mixed signal controller.
FIG. 24A shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a digital controller during loading changes in accordance with an example embodiment.
FIG. 24B shows a graph of a voltage and current of a three-phase power system after HAPF compensation with a mixed signal controller during loading changes in accordance with an example embodiment.



SUMMARY OF THE INVENTION
One example embodiment is a mixed signal controller for a power quality compensator that includes an analog circuit, an analog-to-digital converter (ADC), and a digital circuit. The analog circuit amplifies an input signal from the power quality compensator by a gain factor and outputs an analog signal, which is converted to a digital signal by the ADC. The digital circuit receives the digital signal, calculates the reference compensating current of each phase and generates a trigger signal via hysteresis PWM to the power quality compensator. The digital circuit includes an evaluation circuit that calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the gain factor when the value of the system total harmonic distortion reaches a predetermined threshold.
Other example embodiments are discussed herein.
DETAILED DESCRIPTION
Examples embodiments relate to system and methods that control power quality compensators via mixed signal controllers.
Various algorithms have been proposed to improve compensation performance of power quality compensators by increasing response speed and reducing the total harmonic distortion (THD). Existing power quality compensators usually execute compensation control algorithms via a digital controller.
Most digital controllers are designed for a full loading situation. The full analog-to-digital conversion input signal range of a digital controller is utilized to avoid analog signal saturation. In a light loading situation, the digital controller may suffer from low resolution. International standards of compensation performance requires the THD to be less than 20%, which is hard to meet for light loading power systems due to the low resolution of the input signals compared with the error signal and the Pulse Width Modulation (PWM) error margin. An example embodiment can relax these problems related to power quality compensation.
In one example embodiment, a self-configuration control algorithm for a power quality compensator is executed by a mixed signal controller that includes an analog circuit, such as a field programmable analog array (FPAA) and a digital circuit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP) circuit. The mixed signal controller improves power compensation quality with adaptive gain, on-the-fly programmability and self-reconfiguration properties in a three-phase four-wire HAPF system. An approximate total harmonic distortion (ATHD) is calculated in real time to detect the compensation performance instantaneously. Gains are calculated in the FPGA and transferred by a feedback loop to the FPAA in a dynamic configuration process.
In one example embodiment, an ATHD index is calculated to determine the total harmonic distortion value in real time, which reduces the evaluation time of the power quality compensation system performance.
In another embodiment, a hysteresis error margin or a hysteresis band (HB) is designed with hysteresis pulse width modulations to determine the ATHD of the power quality compensator instantaneously. When an actual current is greater than a reference current by a HB value, an inverter leg in the power quality compensator is switched on. When the actual current is less than the reference current by the HB value, the inverter leg is witched off. The HB specifies the maximum current ripple.
In another embodiment, the analog circuit of the mixed signal controller amplifies an input signal from the power quality compensator by a gain factor. The digital circuit of the mixed signal controller calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the gain factor when the value of the system total harmonic distortion reaches a predetermined threshold. The analog circuit and the digital circuit communicates directly with each other. Gains are calculated in the digital circuit and sent back to the analog circuit in a dynamic configuration process.
FIG. 1 shows a mixed signal controller 100 in accordance with an example embodiment. The mixed signal controller 100 includes an analog circuit 110, an analog-to-digital converter (ADC) 120 and a digital circuit 130. The digital circuit 130 includes an evaluation circuit 132 and a calculation circuit 134.
As one example, the analog circuit 110 amplifies an input signal from the power quality compensator by a first gain factor and outputs an analog signal. The analog signal is converted to a digital signal by the ADC. The digital circuit receives the digital signal from the ADC 120, then calculates the reference compensating current of each phase and then generates a trigger signal to the power quality compensator.
In an example embodiment, the trigger signal generated by the digital circuit 130 is a pulse width modulation (PWM) signal that controls a switching device of the power quality compensator.
In an example embodiment, the evaluation circuit 132 calculates a value of the system total harmonic distortion after the power quality compensator compensates power and adjusts the first gain factor when the value of the system total harmonic distortion reaches a predetermined threshold. By way of example, the value of the system total harmonic distortion is an approximate total harmonic distortion (ATHD) that is calculated instantaneously without frequency spectrum computation by the following equation:




  
    ATHD
    =
    
      
        
          2
          3
        
      
      ⁢
      
        HB
        
          I
          
            1
            ⁢
            p
          
        
      
    
  
  ,




where I1p is a peak value of a sinusoidal current, and HB is a hysteresis band value that specifies a maximum variation of the current. ATHD is defined as a fast evaluation index of compensation performance instead of THD, in which the HB of the ATHD can be determined according to hysteresis pulse width modulation (PWM) or the compensation error of space vector modulation.
In an example embodiment, the calculation circuit 134 calculates a second gain factor and sends the second gain factor to the analog circuit. The analog circuit compares the second gain factor to a predetermined value and adjusts the first gain factor to decrease the system total harmonic distortion after the power quality compensator compensates power when the second factor is different than the predetermined value. By way of example, the second gain factor is given by the following equation:




  
    G
    =
    
      INT
      ⁡
      
        (
        
          W
          R
        
        )
      
    
  
  ,




where INT is an integer function, W is a measured amplitude width of the digital signal out of the ADC, and R is a peak-to-peak range of the input signal.
As one example, the analog circuit 110 detects saturation by comparing the second gain factor sent from the digital circuit with a predetermined value and adjusts the first gain factor when the second gain factor is different than the predetermined value. As another example, saturation occurs when the second gain factor equals to 1.
FIG. 2 shows a method executed by a mixed signal controller to control a power quality compensator in accordance with an example embodiment.
Block 210 states amplifying an input signal from the power quality compensator by a first gain factor to generate an analog signal.
Consider an example in which a mixed signal controller includes an analog circuit, an analog-to-digital converter (ADC) and a digital circuit. The digital circuit includes an evaluation circuit and a calculation circuit.
As one example, the analog circuit amplifies an input signal from the power quality compensator by a first gain factor and outputs an analog signal.
Block 220 states converting the analog signal to a digital signal.
In one example embodiment, the analog-to-digital converter (ADC) converts the analog signal sent from the analog circuit to a digital signal and sends the digital signal to the digital circuit.
Block 230 states receiving the digital signal and calculating a value of the system total harmonic distortion after the power quality compensator compensates power.
By way of example, the digital circuit receives the digital signal from the ADC and calculates an approximate total harmonic distortion (ATHD) that is calculated instantaneously without frequency spectrum computation by the following equation:




  
    ATHD
    =
    
      
        
          2
          3
        
      
      ⁢
      
        HB
        
          I
          
            1
            ⁢
            p
          
        
      
    
  
  ,




where I1p is a peak value of a sinusoidal current, and HB is a hysteresis band value that specifies a maximum variation of the current. ATHD is defined as a fast evaluation index of compensation performance instead of THD, in which the HB of the ATHD can be determined according to hysteresis pulse width modulation (PWM) or the compensation error of space vector modulation.
Block 240 states calculating a second gain factor that is sent to the analog circuit.
As one example, the digital circuit calculates a second gain factor and sends the second gain factor to the analog circuit. By way of example, the second gain factor is given by the following equation:




  
    G
    =
    
      INT
      ⁡
      
        (
        
          W
          R
        
        )
      
    
  
  ,




where INT is an integer function, W is a measured amplitude width of the digital signal out of the ADC, and R is a peak-to-peak range of the input signal.
Block 250 states adjusting the first gain factor based on the second gain factor to decrease the value of the system total harmonic distortion.
As one example, the analog circuit receives the second gain factor calculated by the digital circuit and compares the second gain factor to a predetermined value. When the second factor is different than the predetermined value, the analog circuit adjusts the first gain factor to decrease the system total harmonic distortion after the power quality compensator compensates power and to avoid situation.
Block 255 states calculating the reference compensating current of each phase.
By way of example, the reference compensating current i*cx for a HAPF shown is given by the following equation:




  
    
      i
      cx
      *
    
    =
    
      
        
          (
          
            
              i
              La
            
            -
            
              
                
                  p
                  _
                
                
                  v
                  2
                
              
              ⁢
              
                v
                La
              
            
          
          )
        
        ⁢
        
          
            n
            a
          
          →
        
      
      +
      
        
          (
          
            
              i
              Lb
            
            -
            
              
                
                  p
                  _
                
                
                  v
                  2
                
              
              ⁢
              
                v
                Lb
              
            
          
          )
        
        ⁢
        
          
            n
            b
          
          →
        
      
      +
      
        
          (
          
            
              i
              Lc
            
            -
            
              
                
                  p
                  _
                
                
                  v
                  2
                
              
              ⁢
              
                v
                Lc
              
            
          
          )
        
        ⁢
        
          
            n
            c
          
          →
        
      
    
  
  ,




where {{right arrow over (na)},{right arrow over (nb)},{right arrow over (nc)}} is the space basis in the a-b-c coordinate, p=vLaiLa+vLbiLb+vLciLc, and p is an average value of the instantaneous power p.
Block 260 states sending a pulse width modulation (PWM) signal to the power quality compensator.
In an example embodiment, the mixes signal controller controls a voltage source PWM inverter via hysteresis current control, in which a sinusoidal reference current is compared with an actual current. When the actual current is greater than the reference current by a hysteresis band (HB) value, the inverter leg is witched on. When the actual current is less than the reference current by the HB value, the inverter leg is witched off. The HB specifies the maximum current ripple.
FIG. 3 shows a mixed signal controller 300 in accordance with an example embodiment. The mixed signal controller 300 includes a field programmable analog array (FPAA) 310, an analog-to-digital converter (ADC) 320 and a field programmable gate array/digital signal processor (FPGA/DSP) 330.
By way of example, input signals for the FPAA are analog signals from a power system and/or a power quality compensator. The output digital signals generated by the FPGA/DSP are pulse width modulation (PWM) trigger signals, which control switching devices of the power quality compensator.
In an example embodiment, The FPAA can be operated as an adaptive signal conditioning unit that preconditions and filters according to the optimization of system performance. The modified signals then pass to the digital units for further processing, assisted by the ADC. The digital unit, FPGA/DSP works with a subprogram to optimize the system operation by reconfiguring the control system automatically, or by self-testing and self-repairing. When it is necessary to reconfigure the analog part, the reprogramming data can be transferred directly through a digital path to the FPAA.
In another example embodiment, the FPAA communicates directly with the FPGA/DSP and sends out control signals to the FPGA to modify operation algorithms.
FIG. 4 shows a circuit diagram of a hybrid active power filter (HAPF) 400 in accordance with an example embodiment. The power quality compensator 400 is a three-phase four-wire hybrid active power filter (HAPF) system. Various phases are denoted as a, b, c, and n. Vsa, Vsb and Vsc are system voltages at different phases. System current, load current, and inverter current are is, iL, and ic, respectively.
Exemplary self-reconfiguration control strategies for improving power quality compensator performance based on this HAPF system are discussed herein.
In one example embodiment, total harmonic distortion (THD) reflects a level of electrical noise generated by a power system and its ideal amount is 0%. It is given by the following equation:




  
    THD
    =
    
      
        
          
            ∑
            
              n
              =
              2
            
            ∞
          
          ⁢
          
            I
            n
            2
          
        
      
      
        I
        1
      
    
  
  ,




where the numerator is a sum of all harmonic currents, and the denominator I1 is a fundamental current.
THD is used as an index to evaluate whether the power quality of a power supply is acceptable or not. However, the fundamental frequency current and its related harmonic components are defined and computed under root mean square (rms) values. It takes at least a period cycle of time to sample data for computation. For example, a 50-Hz system needs 0.02 s of cycle time.
FIG. 5 shows a control method of a voltage source inverter by hysteresis pulse width modulation PWM in accordance with an example embodiment.
FIG. 5 illustrates the hysteresis current control of a voltage source PWM inverter, in which the sinusoidal reference current i*cx is compared with the actual current icx. When the actual current is greater or less than the reference current by a hysteresis band (HB) 510, the inverter leg is switched on or off accordingly. Therefore, the HB 510 specifies the maximum current ripple.
FIG. 6A shows a current error waveform 610 of the voltage source inverter by hysteresis PWM in accordance with an example embodiment. The X-axis shows time, and the Y-axis shows values of the actual current icx.
By way of example, the actual current icx is decomposed into a sinusoidal current and an irregular triangular current waveform by superposition. After the superposition, the current error waveform 610 as shown in FIG. 6A has an irregular triangular shape, in which the rate of change of current at any moment is different, due to its different voltage amplitude at different times. Therefore, the triangular waveforms are not symmetrical.
FIG. 6B shows an approximate current error waveform 620 of the voltage source inverter by hysteresis PWM in accordance with an example embodiment. The X-axis shows time, and the Y-axis shows values of the actual current icx.
The ratio of the sum of all harmonic current components to the fundamental current component can be considered as the ratio of the rms value of the irregular triangular waveform to the fundamental sinusoidal waveform. However, by taking an approximation, the regular triangular waveform 620, as shown in FIG. 6B, is chosen instead of the irregular triangular waveform 610 as shown in FIG. 6A.
Further, FIG. 6B shows that each period of the triangular waveform is different. Correspondingly, the rms value of a regular triangular waveform is given by the following equation:




  
    
      I
      h
    
    =
    
      
        
          
            1
            T
          
          ⁢
          
            
              ∫
              0
              T
            
            ⁢
            
              
                
                  [
                  
                    
                      
                        8
                        ·
                        HB
                      
                      
                        π
                        2
                      
                    
                    ⁢
                    
                      
                        ∑
                        
                          n
                          =
                          1
                        
                        ∞
                      
                      ⁢
                      
                        (
                        
                          
                            1
                            n
                          
                          ⁢
                          cos
                          ⁢
                          
                            
                          
                          ⁢
                          n
                          ⁢
                          
                            
                          
                          ⁢
                          ω
                          ⁢
                          
                            
                          
                          ⁢
                          t
                        
                        )
                      
                    
                  
                  ]
                
                2
              
              ⁢
              
                
              
              ⁢
              
                d
                t
              
            
          
        
      
      =
      
        HB
        
          3
        
      
    
  
  ,




where the rms value is shown to be independent of the period of the triangular waveform. An approximate total harmonic distortion (ATHD) is then given by the following equation:




  
    ATHD
    =
    
      HB
      
        
          3
        
        ⁢
        
          I
          1
        
      
    
  
  ,




where I1 is an rms current value hat has √{square root over (2)} difference with its peak value I1p, and HB is a hysteresis band value that specifies a maximum variation of the current.

As one example, the instantaneous fundamental active current peak value can be calculated by the following equation:




  
    
      I
      
        1
        ⁢
        p
      
    
    =
    
      
        
          2
        
        ·
        
          p
          _
        
      
      
        
          3
        
        ⁢
        
          
          Δ
          
        
      
    
  
  ,




where ∥Δ∥=√{square root over (va2+vb2+vc2)}, and




  
    p
    _
  
  =
  
    
      
        1
        T
      
      ⁢
      
        
          ∫
          0
          T
        
        ⁢
        
          
            
              v
              →
            
            ·
            
              i
              →
            
          
          ⁢
          
            
          
          ⁢
          dt
        
      
    
    =
    
      
        1
        T
      
      ⁢
      
        
          ∫
          0
          T
        
        ⁢
        
          
            (
            
              
                
                  v
                  a
                
                ·
                
                  i
                  a
                
              
              +
              
                
                  v
                  b
                
                ·
                
                  i
                  b
                
              
              +
              
                
                  v
                  c
                
                ·
                
                  i
                  c
                
              
            
            )
          
          ⁢
          
            
          
          ⁢
          
            dt
            .
          
        
      
    
  




The approximate total harmonic distortion (ATHD) is then given by the following equation:




  
    ATHD
    =
    
      
        
          2
          3
        
      
      ⁢
      
        HB
        
          I
          
            1
            ⁢
            p
          
        
      
    
  
  ,




where I1p is a peak value of a sinusoidal current which can be calculated instantaneously, and HB is a hysteresis band value that specifies a maximum variation of the current. ATHD is a fast evaluation index of compensation performance instead of THD, in which the HB of the ATHD can be determined according to hysteresis pulse width modulation (PWM) or the compensation error of space vector modulation.
By way of example, the ATHD is calculated during compensation, and as a result the fundamental reactive component is not considered in computing the ATHD value. The calculated ATHD would otherwise be smaller when the fundamental reactive current is included.
Simulated total harmonic distortion (THD) and approximate total harmonic distortion (ATHD) values are shown in table 700 of FIG. 7.
By way of example, table 700 shows the simulated THD and ATHD values with respect to the different fundamental current peak I1p, in per unit (pu), and HB in pu at a sampling frequency of 5 KHz, and a system frequency of 50 Hz. For example, when I1p=0.5 and HB=0.1, the simulation results show that THD is 16.08% and its ATHD is 16.33%.
Simulated absolute percentage error of ATHD compared with THD is shown in table 800 of FIG. 8.
By way of example, table 800 shows the simulated absolute percentage error of ATHD compared with THD calculated by the following equation:




  
    
    
      Δ
      ATHD
    
    
  
  =
  
    
      
      
        
          THD
          -
          ATHD
        
        THD
      
      
    
    ×
    100
    ⁢
    
      %
      .
    
  




The ATHD index is estimated to evaluate the compensation performance instantaneously. As shown in table 800, the absolute percentage error range of ATHD is shown to be from 0.06% to 14.5%, and its average percentage error is 3.44%. THD values that are close to or below 20% are highlighted underline in tables 700 and 800. The average percentage error of ATHD within 20% THD is 2.089%.
In one example embodiment, an ATHD at 16% is chosen when THD at 20% is the compensation target to include this average percentage error of ATHD.
The simulated results are estimated values and the values will be different in other example embodiments.
FIGS. 9-12 show simulated current waveforms at THD of 5%, 16%, 68%, and 124%, respectively. The X-axis shows time in seconds, and the Y-axis shows current values in amperes.
FIG. 9 shows the waveform 900 at THD of around 5% with |ΔATHD|=3.72%, corresponding to I1p=1.6 A and HB=0.1 A. FIG. 10 shows the waveform 1000 at THD of around 16% with |ΔATHD|=1.55%, corresponding to I1p=0.5 A and HB=0.1 A. FIG. 11 shows the waveform at THD of around 68% with average |ΔATHD|=3.44%, corresponding to I1p=0.7 A and HB=0.6 A. FIG. 12 shows the waveform at THD of around 124% with the largest |ΔATHD|=14.5%, corresponding to I1p=0.4 A and HB=0.7 A.
By way of example, at THD of around 16%, based on table 700 of FIG. 7, the hysteresis error band HB should be set as one-fifth of the fundamental amplitude. Furthermore, a parameter K=I1/HB is defined as a ratio of the fundamental rms current amplitude to the hysteresis error band value. When K increases, the compensated current ripple relatively decreases.
FIG. 13 shows simulated THD 1310 and ATHD 1320 in accordance with an example embodiment. The X-axis is K values, and the Y-axis shows a ratio of the simulated THD to the ATHD. With respect to K, the difference between THD and ATHD is small.
Simulated and experimental system parameters are shown in table 1400 of FIG. 14.
By way of example, the simulation shown in FIG. 13 takes the system parameters listed in table 1400 under 50% loading compensation. The THD standard of 20% is selected, as discussed, while the ATHD of 16% for the percentage error and safety margin considerations is selected.
It is shown in FIG. 13 that K is around 3.8 at ATHD of around 16%, which corresponds to I1p=0.5 A, HB=0.1 A, and THD=16.08% in table 700. I1p is the fundamental current peak value. As one example, the HB value or error margin of the hysteresis PWM control should not be less than 0.26 times the fundamental rms current amplitude.
The ATHD as discussed herein is an approximated performance index that rapidly determines the THD value and that estimates the power quality compensation system performance of active power filters (APFs) and/or hybrid active power filters (HAPFs). The advantages of using an ATHD over THD are: 1) It can simplify the computation without computation of the frequency spectrum; 2) The ATHD value can be obtained in real time; 3) Hardware implementation of ATHD is simplified.
FIG. 15 shows a mixed signal controller 1500 in accordance with another example embodiment. The mixed signal controller 1500 includes a field programmable analog array (FPAA) 1510, an analog-to-digital converter (ADC) 1520 and a field programmable gate array/digital signal processor (FPGA/DSP) 1530.
By way of example, input signals are ic, vL and iL, which are inverter current, load voltage, and load current, respectively. The FPAA 1510 amplifies the input signals by a gain factor (G) and sends the amplified analog signals to the ADC 1520. The FPGA/DSP 1530 receives digital signals from the ADC, calculates the reference compensating current of each phase and then generates pulse width modulation (PWM) trigger signals to control switching devices in a power quality compensator.
As an example, the FPAA 1510 is an analog control part in which G is the amplified analog signal which is calculated in the FPGA/DSP 1530. The FPGA/DSP calculates and determines if the ATHD value of the compensator can fulfill the requirement of the THD standard. If not, the amplification of the analog input signal before the ADC will be taken to enhance the compensation performance. The amplifying gain G will be calculated by diving the range of ADC and the range of peak-to-peak input signal. Then this gain signal calculated by the FPGA/DSP is sent to analog circuit to implement the signal amplification. If the input signal is larger than the input range of the ADC, then G=1. If the input is not larger than the input range of the ADC, then G is determined by:




  
    G
    =
    
      INT
      ⁡
      
        (
        
          W
          R
        
        )
      
    
  
  ,




where INT is an integer function that takes out all the fraction parts, W is a measured width (range) of the ADC, and R is a peak-to-peak input signal range for a given period.
In an example embodiment, block 1540 in the FPGA/DSP 1530 calculates the average active power ({right arrow over (p)}) by:




  
    p
    _
  
  =
  
    
      
        1
        T
      
      ⁢
      
        
          ∫
          0
          T
        
        ⁢
        
          
            
              v
              →
            
            ·
            
              
                ι
                ⁢
                
                  
                
              
              →
            
          
          ⁢
          
            d
            t
          
        
      
    
    =
    
      
        1
        T
      
      ⁢
      
        
          ∫
          0
          T
        
        ⁢
        
          
            (
            
              
                
                  v
                  a
                
                ·
                
                  Gi
                  La
                
              
              +
              
                
                  v
                  b
                
                ·
                
                  Gi
                  Lb
                
              
              +
              
                
                  v
                  c
                
                ·
                
                  Gi
                  Lc
                
              
            
            )
          
          ⁢
          
            
          
          ⁢
          
            
              d
              t
            
            .
          
        
      
    
  




Block 1550 in the FPGA/DSP 1530 calculates the reference current by:




  
    Gi
    cx
    *
  
  =
  
    
      
        (
        
          
            Gi
            La
          
          -
          
            
              
                p
                _
              
              
                v
                2
              
            
            ⁢
            
              v
              La
            
          
        
        )
      
      ⁢
      
        
          n
          a
        
        →
      
    
    +
    
      
        (
        
          
            Gi
            Lb
          
          -
          
            
              
                p
                _
              
              
                v
                2
              
            
            ⁢
            
              v
              Lb
            
          
        
        )
      
      ⁢
      
        
          n
          b
        
        →
      
    
    +
    
      
        (
        
          
            Gi
            Lc
          
          -
          
            
              
                p
                _
              
              
                v
                2
              
            
            ⁢
            
              v
              Lc
            
          
        
        )
      
      ⁢
      
        
          
            n
            c
          
          →
        
        .
      
    
  




Then, its fundamental current can be computed instantaneously by:




  
    
      I
      
        1
        ⁢
        p
      
    
    =
    
      
        
          2
        
        ·
        
          p
          _
        
      
      
        
          3
        
        ⁢
        
          
          Δ
          
        
      
    
  
  ,




where ∥Δ∥=√{square root over (va2+vb2+vc2)}.
The mixed signal controller 1500 has self-reconfiguration capabilities that improve the performance of the power quality compensator. By way of example, the reference compensating current i*cx for a HAPF shown in FIG. 4 is given by the following equation:




  
    
      i
      cx
      *
    
    =
    
      
        
          (
          
            
              i
              La
            
            -
            
              
                
                  p
                  _
                
                
                  v
                  2
                
              
              ⁢
              
                v
                La
              
            
          
          )
        
        ⁢
        
          
            n
            a
          
          →
        
      
      +
      
        
          (
          
            
              i
              Lb
            
            -
            
              
                
                  p
                  _
                
                
                  v
                  2
                
              
              ⁢
              
                v
                Lb
              
            
          
          )
        
        ⁢
        
          
            n
            b
          
          →
        
      
      +
      
        
          (
          
            
              i
              Lc
            
            -
            
              
                
                  p
                  _
                
                
                  v
                  2
                
              
              ⁢
              
                v
                Lc
              
            
          
          )
        
        ⁢
        
          
            n
            c
          
          →
        
      
    
  
  ,




where {{right arrow over (na)},{right arrow over (nb)},{right arrow over (nc)}} is the space basis in the a-b-c coordinate, p=vLaiLa+vLbiLb+vLciLc, and p is an average value of the instantaneous power p.
Under perfect compensation, the actual compensator current i*cx should be the same as its reference current i*cx. The subscript “x” denotes phases a, b and c. The source current isx, composed of load current and compensator current is given by the following equations:

isx=iLx+i*cx≡isx1 and

isx1≅iLx+icx+HB, 

where HB is a hysteresis band (HB) value that specifies a maximum variation of the compensator current.

In one example embodiment, the resolution of HB is limited by the available bits (B) of the ADC, and the amplitude width (W) of the input signal. The minimum HB value is given by the following equations:




  
    
      HB
      min
    
    =
    
      W
      
        2
        
          B
          +
          1
        
      
    
  
  ,




where HBmin is the minimum value of HB and cannot be further reduced due to the hardware limitations of the controller. When the amplitude of HB is relatively near to the amplitude of iLx and icx, the compensation performance may not be acceptable. This is because the HBmin cannot be further reduced. The gain factor G is attached to K and the K value can be adjusted to a larger value to decrease THD and ATHD, as shown in the following equations:



  
    K
    =
    
      
        G
        ·
        
          
            i
            
              sx
              ⁢
              
                
              
              ⁢
              1
            
          
          HB
        
      
      ≅
      
        
          G
          ·
          
            (
            
              1
              +
              
                
                  
                    i
                    Lx
                  
                  +
                  
                    i
                    cx
                  
                
                HB
              
            
            )
          
        
        ⁢
        
          
        
        ⁢
        and
      
    
  




  
    
      G
      =
      
        INT
        ⁡
        
          (
          
            W
            R
          
          )
        
      
    
    ,
  



where INT is an integer function that takes out all the fraction parts, W is the measured width (range) of the ADC, and R is the peak-to-peak input signal range for a given period, for example, 1 min or several hours, to avoid system fluctuation during operations.
As an example, the gain factor (G) is calculated by the DSP/FPGA, and then sent to the FPAA for gain modification. During light loading, G is an integer number larger than 1.
The gain factor G improves the compensation performance of the system. As one example, when the ATHD is around 16%, K≈3.8 according to FIG. 13 when there is no gain (G=1). As another example, when the ATHD is around 20%, K≈3 according to FIG. 13 when there is no gain, but ATHD can be reduced to around 10% if G is set to 2, which leads to K≈6.
In an example embodiment, a saturation detection function is implemented in FPAA to avoid analog signal saturation. The gain factor G is adjusted to 1 by the FPAA when saturation occurs.
In another example embodiment, a compensation error (Δierror) is given by the following equation:

Δierror=HBmin=G·i*cx−G·icx.

FIG. 16 shows a connection configuration of a mixed signal controller 1600 in accordance with another example embodiment. The mixed signal controller includes two field programmable analog arrays (FPAAs) 1610, two analog-to-digital converters (ADCs) 1620 and a field programmable gate array/digital signal processor (FPGA/DSP) 1630. The mixed signal controller 1600 reconfigures itself to adjust the gain automatically and rapidly, which further improve the compensation performance of the system.
By way of example, the FPAAs 1610 are controlled by the FPGA 1630. The inherent reconfigurable properties of FPAAs allow the analog modules to be dynamically reconfigured through a serial interfaces. During system initialization, voltage and current signals are detected and amplified by the FPAA by a gain factor, digitized through an ADC, and fed into the FPGA for further processing. The gain factor is controlled by the FPGA. The output voltage limit is 3 V, which is the maximum input voltage for the ADC. If the input signal amplified by the FPAA is saturated, the FPGA will reset the gain factor to 1. Through various computations and comparisons, the corresponding value of the gain factor for the FPGA will be obtained.
As an example, the mixed signal controller improves power compensation quality with adaptive gain, on-the-fly programmability and self-reconfiguration properties in a three-phase four-wire HAPF system. An ATHD is calculated in real time to detect the compensation performance instantaneously. Gains are calculated in the FPGA and transferred by a feedback loop to the FPAA in a dynamic configuration process.
FIG. 17 shows a data stream 1700 of a mixed signal controller in accordance with another example embodiment.
As one example, the configuration clock of the FPAA and FPGA is 20 megahertz (MHz). In the configuration process, every gain value needs 11 bytes of control logic data, defined by the configuration protocol in the FPAA.
Each byte has one 8-bit address, which in total needs t1 (second) to completely transmit. The sampling frequency of the whole controller is 25 kHz, so the controller outputs obtained in this period is 1/25 kHz (40 μs). In total, the control loop, including the analog to digital conversion, power quality theory, PWM techniques, and feedback loop, can be completed in one ADC sample period. Moreover, t1, as given in the following equation, is much smaller than one ADC sampling cycle, which means the compensation control algorithm will not be affected by the on-the-fly FPAA reconfiguration.




  
    t
    1
  
  =
  
    
      11
      ×
      8
      ×
      
        1
        
          20
          ×
          
            10
            6
          
        
      
    
    =
    
      
        
          4.4
          ×
          
            10
            
              -
              6
            
          
          ⁢
          s
        
        ⪡
        
          1
          
            25
            ×
            
              10
              3
            
          
        
      
      =
      
        4
        ×
        
          10
          
            -
            5
          
        
        ⁢
        
          s
          .
        
      
    
  




Example embodiments are provided below to show power quality compensator performance compared with a conventional digital controller, in which a three-phase four-wire HAPF system as shown in FIG. 4 is chosen as the power quality compensator. Table 1400 of FIG. 14 lists the simulated and experimental system parameters for the HAPF with different loadings.
FIG. 18 shows a graph 1800 of a simulated voltage and current of a system before compensation in accordance with an example embodiment. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
As one example, when 50% loading is connected, the three-phase simulated THD of the system current (THDisa, THDisb and THDisc) are 39.3%, 38.3%, and 37.1%, with a power factor (PF) of 0.83, 0.82, and 0.82, respectively. When 90% loading is connected (loading compensation, by applying the conventional digital changes), the three-phase simulated are 20.8%, 20.3%, and 19.6%, with PF of 0.95, 0.95, and 0.95, respectively. The above simulated THD values do need satisfy the requirement of less than 20% under both 50% and 90% loading conditions before compensation.
FIG. 19 shows a graph 1900 of a simulated voltage and current of the system after HAPF compensation in accordance with an example embodiment. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
As one example, the simulated THD values satisfy the requirement of less than 20% under both 50% and 90% loading conditions after HAPF compensation. Moreover, the PF are improved to unity. The HAPF compensation performance is satisfactory under both light loading and full loading.
FIG. 20A-20D show graphs 2000A-2000D of voltages and currents of a three-phase power system before compensation at 20% loading, 50% loading, 70% loading and 90% loading. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
FIG. 21A-21D show graphs 2100A-2100D of voltages and currents of a three-phase power system after HAPF compensation with a digital controller at 20% loading, 50% loading, 70% loading and 90% loading. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
FIG. 22A-22D show graphs 2200A-2200D of voltages and currents of a three-phase power system after HAPF compensation with a mixed signal controller at 20% loading, 50% loading, 70% loading and 90% loading. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
By way of example, the three-phase power system with the mixed signal controller achieves best compensation performance, particularly under light loading conditions. As shown in FIG. 22A-22D, the THD values in phase “a” are improved to 13.9%, 10.8%, 5.7%, and 5.6%, at 20% loading, 50% loading, 70% loading and 90% loading, respectively. With a conventional digital controller as shown in FIG. 21A-21D, the THD at 20% loading fails to meet the requirement of less than 20%.
FIG. 23 summarizes experimental compensation results of a three-phase power system after HAPF compensation with a digital controller compared with a mixed signal controller in table 2300. It summarizes the power quality parameters as shown in FIG. 20-22 for different testing loads before and after compensation.
FIG. 24A shows a graph 2400A of a voltage and current of a three-phase power system after HAPF compensation with a digital controller during loading changes in accordance with an example embodiment. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
FIG. 24B shows a graph 2400B of a voltage and current of a three-phase power system after HAPF compensation with a mixed signal controller during loading changes in accordance with an example embodiment. The X-axis shows time in seconds, and the Y-axis shows voltage in volts and current in amperes.
By way of example, the dynamic compensation performance during loading changes with the conventional controller (as shown in FIG. 24A) and with the mixed signal controller (as shown in FIG. 24B) is compared. The dynamic response time of both controllers is less than two cycles, which verifies the fast dynamic response of the mixed signal controller and the function of on-the-fly mixed signal reconfiguration.
As used herein, a “hybrid active power filter” or “HAPF” is one of the power compensation systems with passive filters and active power filters that compensates harmonic current and reactive power.
As used herein, “pulse width modulation” or “PWM” is a process of modifying the width of pulses in a pulse train in proportion to a control signal.
As used herein, a “hysteresis band” or “HB” is a numerical range that specifies a variation of current.
As used herein, a “power factor” or “PF” is the ratio of the real power flowing to the load to the apparent power in the circuit of an electrical power system.
As used herein, a “power quality compensator” is an electronic system for a power supply. Examples of power quality compensators include, but are not limited to, passive power filters (PPFs), active power filters (APFs), and hybrid active power filters (HAPFs).
The systems and methods in accordance with example embodiments are provided as examples, and examples from one system or method should not be construed to limit examples from another system or method. Further, methods discussed within different figures can be added to or exchanged with methods in other figures. Further yet, specific numerical data values (such as specific quantities, numbers, categories, etc.) or other specific information should be interpreted as illustrative for discussing example embodiments. Such specific information is not provided to limit example embodiments.

## Claims

1. A mixed signal controller for a power quality compensator, comprising:
an analog circuit that amplifies an input signal from the power quality compensator by a first gain factor and outputs an analog signal;
an analog-to-digital converter (ADC) that converts the analog signal to a digital signal; and
a digital circuit that receives the digital signal and generates a trigger signal to the power quality compensator,
wherein the digital circuit further includes an evaluation circuit that calculates a value of a system total harmonic distortion after the power quality compensator compensates power and adjusts the first gain factor of the analog circuit in real time to decrease the system total harmonic distortion by comparing the first gain factor with a second gain factor represented by:





  G
  =
  
    INT
    ⁡
    
      (
      
        W
        R
      
      )
    
  



where INT is an integer function, W is a measured amplitude width of the digital signal out of the ADC, and R is a peak-to-peak range of the input signal.

2. The mixed signal controller of claim 1, wherein the value of the system total harmonic distortion is an approximate total harmonic distortion (ATHD) that is calculated instantaneously without frequency spectrum computation by:




  ATHD
  =
  
    
      
        2
        3
      
    
    ⁢
    
      HB
      
        I
        
          1
          ⁢
          p
        
      
    
  



where HB is a hysteresis band value that specifies a variation range of the current, and I1p is a peak value of a sinusoidal current that is determined instantaneously by:





  
    I
    
      1
      ⁢
      p
    
  
  =
  
    
      
        2
      
      ·
      
        p
        _
      
    
    
      
        3
      
      ⁢
      
        
        Δ
        
      
    
  



where ∥Δ∥=√{square root over (va2+vb2+vc2)}, p is an average active power, and va, vb, and vc are voltages at phases a, b, and c.

3. The mixed signal controller of claim 1, wherein the trigger signal is a pulse width modulation (PWM) signal that controls a switching device of the power quality compensator.

4. The mixed signal controller of claim 1, wherein the value of the system total harmonic distortion is dependent on a compensation error that is limited by the ADC.

5. The mixed signal controller of claim 1, wherein the value of the system total harmonic distortion is dependent on a value of the first gain factor.

6. The mixed signal controller of claim 1, wherein the digital circuit further includes a calculation circuit that calculates the second gain factor and sends the second gain factor to the analog circuit, wherein the analog circuit compares the second gain factor to a predetermined value and adjusts the first gain factor to decrease the system total harmonic distortion after the power quality compensator compensates power when the second factor is different than the predetermined value.

7. The mixed signal controller of claim 1, wherein the analog circuit compares the second gain factor sent from the digital circuit with a predetermined value and adjusts the first gain factor when the second gain factor is different than the predetermined value.

8. A method executed by a mixed signal controller that controls a power quality compensator, the method comprising:
amplifying, by an analog circuit and by a first gain factor, an input signal from the power quality compensator to generate an analog signal;
converting, by an analog-to-digital converter (ADC), the analog signal to a digital signal;
receiving, by a digital circuit, the digital signal from the ADC;
calculating, by the digital circuit, a value of a system total harmonic distortion after the power quality compensator compensates power;
calculating, by the digital circuit, a second gain factor that is sent to the analog circuit;
adjusting, by the analog circuit and based on the second gain factor, the first gain factor to decrease the value of the system total harmonic distortion; and
sending, by the digital circuit, a pulse width modulation (PWM) signal to the power quality compensator,
wherein the second gain factor is calculated by:





  G
  =
  
    INT
    ⁡
    
      (
      
        W
        R
      
      )
    
  



where INT is an integer function, W is a measured amplitude width of the digital signal out of the ADC, and R is a peak-to-peak range of the input signal.

9. The method of claim 8, wherein the value of the system total harmonic distortion is an approximate total harmonic distortion (ATHD) that is calculated instantaneously without frequency spectrum computation by:




  ATHD
  =
  
    
      
        2
        3
      
    
    ⁢
    
      HB
      
        I
        
          1
          ⁢
          p
        
      
    
  



where HB is a hysteresis band value that specifies a variation range of the current, and I1p is a peak value of a sinusoidal current that is determined instantaneously by:





  
    I
    
      1
      ⁢
      p
    
  
  =
  
    
      
        2
      
      ·
      
        p
        _
      
    
    
      
        3
      
      ⁢
      
        
        Δ
        
      
    
  



where ∥Δ∥=√{square root over (va2+vb2+vc2)}, p is an average active power, and va, vb, and vc are voltages at phases a, b, and c.

10. The method of claim 8, wherein the value of the system total harmonic distortion is dependent on a compensation error that is limited by the ADC.

11. The method of claim 8, wherein the value of the system total harmonic distortion is dependent on a value of the first gain factor.

12. The method of claim 8, further comprising:
comparing, by the analog circuit, the second gain factor with a predetermined value; and
adjusting, by the analog circuit, the first gain factor when the second gain factor is different than the predetermined value.

13. A mixed signal controller for a power quality compensator, comprising:
an analog circuit that filters an input signal from the power quality compensator by a first factor and outputs an analog signal;
an analog-to-digital converter (ADC) that converts the analog signal to a digital signal; and
a digital circuit that receives the digital signal from the ADC and generates a pulse width modulation (PWM) signal that triggers the power quality compensator,
wherein the digital circuit further includes a calculation circuit that calculates a second factor and sends the second factor to the analog circuit, the second factor represented by:





  G
  =
  
    INT
    ⁡
    
      (
      
        W
        R
      
      )
    
  



where INT is an integer function, W is a measured amplitude width of the digital signal out of the ADC, and R is a peak-to-peak range of the input signal,
wherein the analog circuit compares the second factor to a predetermined value and adjusts the first factor to decrease a system total harmonic distortion after the power quality compensator compensates power when the second factor is different than the predetermined value.

14. The mixed signal controller of claim 13, wherein the digital circuit further includes an evaluation circuit that calculates a value of the system total harmonic distortion after the power quality compensator compensates power by calculating an approximate total harmonic distortion (ATHD) by:




  ATHD
  =
  
    
      
        2
        3
      
    
    ⁢
    
      HB
      
        I
        
          1
          ⁢
          p
        
      
    
  



where I1p is a peak value of a sinusoidal current, and HB is a hysteresis band value that specifies a variation range of the current.

15. The mixed signal controller of claim 13, wherein the ATHD is dependent on a compensation error that is limited by the ADC.

16. The mixed signal controller of claim 13, wherein the ATHD is dependent on a value of the first factor.

17. The mixed signal controller of claim 13, wherein the analog circuit compares the second factor with a predetermined value and adjusts the first factor when the second factor is different than the predetermined value.