# Patent

## Title
Method and device for measuring changes over time of the electrical performance of an FDSOI transistor

## Abstract

A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps:

    
    
        measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas,
        determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1−1((Cmax+Cplat)/2) and VLower(0)=C1−1((Cmin+Cplat)/2),
        determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2−1((Cmax+Cplat)/2) and VLower(t1)=C2−1((Cmin+Cplat)/2),
        determination of variations of defect densities ΔDit1, ΔDit2 between the transistor's first and second states, at the transistor's front and back interfaces, from values ΔVUpper(t1)=VUpper(t1)−VUpper(0) and ΔVLower(t1)=VLower(t1)−Vlower(0).

## Background
TECHNICAL FIELD
The invention relates to a method and a device for measuring, or assessing, changes over time of the electrical performance of transistors of the FDSOI type, i.e. of fully depleted transistors of the semiconductor on insulator type.
The invention is used in particular to study the ageing of FDSOI transistors, by assessing changes over time, after a certain period of use, of the defect densities at the transistors' dielectric/semiconductor interfaces, since the electrical performance of the FDSOI transistors is directly dependent on the quality of these interfaces, and therefore on the defect densities present at these interfaces.
STATE OF THE PRIOR ART
An example of an FDSOI transistor 1 is represented in FIG. 1.
Transistor 1 is produced on a substrate of the SOI type including a semiconductor supporting layer, or substrate, 3, where the semiconductor may for example be silicon, on which are positioned a dielectric layer 5, for example comprising SiO2, forming a buried dielectric (BOX), and a layer of semiconductor, such as silicon, in which a channel area 7 and source 9 and drain 11 areas are formed, covering buried dielectric layer 5. Channel 7 is covered by a gate dielectric 13, for example comprising SiO2, on which a gate 15, for example comprising TiN, is positioned.
The electrical performance of such an FDSOI-type transistor 1 depends on the quality of its silicium/SiO2 interfaces, i.e. the interface between the portion of silicon intended to form channel 7 and gate dielectric 13, called the front interface, and the interface between the portion of silicon intended to form channel 7 and buried dielectric 5, called the back interface.
To assess the electrical performance of this transistor 1 the defect densities must be able to be measured and quantified at these front (Dit1) and back (Dit2) interfaces.
Document EP 2 290 386 A1 describes a method for assessing the electrical performance of such a FDSOI transistor, by means of a quantification of defect densities Dit1 and Dit2.
The electrical performance of an FDSOI transistor deteriorates over time as it is used; this deterioration leads to an increase of the transistor's defect densities Dit1 and Dit2. Although the method described by EP 2 290 386 A1 is effective in terms of the assessment made of the transistor's electrical performance, and could therefore be used to monitor changes in this performance over time, it is complex to implement, notably due to the complex model used to describe the electrical response of the transistor's interface states.
DESCRIPTION OF THE INVENTION
Thus there is a need to propose a method of measuring changes over time of the electrical performance of an FDSOI transistor which is less complex to implement.
To this end, one embodiment proposes a method of measuring the changes of the electrical performance of an FDSOI transistor positioned on a semiconductor substrate, between a first state and a second state of the transistor after an operating period t1, including at least the following steps:

    
    
        measurement of the transistor's capacities C1 and C2 respectively in the first and second states, by applying a voltage VBG>0 to the substrate when the transistor is of the NMOS type, or a voltage VBG<0 to the substrate when the transistor is of the PMOS type, according to a voltage VFG applied between a gate and source and drain areas of the transistor,
        determination, in relation to characteristic C1(VFG) measured varying between a maximum value Cmax and a minimum value Cmin, and including three consecutive inflection points, of an ordinate value Cplat of C1(VFG) at the second of the three inflection points of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) such that VUpper(0)=C1−1((Cmax+Cplat)/2) and VLower(0)=C1−1((Cmin+Cplat)/2),
        determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) such that VUpper(t1)=C2−1((Cmax+Cplat)/2) and VLower(t1)=C2−1((Cmin+Cplat)/2),
        determination of variations of defect densities ΔDit1, ΔDit2 between the transistor's first and second states, respectively at an interface between a gate dielectric of the transistor and a channel area of the transistor, and an interface between the channel area and a buried dielectric of the transistor, from values ΔVUpper(t1)=VUpper(t1)−VUpper(0) and ΔVLower(t1)=VLower(t1)−VLower(0).
    
    


Ordinate value Cplat of C1(VFG) can be determined by considering a portion of the transistor's characteristic C1(VFG) varying between maximum value Cmax and minimum value Cmin with a gradient of constant sign, and including at least the three consecutive inflection points.
Use of this method enables the deterioration over time of the transistor's electrical performance to be assessed through the assessment of the deterioration over time of the quality of the transistor's semiconductor/dielectric interfaces (i.e. by determining whether defect densities Dit1, Dit2 have changed over time in the transistor's semiconductor/gate dielectric front interface and/or gate semiconductor/gate dielectric back interface), by locating a possible variation of the number of defects created in the transistor's front interface and/or back interface, and possibly in quantifying these variations of the transistor's defect densities ΔDit1, ΔDit2 over operating period t1 in this or these front and back interfaces.
Compared to use of the method described in EP 2 290 386 A1 to measure the transistor's defect densities Dit1 and Dit2 in the first state, and then in the second state, after an operating period t1, this method requires no complex modelling of the transistor, thus reducing the computations to be made.
In addition, with this method, a single measurement of the transistor's capacities in the first and the second states is made.
This method can be used both for NMOS-type FDSOI and PMOS-type FDSOI transistors.
The value of ΔDit1 may be calculated using the following equation:




  
    Δ
    ⁢
    
      
    
    ⁢
    
      Dit
      1
    
  
  =
  
    
      
        ɛ
        ox
      
      
        q
        ·
        EOT
      
    
    ⁢
    Δ
    ⁢
    
      
    
    ⁢
    
      V
      Upper
    
  




where ∈ox: dielectric constant of the material of the transistor's gate dielectric,
EOT: equivalent oxide thickness of the gate dielectric,
q: elementary charge (q=1.6×10−19 C).
The value of ΔDit2 may be determined at least by using the following steps:

    
    
        calculation of the transistor's characteristics C(VFG) for different theoretical values of ΔDit2,
        calculation of the relation ΔVLower=f(ΔDit2) from previously calculated characteristics C(VFG),
        calculation of value ΔDit2=f−1(ΔVUpper(t1)−ΔVLower(t1)).
    
    


The transistor's characteristics C(VFG) for different theoretical values of ΔDit2 may be calculated by a Poisson-Schrödinger solver-type application from the values of the thickness of the semiconductor intended to form the transistor's channel, of the equivalent oxide thickness EOT of the transistor's gate dielectric, of voltages VBG and VFG applied to the transistor, of the thickness of the transistor's buried dielectric, and of the temperature of the environment in which the transistor is operating.
As a variant, the value of ΔDit2 may be determined by the following equation:




  
    Δ
    ⁢
    
      
    
    ⁢
    
      D
      
        it
        ⁢
        
          
        
        ⁢
        2
      
    
  
  =
  
    
      Δ
      ⁢
      
        
      
      ⁢
      
        V
        Lower
      
    
    
      (
      
        
          α
          ·
          
            t
            Si
          
        
        +
        
          β
          ·
          EOT
        
      
      )
    
  




Where α=1.25×10−4 mV·cm,
and β=4.5×10−4 mV·cm,
EOT: equivalent oxide thickness of the gate dielectric,
tSi: thickness of the semiconductor intended to form the transistor's channel.
In another variant, the value of ΔDit2 may be determined from a relation ΔVLower=f(ΔDit2) which is known for the transistor (for example by using an abacus for the type of transistor under study), by calculating value ΔDit2=f−1(ΔVUpper(t1)−ΔVLower(t1)).
Voltage VFG may include a direct current component, the value of which is between approximately −2 V and 2 V, and a sinusoid alternating component, the frequency of which may be between approximately 10 kHz and 100 kHz.
Voltage VBG may be a direct current voltage, the value of which may be between approximately 5 V and 10 V when the transistor is of the NMOS type, or between approximately −5 V and −10 V when the transistor is of the PMOS type.
The transistor's capacity C may be measured by an impedance analyser.
Another embodiment relates to a device for measuring the changes of the electrical performance of an FDSOI transistor, including means for implementing a method for measuring changes of the electrical performance of the FDSOI transistor as described above.



BRIEF DESCRIPTION OF THE ILLUSTRATIONS
The present invention will be better understood on reading the description of example embodiments given purely as an indication and in no way restrictively, making reference to the appended illustrations in which:
FIG. 1 represents a transistor of the FDSOI type,
FIG. 2 represents an example embodiment of a device for measuring changes of the electrical performance of an FDSOI transistor,
FIGS. 3A and 3B represent measurements of a characteristic C(VFG) of an FDSOI transistor produced during a method for measuring changes of the electrical performance of an FDSOI transistor,
FIGS. 4 to 12 represent different measurement and calculation curves plotted during use of a method for measuring changes of the electrical performance of an FDSOI transistor.



Identical, similar or equivalent portions of the various figures described below have the same numerical references, to make it easier to move from one figure to another.
The various portions represented in the figures are not necessarily represented at a uniform scale, in order to make the figures more readable.
The various possibilities (variants and embodiments) must be understood as not being mutually exclusive, and being able to be combined with one another.
DETAILED ACCOUNT OF PARTICULAR EMBODIMENTS
A method for measuring changes in the electrical performance of an FDSOI transistor, corresponding for example to FDSOI transistor 1 previously described in connection with FIG. 1, and which may be of the NMOS or PMOS type, is described below, enabling changes over time of the defect densities present at the front interface between gate dielectric 13 and the semiconductor of channel 7 (Dit1) and at the back interface between the semiconductor of channel 7 and buried dielectric 5 (Dit2) to be characterised.
This characterisation consists in locating the deterioration incurred by transistor 1, i.e. in determining whether additional defects have been generated at the dielectric/semiconductor front interface and/or back interface of transistor 1, and possibly in then calculating the quantities of defects ΔDit1 and/or ΔDit2 created over time by the operation of transistor 1 at these interfaces.
ΔDit1 is defined as being the difference between defect density Dit1(0) at the front interface of transistor 1 in a first state, corresponding for example to the initial state of transistor 1 (i.e. the state of transistor 1 when it has never been used) and defect density Dit1(t1) at the front interface of transistor 1 in a second state, i.e. its state after an operating period t1 since the first state, corresponding to ageing due to use during time period t1, such that:

ΔDit1=Dit1(t1)−Dit1(0)  (1)

Similarly, ΔDit2 is defined as being the difference between defect density Dit2(0) at the back interface of transistor 1 in its first state, corresponding for example to the initial state of transistor 1 (i.e. the state of transistor 1 when it has never been used) and defect density Dit1(t1) at the back interface of transistor 1 in its second state, i.e. its state after an operating period t1 since the first state, corresponding to ageing due to use during time period t1, such that:

ΔDit2=Dit2(t1)−Dit2(0)  (2)

This method is implemented by a device 100 for measuring the changes of the electrical performance of FDSOI transistor 1, represented in FIG. 2. Device 100 includes an impedance analyser 102, for example of the Agilent HP4184 type or equivalent, the High input of which is connected to gate 15, and the Low input of which is connected to source 9 and to drain 11 of transistor 1, together with calculation means 104 able to determine different values which will be described below. Calculation means 104 may notably include a computer.
In a first step of the method for measuring changes of the electrical performance of transistor 1, the capacity of transistor 1 is measured according to the value of a voltage VFG applied to gate 15, with a voltage VBG applied to the back face of transistor 1, i.e. to substrate 3. Voltage VBG is greater than 0 when transistor 1 is of the NMOS type, and is less than 0 when transistor 1 is of the PMOS type. In physical terms, this amounts in transistor 1 to separating the inversion of the channel in the front and back interfaces, i.e. in decorrelating the electrical response of the defects present in the front interface of transistor 1 in relation to that of the defects present in the back interface of transistor 1.
This measurement of capacity C of transistor 1 is made by electrically connecting source 9 to drain 11, applying voltage VFG between gate 15 and source 9, or between gate 15 and drain 11, and by applying voltage VBG to substrate 3 through a voltage source. This measurement of capacity C is made by impedance analyser 102.
The values of voltages VFG and VBG are chosen so as to obtain a curve C(VFG) including at least one portion which varies between a maximum value Cmax and a minimum value Cmin with a gradient of constant sign (positive or negative depending on whether transistor 1 is of the PMOS or NMOS type) and including three consecutive inflection points. Voltage VFG includes a direct current component, the value of which is made to vary, for example between approximately −2 V and +2 V, to make the measurement of capacity C of transistor 1, together with an alternating component of amplitude of, for example, between approximately 30 mV and 40 mV, and of frequency of, for example, between approximately 10 kHz and 100 kHz (in this case set at 100 kHz). VBG may typically be set so as to obtain an electric field Eox=VBG/Tox in buried dielectric 5 of between approximately 1 MV/cm and 4 MV/cm, where Tox is the thickness of buried dielectric 5. Thus, for a PMOS-type transistor 1 including a portion of silicon forming a channel 7 of thickness equal to approximately 7 nm, a buried dielectric 5 of thickness equal to approximately 25 nm and a gate dielectric 13 having an equivalent oxide thickness EOT of approximately 1.2 nm, VBG may be chosen independently within interval [−5 V, −10 V].
Curve 106 represented in FIG. 3A is the measurement made of capacity C of transistor 1 as a function of voltage VFG (where C is expressed in μF/cm2, and VFG is expressed in Volts) of transistor 1 in its first state, i.e. the defect densities of which at its front and back interfaces are Dit1(0) and Dit2(0), with VFG varying between 1.5 V and −2V. This curve 106 is called characteristic C1(VFG) of transistor 1.
By considering the variation of the value of C between VFG=1.5 V and VFG=−2 V (reading of curve 106 represented in FIG. 3A from right to left), it can be seen that curve 106 changes from minimum value Cmin at VFG equal to approximately 1.25 V, to maximum value Cmax at VFG equal to approximately −2 V, with a positive gradient. In this curve 106 a first rise can be observed (referenced 108 in FIG. 3A) of the value of C with VFG varying from approximately 1.25 V to 0.75 V. This first increase of the value of C corresponds to an accumulation occurring solely in the back interface of transistor 1, since the front interface of transistor 1 is depleted. With VFG varying between approximately 0.75 V and 0.25 V, the gradient of curve 106 declines, where this portion (referenced 110 in FIG. 3A) of curve 106 forms a “plateau”, or transition phase. Curve 106 then includes a second rise (referenced 112 in FIG. 3A) of the value of C with VFG varying between approximately 0.25 V and −2 V (with an increase of the gradient of curve 106 relative to portion 110), which this time corresponds to an accumulation occurring at the front interface of transistor 1, where the back interface is still accumulated, until the value of C reaches maximum value Cmax.
This curve 106 varies between a maximum value Cmax and a minimum value Cmin with a gradient of constant sign, and includes three consecutive inflection points, referenced 114, 115 and 116, and which are located respectively in portions 108, 110 and 112. Second inflection point 115 is located in “plateau” portion 110 of curve 106.
A value Cplat is defined as being the value of C at second inflection point 115, in the middle of “plateau” portion 110. Abscissa values VLower(0) and VUpper(0) of characteristic C1(VFG) are then defined as being the values of VFG at values (Cmin+Cplat)/2 and (Cmax+Cplat)/2, which correspond approximately to the values of VFG at first inflection point 114 and at second inflection point 116. We therefore have:

VUpper(0)=C1−1((Cmax+Cplat)/2)  (3)

VLower(0)=C1−1((Cmin+Cplat)/2)  (4)

In the case of an NMOS-type transistor, an identical analysis of characteristic C1(VFG) would be made by reading the corresponding curve from left to right, for example by considering the variation of the value of C between −0.5 V and 2 V, as represented in FIG. 3B. VBG is in this case positive. In this case the curve has a gradient of positive sign when considering the change of the value of C from VFG−1.25 V to VFG=2 V.
Values VUpper(0) and VLower(0) are, for example, calculated by calculation means 104 from data supplied by impedance analyser 102.
A similar measurement of capacity C is then made according to voltage VFG of the same FDSOI transistor 1, but in its second state, i.e. after a certain operating period t1. The defect densities at its front and back interfaces are called Dit1(t1) and Dit2(t1). The value of VBG and the range of values of VFG applied to transistor 1 during this measurement are similar to those applied during the previous measurement of characteristic C1(VFG). This measurement enables characteristic C2(VFG) of transistor 1 to be obtained.
Characteristics C1(VFG) and C2(VFG) obtained are then compared to one another (see FIG. 4: curve 106 corresponds to characteristic C1(VFG) of transistor 1 in its first state, and curve 118 corresponds to characteristic C2(VFG) of transistor 1 in its second state, i.e. after a period of use t1). In a manner comparable to the calculation of values VUpper(0) and VLower(0) made previously from characteristic C1(VFG), values VUpper(t1) and VLower(t1) are calculated from characteristic C2(VFG) such that:

VUpper(t1)=C2−1((Cmax+Cplat)/2)  (5)

VLower(t1)=C2−1((Cmin+Cplat)/2)  (6)

Values VUpper(t1) and VLower(t1) can be calculated from values Cmin, Cplat and Cmax which were previously determined from C1(VFG). It is also possible to recalculate Cmin, Cplat and Cmax from C2(VFG) if differences of value are observed between those of C1(VFG) and those of C2(VFG).
It is then possible to calculate, in analytical fashion from values VUpper(t1), VUpper(0), VLower(t1) and VLower(0), or in graphical fashion from plotted curves 106 and 118, the variations of values VUpper and VLower between the transistor's first and second states, such that:

ΔVUpper(t1)=VUpper(t1)−VUpper(0)  (7)

ΔVLower(t1)=VLower(t1)−VLower(0)  (8)

From these values ΔVUpper(t1) and ΔVLower(t1), it is then possible to locate the deterioration incurred by transistor FDSOI 1, i.e. to determine whether additional defects have been produced at the dielectric/semiconductor front interface and/or back interface of transistor 1.
In a first case, if ΔVUpper(t1)≈ΔVLower(t1), this means that defects have been created only in the front interface of transistor 1 (which reflects the fact that |ΔDit1|>0 and ΔDit2≈0). This case corresponds to characteristics C1(VFG) and C2(VFG), referenced respectively 106 and 118, represented in FIG. 5. It can be seen in this figure that characteristic C2(VFG) 118 of transistor 1 obtained after a period of use t1 of the transistor is offset by a constant value in parallel to the axis of the abscissae, compared to the transistor's characteristic C1(VFG) 106 in its first state.
In a second case, if ΔVUpper(t1)≈0 and ΔVLower>0, this means that defects have been created only on the back interface of transistor 1 (which reflects the fact that |ΔDit2|>0 and ΔD1t1≈0). This case corresponds to characteristics C1(VFG) 106 and C2(VFG) 118 represented in FIG. 6. This dissymmetry between ΔVUpper(t1) and ΔVLower(t1) is explained by a physical phenomenon of screening of the charges at the back interface by free carriers (holes) accumulated in the silicon layer when −2 V<VFG<0.2 V. This screening does not occur when 0.2 V<VFG<1 V, when the majority of the silicon layer is depleted.
Finally, in a third case, if ΔVUpper(t1)≠0 and |ΔVUpper(t1)|<|ΔVLower(t1)|, this means that defects have been created at both front and back interfaces of transistor 1 (which reflects the fact that |ΔDit1|>0 and |ΔDit2|>0). This case corresponds to characteristics C1(VFG) 106 and C2(VFG) 118 represented in FIG. 4.
Thus, depending on the values of ΔVUpper(t1) and ΔVLower(t1), the defects created at one or both of the semiconductor/dielectric interfaces of an FDSOI transistor can be located after the transistor has been used.
From the measurements and calculations previously made to locate the created defects, quantities ΔDit1 and ΔDit2 of defects generated by the use of transistor 1 during operating period t1 can be calculated.
Thus, when ΔVUpper(t1)≠0 (first and third cases described above), the value of ΔDit1 is calculated from the following formula:




  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            Dit
            1
          
        
        =
        
          
            
              ɛ
              ox
            
            
              q
              ·
              EOT
            
          
          ⁢
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            Upper
          
        
      
    
    
      
        (
        9
        )
      
    
  




where ∈ox: dielectric constant of the material of gate dielectric 13 (equal to 3.45×10−11 F/m2 for SiO2),
EOT: equivalent oxide thickness of gate dielectric 13,
q: elementary charge.
To calculate ΔDit2, previously obtained curve 106 (corresponding to characteristic C1(VFG) of transistor 1 in its first state) and another curve, referenced 120 in FIG. 7, representing the values of the transistor's capacity C in its second state, but depending on VFG−ΔVUpper(t1), are first plotted in the same graph. Curve 120 therefore corresponds to characteristic C2(VFG) (curve 118) offset, in parallel with the axis of the abscissae, by the value of ΔVUpper(t1). At value C=(Cmax+Cplat)/2, the offset between curves 106 and 120 is therefore zero. At value C=(Cmin+Cplat)/2, the offset between curves 106 and 120 is therefore equal to ΔVLower(t1)−ΔVUpper(t1). This offset ΔVLower(t1)−ΔVUpper(t1) is related solely to the creation of defects at the back interface, i.e. to variation ΔDit2, given that offset ΔVUpper(t1) is caused only by ΔDit1.
However, value ΔVLower(t1)−ΔVUpper(t1) can be calculated directly from previously calculated values ΔVLower(t1) and ΔVUpper(t1), without having to plot the curves represented in FIG. 7.
An application of the Poisson-Schrödinger solver type, for example the SCHRED software, is then used, enabling the Poisson equation to be resolved in an SOI-type structure in accordance with the parameters of the structure and the measuring conditions, such that:




  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          V
        
        =
        
          -
          
            ρ
            ɛ
          
        
      
    
    
      
        (
        10
        )
      
    
  




The input parameters of this application are: thickness tSi of the portion of silicon forming channel 7 of transistor 1, equivalent oxide thickness EOT of gate dielectric 13 of transistor 1 (where the calculation of the EOT of a transistor is described, for example, in document EP 1 591 558), the thickness of buried dielectric 5 tBox, the values of voltages VBG and VFG, the transistor's operating temperature and a value of back interface states density Dit2.
Equation (10) is firstly resolved, for an applied voltage VFG which is constant over time (pulse ω of the sinusoid alternating component of VFG is in this case zero), and a constant value of interface states density Dit2.
From these input parameters, the application can then calculate the concentration of electrons n(x) and of holes p(x) and the potential ψ(x) at depth x in the portion of silicon intended to form the channel, where this depth is between 0 and TSi.
It is then possible to calculate the integrated charges of holes Qh and electrons Qe given respectively by the following equations:




  
    
      
        
          Q
          h
        
        =
        
          e
          ⁢
          
            
              ∫
              0
              Tsi
            
            ⁢
            
              
                p
                ⁡
                
                  (
                  x
                  )
                
              
              ⁢
              
                
              
              ⁢
              
                d
                x
              
            
          
        
      
    
    
      
        (
        11
        )
      
    
  
  
    
      
        
          Q
          e
        
        =
        
          e
          ⁢
          
            
              ∫
              0
              Tsi
            
            ⁢
            
              
                n
                ⁡
                
                  (
                  x
                  )
                
              
              ⁢
              
                
              
              ⁢
              
                d
                x
              
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




Total charge Qtot in the portion of silicon is then equal to:

Qtot=Qdep+Qh+Qe+eDit2  (13)

where e is the elementary electrical charge of an election and Qdep the depletion charge equal to e·Ndop Tsi, and where Ndop is the dopant concentration.
By repeating this resolution for different voltage values VFG and for the same fixed value of Dit2, capacity C(VFG) is obtained by simple derivation with respect to voltage VFG:




  
    
      
        
          C
          ⁡
          
            (
            
              V
              FG
            
            )
          
        
        =
        
          -
          
            
              d
              
                Q
                tot
              
            
            
              d
              
                V
                FG
              
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




Finally, by resolving this equation for different theoretical values of ΔDit2, the transistor's characteristic C(VFG) for the different values of ΔDit2 is obtained (see curves 106, 122, 124 and 126 represented in FIG. 8, corresponding to the characteristics C(VFG) of transistor 1 respectively for the theoretical values of ΔDit2 equal to 0, 1×1012, 2×1012 and 3×1012 cm−2). By measuring the differences ΔVLower between characteristic C(VFG) of transistor 1 in its first state (corresponding to curve 106 represented in FIG. 8, and which corresponds to ΔDit2=0) and each of the previously calculated characteristics C(VFG), i.e. the differences of the abscissa values between characteristic C(VFG) of transistor 1 in its first state and each of the other calculated characteristics C(VFG), at ordinate value (Cmin+Cplat)/2, the relation between ΔVLower and ΔDit2 can be determined (see FIG. 9, in which relation ΔVLower is represented, in mV, as a function of ΔDit2/in cm−2, for the following parameters: tSi=7 nm; tBox=25 nm; EOT=1.2 nm). This relation can be obtained by choosing several values, for example ten, of ΔDit2 within the range [1010 cm−2; 5×1012 cm−2].
By then plotting previously calculated value ΔVLower(t1)−ΔVUpper(t1) on the curve representing the relation ΔVLower=f(ΔDit2) represented in FIG. 9, a precise value of ΔDit2 is obtained for transistor 1 representing the variation, after an operating period of the defects density at the back interface of transistor 1. We therefore have:

ΔDit2=f−1(ΔVUpper(t1)−ΔVLower(t1))  (15)

To avoid having to implement the calculation steps enabling the relation ΔVLower=f(ΔDit2) to be determined each time this method is used, abacuses ΔVLower=f(ΔDit2) can be used for habitual values of tSi, tBox and EOT of different FDSOI transistors. Examples of VLower=f(ΔDit2) abacuses for different values of tSi, tBox and EOT are represented in FIGS. 10, 11 and 12:

    
    
        FIG. 10: ΔVLower=f(ΔDit2) for different values of tSi (5 nm, 7 nm, 10 nm and 20 nm), EOT=1.2 nm, and tBox=10 nm or 25 nm or 145 nm,
        FIG. 11: ΔVLower=f(ΔDit2) for different values of tSi (5 nm, 7 nm, 10 nm, 15 nm and 20 nm), EOT=1 nm, and tBox=25 nm,
        FIG. 12: ΔVLower=f(ΔDit2) for different values of tSi (5 nm, 7 nm, 10 nm, 15 nm and 20 nm), EOT=2 nm, and tBox=25 nm.
    
    


As a variant, the value of ΔDit2 can be calculated from the following relation:

ΔVLower=(α·tSi+β·EOT)ΔDit2  (16)

Where α=1.25×10−4 mV·cm−3,
and β=4.5×10−4 mV·cm−3.
In the method described above, the change over time of the electrical performance of FDSOI transistor 1 between its initial state, i.e. when it has never operated, and a second state of this transistor after an operating period t1, has been measured. This method can also be used to assess the change over time of the electrical performance of an FDSOI transistor between a first state of the transistor, corresponding to its state after an operating period t2, and a second state of this same transistor after an operating period t3, where t3>t2.

## Claims

1. A method of measuring the changes of the electrical performance of an FDSOI transistor positioned on a semiconductor substrate, between a first state and a second state of the transistor, after an operating period t1, including at least the following steps:
using a capacitance measuring device to measure the transistor's capacitance C1 and C2 respectively in the first and second states, by:
applying a voltage VBG>0 to the substrate when the transistor is of the NMOS type, or a voltage VBG<0 to the substrate when the transistor is of the PMOS type, wherein application of VBG to the substrate decorrelates the electrical response of defects present in a front interface of the transistor in relation to the electrical response of defects present in a back interface of the transistor and voltage VBG is a direct current voltage, the value of which is between approximately 5 V and 10 V when the transistor is of the NMOS type, or between approximately −5 V and -10 V when the transistor is of the PMOS type, and
connecting a first lead of the capacitance measuring device to a gate of the transistor, and
connecting a second lead of the capacitance measuring device to the source and drain area of the transistor, such that a voltage VFG from the capacitance measuring device is applied between the gate, and the source and drain areas of the transistor;

determining, in relation to characteristic C1(VFG) measured varying between a maximum value Cmax and a minimum value Cmin, and including three consecutive inflection points, of an ordinate value Cplat of C1(VFG) at the second of the three inflection points of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1−1((Cmax+Cplat)/2) and VLower(0)=C1−1((Cmin+Cplat/2),
determining, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2−1((Cmax+Cplat)/2) and VLower(t1)=C2−1((Cmin+Cplat)/2), and
determining variations of defect densities ΔDit1, ΔDit2 between the transistor's first and second states, respectively at an interface between a gate dielectric of the transistor and a channel area of the transistor, and an interface between the channel area and a buried dielectric of the transistor, from values ΔVUpper(t1)=VUpper(t1)−VUpper(0) and ΔVLower(t1)=VLower(t1)−VLower(0).

2. The method according to claim 1, in which the value of ΔDit1 is calculated according to the following equation:




  
    Δ
    ⁢
    
      
    
    ⁢
    
      Dit
      1
    
  
  =
  
    
      
        ɛ
        ox
      
      
        q
        ·
        EOT
      
    
    ⁢
    Δ
    ⁢
    
      
    
    ⁢
    
      V
      Upper
    
  



where ∈ox: dielectric constant of the material of the gate dielectric,
EOT: equivalent oxide thickness of the gate dielectric,
q: elementary charge.

3. The method according to claim 1, in which the value of ΔDit2 is determined at least by the implementation of the following steps:
calculating the characteristics C(VFG) of the transistor for different theoretical values of ΔDit2,
calculating the relation ΔVLower=f(ΔDit2) from previously calculating value ΔDit2=f−1(ΔVUpper(t1)·ΔVLower(t1)).

4. The method according to claim 3, in which the characteristics C(VFG) of the transistor for different theoretical values of ΔDit2 are calculated by a Poisson-Schrödinger solver-type application from the values of the thickness of the semiconductor intended to form the transistor's channel, of the equivalent oxide thickness EOT of the gate dielectric of the transistor, of voltages VBG and VFG applied to the transistor, of the thickness of the buried dielectric tBox of the transistor, and of the temperature of the environment in which the transistor is operating.

5. The method according to claim 1, in which the value of ΔDit2 is determined by the following equation:




  
    Δ
    ⁢
    
      
    
    ⁢
    
      D
      
        it
        ⁢
        
          
        
        ⁢
        2
      
    
  
  =
  
    
      Δ
      ⁢
      
        
      
      ⁢
      
        V
        Lower
      
    
    
      (
      
        
          α
          ·
          
            t
            Si
          
        
        +
        
          β
          ·
          EOT
        
      
      )
    
  



Where α=1.25×10−4 mV·cm,
and β=4.5×10−4 mV·cm,
EOT: equivalent oxide thickness of the gate dielectric,
tSi: thickness of the semiconductor intended to form the channel of the transistor.

6. The method according to claim 1, in which the value of ΔDit2 is determined, from a relation ΔVLower=f(ΔDit2) which is known for the transistor, by calculating value ΔDit2=f−1(ΔVUpper(t1)−ΔVLower(t1)).

7. The method according to claim 1, in which voltage VFG includes a direct current component, the value of which is between approximately −2 V and 2 V, and a sinusoid alternating component, the frequency of which is between approximately 10 kHz and 100 kHz.

8. The method according to claim 1, in which capacitance C of the transistor is measured by an impedance analyser.

9. A device for measuring the changes of the electrical performance of an FDSOI transistor, including means for implementing a method for measuring changes of the electrical performance of the FDSOI transistor according to claim 1.