# Patent

## Title
Programmable analog and mixed mode circuit emulation system

## Abstract

A programmable circuit and emulation system is used to emulate the behavior of analog and mixed mode circuit. The emulation preserves circuit electrical behavior while operating at a lower frequency than an intended frequency of the original circuit. The emulation system comprises an emulation hardware that includes control circuit, function groups, on chip function generation circuit, on chip measurement circuit and on chip characterization circuit and all are connected through programmable interconnect. Each function group comprises of transistor arrays or programmable passive devices, each transistor array or programmable passive device is connected to others through local programmable interconnect. Each transistor array or programmable passive device can be programmed to match the behavior of a transistor or passive device in the circuit to be emulated.

## Background
FIELD OF INVENTION
The present invention refers to an analog and mixed mode circuit emulation system and a programmable analog and mixed mode circuit, and more specifically, the system can be programmed to emulate the behavior of an analog and mixed mode circuit.
BACKGROUND
User programmable devices, such as PLDs and FPGAs, have been known for decades. These devices, which are useful for fast prototyping, emulation, and reconfigurable systems, are used predominantly for digital circuits and constructed by a plurality of logic cells at the gate level. The cells are connected with one another through user-programmable interconnections.
One of the applications of programmable devices is circuit emulation. Devices such as FPGAs can emulate the behavior of a digital circuit at a speed that is tens or hundreds times faster than that of digital logic simulation software. Circuit emulation plays a vital role in verifying the functionality of large digital systems. An emulation system using PLDs or FPGAs emulates digital circuits, as described, for example, in U.S. Pat. No. 7,356,454, U.S. Pat. No. 6,842,729, and U.S. Pat. No. 7,348,827.
Unlike digital circuits, whose operations are based on a limited number of logic values (e.g., 0, 1), analog circuits operate based on voltages and currents, and each of these quantities may have any of an infinite number of values at any given time. Analog circuits can have digital or analog inputs and outputs but the internal signals contain analog signals. Digital signals can also reside within the analog circuit. A “mixed mode circuit” contains both analog and digital circuit blocks.
In the analog domain, most analog circuits are custom designed. Analog designs are typically verified with a circuit simulation software, such as a SPICE simulator. Analog circuit simulation is much slower than digital circuit simulation, and there has been no significant advancement in analog circuit design technique and circuit simulation technology over the past 30 years. The custom circuit design processes often require many re-design cycles for circuit verification and optimization. Once a mistake is made and corrected, a new verification cycle has to be performed through wafer fabrication, package substrate fabrication, assembly operation, and design verification, the combination of which could take months to complete. If multiple redesigns occur and a verification cycle is completed for each redesign, the iterations can take years to complete. Due to the slow speed of circuit simulation, many analog and mixed mode circuit designs either take too long to design or enter the manufacturing phase without being fully verified or optimized. As a result, there are more missed market opportunities, circuit functional failures, or losses of product yield than there should be.
Prior efforts in programmable analog circuits focused on using predefined analog function blocks connected through programmable interconnection networks. The predefined analog function blocks can be operational amplifier, comparator, analog-to-digital converter, digital-to-analog converter, voltage reference, filter and others. These circuits can provide programmability and controllability of analog circuits for specific applications with pre-defined analog building blocks. Examples that reflect this type of effort are presented in U.S. Pat. No. 7,280,058, U.S. Pat. No. 6,910,126, U.S. Pat. No. 6,724,220, U.S. Pat. No. 6,910,126, U.S. Pat. No. 6,728,666, U.S. Pat. No. 6,424,209, U.S. Pat. No. 5,677,691, U.S. Pat. No. 5,563,526. None of these references describe a user-programmable analog circuit emulation system. For example, some of these references may solve the connectivity issue of the fully programmable analog circuit without addressing the programmability of circuit element characteristics.
A problem with user-programmable analog circuit using predefined analog function blocks is that it is not suitable for circuit emulation since the circuit can not match arbitrary circuit element characteristic and circuit topology. Furthermore, this type of circuit is intended to run circuit at-speed, which usually means the circuit runs at too high of a speed to measure circuit behavior accurately. Also, the high resistance values in switches interfere with accurate analog circuit emulation. In more detail, a fully programmable analog circuit uses a network of switches to connect the circuit elements. A MOS transistor requires three switches (at its drain, gate and source terminals) and sometimes additional switches to connect to other transistors (see U.S. Patent Application No. 2006/0261846 and U.S. Pat. No. 6,728,666). Most switches used in existing programmable digital and analog circuits are of minimum channel length and width to minimize parasitic effect and area usage. However, such switches have high resistance values. While the high resistance values may be acceptable in digital circuit emulation since digital circuit emulation mainly emulates logic “0” and “1” state, they will greatly affect the functionality of analog circuit emulation since an analog circuit operation requires higher precision and accuracy.
For the above reasons, there is currently an unfulfilled need for a fully user-programmable analog and mixed mode circuit and an analog and mixed mode circuit emulation system.
SUMMARY
In light of the above, the invention provides a fully programmable system which can emulate the behavior of analog and mixed mode circuits. By using the invention in combination with existing digital emulation system, an entire system with digital and analog circuit elements can be emulated.
In one aspect, the invention is an analog and mixed mode circuit emulation system that emulates analog and mixed mode circuit electrical behavior of an original circuit. The emulation system includes a control circuit and an emulation circuit controlled by the control circuit. The emulation circuit includes programmable function groups that are connected to each other in an interconnection network, wherein the function groups are capable of matching one or more electrical behaviors of the original circuit at a lower frequency than an intended frequency of the original circuit.
In another aspect, the invention is a transistor array that is capable of matching the threshold voltage and current of a transistor in an original circuit. The transistor array includes an array of transistors, each transistor having a drain terminal, a source terminal, a gate terminal, and switches at the source, drain and gate terminals. The transistor array is capable of being configured to match different transistor characteristics. Each transistor has an individually-controlled threshold voltage and each transistor is turned on/off independently of other transistors.
In yet another aspect, the invention is a method of emulating an original circuit that has analog components. The method entails matching one or more electrical behaviors of the original circuit at a lower frequency than an intended operating frequency of the original circuit.
Other features and aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, the features in accordance with embodiments of the invention. The summary is not intended to limit the scope of the invention, which is defined solely by the claims attached hereto.



DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of an emulation system in accordance with one embodiment of the invention.
FIG. 2 is a schematic diagram of the emulation hardware in FIG. 1.
FIGS. 3A, 3B, 3C, 3D, and 3E are diagrams of a basic switch and different embodiments of the switch in the emulation system.
FIG. 3F depict relative values of voltages used to operate the switches shown in FIGS. 3A, 3B, 3C, 3D, and 3E.
FIG. 3G shows current-voltage (I-V) curves for devices in FIGS. 3A, 3B, 3C, 3D and 3E.
FIG. 4A shows an embodiment of the function group in the emulation system of the invention.
FIG. 4B and FIG. 4C show different embodiments of the functional group in the emulation system of the invention.
FIGS. 5A, 5B, and 5C each shows another embodiment of the function group in the emulation system of the invention.
FIGS. 6A and 6B show schematic of an amplifier circuit and its construction by the function group (FG).
FIGS. 6C and 6D show different embodiments of the functional group in the emulation system of FIGS. 6A and 6B.
FIGS. 7A, 7B, 7C, and 7D show possible architectures of function groups that include programmable passive devices.
FIG. 8, is an exemplary embodiment of the transistor array (TA), which includes transistors and switches.
FIG. 9, shows the IV (current-voltage) curves of the original transistor and IV curves of the emulation result.
FIGS. 10A, 10B, 10C, and 10D are diagrams depicting different embodiments of the on-chip function generation circuit.
FIGS. 11A, 11B, 11C, and 11D are diagrams depicting different embodiments of on chip measurement circuit.
FIG. 12 shows the architecture of the on chip characterization circuit.
FIG. 13 shows full chip emulation system with the analog/mixed mode emulation system and digital emulation system working together.



DETAILED DESCRIPTION
In the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is understood that other embodiments may be utilized and mechanical, compositional, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is not to be taken in a limiting sense, and the scope of the embodiments of the present invention is defined only by the claims of the issued patent.
Some portions of the detailed description which follows are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that can be performed on computer memory. Each step may be performed by hardware, software, firmware, or combinations thereof.
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, “emulated circuit” or “original circuit” refers to the circuit that the system of the invention emulates. “Emulated transistors” refer to transistors in the emulated/original circuit. A “minimum-resistance switch” refers to a switch that has a resistance below about 500Ω.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
The emulation system of the invention emulates circuit behavior at a lower speed than the speed of the emulated circuit while preserving the intended circuit behavior. In a logic emulation system, the intent is to preserve the circuit logic behavior. In an analog and mixed mode emulation system of the invention, the intent is to preserve circuit electrical behavior, such as voltages and currents. The circuit is scaled or transformed such that some circuit elements are larger than the emulated circuit elements. By increasing the size of the circuit elements, the emulation errors due to switches and interconnection parasitic can be greatly reduced. By operating the circuit at a lower speed, the measurement accuracy of circuit behavior is improved. In one aspect, the invention is an analog and mixed mode emulation system that can emulate and verify the behavior of an arbitrary circuit.
The switch used in the interconnection network presents a major challenge in analog circuit emulation due to the high resistance in the switch. Previous approaches utilized regular threshold voltage transistors with minimum channel length and width. In contrast, an emulation system according to the present invention uses low threshold or zero threshold voltage or CMOS transistors with large channel width, which can provide low resistance when turned on and have low leakage when turned off. Although a larger switch creates a larger parasitic, any undesired effect from the parasitic is minimized when the circuit elements are much larger than the switches.
The programmable elements in the emulation circuit, such as a transistor array or programmable passive devices, are capable of being programmed to match the behavior of given circuit elements. The transistor array contains transistors with different channel lengths and widths and with different substrate connections. One or more transistors in the transistor array emulate threshold voltage and current characteristics of an original transistor. For example, the threshold voltage can be programmed by selecting transistors with threshold voltages close to target threshold voltage and fine tuned to the target threshold voltage by adjusting substrate bias voltage or using other methods. The target transistor current can likewise be programmed by turning on one or more transistors in the transistor array. After programming, the transistor array has similar threshold voltage and current as the emulated transistor but with a larger channel length and width. The programmable passive devices include resistors, capacitors and inductors. After programming, the resistors should have similar values as the resistors in the emulated circuit; likewise, the capacitors and inductors will have a larger value than the emulated elements.
As described in more detail below, the emulation circuit contains an on-chip function generation circuit which can generate DC and AC voltages and currents. The emulation circuit also contains an on-chip measurement circuit which can measure voltages and currents in the emulation circuit and store the data in memory to be sent back to a processor for post processing and display. The emulation circuit also contains an on-chip characterization circuit which can be characterized with the on-chip function generation circuit and on-chip measurement circuit or be characterized with external devices.
Reference is now made in detail to embodiments of the invention, a programmable mixed analog/digital circuit architecture and emulation system, examples of which are illustrated in the accompanying drawings. While the invention is described in conjunction with the embodiments, it will be understood that the invention is not limited to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the claims.
FIG. 1 is a schematic diagram of an emulation system 100 in accordance with one embodiment of the invention. The emulation system 100 includes a processor 103, a memory 104, an input device 101, an output device 102, and an emulation hardware 108. An emulation software 105 resides in the memory 104. The emulation hardware includes a control circuit 106 and at least one emulation circuit 107. The emulation system 100 is controlled by the emulation software 105. When a user specifies the circuit to be emulated, the emulation software 105 configures the emulation hardware 108 to match the topology and characteristics of the emulated circuit. The emulation software 105 then configures the emulation hardware 108 to reproduce the input, to monitor and to record the circuit behavior, and to store the circuit behavior in the memory 104. The emulation software 105 analyzes and/or displays the results. Although FIG. 1 shows three emulation circuits 107, any suitable number of emulation circuits may be used.
FIG. 2 is a schematic diagram of the emulation hardware 108 in FIG. 1. As shown, the emulation hardware 108 includes the control circuit 106 and at least one emulation circuit 107. The emulation circuits 107 are controlled by the control circuit 106, which transmits control signals via data buses 203, 204, 205, 206. In this embodiment, each emulation circuit 107 is of a specific process technology, process corner, and/or transistor option. Hence, the more emulation circuits 107 there are in the emulation system 100, the more flexibility the system will have in terms of the different kinds of circuit designs it can emulate.
The emulation circuit 107 includes an on-chip function generation circuit 207, an on-chip measurement circuit 208, an on-chip characterization circuit 209, and a control register 210 in addition to an interconnection network and a function group array 211. The interconnection network includes interconnection wires 213 and switches 214 that connect programmable function groups 212 of the function group array 211. The programmable function groups 212 can match the circuit topology and characteristic of a function block in the original circuit. The function groups 212 are connected through a network of interconnection wires 213 and switches 214 to form the complete circuit. Each of the switches 214 is an NMOS transistor, a PMOS transistor, or both (i.e., a CMOS transistor) having the lowest threshold voltage in a given process technology, which is typically a voltage between 0.15 V to near zero or slightly below zero (e.g., −0.1 V) for an NMOS transistor and between −0.15 V to slightly above zero (e.g., 0.1 V) for a PMOS transistor. Each of the switches 214 can also be a CMOS transistor, which comprises both NMOS and PMOS transistors. The CMOS switch does not require a low threshold voltage as the single NMOS or PMOS switch.
The on-chip function generation circuit 207 provides input to the emulated circuit. The functional generation circuit 207 generates AC and DC voltages and currents, as will be explained in more detail in reference to FIGS. 10A, 10B, 10C and 10D below. The on-chip measurement circuit 208 can measure and store the outputs of the emulated circuit. The measurement circuit measures voltages and currents in the emulation circuit, as will be explained in more detail in reference to FIGS. 11A, 11B, 11C, and 11D below. The on-chip characterization circuit 209 is used to characterize the behavior of the basic elements, such as Bipolar Junction Transistor (BJT), MOS transistor, capacitor, resistor and inductor used in the emulation circuit 107. The characterization circuit includes all the different transistor arrays and programmable passive devices in the emulation circuit 107.
The interconnection network connecting the function groups 212 includes wires 213 and switches 214. The switches 214 can be NMOS, PMOS or CMOS (NMOS and PMOS) pass transistors with regular threshold voltage, low threshold voltage, zero threshold voltage, native transistor or depletion transistor.
FIG. 3A shows a symbolic representation of an NMOS switch 301. FIG. 3B shows an NMOS switch 301 having a drain 302, a gate 303, a source 304 and a substrate 305. FIGS. 3C, 3D, and 3E are diagrams of different embodiments of the switch 301 that is incorporated into the switch 214 of the emulation system 100.
FIG. 3F shows the relative voltage values that affect the function of the switch 301, such as Vgate_on voltage 308, Vdd 306, GND 307, and Vgate_off 309. When the gate voltage (Vgate_on 308) is above the regular supply voltage Vdd 306, the switch 301 is turned on. When the switch 301 is turned on, it provides maximum drive to the transistor and has minimum transistor resistance. When the gate voltage (Vgate_off 309) of the NMOS switch is below GND 307, the NMOS switch 301 is turned off. The substrate voltage (Vgate_off 309) of the NMOS switch 301 is below GND 307 to increase the threshold voltage and reduce the leakage current.
Most MOS transistors cannot operate at a voltage much higher than their intended operating voltage for an extended period of time without causing long term reliability issues. Hence, the voltage Vgate_on 308 cannot be much higher than the intended operating voltage Vdd 306. To ensure that the NMOS switch has a low resistance when operating at a high voltage, the threshold voltage of the NMOS switch 301 is preferably made as low as possible.
The selection of a MOS element for a switch depends on the process technology. The selection of the transistor is to achieve minimum resistance when the transistor is turned on while consuming minimum area. Special circuit technique is needed to reduce leakage current when the switch is turned off. If a higher threshold voltage transistor is used, the emulation accuracy may be adversely affected due to higher resistance in the switch and the threshold voltage itself. In a preferred embodiment of the invention, the switch selection includes either a zero threshold voltage transistor or a native NMOS transistor and/or a CMOS transistor.
FIG. 3C shows a MOS transistor 313 having four terminals: a substrate terminal 317, a drain terminal 314, a gate terminal 315, and a source terminal 316. The substrate terminal 317 is normally connected to a power supply, ground or a bias voltage. For maximum connectivity, the drain terminal 314, the gate terminal 315, and the source terminal 316 of the transistor 313 connect to interconnection network via a switch, such as a drain switch 311, a source switch 310 and a gate switch 312.
The switches may degrade emulation accuracy due to the voltages across the switches; however, the effect on accuracy is not the same for all switches. FIG. 3G shows the I-V curve 319 of an emulated transistor, the I-V curve 320 with the drain switch 311, the I-V curve 321 with the source switch 310 and the I-V curve 322 with the gate switch 312. As shown in FIG. 3G, the source switch 310 causes the largest error (see curve 321) and the drain switch 311 causes the second largest error (see curve 320). The gate switch 312, on the other hand, has little effect on accuracy as seen in the curve 322. Typically, the most important region of operation for a MOS transistor in an analog circuit is the saturation region where the transistor has the highest gain and largest resistance. The simplified transistor current equation is:

Ids=β/2(Vgs−Vt)2(1+λVds),

wherein Vgs is the voltage difference between the gate and the source, Vt is the threshold voltage, and Vds is the voltage difference between the drain and the source.
The error in the curve 321 caused by the source switch 310 is a reduction of the overdrive voltage (Vgs−Vt), and the effect is large and quadratic. The error in the curve 320 caused by the drain switch 311 is a reduction of Vds, since the switch resistance is relatively small compared to that of the transistor and the effect is small and linear. The MOS transistor has a high gate input resistance compared to the resistance of the switch, and hence the error in the curve 322 caused by the gate switch 312 is negligible. If the resistance of the switch were made very small by increasing the channel width of the transistor, then the errors caused by the gate switch 312, the drain switch 311, and the source switch 310 would be small. However, when the emulation circuit requires millions of switches to program and connect the circuit, the switch system could become large enough to be prohibitively expensive.
Although the source switch 310 causes the largest error, the resistance at the source terminal 316 actually emulates the short channel effect due to velocity saturation in the MOS transistor. Thus, a switch at the source terminal 316 is also desirable to emulate other transistor behaviors. When the source switch 310 is used, the transistor current is smaller but the current can be increased by increasing the transistor width. Based on the above observations, it is preferable for the system of the invention to have either no switch or one switch at the source terminal 316 and minimum number of drain switches 311. The gate switch 312 is used as a main means for interconnection to emulate transistor behavior.
FIGS. 3C, 3D, and 3E show three possible switch configurations of the invention. In the first configuration (shown in FIG. 3C), the source switch 310, the drain switch 311 and the gate switch 312 are turned on and off by fixed voltages Vgate_on 308 and Vgate_off 309. This configuration results in the I-V curve 324. In the second configuration (shown in FIG. 3D), there is no switch at the source terminal 316 and the drain switch 311 and gate switch 312 are turned on and off by fixed voltages Vgate_on 308 and Vgate_off 309. This second configuration produces the I-V curve 320. In the third configuration (shown in FIG. 3E), the drain switch 311 that receives a control signal (gate terminal of the switch) is connected to the gate 315 of the transistor through switches 318 and 312 (see FIG. 3E). There is no switch at the source terminal 316 for the third configuration either. The last configuration is generally referred as “composite transistor” or “self-cascode configuration,” and as this configuration has a slightly different I-V curve 323 from the I-V curve 320, this configuration is suitable for matching the I-V curve of a transistor with a larger channel length.
FIG. 4A is a diagram of an exemplary embodiment of the function group 212. As explained above, the function group 212 uses transistor arrays and an interconnection network to match a circuit block with specific functions. In this embodiment, the function group 212 includes transistor arrays 401, 402 and local interconnection network 213, 214 (which together make up wires 213). The interconnection wires 213 contain M vertical wires and N horizontal wires, the connection between vertical and horizontal wires are achieved through switches 214 and the switches are defined in FIGS. 3A, 3B, 3C, 3D, and 3E. The function group 212 includes columns of MOS transistor arrays of various lengths. Each column contains multiple drain-source connected PMOS transistor arrays 401 and NMOS transistor arrays 402. The source terminals of the NMOS transistor arrays at the bottom of the function group array 211 are connected to GND 406, and the source terminals of the PMOS transistor arrays 401 at the top of the array are connected to Vdd 405.
A “transistor array” can be an array of NMOS transistors residing within the same or different P-WELL substrate, wherein the P-WELL voltage can be individually controlled. A “transistor array” can also be an array of PMOS transistors residing within the same or different N-WELL substrate, wherein the N-WELL voltage can be individually controlled. In one embodiment of the invention, a triple well process technology is used. The triple well process has separate P-WELL and N-WELL to provide independent programmability for each NMOS and PMOS transistor substrate voltage. A transistor array may include a combination of different transistors selected from low threshold voltage transistors, high threshold voltage transistors, zero threshold voltage transistors, regular threshold voltage transistors, thin gate logic transistors, thick gate I/O transistors and high voltage transistors.
There are two source terminals, one with no switch and the other with one switch, and multiple drain and gate terminals in each of the transistor arrays 401 and 402. There is either one switch or no switch at the source terminal of the transistor arrays 401, 402 and two or more switches at at least some of the drain terminals within the transistor array. One of the drain terminals is connected to the neighboring transistor, and the other drain terminals are connected to the bypass connections 408, which bypasses the neighboring transistor array. With bypass connection, each column can be configured to have various numbers of NMOS and PMOS transistors. There is only one switch at the drain when a transistor in one transistor array is connected to a transistor in another transistor array. The interconnections are mainly made through the gate terminal; thus, there are more than one switch connected to the gate connection.
Besides transistor arrays 401, 402, there are different function groups 212 that can match commonly used analog circuit building blocks, such as current mirrors, reference circuits, amplifiers, oscillator, filter and other circuits. The predefined topology can better match the critical circuit portion of the emulated circuit, the predefined circuits eliminate unnecessary routing, preserve matching of the circuit and offers better accuracy. Some function groups may include BJT/diode 409 as shown in FIG. 4B, and other function groups may contain passive devices 410 as shown in FIG. 4C. Passive devices 410 include programmable resistors and programmable capacitors.
The circuit in FIG. 4A shows a predefined direct connection 407 for NMOS and PMOS differential amplifiers, which are commonly used in analog circuit design. The direct connection eliminates switches at the MOS source terminal and achieves better accuracy. When one transistor cannot supply the current of the transistor to be emulated, two or more transistor arrays combined in parallel may provide the current, as shown by reference numeral 411. There will be slight loss of accuracy due to switches used to connect the transistor arrays. The transistor arrays can also be combined in series as the composite transistor or self-cascode configuration 412. The transistor arrays can also be combined in both series and parallel 413. The combination of parallel and/or series of transistor arrays can provide different characteristic to emulate different kinds of transistors.
FIG. 5A is a diagram of another embodiment of the function group 212. In this embodiment, the function group has NMOS transistor arrays 501 and PMOS transistor arrays 502, which are placed in a two-dimensional array with local interconnection networks 213, 214. The interconnection wires 213 contain M vertical wires and N horizontal wires, the connection between vertical and horizontal wires are through switches 214, which may be any of the switches shown in FIGS. 3A, 3B, 3C, 3D, and 3E. The function group 212 includes columns of MOS transistor arrays having various numbers of transistors, and each column contains several drain-source connected PMOS transistor arrays 501 and NMOS transistor arrays 502. The source of the NMOS transistor array 502 at the bottom of the array is connected to GND 508, and the source of the PMOS transistor array 501 at the top of the array is connected to VDD 507. There are two source terminals and multiple drain and gate terminals for each of the transistor arrays 501 and 502. There is either no switch or one switch at the source terminals in the transistors arrays 501, 502. There are two or more switches at the drain terminal within the transistor array. One of the drain terminals is connected to a neighboring transistor and some drain terminals are connected to the bypass connections, such as by pass connection 506, which bypasses one or more neighboring transistor arrays. With a bypass connection, each column can be configured to include various numbers of NMOS and PMOS transistors. Some of the drain terminals of transistor arrays 501, 502 are connected to drain switches 311 which provides more flexible connections to other transistor arrays through interconnection network 213,214. The drain can have one or more switches when connected to other transistor array, there are more than one switch at the gate terminal connection.
The function group 212 of FIG. 5A can match circuit building blocks which cannot be matched by the function group 212 shown in FIG. 4A. Some function groups also contain diodes/BJT transistors 509 as shown in FIG. 5B or other passive devices 510 as shown in FIG. 5C, including programmable resistors and programmable capacitors. When one transistor array can not supply the current of the transistor to be emulated, two or more transistor arrays can be combined in parallel to provide the current, as shown by reference numeral 511. There will be slight loss of accuracy due to switches used to connect the transistor arrays.
The transistor arrays can also be combined in series as the composite transistor or self-cascode configuration 512. The transistor arrays can also be combined in both series and parallel 513. The combination of parallel and/or series of transistor arrays can provide different characteristic to emulate different kind of transistors.
FIGS. 6A and 6B show the schematic of an amplifier circuit that has been emulated by the emulation system. The circuit is mapped onto a function group array 211, as shown in FIG. 4A, with transistor arrays and local interconnections. The CMOS amplifier circuit can be divided into differential amplifiers M1, M2, M3, M4, M5, M6, output stages M7, M8, M9 and output loading 606. The inputs of the amplifier are Vin− 601 and Vin+ 602, output is Vout 603, the bias inputs are bias1 604, bias2 605. The mapping from circuit schematic into function group is shown. Each transistor of the circuit is mapped onto a transistor array (TA) with minimum number of switches for interconnection, there is no switch at source terminal of each transistor, only one switch at drain terminal and at least two switches at the gate terminal. The mapping uses the pre-defined connection 607 for NMOS differential amplifier to eliminate the switch at the source terminals of M1 and M2.
FIGS. 6C and 6D show different functional groups 212. Specifically, the functional groups 212 may contain diodes/BJT transistors 609 as shown in FIG. 6B or a passive device 608 (e.g., programmable resistors, programmable capacitors) as shown in FIG. 6C. These alternative functional groups 212 will allow emulation of a wider variety of circuits. For example, if a capacitance is large, it is difficult to achieve accurate emulation by using transistors and a programmable capacitor would improve emulation accuracy.
Interconnection parasitic is a major concern in analog circuit layout, as interconnection parasitic degrades analog circuit performance. Accurate simulation of analog circuit needs to include extracted interconnection parasitic. The interconnection parasitic includes both resistance and capacitance. The interconnection resistance can be selectively emulated by combining interconnection wire resistances and switch resistances in series and/or parallel. The interconnection capacitance can be emulated with unused transistor arrays as programmable MOS capacitors. The output loading 606 can be emulated by the unused transistor arrays in the function group array 211. If the output capacitance loading is large, the capacitance loading can be emulated by the programmable capacitor array 608.
FIGS. 7A, 7B, 7C, and 7D show possible architectures of function groups 212 that include programmable passive devices. FIG. 7A shows a programmable capacitor with terminals 701, 702 that includes an array of parallel connected capacitors 704 of different values. In the preferred embodiment, the capacitors are binary weighted (e.g., the capacitor values are of 1, 2, 4, 8 . . . of the unit value). Programmability can be achieved by turning on/off the pass transistors 703 connecting the capacitors to the circuit.
FIG. 7B shows a programmable inductor with terminals 705, 706, which may be implemented with inductors 708 connected in series. Programmability can be achieved by turning on/off the pass transistors 707. In the preferred embodiment, the inductors are binary weighted, which means the inductor values are of 1, 2, 4, 8 . . . of the unit value.
In FIG. 7C, a programmable resistor with terminals 709, 710 is implemented with resistors 712 connected in series. In this case, programmability can be achieved by turning on/off the pass transistors 711. In the preferred embodiment, the resistors are binary weighted, which means the resistor values are of 1, 2, 4, 8 . . . of the unit value.
FIG. 7D shows a commonly used resistor circuit including a resistor ladder used as voltage divider between two terminals 713, 714; the emulation circuit also provides resistor ladder circuit with programmable resistor 715 and provides different number of voltage divider outputs 716.
Another implementation of programmable capacitor and inductor is to use capacitance multiplication and inductance multiplication techniques. These techniques can greatly reduce the areas used by the capacitor and inductor elements.
FIG. 8 is an exemplary embodiment of a transistor array 401, 402, 501, and/or 502. Each transistor array includes an array of transistors and switches and each transistor array can be used to match the operating point of a transistor of the emulated circuit.
There are at least two drain terminals 802 in the transistor array. Each drain terminal 802 is connected to the drain of a transistor through one of the switches 311. In the preferred embodiment of the invention, the switch 311 has one of the configurations shown in FIGS. 3A, 3B, 3C, 3D, and 3E.
There are at least two gate terminals 803 in each transistor array. Each gate terminal 803 is connected to the gate of a transistor through one of the switches 312. In the preferred embodiment of the invention, the switch 312 has one of the configurations illustrated in FIGS. 3A, 3B, 3C, 3D, and 3E.
All transistors in a transistor array share the same source terminal 801 (or source terminals 801, depending on the embodiment). This configuration will provide best accuracy. All transistors 800, 805 in the transistor array may be individually disabled by applying a control voltage Voff at one of the gate terminals 803 and turning on one of the gate switches 312. Depending on the situation, Voff may be implemented as a voltage equal to or less than GND for NMOS, and Voff may be implemented as a voltage equal to or greater than Vdd for PMOS to reduce leakage current.
A method is developed to match the MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) or MOS transistor operating point with multiple MOS transistors; a MOS transistor can be NMOS (N-Type Metal Oxide Semiconductor) or PMOS (P-Type Metal-Oxide Semiconductor). A “transistor operating point” is defined as transistor threshold voltage and transistor current at specific transistor terminal voltages, temperature and other conditions.
Each transistor 800 within a transistor array 401/402/501/502 with the same channel length has the same threshold voltage. Each transistor within a transistor array with different channel length 805 has different threshold voltages. In general, a transistor with longer channel length has smaller threshold voltage.
The voltage applied to the substrate 317 of a transistor array 401/402/501/502 can be individually controlled. This substrate voltage controls the threshold voltage of the transistors within the transistor array. Transistors 800 in the transistor array 401/402/501/502 share the same channel length. There are transistors 805 with channel lengths that are different than that of transistors 800, and these transistors 805 can be used to fine-tune the transistor array electrical behavior. As shown, each of the transistors 800 and 805 correspond to the transistor 313 shown in FIGS. 3C, 3D, and 3E but the transistors 800 have a different channel length than the transistors 805. The switch 318 provides the path from one of the transistor array gate terminals to the gate of one of the switches at the transistor array drain terminal, and this path enables the composite transistor or self-cascode configuration which provides a slightly different I-V curve to match a transistor with a longer channel length, as illustrated in FIG. 3E. The source switch 310 is used to emulate a transistor with short channel effect as illustrated in FIG. 3C. The transistor array also operates as illustrated in FIG. 3D when both switches 318 and 310 are disabled and only uses drain switch 311 and gate switch 312.
For both PMOS and NMOS transistors, increasing the voltage between the source terminal 801 and the substrate 804 increases the transistor threshold voltage, and decreasing the voltage between the source terminal 801 and the substrate 804 decreases the transistor threshold voltage. This effect is sometimes referred to as the body-effect of MOS transistor. This transistor behavior enables fine tuning of transistor threshold voltage by varying the transistor substrate voltage.
For each transistor 800 in the transistor array with the same channel length, the channel widths are different. When two transistors are turned on at the same time, the effective channel width equals the sum of the effective channel widths of the two transistors. In the preferred embodiment, the channel width is binary weighted with 1, 2, 4, 8, . . . times of a unit width. The total effective transistor width of a transistor array can be controlled by turning on or off selected transistors in the array. This mechanism is used to match the current of the emulated transistor. The transistor array also contains transistors 805 with different channel lengths and widths, and these transistors are used to fine tune the transistor behavior to better match the target transistor.
Each transistor array can match a transistor within certain ranges of threshold voltages and currents by controlling the substrate voltage and turning on/off transistors within the transistor array. FIG. 9 shows the comparison of transistor I-V curve of NMOS and PMOS transistor and the IV curve of emulated NMOS and PMOS transistor array. The PMOS transistor current 901 of the emulated circuit may be compared with the PMOS transistor array current 902 of the emulation circuit, and the NMOS transistor current 903 of the emulated circuit may be compared with the NMOS transistor array current 904 of the emulation circuit. The results show only a few % errors in threshold voltage and current can be achieved through transistor array at a specific operating point.
The transistor array 401/402/501/502 contains transistors that have a longer channel length and a greater channel width than the emulated transistor. The transistor array can emulate the threshold voltage and current of the emulated transistor but has a larger channel length and width than the original transistor and operates at a lower frequency than the emulated transistor. There are several advantages of having a larger transistor to improve emulation accuracy. The interconnection network in the programmable circuit has a large capacitance due to switches and long wires. The interconnection capacitance can degrade emulation accuracy when the interconnection capacitance is larger than device capacitance. As a large transistor has a large capacitance, the capacitance of the interconnection network has less effect on emulation accuracy. Device mismatch is an important factor that affects analog circuit performance. The emulation circuit also exhibits device mismatch which affects the emulation accuracy. The larger transistor has better device matching characteristic than smaller transistor and the degree of transistor mismatch is inversely proportional to the transistor area. Having a larger transistor improves device matching and thus improves emulation accuracy. When the circuit operates at very high frequency, it's very difficult to measure circuit behavior accurately. Having a larger transistor forces the emulation to be performed at lower frequency, thereby improving measurement accuracy.
The transistors in a transistor array 401/402/501/502 can also be a combination of different types of transistors, such as one of a low threshold voltage, a high threshold voltage, zero threshold voltage, and regular threshold voltage. Some process technologies also offer other threshold voltage options. The transistor array also includes I/O transistors with different operating voltages, and the I/O transistor operates at a higher voltage than a logic transistor. The I/O transistor is used in an analog circuit design when higher voltage operation is required. The transistor array also includes high voltage MOS transistors for high voltage applications.
In order to match the behavior of any transistor regardless of its type, different threshold voltage option, different threshold voltage value and current, the emulation circuit needs to have transistor arrays of different types, with different threshold voltage options, different channel lengths and a wide range of channel width.
The emulation system of the invention can closely match the operating point of a transistor with the same process technology as long as the transistor characteristics are similar. The system can also be used to match the operating point of a transistor in different process technology and it is accurate around the operating point of the transistor. If the transistor operates far away from the operating point where it is characterized, the error may be larger.
FIGS. 10A, 10B, 10C, and 10D illustrate exemplary embodiments of the on-chip function generation circuit 207 that generates analog inputs to the emulation circuit of the invention. For consistency with FIG. 2, the input (e.g., from the control circuit 106) is shown on the lefthand side and the output (e.g., to the function group array 211) is shown on the righthand side in these figures. As shown in FIG. 10A, the circuit contains a PLL (phase locked loop) 1003 which can generate an internal clock 1007 of a frequency that is different from a reference clock input 1001. The circuit also contains a waveform generator circuit 1008 for generating a square wave 1009, a triangular wave 1010, and a sine wave 1011.
As shown in FIG. 10B, the circuit also contains a D/A (digital-to-analog) converter 1004 to generate an analog voltage waveform 1012 according to a digital input 1002. As shown in FIG. 10C, the analog voltage 1012 can be converted into an analog current 1015 by a voltage-to-current converter 1016.
In the embodiments of FIG. 10D, the circuit may also contain a voltage reference 1005 and a current reference 1006 circuit for generating an accurate analog voltage 1013 and analog current 1014 according to values of the digital inputs.
FIGS. 11A, 11B, 11C, and 11D are exemplary embodiments of the on-chip measurement circuit 208 that can measure voltages and currents within the circuit. For consistency with FIG. 2, the input (e.g., from the function group array 211) is shown on the righthand side and the output (e.g., to the control circuit 106) is shown on the lefthand side. In the embodiments of FIG. 11A and FIG. 11B, the circuit contains a switch 1104 for routing the digital and analog signals 1105, 1106 to the measurement circuit. The circuit may contain A/D (analog-to-digital) converters 1102 to be used to convert analog voltage 1107 to digital signals 1101. In the embodiment of FIG. 11C, the circuit also contains a current measurement circuit 1103 that converts an analog current 1108 into digital values 1101. The digital signals 1105 can be routed through the switch 1104 to produce the digital output 1101 (as in FIG. 11A), and the analog signals 1106 can be routed through the switch 1104 to analog output 1109 (as in FIG. 11D). The analog output 1109 can be measured by external devices.
FIG. 12 depicts the on-chip characterization circuit 209, which is used to characterize the behavior of the transistor arrays 1207, 1208 and programmable passive devices 1210 and BJT/diodes 1211. The circuit contains switches 1205, 1209 between the transistor arrays 1207, 1208, passive devices 1210, BJT/diodes 1211, function generator 207, measurement circuit 208, and I/O circuit 1204. The lefthand side of FIG. 12 shows how the characterization circuit is connected to the function generator 207 and the measurement circuit 208. The characterization circuit 209 includes an I/O circuit 1204 and a switch 1205, which connects functional generator 207, measurement circuit 208, I/O circuit 1204 over analog signal lines 1206 to transistor arrays 1207 and 1208, programmable passive devices 1210 and BJT/diodes 1211. The I/O circuit 1204 is connected to an external measurement device 1201.
The on-chip characterization circuit 209 is useful since the effect of process variation varies from wafer to wafer, from die to die and even within the die. As a result of this variation, the device characteristics of the emulation circuit cannot be pre-determined—it has to be measured from the actual die. However, measuring the characteristic of every device in the emulation circuit is not practical if not impossible.
The characterization can be done before emulation; the pre-characterization can speed up the emulation set-up time. The characterization can also be done during emulation, although doing so could mean a longer set-up time for the emulation. In the preferred embodiment, the characterization results are stored after the first characterization so there is no need for characterization in future emulations of the same circuit or same process technology.
Characterization involves measuring the device characteristics of the actual device in the emulation circuit. The characterization circuit contains at least one unique instance of NMOS, PMOS transistor array 1207, 1208 and programmable passive devices 1210, BJT/diode 1211 in the emulation circuit. The device characteristic is determined by applying different voltages or currents and measuring the resulting voltages or currents. The device characteristics are extracted from the measured results. For each device to be emulated, the device characteristic, such as threshold voltage, current, capacitance, resistance, and inductance is simulated with a circuit simulator, such as SPICE simulator. The emulation software can match the ideal characteristic of a device with the characteristic of the actual device in the emulation circuit.
The accuracy of the measured device characteristic relative to the actual device in the emulation circuit depends on process variation. Process variation can be classified as inter-die or die-to-die variation and intra-die or within-die variation, and the invention focuses on the latter. In another method of classification, process variation can be systematic or random. Generally, systematic variations are deterministic in nature and are caused by the structure of the device and its neighboring environment. Since the devices in measurement circuit and device in the emulation circuit have the same structure, most systematic variations are eliminated. Random variations are unpredictable by nature, and each device can vary independently. Random variations are inversely proportional to the size of the device. Since the transistor array, programmable resistor, capacitor and inductor have large size in the emulation system of the invention, random variations are greatly reduced and high accuracy can be achieved.
The characterization can be done with on chip function generation circuit and on chip measurement circuit. It can also be done with off chip equipments.
FIGS. 13A and 13B depict a full-chip emulation system that includes an analog emulation system 1300 and a digital emulation system 1307. In the full chip emulation system, the analog emulation system 1300 emulates the analog/mixed mode portion of the circuit and the digital emulation system 1307 emulates the digital portion of the circuit. In the configuration of FIG. 13A, the analog emulation system 1300 and digital emulation system 1307 are connected through input/output interfaces 1301, 1302, 1308, 1309 to exchange data. In the configuration of FIG. 13B, the analog and digital emulation system share the same processor 1303, memory 1304, the analog emulation hardware 1306 and digital emulation hardware 1310 are controlled by analog emulation software and digital emulation software 1305. In this configuration, the communication between analog and digital emulation systems occurs through shared memory and/or internal buses.
The analog and mixed mode emulation system emulates circuit at a lower frequency than the frequency of the emulated circuit. The circuit is scaled or transformed so that the circuit behavior is preserved while operating at lower frequency.
In summary, emulation of the analog and mixed mode circuit behavior involves the following steps:

    
    
        The circuit netlist, device models, operating condition, circuit input and output signals are input into the emulation system
        The emulation circuit is characterized to match the device models used before emulation
        Divide the original circuit into blocks that can be matched by the function groups
        Select the function group (FG) that can match the transistor behaviors and functionality of a block in the original circuit
        Program the transistor arrays (TA's) and programmable passive devices in the FG to match the electrical behavior of the transistors and passive devices in the corresponding functional blocks
        Program the local connectivity network to match the connectivity of the original functional block
        Program the connectivity network to connect the function groups (FGs) to match the original circuit connectivity
        Program the on chip function generation circuit to generate the input signals specified in the design
        Program the on chip measurement circuit to monitor or store the electrical behaviors of the circuit nodes/elements to be monitored
        Perform analog and mixed mode circuit emulation
        Perform post processing to report or display the emulation results
    
    


EXAMPLES
Now, examples of several circuits will be described to demonstrate how emulation can be performed at lower frequency while preserving circuit voltage and current behavior. The examples include simplest RC circuit to a complicated PLL (phase-locked-loop) circuit.
First example uses an RC circuit including a resistor and a capacitor. Initially, the circuit is at Vdd and then discharges to GND. The circuit is emulated at a lower frequency with an emulation circuit, and this emulation involves scaling the capacitance to larger value while keeping the resistor value the same. With a larger capacitance, the circuit takes longer time to discharge the capacitance. If the emulation circuit capacitance value is 10 times larger than the emulated circuit, then discharge takes 10 times longer for the emulation circuit compared to the emulated circuit. The waveform generated by the emulation circuit has 10 times the delay compared with the waveform generated by the emulated circuit. As the RC circuit is linear, it should, at least theoretically, offer perfect accuracy when the circuit is scaled. However, in reality, the switch used in the circuit degrades the accuracy and most analog circuits are nonlinear; thus there will be error due to circuit non-linearity and switches.
Second example uses an inverter circuit with a capacitance load. The inverter contains an NMOS and a PMOS transistor. The input of the circuit is a pulse, and thus the output of the circuit toggles between logic “0” and logic “1”. The circuit is emulated at lower frequency with an emulation circuit. The transistor arrays are programmed to emulate the NMOS and PMOS transistors' threshold voltage and current. The transistor array of the emulation circuit has approximately five times the transistor length and width than the emulated transistor. Thus, the transistor array has approximately 25 times the capacitance than the original transistor; the capacitance load is scaled up 25 times and the input of the circuit is also scaled 25 times in time. The emulation circuit has approximately 25 times the delay of the emulated circuit. The differences or errors between the two results are due to differences in the behavior of the emulating transistor and the switches used in the emulation circuit.
Third example includes an operational amplifier circuit and examines its frequency response. The transistors in the emulated circuit are scaled up three times in channel width and length in the emulation circuit, and the transistor capacitances are scaled up approximately nine times. The frequency response of the emulation circuit is about nine times slower than that of the emulated circuit. The differences or errors between the two circuit frequency responses are primarily due to differences in the behavior of the emulated transistor and the switches used in the emulation circuit.
The fourth example includes a PLL (Phase Locked Loop) circuit which is commonly used in analog and mixed mode system. The transistors in the circuit are scaled up three times in channel width and length, and the transistor capacitances are scaled up approximately nine times. The capacitors in the circuit are also scaled up nine times. When compared with emulated PLL circuit, the settling time of the emulation circuit PLL is about nine times that of the emulated circuit. The final VCO (voltage controlled oscillator) control voltage of the emulated circuit and the emulation circuit shows a larger error. The differences or errors between the two waveforms are due to differences in the behavior of the emulated transistor and the switches used in the emulation circuit. Better accuracy can be obtained through fine tuning the emulation circuit to better match the circuit behavior of the original circuit.
The above examples, which are merely illustrative and not limiting of the invention, demonstrate how analog and mixed mode circuit can be emulated by the present invention with high accuracy. In the invention, the emulation accuracy is improved by reducing the interconnection parasitic effect, by improving device matching and by improving measurement accuracy.
Besides silicon technology, which creates BiCMOS transistors, NMOS and CMOS transistors, transistors made with other technologies that can offer analog behavior or simulate analog behaviors can also be used in conjunction with the present invention. Transistors made of III-V compound technology or molecular technology are examples that exhibit analog behaviors.
Embodiments of the present invention may provide various advantages not provided by prior art systems. An advantage of the invention is that analog and mixed-mode circuits can be quickly designed and redesigned by emulating the behavior of the circuit in real time and greatly reduces circuit development time. Thus, the present invention enables a designer to perform more thorough analysis of the circuit to meet design specification and even achieve higher performance and better yield.
Another advantage of the invention is that the programmable emulation circuit can be applied to various circuit designs targeting different application markets such as, data/voice communication, wire/wireless communication, networking, digital/analog audio, digital/analog video, display, storage, digital photography, automotive, power management, high voltage applications, measurement and others. The system of the invention can emulate RF (radio frequency) circuits, IF (intermediate radio frequency) circuits, base-band circuits, transceiver circuits, amplifiers, high speed data link circuits, data conversion circuits, frequency synthesis circuits, clock recovery circuits, power management circuits, memory circuits, high voltage circuits and other analog circuits
Another advantage of the invention is that a full system design containing both digital and analog circuitry can be emulated and verified together at high speed, thus reducing system design and production cycle. The system can be a SOC (system on chip), SIP (system in package) or other forms of electronic system.
Another advantage of the invention is that the emulation system can also be used for analog computing and hybrid analog/digital computing. The emulation system offers full programmability and performance tuning to achieve the best flexibility and accuracy for analog computing. The system can emulate hybrid electrical/mechanical/physical systems for manufacturing, communication, automotive, aerospace, oil drilling, power system, weather forecast, and earth science, among other systems. The system can also be used for building neural networks for artificial intelligence (AI) applications. In the electronic design area, the system can be used for control systems and to speed up parasitic extraction, OPC (optical proximity correction), litho simulation, packaging and interconnection simulation and other applications.
Accordingly, the present invention provides an emulation system consisting of processor, memory, emulation software, input device, and output device and emulation circuit. A programmable analog and mixed mode emulation circuit offers full programmability to emulate given analog/mixed mode circuit design. The present invention provides a solution to emulate a system which is analog/mixed mode or contains both analog and digital circuitries. The present invention can achieve an emulation task which could not be achieved in the past.
Therefore, it should be understood that the invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is not intended to be exhaustive or to limit the invention to the precise form disclosed. It should be understood that the invention can be practiced with modification and alteration and that the invention be limited only by the claims and the equivalents thereof.

## Claims

1. An analog and mixed mode circuit emulation system that emulates analog and mixed mode circuit electrical behavior of an original circuit, comprising:
a control circuit; and
an emulation circuit controlled by the control circuit, the emulation circuit including programmable function groups that are connected to each other in an interconnection network, wherein the function groups match one or more analog electrical behaviors of the original circuit at a lower frequency than an intended frequency of the original circuit.

2. The circuit emulation system of claim 1 further comprising an input device for receiving one or more of a netlist, a device model, and an operating condition.

3. The circuit emulation system of claim 1, wherein the system is implemented in BiCMOS technology and comprises one or more of a BJT, a diode, an NMOS transistor, a PMOS transistor, a resistor, a capacitor, and an inductor.

4. The circuit emulation system of claim 1, wherein the analog electrical behavior includes circuit voltage and current characteristics, and wherein circuit timing and frequency are scaled.

5. The circuit emulation system of claim 1, wherein the interconnection network comprises a switch and wires.

6. The circuit emulation system of claim 5, wherein the switch is a minimum-resistance switch.

7. The circuit emulation system of claim 5, wherein the switch is one of a NMOS, a PMOS or a CMOS transistor having minimum resistance when turned on while maintaining minimum area in a given process technology.

8. The circuit emulation system of claim 1, wherein the interconnection network connects at least one of transistor arrays and programmable passive devices in the function groups.

9. The circuit emulation system of claim 1, wherein the interconnection network comprises programmable loading to emulate actual interconnection loading in the original circuit.

10. The circuit emulation system of claim 1 further comprising a function generation circuit that is coupled to the control circuit and generates AC and DC voltage and current inputs for the emulation circuit.

11. The circuit emulation system of claim 1 further comprising a measurement circuit that is coupled to the control circuit and measures voltage and current outputs from the emulation circuit.

12. The circuit emulation system of claim 1 further comprising a characterization circuit that is coupled to the control circuit and characterizes the emulation circuit based on the output from the emulation circuit.

13. The circuit emulation system of claim 12, wherein the characterization circuit comprises at least one of each configuration of the different transistor arrays, BJTs/diodes and programmable passive devices in the emulation circuit.

14. The circuit emulation system of claim 1 further comprising a control register that is coupled to the control circuit and the emulation circuit to control the interconnection and to control the programmable circuit elements.

15. The circuit emulation system of claim 1 further comprising:
a processor coupled to the control circuit;
a memory coupled to the control circuit; and
an output device coupled to the control circuit that displays emulation results.

16. The circuit emulation system of claim 15 further comprising an emulation software residing in the memory and executed by a processor, wherein the emulation software programs devices and interconnection network in the emulation system to match the circuit topology and circuit characteristic of the original circuit and controls the emulation circuit to generate inputs and monitor outputs.

17. The circuit emulation system of claim 16, wherein the control circuit interfaces between the emulation circuit and at least one of the processor and the memory.

18. The circuit emulation system of claim 1, wherein the function groups match the electrical characteristic and connectivity of a function block in the original circuit.

19. The circuit emulation system of claim 1, wherein the programmable function groups comprise one or more of MOS transistors, resistors, capacitors, inductors, diodes, and BJTs that are programmable to match the characteristics of elements in the original circuit.

20. The circuit emulation system of claim 1, wherein each of the function groups comprises transistor arrays that are interconnected by horizontal wires extending in a first direction and vertical wires extending in a second direction, wherein the horizontal wires and vertical wires are connected through switches.

21. The circuit emulation system of claim 20, wherein each of the transistor arrays comprises a PMOS transistor array and an NMOS transistor array, each of the PMOS transistor array and the NMOS transistor array having at least one source terminal, multiple drain terminals, and multiple gate terminals.

22. The circuit emulation system of claim 21, wherein the multiple drain terminals comprise:
a first drain terminal connected to a neighboring transistor array;
a second drain terminal that bypasses the neighboring transistor array and connects to a non-neighboring transistor array; and
at least one switch at each of the first and second drain terminals.

23. The circuit emulation system of claim 22, wherein there are a first and a second source terminals in each of the PMOS transistor array and the NMOS transistor array, and wherein each of the first and second source terminals is connected to a neighboring transistor army or VDD or GND, and the first source terminal is switchless and the second source terminal has one switch.

24. The circuit emulation system of claim 23, wherein the multiple gate terminals are used for interconnection and each gate terminal comprises at least one switch.

25. A method of emulating an original circuit that has analog components, the method comprising:
providing a programmable circuit comprising components interconnected by switches and an interconnection network;
matching one or more analog electrical behaviors of the original circuit to analog electric behaviors of selected circuit components in the function groups of the programmable circuit at a lower frequency than an intended operating frequency of the original circuit.

26. The method of claim 25 further comprising matching the characteristics of circuit elements in the original circuit on an element-by-element basis with the circuit components of the function groups and matching the connectivity of the original circuit to the interconnection network.

27. The method of claim 25 further comprising forming the functional groups using a combination of MOS transistors, resistors, capacitors, inductors, diodes, and BJTs.

28. The method of claim 25 further comprising scaling up transistor capacitance, capacitor capacitance, and inductance relative to the original circuit to operate at a frequency lower than the operating frequency of the original circuit.

29. The method of claim 25, wherein the matching comprises using the circuit components of the function groups to match the analog electrical behaviors of elements in the original circuit, further comprising minimizing distance between function groups to improve accuracy.

30. The method of claim 29, wherein the matching further comprises programming the interconnection network to connect the functional groups to match the connectivity of the original circuit.

31. The method of claim 29, wherein one or more of the function groups comprises a transistor array, the method further comprising minimizing the number of switches used for interconnection of the transistor arrays of the function groups.