# Patent

## Title
RF power measurement with bi-directional bridge

## Abstract

A bi-directional bridge includes a forward bridge portion, and reverse bridge portion and a shared portion that enables the simultaneous measurement of power flowing in both directions while reducing insertion losses, providing better impedance matching and/or providing improved directionality. In some embodiments, additional attenuation is provided to reduce the common mode rejection requirements of detectors used with the bridge. In other embodiments, multi-tap attenuators and steering circuits may be integrated into the forward and/or reverse bridge portions to reduce common mode signal levels while still maintaining high levels of sensitivity for measuring small input signals.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to U.S. Provisional Patent Application Ser. No. 61/552,601 filed Oct. 28, 2011.


BACKGROUND
FIG. 1 illustrates a prior art arrangement for measuring the amount of radio frequency (RF) power transmitted from an RF power amplifier (PA) 10, to an antenna 12 through a transmission line 13. A directional coupler 14 diverts a small portion of the power to a detector 16 which measures the power transferred in the forward direction.
In some applications, both the forward and reverse (reflected) power must be measured simultaneously, for example, to determine the voltage standing wave ratio (VSWR). FIG. 2 illustrates how two directional couplers 14 and 18 may be arranged in series. One directional coupler 14 enables the first detector 16 to measure the forward power, while the other directional coupler 18 enables a second detector 20 to measure the reverse power.
Directional couplers tend to have low insertion loss, i.e., the loss in power resulting from the insertion of the coupler into the transmission line, because they have low series resistance. The insertion loss of a typical directional coupler may be about 0.1-0.2 dB. However, they also tend to be narrowband devices which restricts their use to applications where the signals to be measured fall within a relatively narrow frequency range, for example, from several hundred megahertz (MHz) to a few gigahertz (GHz).
FIG. 3 illustrates a prior art arrangement in which a directional bridge 22 is used in place of a coupler. Directional bridges are resistor bridges that are designed to divert a portion of the transmitted signal traveling in one direction to a detector. Because they are fabricated from resistive materials, they are inherently broadband devices that can operate over very wide frequency ranges, for example, from essentially DC to tens of GHz where the upper end is limited by parasitics. The resistive nature of a directional bridge, however, typically results in relatively high insertion loss, for example, 1.0-2.0 dB. Although the insertion loss of a single directional bridge is typically tolerable, if power must be measured in both directions, the use of two opposing, series-connected directional bridges introduces an unacceptable level of insertion loss.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a prior art transmission system having a single directional coupler.
FIG. 2 illustrates a prior art transmission system having forward and reverse directional couplers connected in series.
FIG. 3 illustrates a prior art transmission system having a directional bridge.
FIG. 4 illustrates the construction of a prior art directional bridge.
FIG. 5 illustrates an approximation of the bridge of FIG. 4.
FIG. 6 illustrates a technique for determining the input impedance of the bridge of FIG. 4.
FIG. 7 illustrates a technique for determining the output impedance of the bridge of FIG. 4.
FIG. 8 illustrates an embodiment of a multi-directional bridge according to some inventive principles of this patent disclosure.
FIG. 9 illustrates another embodiment of a multi-directional bridge according to some inventive principles of this patent disclosure.
FIG. 10 illustrates an embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure.
FIG. 11 illustrates the bridge of FIG. 10 with simplified components.
FIG. 12 illustrates another embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure.
FIG. 13 illustrates another embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure.
FIG. 14 illustrates a prior art packaging arrangement for an integrated circuit.
FIG. 15 illustrates an embodiment of a packaging arrangement for an integrated circuit according to some inventive principles of this patent disclosure.
FIG. 16 illustrates one technique for modeling the embodiment of FIG. 15.
FIG. 17 illustrates another embodiment of a packaging arrangement according to some inventive principles of this patent disclosure.
FIG. 18 illustrates an embodiment of a bi-directional bridge having a switched detector according to some inventive principles of this patent disclosure.
FIG. 19 illustrates another embodiment of a bi-directional bridge having a switched detector according to some inventive principles of this patent disclosure.
FIG. 20 illustrates an embodiment of a bi-directional bridge having integral multi-tap attenuators and signal-responsive steering according to some inventive principles of this patent disclosure.
FIG. 21 illustrates an example embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure.
FIG. 22 illustrates another example embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure.



DETAILED DESCRIPTION
FIG. 4 illustrates the construction of a prior art directional bridge and detector combination that may be used, for example, as the directional bridge 22 shown in FIG. 3. Because the diode detector D1 has a high input impedance over the relevant frequency range, the circuit of FIG. 4 can be approximated by the circuit of FIG. 5. The following analysis illustrates how the circuit of FIG. 5 enables the measurement of signals traveling through the bridge in only the forward direction.
First, the input impedance Zin looking into the input terminal is determined when a load or transmission line having a characteristic impedance R is coupled to the output terminal as shown in FIG. 6. Using the values R1=0.1R, R2=R and R3=10R, it can be shown that the input impedance Zin is given by

Zin=1.02R  (Eq. 1)

The detector measures the voltage Vba between points A and B, and using the same values of R1, R2 and R3, it can be shown that the measured voltage Vba is given by

Vba=0.181Vin  (Eq. 2)

Next, the output impedance Zout looking into the output terminal is determined when a load or transmission line having a characteristic impedance R is coupled to the input terminal as shown in FIG. 7. Using the same values of R1=0.1R, R2=R and R3=10R, it can be shown that the output impedance Zout is given by

Zout=R  (Eq. 3)

and the measured voltage Vba is given by

Vba=0  (Eq. 4)

Thus, the directivity is theoretically infinite because the bridge measures some positive value of Vba for a signal traveling in the forward direction, while it measures no signal (Vba=0) for a reflected or backward traveling signal.
The bridge of FIG. 5 also provides good impedance matching in both directions, with theoretically perfect matching in the reverse direction (Zout=R), and only about a two percent mismatch (Zin=1.02R) in the forward direction.
The insertion loss of the bridge of FIG. 5 is determined primarily by the value of R1, and to a lesser extent by the values of R2 and R3. In an implementation with 50 ohm source and load impedances, i.e., R=50Ω, the series resistor R1 has a value of 5 ohms which typically results in an insertion loss of about 1-1.5 dB over the operating frequency range which may be about 0.01 to 25 GHz.
As mentioned above, a common parameter that must be measured in RF systems is the voltage standing wave ratio (VSWR) which is defined as follows:




  
    
      
        
          V
          ⁢
          
            
          
          ⁢
          S
          ⁢
          
            
          
          ⁢
          W
          ⁢
          
            
          
          ⁢
          R
        
        =
        
          
            1
            +
            
              
              Γ
              
            
          
          
            1
            -
            
              
              Γ
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          5
        
        )
      
    
  




where Γ (uppercase Greek letter gamma) is the reflection coefficient (return loss) which has an absolute value defined as the difference between the power of the forward signal and the power of the reverse signal:

Pforward−Preverse=|Γ|  (Eq. 6)

Thus, to measure VSWR, it is necessary to simultaneously measure the power of signals traveling in both directions. However, because the directional bridge described above with respect to FIGS. 4-7 can only measure power in one direction, two identical bridges would have to be connected in series, facing opposite directions, to obtain the two power measurements needed to determine the VSWR for a system. This, in turn, would result in double the insertion loss.
FIG. 8 illustrates an embodiment of a multi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 8 includes a forward bridge portion 24 that enables the measurement of a forward signal (e.g., the forward signal from an RF signal source, such as a PA, to an antenna, as discussed above and illustrated in FIGS. 3 and 5) by a forward detector 26, and a reverse bridge portion 28 that enables the measurement of a reverse signal (e.g., the reverse signal from an antenna to an RF signal source, such as a PA, as discussed above and illustrated in FIGS. 3 and 5) by a reverse detector 30. The forward and reverse portions, however, have a shared portion 32 which simultaneously functions as a major component of both the forward and reverse portions. The multi-function characteristic of the shared portion may impart one or more beneficial characteristics to the bridge such as reducing insertion losses, providing better impedance matching, improving directionality, etc. The forward and reverse bridge portions 24 and 28 may include any suitable arrangement of components such as resistors, capacitors, inductors, etc., that implement two bridges that enable simultaneous measurement of forward and reverse flowing signals.
FIG. 9 illustrates another embodiment of a multi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 9 includes forward and reverse bridge portions 24A and 28A having a shared portion 32A, and forward and reverse detectors 26A and 30A similar to those of the embodiment of FIG. 8, but with the addition of an interface circuit 34 that interfaces the forward and reverse bridge portions to the detectors. The interface circuit 34 may, for example, shift one or more signal levels to reduce the common mode rejection (CMR) requirements of one or more of the detectors. As another example, the interface circuit may attenuate one or more signals to change the common mode level, provide better impedance matching or more accurate scaling of the signal detection process. As a further example, the interface circuit may convert between voltage-mode and current-mode signals to enable the use of current-input detectors with voltage-mode bridge portions, or vice-versa.
FIG. 10 illustrates an embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 10 is one example of a more detailed implementation of the embodiment of FIG. 8. The embodiment of FIG. 10 includes a shared or common sense resistor RC connected between the input and output terminals 36 and 38. A first string of shunt resistors RX1 and RX2 is connected between one side of RC and a common or ground node GND. A second string of shunt resistors RY1 and RY2 is connected between the other side of RC and GND. A first detector 40 generates an output signal VF that provides a measure of the forward power, while a second detector 42 generates an output signal VR that provides a measure of the reverse power.
Thus, the embodiment of FIG. 10 includes two overlapping directional bridges that face in opposite directions. The shared sense resistor RC and the first string of shunt resistors RX1 and RX2 form a first directional bridge which, along with the first detector 40, measures the forward power. Simultaneously, the shared sense resistor RC and the second string of shunt resistors RY1 and RY2 form a second directional bridge which, along with the second detector 42, measures the reverse power.
Because the two overlapping directional bridges share the common sense resistor RC, a bi-directional bridge can be implemented, but the insertion loss is only one-half of the insertion loss that would be associated with using two full directional bridges, each having a sense resistor RC, connected in series. That is, both the forward and reverse measurements may be obtained simultaneously, but the insertion loss penalty is paid only once.
Selecting suitable values for RC, RX1, RX2, RY1 and RY2 may involve balancing of various factors depending on the specific application. Some techniques for selecting component values according to the inventive principles of this patent disclosure will be illustrated by calculating example values of RC, RX1, RX2, RY1 and RY2 for a bi-directional bridge that is to be used with a source impedance RS and a load impedance RL as shown in FIG. 11.
FIG. 11 illustrates the bridge of FIG. 10 with the series combination of RY1 and RY2 shown as a simplified resistor RY, and the series combination of RX1 and RX2 shown as a simplified resistor RX. That is, RY1+RY2=RY and RX1+RX2=RX.
Maximum power transfer is obtained when the input impedance RIN equals the source impedance RS, and the output impedance ROUT equals the load impedance RL. Also, for measurement symmetry, it is assumed that RY=RX, RS=RL, and RIN=ROUT. Thus, for RIN=RS=RL=ROUT, it can be shown that




  
    
      
        
          R
          X
        
        =
        
          
            
              R
              L
              2
            
            ±
            
              
                R
                L
                2
              
              ⁢
              
                
                  1
                  +
                  
                    
                      R
                      C
                    
                    /
                    
                      R
                      L
                    
                  
                
              
            
          
          
            R
            C
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          7
        
        )
      
    
  




To apply Eq. 7, a suitable value for RC is first selected. Assuming RS=RL=50 ohms, a value of RC=5Ω is selected to keep the insertion loss below 1 dB. Plugging these values for RL and RC into Eq. 7 and discarding the ± option that produces a negative value yields the following result

RY=RX=1024.4Ω  (Eq. 8)

which provides ideal input and output impedance matching.

After suitable values for RX and RY have been determined, the individual values of RY1, RY2, RX1 and RX2 can be determined. Referring to FIG. 10, theoretically perfect directivity is achieved when values of RY1, RY2, RX1 and RX2 are selected so that a forward traveling signal is completely nulled at the input of the reverse detector 42, and a reverse traveling signal is completely nulled at the input of the forward detector 40. The first step in determining these values is to calculate an attenuation factor Attn1 from VY1 to VX1. Referring back to FIG. 11, the value of Attn1 is determined by the voltage divider formed by RC in series with the parallel combination of RX and RL as follows:




  
    
      
        
          Attn
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              
                R
                X
              
              ||
              
                R
                L
              
            
            
              
                
                  R
                  C
                
                +
                
                  R
                  X
                
              
              ||
              
                R
                L
              
            
          
          =
          
            
              
                R
                X
              
              ⁢
              
                
                  R
                  L
                
                /
                
                  (
                  
                    
                      R
                      X
                    
                    +
                    
                      R
                      L
                    
                  
                  )
                
              
            
            
              
                R
                C
              
              +
              
                
                  R
                  X
                
                ⁢
                
                  
                    R
                    L
                  
                  /
                  
                    (
                    
                      
                        R
                        X
                      
                      +
                      
                        R
                        L
                      
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          9
        
        )
      
    
  




For RC=5 ohms, RS=50 ohms, and RX=1024.4 ohms, Eq. 9 evaluates to Attn1=0.905. That is, for an input voltage VY1 applied to the input terminal 36, the voltage at VX1=0.905·VY1, which also appears at the noninverting (+) input of the reverse detector 42.

Next, to assure zero differential voltage across the input terminals of the reverse detector 42, the voltage at VY2 must equal the voltage at VX1. This is achieved when a second attenuation factor Attn2 from VY1 to VY2 is equal to Attn1, that is, when




  
    
      
        
          Attn
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            Attn
            ⁢
            
              
            
            ⁢
            2
          
          =
          
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                2
              
            
            
              
                R
                
                  Y
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              +
              
                R
                
                  Y
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          10
        
        )
      
    
  




In this example, Attn1=0.905, and RY1+RY2=1024.4. Thus, RY2=927.1 and RY1=97.3.

From these example values, it is apparent that the differential signal between VY1 and VX2 (forward detector) and between VX1 and VY2 (reverse detector) may be difficult to measure because the sensed signal is relatively small, but riding on a very large common mode signal. Thus, the detectors may need to have very high common mode rejection.
The embodiment of FIG. 10 may be well-suited for use with passive detectors such as diode detectors that do not have constraints such as power supply headroom, common mode rejection requirements, etc. In some implementations, however, it may be beneficial to use more sophisticated or active power detectors such as root-mean-square (RMS) detectors, logarithmic amplifiers (log amps), linear amplifiers, etc. These types of detectors include active circuitry that is constrained by dual or single-ended power supplies, and if the embodiment of FIG. 10 is to be used for measuring relatively high power signals, the signal levels involved may conflict with the available power supplies. For example, a +30 dBm input signal from a 50Ω source impedance has ±10 volt excursions (20 volts peak-to-peak), which may have to be processed by an active detector operating from a single or dual 3 or 5 volt power supply.
The demands placed on the detectors, however may be relaxed through the use of interface circuitry that may provide attenuation, level shifting, etc. as described below.
FIG. 12 illustrates another embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 12 is one example of a more detailed implementation of the embodiment of FIG. 9 in which the shunt paths of the bridge are structured so that the detectors 46 and 48 see attenuated and level-shifted signals, thereby reducing the CMR requirements of the detectors and allowing them to operate at typical power supply voltages.
The first shunt path, which will be referred to as the X or RX shunt path, includes resistors RX1, RX2 and RX3 connected in series. Likewise, the second shunt path, which will be referred to as the Y or RY shunt path, includes resistors RY1, RY2 and RY3 connected in series.
Selecting values for RC, as well as the X and Y shunt paths may involve subtle balancing of various factors depending on the specific application. In the following example, some suitable component values will be determined for an embodiment in which the bi-directional bridge is fabricated on an integrated circuit (IC) chip on which input and output terminals RFIN and RFOUT are bond pads, and the source and load impedances RS and RL are assumed to be 50Ω.
To begin the process, a suitable value for RC is selected. In this example, a value of RC=5Ω is selected to keep the insertion loss below 1 dB.
Next, the overall values of the X and Y shunt paths are selected to provide input and output impedance matching. Theoretically perfect matching is obtained when RS=RIN and ROUT=RL. Measurement symmetry is maintained by setting RY=RX, RS=RL, and RIN=ROut. If RX=RX1+RX2+RX3 and RY=RY1+RY2+RY3, then solving for RX in much the same manner as using Eq. 7 in the embodiment of FIGS. 10 and 11, the optimum value of RY (and thus RX) is again determined to be 1024.4Ω.
Next, the individual values of RY1, RY2 and RY3 (and thus RX1, RX2 and RX3) are selected. This involves two primary determinations. First, a common mode attenuation factor from VY1 to VY2 (and VX1 to VX2) is selected to bring the voltage levels at VY2 and VX2 down to a level that provides a manageable common mode input for the detectors 46 and 48. Second, the relative values of RY2 and RY3 (and RX2 and RX3) are selected to provide adequate directivity.
The common mode attenuation factor from VY1 to VY2, which will be referred to as AttnCM, is determined by the following equation:




  
    
      
        AttnCM
        =
        
          
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                2
              
            
            +
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                2
              
            
            +
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                3
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          11
        
        )
      
    
  




To provide optimum directivity, the reverse detector 46 should see zero volts across its inputs in response to a forward traveling signal at the RFIN terminal 36. Optimizing the directivity involves defining two more attenuation factors: Attn1 is defined as the attenuation from VY1 to VX1 (and VX1 to VY1, where RS=RL):




  
    
      
        
          Attn
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              
                R
                X
              
              ||
              
                R
                L
              
            
            
              
                
                  R
                  C
                
                +
                
                  R
                  X
                
              
              ||
              
                R
                L
              
            
          
          =
          
            
              
                R
                X
              
              ⁢
              
                
                  R
                  L
                
                /
                
                  (
                  
                    
                      R
                      X
                    
                    +
                    
                      R
                      L
                    
                  
                  )
                
              
            
            
              
                R
                C
              
              +
              
                
                  R
                  X
                
                ⁢
                
                  
                    R
                    L
                  
                  /
                  
                    (
                    
                      
                        R
                        X
                      
                      +
                      
                        R
                        L
                      
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          12
        
        )
      
    
  




where RX=RX1+RX2+RX3, and Attn2 is defined as the attenuation from VY2 to VY3 (and VX2 to VX3):





  
    
      
        
          Attn
          ⁢
          
            
          
          ⁢
          2
        
        =
        
          
            R
            
              Y
              ⁢
              
                
              
              ⁢
              3
            
          
          
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                2
              
            
            +
            
              R
              
                Y
                ⁢
                
                  
                
                ⁢
                3
              
            
          
        
      
    
    
      
        (
        
          Eq
          .
          
            
          
          ⁢
          13
        
        )
      
    
  




Referring to FIG. 12, it is apparent that the reverse detector 46 sees zero volts across its inputs when VY3=VX2. Using the attenuation factors defined above:

VY3=VY1·AttnCM·Attn2  (Eq. 14)

and

VX2=VY1·Attn1·AttnCM  (Eq. 15)

Setting VY3=VX2 yields:

Attn1=Attn2  (Eq. 16)

for optimum directivity.

One approach to selecting values for RY1, RY2 and RY3 is to use brute force calculations to determine exact values. For example, as determined above, ideal input and output impedance matching is achieved when RX=1024.4 ohms. Assuming RC=5 ohms and RL=50 ohms, (Eq. 12) evaluates to Attn1=0.905. Since optimum directivity is achieved when Attn1=Attn2, a common mode attenuation factor AttnCM may be chosen, then (Eq. 11) and (Eq. 13) may be solved to determine exact values for RY1, RY2 and RY3.
Some additional observations, however, may provide a more nuanced approach to selecting values that are more amendable to fabrication in monolithic form. First, the absolute values of RX (and RY) may be varied somewhat while still providing adequate input and output impedance matching. Second, the exact value of the common mode attenuation factor AttnCM is typically not important as long as the input signal at VY1 is attenuated enough to bring the voltage at VY2 down to a low enough level that is within the CMR range of the detector 46. Third, although the absolute values of RX (and RY) are typically not important, the relative values of RX and RY will typically need to be matched closely to provide adequate performance, and when designing an integrated circuit, matching is often achieved by using unit resistors.
Therefore, another approach to selecting values for RY1, RY2 and RY3 involves making some educated guesses at resistor values using unit resistors, then iteratively adjusting the values as illustrated with the following example which utilizes 100 ohm unit resistors.
As a starting point, assume the inputs to the detectors 46 and 48 can handle a common mode input voltage of about ±1.2 volts, and the bridge is intended to handle a 30 dBm input signal from a 50Ω source impedance which therefore has ±10 volt excursions. Also select RC=5 ohms to keep the insertion loss less than 1 dB. Since RY (that is, RY1+RY2+RY3) should be about 1024 ohms, and AttnCM must be about 0.12, a first guess for RY1 according to (Eq. 11) is 900 ohms, which means RY2+RY3 would have to be a little over 100 ohms.
From (Eq. 12), Attn1 is about 0.905. According to (Eq. 16), Attn1=Attn2 for optimum directivity, and thus, according to (Eq. 13), RY3/(RY2+RY3)=0.905. Since RY2+RY3 should be a little over 100 ohms, and using values that can be obtained with 100 ohm unit resistors, first guesses for RY2 and RY3 are 10 ohms, and 100 ohms, respectively. Thus, the first guess is:
RY1=900 ohms
RY2=10 ohms
RY3=100 ohms.
Plugging these values into (Eq. 11) yields AttnCM≈0.11. That is, a ±10 volt input at VY1 is attenuated down to about ±1.1 volts at VY2, which is within the ±1.2 volt common mode input range of the detectors 46 and 48, so the attenuation factor is acceptable. As for impedance matching, RY=RY1+RY2+RY3=900+10+100=1010 ohms. This is within one percent of the theoretically perfect value of 1024.4 ohms, so the input and output impedance matching are acceptable.
Turning now to directivity, (Eq. 12) yields Attn1≈0.905 and (Eq. 13) yields Attn2≈0.909. It can be shown that these values yield a best case directivity of about 34 dB. This is a good value, but from (Eq. 13), it is apparent that the value of RY2 could be increased slightly for even better directivity.
Increasing the value of RY2 to 10.5 ohms (using 105 ohm unit resistors) essentially leaves the value of Attn1 unchanged at 0.905, but reduces the value of Attn2 to 0.905, thereby providing excellent directivity.
Thus, using the following final values for the embodiment of FIG. 12:
RY1=900 ohms
RY2=10.5 ohms
RY3=100 ohms
provides a bi-directional bridge with a common mode voltage that is low enough to utilize readily available detectors, provides good input and output impedance matching, and is easy to fabricate on an integrated circuit using unit resistors that provide excellent matching between the two shunt paths of the bridge, as well as excellent directivity. Moreover, because the structure is a resistive bridge, it is inherently capable of broadband operation, where the lower end is DC and the upper end is only limited by parasitics.
Examples of detectors suitable for use with the embodiments of FIGS. 9, 12, and 13 include diode detectors, logarithmic amplifiers (log amps), and root-mean-square (RMS) detectors, as well as linear amplifiers if there is a need to preserve amplitude and phase information.
Current Conversion
FIG. 13 illustrates another embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 13 is another example of a more detailed implementation of the embodiment of FIG. 9, but in this embodiment, the measured signals are converted to current mode signals to reduce the necessary voltage swing that the detectors have to process.
The embodiment of FIG. 13 is similar to that of FIG. 12, but the lower portions of the shunt paths are arranged as parallel rather than series combinations of resistors to enable sensing the shunt path signals in the form of currents rather than voltages. In the Y shunt path, all of the current flows through resistor RY1. It then splits with a portion of the current flowing through RY2 into the inverting (−) input of reverse detector 50 and the rest of the current flowing through RY3 into the noninverting (+) input of forward detector 51. In the X shunt path, all of the current flows through resistor RX1. It then splits with a portion of the current flowing through RX2 into the inverting (−) input of reverse forward 51 and the rest of the current flowing through RX3 into the noninverting (+) input of forward reverse detector 50.
Detectors 50 and 51 are configured with very low impedance inputs (current sinks) to implement an AC ground to absorb all of the current flowing through the current-splitting resistors RY2, RY3, RX2 and RX3. The output of each detector is a measure of the differential current at its inputs. Because the inputs are at AC ground, there is no common mode voltage to contend with. The common mode voltage is converted into differential currents via the CM voltage at VY2 and VX2 applied across resistors RX2, RX3, RY2 and RY3.
Many of the same design considerations discussed above with respect to the embodiment of FIG. 12 may apply to the embodiment of FIG. 13. For example, an attenuation factor Attn1 can be defined from VY1 to VX1:

Attn1=VX1/VY1  (Eq. 17)

It can be shown that, for optimum directionality in the embodiment of FIG. 13, the values of RX3 and RY2 are related to the value of Attn1 as follows:





  
    
      
        
          
            R
            
              X
              ⁢
              
                
              
              ⁢
              3
            
          
          
            R
            
              Y
              ⁢
              
                
              
              ⁢
              2
            
          
        
        =
        
          Attn
          ⁢
          
            
          
          ⁢
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Parasitics and Packaging
Integrated circuits are mounted in packages that have inherent parasitic effects such as the resistance, inductance and capacitance of bond wires that connect bond pads on the IC chip to terminals or lead frames on the packages. These parasitics are generally detrimental to the operation of the chip, although they can sometimes be utilized to advantage as an extension of the circuit on the chip as disclosed, for example, in U.S. Pat. No. 6,046,640 by an inventor of this patent disclosure.
The use of packaging parasitics have previously been used in conjunction with a single terminal of an IC package. Referring to FIG. 14, a conventional packaging arrangement includes an IC chip 52 having a bond pad 54. The IC chip is mounted in a package 56 with a lead frame 58. The bond pad 54 is connected to the lead frame 58 through a bond wire having an inductance LBW. The lead frame 58 has a parasitic capacitance CLF.
Rather than letting the bond wire inductance and lead frame capacitance exercise an uncontrolled influence over the operation of the chip, an on-chip capacitor COC is added to the integrated circuit. The value of COC is tuned so that the combination of CLF, LBW, and COC form a maximally flat, third-order, low pass filter. The filter is third-order because it includes three reactive components.
The architecture of a bi-directional bridge according to the inventive principles of this patent disclosure enables the implementation of higher-order filters using packaging parasitics according to some additional inventive principles of this patent disclosure.
FIG. 15 illustrates an embodiment of a packaging arrangement for an integrated circuit according to some inventive principles of this patent disclosure. An integrated circuit 60 includes a bi-directional bridge having resistors RC, RY1, RY2, RY3, RX1, RX2 and RX3 as in embodiments described above. The IC includes bond pads 62 and 64 which provide access to the input and output terminals of the bridge. The bond pads 62 and 64 are coupled to lead frames 66 and 68 of a package 70 through bond wires having inductances LBW1 and LBW2, respectively. Lead frames 66 and 68 have parasitic capacitances CLF1 and CLF2, respectively.
By including additional on-chip capacitors COC1 and COC2, which can also be part of the parasitic capacitance, at or near the bond pads 62 and 64, a fifth-order or higher low-pass filter can be realized. The structure of the filter can be conceptualized as flowing through the chip. Because the value of RC is relatively small, the two on-chip capacitors COC1 and COC2 can be modeled as a single capacitor COC as shown in FIG. 16. Thus, by including capacitors having suitable values on an IC having a bi-directional bridge according to the inventive principles of this patent disclosure, a fifth-order maximally flat, low-pass filter may be implemented utilizing packaging parasitics.
FIG. 17 illustrates another embodiment of the packaging arrangement according to some inventive principles of this patent disclosure. The embodiment of FIG. 17 is similar to that of FIGS. 15 and 16 but includes inductances LLF1 and LLF2 of the lead frames and also illustrates some example values that provide a fifth-order maximally flat, low-pass filter with a −3 dB point at 20 GHz.
Buffered Detectors
In any of the embodiments described above, one or more of the detectors may include an input buffer according to some additional inventive principles of this patent disclosure. For example, a detector may include a unity-gain buffer to improve the common mode rejection by eliminating some or all of the common mode portion of the input signal to the detector. These same buffers could also be used to bring out the detected signals in applications where amplitude and phase information needs to be preserved as in the case of a vector network analyzer (VNA).
Switched Detectors
FIG. 18 illustrates an embodiment of a bi-directional bridge having a switched detector according to some inventive principles of this patent disclosure. The embodiment of FIG. 18 includes a bi-directional bridge having resistors RC, RY1, RY2, RY3, RX1, RX2 and RX3 as in embodiments described above. Rather than including two detectors, however, a two-pole, double-throw switch circuit 72 is used to selectively couple the differential inputs of a single detector 74 to the nodes that enable it to measure either the forward or reverse traveling signals in response to a digital control circuit 76 having a user interface such as a serial peripheral interface (SPI) port.
The output of the detector may be brought out to a user-accessible terminal 78. Thus, the user may implement a time-multiplexed measurement scheme in which the switch circuit 72 alternately re-connects the detector 74 to measure the forward or reverse traveling signals, which then receive further processing by the user.
The embodiment of FIG. 18 may be beneficial in applications where the forward or reverse traveling signals do not need to be measured exactly simultaneously. By reducing the number of detectors, this embodiment may enable a substantial reduction in power consumption and dissipation, complexity, chip space, etc.
In some embodiments, an optional analog-to-digital converter (ADC) 80 may be included to provide the user with the output in a digital form. A memory 82 may also be included to store the digitized values of the forward and reverse signals.
In some additional embodiments, an additional switch circuit may be included and operated as dummy switches that are connected to the otherwise unconnected nodes to keep the effective loading on all nodes constant regardless of which set of signals is being measured.
FIG. 19 illustrates another embodiment of a bi-directional bridge having a switched detector according to some inventive principles of this patent disclosure. The embodiment of FIG. 19 includes a bi-directional bridge similar to that of FIG. 18, but instead of a double-pole, double-throw switch, a four-pole, single-throw switch 84 is arranged to individually couple the input of a single-ended detector 86 to each of the four measurement nodes in response to a digital control circuit 76. The values of VF and VR may then be obtained by subtracting VX3 from VY2 and VY3 from VX2, respectively. An optional ADC 80 may be included along with an optional memory 82.
Integral Multi-Tap Attenuators and Signal-Responsive Steering
Some additional inventive principles of this patent disclosure relate to a synergistic integration of multi-tap attenuators and steering circuits into a bi-directional bridge.
Multi-tap attenuators and steering circuits are utilized in some types of variable gain amplifiers (VGAs) such as the X-AMP® architecture. An example is illustrated in FIG. 8 of U.S. Pat. No. 7,495,511 which has a common inventor with this patent disclosure and is incorporated by reference. The input signal is applied to an attenuator network. Attenuated versions of the input signal are available at tap points along the attenuator. A steering circuit, typically based on a series of transconductance (gm) cells controlled by an interpolator, selects the signals from one or more tap points and feeds them to a fixed gain amplifier. By selecting various tap points along the attenuator and merging the signals from adjacent tap points, the steering circuit provides continuously variable gain control. The steering circuit may alternatively be controlled by a series of binary signals, instead of interpolator signals, to provide discrete gain steps.
According to some of the inventive principles, one or more multi-tap attenuators and accompanying steering circuits may be used to implement all or a portion of one or more of the strings of shunt resistors in a bi-directional bridge. In addition to enabling the multi-tap attenuator to serve the dual purpose of shunt string, this configuration offers additional inherent benefits as described in more detail below.
FIG. 20 illustrates an embodiment of a bi-directional bridge having integral multi-tap attenuators and signal-responsive steering according to some inventive principles of this patent disclosure. The embodiment of FIG. 20 includes a bi-directional bridge having a forward portion 24B, a reverse portion 28B and a shared portion 32B. A multi-tap attenuator 90 is used to implement all or part of the forward bridge portion 24B, while another multi-tap attenuator 92 is used to implement all or part of the reverse bridge portion 28B. A first steering circuit 86 selectively connects a forward detector 26B to suitable taps on both multi-tap attenuators 90 and 92, while a second steering circuit 88 connects a reverse detector 30B to suitable taps on both multi-tap attenuators 90 and 92.
The multi-tap attenuators 90 and 92 may be implemented in any suitable form, for example, as resistive strings, ladders or other types of networks. They may be realized as single-sided or differential structures, etc. The steering circuits may be implemented to provide continuous or discrete steering, i.e., with interpolated or binary switching. Like the attenuators, they may be realized as single-sided or differential structures, etc.
Feedback paths 94 and 96 may be included to enable the steering circuits 86 and 88 to respond to any suitable signal levels such as the levels of the input signal and/or output signal to/from the bi-directional bridge, a setpoint signal level, reference signal level, etc. For example, the feedback paths 94 and 96 may be arranged to servo the steering circuit to control the gain of a power amplifier in a controller configuration, or to provide a scaled output reading when arranged in a measurement configuration.
FIG. 21 illustrates an example embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 21 is one example of a more detailed implementation of the embodiment of FIG. 20. In the embodiment of FIG. 21, the Y and X shunt paths are implemented as a multi-tap attenuators RY1-RY8 and RX1-RX8, respectively.
A first steering circuit includes steering cells SR1-SR4 that can be selectively enabled and disabled, fully or partially, in response to reverse gain control signals GR1-GR4. A second steering circuit includes steering cells SF1-SF4 that can be selectively enabled and disabled, fully or partially, in response to forward gain control signals GF1-GF4. The steering cells may be implemented as transconductance (gm) cells, and the gain control signals may be implemented as bias signals for the gm cells. The bias signals may be fully switched to provide discrete gain steps or interpolated to provide partial switching for continuous gain control.
The outputs of the first steering cells SR1-SR4, which in this example may be current outputs from transconductance cells, are combined at a first summing node N1 and applied to a reverse detector cell 102. The outputs of the second steering cells SF1-SF4 are combined at a second summing node N2 and applied to a forward detector cell 104.
A second reverse detector cell 100 is matched to the first reverse detector cell 102 and receives a target current ITGT. One of the two reverse detector cells is configured to provide an output of opposite polarity as the other so that the difference between the outputs of the two reverse detector cells is obtained at a summing node N3. The difference is integrated by a filter capacitor CFR to generate a voltage which is buffered by output buffer 108 and appears as the reverse detector output VOUT REV. A similar arrangement of matched forward detector cells 104 and 106 generate a difference current at summing node N4 which is integrated by a filter capacitor CFF to generate a voltage which is buffered by output buffer 110 and appears as the forward detector output VOUT FWD.
The detector cells may be implemented with any suitable circuitry including diode detectors and relatively simple transistor squaring cells such as transconductance squaring cells and translinear squaring cells, as well as more complex detectors such as logarithmic amplifiers (log amps), complete RMS detector subsystems, etc. In the example embodiment of FIG. 21, the detector cells are implemented as relatively simple translinear squaring cells which can receive the outputs IR and IF from the steering circuits directly as current mode signals.
The reverse and forward gain control circuits 112 and 114 can be implemented with any suitable circuitry. For example, in an embodiment with continuous gain control, the gain control circuits may be implemented with interpolators that generate a series of interpolator currents which may be used as gain control signals GR1-GR4 and GF1-GF4 in response to input voltage signals VSET REV and VSET FWD, respectively.
In the embodiment of FIG. 21, the reverse detector output VOUT REV is connected to the reverse gain control input VSET REV, and the forward detector output VOUT FWD is connected to the forward gain control input VSET FWD. This configures the system in a measurement mode with the forward and reverse detector outputs provided at VOUT FWD and VOUT REV, respectively. This causes the feedback paths through the gain control circuits to servo each side of the system so that the optimal steering cell or cells are activated or selected depending on the levels of the signals applied to the attenuators. The system can alternatively be configured in a controller mode with setpoint signals applied to VSET REV and VSET FWD. In either configuration, scaling is provided by the signal ITGT which may provide a reference level for scaling the outputs VOUT FWD and VOUT REV.
An advantage of the system of FIG. 21 is that the multi-tap attenuators provide inherent level-shifting for large input signals while still providing good sensitivity for smaller input signals. For example, when a large input signal is applied to VY1, a relatively large voltage appears at VY2 and to a decreasing extent at VY4 and VY6. The reverse gain control loop servos the system so that steering cells SR1-SR3 (which in this example are gm cells) are turned off and steering cell SR4 is turned on to measure the largely attenuated, but still easily detectable, signal at VY8. The common mode voltage at SR4 is never a problem because the signal applied to VY1 is always highly attenuated by the time it appears at VY8. Although a relatively high common mode voltage appears at VY2, and to a decreasing extent at VY4 and VY6, cells SR1-SR3 are turned off due to the operation of the servo loop. Therefore, the relatively high common mode voltages are not a problem at steering cells SR1-SR3, which are limited only by their breakdown voltages.
In contrast, when a relatively small voltage is applied to VY1, the reverse gain control loop servos the system so that steering cells SR2-SR4 are turned off and steering cell SR1 is turned on to measure the signal at VY2 with relatively little attenuation.
Thus, the system of FIG. 21 eliminates problems with common mode signal levels while still maintaining high levels of sensitivity for measuring small differential input signals.
An additional advantage of the embodiment of FIG. 21 is that the relatively simple attenuator strings may require the use of few resistors compared to other attenuator arrangements, thereby resulting in reduced parasitic capacitance and increased bandwidth.
To provide convenient scaling, the values of RY1-RY8 and RX1-RX8 can be related to normalized values R1 and R2 as follows:
RY1, RX1=2R1 
RY2, RX2=2R2 
RY3, RX3=R1 
RY4, RX4=R2 
RY5, RX5=R1/2
RY6, RX6=R2/2
RY7, RX7=R1/4
RY8, RX8=R2/4
This provides a binarily weighted voltage distribution along the attenuator strings as follows:
VY3=VY1/2
VY5=VY1/4
VY7=VY1/8
and
VX3=VX1/2
VX5=VX1/4
VX7=VX1/8
Some example values for a system having 50 ohm input and output impedance are RC=5Ω, R1=47.5Ω and R2=202.5Ω. This provides a voltage distribution as follows:
VY1=0.905VX1 
VY2=0.905VY1 
VY4=0.905VY1/2
VY6=0.905VY1/4
VY8=0.905VY1/8
and
VX1=0.905VY1 
VX2=0.905VX1 
VX4=0.905VX1/2
VX6=0.905VX1/4
VX8=0.905VX1/8
FIG. 22 illustrates another example embodiment of a bi-directional bridge according to some inventive principles of this patent disclosure. The embodiment of FIG. 22 is similar to that of FIG. 21, but the attenuator strings are replaced with attenuator ladders. Although any suitable attenuator ladders may be used, the embodiment of FIG. 22 is implemented with R-2R ladders to provide a binarily weighted voltage distribution along the attenuators. To provide suitable tap points for the steering cells, the “2R” rungs of the ladders are split into resistive dividers in which R2+R3=2R1. Some example values for a system having 50 ohm input and output impedance are RC=5Ω, R1=1KΩ, R2=190Ω and R3=1.81KΩ.
An advantage of the embodiment of FIG. 22 is that it utilizes a repetitive structure that enables the use of unit resistors which simplifies the layout on an integrated circuit.
The inventive principles of this patent disclosure have been described above with reference to some specific example embodiments, but these embodiments can be modified in arrangement and detail without departing from the inventive concepts.

## Claims

1. A bi-directional measurement circuit comprising:
an RF input terminal;
an RF output terminal;
a forward component;
a reverse component;
a forward bridge portion coupled between the RF input terminal and the RF output terminal and arranged to divert a portion of the power flowing from the RF input terminal to the RF output terminal to the forward component; and
a reverse bridge portion coupled between the RF input terminal and the RF output terminal and arranged to divert a portion of the power flowing from the RF output terminal to the RF input terminal to the reverse component;
wherein:
the forward component is coupled to the forward bridge portion,
the reverse component is coupled to the reverse bridge portion,
the forward bridge portion comprises a first shunt path coupled to the RF output terminal,
the reverse bridge portion comprises a second shunt path coupled to the RF input terminal, and
the forward bridge portion and the reverse bridge portion each include an electrical pathway through a shared portion, the shared portion is arranged to function simultaneously as part of the forward bridge portion and as part of the reverse bridge portion, and the shared portion comprises a resistor coupled between the RF input terminal and the RF output terminal.

2. The circuit of claim 1, wherein:
the first shunt path comprises a first resistor coupled between the RF output terminal and a first node, and a second resistor coupled between the first node and a second node; and
the second shunt path comprises a third resistor coupled between the RF input terminal and a third node, and a fourth resistor coupled between the third node and a fourth node.

3. The circuit of claim 2, wherein:
the forward component is coupled between the RF input terminal and the first node; and
the reverse component is coupled between the RF output terminal and the third node.

4. The circuit of claim 1, further comprising an interface circuit coupled between the forward and reverse bridge portions and the forward and reverse components.

5. The circuit of claim 4, wherein the interface circuit is arranged to level shift the signals applied to the forward and reverse components.

6. The circuit of claim 1, wherein:
the first shunt path comprises a first resistor coupled between the RF output terminal and a first node, a second resistor coupled between the first node and a second node, and a third resistor coupled between the second node and a third node; and
the second shunt path comprises a fourth resistor coupled between the RF input terminal and a fourth node, a fifth resistor coupled between the fourth node and a fifth node, and a sixth resistor coupled between the fifth node and a sixth node.

7. The circuit of claim 6, wherein:
the reverse component is coupled between the first node and the fifth node; and
the forward component is coupled between the second node and the fourth node.

8. The circuit of claim 7, wherein the third and sixth nodes comprise AC grounds.

9. The circuit of claim 1, wherein the forward and reverse bridge portions are arranged to provide current mode inputs to the forward and reverse components.

10. The circuit of claim 1, wherein:
the forward component includes a forward linear buffer amplifier and a forward detector, and the forward linear buffer amplifier is coupled between the forward bridge portion and the forward detector; and
the reverse component includes a reverse linear buffer amplifier and a reverse detector, and the reverse linear buffer amplifier is coupled between the reverse bridge portion and the reverse detector.

11. The circuit of claim 1, wherein the forward component includes a forward linear amplifier, and the reverse component includes a reverse linear amplifier.

12. The circuit of claim 1, wherein the forward component includes a forward detector, and the reverse component includes a reverse detector.

13. A method of measuring an amount of radio frequency (RF) power in a signal, comprising:
measuring a forward power of the signal with forward detection circuitry; and
measuring a reverse power of the signal with reverse detection circuitry, wherein the forward detection circuitry and the reverse detection circuitry includes circuitry shared between the forward detection circuitry and the reverse detection circuitry such that the forward detection circuitry and the reverse detection circuitry each include an electrical pathway through the shared circuitry, and the shared circuitry includes a resistor;
wherein measuring the forward power of the signal comprises converting a current-mode signal to a voltage-mode signal, or converting a voltage-mode signal to a current-mode signal.

14. The method of claim 13, wherein measuring the forward power of the signal comprises level-shifting the signal.

15. The method of claim 13, wherein measuring the forward power of the signal comprises attenuating the signal.

16. The method of claim 13, further comprising:
determining a voltage standing wave ratio (VSWR) based on the forward power and the reverse power.

17. The method of claim 13, further comprising:
receiving the signal from an output of a power amplifier (PA).

18. A radio frequency (RF) transmission system, comprising:
an RF input terminal;
an RF output terminal; and
a measurement circuit coupled between the RF input terminal and the RF output terminal, wherein the measurement circuit includes:
a forward bridge coupled between the RF input terminal and the RF output terminal, wherein the forward bridge is to divert, to a forward detector, a portion of the power flowing from the RF input terminal to the RF output terminal, and
a reverse bridge coupled between the RF input terminal and the RF output terminal, wherein the reverse bridge is to divert, to a reverse detector, a portion of the power flowing from the RF output terminal to the RF input terminal,
wherein:
the forward bridge is coupled to the forward detector,
the reverse bridge is coupled to the reverse detector,
the forward bridge and the reverse bridge each include an electrical pathway through circuitry shared between the forward bridge and the reverse bridge,
a first input terminal of the forward detector is coupled to a first node in a first resistor network, and a second input terminal of the forward detector is coupled to a first node in a second resistor network,
a first input terminal of the reverse detector is coupled to a second node in the first resistor network, and a second input terminal of the reverse detector is coupled to a second node in the second resistor network, and
the circuitry shared between the forward bridge and the reverse bridge is coupled between the first and second resistor networks.

19. The RF transmission system of claim 18, further comprising:
an RF signal source coupled to the RF input terminal.

20. The RF transmission system of claim 18, wherein the portion of the power diverted to the forward detector is within a common mode rejection range of the forward detector.

21. The RF transmission system of claim 19, wherein the RF signal source includes a power amplifier (PA).

22. The RF transmission system of claim 18, further comprising:
an antenna coupled to the RF output terminal.

23. The bi-directional measurement circuit of claim 1, further comprising a power amplifier to which the RF input terminal is coupled.

24. The bi-directional measurement circuit of claim 1, further comprising an antenna to which the RF output terminal is coupled.

25. The circuit of claim 2, wherein:
the forward component is coupled between the RF input terminal and the second node; and
the reverse component is coupled between the RF output terminal and the fourth node.

26. The circuit of claim 25, wherein:
the forward component is coupled between the third node and the fourth node; and
the reverse component is coupled between the first node and the fourth node.

27. The circuit of claim 26, further comprising:
a fifth resistor coupled between the first node and the reverse component; and
a sixth resistor coupled between the third node and the forward component.

28. The RF transmission system of claim 18, wherein the first resistor network includes a first resistor and a second resistor in series between the RF output terminal and the first node of the first resistor network, and the first resistor network includes a third resistor coupled between the first resistor and the second node of the first resistor network.

29. The RF transmission system of claim 28, wherein the second resistor network includes a fourth resistor and a fifth resistor in series between the RF input terminal and the second node of the second resistor network, and the second resistor network includes a sixth resistor coupled between the fourth resistor and the first node of the second resistor network.