NATL INST OF STANDARDS & TECH R.I.C.

A1 11 03087564

Goodman, Alvin M/A 25-ky blas-lsolatlon QC100 .U57 NO.400-40, 1977 C.2 NBS-PUB-C SPECIAL PUBLICATION 400-40

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

Semiconductor Measurement Technology

A 25-kV Bias-Isolation Unit

for 1-MHz Capacitance and

Conductance Measurements
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards^ was established by an act of Congress March 3, 1901. The Bureau's overall goal i strengthen and advance the Nation's science and technology and facilitate their effective application for public benefit. To

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THE INSTITUTE FOR BASIC STANDARDS provides the central basis within the United States of a complete and con

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' Located at Boulder, Colorado 80302.
OF STANDAKJUB

Semiconductor Measurement Technology:

A 25-kV Bias-Isolation Unit for

1-MHz Capacitance and Conductance Measurements

Alvin M. Goodman

RCA Laboratories

Princeton, New Jersey 08540

SEP 1 1977

100

^peeled I~0biie^t/«?i7 ^OO-'^O - " /Jc. ^/C>c-HC

This activity was supported by

The Defense Advanced Research Projects Agency

and The National Bureau of Standards

U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary

Dr. Sidney Harman, Under Secretary

Jordan J. Baruch, Assistant Secretary for Science and Technology

'J. 5 NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director

Issued September 1977
Library of Congress Cataloging in Publication Data Goodman, Alvin M. A 25-kV bias-isolation unit for 1-MHz capacitance and conductance

measurements. (Semiconductor measurement technology) (NBS special publication ; 400^)

Supt.ofDocs.no.: €13.10:400-40

1. Semiconductors—Testing. 2. Electric capacity. 3. Electric conductivity. 4. Electric meters. I. Title. II. Series. III. Series: United

States. National Bureau of Standards. Special publication ; 400-40. QC100.U57 no. 400^ [TK787 1.85] 602'. 1 s [621 .38 1 5'2'028] 77-608 1 78

National Bureau of Standards Special Publication 400-40

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-40, 57 pages (Sept. 1977) CODEN: XNBSAV

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402

Price $2 Stock No. 003-003-01832-5
CONTENTS

PAGE

1. Introduction 1

2. Circuit 3

2.1, Functional Description 3 a. Bias-Protection Circuit 4

b. C/G-Meter Operation 7 c, Capacitance-Zero Circuit 9

d, Conductance-Zero Circuit 9

2.2, Measurement Accuracy 10

a. Basic Considerations 10

b. Equivalent Circuit 10

c. Capacitance Sensitivity Factors 12

(1) L = 0 13

(2) L ^ 0 13

d. Conductance Measurements 15

3. Experimental Results 16

3.1, General 16

3.2, Transient Suppression 16

3.3. Effect of the BIU on the Capacitance-Measurement

Accuracy 16

3.4. Effect of the BIU on the Conductance-Measurement

Accuracy 18

4. Application 20

5. Discussion and Conclusions 20

Acknowledgment 24

Appendix 25

References 49

FIGURE CAPTIONS

Figure 1. Schematic circuit diagram of C/G-meter biasisolation unit (BIU) 4

iii
FIGURE CAPTIONS (Continued)

PAGE

Figure 2. Schematic drawing of connections to C/G-meter BIU . 6

Figure 3. Simplified equivalent circuit of C/G-meter and BIU . 8

Figure 4. Simplified equivalent circuit of sample and BIU . . 11

Figure 5. Plots of relative sensitivity factor S(C) and

relative incremental sensitivity factor S'(C) vs C

with R = 100 and G/coC as a parameter 14

Figure 6. Plots of C^ (Cg) and S(Cg) , . . 17

Figure 7. Relative incremental sensitivity S'(C ) vs C , . . 19

Figure 8. Plot of G vs C 21

Figure 9. Plot of G^ - G^^ vs G^ . . . 22

Figure 10, Variation of capacitance and conductance with bias

for an MIS sample fabricated from n-Si on sapphire . 23

Figure Ml Front panel Capacitance/Conductance-Meter BiasIsolation Unit 26

Figure M2 Side panels 27

Figure M3 Rear panel 28

Figure M4 Chassis top and bottom covers 29

Figure M5 Shield 30

Figure M6 Shield cover 31

Figure M7 Drawing containing:

(a) Mounting bracket for L4,L5 32

(b) Zener diode heat sink 32

Figure M8 Acrylic support for "Capacitance Zero" assembly . , 33

Figure M9 Acrylic base 34

Figure MIO Acrylic insulator for top cover 35

Figure Mil Drawing containing:

(a) Acrylic insulator for shield rear 36

(b) Acrylic insulator for shield side 36

iv
i FIGURE CAPTIONS (Continued)

PAGE

Figure M12 Drawing containing:

(a) Acrylic insulator for chassis rear 37

(b) Acrylic insulator for chassis side . , . ... 37

Figure M13 PTFE terminal block 38

Figure M14 Drawing containing:

(a) HV assembly acrylic front 39

(b) HV assembly acrylic rear 39

Figure M15 HV assembly acrylic left and right sides ^0

Figure M16 Drawing containing:

(a) HV assembly acirylic bias-attenuator panel ... 41

(b) HV assembly diode mounting panel . 41

Figure M17 Top and bottom support panels for RIO and Rll ... 42

Figure M18 Drawing containing:

(a) Brass mounting post for "Capacitance Zero"

assembly 43

(b) Brass mounting post for speed-reducing drive

on C9 43

(c) Brass mounting post for speed-reducing drive

on CIO 43

Figure M19 Physical layout of components in high-voltage

section • 44

Figure Al Front view of Capacitance/Conductance-Meter

Bias-Isolation Unit 45

Figure A2 Top view with top cover removed 46

Figure A3 Top view of Capacitance and Conductance Zero

circuits with top cover and shield cover removed . . 47

Figure A4 Bottom view with bottom cover removed 48

LIST OF TABLES

Table 1. Electrical Parts List for C/G-Meter Bias-Isolation

Unit 5

Table 2. List of Mechanical Parts (not commercially available), 25

i

PREFACE

This study was carried out at the RCA Laboratories as a part of the

Semiconductor Technology Program in the Electronic Technology Division

at the National Bureau of Standards. The Semiconductor Technology Prograip serves to focus NBS efforts to enhance the performance, interchangeability, and reliability of discrete semiconductor devices and

integrated circuits through improvements in measurement technology for

use in specifying materials and devices in national and international

commerce and for use by industry in controlling device fabrication processes. The work was supported by the Defense Advanced Research Projects Agency* through the National Bureau of Standards' Semiconductor

Technology Program, Contract 5-35912. The contract was monitored by

R. L, Raybold as the Contracting Officer's Technical Representative

(COTR) and R. Y. Koyama as Assistant COTR.

Larger scale drawings of the mechanical parts are available on request

from the COTR, TECH-A-361, National Bureau of Standards, Washington,

DC 20234.

DISCLAIMER

Certain commercial equipment. Instruments, or materials are identified

in this report in order to adequately specify the experimental procedure.

In no case does such Identification imply recommendation or endorsement

by the National Bureau of Standards, nor does it imply that the material or equipment identified is necessarily the best available for the

purpose.

*Through ARPA Order 2397, Program Code 6D10

vii

Semiconduotov Measuvement Technology:

A 25-kV BIAS-ISOLATION UNIT FOR 1-MHz

CAPACITANCE AND CONDUCTANCE MEASUREMENTS

Alvin M. Goodman

RCA Laboratories

Princeton, N.J, 08540

Abstract: The measurement of small signal (differential)

capacitance (C) and conductance (G) at 1 MHz as a function of appliedbias voltage can be carried out with a commercially available capacitance/conductance (C/G) meter at moderate applied-bias voltage (^100 V)

,

However, C and G measurements of metal-sapphire-silicon capacitors for

characterizing silicon-on-sapphire require the use of much larger

applied-bias voltage.

This report describes a technique for using a commercially available

C/G-meter with a Bias-Isolation Unit (BIU) for C and G measurements at

bias-voltage magnitudes up to 25 kV without damage to the measurement

equipment. The basic principles of operation and the details of the

electrical design of a BIU are presented.

The use of the BIU imposes certain limitations on the range of sample

capacitance and conductance that may be measured without introducing

excessive error. The theory of these limitations is presented and

compared with experimental results obtained from the use of the BIU.

The measurement capability demonstrated by these results is adequate

for the intended silicon-on-sapphlre measurement application and may

be described in terms of a measurement range for a maximum added ewor>

due to the use of the BIU, For less than +1% added error in the indicated (measured) capacitance, the measurable range of the sample

capacitance is found to be from 0 to about 100 pF, In this application, it is also important to be able to accurately measure small

changes in the sample capacitance; for less than +1% added error in

the indicated (measured) value of a small change in the sample

capacitance, the measurable range of the sample capacitance is found

to be from 0 to about 38 pF, Conductance measurements may be made

with less than about 2% added error for samples whose capacitance

is in the range 0 to 50 pF,

Key Words: Bias-Isolation Unit; capacitance and conductance

measurements at high applied-bias voltage; capacitance/conductancemeter; capacitance-voltage measurements; electronics; extended-range

C(V) and G(V) measurements; high voltage C(V) and G(V) measurements;

MIS capacitors; modified MIS C(V) measurements; semiconductor devices;

silicon-on-sapphire measurements; SOS measurements.

1 . INTRODUCTION

A technique for using a commercial 1-MHz capacitance meter (C-meter)

for measurements at bias-voltage magnitudes up to 10 kV without risk

1
of damage to the measurement equipment has been described in a recent

report [1]. The technique involves the use of a Bias-Isolation Unit

(BIU) which allows the bias voltage to be applied to the sample, but

not to the C-meter, In addition, the BIU isolates the bias-voltage

supply from the high-frequency test signal and permits the capacitance measurement to be made without excessive error, A BIU of this

type has been used to carry out "modified" or extended-range MIS C(V)

measurements [2] of Al-sapphire-Si capacitors fabricated from siliconon-sapphire (SOS) [3], It was shown that such measurements can be

used to characterize SOS and the Si-sapphire interface [3] as well as

to determine the effects of oxidation and hydrogen annealing [4] and

exposure to soft X-rays [5] on the Si-sapphire interface.

In all of this work the sapphire substrates for the SOS were lapped

and polished to final thickness in the range 125 to 190 ym. Although

the +10 kV bias capability was sufficient for characterization of

Si on these sapphire substrates, it was clear that a larger bias

capability would be required if thicker substrates were to be used.

Since 2 in -diameter substrates used for production of integrated

circuits on SOS are typically 250 to 325 ym in thickness, and it was

anticipated that larger diameter substrates ranging up to '^^400 ym in

thickness would eventually be used, it was decided that a new BIU with

a larger bias-voltage capability should be developed. It is desirable

to be able to use these thicker sapphire wafers to characterize the

Si-sapphire interface since this would allow the characterization of

the same wafer on which devices are being fabricated or, alternatively identical starting wafers as monitors during device processing.

Thus, a primary objective of the present work was the extension of the

previously developed capacitance measurement capability to bias-voltage levels up to +25 kV for characterization of SOS,

The extended-range capacitance measurements can be used to determine

the Si-sapphire interface-state density [3] using point-by-point

differentiation of an experimentally derived quantity [6], It has

been shown that G(V) measurements (ac conductance measurements as a function of voltage) are capable of providing information about the

Si-Si02 interface-state density [7,8], This type of measurement had never been carried out on SOS nor was it clearly feasible; in fact, no instrumental capability for it existed. Accordingly, a secondary

goal of the present work was to provide an instrumental capability

for implementing and evaluating MIS G(V) measurements on SOS,

It is important to point out that while the accuracy requirements for

the MIS C(V) measurements were quite stringent since the data (or a quantity derived from the data) must be differentiated to obtain the

desired density of states information, the G(V) data is used directly.

Thus, although an error limit of about +1% on C(V) measurement was

sought, an error of +5 to 10% on G(V) would be reasonable for the

measurement purpose intended.

There is at the present time only one commercially available 1-MHz

C-meter that can also function as a conductance meter (G-meter) - the

2
PAR Model 410*. A modified version of the instrument was obtained for

the work described in this report. These modifications were:

(1) a lOX increase in the test signal level to produce

a similar increase in the signal-to-noise ratio of

the analog output signal, AC(V) and

(2) extra filtering to eliminate the effect of harmonics

in the test signal. This point is discussed in some

detail in reference 1.

In section 2, the BIU circuit is considered from the point of view of

both a functional description and the effect of the circuit on measurement accuracy. Some experimental results obtained using the BIU

are presented in section 3. An example of a typical measurement

application is presented in section 4. Finally, section 5 contains

some further discussion and conclusions.

The appendix to this report contains construction details and other

information intended for use by anyone who wants to duplicate the

BIU described in the body of the report,

2. CIRCUIT

2.1, Functional Description

A schematic circuit diagram of the C/G-meter BIU is shown in figure 1,

and the individual circuit elements are described in table 1,

Connections to the BIU are shown schematically in figure 2, The HI

side of the TEST and DIFF terminals of the BIU are connected together

and to the C-meter terminal marked INPUT. The LO side of the TEST

and DIFF terminals of the BIU are connected, respectively, to the

C-meter terminals marked DRIVE and NULL,

The capacitor to be measured is connected to the terminals marked

SAMPLE and the bias-voltage power supply is connected to the terminals

marked BIAS INPUT, If a guard-ring-electrode system is to be used on

the sample, the guard ring is connected to the terminal marked GUARD

and the guarded electrode must be connected to the HIGH side; the un- guarded electrode is connected to the LOW side. If the sample does

not have a guard ring, the terminal marked GUARD should be terminated

("blanked off") with an insulated, unwired mating connector to prevent surface breakdown or "arcing" during high-voltage operation of

the BIU.

The terminals marked 1000:1 ATTN BIAS should be connected to the

X-Axis of an X-Y recorder with an input resistance of 106 Q, for a directly calibrated measure of the bias applied to the sample.

*PAR (Princeton Applied Research Corp.) Model 410 CV Plotter. In the

present work, only the C/G-meter portion of the instrument is used.

3
| |FINE| |MEDIUM| |

) CO^NDUCTANCE^ J

Figure 1, Schematic circuit diagram of C/G-meter

bias-isolation unit (BIU)

The BIU performs three major functions: (a) bias protection;

(b) capacitance-zero adjustment; and (c) conductance-zero adjustment.

The portions of the circuit which perform these functions are indicated in figure 1, and described below,

a. Bias-Protection Circuit

The high and low terminals of the output to the C-meter are individually clamped by diodes (Dl and D2 on the high side, D3 and D4 on the

low side) to remain within some allowable range with respect to

groundo Each of the diodes Dl through D4 has low-forward resistance.

*A more detailed description of the bias-protection function is given

in reference 1,

4
Table 1. Electrical Parts List for C/G-Meter

Bias-Isolation Unit

Schematic Reference

R1,R2,R3,R4,R5

R6,R7

R8,R9

RlO.Rll

R12,R13

RIA R15,R16 R17,R18,R19,R20

R21 R22 R23 R24,R25

R26-R45 C1,C2,C3,C4

C5,C6,C7,C8

C9

CIO

D1,D2,D3,D4

L1,L2

L3L4,L5

J1,J2, J3,J4, J5

J6,J7,J8,J9

J10,J11,J12

SIS2

VRl

VR2 Fuse Power Supply

S3

Description (Commercial designation* If appropriate shown In parentheses)

5 X 10^ a, 1%, 12.5 W (Vlctoreen MOX 5)

5 X 105 Q, 10%, 2W

Use two resistors In series or parallel

to obtain 1000:1 attenuation with 10^ a load between JIG and Jll Series string of 50 1-Si @ 3 W, noninductlve

resistors

820 n, 10%, 2 W

100 a, 1%, 2 W

20 X 103 n, 5%, 2 W, noninductlve

5.1 X 103 Q., 5%, 2 W, noninductlve

106 Si, 5%, 2 W

20 X 103 a, 5%, 2 W, noninductlve

500 a, 5%, 2 W, noninductlve

10 turn, vernier adjustable carbon potentiometer 10^ Q, linear taper 510 a, 5%, 1/2 W

0.001 pF @ 50 kVDCW (Plastic Capacitors

0FN500-102, Extended Foil)

51 pF Silvered Mica @ 500 V

33-0-33 pF differential type variable

capacitor with speed-reducing planetary

drive (E.F. Johnson Type "L" No. 167-

0033-001) (Jackson Brothers Type 4511/DAF

planetary ball drive with 6:1 ratio) 2.2-10 pF variable capacitor with speedreducing planetary drive (E.F. Johnson

Type "L" No. 167-0001-001) (Jackson Brothers Type 4511/DRF dual ratio (36:1 and 6:1) planetary ball drive) Type 482A diode Special choke, 58 turns wound on C3 and C4 Special choke, 90 turns wound on C2 3-5.5 yH adjustable (North Hills type 120B) High-voltage coaxial chassis connector

(Amphenol type 97-3102A-18-420S)

Insulated BNC coaxial chassis connector

(Amphenol type 31-010) Insulated banana jack

SPST toggle switch

Ceramic insulated continuous shorting-type

switch (Centralab type PA-300 shaft and index assembly with type PA-13 ceramic switch

section) Type IN3305B Zener diode

Type IN3305RB Zener diode

Type 3AG-1A

Regulated with + and -15 V outputs

(Semiconductor Circuits Type 2.15.100) Ceramic Insulated 21-posltion shortingtype switch (Centralab Type PA4002)

*See Disclaimer on page vi.

5
\C/G

PAR MOD 410

DR^E NULL

I000:|

ATTN BIAS OUT

HIGH

SAMPLE

LOW GUARD HIGH ^ fl^ fi^

C/G METER BlU BJAS^JNrfBIAS In"" ^

6-zERo ffi^* omrnii

TO X-AXIS OF

X-Y RECORDER

TO BIAS

SOURCE

TO

SAMPLE

Figure 2. Schematic drawing of connections

to C/G-meter BIU.

6
high-reverse resistance, and fast turn-on. To reduce their loading

effect on the C-meter, they are normally maintained at a reverse bias

of 6,8 V, The bias voltages (+6.8 and -6,8 V) are provided with a very low source impedance by the Zener diodes, VRl and VR2,

The high-voltage blocking capacitors C3 and C4 are at (or nearly at)

series resonance at 1 MHz with LI + L4 and L2 + L5, respectively. Adjustment of L4 and L5 can be used to compensate for series inductance

of the connecting leads both inside and outside the BIU.

High-frequency noise from the bias supply is attenuated by the low-pass

filter formed by R6, R7, and CI. The resistors R3 and R4 and the ca- pacitor CI form a filter isolating the bias supply from the 1-MHz

measurement signal.

A bias voltage equal to that at the high side of the sample is available at J5 for application to a guard-ring electrode. The 1-MHz series

resonant circuit formed by L3 and C2 assures that the guard ring is

effectively grounded at the measurement signal frequency.

There is also in this portion of the circuit, a voltage divider formed

by Rl and R8 on the HIGH side and R2 and R9 on the LOW side which

serves to attenuate the bias input so that it may be fed directly to

the X-axis of an X-Y recorder. The voltage divider is arranged so that if the input resistance of the recorder is 10^ fi, the bias attenuation factor will be 1000:1. If a recorder with a different input

resistance were used, an appropriate correction factor could be calculated from the values of Rl, R2, R8, R9, and the input resistance,

b, C/G-Meter Operation

The operation of the C/G-meter in combination with the BIU is most

easily understood by referring to the simplified equivalent circuit

shown in figure 3.

Consider first the operation when C-Zero and G-Zero are "zero," i.e.,

they are effectively removed from the circuit, A 1-MHz oscillator

provides a modulation or drive signal to the sample under test as well

as a reference signal to the phase sensitive detector (PSD). The

sample as shown in figure 3 includes the bias protection circuit, the

effect of which will be considered in section 2,2, The current that

flows through the sample in response to the drive voltage is converted

to a voltage by the conductance, g, which is very large in comparison

with both the sample susceptance and conductance. The voltage developed across g is amplified by Ai and sjmchronously demodulated with

respect to the reference signal by the PSD, thereby producing a quasidc level (proportional to C or G) which is further amplified by A2 to

produce the signal labeled OUTPUT, If the mode switch is in position

G, the PSD will "recognize" only that component of the input signal

which is in phase with the reference signal. For a fixed magnitude

7
90«

PHASE SHIFT

JPG

NULL^

G- : zero; JZERO

MODE

SWITCH

^ DRIVE

I MHZ OSCILLATOR

HCaI SAMPLE (INCLUDING BIAS T \- T /PROTECTION CIRCUIT)

INPUT

AC

AMPLIFIER

g(»G, »u)C)

REFERENCE

SIGNAL

PHASESENSITIVE

DETECTOR

DC

AMPLIFIER

A2

ANALOG C OR G MUTPUT TO METER

ANND Y-AXIS OF

X-Y RECORDER

Figure 3. Simplified equivalent circuit of

C/G-meter and BIU.

8
of drive voltage, the output will be proportional to the conductance

of the sample. Similarly, if the mode switch is in position C,

the PSD will recognize only that component of the input signal which

is in quadvatuve with the reference signal. In this case, for a fixed

magnitude of drive voltage, the output will be proportional to the

sample capacitance C^. The output is used to feed both a panel meter

and an X-Y recorder, each of which is calibrated to read directly in

the appropriate units of C or G,

The discussion thus far has assumed that C-ZERO and G-ZERO are removed

from the circuit. We now consider the effect of including those circuit elements in figure 3, The voltage at the terminal marked NULL is

equal in magnitude to that at the DRIVE terminal but is 180 deg out of

phase with it. The currents through C-ZERO and G-ZERO can be used to

null or cancel those through C and G of the sample thereby allowing

zero correction or zero adjustment of both C and G. This is useful

not only for the usual nulling of stray capacitance due to the sample

holder and connecting leads, but also for operation in a suppressedzero mode, as is required for modified or extended-range MIS C(V)

measurements [2 through 6] and for the MIS G(V) measurements discussed in section 1, The actual capacitance-zero and conductancezero circuits shown in figure 1 are somewhat more complicated than

their simplified equivalents in figure 3; they are discussed in more

detail below,

c. Capacitance-Zero Circuit

Both large range and excellent precision of the capacitance-zero function are obtained by using three stages of adjustment, appropriately

labeled COARSE, MEDIUM, and FINE, The COARSE and FINE stages (C5-8

and CIO in fig. 1) provide a variable capacitance between the NULL and

INPUT terminals. The medium stage of capacitance-zero adjustment (C9)

is a capacitive divider between the DRIVE and NULL voltages (see

fig, 2) , capable of canceling out the minimum value of CIO plus the

stray capacitance of the wiring, thereby allowing the total capacitance-zero correction or adjustment range to include "zero," i.e,, no QOTvection,

The total range of capacitance-zero correction is approximately 250 pF.

To facilitate more precise adjustment, the shafts of C9 and CIO are controlled through speed-reducing planetary drives,

d. Conductance-Zero Circuit

Three stages of adjustment appropriately labeled COARSE, MEDIUM and

FINE are used to obtain both large range and excellent precision. All

three stages are resistive dividers between the DRIVE and NULL voltages.

The total range of the conductance-zero adjustment is greater than

300 umho (ysiemens) , The shafts of R24 and R25 are controlled through

9
speed-reducing planetary drives; this allows a more precise adjustment of the conductance zero.

2.2 Measurement Accuracy

a. Basic Considerations

The use of the BIU places certain constraints upon the range of sample

capacitance and conductance values which can be measured, and the

accuracy with which these measurements can be made. In what follows we shall first, consider a simple equivalent circuit for the combination of the sample and the BIU, and second, derive expressions describing the deviation of the apparent or "measured" capacitance and

conductance values from the actual values as a function of the equivalent circuit parameters.

The C/G-meter measures the capacitive and conductive components of a sample admittance, Y, connected between its terminals, and displays

these values on a suitably calibrated linear scale reading directly in

units of capacitance (usually pF) or conductance (usually ymho).

Let us define this value of admittance as:

where B is the susceptance of C.

When the C/G-meter is used with the BIU to measure the same sample, the

equivalent circuit is one in which the sample appears to be in series

with a resistance, R, and (possibly) a reactance, X. This is illustrated in figure 4. The resistance is due principally to the sum of RIO +

Rll in figure 1. There may also be a small contribution due to the

resistance in the windings of LI, L2, L4, and L5, and in the blocking

capacitors C3 and C4. The reactance, X, is equal to the difference between the inductive reactance of the sum of the circuit inductances

(Ll + L2 + L4 + L5 + lead inductance) and the capacitive reactance of

the series combination of C3 and C4. It was shown in reference 1 that

there is no advantage to X being capacitive (negative); in practice,

we would like it to be either zero or slightly inductive. We shall,

therefore, treat it as if it were due to an "excess" inductance, L.

The admittance "seen" by the C/G-meter; i.e., the apyavent adnrittanoe of the sample, may be written in the form

b. Equivalent Circuit

A Y E G + iB = G + iwC, (1)

A

G,AAA + iB, = G, + iwC,A

(2a)

10
R

-VW\r

BlU

G 1

} SAMPLE

B-tuC

Figure 4. Simplified equivalent circuit

of sample and BIU.

11
where

P ^ G(l+RG)+a3^RC^

A 2 112 U 1 1 1111 \^")

1+00 R C -2oo LC+w X C +2RG+(R +00 L )G

and

C \ ^ C(l-uj^LC)-LG^ (2c) ^ " l+2RG+R^G^+oo^L^G^-2a)^LC+(oo^R^+oo^L^)C^

Note that these equations (2a, 2b, and 2c) consider the effect of

sample conductance, G, which was in a previous analysis [1] assumed to

be zero,

c. Capacitance Sensitivity Factors

We may define a relative sensitivity factor for capacitance

measurements S(C).

S(C) E B^/B (3a)

S(C) = (1-AC)-LG^/C(3^^

(l-w LC+RG) + (wLG+ooRC)

This gives the ratio of the apparent value of the capacitance that

would be measured by the C-meter when used with the BIU to the actual

value C which would be indicated by the C-meter alone. In "extendedrange" or "modified" MIS C(V) measurements [2], it is necessary to

determine small changes in the capacitance of a sample under test. It

is, therefore, of interest to derive an expression for the relative

inovementdl sensitivity factor which we shall call S'(C).

(l-oo\c+RG)^ - (ooLG+ooRC)^ ....

15 (.c; = T— (4b;

[(1-00 LC+RG) + (ojLG+ooRC) ]

This gives the ratio of the apparent value of a small change in C that

would be indicated by the C-meter when used with the BIU to the actual

value of the small change in C that would be indicated by the C-meter

alone. Ideally, of course, both S(C) and S'(C) should be equal to 1.00

for all values of C, but this could be true only for L and R equal to

zero; i.e., without the protection circuit to which R is essential.

12
The extent to which each of the sensitivity factors differs from 1.00

may be thought of as an added error due to the use of the BIU.

It is helpful to consider two separate regimes, (1) L = 0, and (2)

L 7^ 0.

(1) L = 0

In this regime eqs (3b) and (4b) reduce to

S(C) = ^-i T (5)

(1+RG) + (coRC)

s.(c) =_ii±EG)i^jA!ci

[(1+RG)^ + (a)RC)^]^

Clearly, to avoid significant variation of S(C) and S'(C) from 1.00, it

is necessary that RG << 1 and ojRC << 1. In previous work involving

capacitors fabricated from SOS, the electrode diameter was 0.800 cm,

giving an area of 0.5027 cm^. The anticipated range of sapphire thickness to be used in future measurement was as discussed in section 1,

from 125 to '^400 ym. The maximum capacitance to be expected was,

therefore, about 38 pF, using £ = 10.6 Eq for the dielectric constant

of sapphire. Further, for an MIS sample, it is expected that the

maximum value of G will always he less than wC/2, [7]. It follows

then that for the values C — 38 pF and R = 100 (see fig. 1 and

table 1) the upper bounds on the maximum expected values of RG and toRC would be (uRC)]^ ^ 0.024 and (RG)maX = 0.012.

This could result in a significant error in S(C) and S'(C) if the

value of G were to approach coC/2. Plots of S(C) and S'(C) are shown

in figure 5 for several values of the parameter G/caC. Note that for

G/a)C ^ 0.1 the error in S(C) and S'(C) will be very small.

(2) L 0

It is convenient to write eqs (3b) and (4b) in the form

S(C) =

- ^^^^ J

(7)

(1-aC+Y) + (a6C+xC)

S. (c) = (1-aC+y)^ - (a6C+xC)^

[(1-aC+Y) + (a6C+xC) ]

13
Figure 5. Plots of relative sensitivity factor S(C)

and relative incremental sensitivity factor S'(C) vs

C with R = 100 ^ and G/coC as a parameter.

where the definitions and approximate maximum values of aC, xCj Yj and

6 in the range 0<C<100 pF are:

aC = (jo\c < 0.02,

XC = wRC ^ 0.06,

Y = RG ^ 0.015, and

6 = G/wC < 1/2.

(9a)

(9b)

(9c)

(9d)

Equations (7) and (8) may be simplified by carrying out the indicated

operations and retaining only linear terms in aC and y» and quadratic

terms involving xC.

S(C) = H-aC(l-6")-2Y-x"C

2^2 (10)

S'(C) = l+2aC-2Y-3x^C2^2 (11)

14
For non-zero a, both S(C) and S'(C) are increasing functions of C at

low values of C; go through maxima and become decreasing functions, of

C. If G were small enough to be ignored, the terms involving 6 and

Y could be dropped and eqs (10) and (11) would reduce to eqs (7a)

and (7b) of reference 1, where the symbol 3 is used instead of It was shown there that an appropriate amount of excess inductance, L, can be used to increase the measurable range of C without exceeding a set of preassigned error limits on either S(C) or S'(C). The same technique would be applicable here if G were small enough so that 6 and

Y could either be ignored or limited by smaller maximum values.

d. Conductance Measurements

Examination of eq (2b) reveals that even when G=0^ there is an apparent conductance, Ga, due to the series resistance, R, and the

capacitance, C. The contribution" of C to G^ is

2 2 = ^iL^c n 2)

AC 2 2 2

(1-0) LC+RG) + (wLG+ojRC)

We may define the "measured conductance" G,, as M

S " ^A " ^AC

G(1+RG)

G„ = ^ (l-oj^LC+RG)^ + CwLG+oaRC)^

-We may use eqs (9a) through (9d) to obtain the approximate form

G^ ^ G(l-Y+2aC-2x^C^) (13)

and G^^ ^ co^RC^ (l-2Y+2aC-2x^C^)

where the expression in parentheses differs from loOO by not more than

about 4% in the range 0<C<100 pF. Thus, to a reasonable approximation for the present application

^ = ^A - ^AC (1^)

and G^^ ^ w^RC^, (15)

15
3. EXPERIMENTAL RESULTS

3.1. General

The BIU described in section 2 was tested to ensure that it would

properly perforin the desired bias-protection (transient-suppression)

function and that the accuracy of measurements made with it would not

be excessively degraded. These tests and their results will now be

described,

3.2, Transient Suppression

The experimental arrangement for testing the transient-suppression

capability of the BIU is essentially the same as that shown in

figure 6 of reference 1. A test capacitor periodically short-circuiting

under high bias (25 kV) is simulated by a motor-driven spark gap. The

resulting transient voltage at the C/G-meter BIU output terminals is

picked up with a probe and displayed on a fast oscilloscope. The voltage from each terminal to ground was checked individually for each

polarity of applied bias and was found to have a peak value less than

+110 V without the C/G-meter connected. When the C/G-meter was con- nected (as shown in fig. 2) the peak value of the transient voltage

observed at each terminal decreased by more than an order of magnitude.

Thus, the C/G-meter is probably overprotected in the sense that RIO and

Rll in figure 1 are somewhat larger than necessary to achieve the re- quired transient suppression.

3.3. Effect of the BIU on the Capacitance-Measurement Accuracy

In section 2.2 the effect of the BIU on the accuracy of C-meter measurement was considered from a theoretical point of view. The actual

effect was determined experimentally by measuring S(Cs) and S'(Cg),

where Cg is a standard capacitance for which a precision decade capacitor was used. This 3-terminal capacitance standard has an accuracy of

0,25% for each of its component capacitors. The output of the C-meter

was read on the 10- in scale of an X-Y recorder having an accuracy of

0,2% of full scale. Prior to the measurements of S(Cs) and S'(Cg), the

C-meter was calibrated on the appropriate scales by connecting the

standard capacitor diveofly to the C-meter (i,e,, with the BIU out of

the circuit), and following the manufacturer's calibration instructions.

After the completion of the C-meter calibration procedure, the standard

capacitor was connected to the C-meter through the BIU and through the

high-voltage leads connecting the sample holder and test chamber [9]

to the BIU, With Cg = 50 pF, L4 and L5 were adjusted to make C^. ex- actly 50 pF, This is equivalent to setting L slightly larger than zero

(L^0,5 yH),

The value of C^ was then determined as a function of Cg and S(Cg) was

computed for each data point. The results are shown in figure 6, Also

16
17
shown in this figure for comparison are plots of eq (5) for G = 0 when

there is no stray capacitance present, and when the stray capacitance,

Cq, is 50 pF, This will be discussed further in section 5.

It was not possible to obtain S'CCg) directly. Therefore, the followin

approximation was used: S*(Cg) = (measured increase in the value of

Ca due to an increase of 6Cs)/6Cs. For the measurements discussed here

6Cs = 1 pF, The actual measurement procedure was as follows: (1) a value of Cg was set on the standard capacitor; (2) the capacitance and

conductance readings were reduced to zero using the CAPACITANCE ZERO

and CONDUCTANCE ZERO controls; (3) the sensitivity of the recorder was

increased by a factor such that an additional 1 pF should cause fullscale deflection on the recorder; (4) capacitance and conductance

readings were again adjusted to zero; (5) the standard capacitor was

increased by 1 pF; and (6) the value of S'(Cs) was read directly from

the recorder with full-scale deflection corresponding to S' = 1,00,

If the deflection exceeded full scale by more than 1% (the available

recorder over-range) the sensitivity was reduced by a factor of 1/2,

in which case, half-scale deflection corresponded to S* = 1,00,

A plot of the experimentally determined S'(Cg) is shown in figure 7,

For comparison, the figure also shows the theoretical expression,

eq (6), for S(Cs) based on the simplified equivalent circuit with

L = 0 and G = 0, The solid line is for the case when the stray capacitance Cq is zero; the dashed line is for the case when Cq = 50 pF,

Clearly neither of these plots is a good fit to the experimentally

determined values of S'. This will be discussed further in section 5,

3.4. Effect of the BIU on the Conductance-Measurement Accuracy

According to eq (15), the apparent conductance due solely to the series

resistance R and the capacitance is

However, C is the sum of the standard capacitance Cg and the stray

capacitance Cq, Among the contributions to Cq are stray capacitances

among leads and components in the BIU, capacitance between the sample

base in the test chamber and the probe which contacts the sample, capacitance between the high- and low-side leads in the test chamber, and

the "zero capacitance" (3 pF) of the standard capacitor when it is

connected.

Thus, when the standard capacitor is connected but Cg = 0, there is

already a contribution to the conductance

which would normally be suppressed by adjusting the CONDUCTANCE ZERO

18

controls to produce a zero conductance reading (G^ = 0), Adding increments of Cg should then produce a variation of according to eq (17)

A good fit of eq (17) to the experimentally determined variation of

^AC (^s) obtained for the value Cq = 50 pF. This is shown in

figlire 8, The two data points at Cg = 50 pF correspond to two different ways of experimentally selecting Cg = 50 pF using the precision decade capacitor, viz., 50 pF (lower point) and 30 + 20 pF

(upper point).

Selected precision (1% accuracy) film resistors were used as conductance "standards" to check the accuracy of the approximation inherent

in eq (14). This was done by using the following procedure: (1) with

the standard capacitor connected and Cg = 0, Ca and Ga were set to zero

(2) a value of Cg was set on the standard capacitor; (3) Ga was set to

zero; (4) a conductance "standard" Gg was connected across Cg and the

resultant conductance G^ - Gag was determined. The results were virtually independent of Cg. The largest variation was between the results

obtained for Cg = 0 and Cg = 50 pF; these results are shown in figure 9

The results for Cg = 10,20,30, and 40 pF were intermediate between

those for Cg = 0 and 50 pF. Thus, the validity of eq (14) is con- firmed with less than 2% added error in the range 0<C <50 pF.

4. APPLICATION

An example of a typical application of the C/G-meter BIU is shown in

figure 10. Here, the results are plotted of MIS C(V) and G(V) measurements versus bias voltage for a capacitor fabricated from n-Si on a sapphire wafer of thickness ^ 305 ym. These data are typical of the

results obtained thus far with the equipment described in this report.

The bias range used for this sample, -15 kV to +15 kV is clearly sufficient to cover the desired measurement range. The + 25 kV capability

of the BIU should be more than adequate to cover the bias range re- quired for samples fabricated from Si on sapphire of the maximum thickness currently anticipated (^^400 ym)

,

5. DISCUSSION AND CONCLUSIONS

Although the performance of the BIU is adequate for implementing the

desired measurements, there are certain departures from ideality and

it is appropriate to discuss them here.

Equations (5) and (6) did not exhibit a good fit to the experimentally

determined S(Cg) and S'(Cg) respectively, as shown in figures 6 and 7.

Even when the stray capacitance of "^^50 pF, as determined in section 3.4

(fig. 8) was accounted for, the theoretical plots and the experimental

data were not in good agreement. Using eqs (3b) and (4b) instead of

20
21
50

o

/

E

=t 40 / 1 30 — /// 0 Gs«0

+ C«ve "50dF V/ V p 1

10

n //1 1 1 1 1 1 0 10 20 3 0 40 50 60

63 (yLLinho)

Figure 9. Plot of G - G vs

22
(11 >t> M

f\ \ til § o

rrl [ \ rnuj fw1

•-J c!>-i n-l r\\J

r"l-< *H r 1 \J CO11C

CO c!

r\\j

0) ti

M-l rj

CTl Tiw 1 1 fit

cd

cO

r 1 •H

J-i

Oo

0)

fl iH o P. •H

4-1 CD •H

COH > c • o

iH o

0) M-l

!-i 3 CO bO CO •H

23
eqs (5) and (6) to take the excess Inductance into account, would improve

the agreement only slightly, at best. However, the simplified equivalent circuit (fig. 4) used for the theoretical analysis assumes only

lumped constant elements. The distributed capacitances and inductances

of the actual circuit may contribute significantly to the observed disagreement. Despite this lack of agreement, there is a sufficient range

of measurement capability which may be described in terms of an added

error due to the use of the BIU, For less than +1% added error in the

measured capacitance, C^, the measurable range of the sample capacitance

is foimd to be from 0 to at least 100 pF. For less than +1% added error

in the measured value of a small change in the sample capacitance,

the measurable range of the sample capacitance is found to be from

0 to about 38 pF.

In conclusion: (1) A technique has been described which allows the

safe operation of a commercially available C/G-meter for characterization of silicon-on-sapphire by capacitance and conductance measurements at applied-bias voltage levels up to +25 kV. (2) The technique

requires a BIU for which the circuit, theory, and practical results

have been presented. (3) Details of construction of the BIU are provided in the appendix.

ACKNOWLEDGMENT

1 am indebted to Chester J. Halgas for the mechanical design and the

construction of the bias-isolation unit described in this report, and

to James M, Breece for assistance with sample preparation and some of

the measurements.

24
APPENDIX

This appendix contains information which is intended for use by anyone

who wants to duplicate the BIU described in the body of the report. It

consists of:

(1) A list of the mechanical parts which are not commercially

available.

(2) detailed drawings of those parts, and

(3) a drawing and photographs showing the placement of all

parts.

Table 2. List of Mechanical Parts

(not commercially available)

Part Drawing

No, Part Description No.

1. Front panel Ml

2. Left side panel M2

3. Right side panel M2

4. Rear panel M3

5. Top cover M4

6. Bottom cover M4

7. Shield M5

8. Shield cover M6

9. Mounting bracket for L4,L5 M7

10. Acrylic support for "Capacitance Zero"

assemb ly M8

11. Acrylic base M9

12. Acrylic insulator for top cover MIO

13. Acrylic insulator for shield rear Mil

14. Acrylic insulator for shield side Mil

15. Acrylic insulator for chassis rear M12

16. Acrylic insulator for chassis side Ml2

17. PTFE terminal block M13

18. H.V. assembly acrylic front M14

19. H.V. assembly acrylic rear M14

20. H.V. assembly acrylic left side Ml5

21 H.V. assembly acrylic right side M15

22. H.V. assembly acrylic bias attenuator panel M16

23. H.V. assembly acrylic diode mounting panel Ml6

24. Top support panel for RIO and Rll Ml7 25. Bottom support panel for RIO and Rll M17

26. Brass mounting post for "Capacitance Zero"

assembly (4 required) M18

27. Brass mounting post for speed-reducing drive

on C9 (2 required) M18

28. Brass mounting post for speed-reducing drive

on CIO (2 required) M18

29. Zener diode heat sink M7

25
26
i- lil U- a

(U

•H

CO

CM

•H

27
- V

Q

/

3^,

5 Eli

U- a

u

(U

S

(U

00

•H

PC4

28
col >

a tu 2

<

a. 9

2

(3

y 5

4

5 ye

I- ° Si V

° kL _g

o

COu

>

o

oo

o

fto

4J

CO •H

CO

CO

cd

u

W)

•rl

PC4

29
0) •H

30
OO

r

r

8

-®- @-

oo

o

o

v3

-(J)'

A

0^

o

:r

o

O

o

2

CO >

in

£

o

2

3

•H

•H

t"

31
IS

i

I

o

f I 3

cD >

q

{A

U) -2

U)j4

3

OD >

o

O

0

if) J

«50 m

1=1 hJ •Ha

•H

CO 4Jco

o

4-1 60 <U

CO

M (Uo

60 -H 0 T3 S

(Uu

d60^

•H m

S to

32
5o

<Z -

\0 >^ cV2 oo0 o 1 cr <^ < - ^ dOQQ.

(Xo

I/) Ua<

CD

Q)>1J o2q oN

01a

4-) •HO

CO

cx, U

i-i Oo

CJ •Ho

00g

0)3M

•H

fa

33
1'

a

'® —

no-}>

osiONS o d

2

o

J v5 3- 2

u<

-iL^k

-00?——rl-

-.J 1

o

34
O

2

r tI

r. J

35
•J) r-o >2Jyo o to r)

0) •H

^-1 CO • • 13 T3

bO

H tH

0) 0) •H •H •H d

•H

w CO

«0 M !-) d o O o M-( o

!-i

M

W)

O

O

P! 4J •H to CO S rH tH

cdM CO CO P

•H •H • a a

•H •H iH H S

0) o O

i-l < <!

13 •H to

36
Vj QJ cd X)

(1) •H U CO

CO CO •H •H m CO

G CO CO •H CO CO C

•Ha o

nJ p >-< y> 0 o o o CW <4-l o

bO o o a 4-1 4-J •H cd CO iH iH 3

CO CD

Qd

•H •H • O a

•H •H

I—

s M O O U <

•H CCJ

37
38
[0

0—0-

—

4J • C

O CO

t-i cu

^-^ !-< o O

•H •H iH rH U u O O

a CO •H•H

nJ 4J -i C 0) 0) o CO CO o CO CO

CO CO

•H a Q —

(UM

:360

•H

39
-f

W5 >< o s h

c52 2< <

•V a

Ui

-1

CO0) -a

•H

0}

00

•HU

'X3

14-1 (UO

•HO

rHww

cd

in

0)

V4a

•H

40
9.875- i

JSo

f76f

.75 4-

2 SKV E. I U

HV AssE/v\e,LV Acievuc

DiQOE' iTMoOMTvM6, PAfOEL

.I2& —

I.2S

1

QOftUTiTv : I c-c EACH -\ -^^e HOLe~s ; ® . 1 2S DiA

3.5o

4 00

(— ./Z5

- 9.'<76

-3 ooHV ASSfcrvifeLS' ACeVLlC

BIAS i^irgMu^-TOR T».^^EL

Figure M16. Drawing containing:

(a) HV assembly acrylic biaS'-

attenuator panel.

(b) HV assembly diode mounting

panel.

41
42
2,75

Bgftf'S.S rv\QOk^TiK>(s, Post F<>e

.Die^LL ^TAP /2"l)E^P foe

-2.00-

./87

2SK\/ 6IU

i^"^ b - e-b PC I lor^ I; (2 y

,312. -Jt_

(2oD

/ bO

ggi^ss nAQumif^^fe, Post fg^^

oki c lo

'

QTV CEQ -2.

Figure M18, Drawing containing:

(a) Brass mounting post for "Capacitance

Zero" assembly.

(b) Brass mounting post for speed-reducing

drive on C9.

(c) Brass mounting post for speed-reducing

drive on CIO.
44
Figure Al. Front view of capacitance/conductanceMeter Bias-Isolation Unit.

45
Figure A2. Top view with top cover removed.

46
! /

>. /

Figure A3. Top view of capacitance and conductance

zero circuits with top cover and shield cover

removed.

47
i % Y

Figure A4. Bottom view with bottom cover removed.

48
REFERENCES

1. Goodman, A. M. , Semiconductov Measurement Technotogy: Safe

Operation of Capacitance Meters Using Kigh Applied-Bias Voltage,

NBS Special Publication 400-34, December 1976.

2. Goodman, A, M, , A Useful Modification of the Technique for

Measuring Capacitance as a Function of Voltage, IEEE Trans,

Electron Devices ED-21 , 753-757 (1974)

3. Goodman, A, M, , An Investigation of the Silicon-Sapphire Interface

Using the MIS Capacitance Method, IEEE Trans, Electron Devices

ED-22 , 63-65 (1975).

4. Goodman, A, M, and Weitzel, C. E,, The Effects of Oxidation and

Hydrogen Annealing on the Silicon-Sapphire Interface Region of

SOS, IEEE Trans, Electron Devices^ ED-24 , 215 (1977).

5. Goodman, A. M. and Weitzel, C. E., The Effect of Electron Beam

Aluminization on the Si-Sapphire Interface, Submitted for publication in Appl. Phys. Letters,

6. Terman, L, M, , An Investigation of the Surface States at a Silicon/Silicon Oxide Interface Employing Metal-Oxide-Silicon

Diodes, Solid-State Electron, 5_, 285 (1962).

7. Nicollian, E. H. and Goetzberger, A., MOS Conductance Technique

for Measuring Surface State Parameters, Appl, Phys, Letters

216 (1965).

8. Nicollian, E. H. and Goetzberger, A., The Si-Si02 Interface

Electrical Properties as Determined by the MIS Conductance

Technique, Bell Syst, Tech, J. 46, 1055 (1967).

9. Goodman, A. Mo, Semiconductor Measurement Technology: Suppression

of Premature Dielectric Breakdown for High-Voltage Capacitance

Measurements, NBS Special Publication 400-37.

49
NBS-n4A (REV. 7-73)

U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. Special Publication 400-40

2. Gov't Accession

No.

3. Recipient's Accession No.

4. TITLE AND SUBTITLE

Semiconduotor Measurement Teohnology : A 25-kV Bias-Isolation

Unit for 1-MHz Capacitance and Conductance Measurements

5. Publication Date September 1977

6. Performing Organization Code

7. AUTHOR(S)

Alvin M. Goodman

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

RCA Laboratories

Princeton, New Jersey 08540

10. Proiect/Task/Work Unit No.

11. Contract/Grant No. 5-35912

1 2. Sponsoring Organization Name and Complete Address (Street, City, State, ZIP)

NBS - Washington, D. C. 20234

ARPA - Arlington, Virginia 22209

13. Type of Report & Period Covered

14. Sponsoring Agency Code

15. SUPPLEMENTARY NOTES This work was funded by the Defense Advanced Research Projects

Agency under ARPA Order 2397, Program Code 6D10.

Library of Congress Catalog Card Number: 77-608178

16. ABSTRACT (A 200-word or less (actual summary of most significant information. If document includes a significant

bibliography or literature survey, mention it here.) The measurement of small signal (differential) capacitance (C) and conductance (G) at 1 MHz as

a function of applied-bias voltage can be carried out with a commercially available capacitance/

conductance (C/G) meter at moderate applied-bias voltage (^100 V). However, C and G measurements

of metal-sapphire-silicon capacitors for characterizing silicon-on-sapphire require the use of much

larger applied-bias voltage.

This report describes a technique for using a commercially available C/G-meter with a BiasIsolation Unit (BIU) for C and G measurements at bias-voltage magnitudes up to 25 kV without damage

to the measurement equipment. The basic principles of operation and the details of the electrical

design of a BIU are presented.

The use of the BIU imposes certain limitations on the range of sample capacitance and conductance that may be measured without introducting excessive error. The theory of these limitations

is presented and compared with experimental results obtained from the use of the BIU. The measurement capability demonstrated by these results is adequate for the intended silicon-on-sapphire

measurement application and may be described in terms of a measurement range for a maximum added

error due to the use of the BIU. For less than ±1% added error in the indicated (measured) capacitance, the measurable range of the sample capacitance is found to be from 0 to about 100 pF. In

this application, it is also important to be able to accurately measure small changes in the sample

capacitance; for less than ±1% added error in the indicated (measured) value of a small change in

the sample capacitance, the measurable range of the sample capacitance is found to be from 0 to about 38 pF. Conductance measurements may be made with less than about 2% added error for samples

whose capacitnace is in the range 0 to 50 pF.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name; separated by semicolons) Bias-isolation unit; capacitance and conductance measurements at high applied-bias voltage; capacitance/conductance-raeter; capacitance-voltage measurements;

electronics; extended-range C(V) and G(V) measurements; high voltage C(V) and G(V) measurements;

MIS capacitors; modified MIS C(V) measurements; semiconductor devices; silicon-on-sapphire measurements; SOS measurements.

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