A111D3 fl710fi

NATL INST OF STANDARDS & TECH R.I.C.

A1 11 030871 08

Rubin, Sherwin/Thermal resistance measur QC100 .U57 NO.400-14 V1979;C.2 C

-NBS SPECIAL PUBLICATION 400-14

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

1-14
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liRMMl IwiM 0f Vmimm

JUN ^ ^ )m

)0l

Semiconductor Measurement Technology:

Thermal Resistance Measurements on Power Transistors

Sherwin Rubin and Frank F. Oettinger

Electron Devices Division

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, DC 20234

U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary

Jordan J. Baruch, Assistant Secretary for Science and Technology

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director

Issued April 1979
Library of Congress Cataloging in Publication Data

Rubin, Sherwin. Thermal resistance measurements on power transistors. (Semiconductor measurement technology) (NBS special publication , 400-14) Supt. of Docs, no.: C 13.10:400-14

1. Power transistors—Thermal properties. 2. SemiconductorsJunctions. I. Oettinger, Frank F., jointauthor. II. Title. III. Series.

IV. Series: United States. National Bureau of Standards. Special

publication ; 400-14. QC100.U57 no, 400-14 [TK7871,92] 602Ms [621.3815'2] 79-9984

National Bureau of Standards Special Publication 400-14

Nat. Bur. Stand. (U.S.), Spec. Pub). 400-14, 69 pages (Apr. 1979) CODEN; XNBSAV

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For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402

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TABLE OF CONTENTS

Page

Abstract 1

1. Introduction 1

2. The Concept of Thermal Resistance 2

3. Electrical Measurement of Thermal Resistance 3

3.1 Continuous Electrical Methods 3

3.2 Switched or Pulsed Methods 4

4. Preferred Electrical Measurement Method 7 4.1 Measurement Procedure 7 4.2 Test Circuit Description 8

4.3 Special Precautions and Considerations 11

4.3.1 Measuring Current Considerations 11

4.3.2 Oscillations in the Device Under Test 12

4.3.3 Operating Conditions of the Device Under Test . . 12

4.4 Simplification of Measurement Procedure for Industrial

Use 18

4.4.1 Simplified Calibration Procedure 18

4.4.2 Simplified Extrapolation Procedure 18

5. Thermal Response Measurements for Die Attachment Evaluation . 20

6. Conclusions 21

7. References 23

Appendix I 25

Appendix II 39

Appendix III 45

Appendix IV 59

Appendix V 61

iii
LIST OF FIGURES

Page

1. Basic circuits for measuring thermal resistance by the

emitter-only switching technique 9

2. Block diagram for the emitter-only switching circuit used

to measure npn transistor thermal resistance 10

3. A 125-W power transistor coated with a thermographic phosphor shown for two different operating conditions, each

dissipating 50 W 13

4. Measured thermal resistance as a function of collector current at a constant power of 20 W for a 35-W triple-diffused

transistor 15

5. Cooling curves for a transistor operated with a collector

current of 4 A and various emitter-collector voltages .... 17

6. Block diagram for thermal response measuring system for

npn transistors 22

iv
PREFACE

This study, which resulted in a recommended procedure for measuring

the thermal resistance of power transistors, was conducted as part of

the Semiconductor Technology Program in the Electron Devices Division of

the National Bureau of Standards (NBS) . This Program serves to focus

NBS research to enhance the performance, interchangeability , and reliability of discrete semiconductor devices and integrated circuits through

improvements in measurement technology for use in specifying materials

and devices in national and international commerce and for use by industry in controlling device fabrication processes. This research leads to

the development of carefully evaluated and well-documented test procedures and associated technology. Special emphasis is placed on the dissemination of the results of the research to the electronics community.

Application of these results by industry will contribute to higher

yields, lower cost, and higher reliability of semiconductor devices.

Improved measurement technology provides a common basis for the purchase

specifications of government agencies which will lead to greater economy

in government procurement and, in addition, provides a basis for controlled improvements in fabrication processes and in essential device

characteristics. The Semiconductor Technology Program is carried out

with funds from a multiplicity of sponsoring agencies; the specific work

reported herein was funded by NBS,

The authors are indebted to several persons who assisted in the

editing and preparation of this report. David L. Blackburn performed a critical and constructive reading of the text. The figures were prepared by William A. Cullins and Leo R. Williams. The typing of the final draft was done by E, Jane Walters.

V
DISCLAIMER

Certain commercial equipment, instruments, or materials are identified in this report in order to adequately specify the experimental

procedure. In no case does such identification imply recommendation or endorsement by the National Bureau of Standards, nor does it imply that

the material or equipment identified is necessarily the best available

for the purpose.

vi
Semiaonduator Measurement Technology:

Thermal Resistance Measurements on Power Transistors

by

Sherwin Rubin and Frank F. Oettinger

Ahstvact: A brief description of the idealized concept

of thermal resistance is given along with the problems and

pitfalls encountered in applying the concept to power transistors. In addition, the advantages and disadvantages of

various electrical techniques for measuring junction temperature (thermal resistance) are described, and a preferred,

standard technique is discussed in detail. This preferred

technique, in which the forward-biased emitter-base junction is used as the temperature-sensitive parameter, is us- able on all types of bipolar transistors. The measurement

procedure is relatively simple and lends itself to industrial measurements as well as for referee purposes. The power

interruption circuitry is also relatively fast and simple

since only one device terminal is switched. The preferred

technique that was developed for measuring the thermal re- sistance of power transistors has been adopted as EIA Recommended Standard RS-313-B on Thermal Resistance Measurements

of Conduction Cooled Power Transistors, dated October 1975.

Key Words: Current crowding; die attachment evaluat ion

:

junction temperature; measurement technology; power transistors; semiconductor devices; thermal characterization; thermal resistance; transistors.

1. Introduction

The thermal characterization of power semiconductor devices is important for predicting the reliability and performance of these devices and

for ensuring their safe operation. Manufacturers usually specify a thermal resistance, Rg, and a maximum safe junction temperature, T^.^

The specified thermal resistance is assumed to be constant for each device and is used to calculate the device junction temperature as a function of power dissipation for a given mounting arrangement and case or ambient temperature. Ultimately, Rg is used to ensure that . is

not exceeded during operation. The effect of exceeding the ratet maximum safe junction temperature can range from a change in the electrical

characteristics of the device to catastrophic failure. Thus, a knowledge

of the operating junction temperature is critical for predicting device

quality, reliability, and performance. For speed and simplicity of production line screening and to enable device users to duplicate the measurements, electrical measurement methods are usually used for determining device thermal resistance. However, there are problems with this ap-
proach that had been brought to our attention by industrial standards or- ganizations, manufacturers and users of devices, and military and space

agencies. Measurements were not repeatable within the desired precision

due to the use of different test procedures and device operating conditions. The effect of current crowding on the accuracy of the electrical

measurement of thermal resistance was not widely understood. This led

to buyer-seller disagreements and in some cases to failure through misOn the recommendation of these semiconductor manufacturers and users

and of other government agencies, the National Bureau of Standards initiated a study of methods for nondestructively measuring the thermal re- sistance of power transistors in order to develop a satisfactory referee

test method. Based on the criteria that the method must be easy to perform, precise, nondestructive-, as accurate as possible, and usable at

the working level, the emitter-only switching technique (in which the

forward-biased emitter-base junction is used as the temperature-sensitive

parameter) was found to be the preferred procedure for measuring the thermal resistance of power transistors.

This paper discusses the concept of thermal resistance, its shortcomings, and the care that must be exercised when it is used for specifying or checking the thermal characteristics of a device. Electrical

techniques for measuring junction temperature (thermal resistance) of

power transistors are discussed in some detail with the emphasis on the

preferred method, now adopted as a standard technique [1] (reprinted

with permission of EIA in Appendix I)

Thermal resistance has been used over the years as an aid to device manufacturers and users for calculating the junction temperature

of operating devices. The concept of thermal resistance is based upon

an analogy between the electrical and thermal properties of materials,

with temperature, power dissipation, and thermal resistance being analo- \ gous to voltage, current, and electrical resistance, respectively. The

thermal resistance (ItL ) is defined as follows:

use

2. The Concept of Thermal Resistance

eJR

R

R

(1) 6JR P

where

R

eJR

= thermal resistance between the junction and the reference

point, in degrees Ceisius/watt

T temperatures of the junction and the reference point, re- spectively, in degrees Celsius, and

P = power dissipated in the device, in watts.
In applying the electrical analogy to the thermal problem and in using eq (1), it is implicitly assumed that uniform current and temperature distributions exist across the junction of the device under test

and that one-dimensional heat flow occurs from a planar heat source. These assumptions imply a unique value of thermal resistance for devices

of a given design and construction. Since these assumptions are not com- pletely valid for actual power transistors, care is needed in applying

the results of eq (1) to real devices [2],

3. Electrical Measurement of Thermal Resistance

Because a power transistor cannot always be characterized by a unique value of thermal resistance for all operating conditions due to

such effects as current crowding, it is very important to be able to measure the critical junction temperature for a variety of operating conditions. Ideally, the measurement method chosen should 1) yield a temperature as close to the peak junction temperature as possible, 2) be easy

to perform, 3) be precise, and 4) be nondestructive. The most commonly

used methods for measuring the junction temperature of a semiconductor

device utilize a temperature-sensitive electrical parameter (TSP) of the

device as the temperature indicator. Although electrical techniques do

not always directly yield the peak junction temperature, they are nondestructive, are generally simple to perform, and can be precise.

A number of electrical parameters, such as the forward-biased

collector-base voltage (V^^) , the d-c forward current gain (h^^) , the

collector-base leakage current (^q^q) » the forward-biased emitterbase voltage (Vgg) have been used as temperature indicators. In addition, various techniques have been used for monitoring each of these

parameters; all these techniques can generally be put into one of two

generic classes: 1) continuous methods and 2) switched or pulsed methods. Each of the techniques relies on the ability to simply and

uniquely relate the. TSP to junction temperature. The degree that this

is possible is a major factor in assessing the worth of a particular

technique. A brief description of the use of the various electrical

parameters as TSPs is given below followed by a detailed description of

a preferred technique which most closely meets the requirements of the

ideal measurement method. With minor modifications, the circuit used

for the preferred method for measuring thermal resistance can also be

used to measure the transient thermal response of devices [3], the thermal resistance of integrated Darlington power transistors [4], and the

quality of the die attach of devices (using the transient thermal response) [5].

3.1 Continuous Electrical Methods

In these methods, the TSP is monitored while the device is operating in an active, power-dissipating mode. In one version [6], the case,

ambient, or other reference point is elevated to a high temperature

(T2), not exceeding the maximum junction temperature. The collector

current (I^) is set and a collector-base voltage (V2) applied to the

3
device. The TSP is measured under these conditions and then the reference temperature is reduced to a lower temperature (Ti) and the

collector-base voltage increased to a value until the same value of

the TSP is measured as was measured above. The thermal resistance is

then

T2 - Ti

^6 ^ - V2) •

The dc current gain (bp„) [6] and the base-emitter voltage (Vg^) [7]

have been used as transistor TSPs for measuring temperature by the continuous method.

It is generally assumed with continuous methods that the TSP (h^g or V ) varies monotonically with temperature and that variations in

the TSP as a result of the changes in the temperature are much greater

than variations as a result of changes in the collector-base voltage

(V^g).* Unfortunately, both h^ and V^^ may be strong functions of

V^g, and it is often difficult to separate these electrical effects

from the desired thermal effects. For example, in the continuous

method, a correction for the Early effect [8] may have to be included

[9]. The added complexity required for this correction negates the apparent simplicity of the continuous V method. In addition, it has

been found that h^^ may not vary monotonically with V^^ because of

changes in the device current density as the collector voltage is varied

[10]. Thus, although the continuous methods appear at first glance to

be simple, they are not recommended for use in making temperature measurements of semiconductor devices because of the difficulties mentioned.

3.2 Switched or Pulsed Methods

Switched or pulsed electrical methods require that the device be

rapidly switched between a condition of high power dissipation and a condition of very low or zero power dissipation. In switched methods,

the TSP is monitored during the low power dissipation condition immediately after the removal of a high power dissipation d-c operating condition. The calibration of the TSP against junction temperature is performed at the low power condition. In pulsed methods, the TSP is monitored during the high power dissipation d-c condition, while calibration

of the TSP against junction temperature is performed by monitoring the

TSP during a very short pulse at the same high power level. In both

techniques, it is assumed that the junction temperature rise above the

reference is negligible during the calibration procedure. The switched

methods achieve this by a very low power dissipation, while the pulsed

methods achieve this by a very short pulse of high power. Thus, the ref-

* An example of the use of this assumption can be found in Method 3132,

Thermal Resistance (DC Forward Voltage Drop, Emitter Base, Continuous Method) of MIL-STD-750B, February 27, 1970.

4
erence point temperature is indicative of the junction temperature under

these conditions. The transistor TSPs that have been used in measuring

thermal resistance by switched or pulsed methods are the collector-base

current (I^^q) [11]> the d-c forward current gain (h^^) [12], the

collector-base forward voltage (V__) [13], and the emitter-base forward

voltage (Vg^) [14].

Since h can be a double-valued function of temperature, it is not

recommended for use as the TSP. The switched method using I^^q the

TSP is generally limited to measurements on germanium devices having relatively large bulk leakage currents and is of no real interest for the ma- jority of modern silicon devices where surface and bulk leakage current

effects may be of the same order.

The switched methods which use V^^ or as the TSP are generally

equally precise. However, it has been found that when used as the

TSP tends to indicate a junction temperature nearer the peak temperature than does V^^, and, in addition, the switching techniques are simpler for the methods. In contrast to the other methods discussed,

the circuit variations used to implement the switched V techniques

are numerous [14,15,16]. It can also be shown that switched V^^ methods are simpler to perform than the pulsed methods and under conditions of current crowding tend to indicate a junction temperature nearer

to the peak temperature due to differences in calibration operating conditions. The switched V^^ technique that has been found to be the easiest to perform and to generally yield a temperature closest to the peak

junction temperature is one in which the device under test operates as

a transistor both during the heating and TSP monitoring or calibration

procedures . This approach has come to be known as the V^^ emitter-only

switching technique and is the preferred method for measuring the

junction-to-case thermal resistance (R )

.

9 J C

Table 1 presents a comparison of measurements of ^qjq using the

preferred V^^ emitter-only switching technique with other switching

techniques. The data were extracted from measurements made by the National Bureau of Standards for use in a preliminary round-robin experiment on thermal resistance conducted in cooperation with EIA-JEDEC Committee JC-25 on Power Transistors. These data illustrate the apparent

differences in thermal resistance when measured using a variety of electrical techniques. Eleven devices were measured. Three were encased in

TO-66 cans and eight in TO-3 cans. As expected, the technique gave

lower values of thermal resistance than the V „ base-ana-collector

switching technique, which in turn was lower than the V emitter-only

switching technique. It is this latter method that has been adopted as

a standard technique for measuring the junction temperature of power

transistors [1].

* This round robin was conducted under the auspices of Committee JC-25

on Power Transistors of the Solid State Products Division, Joint Electron Devices Engineering Council, Electronic Industries Association.

5
Table 1

Comparison of Different Electrical Techniques for Measuring

the Thermal Resistance of Power Transistors

Device

Number

Case

Type

Measured Thermal Resistance

(°C/W)

as ^CB

TSP

V

as

t BETSP

\b

as TSP

A

TO

1 .00 1 .09 1.41

B-1 TO

0 .74 0 .90 1.06

B-2 TO-3 0 . 96 0 . 99 1 . 24

B-41 TO0 .48 0 .53 0.71

B-42 TO-3 0 .46 0 .50 0.71

D-2 TO-3 0 .41 0 .48 0.56

D-3 TO-3 0 .41 0 .46 0.55

W-2 TO-3 0 .38 0 .40 0.61

W-3 TO-66 1 .69 1 .79 2.34

W-4 TO-66 1 .69 1 .79 2.40

D-4 TO-66 1 .47 1 .52 1.74

Base and collector switching (device under test is operated as a diode during TSP

monitoring or calibration)

Emitter-only switching.

6
4. Preferred Electrical Measurement Method

The emitter-only switching technique in which the forward-biased

emitter-base junction is used as the temperature-sensitive parameter is

usable on all types of bipolar power transistors. The measurement procedure is relatively simple and lends itself to industrial measurements

as well as for referee purposes. The power interruption circuitry is

also relatively fast and simple since only one device terminal is

switched. The technique also gives unambiguous results when current

crowding occurs

.

4.1 Measurement Procedure

In this method the emitter-base forward voltage (V^g) is used as the TSP to indicate the junction temperature. The test procedure involves the measurement of the TSP as part of two steps, the power application and the calibration steps. In the power application step, V is

measured to determine the increase in the junction temperature due to

power dissipation in the device under test. During the calibration step,

is measured to determine the temperature coefficient of the device

under test. A more detailed description of the measurement procedure

is given in Appendix I where EIA Recommended Standard RS-313-B on Thermal Resistance of Conduction Cooled Power Transistors is reproduced by

permission of the EIA. In this standard, the thermal resistance is given

as

:

ejR

T - T

_J R

^ (AVG)

\2 - \C "mC = \^

DP„

AV,MC

ATMC

-1

Calibration

(3)

where

:

^ejR ~ thermal resistance, junction-to-reference point, in degrees

Celsius/watt

,

T = junction temperature, in degrees Celsius,

J T = reference point temperature, in degrees Celsius,

P.. V = average heating power applied to transistor causing temperature difference T - T , in watts,

J R

P2 = magnitude of heating power applied to transistor, in watts,

~ value of TSP corresponding to the temperature of the junction heated by P_ and measured at the measuring current

(Ij^) , in millivolts,

D = heating power duty factor (^^1)

,

(AV^_/AT^_) = TSP temperature coefficient measured at L,, in millivolts/degrees Celsius,

T^-^Q ~ calibration temperature measured at reference point, in

degrees Celsius, and
V = values of TSP during calibration at and specific values

of T,,^ In millivolts.

MC

4.2 Test Circuit Description

There are two basic test circuits used for the emitter-only thermal

resistance measuring procedure. As can be seen In figure 1, the emitter

has two current sources, one attached permanently which provides the con stant measuring current and the other active only during the heating por

tlon of the test cycle. The switching action is provided by a switch

that either Interrupts the emitter current by opening the line (series

switching) or by shunting the emitter supply current to another path

(parallel switching) as indicated in figure la and lb, respectively.

The circuit in figure la offers no protection against reversebiased emitter-base breakdown which can occur during switching. It was

found that the process of rapidly reducing the emitter current from a very high value during heating to a very low value during measurement

while the collector remained connected to Its voltage supply could result in reverse-bias breakdown of the emitter-base junction of some transistors. Since the transistor may be damaged by reverse-biased

breakdown of the emitter-base junction [17], fast switching circuits

such as those needed for measurement of thermal resistance must be designed to avoid the possibility of such breakdown. A detailed explanation of the characteristics of the emitter-base voltage and current

transients which occur when switching the emitter with a series transistor during measurement of thermal resistance is given in Appendix II

together with a description of a proposed model.

Although the emitter-base voltage can be limited to a value below

the breakdown voltage with a protective circuit based on the use of a regulator (zener) diode, a better solution is to use the parallel switch

Ing scheme. In this method, the emitter-base voltage is limited to the

drop across the series diode Dl during switching. This method has the

added advantage that parallel switching is a far superior procedure for

high currents. For this reason, the preferred circuit for measuring the

thermal resistance of power transistors utilizes parallel switching in

the emitter lead to Interrupt the heating current to the device under

test (DUT).

The block diagram for the emitter-only switching circuit used to

measure the thermal resistance of npn transistors, utilizing parallel

switching in the emitter of the DUT, is given in figure 2.* The circuit

is controlled by a clock pulse with a pulse width of approximately 300

ys and a repetition rate of approximately A Hz. When the voltage level

of the clock pulse is zero, the transistor is off and the current

through the DUT is the sum of the heating current (switch S closed) and

* This test method can also be applied to pnp devices by appropriate

polarity charges in the test circuit elements.

8
DUT

CLOCK PULSE

Figure 1. Basic circuits for measuring thermal resistance by the

emitter-only switching technique. (a) series switching, (b) parallel

switching.

9
As-I <>-(

o

4-) CO •H

C9e-Jo

bO (1) •H ^

10
the measuring current 1^^. The constant heating current is furnished by

the supply, and the constant measuring current by the supply.

At the end of each heating power pulse, the clock assumes a specified

nonzero level for a period of time ("V/SOO ys) that is short compared with

the heating interval (^^^250 ms). This is sufficient to bias the transistor on, which reverse biases the diode Dl so that the heating current

no longer passes through the DUT. The function of the optional regulator (zener) diode Z is to decrease the switching time of the DUT. The

regulator voltage, v^,, of the diode Z should be equal to or less than

the maximum rated V q of the DUT. Tne sample-and-hold unit (S&H) is

triggered when the Heating current is removed and after a delay, usually

5 to 100 ys , senses the TSP, V^^^j ^ 1.5-ys period and displays its

value on the digital voltmeter XDVM) . The temperature coefficient of the

TSP and the calibration correlation voltage V (for T = T^) are obtained by making the required measurements with the heating current supply disconnected (switch open) . The digital voltmeter used to measure

the TSP is also used to measure the power dissipation of the DUT as indicated by the DVM switch S^. A noninductive current-sensing resistor R

is used to measure the collector current 1^.

Details of the instrumentation to implement the emitter-only

switching method for measuring the thermal resistance or power transistors are given in Appendix III. This appendix includes a description of

the basic circuit itself as well as a description of the clock pulse generator, the sample-and-hold circuit, the temperature controller, and the

temperature-controlled, water-cooled heat sink. Appendix IV describes

the results of long-term, single-operator measurements to check the re- peatability of the equipment for measuring thermal resistance described

in Appendix III.

4.3 Special Precautions and Considerations

There are several special precautions and considerations that must

be taken into account when measuring the thermal resistance of power

transistors. They generally relate to the nonideal characteristics of

semiconductor devices and interactions of the device under test with the

measuring system. They range from such questions as to how to pick the

measuring current to how to prevent oscillations in the device under test.

4.3.1 Measuring Current Considerations

As indicated previously, the measuring current is generally se- lected such that the TSP varies linearly with temperature over the range

of interest and that negligible internal heating occurs during the calibration procedure and measuring interval. A measuring current equal to

0.1 percent of the maximum rated collector current (I , .) of the device under test will generally meet this criterion. Ginlrilly, a measuring current of a few milliamperes is acceptable for the large majority

of medium power transistors.

11
It has also been found that, for some devices, the calibration curve deviates from its normally linear slope for junction temperatures above

150 to lyS^'C due to high leakage current effects. When this happens, a best fit linear line to the actual curve, over the temperature range of

interest, generally gives the required accuracy of measurement. If this

is not the case for the particular temperature range of interest, the actual calibration curve should be plotted and the junction temperature

due to internal power dissipation read off the curve.

4.3.2 Oscillations in the Device Under Test

The occurrence of oscillations in the device under test can make it

impossible to determine the actual power dissipation for calculations of

thermal resistance. Also, the measurement of the TSP within the re- quired time after the heating power is terminated becomes difficult, if

not impossible, if oscillations occur.

The use of lossy ferrite beads on the emitter and base leads of the

device under test has been found to be an effective means of attenuating

unwanted high frequency oscillations. Lossy ferrite beads selectively

absorb rf energy, being most effective at the higher frequencies where

feedback energy causes oscillation. The effectiveness of the beads depends on the relative magnitude and frequency distribution of the source,

the ferrite bead, and the load impedances.

It has also been found that a capacitor may be required between the

collector and base (ground) of the device under test to prevent oscillations. The value of the capacitor has to be large enough to damp the

oscillations and may require parallel capacitors so as not to become

series resonant within the frequency range of the test equipment.

4.3.3 Operating Conditions of the Device Under Test

The ability of the V^g emitter-only technique to accurately measure

the peak junction temperature is greatly dependent on the degree of heating current nonuniformity that exists within the active region of the

semiconductor chip. The degree of current crowding is dependent on the

device operating conditions even under constant heating power situations

where

"''c^CE An example of this can be seen in figure 3

for a Iz5-W triple-diffused power transistor which is dissipating 50 W

of power for two different operating conditions. The device is coated

with a thermographic phosphor [19] which appears darkest at the hottest

areas of the device in this figure. For the low -current, high -voltage

condition (I^ = 0.25 A, V^^ = 200 V), the power density is much more

localized (as evidenced by the very dark "hot spot") than for the other

operating condition. Even though the power dissipation in the transistor was held constant, the peak junction temperatures are dramatically

different. In this case, the difference is approximately 150°C.

12 I:
(a)

(b)

Figure 3. A 125-W power transistor coated with a thermographic

phosphor shown for two different operating conditions, each dissipating 50 W. The phosphor when illuminated with ultraviolet radiation as done here is brightest at the cooler areas and darkest at

the hotter areas. (a)

^CE

= 200 V.

= 1.0 A, V^^ = 50 V; (b) = 0.25 A,

13
In general, for low-current, high-voltage operation, the measured

thermal resistance is a strong function of operating conditions. At the

other extreme, high current and low voltage, it is not as strong a function of the operating conditions. This can be seen in figure 4, which

shows a plot of measured thermal resistance versus collector current at

constant power for a 35-W power transistor. Data taken on three power

transistors at various operating conditions, comparing indirect and direct measurements of thermal resistance, are summarized in table 2. It can be seen from the data that, as the degree of current crowding increases, the electrically measured thermal resistance deviates further

from the actual peak thermal resistance as determined from direct measurements with an infrared microradiometer

The reason for the large values of Rqj^, at low values of I^ is

that the thermal-electrical feedback mechanisms that initiate current

crowding and eventually second breakdown [20] are stronger at small

values of I^ than at large values. Thus, the current tends to be more

constricted and the peak temperature higher for these conditions.

The fact that for high-current, low-voltage operation the thermal

resistance is generally not a strong function of device operating conditions does not mean that measurements at low collector voltage and high

collector current are without difficulties. For example, the extremely

long switching times of devices operating in the quasi-saturation re- gion [21] make thermal resistance measurements using a switching technique in this region of operation essentially meaningless. This is because the part of the measured V which arises from a long-lived nonthermal transient, which is due to the large density of stored charge,

cannot be separated out from the desired thermal part. The problems en- countered are illustrated in figure 5, which shows the measured thermal

resistance of a 35-W power transistor plotted against the square root

of the time after cessation of power for a transistor with collector

current of 4 A and a range of values of collector-emitter voltage, V^^.*

The device is operating in the quasi-saturation mode at 5 and 7.5 V and

is just beginning to come out at 10 V. Note that for 5, 7.5, and 10 V

there is almost no linear portion of the curve as would be predicted by

the extrapolation procedures based on one-dimensional cooling [3]; the

nonlinearity indicates that nonthermal switching transients are present.

The thermal resistance at 5, 10, and 20 V as calculated from measure- ments of the peak junction temperature with an infrared microradiometer

are also indicated in the figure at zero time. Because the electrical

method is known to average the junction temperature, it should always indicate a temperature less than the peak temperature. Only at 20 V is

this the case; at 5 V, the electrically measured temperature is greater

than the peak temperature even after the device has cooled for 250 ys.

This arises because the nonthermal switching transients completely ob- scure the temperature dependence of the junction voltage. Thus, operat-

_

This extrapolation procedure is discussed in Appendix C of Appendix I of this report; also see 4.4,2.

14
15
Table 2

Comparison of Electrical and Infrared Techniques for Measuring

the Thermal Resistance of Power Transistors under

Various Device Operating Conditions

Measured Thermal Resistance

Device Specified R

(°c/w)

"-^^ Operating Condition Power

(°C/W)

Number Ic(A)/V.g(V) (W) Standard Infrared

Electrical Microradiometer

0 1/170 17 8 .5 14 6

0 .2/105 21 5 5 9 0

1 5 0 4/80 32 4 .2 5 5

1 0/54 54 3 0 3 4

2 0/33 66 2 5 2 7

0 2/140 28 2 9 4 6 0 3/106 32 2 8 4 0

2 1.5

1 0/44 44 2 4 2 9

2 0/38 76 1 9 2 1

0 6/76 46 3 3 3 8 1 0/50 50 3 0 3 4

3 7 2 0/28 56 3 0 3 2

3 0/20 60 2 8 2. 9

16
0.80

0 0.5x10'^ 10' 1.5x10'^

Figure 5. Cooling curves for a transistor operated with a collector

current of A A and various emitter-collector voltages. Data points

at zero time are derived from measurements of the peak junction temperature with an infrared microradiometer

.

17
ing conditions that place the device under test in the quasi-saturation

region should be avoided when making thermal resistance measurements.

4. A Simplification of Measurement Procedure for Industrial Use

The basic procedure for measuring the thermal resistance of power

transistors using the V emitter-only switching technique was developed

as a referee test method, although the ability to use the technique in

the industrial environment was a major criterion involved in its selection. This section deals with modifications to the basic procedure to

allow measurements to be made in an industrial environment with greater

speed and without significant loss in precision and accuracy. Discussed

are simplifications to the measurement procedure that allow testing of

devices of a given design and construction to be accomplished without

determining the calibration coefficient and extrapolated value of the

TSP for each device being measured.

4.4.1 Simplified Calibration Procedure

When thermal resistance measurements are being made on a large number of devices of a given design and construction, the use of a simplified calibration procedure is often acceptable. It can generally be as- sumed that under these conditions the slope of the calibration curve

(the temperature coefficient of the TSP) is relatively constant. Data,

extracted from a study on the use of thermal response for die attachment

evaluation [5] taken on 42 transistors mounted on TO-5 headers, indicated that the relative sample standard deviation of the calibration slope was 1.2 percent. Thus, if the processing for a particular device type

does not change, then the slope of the calibration curve should not vary

by more than a few percent.

The validity of the assumption that the temperature coefficient of

the TSP is relatively constant can be verified in the following manner.

The temperature coefficient should be measured on 10 devices of the same design and construction as those to be tested. If the relative sample

standard deviation of these measurements is less than or equal to ±3

percent, the average of the measured temperature coefficients can be

used in the calculation of thermal resistance for all other devices of

that design and construction.

4.4.2 Simplified Extrapolation Procedure

In measuring thermal resistance using the switched method, it would

seem desirable to measure the TSP at the exact instant that the heating

* This validation procedure was developed in conjunction with EIA-JEDEC

Committee JC-13.1 on Government Liaison for Discrete Semiconductor Devices for use in a revision of Method 3131 on Thermal Resistance of

MIL-STD-750. The revised test method for measuring the thermal resistance of transistors is designated Method 3131.1 and can be found in

MIL-STD-750B, Notice 9, dated September 19, 1978.

18
power is removed, since the junction temperature is maximum at that time.

However, this is not possible because 1) it takes a finite time for the

transistor current to decay from the heating value to the measuring value and 2) transients exist in the measuring voltage waveform for some

time after the measuring current value is reached due primarily to

charge storage effects in the device under test (as discussed in 4.3.3).

Because some semiconductor element cooling occurs during this delay period, the TSP may have to be extrapolated back to the time when the heating

power was terminated (see Appendix C of Appendix I for details) .

The extrapolation procedure is based on the assumption that the heat

source thickness is small compared to the total chip thickness and that

for approximately the first 250 us of cooling one-dimensional heat flow

occurs [3]. During this period, a proportionality factor, K, which re- lates the change in T^. during cooling to t^'^ [see eq (1) of Appendix C of Appendix I] can be defined as follows:

K = T - T

J2 Jl

^ 1/2 _ ^ 1/2

^1 ^2

(4)

where

:

t = delay time after heating power is terminated, in microseconds,

Tj.^ = junction temperature at time t = t^, in degrees Celsius, and

= junction temperature at time t = t^ < t^, in degrees Celsius.

When thermal resistance measurements are being made on a large number of devices of a given design and construction, the use of a simplified extrapolation procedure is often acceptable. Under these conditions and for a given set of device operating conditions C^q-^j » I ), the proportionality factor, K, is relatively constant. It was also

snown in section 4.4.1 that a single value of the temperature coefficient of the TSP is also appropriate for devices of a given design and

construction. Then the extrapolation correction factor (k') is given

by:

^/ _ ^2(1) \2(2)

^ - t^l/2 - t^U2 = K

AV.MC

AT.MC

(5)

Calibration

where K' is the slope of the VM2 ^^^s^s

250 us of device cooling and V:,„ . and V„„,^,

t2, respectively. ^^^^^ ^^^(2)

t^/2 cooling curve for the first

are measured at t^ and

The basic relationship used to calculate the thermal resistance

[see eq (3)] can be modified as follows to take into account the use of

the constant extrapolation correction factor (K'):

19
R

ejR

AV,

AT,MC

MC

-1

Calibration

(6)

where V is measured at time t. (For greatest precision, t should be

as small as possible, consistent with t2 ^ t <_ t^.)

To validate the assumption that a single extrapolation correction

factor (K') can be used, the extrapolated slope of the cooling curve should be measured for 10 devices of the same design, construction, and

operating conditions as those to be tested. If the relative sample standard deviation of these measurements is less than or equal to ±3 percent,

the average extrapolation correction factor can be used in the calculation of thermal resistance for all other devices of that design and con- struction.* Since the cooling curve during the first 250 ys of cooling

is proportional to the area of conduction of the transistor, the use of

this simplified extrapolation procedure is not recommended for operating

conditions at which current crowding occurs.

5. Thermal Response Measurements for Die Attachment Evaluation

Both the steady-state thermal response (or thermal resistance) and

the transient thermal response of semiconductor devices are sensitive to

the presence of voids in the die attachment material between the semiconductor chip and header since these voids impede the flow of heat from the

chip to the case (header). Due to the difference in the thermal time constants of the chip and case, the measurement of transient thermal re- sponse can be made more sensitive to the presence of voids than can the

measurement of steady-state thermal response. This is because the chip

thermal time constant is generally several orders of magnitude shorter

than that of the case. Thus, the heating power pulse width can be se- lected so that only the chip and the chip-to-case interface are heated

during the pulse by using a pulse width somewhat greater than the chip

thermal time constant, but less than that of the case. Heating power

pulse widths ranging from 5 to 10 ms have been found to satisfy this criterion. This enables the detection of voids to be greatly enhanced, with

* This validation procedure was developed in conjimction with EIA-JEDEC

Committee JC-13.1 on Government Liaison for Discrete Semiconductor Devices for use in a revision of Method 3131 on Thermal Resistance of

MIL-STD-750. The revised test method for measuring the thermal resistance of transistors is designated Method 3131.1 and can be found in

MIL-STD-750B, Notice 9, dated September 19, 1978. In Method 3131.1, the

extrapolation correction factor, K', is labeled K. [See Appendix V

of this report for information on the equivalency of symbols used in

the commercial and military thermal resistance test methods for transistors . ] ** This procedure is incorporated in EIA Recommended Standard RS-313-B,

Thermal Resistance of Conduction Cooled Power Transistors, dated October 197.5 as Appendix A. (See Appendix I of this report).

20
the added advantage of not having to mount the device under test on a heat sink [5 ]

.

To compare relative quality of the die bond, it is assumed that the

temperature coefficient of the TSP is the same for all members of a given

group of devices of the same design and construction (see section 4.4.1).

It is therefore necessary only to measure the TSP first under conditions

of no internal power dissipation (V^^p) si^d then at some specified time

after the termination of the constant heating power pulse (^^2) • ^ quantity proportional to the junction-to-reference point temperature difference is obtained by subtracting V^^^ fi^om V . This allows the transient

thermal response technique to be made less time-consuming for use as a manufacturing screen or process control measurement for die attachment

evaluation.

A typical circuit for measuring V^^ and V^^ is shown in figure 6.

It should be noted that the power interruption circuitry is similar to

that used in the measurement of thermal resistance utilizing the emitteronly switching procedure, although for transient thermal response measure

ments , the power-off interval is long compared to the power-on interval.

The circuit is controlled by a clock pulse with adjustable width and

repetition rate. When the voltage level of the clock pulse is zero, tran

sistor is off, and the current through the DUT is the sum of the heating current (switch S^^ closed) and 1^^^. The heating power pulse ends when

the clock goes negative. This turns Q- on, causing the heating current

from to now flow thr.^ugh instead of the DUT. After a delay to allow electrical transients to subside (usually 10 to 50 ys") , the sampleand-hold unit (S&H) senses V and displays its value on the digital volt

meter (DVM) (switch as indicated) . The voltage is obtained by mak

ing the measurement, with the heating current supply disconnected (switch

open) or with transistor turned on, prior to the application of the

heating power pulse.

6. Conclusions

A brief description of the idealized concept of thermal resistance

has been given along with the problems and pitfalls encountered in applying the concept to power transistors. It was shown that for high-current

low-voltage operating conditions, a unique and meaningful thermal resistance based on the peak junction temperature can usually be defined, but

for low-current, high-voltage conditions, no unique value, independent

of operating conditions, can be defined.

In addition, the advantages and disadvantages of various electrical

techniques for measuring thermal resistance were described, and a preferred standard technique was discussed in detail. This preferred technique, in which the forward-biased emitter-base junction is used as the

temperature-sensitive parameter, is usable on all types of bipolar transistors. The measurement procedure is relatively simple and, because the

temperature-sensitive parameter is sensed under conditions that simulate

normal device operation, it is relatively accurate. The power interrup21
22
tion circuitry is also relatively fast and simple since only the emitter

terminal of the device under test is switched. Detailed circuit diagrams

and mounting and cooling arrangements to enable the building of a com- pleted test system for measuring the thermal resistance of power transistors using the V emitter-only switching technique are also presented.

Simplifications in the temperature-sensitive parameter calibration and

extrapolation procedures to make the technique usable in a production

environment are valid under a variety of device operating conditions as long as the device design and construction is not changed. The basic approach and test circuitry is also usable for semiconductor device die attachment evaluation.

7. References

1. Thermal Resistance Measurements of Conduction Cooled Power Transistors, EIA Recommended Standard RS-313-B (Revision of RS-313-A)

,

October 1975. (Available from Electronics Industries Association,

2001 Eye Street, N.W. , Washington, DC 20006.) (This reference can

be found in Appendix I of this report.)

2. Blackburn, D. L. , An Electrical Technique for the Measurement of

the Peak Junction Temperature of Power Transistors, 13th Annual ProaeedingSj Reliability Physios 1976, Las Vegas, Nevada, April 1-3,

1975, pp. 142-150.

3. Blackburn, D. L. , and Oettinger, F. F., Transient Thermal Response

Measurements of Power Transistors, PESO '74 Record, IEEE Power Electronics Specialists Conference, Murray Hill, New Jersey, June 10-12,

1974, pp. 140-148.

4. Rubin, S. , Thermal Resistance Measurements on Monolithic and Hybrid

Darlington Power Transistors, PESO '75 Record, IEEE Power Electronics Specialists Conference, Culver City, California, June 9-11,

1975, pp. 252-261.

5. Oettinger, F. F. , and Gladhill, R. L., Thermal Response Measurements

for Semiconductor Device Die Attachment Evaluation, 197Z lEDM Technical Digest, Washington, D. C, December 3-4, 1973, pp. 47-50.

6. Reich, B., Continuous Thermal Resistance Measurements, Semiconductor Products 5_, No. 11, 24-27 (1962).

7. Reich, B. , and Hakim, E. B., An Appraisal of Transistor Thermal Resistance, SCP and Solid State Technology 8^, No. 4, 21-29 (1965).

8. Early, J. M. , Effect of Space Charge Layer Widening in Junction

Transistors, Proc, IRE l^, 1401-1406 (1952).

9. Sparkes , J. J., Voltage Feedback and Thermal Resistance in Junction

Transistors, Proc. IRE 1305-1306 (1958).

23
10. Oettinger, F. F., and Rubin, S., The Use of Current Gain as an Indicator for the Formation of Hot Spots Due to Current Crowding in

Power Transistors, 10th Annual Vvooeedingsy Reliability Physios

1972, Las Vegas, Nevada, April 5-7, 1972, pp. 12-18.

11. Tellerman, J., Measuring Transistor Temperature Rise, Electvonios

Tl_, No. 4, 185-187 (1954).

12. Nelson, J. F., and Iwersen, J. E., Measurement of Internal Temperature Rise of Transistors, Vvoo.. IRE 1207-1208 (1958).

13. Gates, R. F., and Johnson, R. A., The Measurement of Thermal Resistance — A Recommendation for Standardization, Semiconductor Products

2, No. 7, 21-26 (1959).

14. Coleby, P., Thermal Resistance of Semiconductor Devices under SteadyState Conditions, Mullard Technical Communications 7_, No. 65, 127-

140 (1963).

15. Vollheim, E. L., How to Measure Thermal Resistance of Transistors,

£'£'£'11, No. 12, 71-73 (1963).

16. Grutchfield, H. B. , Measurement of the Thermal Resistance and Thermal Response of Diffused Silicon Transistors, Fairchild Semiconductor Application Bulletin, APP-53 (January 1963).

17. Verway, J. F., On the Mechanism of h^^ Degradation by Emitter-Base

Reverse Current Stress, Microeleotromcs and Reliability 9_, 425-432

(1972) .

18. Gaur, S. P., Navon, D. H. , and Teerlinck, R. W. , Transistor Design

and Thermal Stability, IEEE Trans. Electron Devices ED-20 , 527-534

(1973) .

19. Brenner, D. J., A Technique for Measuring the Surface Temperature of

Transistors by Means of Fluorescent Phosphors, NBS Tech. Note 591

(July 1971).

20. Hower, P. L. , and Govil, P. K. , Comparison of One- and TwoDimensional Models of Transistor Thermal Instability, IEEE Trans.

Electron Devices ED-21 , pp. 617-623 (1974).

21. Olmstead, J., Einthoven, W. , Ponczak, S., and Kannam, P. J., High

Level Current Gain in Bipolar Power Transistors, RCA Rev. 32., 221-

249 (1971).

24
APPENDIX I OCTOBER 1975

THERMAL RESISTANCE

MEASUREMENTS OF

CONDUCTION COOLED

POWER TRANSISTORS

Reprinted with Permission of the

Electronic Industries Association

ELECTRONIC INDUSTRIES ASSOCIATION

RS-313-B

Revision of RS-313-A

Formulated by

JEDEC SOLID STATE PRODUCTS COUNCIL
NOTICE

EIA engineering standards are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the

proper product for his particular need. Existence of such standards shall not in any respect pre- clude any member or non-member of EIA from manufacturing or selhng products not conformine to such standards, nor shall the existence of such standards preclude their voluntary use by those other

than EIA members whether the standard is to be used either domestically or internationally.

Recommended standards are adopted by EIA without regard to whether or not their adoption

may involve patents on articles, materials, or processes. By such action, EIA does not assume any

liability to any patent owner, nor does it assume any obligation whatever to parties adopting the

recommended standards.

Published by

ELECTRONIC INDUSTRIES ASSOCIATION

Engineering Department

2001 Eye Street, N.W., Washington, D. C. 20006

© Electronic Industries Association 1975

All rights reserved

Printed in U S A.

26
FOREWORD

This standard describes a recommended test method for measuring the thermal resistance

of conduction-coqled power transistors. This method is offered as a replacement for that

contained in EIA/NEMA Standard RS-313-A (March 1968) which has been found deficient

in its test method detail. The present method is the emitter-base forward voltage method

with emitter-base switching and treats the detail circuitry, test instruments, calibration

and precautions to assure reliable and reproducible measurement. It generally conforms

to the principle of MIL-STD-750 Method 3131 and to lEC Pubhcation 147-C2 Method

12.3.1. However, experience has shown that the test performed under this Standard is applicable to all power transistors regardless of thermal response times.

This material was prepared by JEDEC Committee JC-25 on Power Transistors and

approved for publication by the JEDEC Solid State Products Council.

27
THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTOl

(From Standards Proposal No. 1 1 79, formulated under the cognizance of the JC-25 JEDEC Committee

on Power Transistors.)

1. THERMAL RESISTANCE, JUNCTION to SPECIFIED REFERENCE POINT (R^jr).

1.1 General Considerations. Of the thermal characteristics of a semiconductor device, the most

frequently specified parameter is the thermal resistance between the chip and a reference point

such as the device case or ambient.

The thermal resistance of a semiconductor device is a measure of the ability of its mechanical

structure (package) to provide for heat removal from the semiconductor junction. In most

devices, the maximum junction temperature can't be measured directly since the area of interest

is not accessible due to packaging considerations. Thus, indirect means are used to infer the

temperature of a specific area on the chip. The thermal resistance of a semiconductor device

is therefore determined by the measurement of a temperature-sensitive electrical parameter of a semiconductor junction within the device.

The measured thermal resistance of semiconductor elements (transistors) is not constant as frequently assumed, but depends on the device operating conditions, the junction and reference

point temperatures, and the temperature-sensitive parameter chosen. When specifying thermal

resistance, it is therefore important to indicate clearly the measuring conditions. The temperature

sensitive device parameter is used as an indicator of an average (weighted) junction temperature

of the semiconductor element for calculations of thermal resistance.

In measuring power transistor thermal resistance, either the emitter-base forward voltage or

the collector-base forward voltage can be used as the temperature sensitive electrical parameter

to indicate the junction temperature. Although equally precise, the Emitter-Base Voltage Technique

has been found to be more accurate than the Collector-Base Voltage Technique, i.e., the Emitter- Base Voltage Technique gives a junction temperature closer to the actual peak temperature on the

chip. The greater inaccuracy of the Collector-Base Voltage Technique is due to the greater deviation

between the region of the collector junction traversed by the measuring current during calibration

and the region traversed during test.

1.2 The Measurement of Thermal Resistance, Junction to Specified Reference Point (Rgjj^),

using the emitter-base voltage of a transistor in the emitter-only switching mode as the temperature

sensitive parameter.

1.2.1 Purpose. The purpose of the test is to measure the junction to specified reference

point thermal resistance of single element transistors by using the emitter-base junction

to indicate the device junction temperature. This method is to be used as the standard

28
technique, i.e., referee method for the measurement of thermal resistance. However, the

procedure is also adaptahle to production testing, including die attachment screening (see

Appendix A).

1.2.2 Procedure. In measuring transistor tliernial resistance, the emitter-base forward

voltage of the transistor is used as the temperature sensitive parameter (TSP) to indicate

the junction temperature. The TSP is measured at a small fixed forward current. This

low level current, at which the temperature sensitive parameter is measured, is called the

measuring or calibration current (Ijyj). The magnitude of Ijyj is such that the TSP varies

linearly with temperature and is stable. The TSP is measured under two general operating

conditions. First, the measurements of the emitter-base forward voltage necessary to determine the changes in the TSP due to the dissipation of power are made. For these

measurements the case temperature is kept at a constant preset value. After this is complete, the calibration curve is generated by measuring the TSP as a function of the case temperature starting at the lowest case temperature of interest. The information generated

under these operating conditions is then used to calculate the junction-to-reference point

thermal resistance in the following manner:

R0]K

~ R_ ^M >- ^Mi

P(AVG)"(P^-Pl)D

AV MC

Calibration

where:

R

P(AVG)

= Thermal Resistance, junction to reference point, in degrees Celsius/watt.

= Junction temperature in degrees Celsius.

= R(4"erence point temperature in degrees Celsius.

= Average heating power applied to transistor causing temperature difference

Tj - Tj^ in watts.

= Magnitude of higher heating power applied to transistor in watts.

= Magnitude of lower heating power applied to transistor in watts.

M2

Ml

D

= Value of TSP corresponding to the temperature of the junction heated by P2

and measured at I]yj in millivolts.

- Value of TSP corresponding to the temperature of the junction heated by Pj

and measured at I ^ in millivolts.

= Heating power duty factor.

29
( AVj,^|(^/AT]yj(^) = Temperature sensitive parameter temperature coefficient measured at Ijyj

in millivolts/degree Celsius.

T]y|(-. = Calibration temperature measured at reference point in degrees Celsius.

^MC ~ Value of TSP during calibration at Ijyj and specific value of in millivolts.

If the lower heating power (Pj) apphed to the transistor is equal to the power dissipation during

calibration then Vjy|^ = V^k^ (for T]vi(^= T^). Also, if the power dissipation during calibration is negligible, then P^^Q. Rqj^ can then be simplified to:

'0]R R..^= - - X PoD

-1

Calibration

Measurements of Tpj and Tjy/i^. are made by means of a thermocouple attached to the reference

point. See Appendix B for information on reference point tcmj)eraturc measurements of conduction

cooled power transistors. The power dissipation in the device under test is calculated as follows:

p^Ic^cb^Ie^beThe measurement of thermal resistance is generally divided into two steps:

Step I - Power Application Test.

The power application test is performed in two parts. For both portions of the test, the reference

point temperature is held constant at a preset value. The first measurement to be made is that of the

temperature sensitive parameter, i.e., Vjyj^, under operating conditions with the measuring current

(I]yj) and the collector-emitter voltage (V^-g) used during the calibration procedure (see Step 2). If the power dissipation during this part of the test is not negligible, then power Pj^ - ^^^j^^ + ^C^CB 1 should be subtracted from P2 when calculating the thermal resistance.

The device under test is then operated with power (P2) intermittently applied, but at a very high

(greater than 99 percent) duty factor. The specified power level (P2) is reached by varying the emitter

current (I^) to attain the required collector current (I(^); the collector-emitter voltage being equal to

that value used during the calibration procedure. During the interval between heating pulses (generally

less than or equal to 250 /us), and with the constant measuring current (l^) and collector-emitter

voltage (V(-£) apphed, the value of the temperature sensitive parameter (V]yj2) i'' measured. When

measuring the thermal resistance of a transistor, only the emitter current is switched from the heating

to measuring mode.

30
It would be desirable to measure the temperature sensitive parameter at the exact instant

that the heating power removal is initiated since the junction temperature is maximum at that

time. However, this is not possible for the following reasons:

1. It takes a finite time for the transistor current to decay from the heating value

to the measuring value.

2. Transients exist in the measuring voltage waveform for some time after the

measuring current value is reached due primarily to charge storage effects in the device under test.

The measuring voltage cannot be used as an indicator of junction temperature until after these

transients subside. The delay time before the TSP can be measured ranges from 5 to 100 pis for

most transistors. Since some semiconductor element cooling occurs between the time that the

heating power is removed and the time that the TSP is measured, the junction temperature value

determined from the TSP wiU be in error leading to a deceptively lower calculated thermal re- sistance. It may therefore be necessary to extrapolate the measured junction temperature back to the time where the heating power was terminated based on the shape of the cooling waveform

beyond the measuring point (see Appendix C for details). The extrapolated value, either in terms

of the TSP in millivolts or in terms of the actual calculated temperature in degrees Celsius, should

then be used in the calculation of thermal resistance.

It is recommended that the Power Application Test be performed so that the test device junction

temperature is representative of worse case usage. Consistent with this, the reference point

temperature should be such that the generated junction-to-case temperature difference is greater

than or equal to 30°C. The type of heat dissipator used for the Power Application test must be

chosen to accomplish this. The values of ^ ^MC' ^2' ^ recorded during the Power

Application Test.

The same value of collector-emitter voltage used during the Power Application Test for internal

device heating purposes is also applied during the Calibration Procedure (see Step 2).

Step 2 — Measurement of the Temperature Coefficient of the TSP.

The temperature coefficient of the temperature sensitive parameter is generated by measuring

the TSP as a function of the reference point temperature, for a specified constant measuring or

calibration current (Ijyj) and collector-emitter voltage (V^^), by externally heating the device

under test in an oven or on a temperature controlled heatsink. At small currents, the transistor

emitter-base voltage decreases with increasing temperature. A measuring current ranging from 1.0

to 50 mA is generally used, depending on the rating and operating conditions of the device under

test, for measuring the TSP. The measuring current is generally picked such that the TSP varies

linearly with temperature over the range of interest and that negligible internal heating (Pj ^ 0) occurs during the measuring interval. Therefore, the reference point temperature is approximately

equal to the junction temperature during calibration. The value of the TSP temperature coefficient

^^^MC^'^ '^MC^'

^^"^ particular measuring current and collector-emitter voltage used in the test,

is calculated from the calibration curve.

31
1.2.3 Test Conditions to be Specified

1. Case Temperature range during calibration.

2. Measuring or calibration current.

3. Heating current magnitude.

4. Heating (collector) voltage magnitude.

5. Heating power duty factor.

6. Heating power repetition rate.

7. Delay time before measurement of TSP.

8. Total heating time duration.

9. Reference temperature measuring point.

10. Reference point temperature for heating power measurements.

11. Mounting torque.

12. Mounting arrangement.

13. Extrapolation procedure.

CHARACTERISTIC TO BE MEASURED

Thermal Resistance, Junction to Specified Reference Point (R^jj^).

Two of the most common thermal resistance specifications are:

1- ^QjQ - Thermal resistance from junction to case.

^" ^(9 JM'

'T^^''"^^ resistance from junction to mounting surface.

32
1.2.4 Test. Circuit

Note: Lossy ferrite beads may he required on the emitter and base leads of the device under test to prevent oscillations. A capacitor may also be required between the collector and ground

of the device under test to prevent oscillations.

The circuit is controlled hy a clock pulse width of approximately 250 /is * and a repetition rate of approximately 4 Hz *. When the voltage level of the clock pulse is zero, the transistor Ql is off and the current through the transistor under test (TUT) is the sum of the heating current

(switch SI closed) and the measuring current (I[yj)- The heating current is furnished by the

supply, and the measuring current by the Vj^|jyj supply. At the end of each heating power pulse

the clock assumes a specified non-zero level for a period of time that is short compared with the

heating interval. This is sufficient to bias the transistor Ql on, which reverse biases the diode Dl

so that the heating current no longer passes through the device under test. The function of the

regulator Zener) diode Zl (optional) is to decrease the switching time of the device under test. The regulator voltage of the diode Zl should be equal to or less than the maximum rated VppQ

of the transistor under test. After a delay, usually 5 to 100 /is, the sample-and-hold unit (S & H)

senses the TSP, i.e., Vjyj2, for a 1.5 /is * period and displays its value on the digital voltmeter (D VM).

Tlie temperature coefficient of the TSP and the required voltage Vjyj^ (for T^(2 - T^) are obtained

by making the required measurements with the heating current supply disconnected (switch SI open).

I The digital voltmeter used to measure the TSP can also be used to measure the power dissipation of

the device under test by connecting it across the junction(s) to measure the voltage(s), a id across

a suitable non-inductive current sensing resistor(s) to measure the current(s).

* Typical Value 33
APPENDIX A

Thermal Response Measurements for Semiconductor Device Die Attachment Evaluation

A.1 General Considerations

Steady-state thermal response (or thermal resistance) and transient thermal response of semiconductor devices are sensitive to the presence of voids in the die attachment material between

the semiconductor chip and header since these voids impede the flow of heat from the chip to the

case (header). Due to the difference in the thermal time constants of the chip and case, the

measurement of transient thermal response can be made more sensitive to the presence of voids

than can the measurement of steady-state thermal response. This is because the chip thermal

time constant is generally several orders of magnitude shorter than that of the case. Thus, the

heating power pulse width can be selected so that only the chip, and the chip-to-case interface,

are heated during the pulse by using a pulse width somewhat greater than the chip thermal time

constant but less than that of the case. Heating power pulse widths ranging from 5 to 10 ms

have been found to satisfy this criterion. This enables the detection of voids to be greatly en- hanced, with the added advantage of not having to heatsink the device under test.

A. 2 Procedure

To compare relative quality of the die bond, if it is assumed that the temperature coefficient

of the TSP is the same for all members of a given group of devices of the same type or lot, it

is possible to eliminate Ihe conversion of the TSP to temperature in the calculations. This

assumption is generally valid for semiconductor devices where the forward voltage of a p-n junction is used as the TSP. It is therefore necessary only to measure the TSP first under conditions of no internal power dissipation and then at some specified time after the termination

of the iieating power pulse. A tjuantity proportional to the junction-to-reference point temperature difference is obtained by subtracting the second voltage, Vjyj.^, from the first, Vjyj j. This

allows the transient thertTial response technique to be made less time consuming for use as a manufacturing screen or process control measurement for die attachment evaluation.

34
APPENDIX B

Reference Point Temperature Measurements of Conduction Cooled Power Transistors.

B.l Case Temperature (T^)

The case temperature of a stud-mounted, hexagonal-base transistor is measured at the center of

any flat on the hex. The case temperature of other base-mounted transistors is measured at a point specified by the manufacturer. The recommended procedure for measuring the case temperature of a transistor employs the use of a thermocouple and is defined as follows:

B.1.1 Type of Thermocouple — The thermocouple material shall be copper-constantan (Type T).

Its useful temperature range for standard temperature measurements is -183 to +371°C. The

wire size shall be no larger than #30 AWG. The junction of the thermocouple shall be welded to- gether to form a bead rather than soldered or twisted. [See "1971 Annual Book of ASTM StandardsPart 80, Method E220 for Calibration of Thermocouples by Comparison Techniques" for information on construction and usage of thermocouples.]

B.l. 2 Mounting Method — A small hole, just large enough to insert the thermocouple, shall be

drilled approximately 0.762 mm (0.03 in) deep in the base plate of the semiconductor device at the point specified by the manufacturer. The edge of the hole should then be peened with a small center punch to form a rigid mechanical contact with the welded bead of the thermocouple.

In the event that drilling into the base plate of the device case becomes impractical because of case

material or case dimensions, the thermocouple wire may be welded or soldered directly to a specified point on the case.

B.1.3 Accuracy — An accuracy of ±0.5"C should be expected of the thermocouple and associated

measuring system. Under load condition, slight variations in the temperature of different points on

the case may reduce the accuracy to il.O'^C for still-air coohng, and ±2.0*^C for forced-air cooling.

B.l. 4 Other Thermocouple Mounting Methods — Other methods of mounting thermocouples,

with the possible exception of the thermocouple welded or soldered directly to the case, usually

result in temperature readings lower than the actual temperature. Such deviations result from:

i A. Inadequate contact with the case when using cemented thermocouples.

B. External heat dissipator in contact with the thermocouple when using pressure contacts.

B.2 Mounting Surface Temperature (Tjyj)

The mounting surface temperature for EIA Registered Power Transistor packages is measured

using a thermocouple imbedded in a washer. The use of a washer, with a thermocouple imbedded,

offers the best single method of non-destructive testing that is compatible with most package types.

[The case and mounting surface temperatures are sometimes used interchangeably.]

35
B.2.1 Type of Tliermocouple - The thermocouple material shall be copper-constantan (Type T).

Its useful temperature range for standard temperature measurements is -183 to +37l'^C. The

wire size shall be no larger than #30 A.WG. The junction of the thermocouple shall be welded together

to form a bead rather than soldered or twisted. [See "1971 Annual Rook of ASTM Standards -

Part 30, Method E220 for Calibration of Thermocouples by Comparison Techniques" for information on construction and usage of thermocouples.]

B.2.2 Mounting Washer Construction — For all registered TO outhnes the following general rules apply:

a. The base material of the washer shall be copper. (Preferred half hard or softer).

b. The thickness of the washer shall be 3.175 ±0.127 mm(0.125 ± 0.005 in).

c. The outhne of the washer shall be larger by 0.762 to 1.524 mm (0.03 to 0.06 in)

than the outline of the seating surface of the package for which the washer is intended.

d. Clearance holes shall be 0.406 to 0.787 mm(0.0l6 to 0.031 in) larger than the maximum

outside diameter of the studs or screws intended to pass through the holes.

e. Surfaces of the washer sliall be flat within 25 jum per 25 mm (0.001 in per in) and

parallel within 75 urn per 25 mm (0.003 in per in) and shall be nickel plated to a thick- ness of 1.27 to 2.54 )um (50 to lOOjuin). [See "ANSI B46.1 - 1962, Surface Texture" for further details.]

f. The surface of the washer shall be free from burrs, but the maximum chamfering of

edges or holes shall not exceed 0.406 mm(0.016 in) by 45 deg. so as not to effectively

reduce the contact area of the washer.

g. Both surfaces of the washer shall have a 1.60 ^m (63 juin) finish or better and be free of oxides. [See "ANSI B46.1 - 1962, Surface Texture" for further details.]

h. The thermocon[)le hole shall be drilled into the washer midway between and [)arallel to the top and Ijottom surfaces. The size of the thermocouple hole shall be no greater

than 1.52 nim(0.06 in) in diam. but it is recommended that it be no larger than necessary

to accept the thermocouple.

i. For flat type packages (such as TO-3) the bottom of the thermocouple hole shall extend

approximately 0.76 mm(0.03 in) beyond the geometric center of the washer. Radial

orientation of thermocouple hole is arbitrary.

j. For stud type packages (such as TO-61) the bottom of the thermocouple hole shall be

approximately 0.76 mm(0.03 in) from the inside hole of the washer,

k. For tab type [)ackages the bottom of the thermocouple hole shall extend approximately

0.76 mm(0.03 in) beyond the geometric center of the seating surface.

1. It is recommended that the thermocouple be secured into the washer with a thermal

conducting adhesive and that particular attention be paid to minimizing air voids

around the ball of the thermocouple. (The thermocouple bead should be in direct contact with the copper washer.) m. Clearance holes for device leads should allow suitable clearance to prevent electrical shorting to the washer. It is recommended that this clearance hole be approximately

1.52 mm- (0.06 in) larger in diameter than the lead to allow clearance for insulating

sleeving to be used on the leads.

36

i
n. Device mounting torque should comply with the manufacturer's recommendations,

o. A thermal conducting compound at the interface of the washer and device should

be used.

p. Special precautions must be taken so that only the bead of the thermocouple is allowed to come in mechanical contact with the washer.

37
APPENDIX C

Extrapolation Procedure for Power Transistors

C.l Extrapolation Procedure

This extrapolation procedure is based on the assumption that the heat source thickness is small

compared to the total chip thickness and that for approximately the first 200 or 250 /is of cooling, one dimensional heat flow occurs. Therefore, the first 200 or 250 microseconds of cooling can be represented by

Tj(CooUng)<') = Tj(s.s.)-K.'^ (D

where K is approximately constant and Tj^g

g ^ is the steady state junction temperature.

If, for equation (1), Tj^(^QQjij^g^(t) versus f^^ is plotted on linear graph paper, the generated

curve will be a straight line with TJ^^ S ) ^ intercept, i.e., at t = 0. Plotting this curve

for an actual device also provides a means for determining when non-thermal switching transients

are significant since the curve, as plotted, will be non-linear under this condition.

Using equation (1), a mathematical expression which can be used to generate the extrapolated vaJ Tj^g

g ^ (t = 0) is a follows:

^12 ~ ^11 '/,

where

Tj^g

s ) = 0) - Junction temperature, extrapolated to the time at which the

heating power is terminated.

t = Delay time after heating power is terminated.

Tjj = Junction temperature at time tj, e.g., tj = 200 /js.

Tj2 = Junction temperature at time t2, e.g., t2 = 100 jus.

38
APPENDIX II

SWITCHING TRANSIENTS IN TRANSISTORS*

The turn-off transient which occurs when the emitter of a transistor is opened

rapidly while the base and collector remain connected can result in emitter-base junction breakdown. This breakdown may cause deterioration [1] or catastrophic failure

of the transistors. The breakdown occurs even though the emitter current is in the

direction appropriate to a forward-biased emitter-base junction. It arises because

of a potential drop along the emitter-base junction induced by the flow of majority

carriers out of the base as required to bring the base region back to equilibrium

following reduction of electron injection from the emitter. Breakdown can be

avoided if the emitter is opened slowly enough that the base can remain in a near neutral condition without rapid flow of charge and the resulting potential buildup. Alternatively, the emitter-base voltage can be limited to a value below the

breakdown voltage with a protective circuit based on the use of a zener diode. The

charge flow in the base during the turn-on and turn-off transients and of the operation of the protective circuit are described in detail below.

To elucidate the details of the charge flow during switching an extensive series

of experiments was conducted. In these experiments, the current in various branches

of the circuit was measured with a current probe and the voltage across the appropriate

transistor terminals was measured with an oscilloscope. The circuit used for these

measurements is shoxm in figure II-l. This circuit also contains a protective zener

diode circuit which can be incorporated by the switch Si.

* Extracted from Methods of Measurement for Semiconductor Materials, Process Control, and Devices (Quarterly Report for Period January 1 to March 31, 1973),

NBS Tech. Note 788, W. M. Bullis, Ed, pp. 65-70.

Figure II-l. Test circuit. (Current is measured by means of a probe at the loops marked iy)

39
The low- level emitter current supply, usually included when measuring thermal resistance, was omitted during this series of experiments; no significant differences, except

one which will be noted subsequently, were observed when the low-level emitter current was included.

Turn-on Transient — Consider first the conditions in the on state which are set

up during turn on. For explicitness the argument is developed for an n-p-n transistor, but it can easily be extended to a p-n-p transistor. In the quiescent state the

base is grounded and the collector-base junction is reverse biased (collector positive). At a time t = 0, the emitter supply is connected to the emitter contact to foward bias the emitter-base junction (emitter negative) which results in electrons

being injected into the base. The injected electrons are minority carriers in the

base. They diffuse toward the collector-base junction with a time constant that can be the order of microseconds, but as soon as they enter the base they upset the charge

neutrality in the base. To maintain charge neutrality, majority holes flow rapidly

into the base from the base contact. The return to neutrality in the base occurs with

a time constant determined by the dielectric relaxation time in the base. This time

constant is the order of 10"-^^ to lO"'^^ s. Thus, as soon as an electron is injected

into the base a hole is created to neutralize it. This process results in a build up

of the electron-hole pair density in the base and continues until equilibrium is

reached. The turn-on current transients for a 35-W, single diffused transistor with

a 1.5 mil (60 ym) wide base are shown in figure II-2 . During the period of charge build

up, the electron current into the base from the emitter is much larger than the electron current leaving the base for the collector, and holes flow into the active region

of the base, under the emitter-base junction. Outside the active region the base is

thin and long relative to its width. The charge flow across the extrinsic base

40
resistance associated with this region results in a potential drop such that the edge

of the active region of the transistor is negative with respect to the base contact.

Lateral hole flow across the intrinsic base resistance within the active region, causes an additional potential drop across the emitter -base junction; this potential

drop is, of course, in the same direction. It acts to debias the center of the junction and causes the familiar current crowding phenomenon which forces the emitter

current to the outer periphery of the junction.

Equilibrium is established when the excess hole-electron pair density in the base

region reaches the value appropriate to the injected electron current from the emitter.

In equilibrium, holes still flow from the base contact to the active region in order

to supply holes for recombination with electrons in the base (base transport losses)

and for injection into the emitter (injection efficiency losses) . The current associated with these losses is much smaller than either the peak base current during turn-on

or the steady-state emitter current. In the example shown in figure II-2, the equilibrium

base current is 15 mA while the peak base current is approximately 450 mA and the

steady-state emitter and collector currents are about 1 A.

Turn-off Transient — When the transistor emitter circuit is opened, electron injection into the base from the emitter decreases. However, the excess carrier density

which causes the concentration gradient associated with the diffusion of electrons

toward the collector does not change instantaneously; hence, electrons continue diffusing toward the collector-base junction where they are swept out of the base region.

This results in a reduction of the electron density in the base which must be accompanied by a reduction of the hole density in order to maintain charge neutrality.

Consequently, holes must flow out from the active region of the transistor to the base

contact. This flow is in the opposite direction to the flow during the turn-on transient and sets up a potential gradient across the extrinsic base resistance such that

the active region of the transistor is positive with respect to the contact. The

most positive portion of the base can approach the potential of the collector region.

The simplest turn-off transient occurs for collector-base voltage well below the

breakdown voltage of the emitter base junction. To Illustrate this case, the current

and base emitter voltage turn-off transients are shown for a collector voltage of

about 10 V in figure II-3. The switch Sj in the test circuit (figure II-l) was set to position 1 so that the protective circuit is not connected. When turn-off begins, as evidenced by a decrease in i„, v begins to rise toward zero from a small negative

t. bis potential. At the same time, i_ decreases from a small positive value to zero and

D then Increases to a negative value of approximately 165 mA. During this same period

ig begins to decrease rather rapidly, but the collector current does not begin to decrease rapidly until about 0.2 ys after i„ starts to decrease. During this 0.2-ys

period, i increases in the reverse direction in such a way as to be always equal to

41
Figure II-3. Turn-off emitterbase voltage and base, emitter, and collector current

transients for collector-base

voltage less than emitter-base

junction breakdown voltage.

(V cc

10 V. Horizontal

scale: 1 ys/div. Vertical

scales: 5 V/div (v„g)

200 mA/div (i).)

the difference between the magnitudes of i^ and i„. The action of the currents and

the reverse-biased emitter-base voltage during this time period can be explained as follows. Since the injection rate of electrons from the emitter is being reduced

while for a time the extraction rate of electrons at the collector remains unchanged,

holes must flow out of the active region of the device toward the base contact through

the extrinsic base resistance. Since both i^ and v„^ increase linearly during this

period, it appears that the extrinsic base resistance is constant as one would expect.

About the time i_ begins to decrease significantly, i also begins to decrease.

Since v„„ continues to increase even more rapidly, this suggests that the base resistance is increasing. This could occur if the active area of the emitter changed from

the periphery to the central core. Such a change is in accord with the direction of

hole flow; in contrast to the situation encountered during turn-on the outer regions

of the emitter tend to be debiased. Next i„ stabilizes for a time while v continues

to increase; then when v„_ reaches its maximum value (limited by the collector voltage), i decreases toward its new steady-state value (in the present case, zero). At

D long times, after i , i , and i reach their new steady-state values, v^,, begins to decrease to zero or, if i ?^ 0, a small value of forward bias,

in figure II-3 (see arrow)

This is also illustrated

If a higher value of collector voltage is applied, again with the protective

circuit not connected, the turn-off transients begin in the same fashion, but when

Vgg reaches a value near the breakdovm voltage of the emitter-base junction it ceases

to rise significantly and i„ increases abruptly as illustrated in figure II-4. This

D abrupt increase in i^ is due to the onset of breakdown at the periphery of the emitterbase junction. The active region of the transistor has been pinched in toward the

center of the emitter area by virtue of the hole flow out to the base lead as discussed

42
Figure II-4, Turn-off emitterbase voltage and base, emitter, and collector current

transients for collector-base

voltage greater than emitterbase junction breakdown voltage, without protective circuit. (V(,(, = 20 V. Horizontal

scale: 1 ys/div. Vertical

scales: 5 V/div (vgg)

;

200 mA/div (i) .)

above. In this central region the emitter-base junction is forward biased so the

emitter potential is only a fraction of a volt more negative than the potential in

the central base region. Since the emitter is a low-resistance element the entire

emitter is at approximately the same potential. However, the base contact is much

more negative than the central region of the base because of the resistive drop associated with the lateral hole flow through the base. As a result, except for the central active area, the emitter-bias junction is reverse biased; this bias can increase

until its value at the periphery reaches the limit imposed by the collector voltage or

the junction breakdown voltage, whichever is lower. In the latter case, there is a substantial flow of electrons from the base contact, laterally across the extrinsic

base resistance, into the emitter across the reverse-biased junction at the periphery,

through the emitter layer, to the central region of the emitter where they join the

injected electrons from the emitter circuit in crossing the forward-biased portion of

the junction, through the base, and into the collector. These electrons serve to retard the rate of decrease of the collector current as can be seen in figure II-4.

This model can be verified by considering the transients in the case where the zener diode protective circuit is included and the collector voltage is greater than

the zener voltage. In this case as illustrated in figure II-5 it is possible to separate the current through the base region and the current through the zener diode which

breaks down in much the same way as the peripheral region of the emitter-base junction

in the previous case. The i^ transient, which consists of holes leaving the active

region of the base, is very similar to the i„ transient when breakdown of the emitterbase junction does not occur (figure II-3), while the i^ transient, which is the sum

of the base and zener currents, is very similar to the transient when breakdown

occurs (figure II-4) . Note that in this case, the zener current also influences i in

1 43
Figure II-5. Turn-off emitter

base voltage and base, emitter, and collector current

transients for collector-base

voltage greater than emitterbase junction breakdown voltage with a 12-V zener diode

protective circuit.

(Vp^ = 20 V. Horizontal scale

1 ys/div. Vertical scales:

5 V/div (vgg) ; 200 mA/div

(i).)

Figure II-6. Turn-off emitter

base voltage transients.

(A: V^^ ~ 10 V, no protective

circuit. B: V,CC 20 V, no protective circuit.

C: V^^ ~ 20 V, 12-V zener diode protective circuit. Hor

izontal scale: 5 ps/div. Vertical scale: 5 V/div.)

contrast to the previous case. With the protective circuit, the fall of v is someEB what delayed. This can be seen more clearly in the traces presented in figure II-6

which cover a longer time period.

As a final observation, it should be noted that the rate of decay of the v

EB transient depends primarily on the nature of the external circuit and not on the

device properties. In particular,, inclusion of the low-level emitter current supply

used for thermal resistance measurements substantially increases the rate of decay.

REFERENCE

1. Verway, J. P., On the Mechanism of h^^ Degradation by Emitter-Base Reverse Current Stress, Mvaroeleatronics and ReliabzHty 9, 425-432 (:.970).

44
APPENDIX III

Detailed Description of Test Circuitry

The instrumentation to implement the measurement of transistor thermal resistance using the emitter-only switching technique, in which the

forward-biased emitter-base junction is used as the TSP, is described in

this section. This includes a description of the basic test circuit itself as well as a description of the clock pulse generator, the sampleand-hold circuit, the temperature controller, and the temperaturecontrolled water-cooled heat sink. The description which follows is

for the purpose of presenting an operating system in sufficient detail

to allow duplication. However, it should be emphasized that the instrumentation being described may not represent an optimized system.

III.l Basic Circuit for Thermal Resistance Measurements

The complete circuit diagram of the thermal resistance test system

used for measuring the thermal resistance of npn transistors with the ex- ception of the heat-sink temperature controller is given in figure III-l.

A floating constant-voltage power supply V is connected between collector and ground via a precision power resistor R , which is used to monitor the collector current. The parallel capacitor C serves to absorb

the switching transient which occurs when the collector current drops

from the heating value to the measuring value. The lossy torroid on the

emitter lead is an oscillation suppressor. The speedup diode D and the

diode switch D^ should be placed close to the emitter of the DUT. The

ground connections for the DUT and associated equipment should all have

a common ground on a low impedance copper strap placed close to the base

lead of the DUT. The problem of switching transients in the V^^ supply

is not as serious as those in the collector supply, since V is disconnected during the measuring interval. Further, the low (4-Hz) repetition rate allows leeway in the recovery time of V^^ because the transients occur for such a small portion of the heating time of the DUT. The

recovery time transients are not important because no measurements are made while they exist.

The parallel emitter switch (transistors Qx and Q2)> which can handle 4A of emitter current, is shown in detail. For higher currents, more

transistors can be paralleled or, preferably, higher current transistors

should be used. Mechanically, the two transistors are mounted on a heat

sink cooled by tap water. The water cooling is used to reduce the size

of the heat sink so that the switch can be placed in reasonable proximity

to the DUT. A single high current Darlington could be used where higher

currents create the need for a preamplifier to drive the emitter switching transistor, since the use of two diodes in series (the series switch

D2 and the speedup diode D^) ensures emitter current cutoff even though

the saturation voltage of a Darlington is greater than that of a single

transistor stage. As discussed in Appendix II, the turnoff speed of the

DUT is proportional to the forward drop of the series combination of D,

45
46
and This switching speed can be increased if is a regulator

(zener) diode with a breakdown voltage less than the reverse-biased

breakdown voltage of the emitter-base junction of the DUT. However, if

the extrapolation procedure for measuring the thermal resistance is

used, the high power regulator diode is not needed and a single forwardbiased diode can be used as the speedup diode Dj. The use of a watercooled heat sink may still be desirable to minimize changes in the diode

electrical characteristics. The variable emitter-resistor R^g> composed

of a group of parallel resistors, is mounted on a separate tap-watercooled heat sink. This is done for economy of space since the physical

size of the resistors would be much greater if they were not cooled.

Both V„„ and V.„. along with their associated variable resistors function

EE MM ° , , as constant current supplies.

III. 2 Clock Pulse Generator

The 4-Hz pulse generator circuit is shown in detail in figure III-2.

Commercial generators have also been used and are quite satisfactory, but

they included a great deal of versatility which is not required in this

operation. Further, the use of common power sources for the pulse generator and other devices simplified the overall test unit construction. A

unijunction relaxation oscillator Qi generates a 4-Hz pulse which is am- plified by fed to the one shot 74121 whose pulse width is governed

by the time constant of ^-j^^' '^^^ negative going output pulse is fed

from pin one of 74121 to amplifier inverter whose positive pulse

is fed to the test unit via emitter follower Q^. The output of is

also fed to amplifier inverter which drives amplifier Q . Because

is a pnp transistor, a positive going input signal will turn the transistor off and give a negative going output signal which is amplified by

the emitter-follower and fed to the test unit. Capacitors C^ and

C^ provide the energy storage needed by and to drive the test circuit of figure III-l and should be 1 yF or larger. In particular, this

energy storage is required to provide the charge needed to rapidly turn

on the parallel emitter switching transistors. The positive supply is

7 V and the diodes D^yD^ and the regulator diode-resistor combination

D^jR^ are used to prevent overvoltage damage to the one shot. Switch

disconnects the unijunction relaxation oxcillator, while switch S2

in conjunction with resistor provides a means for single pulse operation. This operation is helpful in making some experimental measurements and in troubleshooting the equipment.

III. 3 Sample-and-Hold Unit

The sample-and-hold (S&H) circuit diagram is shown in figure III-3.

The sample-and-hold unit and its logic are placed in an aluminum case and

the case is connected to the common ground of the ±15 V supply. It differs from most commercially available units in that it uses a large integrating capacitor and is therefore basically slow. It therefore tends

to average out the noise in the sampled signal and gives excellent re- peatability. Since the thermal measurements being made are inherently

47

(0

49
slow (it is necessary to wait for thermal stabilization of the DUT whenever the dissipation is changed or whenever the DUT is replaced) , the

settling time of the S&H (of the order of seconds) is not detrimental.

For a test method designed exclusively for rapid production line testing, an S&H with a fast acquisition time would be required.

The S&H as now constituted uses low-cost operational amplifiers

which take considerable time to stabilize when first activated. Further,

they are subject to some drift with time. To provide some method of moni

toring the condition of the S&H unit, a separate reference voltage circuit (fig. III-l) consisting of regulator diode and two separate reference diodes and D was added to the original test unit. These two

reference sources provide a measurement of the degree of equilibrium

and drift of the S&H. Two diodes were used so that a malfunction in one would not indicate a malfunction in the S&H.

The logic for the S&H unit consists of two 74121 one shots in tandem. The first one shot sets the delay time and the second one shot,

triggered by the trailing edge of the output pulse of the first one shot,

operates the FET gate Q^. The S&H consists of two operational amplifiers

The input amplifier is a voltage follower which drives the integrating amplifier This allows the use of a large integrating capacitor

C„. The input resistors and R2 set the gain and should be stable

(temperature coefficient or 100 ppm/°C or less). Metal film or tin oxide resistors are recommended.

It is necessary to adjust the S&H for unity gain by trimming one

of the input resistors with a parallel resistor if the utmost accuracy is

desired. The two amplifiers used (A^ and A-) have to be zeroed prior to use of the circuit. The integrating amplifier A2 is zeroed by opening

the input and output, replacing the integrating capacitor by a 10-kfi

resistor, putting a resistor between the input terminals, and monitoring the output terminals while the trimming resistor is adjusted for

minimum output. Once adjusted, further zeroing of A„ is unnecessary and

the variable resistor can be replaced by a fixed resistor of equal magnitude. A useful procedure for accomplishing this consists of installing

a 50-kf^ potentiometer in parallel with a 562-Q. resistor; after the potentiometer is adjusted to determine the proper value, a fixed trimming

resistor of this value is substituted for it. After A- is zeroed, it is

reconnected and then A is zeroed by shorting its input and monitoring

the S&H output using the DVM. This latter zeroing process is not permanent, and thus an arrangement should be provided for rezeroing the 50-

kO. potentiometer, R^, whenever necessary. It is best to check the zero before each run. Amplifiers with improved temperature coefficients and

offset characteristics would reduce the need for rezeroing.

III. 4 Temperature Controller

The temperature controller is shown in simplified form in figure

III-4 and in detail in figure III-5. Referring to the simplified diagram of figure III-4, one sees a reference voltage on the left picked

50

52
off in part by the potentiometer R2 which is isolated from its load by

voltage follower which drives voltage divider R2,R, . The low voltage

across R^, which is set by potentiometer R^ , is bucked against the thermal emf generated by the chromel-alumel thermocouple. The difference

voltage is amplified by the chopper-stabilized operational amplifier k^,

whose output controls the repetition rate of a blocking oscillator via

a lead network and amplifier A.. The blocking oscillator operates together with pulse transformer T^ to isolate the temperature sensing from

the power circuits of the heat-sink temperature regulator. This allows

the thermocouple to be soldered directly to the copper washer or to a transistor case despite elevated voltage. The output amplifier A^ , con- sisting of two discrete transistors, drives transistor 0^ which in turn

controls the heating power for the heat-sink resistors, . In the circuit shown, the resistor R^ consists of two parallel 5-W, 91-^2 ceramicinsulated wire-wound resistors. The blocking oscillator output consists

of 15-ys pulses. Networks in A, integrate the pulses to provide a drive

for Q^. Now Q drives R^ according to a square law since, if the output

is doubled, both the current and voltage double so that the resistor dissipation is quadrupled. To linearize this characteristic to provide

smoother control, a feedback circuit consisting of two resistors and a regulator diode was used to approximate a square root function so as to

provide linear control. This network is shown between the collector of

output transistor and the gate of FET transistor Q2 in figure III-5

.

The complete schematic of figure III-5 has notations helpful to

those who desire to duplicate it. As noted on the schematic, several

simplifying construction techniques can be applied. The distinguishing

features of this controller lie in the floating input which can be duplicated by using commercially available isolation amplifiers and the

feedback network around A2 which has to be adjusted for optimum response

for each heat-sink configuration. In general, the time required to ensure DUT stabilization was such that a single feedback network sufficed.

III. 5 Hydraulic System

The temperature-controlled heat sink and associated apparatus are shown in figure III-6. Tap water is used to fill an elevated container

which acts as a constant pressure source. This simple device eliminates

the effects of the varying pressure experienced with most tap water

sources. The water from the constant pressure tank flows through a chilled-water heat exchanger via a pressure monitor to the heat sink and

out to the tap water sink. Tap water is also used to cool the heat sinks

on which the emitter resistors, the speedup diode, and the emitter parallel switches are mounted. This tap water is not regulated in pressure

because the heat-sink tem.perature in these cases is not critical.

The chilled water in the heat exchanger is used to allow measurements with a heat-sink temperature of 25°C since this is specified in

most military and commercial documents.

53

III. 6 Temperature-controlled Heat Sink

The temperature-controlled heat sink includes resistance heaters

which work in conjunction with continuously running coolant water to keep

the heat sink temperature constant. The sensing thermocouple is placed

in the upper side of a standard copper washer used to monitor the case temperature of the DUT. This mounting surface technique for measuring

the case temperature is nondestructive and is generally as repeatable as sensing a point directly on the device case. It should be noted that

case temperature and mounting surface temperature are sometimes used interchangeably .

A typical heat sink with its associated copper washer is shown in

figures III-7 and III-8, respectively. The copper washer shown is used

for a TO-3 transistor case outline and is constructed according to EIA

recommended practices [1]. The heat sink itself has a two-level coolingwater path, two servo-controlled, 5-W heating resistors, and a third line

operated, 50-W resistor which is included for manual operation when fast

heating is desired for a temperature calibration run. The 50~W resistor

is operated from a 115-V adjustable-output-voltage transformer.

The three drawings on the left side of figure III-7 are sim.plified

representations which do not include the details of the resistor cavities

The center left drawing is a top view of the heat sink while the top and

bottom drawings are sections through the top and bottom water channel

levels, respectively. The center-of-page drawing is an end view showing

the entrance to the servo-controlled resistor cavities in addition to the

water channel plugs and openings . The top right drawing shows the water

f channels and an end view of the 50-W resistor cavity including a small

air hole which eases the insertion of the resistor when it has been

coated with a thermal heat-sinking compound. The right center and bottom

j drawings are a bottom and side view of the heat sink. The bottom view

drawing includes complete details of the heat sink with the servocontrolled heater cavities and their connector wire lead openings shown

dotted along with the 50-W resistor cavity and the cooling water channels

The right bottom drawing shows how the servo-controlled resistor lead

wires angle out the bottom of the heat sink. The three 6-32 tapped holes

on the right center drawing are used for mounting the heat sink to

insulated ceramic standoffs. The plugs used in the fabrication of the

water channels are silver soldered to allow high temperature operation

during calibration runs. Gold-plated phosphor-bronze contact pins are held in place by glass-filled, free flowing, non-copper-corrosive

silicone rubber. The copper washer can be attached directly to the heat

sink surface with silicone rubber, after applying a thin coating of zincoxide-loaded silicone thermal grease to the heat sink and the washer

contacting surfaces. In instances where it is desired to keep the collector potential off the heat sink, a beryllium oxide washer can be

placed (after coating both sides with thermal grease) between the heat

sink and the copper washer. For this case the mounting screws for the

transistor must be insulated with a high-temperature-compatible spaghetti, and an Insulated bottom plate containing captive nuts must be

55
56
Figure III-8. Typical mounting washer for a TO-3 encased transistor.

(All dimensions in inches)

57
provided for tightening the mounting screws. This necessitates larger

holes in the heat sink for the mounting screws.

Reference

1. Thermal Resistance Measurements of Conduction Cooled Power Transistors, EIA Recommended Standard RS-313-B (Revision of RS-313-A) , October 1975 (Electronics Industries Association, 2001 Eye Street, N.W.,

Washington, D. C. 20006). [This reference can be found in Appendix

I of this report .

58
APPENDIX IV

Single-Operator, Single-Laboratory Repeatability Measurements

Long-term single-operator measurements were undertaken to check the

repeatability of the equipment for measuring thermal resistance of transistors by the emitter-only switching technique. During a ten-week period, 12 to 15 sets of measurements were made on seven test devices at a case temperature of 25°C and 22 sets of measurements on three test devices at a case temperature of 60°C. Two devices (lot A) were singlediffused transistors in TO-66 cases, two devices (lot NM) were epitaxial

transistors in TO-66 cases, and three devices (lot AA) were singlediffused transistors in TO-3 cases.

The test conditions were chosen to provide sufficient power dissipation to ensure a reasonable rise in junction temperature but not enough

power or voltage to cause significant current crowding. Heating current

was 1 A for the devices in TO-66 cases (lots NM and A) and 2 A for the devices in TO-3 cases (lot AA) . In both instances, the collector-emitter

voltage was 20 V. A measuring current, I^, of 6 mA was used. Measurements were made with the circuit shown in figure lb of section 4.2 which

utilizes parallel-switching techniques.

The case temperature was measured using the washer technique in

which a thermocouple is embedded in the nickel-plated copper washer at a location underneath the chip approximately 50 ym below the case-washer interface. All devices were tested with a case temperature of 25°C while

the TO-3 encased devices were also tested with a case temperature of 60''C.

The results of the measurements obtained for a delay time of 10 ys

for the lots NM and AA devices and 20 ys for the lot A devices are listed

in table IV-1. Since more than one device of each type was measured, the

results for the individual device types are pooled.

The data also indicate that for the TO-66 encased devices the sample standard deviation was nearly constant even though the thermal resistance varied from 2.5 to 5.6°C/W. For the TO-3 encased devices, even

though the thermal resistance was measured at case temperatures of 25 and

60°C, the sample standard deviation was also constant. If the measured

thermal resistance is multiplied by the heating power, the sample standard deviation of the resulting junction-to-case temperature difference

ranges from 0.4 to 0.6°C for the parallel emitter switching technique.

Thus, these measurements indicate that the repeatability is nearly independent of the magnitude of the measured thermal resistance but is limited by a minimum resolvable junction-to-case temperature difference.

Extracted from Methods of Measurement for Semiconductor Materials, Process Control, and Devices (Quarterly Report for Period April 1 to June

30, 1973), NBS Tech. Note 806, W. M. Bullis, Ed, pp. 51-53.

59
Table IV-1

Pooled Results of Thermal Resistance

Repeatability Experiment

Lot

Numbe r Case Temperature(°C)

Thermal Resistance

(°C/W)

NM 25 5.57 ± 0.03

A 25 2.53 ± 0.03

AA 25 0.75 ± 0.01 !

AA 60 0.78 ± 0.01

1

60
APPENDIX V

Equivalency of Symbols in Commercial and Military

Thermal Resistance Test Methods

In EIA RS-313-B [1], the junction-to-reference point thermal resistance is given as

:

-1

(V-1)

Calibration

while in MIL-STD-750B, Notice 9, Method 3131.1 [2], the junction-toreference point thermal resistance is given as:

-1

(V-2)

Calibration

A list of equivalent symbols used in the two test methods as they

refer to eqs (V-1) and (V-2) is given in table V-1.

References

1. Thermal Resistance Measurements of Conduction Cooled Power Transistors, EIA Recommended Standard RS-313-B (Revision of RS-313-A) , October 1975 (Electronic Industries Association, 2001 Eye Street, N.W.,

Washington, DC 20006) . [This reference can be found in Appendix I of this report .

]

2. Method 3131.1, Thermal Resistance, Test Methods for Semiconductor Devices, MIL-STD-750B, Notice 9, dated September 19, 1978 (Department

of Defense, Washington, DC 20301).

R

eJR

\2 - \C '^"-^ ^MC °•^R^ DP„

AV

AT.MC

MC

R

^MH - ^MC (^"-^ ^MC = \'>

ejR DP

H

AV.

J AT.MC

MC.

61
Table V-1

Equivalency of Symbols Used in the Measurement of Thermal Resistance Using Various Standard Techniques

EIA RS-313-B ^IIL-STD-750B, Method 3131.1

M2

Ml

K

AV.MC

AT.MC Calibration

MC

K

If is equal to the power dissipation during calibration,

then equals P^ in Method 3131.1.

In the text of this report, K

AV.MC

AT

MC

is denoted k'

Calibration

62

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