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Nbdm 79-1591-3 PUBL,CATfQNs

SEr 2 5 19

i Semiconductor

Program

Progress Briefs

Technology

A 11 ID 4 415^46

W. Murray Bullis, Editor

Electron Devices Division Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards Washington, D.C. 20234

June 1979

Prepared for The Defense Advanced Research Projects Agency

The National Bureau of Standards

The Division of Electric Energy Systems, Department of Energy

The Division of Distributed Solar Technology, Department of Energy

The Defense Nuclear Agency

The Charles Stark Draper Laboratory

The Army Electronics Research and Development Command

\ir Force Avionics Laboratory

Slava! Material Command

Slaval Weapons Support Center

Solar Energy Research Institute
SEMICONDUCTOR TECHNOLOGY PROGRAM

TABLE OF CONTENTS Reverse-Bias Second Breakdown 3 Integrated Gated-Diode Electrometer . . 3 Random Fault Measurements 4 Pattern Generator Positional Accuracy . 4 Intrachip Linewidth Variation 5 Transient Upset in TTL Circuits .... 5 Photoresist Sensitometry 6 Optical Linewidth Measurements 7 Spreading Resistance Profiling 7 Model Spreading Resistance Data .... 8 Silicon Resistivity SRMs 8 Sheet Resistance Measurements 8 New Topics 9 Work in Progress 9 Recent Publications 9 Publications in Press 10

ABSTRACT - This report provides information on the current status of NBS work on measurement technology for semiconductor ma- terials, process control, and devices. Re- sults of both in-house and contract research

are covered. Highlighted activities include

studies of: reverse-bias second breakdown,

an integrated gated-diode electrometer, ran- dom fault measurements, pattern generator

positional accuracy, intrachip linewidth

variation, transient upset in TTL circuits,

photoresist sensitometry, optical linewidth

measurements, spreading resistance profiling, model spreading resistance data, sili- con resistivity SRMs, and sheet resistance measurements. In addition, brief descriptions of new and selected on-going projects

are given. The report is not meant to be exhaustive; contacts for obtaining further

information are listed. Compilations of re- cent publications and publications in press

are also included.

KEY WORDS: Elec tronics; integrated circuits; measurement technology; microelectronics; semiconductor devices; semiconductor materials; semiconductor process control; silicon.

Preface

This report covers results of work during the forty-third quarter of the NBS Semiconductor

Technology Program. This Program serves to focus NBS research on improved measurement technology for the use of the semiconductor device community in specifying materials,

equipment, and devices in national and international commerce, and in monitoring and con- trolling device fabrication and assembly. This research leads to carefully evaluated,

well-documented test procedures and associated technology which, when applied by the industry, are expected to contribute to higher yields, lower cost, and higher reliability

of semiconductor devices and to provide a basis for controlled improvements in fabrication processes and device performance. By providing a common basis for the purchase specifications of government agencies, improved measurement technology also leads to greater economy

in government procurement. Financial support of the Program is provided by a variety of Federal agencies. The sponsor of each technical project is identified at the end of each entry in accordance with the following code: 1. The Defense Advanced Research Projects

Agency; 2. The National Bureau of Standards; 3. The Division of Electric Energy Systems,

Department of Energy; 4. The Division of Distributed Solar Technology, Department of Energy; 5. The Defense Nuclear Agency; 6. The C. S. Draper Laboratory; 7. The Army Electronics

R&D Command; 8. The Air Force Avionics Laboratory; 9. The Naval Material Command; 10. The Naval Weapons Support Center; and 11. The Solar Energy Research Institute.

This report is provided to disseminate results rapidly to the semiconductor community.

It is not meant to be complete; in particular, references to prior work either at NBS or elsewhere are omitted. The Program is a continuing one; the results and conclusions re- ported here are subject to modification and refinement. Further information may be ob- tained by referring to more formal technical publications or directly from responsible

staff members, telephone: (301) 921-listed extension. General information, past issues of progress briefs, and a list of publications may be obtained from the Electron Devices Division, National Bureau of Standards, Washington, D.C. 20234, telephone: (301) 921-3786.

2

1
Semiconductor Technology Program

Progress Briefs

Reverse- Bias Second Breakdown

A qualitative model of transistor turnoff switching behavior has been developed. Typically, the voltage storage

time associated with turnoff is defined

as the interval between the initiation

of turnoff (base current reversal) and

the time at which the collector voltage

reaches 10% of its peak (usually

clamped) value. However, there is a significant interval between the time

that the device voltage begins to rise

above its saturation voltage (leaves sa- turation and enters quasi-saturation)

and the time it reaches 10% of its peak

value. This is because the collector

region of a typical modern power transistor is long and lightly doped. Significant power is dissipated during this

interval because the voltage is rising

and the current is constant at its peak

value. Depending upon the operating

conditions, 10 to 30% of the total energy dissipated during one turnoff cycle can be dissipated before the voltage

reaches 10% of its peak value. To' account for this region of high energy

dissipation, another time interval must

be defined. The voltage storage time

then becomes the time interval from the

initiation of turnoff until the time at which the device leaves saturation. The

other time interval, as yet unnamed,

which accounts for quasi-saturation, ex- tends from the time the transistor

leaves saturation until the time at which the collector voltage reaches 10%

of its peak value. Current crowding occurs only in this latter time interval.

Consequently, the voltage at which sec- ond breakdown occurs is most sensitive

to the magnitude of the reverse base

current during this time interval and is relatively insensitive to the magnitude

during the voltage storage time as newly

defined above. Preliminary experiments

confirm that the reverse base current

magnitude is not important ifs far as the

second breakdown voltage is concerned

until the device reaches its quasisaturation region. [Sponsor: 2] (D. L. Blackburn, x3621)

Integrated Gated-Diode Electrometer

Continuing studies of the integrated

gated-diode electrometer were carried

out. Experimental measurements of the

interactions between the designed elements of the circuit and the parasitic

circuit elements are being compared with

computer circuit simulations.* Preliminary conclusions reinforce confidence

both in the analytical model for the

equivalent circuit for this integrated

test structure and in the methods developed to measure the structure. Insights

have been obtained which provide alternative methods to overcome limitations

of the device. For example, it was ver- ified experimentally that a large fixed

capacitor, connected in parallel with

the diode junction, dominates both the

junction capacitance and parallel parasitic capacitances so that only the

added fixed capacitance need be considered when calculating the leakage current. Measurements of leakage current

with and without the capacitor give the same result, although the presence of

the additional large capacitance substantially decreases the output voltage

decay rate. Under certain circumstances, the tradeoff may be desirable

if it results in a more accurate measurement by reducing the effects of

parasitic capacitance.

As an extension of the utility of the

integrated test structure, pulsed capacitance measurements of the charge build-

*Design and fabrication of the test devices used in' the experiments and the computer simulations were carried out by the Westinghouse Advanced Technology

Laboratories, Baltimore, MD.

C
up in the gate inversion layer are being

investigated. In these measurements,

the diode gate is used as an MOS capacitor, and the diode junction and the

electrometer are employed as a chargesensing amplifier. Unlike conventional

capacitor transient measurements where

capacitance is measured as a function of

time following a voltage pulse which bi- ases the capacitor into deep depletion,

in this procedure the charge buildup in

the gate inversion layer is measured as

a function of time. Evaluation of the

experimental results awaits completion

of an analytical description of the time

rate-of-increase of the inversion layer

charge density, but it is anticipated

that this technique will complement the

gated-diode reverse-bias voltage decay

measurement by providing a second method

for measurement of bulk lifetime. An

extension of this technique would use

the integrated test structure to measure recovery time or storage time in a dynamic memory cell. In this application,

the diode gate functions as the transfer

electrode, and the diode junction and

electrometer operate as a charge integrator, a configuration analogous to the

charge-sensing output amplifier frequently used in CCDs. [Sponsors:

1,2,6] (G. P. Carver, x3541)

Random Fault Measurements

Initial test results have demonstrated

that the location of a fault can be

identified from electrical measurements

on memory-type MOSFET array test structures. In some cases, fault type has

also been identified electrically from

the data taken to date. Four such

structures appear on test pattern

NBS-16. This pattern is being used to develop process assessment methods to evaluate the electrical performance,

radiation tolerance, and yield of

radiation-hardened, silicon-gate

CMOS/SOS LSI circuits. Each randomfault test structure consists of a 10 by

10 array of rt- or p-channel MOSFETs

each with its gate connected to its

drain. The sources are connected in

Check plot of a typical p-channel MOSFET

array found on test pattern NBS-16 • The

probe pads around the periphery of the

array are 80 ym by 80 \xm. columns and the gates and drains are connected in rows, as illustrated in the

accompanying check plot of a typical pchannel MOSFET array. Each device is electrically isolated from its neighbors

(except for the common row and column

connections). Threshold voltage, breakdown voltage, and source-to-drain leakage current can be individually measured

for each MOSFET on the array by addressing the appropriate row and column probe

pads. Further analysis is continuing in order to establish improved criteria for

identifying fault types from electrical

data. [Sponsor: 8]

(L. W. Linholm, x3541)

Pattern Generator Positional Accuracy

The metal-to-doped region potent iometric

electrical alignment test structures on test pattern NBS-15 were used to evaluate the positional accuracy of a typical

computer-controlled pattern generator.

A composite 10X reticle was made up by

flashing the rectangles from the mask

levels for both the metal areas (mask

level 3) and the doped regions (mask

level 1) on the same plate. This reti4

}
cle was stepped and repeated to con- struct a IX working photomask. Two wafers were fabricated by contact printing

the pattern on an aluminum film evaporated on an oxidized silicon substrate

and defining the pattern by wet chemical

etching. The misalignment was measured

at 266 locations on each wafer. The mean value of the measured misalignment

(35 nm) is indicative of the positional

accuracy of the pattern generator. This

indicates that rectangles could be positioned within 350 nm on the 10X reticle,

well within the stated accuracy of the

pattern generator employed. Variability

in the alignment may be introduced by

the processing of the 10X reticle, the IX photomask, and the wafers. The average of the sample standard deviations

was 49 nm, which suggests that variability from processing exceeds the afterreduction positioning error of the pattern generator. [Sponsor: 1] (T. J. Russell, x3541)

Intrachip Linewidth Variation

Additional measurements of periodic and

random variations in linewidth over an integrated circuit wafer were made using

test pattern NBS-21 . This single-level

pattern consists of an 8 by 15 array of

identical cross-bridge sheet resistors

with a drawn linewidth of 0.600 mils

(15.24 ym) . The array fits within a square 200 mils (5.08 mm) on a side and

is repeated across the mask on 200-mil

centers each way. The pattern is fabricated by delineating (with the use of

contact printing and wet chemical etching techniques) the cross-bridge resistors in an 800-nm thick aluminum film

evaporated on an oxidized silicon wafer.

Each wafer contains 53 arrays. All the

arrays on a given wafer exhibited a similar pattern of linewidth variation

which was on the order of 0.2 ym for the

smallest to the largest value, as illustrated by the example of data from one row in the arrays across the diameter of

a wafer shown in the accompanying figure. Similar periodic variations have

been measured on other wafers from variLinewidth variations in one row of the

nine arrays across the diameter of a wafer as measured by the cross-bridge

structures of test pattern NBS-21 . ous lots, all fabricated with the same photomask. These periodic variations

can be attributed to the system used to fabricate the photomask. In addition,

variations over the wafer were observed

when the same structure in each array was measured. These variations, which

are also evident in the example shown in

the figure, can be attributed to the

photolithography associated with the

contact printing or to variations in etching the pattern or to both. The

range in measured linewidth across the

entire wafer was typically about 0.5 ym. [Sponsors: 1,2] L. W. Linholm, x3541)

Transient Upset in TTL Circuits

During an on-going study of transient

upset in digital integrated circuits,

being conducted in collaboration with

the Naval Research Laboratory, a temperature dependence of the upset threshold

was observed in standard transistortransistor logic (TTL) circuits. Preliminary results indicate that the

threshold increases with temperature

over the range from 20 to 150°C. Other

workers addressing this problem have

disagreed in predictions of the direction of the temperature dependence.

Based on the limited amount of data cur- rently available, it has been hypothesized that upset is due to photocurrent

generated in the depletion layer of the
collector-substrate junction. The de- crease in sensitivity to upset with increasing temperature in a standard golddoped TTL gate would result from the re- duction in thickness of the depletion

layer as the resistivity of the golddoped material decreases. The capacitance of the depletion layer in such a gate was measured and was found to in- crease with increasing temperature,

which supports this hypothesis. Further

support for the hypothesis is given by

the fact that in Schottky-clamped ver- sions of the same gate (74S series), the

upset sensitivity and the junction ca- pacitance do not depend significantly on temperature. The Schottky-clamped devices are not gold-doped. [Sponsor: 5]

(T. F. Leedy, x3621)

Photoresist Sensitometry

A more rapid and precise technique than

direct measurement of photoresist linewidth variations as a function of exposure has been found for measuring exposure characteristics of photoresist.

The linewidth measurement technique suffered both from the inability to locate

the line edges accurately and from large

variability in the resulting data. The

current technique is based on the property that the depth of photoresist dissolved during a controlled amount of development after exposure to a known

amount of monochromatic radiation corresponds to a specific fraction of photolysis. The depth of the exposed pattern

is measured with a surface prof ilometer

plots of log exposure against developed

depth of a positive resist exposed to radiation of wavelength 365, 405, or 436 nm (the three strong lines of high pressure, short arc mercury lamps typically

used in microelectronic patterning) show

a linear relationship. Examples of

these plots are given in the accompanying figure. The linear behavior is predicted from theoretical modeling of re- sist exposure performed and reported

previously. The development of this

technique represents an initial step in the complete characterization of resist

j i— 1 1 0.0 0.4 0.8 1.2 1.6 2.0 EXPOSED DEPTH, pm

Semilog plot of photoresist exposure , H, as a function of exposed depth , d, for a positive resist exposed to monochromatic

radiation of wavelength A. The data

follow the relationship

log H = log H o \ + <*\d . The quantity H is proportional to time

of exposure to a constant flux of radiation.

exposure. Each relation of monochromatic exposure against depth constitutes an element in the additive effect of these

exposures when a resist is simultaneously exposed to the complete radiation

spectrum of the mercury lamp. One unex- pected result was obtained: the 405-nm

radiation appears to be more effective

than the 365-nm radiation despite the

greater absorbance of the resist at 365

nm. In general, it had been assumed

that radiation of the wavelength for

which the resist exhibits the greatest

absorbance has the greatest effect on the resist exposure. The 436-nm radiation, which is least sensitive, also has

the lowest absorbance, and so follows

the expected trend. Also, an aging effect, a decrease in resist sensitivity

with time, was observed; this behavior

suggests that this method of resist ex- posure characterization may provide a tool for assessing resist shelf life and

aging effects. [Sponsor: 1]

(D. B. Novotny, x3621)

6 !
Optical Linewidth Measurements

The prototype system for optical linewidth measurements on wafers in re- flected light was completed. Linewidths

down to 0.5 ym can be measured with a sensitivity of 0.01 ym. For measurements of features with steep edges in

thin layers, the capability of the re- flected light system is comparable to that of the scanning photometric microscope developed earlier for measurements

on photomasks in transmitted light.

However, the two systems differ significantly. Both systems operate with Kohler illumination and modified bright

field illumination (the illuminating nu- merical aperture must be one-fourth or less of that of the imaging objective

for low contrast materials), but the re- flected light system uses a 0.5-W krypton laser source and a more sensitive

photomultiplier-detector system. In addition, the alignment requirements for

the optics of the reflected light system, which illuminate a much smaller

field of view, are more stringent than

those for the optics of the transmitted

light system. All of these conditions

result from the need for illumination

with very narrow spectral bandwidth

which is dictated by the strong wavelength dependence of both the reflectance and optical phase difference asso- ciated with thin films. The reflectedlight system produces image profiles

like that shown in the accompanying figure.* From such an image profile, the

linewidth is determined using the coherent optical threshold T c with appropriate corrections for the reflectances

of the materials and the optical path

difference which occurs at the edge on reflection. At the present time, both

the reflected light and transmitted

light systems are limited to films less

than 400 nm thick. For thicker layers

the edge detection equations are no longer valid and determination of best

focus is ambiguous. Research is under-

*To obtain this feature, the NBS linewidth calibration pattern (NBS 77) was contact printed from an anti-reflection chromium photomask and plasma

etched. The wafer pattern contains lines as narrow

as 0.55 pm. (Y. M. Liu, x3541)

DISTANCE Line image profile of a 3.9-\im line

etched in a 150-nm thick layer of sili- con dioxide on a silicon wafer • way to develop accurate edge detection

and focusing procedures for thick layers. [Sponsors: 1,2]

(D. Nyyssonen, x3621)

Spreading Resistance Profiling

A continuum formulation of spreading re- sistance correction factors was obtained

by deriving a differential equation for

the kernel of the correction factor integral in the limit as the layer thickness approaches zero. This differential

equation is nonlinear and inhomogeneous,

but, because it is of the Riccati type,

it can be transformed into a linear,

second-order equation which can be

solved analytically in several cases. The continuum form of the correction

factor was compared with the correction

factor generated from the multilayer

version of the Laplace equation description of spreading resistance for the case of a specimen with exponentially

varying resistivity. The difference between the results obtained from the two forms depends on the exponential constant, the total thickness of the structure, and (most importantly) the number

of layers used in the discrete form.

7
Typically, for the case of 11 layers,

the discrete form yields a factor about one- third that yielded by the continuum

form, but for the case of 201 layers the

difference is only about 6 %. These differences represent a fundamental limitation to the accuracy of the multilayer

correction factor. [Sponsor: 1]

(J. H. Albers, x3625)

Model Spreading Resistance Data

Studies were made of model spreading re- sistance data* for deep diffusions (up

to 90 ym) . For diffusions deeper than

about 5 ym, the simple relationship between spreading resistance, RS p(x),

and incremental sheet resistance,

Rs (x): , R (x) = — R (x) In — , sp 77 s a where s is the probe spacing and a is the effective contact radius, is no longer valid. It is found that, for all

diffused layers investigated, the

spreading resistance is approximately

linear in In s with a slope which is approximately proportional to the sheet

resistance. This result would indicate

that, for diffusions, probe spacing ex- periments could be safely interpreted in

terms of a sheet resistance, even though

the interpretation of the intercept as being related to the probe radius holds

only for uniform layers and shallow

diffusions. [Sponsor: 1]

(J. H. Albers, x3625)

Silicon Resistivity SRMs

Twenty sets of SRM 1522, Silicon Power

Device Level Resistivity Standard, have

been fabricated and individually measured and certified. This new standard

reference material is comprised of three

51-mm diameter slices of neutron transmutation doped (n-type) silicon with

nominal resistivities (at room temperature) of 25, 75, and 180 fi*cm. Each

*An annotated computer program to calculate model spreading resistance data is available on request. The program is written in double-precision UNIVAC

FORTRAN V.

slice is nominally 25 mils (0.64 mm)

thick. A two-operator two- instrument

experiment was performed on five speci- mens from each crystal to estimate the

precision of the certification measurements. Results of the experiment give

estimates of the 95% confidence interval

about the certified values as follows:

±0.2, ±0.4, and ±0.6% for the 25-, 75-,

and 180-Jl‘cm specimens, respectively.

[Sponsor: 2] (j. R. Ehrstein, x3625)

Sheet Resistance Measurements

Results of an inter laboratory experiment

on the measurement of the sheet resistance of thin silicon layers by the

four-probe method were analyzed. The

experiment was coordinated by NBS for

ASTM Committee F-l on Electronics. It was conducted to evaluate the precision

to be expected when ASTM Test Method

F 374, Sheet Resistance of Silicon Layers, is used for the measurement of lay- ers less than 3 ym thick. The procedure

requires the use of a probe assembly

with four blunt probe tips, terminating

either in a hemisphere with a radius between 100 and 250 ym or in a circular

truncation of a cone with a circle diameter between 100 and 250 ym. A probe

force between 0.30 and 0.80 N (31 and 82

gf) is required for either configuration

of probe tips. Six types of implanted

layers and two types of epitaxial layers were used as test specimens in the ex- periment. Layer thicknesses were between 0.2 and 1.5 ym, and layer sheet

resistance values were between 200 and

6000 $!/. The analysis, which accounted

for laboratory-to-laboratory differences, run-to-run differences within a given laboratory, and differences in the

six measurements on each specimen in any

run, indicated that overall precision

generally degraded with increasing

specimen sheet resistance. The precision can be expressed in terms of the

reproducibility interval for the average

of six measurements on a specimen, the

reproducibility interval being the 95%

confidence interval for the difference

in averages of specimen sheet resistance

8 !
measured by two different laboratories.

A conservative estimate for this reproducibility interval, which covers all

specimens tested, is ±10% of the average

sheet resistance value. [Sponsor: 2]

(J. R. Ehrstein, x3625, and J. Orban*)

New Topics . . . Applications of Neutron Transmutation

Doped Silicon — A survey is being

undertaken to determine the technical

impediments to more effective utilization of NTD silicon for thyristor production. During this period, discussions with several industrial users of

NTD silicon were completed to determine

present areas of concern in NTD usage

and to assess the potential for application of NTD silicon in other high power

devices. In addition, groups involved

in silicon materials research were also

contacted. Additional information from

individuals and organizations interested

in this topic is welcomed. [Sponsor:

3] (D. R. Myers, x3625)

Gallium Arsenide Characterization —

Evaluation of improved practical methods

for characterizing device quality galli- um arsenide substrates and epitaxial

layers was initiated. Initial activity

is directed toward extension to gallium

arsenide of measurement techniques for

silicon characterization. These include

capacitance-voltage profiling, resistivity and Hall measurements on van der

Pauw specimens, deep level transient

spectroscopy (DLTS), and spreading re- sistance measurements. In addition,

photo-DLTS and optical absorption measurements are being explored for applicability to characterization of semiinsulating gallium arsenide. [Sponsor:

7] (A. C. Seabaugh and R. Y. Koyama,

x3625 ) Work in Progress . . . An improved pattern for linewidth calibration artifacts has been designed.

*NBS-NRC Postdoctoral Research Associate, NBS Statistical Engineering Division.

The improvements are based on results

from the 10-laboratory evaluation of procedures for optical measurement ol linewidths in the 0.5- to 10- pn range on chromium photomasks with transmitted

light. Additional elements are included

in the artifact to enable the user to check for lead-screw errors in filar and

, image-shearing microscope eyepieces.

Several minor design changes were made

to reduce confusion in locating and

identifying each measurement element and to facilitate distinguishing the multiple lines in line-spacing measurements

with image-shearing eyepieces. Procurement of anti-reflective chromium and

iron-oxide artifacts with the improved

pattern was initiated. [Sponsors:

1,2] (J. M. Jerke, x362l)

Wafer maps of the forward voltage of

power rectifiers at low injection levels were previously found to be correlated

with the reverse leakage current; re- gions of high forward drop corresponded

to regions of low reverse leakage current. However, at values of forward

current exceeding the high injection

threshold, the correlation with reverse leakage is found to disappear abruptly.

This transition is related to the dependence of the forward drop on the carrier

lifetime. At low injection, the minority carrier lifetime dominates, whereas

at high injection the forward drop depends on the high level lifetime.

[Sponsor: 3] (R. Y. Koyama, x3625)

Recent Publications . . . *Weglein, R. D. , and Wilson, R. G., An

Acoustic Gray Scale for Scanning Acoustic Microscopy and Diagnostic Ultrasound, Ultrasound Imaging 1_, 89-100

(January 1979).

Sawyer, D. E., Kessler, H. K. , and

Schafft, H. A., Solar Cell Measurement

Technique Development and Other Services, Proc. Photovoltaic Advanced Materials Review Meeting , October 24-26,

1978, SERI/TP-49-105, CONF. 781017, pp. 41-50 (January 1979).

Reports of Contract Research.

C
Gilsinn, D. , and Kraft, R. , Semiconductor Measurement Technology

DISTRIB I, An Impurity Redistribution Computer

Program, NBS Spec. Publ. 400-57 (February 1979).

Russell, T. J., Maxwell, D. A., Reimann,

C. T., and Buehler, M. G. , A Microelectronic Test Pattern for Measuring Uniformity of an Integrated Circuit Fabrication Technology, Solid State Technology 22_ (2) 71-74 (February 1979).

*Weglein, R. D. , A Model for Predicting

Acoustic Material Signatures, Appl.

Phys. Letters 34^ 179-181 (1 February

1979).

Berning, D. W. , Semiconductor Measurement Technology: A Reverse-Bias Safe

Operating Area Transistor Tester, NBS

Spec. Publ. 400-54 (March 1979).

^Goldsmith, N., and Mayer, A., High-Speed

Spreading Resistance Probe, NBS-GCR-79-

166 (March 1979).

Mayo, S., and Evans, W. M. , Development

of Hydrogen and Hydroxyl Contamination

in Thin Silicon Dioxide Thermal Films,

NBSIR 78-1558 (March 1979).

Russell, T. J., and Maxwell, D. A.,

Semiconductor Measurement Technology:

A Production-Compatible Microelectronic

Test Pattern for Evaluating Photomask

Misalignment, NBS Spec. Publ. 400-51

(April 1979).

Publications in Press . . . Buehler, M. G., Microelectronic Test

Patterns with Test Structures Designed

Within a 2 by N Pad Array, Proc. Microelectronics Measurement Technology

Seminary San Jose, CA, February 6-7,

1979.

Carver, G. P. , and Buehler, M. G. , The

Development of Test Structures for

Characterization of the Fabrication and

Performance of Radiation-Hardened CCD

Imagers, NBSIR 79-1744.

Dickey, D. H., and Ehrstein, J. R. , Semiconductor Measurement Technology:

Spreading Resistance Analysis for Silicon Layers with Nonuniform Resistivity,

NBS Spec. Publ. 400-48.

Ehrstein, J. R. , Two-Probe (Spreading

Reports of Contract Research.

Resistance) Measurements for Evaluation

of Semiconductor Materials and Devices,

Nondestructive Evaluation of Semiconductor Materials and Devices , NATO Advanced Study Institute, Frascati,

Italy, September 18-30, 1978.

Galloway, K. F. , Mayo, S., and Roitman,

P., Radiation Levels Associated with

Advanced Lithographic Techniques, J

,

Electrochem, Soc.

Galloway, K. F. , and Mayo, S. , Radiation

Levels Associated with the Electron

Beam Metallization Process, Solid State

Technology

,

*Ham, W. E., Semiconductor Measurement

Technology

A Comprehensive Test Pattern for SOS Technology, NBS Spec.

Publ. 400-56.

Harman, G. G., Nondestructive Tests Used

to Insure the Integrity of Semiconductor Devices with Emphasis on Passive

Acoustic Techniques, nondestructive

Evaluation of Semiconductor Materials

and Devices

,

NATO Advanced Study Institute, Frascati, Italy, September 18-30,

1978.

*Helms, C. R. , The Morphology and Electronic Structure of Si-Si0 2 Interfaces

and Si Surfaces, J, Vac . Soc , Tech

*Kasden, H. L. , Linewidth Measurements by

Diffraction Pattern Analysis, NBS-GCR78-142.

Koyama, R. Y., and Buehler, M. G., Novel

Variable-Temperature Chuck for Use in the Detection of Deep Levels in Processed Semiconductor Wafers, Rev, Sci.

Instrum,

Leedy, T. F. , LSI Digital Testing — An Annotated Bibliography, NBS Tech. Note

1102 . *Li, S. S., Semiconductor Measurement

Technology

The Theoretical and Experimental Study of the Temperature and

Dopant Density Dependence of the Hole

Mobility, Effective Mass, and Resistivity in Boron-Doped Silicon, NBS Spec.

Publ. 400-47.

Myers, D. R. , Koyama, R.Y., 'and Phillips, W. E., An Implantation Predeposition Technique for Deep Level Characterization, Radiat, Eff.

Myers, D. R. , Roitman, P., and Mayo, S.

,

Electrical Characterization of Low-Dose

(Continued on Back Cover)

} 10
NBS-114A (REV. 9-78) U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBSIR 79-1591-3

2.Gov,LAccOTsl«f*o. 3. Recipient $ Accesstw No.

4. TITLE AND SUBTITLE Semiconductor Technology Program — Progress Briefs

5. Publication Date June 1979

7. AUTHOR(S) W. Murray Bullis, Editor

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS NATIONAL BUREAU OF STANDARDS DEPARTMENT OF COMMERCE

WASHINGTON, DC 20234

.

11. Contract/Grant No. See item 15

12. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street, City. State. ZIP) NBS, Washington, DC 20234; ARPA, Arlington, VA 22209; DNA, Washington, DC

20305; Dept, of Energy, Washington, DC 20545; C. S. Draper Laboratory,

Cambridge, MA 02139; AFAL, Wright-Patterson AFB, OH 45433; Army Electronics

R&D Command, Ft. Monmouth, NJ 07703; NavMat Command, Hdqtrs., Washington, DC

20360; NWSC , Crane, IN 47522; SERI, Golden, CO 80401.

13. Type of Report & Period Covered Interim

Jan. - Mar. 1979

.

i

15. SUPPLEMENTARY NOTES ARPA 0rder 3397 , Program Code 9Y10; DNA IACRO 79-821; Dept, of Energy, Interagency Agreement EX-77-A01-6010, T. 0. A021-EES and T. O. A054-SE; C. S. Draper Laboratory, P. O. DL-H-162208

(Navy contract N 00030-78-C-0100) ; AFAL, MIPR FY117578N2062; Army Electronics, R&D Command, P. O. 78- 09423; NavMat Command, P. O. N0003778IP89010; NWSC, P. 0. N0016479WR30036; SERI, XD-S-0959-1-01

16. ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant bibliography or

literature surrey, mention it here.) This report provides information on the current status of NBS work on measurement

technology for semiconductor materials, process control, and devices. Results of both in-house and contract research are covered. Highlighted activities include

studies of: reverse-bias second breakdown, an integrated gated-diode electrometer, random fault measurements, pattern generator positional accuracy, intrachip

linewidth variation, transient upset in TTL circuits, photoresist sensitometry

optical linewidth measurements, spreading resistance profiling, model spreading

resistance data, silicon resistivity SRMs, and sheet resistance measurements. In addition, brief descriptions of new and selected on-going projects are given. The

report is not meant to be exhaustive; contacts for obtaining further information

are listed. Compilations of recent publications and publications in press are also included.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name;

separated by semicolons) Electronics; integrated circuits; measurement technology; microelectronics; semi- conductor devices; semiconductor materials; semiconductor process control; silicon.

18. AVAILABILITY [£} Unlimited

I | For Official Distribution. Do Not Release to NTIS

I | Order From Sup. of Doc., U.S. Government Printing Office, Washington, DC

20402, SD Stock No. SN003-003-

ItT~1 Order From National Technical Information Service (NTIS), Springfield, VA. 22161

19. SECURITY CLASS

(THIS REPORT)

UNCLASSIFIED

20. SECURITY CLASS

(THIS PAGE)

UNCLASSIFIED

21. NO. OF

PRINTED PAGES 12

11

22. Price $4.00

U SCO MM- D C

£9
(Continued from Page 10) Ion Implanted Silicon Annealed with Microsecond Laser Pulses, Proc. MRS Syrrrp. on Laser-Solid. Interactions and Laser

Processing, Boston, MA, November 28-

December 1, 1978 (AIP Symposium

Series )

Myers, D. R. , and Wilson, R. G. , Alignment Effects on Implantation Profiles

in Silicon, Radiat . Eff.

Nyyssonen, D. , Optical Linewidth Measurement — A Basic Understanding, Proc

Microelectronic Measurement Technology

Seminar, San Jose, CA, February 6-7,

1979.

Rubin, S., and Oettinger, F. F. , Semiconductor Measurement Technology: Thermal Resistance Measurements on Power Transistors, NBS Spec. Publ. 400-14.

Schafft, H. A., Semiconductor' Measurement Technology : Reliability Technology for Cardiac Pacemakers III — A Workshop Report, NBS Spec. Publ. 400-

50. Schafft, H. A., Performance Criteria for Photovoltaic Power Conditioning, Control, and Storage, Proc . DoE Photovoltaic Technology Development and Applications Program Review, Arlington, VA,

Reports of Contract Research.

November 7-9, 1978.

Schafft, H. A., Standards for Photovoltaic Energy Conversion Systems, NBSIR

79-1743.

*Schwarz, S. A., and Helms, C. R. , A Sta- tistical Model of Sputtering, J. Appl.

Phys.

*Schwarz, S. A., and Helms, C. R. , An Ion Knock-On Mixing Model with Application

to Si-Si02 Interface Studies, J. Vac. Sci . Tech.

*Sulouff, R. E., Investigation of Moisture Measurement, Failure Rate, and

Leak Rate and Study of Moisture Infusion, NBS-GCR-78-144.

*Wilson, R. G., and Comas, J., Correlation of Atomic Distribution and Implantation Induced Damage in Be Ion- Implanted Silicon, Radiat. Eff.

*Wilson, R. G., and Comas, J. , Channeling

and Random Equivalent Depth Distributions of 150-keV 3Li, ^Be, and 1 |b Im- planted into <100> and <1 1 0 > Silicon,

Radiat. Eff.

Wilson, R. G., and Weglein, R. D.,

Acoustic Material Signatures Using the Reflection Acoustic Microscope, Proc. 1st Intemat. Symp. Ultrasonics Matls.

Characterization, Washington, DC, June

8-10, 1978.

/ V \

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U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary

Jordan J. Baruch, Assistant Secretary for Science and Technology

NATIONAL BUREAU OF STANDARDS. Ernest Ambler. Director

!