NBS

PUBLICATIONS

A 11 IDE 7 E T ^ NBSIR 87-3668

The Effect of the Gate Oxide

Thickness on the Speed of MOS

Integrated Circuits

J. S. Kim

U.S. DEPARTMENT OF COMMERCE

National Bureau of Standards

National Engineering Laboratory

Center for Electronics and Electrical Engineering

Semiconductor Electronics Division

Gaithersburg, MD 20899

December 1987

U.S. DEPARTMENT OF COMMERCE

NATIONAL BUREAU OF STANDARDS — QC —

100

. U56

87-3668

1987

C . 2

NBSIR 87-3668

Research Information Center

National Bureau of Standards

Gaithersburg, Maryland 20899

THE EFFECT OF THE GATE OXIDE

THICKNESS ON THE SPEED OF MOS

INTEGRATED CIRCUITS

Wl

J. S. Kim

U.S. DEPARTMENT OF COMMERCE

National Bureau of Standards

National Engineering Laboratory

Center for Electronics and Electrical Engineering

Semiconductor Electronics Division

Gaithersburg, MD 20899

December 1987

U.S. DEPARTMENT OF COMMERCE, C. William Verity, Secretary

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director

TABLE OF CONTENTS

Page

Abstract 1

I. Introduction 1

II. General Consideration ...................... 2

III. Effect of Scaling on Propagation Delay ............... 4

IV. Conclusion 7

Acknowledgment 8

References 8

in
LIST OF FIGURES

Page

Figure 1. The equivalent circuit for the initial stages of the CMOS

inverter delay chain ..................... 9

Figure 2. Evolution of a step input signal propagating along the delay

chain .... ........................ 10

Figure 3. The propagation delay as a function of the oxide thickness for

selected values of input parameters ............... 11

LIST OF TABLES

Table I. Status of Transistors in the Initial Stage of the Inverter Circuit . . 12

Table II. Values of Xm (nm) ...................... 13

iv
THE EFFECT OF THE GATE OXIDE THICKNESS

ON THE SPEED OF MOS INTEGRATED CIRCUITS

J. S. KIM

IC Technology Group

Semiconductor Electronics Division

National Bureau of Standards

Gaithersburg, Maryland 20899

ABSTRACT

A simple analysis is presented for the effect of the gate oxide thickness on the circuit

speed in a short-channel CMOS inverter delay circuit . The present analysis is performed

within the first-order theory of the MOS transistor. The result of the analysis shows that an

optimum value of the gate oxide thickness exists, beyond which a further scaling of the gate

oxide will not improve, but will degrade, the circuit speed. The circuit speed corresponding

to this optimum oxide thickness is the ultimate upper limit theoretically possible in a given

MOS integrated circuit. The optimum value of the gate oxide thickness, to the first order

approximation, is proportional to the channel width W, but it is independent of the channel

length L. In particular, for wide channel devices, this optimum value exceeds the 5-nm to

30-nm range, which is of practical significance in the design and processing of advanced

VLSI circuits. At the optimum oxide thickness, the square-root of the net propagation

delay resolves into two components; the square-root of the net delay is the sum of the

square-root of a purely parasitic component and that of a device-dependent component.

Also it is shown that the transverse field dependence of the channel mobility enhances

the parasitic effect; i.e., it tends to increase further the the optimum thickness of the gate

oxide.

Key words: device optimization; oxide scaling; propagation delay; sealing effect; thin gate

oxide; VLSI.

I. INTRODUCTION

The speed of the signal propagation is a key parameter in the performance of MOS integrated circuits. The primary objective of the present VLSI or VHSIC effort is to obtain

the circuit speeds and the device packing densities as high as possible. This will result

in the smallest possible size of the individual device. The scaling of the device geometry,

on the other hand, imposes many difficulties on both device processing and modeling. In

particular, the scaling of the gate oxide thickness causes severe yield and reliability problems. Since the supply voltage cannot be reduced by the same scaling factor as other

parameters, the electric field in the gate oxide of a scaled MOS device is very high under

normal operating conditions. Aside from these reliability and yield problems, the scaling

of the gate oxide thickness may affect the circuit speed of MOS integrated circuits.

Traditionally, the circuit speed analysis has been focused mainly on the effect of the channel

length but seldom on the scaling effect of the gate oxide thickness [1], It is generally

1
assumed that the thinner the gate oxide, the better the circuit performance. However,

this assumption is valid only for an ideal case where each individual transistor does not

have any paxasitics. In real circuits, the individual transistor always is associated with

parasitics such as the series resistance or the stray capacitance. The inclusion of these

paxasitics in the analysis of the circuit speed has seldom been reported.

The purpose of the present paper is to show that inclusion of the transistor paxasitics results

in a finite lower bound of the gate oxide thickness, beyond which a further scaling of the

gate oxide thickness does not improve, but degrades, the circuit speed. The present analysis

is performed within the first-order theory of the MOS transistor, neglecting second-order

effects such as the short-channel effect, the channel-length modulation, and the charge

sharing. But the effect of the mobility degradation arising from the high transverse electric

field is considered in this work.

Qualitatively, the existence of a lower bound for the optimum oxide thickness can be ex- plained as follows. The propagation delay is approximately proportional to the RC time

constant of the individual MOSFET. The capacitive and resistive components of the individual MOSFET should be considered to be a combination of paxasitics and components

resulting from the device itself. In the region where the gate oxide thickness is very small,

the gate capacitance increases toward infinity as the oxide thickness decreases toward zero,

but the resistance component remains as a non-zero, finite quantity. Therefore, the RC

time constant, which is the product of these two quantities, increases. In the other re- gion, where the thickness is very laxge, the channel resistance of the transistor increases

with increasing oxide thickness, but the capacitance component remains as a non-zero

value due to the parasitic capacitance. Thus the circuit speed again degrades as the oxide

thickness increases. Therefore, an optimum thickness for the gate oxide must exist in the

intermediate region.

The propagation delay corresponding to this optimum value of the gate oxide thickness

gives the fastest circuit speed theoretically possible in a given MOS integrated circuit.

It is very important for the design and processing of integrated circuits to determine

this optimum value, for it determines not only the optimum circuit performance, but

also relaxes many constraints which axe imposed on the present device processing by the

stringent device scaling.

II. GENERAL CONSIDERATION

In this section, a simple analytical expression is formulated for the signal propagation delay

in a CMOS inverter chain. Figure 1 shows the equivalent circuit for the first several stages of

the delay chain. P, N, V, J, and r denote the p-channel transistor, the n-channel transistor,

the node voltage, the current, and the delay, respectively, in each stage. The subscript of

these quantities identifies the corresponding stage. Cp

is the parasitic capacitance. The

series resistance Ra , which may include all the resistive components except the transistor

channel resistance in each stage, is assumed to be distributed symmetrically at both ends of

the transistor. Considering the carrier mobility ratio and the resulting design optimization,

we may assume:

2
( 1 )

Ln — Lp = L

WP WN = — = w

2

UN = 2/ip = fi Vtn = —Vtp — Vp

Von = —Vop = Vo,

where X, W, p, Vp, and Vo are the channel length, the channel width, the carrier mobility,

the threshold voltage, and the switching voltage, respectively. The switching voltage Vo

is defined as the voltage which triggers the switching action of the next stage transistor

and can be set Vo ~ 2Vp. The subscript P and N denote the p- and n-channel device,

respectively. From eq (l), the gate capacitance of the transistors is:

C

gN — WLC0 (n-channel device)

CgP = 2 WLC0 [p- channel device)

where CQ = e/X0 , e ~ 3.4x10 13 F/cm; C9n and Cgp are the gate capacitance of n- and

p-channel MOSFET, respectively.

The net propagation delay in each stage can be considered to be a combination of two

components, namely, the inversion layer build-up time and the gate capacitance charging

time as follows:

— 7~inv

Cp + 3 CoWL

Ii

dVi ,

( 3 )

where tv, 7», and Vi are the propagation delay, the current, the voltage in the i th stage,

respectively; Vu and V/ are appropriate integration limits; and Tvnw is the time for the

inversion layer build-up. Note that, for a given delay circuit, Jj is uniquely determined by

Vi _ 1 and Vi which determine the gate voltage and the drain voltage of the active transistor

in the i th stage.

Ti is defined as the time interval between the switching onset time of the i th stage and

that of the (i + l)

t/l stage. Generally, the delay corresponding to a particular stage may

be different from that of an adjacent stage because of gradual degradation of the input

signal propagating along the delay chain. In particular, for a step input

0 (t < 0)

Vdd ( t > 0 ),

( 4)

the series {t2 *+i} and {r2 i} converge to an upper limit tn and rp, respectively, as i increases. Figure 2 shows the evolution of the step input as a function of time t for

the first three stages. If the convergence is rapid enough, the propagation delay can be

3
defined as the average of these two characteristic time constants [2]. Table I shows the

inter-relationship of relevant quantities between adjacent stages.

III. EFFECT OF SCALING ON PROPAGATION DELAY

Since the first stage delay t* is a good indicator of the net delay rpd, only the first stage

delay T\ is evaluated, which is denoted simply as r from now on. At t — 0, the n-channel

transistor Ni is turned on, hence the drain current I\ of transistor N\ begins to discharge

the net gate capacitance of the first stage, as shown in figures 1 and 2. Note that this net

capacitance 3WLC0 -\-Cpis the sum of the gate capacitances of transistor N2 and transistor

P2 , and the parasitic capacitance. Subsequently, as Vi decreases from Vdd-, the effect gate

voltage of transistor P2 increases. At t = r, V\ — Vdd ~ VQ , hence the switching of the

second stage begins, i.e., transistor P2 becomes active. Equation (3) may be rewritten, if

the term T{nv is neglected for simplicity, as follows:

r L

VDD -V0

VD d

('cp + 3WLC„

)

dV. (5)

The subscript 1 is left out in eq (5) for simplicity.

The expression for the drain current I [3] should be modified as follows:

I = ^co{~\vdd-Vt -^){V- ir,). ( 6 )

By re-arranging eq (6), we obtain for two operations of the switching transistor:

/ Ra

| 2 L

1 v. v.C0 WV* (saturation region)

(7) I *1 +

i. K v ^ nC0 W(Vt -\)V (linear region).

where V$ = Vdd — Ft and Vo = 2V?• Assume that the transistor N\ of the first stage

operates in the saturation region for t < r, since both the effective gate voltage and the

drain voltage of transistor N\ are Vdd initially for a step input signal. This may not

generally be true as the input signal degrades at a later stage, where the linear region

of the switching transistor operation becomes important. Therefore, one can expect a

mixture of these two regions of operation in a single switching action and should consider

both the linear- and the saturation-region of operation in performing the integral in eq

(5). Fortunately, the only difference between these two cases is a slight difference in the

numerical scaling factor a contained in the expression of r, as will be seen shortly.

The final expression for the propagation delay can be obtained by performing the integration from eqs (5) and (7):

r = a(r0 + a^L + a2 L

2

) where r0 , ai, and <Z2 are given by

( 8)

4
(9)

To = Ra Cp

2(7

ai =

pCoV'W

+ 3CoRaW

6

02 =

~1F [AVs

where Va = Vqd — Vt- If the switching transistor operates either in the linear region or

in the saturation region only, then from eqs (5) and (7), the scaling factor a is given by:

a

2Vx_

Vdd —2 Vt (saturation region)

ln

( vpc-

'zVt )

(linear region).

( 10 )

Equation (10) shows that, as mentioned earlier, the scaling factor a depends only on voltage

values through integration limits in eq (5) and the operation mode of the the switching

transistor. By superposition, the scaling factor a can be expressed generally as a weighted

average of the value of the linear region and that of the saturation region. Therefore, the

expression of eq (8) for the propagation delay should be applicable more generally than

under specific conditions considered in the present analysis, if the numerical factor a is

modified accordingly.

There axe two important features in eqs (8) to (10) which are:

1) The propagation delay is of a quadratic form with respect to the channel length

L. The constant term r0 = Ra Cp depends only on the parasitic components and

is completely independent of the transistor parameters. The propagation delay

does not have an extremum with respect to the channel length for L > 0; hence it increases monotonically with increasing channel length. This is the rationale behind

the whole effort on the submicron VLSI technology.

2) The gate oxide thickness dependence of the propagation delay appears only in the

coefficient a\ through CQ = e/XQ . As will be shown later, an optimum value for the

gate oxide thickness exists which provides the smallest possible propagation delay.

This aspect is as a direct result of including parasitics in the analysis and may have

a significant impact on the design and fabrication of scaled-down VLSI circuits.

In order to assess quantitatively the effect of scaling of the gate oxide, note that the

dependence of the propagation delay on the thickness of the gate oxide XQ is contained

only in the coefficient a\ in eq (9). Therefore, one obtains from eqs (8) and (9)

dr

dX~o

da\

2 Cp

\iVa WCQ

2 + 312, W

dCQ

dX0

'

( 11 )

5
In performing partial differentials in eq (11), it is assumed that the threshold voltage V?

will be independent of the oxide thickness, since the threshold voltage of the transistors is

usually predetermined by the circuit optimization and is kept constant accordingly during

the device fabrication process. The dependence of the channel mobility on the gate oxide

thickness, which manifests itself as the mobility degradation due to the increased transverse

field for thinner gate oxides, is also neglected for the time being, but its net effect will be

treated qualitatively later. By equating the right-hand-side of eq (11) to 0, one obtains

2CP

tiV.WCo2 + 3R.W = 0. ( 12)

Equation (12) has only one positive root with respect to C70 . The corresponding value of

the gate oxide thickness Xrn is given by

Xm = eW 3fiVa Rs 2Cr (13)

where the relationship CQ — tj

Q is used. Since the second derivative of ai, hence r, with

respect to XQ is always positive as can be shown from eqs (8) and (9), the propagation

delay takes its minimum value at XQ = Xm if plotted against XQ . From eqs (8) and (13),

this minimum delay rm is given by = V^(v^ + V^)

where

(14)

To = Ra Cp

6L2

• (15)

Td = —rr

fdVa The sum rule as shown in eq (14) implies that the square-root of the net propagation delay

can be resolved into two components: a purely parasitic term which is entirely independent

of the transistor used, and a purely device dependent term associated only with the carrier

transport in the channel.

Figure 3 shows the propagation delay per stage, r, as a function of the gate oxide thickness X0 for several different values of relevant device parameters, each curve showing a

minimum. The values of optimum oxide thickness for various combinations of relevant parameters are listed in Table II. Note that Xm varies from several nanometers to several tens

of nanometers, which typically represent the thickness of the gate oxide used in the present

and future VLSI circuits. The existence of an optimum value Xm has a very important

bearing in microelectronics technology. The circuit speed cannot be improved indefinitely

by scaling-down the gate oxide thickness, but a further scaling of the gate oxide thickness

beyond the optimum value Xm will degrade the circuit speed.

By adjusting the geometrical parameters L and W of MOS transistors, Xm and rm can be

varied. Therefore, the existence of the optimum value Xm has a very important bearing on

6
the design of the individual MOSFET in an MOS integrated-circuit. Note again that the

optimization of the circuit speed through the gate oxide thickness adjustment affects only

the linear term in the net propagation — the term which is proportional to the channel

length of the MOSFET as shown in eq (8). One of the main objectives of the future VLSI

technology is to increase the circuit speed by reducing the channel length. In eq (8), the

first term rQ in the parenthesis on the right-hand-side will not be affected by the device

scaling and the third term will be negligible compared to the linear term as the channel

length becomes small, thus leaving the linear term as the only meaningful component for

scaled-down devices. The present analysis shows that a situation may arise, particularly

for scaled-down, wide-channel MOS integrated circuits, where a further scaling of the gate

oxide is both undesirable and deleterious to the circuit performance.

Since the supply voltage in integrated circuits cannot be scaled as other device parameters,

reducing the thickness of the gate oxide increases the effective transverse electric field in the

channel region. This increased transverse field is known to degrade the channel mobility

[4]. Therefore, the partial derivative d[i/dX0 , which has been assumed to be 0 in all

previous steps, must be taken into account in deducing the expression for the optimum

oxide thickness shown in eq (13) in order to include this XQ - dependence of the mobility.

This will lead to the following expression for the modified optimum oxide thickness in

place of eq (13):

XM = /Xm , (16)

where Xm is the optimum oxide thickness for ft = d[i/dX0 = 0, and the correction factor

/ is given by

3eWL\

(17)

Since (3 = dfi/dXQ > 0, one always gets f > 1. This implies that the effect of the mobility

degradation is always to increase the optimum thickness of the gate oxide.

IV. CONCLUSION

The effect of scaling of the gate oxide thickness on the propagation delay has been analyzed.

The result shows that a lower bound in the gate oxide thickness always exists which gives

the maximum circuit speed. The existence of this lower bound is a direct result of transistor

paxasitics interacting with the circuit. The position of this lower bound depends on the

series resistance, parasitic gate capacitance, the channel width, the channel length, the

channel carrier mobility, the turn-on voltage, and the supply voltage. The value of the

lower bound increases linearly with increasing channel width but does not depend on the

channel length within the approximation regime used in the present analysis where higherorder effects such as short-channel effect have been ignored for simplicity. It is also shown

in this work that inclusion of the mobility degradation resulting from the gate oxide scaling

tends to increase the optimum oxide thickness toward values larger than those shown in

Table II. Theoretically, inclusion of higher order effects such as short-channel effect is a

7
worthy effort. Experimentally, a test structure having delay chains can be fabricated with

varying gate oxide thickness and the propagation delay can be measured.

ACKNOWLEDGMENT

The author would like to thank H. S. Bennett, D. L. Blackburn, H. C. Lin, and L. W.

Linholm for their critical reading of the manuscript. He also acknowledges the comments

on the manuscript made by M. H. White.

REFERENCES

1. M. H. White, Characterization of CMOS Devices for VLSI, IEEE Trans. Electron

Devices ED-29, 578 (1982).

2. J. Milman, Microelectronics (McGraw-Hill, 1979), p. 161.

3. S. M. Sze, Physics of Semiconductor Devices (Wiley, 1969), pp. 519-520.

4. O. Leistiko, A. S. Grove, and C. T. Sah, Electron and Hole Mobilities in Inversion

Layers on Thermally Oxidized Silicon Surfaces, IEEE Trans. Electron Devices ED12, 248 (1965).

8
Rs

/2fRs

/2^Rs

/2 9

Figure

1.

The

equivalent

circuit

for

the

initial

stages

of

the

CMOS

inverter

delay

chain.
10

Figure

2.

Evolution

ofa

step

input

signal

propagating

along

the

delay

chain.
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(S) AV13Q NOLLVDVdOHd

11

Figure

3.

The

propagation

delay

as

a

function

of

the

oxide

thickness

for

selected

values

of

input

parameters.
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TABLE

II.

Values

of

X

m

(nm)

13
NBS-1T4A (rev. 2-80

U.S. DEPT. OF COMM.

4 .

BIBLIOGRAPHIC DATA

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1. PUBLICATION OR

REPORT NO.

NBSIR 87-3668

2. Performing Organ. Report No. 3.

TITLE AND SU BTITLE

Publ ication Date

December 1987

The Effect of the Gate Oxide Thickness on the Speed of MOS Integrated Circuits

5. AUTHOR(S)

J. S. Kim

6. PERFORMING ORGANIZATION (If joint or other than N BS. see in struct ion s) 7. Contract/Grant No.

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE 8. Type of Report & Period Covered

WASHINGTON, D.C. 20234

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street. City. State, ZIP)

10.

SUPPLEMENTARY NOTES

Document describes a computer program; SF-185, FlPS Software Summary, is attached.

11.

ABSTRACT (A 200‘word or less factual summary of most significant information. If document includes a si gn i fi cant

bi bl i o graph y or literature survey, mention it here)

A simple analysis is presented for the effect of the gate oxide thickness on the

circuit speed in a short-channel CMOS/inverte r delay circuit. The present analysis

is performed within the first-order theory of the MOS transistor. The result of the

analysis shows that an optimum value of the gate oxide thickness exists, beyond

which a further scaling of the gate oxide will not improve but degrade the circuit

speed. The circuit speed corresponding to this optimum oxide thickness is the

ultimate upper limit theoretically possible in a given MOS integrated circuit. The

optimum value of the gate oxide thickness, to the first order approximation, is

proportional to the channel width W, but it is independent of the channel length L.

In particular, for wide channel devices, this optimum value exceeds the 5 nm - 30 nrn range, which is of practical significance in the design and processing of advanced

VLSI circuits. At the optimum oxide thickness, the square-root of the net

propagation delay resolves into two components; the square-root of the net delay is

the sum of the square-root of a purely parasitic component and that of a device-dependent component.

12.

KEY WORDS (Six to twelve entries; alphabetical order; capi ta I i ze on ly proper names; and separate key words by semicolons)

device optimization; oxide scaling; propagation delay; sealing effect; thin gate

oxide; VLSI

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