# Patent

## Title
Method and device for reducing bit error rate in CDMA communication system

## Abstract

A method and a device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system are described, wherein this method includes: a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q are obtained, and the signals are sent by a signal sending end; the obtained sample sequence Iin and the sample sequence Qin are divided into different groups according to a sample number Ns of a chip, a sum-average operation is performed on a signal in each group, and a corresponding signal group is determined, wherein, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and a signal in the signal group WI and the signal group WQ is grouped to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, and the determined signal is output. The disclosure solves a problem in the related art that a CDMA synchronization method possesses a wrong sampling situation, which results in a high bit error rate of a receiving end, and reduces the bit error rate.

## Background
TECHNICAL FIELD
The disclosure relates to the field of communications, and particularly to a method and a device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system.
BACKGROUND
In a CDMA communication system, a data transmission synchronization problem is very important, if the data transmission synchronization problem of a receiving end and a sending end, it may be caused that a transmission device cannot perform normal communication. There are many traditional CDMA system synchronization methods, for example, in a synchronization capture phase, the sending end first sends a synchronization sequence to the receiving end, and the receiving end establishes synchronization between the receiving end and the sending end after receiving the synchronization sequence of the sending end, and then switches to a data state to perform data transmission. This synchronization method adopts different Pseudo-Noise (PN) codes in a synchronization signal capture phase and a data processing phase. Currently, a typical representative synchronization algorithm of a spreading chip STEL-2000A adopts twice sampling at a front end of a digital matched filter, a sample value after twice sampling and weighted averaging is sent to the matched filter.
A similarity of a traditional synchronization method is to use a relevant feature of the PN code to perform synchronization of the receiving end and the sending end, a difference is a chip sampling time of the front end of the matched filter. However, with regard to a relatively maturely applied currently CDMA synchronization technique, a wrong sampling situation at the front end of the matched filter is neglected. Specifically, an ideal sampling situation is shown in FIG. 1 (a), that is, chips di−1, di, di+1 sample twice separately, and samples correspond to each chip separately are ai−1, bi−1, ai, bi, ai+1, bi+1, and weighted average is performed on information sampled by each chip, namely (ai−1+bi−1)/2, (ai+bi)/2, (ai+1+bi+1)/2. However, in actual operation, this situation may exist: the weighted twice samples do not come from the same chip, but come from adjacent chips, as shown in FIG. 1 (b) or FIG. 2, after the sample is weighted, (ai+bi)/2 is sent to the matched filter, because ai and bi do not come from the same chip, that is wrong sampling is caused. In addition, although it is in the ideal sampling situation, wrong sampling may be caused all because of data jitter, delay, jitter of a local clock, and a Doppler effect. The wrong sampling may bring a serious inter-chip interference, the wrong sampling at a place at which a positive electrical level and a negative electrical level of a PN chip alternate results in a very small weighted sample value, and finally results in a high bit error rate of the receiving end.
Aiming at a problem in the related art that a CDMA synchronization method possesses the wrong sampling situation, which results in a high bit error rate of the receiving end, an effective solution has not been proposed currently.
SUMMARY
An embodiment of the disclosure provides a method and a device for reducing a bit error rate in a CDMA communication system, so as to solve a problem in the related art that a CDMA synchronization method possesses a wrong sampling situation, which results in a high bit error rate of a receiving end.
In order to solve the above technical problem, in one aspect, an embodiment of the disclosure provides a method for reducing a bit error rate in a CDMA communication system, which includes: obtaining a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q, which are sent by a signal sending end; dividing the obtained sample sequence Iin and the sample sequence Qin into different groups according to a sample number Ns of a chip, performing a sum-average operation on a signal in each group, and determining a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and grouping a signal in the signal group WI and the signal group WQ, to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, and outputting the determined signal.
Preferably, the dividing the obtained sample sequence Iin and the sample sequence Qin into different groups according to the sample number Ns of the chip, performing the sum-average operation on the signal in each group, and determining the corresponding signal group, may include: dividing adjacent Ns samples in the sample sequence Iin into one group, successively performing the sum-average operation on Ns samples in each group, and determining the signal group WI; and dividing adjacent Ns samples in the sample sequence Qin into one group, successively performing the sum-average operation on Ns samples in each group, and determining the signal group WQ.
Preferably, grouping the signal in the determined signal group WI and signal group WQ, may include: in the signal group WI, beginning from a first signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group; beginning from a second signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as WI1, WI2, . . . WINs; and in the signal group WQ, beginning from a first signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group; beginning from a second signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as WQ1, WQ2, . . . WQNs.
Preferably, the determining the signal belonging to the same chip in the sample sequence which experiences the sum-average operation, and outputting the determined signal, may include: sending WI1, WI2, . . . WINs into a matched filter meeting a pre-set condition, obtaining a corresponding output result, and marking the output results separately as yI1, yI2, . . . yIns; sending WQ1, WQ2, . . . WQNs into the matched filter, obtaining a corresponding output result, and marking the output results separately as yQ1, yQ2, . . . yQNs; determining signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs; and determining the signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal.
Preferably, the determining signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs, and determining the signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal, may include: determining the signal amplitude values y1, y2, . . . yNs according to a following formula:
y1=√{square root over (YI12+YQ12)}, y2=√{square root over (YI22+YQ22)}, . . . yNs=√{square root over (YINs2+YQNs2)}; and taking a signal corresponding to a maximum signal amplitude value as the signal belonging to the same chip, and outputting the signal corresponding to the maximum signal amplitude value.
In another aspect, an embodiment of the disclosure further provides a device for reducing a bit error rate in a CDMA communication system, which includes: an obtaining unit, configured to obtain a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q, which are sent by a signal sending end; a sum-average unit, configured to divide the obtained sample sequence Iin and the sample sequence Qin into different groups according to a sample number Ns of a chip, perform a sum-average operation on a signal in each group, and determine a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and a grouping unit, configured to group a signal in the signal group WI and the signal group WQ, to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, and output the determined signal.
Preferably, the sum-average unit may include: a first grouping sub-unit, configured to divide adjacent Ns samples in the sample sequence Iin into one group, successively perform the sum-average operation on Ns samples in each group, and determine the signal group WI; and a second grouping sub-unit, configured to divide adjacent Ns samples in the sample sequence Qin into one group, successively perform the sum-average operation on Ns samples in each group, and determine the signal group WQ.
Preferably, the grouping unit may include:
a third grouping sub-unit, configured to, in the signal group WI, begin from a first signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group; begin from a second signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as WI1, WI2, . . . WINs; and a third grouping sub-unit, configured to, in the signal group WQ, begin from a first signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group; begin from a second signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as WQ1, WQ2, . . . WQNs.
Preferably, the grouping unit may further include: a first output sub-unit, configured to send WI1, WI2 . . . WINs into a matched filter meeting a pre-set condition, obtain a corresponding output result, and mark the output results separately as yI1, yI2, . . . yIns; a second output sub-unit, configured to send WQ1, WQ2, . . . WQNs into the matched filter, obtain a corresponding output result, and mark the output results separately as yQ1, yQ2, . . . yQNs; an amplitude value output sub-unit, configured to determine signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs; and a signal output sub-unit, configured to determine the signal belonging to the same chip, according to the determined signal amplitude value, and output the determined signal.
Preferably, the amplitude value output sub-unit may include: an amplitude value calculating module, configured to determine the signal amplitude values y1, y2, . . . yNs according to a following formula: y1=√{square root over (YI12+YQ12)}, y2=√{square root over (YI22+YQ22)}, . . . yNs=√{square root over (YINs2+YQNs2)}; and the signal output sub-unit may include: a signal output module, configured to take a signal corresponding to a maximum signal amplitude value as the signal belonging to the same chip, and output the signal corresponding to the maximum signal amplitude value.
An advantage of the disclosure is in the following:
In the embodiment of the disclosure, after performing the sum-average operation on a signal sample sequence, the signal is grouped; in the grouped signal, the sample sequence experiencing the sum-average operation from the same chip is selected, and the signal of the sample sequence from the same chip is output; this signal processing way solves the problem in the related art that a CDMA synchronization method possesses a wrong sampling situation, which results in a high bit error rate of a receiving end, and effectively reduces the bit error rate.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a sampling way in a CDMA communication system;
FIG. 2 is a diagram of a wrong sampling situation occurred in a CDMA communication system;
FIG. 3 is a preferred flowchart of a method for reducing a bit error rate in a CDMA communication system in an embodiment of the disclosure;
FIG. 4 is a diagram of a sample sequence in a method for reducing a bit error rate in a CDMA communication system in an embodiment of the disclosure;
FIG. 5 is a preferred structure diagram of a device for reducing a bit error rate in a CDMA communication system in an embodiment of the disclosure;
FIG. 6 is another preferred structure diagram of the device for reducing the bit error rate in the CDMA communication system in an embodiment of the disclosure;
FIG. 7 is another preferred structure diagram of the device for reducing the core error rate in the CDMA communication system in an embodiment of the disclosure;
FIG. 8 is a hardware logic diagram of the method for reducing the core error rate in the CDMA communication system in an embodiment of the disclosure;
FIG. 9 is a flowchart of grouping through software in the method for reducing the bit error rate in the CDMA communication system in an embodiment of the disclosure; and
FIG. 10 is a logic diagram of determining a maximum amplitude value in the method for reducing the core error rate in the CDMA communication system in an embodiment of the disclosure.



DETAILED DESCRIPTION
In order to solve a problem in the related art that a CDMA synchronization algorithm possesses a wrong sampling situation, which results in a high bit error rate of a receiving end, an embodiment of the disclosure provides a method and a device for reducing a bit error rate in a CDMA communication system, and the disclosure will be explained in detail below with reference to the drawings and in combination with embodiments. It shall be explained that, the embodiment in the application and a feature in the embodiment may be combined with each other without conflict.
Embodiment 1
The preferred embodiment of the disclosure provides a method for reducing the core error rate in the CDMA communication system, and FIG. 3 shows a preferred flowchart of this method, as shown in FIG. 3, this method includes the following steps:
S302, obtaining a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q, which are sent by a signal sending end;
S304, dividing the obtained sample sequence Iin and the sample sequence Qin into different groups according to a sample number Ns of a chip, performing a sum-average operation on a signal in each group, and determining a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and
S306, grouping a signal in the signal group WI and the signal group WQ, to determine the signal belonging to the same chip in the sample sequence which experiences the sum-average operation, in the signal group WI and the signal group WQ, and outputting the determined signal.
In the above preferred embodiment, after performing the sum-average operation on a signal sample sequence, the signal is grouped; in the grouped signal, the sample sequence experiencing the sum-average operation from the same chip is selected, and the signal of the sample sequence from the same chip is output; this signal processing way solves the problem in the related art that the CDMA synchronization algorithm possesses the wrong sampling situation, which results in the high bit error rate of the receiving end, and effectively reduces the bit error rate.
In a preferred embodiment of the disclosure, a scheme is further provided, which groups and performs sum-average on the sample sequence Iin and the sample sequence Qin, and specifically, this scheme includes the following steps: dividing adjacent Ns samples in the sample sequence Iin into one group, and successively performing the sum-average operation on Ns samples in each group, and determining the signal group WI; and dividing adjacent Ns samples in the sample sequence Qin into one group, and successively performing the sum-average operation on Ns samples in each group, and determining the signal group WQ. For example, it is assumed that a sample number of each chip is Ns=2, and the sample sequence Iin is shown in FIG. 4, which successively contains the following samples: X1 X2, X3, X4, X5, X6, X7, X8, then 2 adjacent sample signals in the sample sequence are obtained, and experience the sum-average operation, to obtain the signal group WI, which successively includes




  
    
      
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Grouping the sample sequence Qin is the same as grouping the sample sequence Iin, and will not be repeated again.

In the above preferred technical scheme, grouping and sum-average are performed on all adjacent Ns samples in the sample sequence Iin and the sample sequence Qin, to guarantee that the signal experiencing the sum-average operation not only contains an ideal sampling situation, but also contains the wrong sampling situation, and to reduce the core error rate by selecting the signal in the ideal sampling situation.
In a preferred embodiment of the disclosure, a scheme is further provided, which groups the signal group WI and the signal group WQ, specifically, this scheme includes the following steps:
in the signal group WI, beginning from a first signal, extracting a signal after Ns−1 signals, successively grouping each extracted signal into one group; beginning from a second signal, extracting a signal after Ns−1 signals, successively grouping each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as WI1, WI2, . . . , WINs; and
in the signal group WQ, beginning from a first signal, extracting a signal after Ns−1 signals, successively grouping each extracted signal into one group; beginning from a second signal, extracting a signal after Ns−1 signals, successively grouping each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as WQ1, WQ2, . . . WQNs.
The example provided above is further explained, specifically, the above signal group WI is




  
    
      
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when performing grouping, beginning from the first signal, signal extraction is perform after 1 signal, therefore





  
    
      
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are extracted successively, and are taken as the first group,





  
    
      
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are taken as the second group; it can be seen from FIG. 4, the group of data





  
    
      
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do not come from the same chip, but come from adjacent chips, this is the wrong sampling situation; the group of data





  
    
      
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come from the same chip, this is the ideal sampling situation.

In a preferred embodiment of the disclosure, a scheme is further provided, which determines signal belonging to the same chip in the sample sequence experiencing the sum-average operation, and outputs the determined signal; the scheme includes the following steps: sending WI1, WI2, . . . WINs into a matched filter meeting a pre-set condition, obtaining a corresponding output result, and marking the output results separately as yI1, yI2, . . . yIns; sending WQ1, WQ2, . . . WQNs into the matched filter, obtaining the corresponding output result, and marking the output results separately as yQ1, yQ2, . . . yQNs; determining signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs; and determining a signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal.
Specifically, the signal amplitude values y1, y2, . . . yNs are determined according to the following formula: y1=√{square root over (YI12+YQ12)}, y2=√{square root over (YI22+YQ22)}, . . . yNs=√{square root over (YINs2+YQNs2)}; the corresponding signal when the signal amplitude value is maximum is taken as the signal belonging to the same chip, and the corresponding signal when the signal amplitude value is maximum is output.
Embodiment 2
Based on the above method for reducing the bit error rate in the CDMA communication system provided by Embodiment 1, this preferred embodiment provides a device for reducing the bit error rate in the CDMA communication system; FIG. 5 is a preferred structure diagram of this device, as shown in FIG. 5, this device includes: an obtaining unit 502, configured to obtain a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q, which are sent by a signal sending end; a sum-average unit 504, configured to divide the obtained sample sequence Iin and the sample sequence Qin into different groups according to a sample number Ns of a chip, perform a sum-average operation on a signal in each group, and determine a corresponding signal group, wherein each signal group contains the signal experiencing the sum average operation, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and a grouping unit 506, configured to group the signal in the signal group WI and the signal group WQ, to determine the signal belonging to the same chip in the sample sequence experiencing the sum-average operation, in the signal group WI and the signal group WQ, and output the determined signal.
In the above preferred embodiment, after performing the sum-average operation on the signal sample sequence, the signal is grouped, in the grouped signal, the sample sequence experiencing the sum-average operation from the same chip is selected, and the signal of the sample sequence from the same chip is output; this kind of signal processing way solves the problem in the related art that the CDMA synchronization algorithm possesses the wrong sampling situation, which results in the high bit error rate of the receiving end, and effectively reduces the core error rate.
In a preferred embodiment of the disclosure, the above device is further optimized, specifically, a scheme is provided which performs grouping and sum-average on the sample sequence Iin and the sample sequence Qin, as shown in FIG. 6, the sum-average unit 504 includes: a first grouping sub-unit 602, configured to divide adjacent Ns samples in the sample sequence Iin into one group, and successively perform the sum-average operation on Ns samples in each group, and determine the signal group WI; and a second grouping sub-unit 604, configured to divide adjacent Ns samples in the sample sequence Qin into one group, and successively perform the sum-average operation on Ns samples in each group, and determine the signal group WQ. For example, it is assumed that the sample number of each chip is Ns=2, and the sample sequence Iin is shown in FIG. 4, which contains the following samples: X1, X2, X3, X4, X5, X6, X7, X8, then adjacent 2 sample signals in the sample sequence are obtained and experience the sum-average operation, to obtain the signal group WI, which successively includes




  
    
      
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Grouping the sample sequence Qin is the same as grouping the sample sequence Iin, and will not be repeated again.

In the above preferred technical scheme, grouping and sum-average are performed on all adjacent Ns samples in the sample sequence Iin and the sample sequence Qin, to guarantee that the signal experiencing the sum-average operation not only contains an ideal sampling situation, but also contains the wrong sampling situation, and to reduce the core error rate by selecting the signal in the ideal sampling situation.
In a preferred embodiment of the disclosure, the above device is further optimized, specifically, a scheme is provided which groups the signal group WI and the signal group WQ, as shown in FIG. 7, the grouping unit 506 includes:
a third grouping sub-unit 702, configured to, in the signal group WI, begin from a first signal, extract a signal after Ns−1 signals, successively group each extracted signal into one group; begin from a second signal, extract a signal after Ns−1 signals, successively group each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as WI1, WI2, . . . , WINs; and
a forth grouping sub-unit 704, configured to, in the signal group WQ, begin from a first signal, extract a signal after Ns−1 signals, successively group each extracted signal into one group; begin from a second signal, extract a signal after Ns−1 signals, successively group each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as WQ1, WQ2, . . . WQNs.
The example provided above is further explained, specifically, the above signal group WI is




  
    
      
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when performing grouping, beginning from the first signal, signal extraction is perform after 1 signal, therefore





  
    
      
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are extracted successively, and are taken as the first group,





  
    
      
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are taken as the second group; it can be seen from the drawing, the group of data





  
    
      
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do not come from the same chip, but come from adjacent chips, this is the wrong sampling situation; the group of data





  
    
      
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come from the same chip, this is the ideal sampling situation.

Preferably, as shown in FIG. 7, the grouping unit 506 further includes: a first output sub-unit 706, configured to send the WI1, WI2, . . . WINs into a matched filter meeting a pre-set condition, obtain a corresponding output result, and mark the output results separately as yI1, yI2, . . . yIns; a second output sub-unit 708, configured to send the WQ1, WQ2, . . . WQNs into the matched filter, obtain the corresponding output result, and mark the output results separately as yQ1, yQ2, . . . yQNs; an amplitude value output sub-unit 710, configured to determine signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs, and a signal output sub-unit 712, configured to determine the signal belonging to the same chip, according to the determined signal amplitude value, and output the determined signal.
Specifically, the amplitude value output sub-unit 710 includes: an amplitude value calculating module, configured to determine the signal amplitudes y1, y2, . . . yNs according to the following formula:

y1=√{square root over (YI12+YQ12)},y2=√{square root over (YI22+YQ22)}, . . . yNs=√{square root over (YINs2+YQNs2)};

the signal output sub-unit 712 includes: a signal output module, configured to take the corresponding signal when the signal amplitude value is maximum as the signal belonging to the same chip, and output the corresponding signal when the signal amplitude value is maximum.
Embodiment 3
Based on the method for reducing the bit error rate in the CDMA communication system provided by Embodiment 1 and the device for reducing the bit error rate in the CDMA communication system provided by Embodiment 2, this preferred embodiment provides another method for reducing the bit error rate in the CDMA communication system; FIG. 8 shows a hardware implementation logic diagram of this method, in FIG. 8, Tc is a chip delay time (chip period), and Ns is a sample number of the chip. In implementation of this method, mainly several groups of delayers and the matched filter group MF are separately added behind two channels of input signals Iin and Qin, behind the filter, accurate synchronization of data is implemented through a maximum amplitude value selector, to eliminate a serious inter-code interference caused by wrong sampling, and to reduce a high bit error rate brought by an inter-code interference of a traditional method.
Specifically, the above method includes the following steps:
1. performing sum-average on the sample sequence;
as shown in FIG. 8, the input signals Iin and Qin are a group of sample sequence, a sampling frequency is Ns times/one chip (one chip samples Ns times). Every adjacent Ns sample values are added and divided by Ns, to obtain WI and WQ, a purpose of this step is to store the results after performing sum-average in all sampling ways (ideal sampling, wrong sampling) into two channels of signals WI and WQ. Preferably, in order to make calculation convenient and reduce a hardware resource cost, Ns is set as powers of 2.
2. grouping two channels of signals WI and WQ;
the purpose of grouping two channels of signals WI and WQ is to find a most ideal sample, and eliminate an inter-chip interference caused by wrong sampling, specifically, as shown in FIG. 8, in two channels of signals WI and WQ, elements separated by Ns−1 (Ns is a sampling number of the chip) elements are separately grouped into one group. Specifically, WI is a signal group obtained by performing Step 1 on I channels of signals, and includes multiple signals, which are marked as WI=(WI(0), WI(1), WI(2), . . . , WI(Ns), WI(Ns+1), WI(Ns+2), . . . , WI(2*Ns), WI(2*Ns+1), WI(2*Ns+2), . . . ), that is, WI is composed of WI(i). In the same way, WQ and WI have the same structure feature, and WQ is composed of WQ(i). WI is grouped into Ns groups with a distance of Ns−1 elements, wI1=(WI(0), WI(Ns), WI(2*Ns), WI(3*Ns), . . . ), wI2=(WI(1), WI(Ns+1), WI(2*Ns+1), WI(3*Ns+1), . . . ), wI3=(WI(2), WI(Ns+2), WI(2*Ns+2), WI(3*Ns+2), . . . ), . . . , wINs=(WI(Ns−1), WI(Ns+Ns−1), WI(2*Ns+Ns−1), WI(3*Ns+Ns−1), . . . ), and a grouping relationship of WQ is the same as that of WI, and will not be repeated again.
In FIG. 8 adopts a delayer to implement grouping. Tc represents a chip delay time (a chip transmission rate is 1/Tc), MF in the drawing is the matched filter, and a work clock frequency is 1/Tc. A simple delayer is added between the traditional matched filter and a Front End Processor (FEP) output, and the signals are divided into Ns groups through driving of a sample clock (a sample clock frequency is Ns/Tc). Through improvement of this method, all grouped WIi and WQi are sent to a matched filter group, in which one group of data must come from the same chip, the amplitude value matched and output in this way will be larger than that obtained in a traditional method, and an interference resistance ability of a system is improved.
In addition, a grouping way may also be implemented through software programming, a specific algorithm flowchart is shown in FIG. 9, during grouping, first a variable flag (called a variable f for short) is defined, of which an initial value is 0, and then WI and WQ output by the sum-average unit are read through driving of each sample clock, simultaneously a modulo of the sample number Ns is calculated with the variable flag, namely flag=flag % Ns; assigning the sample value of the current WI and WQ to corresponding groups WIj and WQj, is decided according to a value of the variable flag (0, 1, . . . Ns−2, Ns−1), and simultaneously flag is added by 1, and a next signal in WI and WQ is obtained continuously to perform grouping, until grouping is completed, and finally WI and WQ are separately divided into Ns groups of signals.
3. calculating the maximum amplitude value;
the grouped signals WIj and WQj are separately sent into the matched filter MF, as shown in FIG. 10. Matched outputs yIj and yQj are obtained. yIj and yQj are sent to an amplitude generator MAG, the amplitude generator MAG calculates a root of a quadratic sum of yIj and yQj to obtain the amplitude value yj. In step 2, WI and WQ are divided into Ns groups, then there are totally Ns amplitude values output here. All output amplitude values are sent to the maximum amplitude selector MAX, and the maximum amplitude selector MAX selects a maximum value from y1 to yNs as the current output y. Simultaneously yIj and yQj constructing this maximum amplitude value are separately assigned to Isum shown in FIG. 8 and Qsum shown in FIG. 8.
4. judgment and demodulation;
when the output y is larger than a threshold, the sign shown in FIG. 8 changes from a high electrical level to a low electrical level, otherwise the sign is the low electrical level. When the sign changes from the low electrical level to the high electrical level, a demodulator reads Isum and Qsum to perform a code demodulation operation.
Through the above several steps, a group of sample values may be found which are all weighted signal values in the same chip; a serious inter-chip interference existed in a traditional rough synchronization algorithm is eliminated, and the bit error rate is reduced to a big extent. Accurate CDMA synchronization is implemented.
Although for the purpose of making an example, the preferred embodiment of the disclosure is disclosed, those skilled in the art will be conscious of a possibility of improvement, increase, and substitution. Therefore, the scope of the disclosure shall not be limited to the above embodiment.

## Claims

1. A method for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system, comprising:
obtaining, by a Front End Processor (FEP), a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q, which are sent by a signal sending end;
dividing the obtained sample sequence Iin and the sample sequence Qin by adopting a first delayer into different groups according to a sample number Ns of a chip, performing a sum-average operation on a signal in each group, and determining a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and
grouping, by adopting a second delayer, a signal in the signal group WI and the signal group WQ, to determine, through a matched filter, a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, in the signal group WI and the signal group WQ, and outputting the determined signal;
wherein the first delayer is added in the FEP, and second delayer is added between a FEP output and the matched filter;
wherein the dividing the obtained sample sequence Iin and the sample sequence Qin by adopting a first delayer into different groups according to the sample number Ns of the chip, performing the sum-average operation on the signal in each group, and determining the corresponding signal group comprises:
dividing adjacent Ns samples in the sample sequence Iin into one group, successively performing the sum-average operation on Ns samples in each group, and determining the signal group WI; and
dividing adjacent Ns samples in the sample sequence Qin into one group, successively performing the sum-average operation on Ns samples in each group, and determining the signal group WQ;
wherein the grouping the signal in the signal group WI and the signal group WQ comprises:
in the signal group WI, beginning from a first signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group; beginning from a second signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as WI1, WI2, . . . WINs; and
in the signal group WQ, beginning from a first signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group; beginning from a second signal, extracting a signal after Ns−1 signals, successively combining each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as WQ1, WQ2, . . . WQNs.

2. The method according to claim 1, wherein the determining, through the matched filter, the signal belonging to the same chip in the sample sequence which experiences the sum-average operation and outputting the determined signal comprises:
sending the WI1, WI2, . . . WINs into the matched filter meeting a pre-set condition, obtaining a corresponding output result, and marking the output results separately as yI1, yI2, . . . yIns;
sending the WQ1, WQ2, . . . WQNs into the matched filter, obtaining a corresponding output result, and marking the output results separately as yQ1, yQ2, . . . yQNs;
determining signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs; and
determining the signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal.

3. The method according to claim 2, wherein the determining signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs, determining the signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal comprises:
determining the signal amplitude values y1, y2, . . . yNs according to a following formula: y1=√{square root over (YI12+YQ12)}, y2=√{square root over (YI22+YQ22)}, . . . yNs=√{square root over (YINs2+YQNs2)}; and
taking a signal corresponding to a maximum signal amplitude value as the signal belonging to the same chip, and outputting the signal corresponding to the maximum signal amplitude value.

4. A device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system, comprising:
a memory storing programming instructions; and
a processor configured to be capable of executing the stored programming instructions to:
obtain a sample sequence Iin of an in-phase component signal I, and a sample sequence Qin of a quadrature component signal Q, which are sent by a signal sending end;
divide the obtained sample sequence Iin and the sample sequence Qin into different groups according to a sample number Ns of a chip, perform a sum-average operation on a signal in each group, and determine a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence Iin is WI, the signal group determined by performing the sum-average operation on the sample sequence Qin is WQ; and
group a signal in the signal group WI and the signal group WQ, to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, in the signal group WI and the signal group WQ, and output the determined signal;
wherein the processor is further configured to be capable of executing the stored programming instructions to:
divide adjacent Ns samples in the sample sequence Iin into one group, successively perform the sum-average operation on Ns samples in each group, and determine the signal group WI; and
divide adjacent Ns samples in the sample sequence Qin into one group, successively perform the sum-average operation on Ns samples in each group, and determine the signal group WQ;
wherein the processor is further configured to be capable of executing the stored programming instructions to:
in the signal group WI, begin from a first signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group; begin from a second signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as WI1, WI2, . . . WINs; and
in the signal group WQ, begin from a first signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group; begin from a second signal, extract a signal after Ns−1 signals, successively combine each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as WQ1, WQ2, . . . WQNs.

5. The device according to claim 4, wherein the processor is further configured to be capable of executing the stored programming instructions to:
sending the WI1, WI2, . . . WINs into the matched filter meeting a pre-set condition, obtain a corresponding output result, and mark the output results separately as yI1, yI2, . . . yINs;
sending the WQ1, WQ2, . . . WQNs into the matched filter, obtain a corresponding output result, and mark the output results separately as yQ1, yQ2, . . . yQNs;
determine signal amplitude values y1, y2, . . . yNs grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results yI1, yI2, . . . yIns and the output results yQ1, yQ2, . . . yQNs, and
determine the signal belonging to the same chip, according to the determined signal amplitude value, and output the determined signal.

6. The device according to claim 5, wherein
the processor is further configured to be capable of executing the stored programming instructions to:
determining the signal amplitude values y1, y2, . . . yNs according to a following formula: y1=√{square root over (YI12+YQ12)}, y2=√{square root over (YI22+YQ22)}, . . . yNs=√{square root over (YINs2+YQNs2)}; and
take a signal corresponding to a maximum signal amplitude value as the signal belonging to the same chip, and output the signal corresponding to the maximum signal amplitude value.