# Patent

## Title
Semiconductor device and method for manufacturing the same

## Abstract

A metal element of a metal film is introduced into the oxide semiconductor film by performing heat treatment in the state where the oxide semiconductor film is in contact with the metal film, so that a low-resistance region having resistance lower than that of a channel formation region is formed. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. After that, an unnecessary metal film is removed. Thus, the metal oxide insulating film can be formed over the low-resistance region.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
In this specification, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electrooptic device, a semiconductor circuit, and an electronic appliance are all semiconductor devices.
2. Description of the Related Art
Attention has been focused on a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface (also referred to as a thin film transistor (TFT)). The transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) or an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another material, an oxide semiconductor has been attracting attention.
Better electric characteristics of a transistor including an oxide semiconductor are required for application to semiconductor devices with higher performance. For example, a transistor having a self-aligned structure, in which a gate electrode and a gate insulating film are formed over a region of an oxide semiconductor film serving as a channel formation region of the transistor, and a source region and a drain region are formed in such a manner that the resistance of a region of the oxide semiconductor film, which is covered with neither the gate electrode nor the gate insulating film, is reduced, is reported (for example, see Patent Document 1). Further, a transistor having a structure in which an oxide semiconductor including aluminum, titanium, or the like as dopant in the depth direction from a top surface is used for a source region and a drain region is reported (for example, see Patent Document 2).
REFERENCE
Patent Document


    [Patent Document 1] Japanese Published Patent Application No. 2007-220817
    [Patent Document 2] Japanese Published Patent Application No. 2011-228622


SUMMARY OF THE INVENTION
In Patent Document 1, in order to form the low-resistance source region and drain region in a self-aligned manner, a silicon nitride film is formed as an interlayer insulating film by a plasma CVD method over the region of the oxide semiconductor film, which is covered with neither the gate electrode nor the gate insulating film, and hydrogen included in the silicon nitride film is introduced into the oxide semiconductor film; thus, the low-resistance regions are formed. However, in this method, hydrogen might diffuse to the channel formation region and it is difficult to obtain stable semiconductor characteristics.
Further, in Patent Document 2, in order to form the low-resistance source region and drain region in a self-aligned manner, a metal film (e.g., aluminum or titanium) is formed over a region of the oxide semiconductor film, which is covered with neither a gate electrode nor a gate insulating film, and heat treatment is performed in an oxidizing gas atmosphere so that the metal film and the oxide semiconductor film react with each other; thus, the low-resistance regions are formed. However, in this method, the metal film is oxidized by being subjected to heat treatment in the oxidizing gas atmosphere after formation of the metal film. If the metal film is not completely oxidized and even part of the metal film remains in the state of not being oxidized, unnecessary capacitance is formed between the metal film and a gate electrode or the like, or the source region and the drain region are electrically connected to each other through the metal film, which might adversely influence electric characteristics of the transistor.
In view of the above problems, an object of an embodiment of the present invention is to provide a self-aligned transistor including an oxide semiconductor film, which has excellent and stable electric characteristics. Further, an object is to provide a method for manufacturing the transistor. Furthermore, an object is to provide a high-performance semiconductor device including the transistor.
In the self-aligned transistor including the oxide semiconductor film, heat treatment is performed in an inert gas atmosphere in the state where the oxide semiconductor film and a metal film are in contact with each other, whereby an element included in the metal film is introduced into the oxide semiconductor film to form a low-resistance region having resistance lower than that of a channel formation region. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. Then, an unnecessary region of the metal film is removed. By the removal of the unnecessary region of the metal film, unnecessary capacitance due to the metal film is not formed. Thus, the metal oxide insulating film can be formed over the low-resistance region and the metal oxide insulating film can prevent diffusion of an impurity entering the oxide semiconductor film from the outside or release of oxygen from the oxide semiconductor film. Details thereof will be described below.
An embodiment of the present invention is a semiconductor device including an oxide film, an oxide semiconductor film which is formed over the oxide film and includes a channel formation region and a low-resistance region having resistance lower than that of the channel formation region, a metal oxide insulating film formed in contact with the low-resistance region, a gate insulating film formed over the oxide semiconductor film, and a gate electrode which is formed in contact with the gate insulating film and overlaps with the channel formation region. The low-resistance region includes at least a metal element included in the metal oxide insulating film.
Another embodiment of the present invention is a semiconductor device including an oxide film, an oxide semiconductor film which is formed over the oxide film and includes a channel formation region and low-resistance regions having resistance lower than that of the channel formation region, metal oxide insulating films formed in contact with the low-resistance regions, a gate insulating film formed over the oxide semiconductor film, a gate electrode which is formed in contact with the gate insulating film and overlaps with the channel formation region, a sidewall insulating film which is formed over the gate insulating film and formed on a side surface of the gate electrode in a cross section taken along the channel length direction, a protective insulating film formed over the metal oxide insulating films, the sidewall insulating film, and the gate electrode, and a source electrode and a drain electrode electrically connected to the low-resistance regions. The low-resistance regions include at least a metal element included in the metal oxide insulating films.
In the above structure, an impurity region having resistance different from that of the low-resistance regions may be formed between the channel formation region and each of the low-resistance regions.
Another embodiment of the present invention is a semiconductor device including an oxide film, an oxide semiconductor film which is formed over the oxide film and includes a channel formation region and low-resistance regions having resistance lower than that of the channel formation region, metal oxide insulating films formed in contact with the low-resistance regions, a gate insulating film formed over the oxide semiconductor film, a gate electrode which is formed in contact with the gate insulating film and overlaps with the channel formation region, a sidewall insulating film which is formed over the metal oxide insulating films and formed on a side surface of the gate electrode in a cross section taken along the channel length direction, a protective insulating film formed over the metal oxide insulating films, the sidewall insulating film, and the gate electrode, and a source electrode and a drain electrode electrically connected to the low-resistance regions. The low-resistance regions include at least a metal element included in the metal oxide insulating films.
Another embodiment of the present invention is a semiconductor device including an oxide film, a source electrode and a drain electrode formed over the oxide film, an oxide semiconductor film which is formed over the oxide film, the source electrode, and the drain electrode and includes a channel formation region and low-resistance regions having resistance lower than that of the channel formation region, metal oxide insulating films formed in contact with the low-resistance regions, a gate insulating film formed over the oxide semiconductor film, a gate electrode which is formed in contact with the gate insulating film and overlaps with the channel formation region, a sidewall insulating film which is formed over the gate insulating film and formed on a side surface of the gate electrode in a cross section taken along the channel length direction, and a protective insulating film formed over the metal oxide insulating films, the sidewall insulating film, and the gate electrode. The low-resistance regions include at least a metal element included in the metal oxide insulating films.
In the above structure, an impurity region having resistance different from that of the low-resistance regions may be formed between the channel formation region and each of the low-resistance regions.
Another embodiment of the present invention is a semiconductor device including an oxide film, a source electrode and a drain electrode formed over the oxide film, an oxide semiconductor film which is formed over the oxide film, the source electrode, and the drain electrode and includes a channel formation region and low-resistance regions having resistance lower than that of the channel formation region, metal oxide insulating films formed in contact with the low-resistance regions, a gate insulating film formed over the oxide semiconductor film, a gate electrode which is formed in contact with the gate insulating film and overlaps with the channel formation region, a sidewall insulating film which is formed over the metal oxide insulating films and formed on a side surface of the gate electrode in a cross section taken along the channel length direction, and a protective insulating film formed over the metal oxide insulating films, the sidewall insulating film, and the gate electrode. The low-resistance regions include at least a metal element included in the metal oxide insulating films.
In any of the above structures, the metal oxide insulating films preferably include one or more elements selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc. Further, the low-resistance regions are preferably formed with the channel formation region interposed therebetween, and preferably include one or more elements selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, zinc, phosphorus, arsenic, antimony, boron, nitrogen, helium, neon, argon, fluorine, and chlorine.
Further, in any of the above structures, the oxide semiconductor film preferably includes an oxide comprising one or more elements selected from indium, zinc, gallium, tin, hafnium, zirconium, titanium, scandium, yttrium, cerium, neodymium, and gadolinium. In addition, it is preferable that the channel formation region include a crystal portion and the c-axis of the crystal portion be aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed.
In the oxide semiconductor film including the channel formation region, the low-resistance regions are provided with the channel formation region interposed therebetween in a cross section taken along the channel length direction, whereby an on-state characteristic (e.g., on-state current and field-effect mobility) which is one of electric characteristics of the transistor including the oxide semiconductor film can be increased.
Further, heat treatment is performed in an inert gas atmosphere in the state where an oxide semiconductor film is in contact with a metal film, whereby an element in the metal film is introduced into the oxide semiconductor film to form a low-resistance region having resistance lower than that of a channel formation region in a self-aligned manner. In addition, a region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. Then, an unnecessary region of the metal film is removed. Thus, the metal oxide insulating film can be formed over the low-resistance region. Further, the metal oxide insulating film can effectively prevent diffusion of an impurity entering the oxide semiconductor film from the outside or release of oxygen from the oxide semiconductor film. Furthermore, by the removal of the unnecessary region of the metal film, unnecessary capacitance due to the metal film is not formed.
Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide film; forming an oxide semiconductor film including a channel formation region over the oxide film; forming a stack of a gate insulating film and a gate electrode over the oxide semiconductor film; selectively introducing dopant into the oxide semiconductor film through the gate insulating film with the use of the gate electrode as a mask; forming a sidewall insulating film on a side surface of the gate electrode in a cross section taken along the channel length direction; removing part of the gate insulating film with the use of the gate electrode and the sidewall insulating film as masks to expose a surface of the oxide semiconductor film; forming a metal film in contact with part of the oxide semiconductor film; forming low-resistance regions including a metal element by heat treatment performed in the state where the oxide semiconductor film is in contact with the metal film to introduce the metal element into the oxide semiconductor film from the metal film; forming metal oxide insulating films by selectively oxidizing the metal film which is in contact with the oxide film and the oxide semiconductor film by the heat treatment; and removing the metal film.
Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide film; forming an oxide semiconductor film including a channel formation region over the oxide film; forming a stack of a gate insulating film and a gate electrode over the oxide semiconductor film; removing part of the gate insulating film with the use of the gate electrode as a mask to expose a surface of the oxide semiconductor film; forming a metal film in contact with part of the oxide semiconductor film; forming low-resistance regions including a metal element by heat treatment performed in the state where the oxide semiconductor film is in contact with the metal film to introduce the metal element into the oxide semiconductor film from the metal film; forming metal oxide insulating films by selectively oxidizing the metal film which is in contact with the oxide film and the oxide semiconductor film by the heat treatment; removing the metal film; forming a sidewall insulating film on a side surface of the gate electrode in a cross section taken along the channel length direction; and selectively introducing dopant into the oxide semiconductor film through the metal oxide insulating films with the use of the gate electrode and the sidewall insulating film as masks.
Each of the above embodiments may further include the steps of forming a protective insulating film and an interlayer insulating film for covering the metal oxide insulating films, the sidewall insulating film, and the gate electrode; forming opening portions reaching the low-resistance regions in the interlayer insulating film; and forming a source electrode and a drain electrode in the opening portions.
Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide film; forming a source electrode and a drain electrode over the oxide film; forming an oxide semiconductor film including a channel formation region over the source electrode and the drain electrode; forming a stack of a gate insulating film and a gate electrode over the oxide semiconductor film; selectively introducing dopant into the oxide semiconductor film through the gate insulating film with the use of the gate electrode as a mask; forming a sidewall insulating film on a side surface of the gate electrode in a cross section taken along the channel length direction; removing part of the gate insulating film with the use of the gate electrode and the sidewall insulating film as masks to expose a surface of the oxide semiconductor film; forming a metal film in contact with part of the oxide semiconductor film; forming low-resistance regions including a metal element by heat treatment performed in the state where the oxide semiconductor film is in contact with the metal film to introduce the metal element into the oxide semiconductor film from the metal film; forming metal oxide insulating films by selectively oxidizing the metal film which is in contact with the oxide semiconductor film by the heat treatment; and removing the metal film.
Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming an oxide film; forming a source electrode and a drain electrode over the oxide film; forming an oxide semiconductor film including a channel formation region over the source electrode and the drain electrode; forming a stack of a gate insulating film and a gate electrode over the oxide semiconductor film; removing part of the gate insulating film with the use of the gate electrode as a mask to expose a surface of the oxide semiconductor film; forming a metal film in contact with part of the oxide semiconductor film; forming low-resistance regions including a metal element by heat treatment performed in the state where the oxide semiconductor film is in contact with the metal film to introduce the metal element into the oxide semiconductor film from the metal film; forming metal oxide insulating films by selectively oxidizing the metal film which is in contact with the oxide semiconductor film by the heat treatment; removing the metal film; forming a sidewall insulating film on a side surface of the gate electrode in a cross section taken along the channel length direction; and selectively introducing dopant into the oxide semiconductor film through the metal oxide insulating films with the use of the gate electrode and the sidewall insulating film as masks.
Each of the above embodiments may further include the step of forming a protective insulating film and an interlayer insulating film for covering the metal oxide insulating films, the sidewall insulating film, and the gate electrode.
Further, in any of the above embodiments, the heat treatment is preferably performed in an inert gas atmosphere. Furthermore, one or more of nitrogen, helium, neon, and argon are preferably used as the inert gas atmosphere. Thus, the heat treatment can be performed in an atmosphere in which a surface of the metal film is not oxidized, and the metal film can be favorably removed in a later step.
Further, in any of the above embodiments, the metal film preferably includes one or more elements selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc. As the dopant, one or more elements selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, zinc, phosphorus, arsenic, antimony, boron, nitrogen, helium, neon, argon, fluorine, and chlorine are preferably used.
A self-aligned transistor including an oxide semiconductor film, which has excellent and stable electric characteristics can be provided. Further, a method for manufacturing the transistor can be provided. Furthermore, a high-performance semiconductor device including the transistor can be provided.



BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating an embodiment of a semiconductor device;
FIGS. 2A to 2E are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 3A to 3E are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 4A to 4D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 5A and 5B are a plan view and a cross-sectional view illustrating an embodiment of a semiconductor device;
FIGS. 6A to 6E are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 7A to 7E are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 8A to 8D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 9A and 9B are a plan view and a cross-sectional view illustrating an embodiment of a semiconductor device;
FIGS. 10A to 10D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 11A to 11D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 12A to 12C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 13A and 13B are a plan view and a cross-sectional view illustrating an embodiment of a semiconductor device;
FIGS. 14A to 14D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 15A to 15D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 16A to 16C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device;
FIGS. 17A and 17B are a plan view and a cross-sectional view illustrating an embodiment of a semiconductor device;
FIGS. 18A and 18B are a plan view and a cross-sectional view illustrating an embodiment of a semiconductor device;
FIGS. 19A to 19C are a cross-sectional view, a plan view, and a circuit diagram illustrating an embodiment of a semiconductor device;
FIGS. 20A and 20B are a circuit diagram and a perspective view illustrating an embodiment of a semiconductor device;
FIGS. 21A and 21B are a cross-sectional view and a plan view illustrating an embodiment of a semiconductor device;
FIGS. 22A and 22B are each a circuit diagram illustrating an embodiment of a semiconductor device;
FIG. 23 is a block diagram illustrating an embodiment of a semiconductor device;
FIG. 24 is a block diagram illustrating an embodiment of a semiconductor device; and
FIG. 25 is a block diagram illustrating an embodiment of a semiconductor device.



DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the invention disclosed in this specification will be described with reference to the accompanying drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the invention should not be construed as being limited to the description in the following embodiments.
Note that the position, size, range, or the like of each structure illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like as disclosed in the drawings and the like.
In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.
Note that in this specification and the like, the term such as “over” or “below” does not necessarily mean that a component is placed “directly on” or “directly under” another component. For example, the expression “a gate electrode over a gate insulating film” can mean the case where there is an additional component between the gate insulating film and the gate electrode.
In addition, in this specification and the like, the term such as “electrode” or “wiring” does not limit a function of a component. For example, an “electrode” is sometimes used as part of a “wiring”, and vice versa. Furthermore, the term “electrode” or “wiring” can include the case where a plurality of “electrodes” or “wirings” is formed in an integrated manner.
Functions of a “source” and a “drain” are sometimes replaced with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be replaced with each other in this specification and the like.
Note that in this specification and the like, the term “electrically connected” includes the case where components are connected through an object having any electric function. There is no particular limitation on an object having any electric function as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an object having any electric function are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring.
Embodiment 1
In this embodiment, an embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1A and 1B, FIGS. 2A to 2E, FIGS. 3A to 3E, and FIGS. 4A to 4D.
<Structure Example 1 of Semiconductor Device>
FIGS. 1A and 1B are a plan view and a cross-sectional view of a top-gate self-aligned transistor as an example of a semiconductor device. FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line X1-Y1 in FIG. 1A. Note that in FIG. 1A, some components of the transistor (e.g., a gate insulating film 108) are not illustrated for simplification.
The semiconductor device illustrated in FIGS. 1A and 1B includes a substrate 102, an oxide film 104 formed over the substrate 102, an oxide semiconductor film 106 which is formed over the oxide film 104 and includes a channel formation region 106a and low-resistance regions 106c having resistance lower than that of the channel formation region 106a, metal oxide insulating films 114 formed in contact with the low-resistance regions 106c, a gate insulating film 108 formed over the oxide semiconductor film 106, a gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, and sidewall insulating films 112 formed on side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. The low-resistance regions 106c include at least a metal element included in the metal oxide insulating films 114.
In addition, a protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the gate electrode 110, an interlayer insulating film 118 formed over the protective insulating film 116, and a source electrode 120a and a drain electrode 120b electrically connected to the low-resistance regions 106c may be included.
Note that as illustrated in FIG. 1B, the gate insulating film 108 preferably has a stacked structure of a first gate insulating film 108a and a second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
The oxide semiconductor film 106 includes impurity regions 106b having resistance different from that of the low-resistance regions 106c between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c and the impurity regions 106b can be formed in a self-aligned manner. Specifically, after the oxide semiconductor film 106 including the channel formation region 106a is formed, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106. Then, dopant is selectively introduced into the oxide semiconductor film 106 through the gate insulating film 108 with the use of the gate electrode 110 as a mask, so that the impurity regions 106b are formed. After that, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. Then, part of the gate insulating film 108 is removed with the use of the gate electrode 110 and the sidewall insulating films 112 as masks; thus, a surface of the oxide semiconductor film 106 is exposed. After that, a metal film is formed in contact with part of the oxide semiconductor film and heat treatment is performed in the state where the oxide semiconductor film 106 is in contact with the metal film so that a metal element is introduced into the oxide semiconductor film 106 from the metal film; thus, the low-resistance regions 106c including the metal element can be formed. Further, the metal film which is in contact with the oxide film 104 and the oxide semiconductor film 106 is selectively oxidized by the heat treatment, whereby the metal oxide insulating films 114 are formed. The metal film is removed.
With such a structure, the low-resistance regions 106c and the impurity regions 106b are formed in the oxide semiconductor film 106 in a self-aligned manner, and the metal oxide insulating films 114 are formed over the low-resistance regions 106c. The metal oxide insulating films 114 can effectively prevent entry of an impurity to the oxide semiconductor film 106 or release of oxygen included in the oxide film 104 and the oxide semiconductor film 106. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed.
Further, in the oxide semiconductor film 106, the impurity region 106b having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at high concentration. The impurity regions 106b are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at low concentration. With such a structure, a potential difference between the source and the drain which are associated with the channel formation region 106a can be reduced, and the semiconductor device can be highly reliable.
The following will show each component that can be included in the semiconductor device of the present invention in detail.
[Detailed Description of Substrate]
Although there is no particular limitation on a substrate that can be used as the substrate 102, it is necessary that the substrate have heat resistance to withstand at least heat treatment performed later. For example, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon, silicon carbide, or the like; a compound semiconductor substrate of silicon germanium or the like; an SOI substrate; or the like can be used.
[Detailed Description of Oxide Film]
The oxide film 104 has the effect of preventing diffusion of an impurity element such as hydrogen or moisture from the substrate 102, and can be formed with a single-layer structure or a stacked structure using one or more of a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. In addition, the oxide film 104 preferably has the effect of supplying oxygen to the oxide semiconductor film 106 to be formed later. In the case where a silicon oxide film is used as the oxide film 104 for example, part of oxygen therein can be released by heating the oxide film 104, so that oxygen can be supplied to the oxide semiconductor film 106 to repair oxygen deficiency in the oxide semiconductor film 106. In particular, the oxide film 104 preferably contains oxygen at an amount that exceeds at least the stoichiometry. For example, a silicon oxide film of SiO2+α (α>0) is preferably used as the oxide film 104. With the use of such a silicon oxide film as the oxide film 104, oxygen can be supplied to the oxide semiconductor film 106.
[Detailed Description of Oxide Semiconductor Film]
An oxide semiconductor to be used for the oxide semiconductor film 106 preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably contained. As a stabilizer for reducing variation in electric characteristics of a transistor using the oxide semiconductor, gallium (Ga) is preferably additionally contained. Tin (Sn) is preferably contained as a stabilizer. In addition, it is also preferable that one or more selected from hafnium (Hf), zirconium (Zr), titanium (Ti), scandium (Sc), yttrium (Y), and lanthanoid (e.g., cerium (Ce), neodymium (Nd), or gadolinium (Gd)) be contained as a stabilizer.
As the oxide semiconductor, for example, any of the following can be used: indium oxide, tin oxide, zinc oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—Zr—Zn-based oxide, an In—Ti—Zn-based oxide, an In—Sc—Zn-based oxide, an In—Y—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide.
Here, an “In—Ga—Zn-based oxide” means an oxide containing In, Ga, and Zn as its main components and there is no particular limitation on the ratio of In:Ga:Zn. The In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn.
Alternatively, a material represented by InMO3(ZnO)m (m>0, m is not an integer) may be used as the oxide semiconductor. Note that M represents one or more metal elements selected from Ga, Fe, Mn, and Co, or the above-described element as a stabilizer. Alternatively, as the oxide semiconductor, a material represented by In2SnO5(ZnO)n (n>0, n is a natural number) may be used.
For example, an In—Ga—Zn-based oxide with an atomic ratio where In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In:Ga:Zn=2:1:3, or an oxide having a composition in the neighborhood of the above composition can be used.
Further, the oxide semiconductor film 106 can be formed by a sputtering method, an atomic layer deposition (ALD) method, an evaporation method, a coating method, or the like. The thickness of the oxide semiconductor film 106 is greater than 5 nm and less than or equal to 200 nm, preferably greater than or equal to 10 nm and less than or equal to 30 nm. Further, the oxide semiconductor film 106 preferably has a structure with crystallinity, such as a single crystal structure, a polycrystalline (also referred to as polycrystal) structure, or a microcrystalline structure.
Further, the oxide semiconductor film 106 is preferably a CAAC-OS (c-axis aligned crystalline oxide semiconductor) film. The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal portions are included in an amorphous phase. Note that in most cases, the crystal portion fits inside a cube whose one side is less than 100 nm. From an observation image obtained with a transmission electron microscope (TEM), a boundary between an amorphous portion and a crystal portion in the CAAC-OS film is not clear. Further, with the TEM, a grain boundary in the CAAC-OS film is not found. Thus, in the CAAC-OS film, a reduction in electron mobility, due to the grain boundary, is suppressed.
In each of the crystal portions included in the CAAC-OS film, a c-axis is aligned in a direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, triangular or hexagonal atomic arrangement which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis. Note that, among crystal portions, the directions of the a-axis and the b-axis of one crystal portion may be different from those of another crystal portion. In this specification, a simple term “perpendicular” includes a range from 85° to 95°. In addition, a simple term “parallel” includes a range from −5° to 5°.
In the CAAC-OS film, distribution of crystal portions is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth occurs from a surface side of the oxide semiconductor film, the proportion of crystal portions in the vicinity of the surface of the oxide semiconductor film is higher than that in the vicinity of the surface where the oxide semiconductor film is formed in some cases. Further, when an impurity is added to the CAAC-OS film, the crystal portion in a region to which the impurity is added becomes amorphous in some cases.
Since the c-axes of the crystal portions included in the CAAC-OS film are aligned in the direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, the directions of the c-axes may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface where the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Note that when the CAAC-OS film is formed, the direction of c-axis of the crystal portion is the direction parallel to a normal vector of the surface where the CAAC-OS film is formed or a normal vector of the surface of the CAAC-OS film. The crystal portion is formed by film formation or by performing treatment for crystallization such as heat treatment after film formation.
With the use of the CAAC-OS film in a transistor, change in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be reduced. Change and variation in threshold voltages can be suppressed. Thus, the transistor has high reliability.
In an oxide semiconductor film having a crystal portion or an oxide semiconductor film having crystallinity, defects in the bulk can be further reduced. Further, when the surface planarity of the oxide semiconductor film having a crystal portion or the oxide semiconductor film having crystallinity is enhanced, a transistor including the oxide semiconductor can have higher field-effect mobility than a transistor including an amorphous oxide semiconductor. In order to enhance the surface planarity of the oxide semiconductor film, the oxide semiconductor is preferably formed over a flat surface. Specifically, the oxide semiconductor is preferably formed over a surface with an average surface roughness (Ra) less than or equal to 0.15 nm, preferably less than or equal to 0.1 nm.
Note that Ra is obtained by expanding, into three dimensions, arithmetic mean surface roughness that is defined by JIS B 0601: 2001 (ISO4287:1997) so as to be able to apply it to a curved surface. Ra can be expressed as an “average value of the absolute values of deviations from a reference surface to a specific surface” and is defined by Formula 1.




  
    
      
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Here, the specific surface is a surface which is a target of roughness measurement, and is a quadrilateral region which is specified by four points represented by the coordinates (x1,y1,f(x1,y1)), (x1,y2,f(x1,y2)), (x2,y1,f(x2,y1)), and (x2,y2,f(x2,y2)). S0 represents the area of a rectangle which is obtained by projecting the specific surface on the xy plane, and Z0 represents the height of the reference surface (the average height of the specific surface). Ra can be measured using an atomic force microscope (AFM).
There are three methods for forming a CAAC-OS film when the CAAC-OS film is used as the oxide semiconductor film 106. The first method is to form an oxide semiconductor film at a temperature higher than or equal to 200° C. and lower than or equal to 450° C. to form, in the oxide semiconductor film, crystal portions in which the c-axes are aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film. The second method is to form an oxide semiconductor film with a small thickness and then heat it at a temperature higher than or equal to 200° C. and lower than or equal to 700° C., to form, in the oxide semiconductor film, crystal portions in which the c-axes are aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film. The third method is to form a first oxide semiconductor film with a small thickness, then heat it at a temperature higher than or equal to 200° C. and lower than or equal to 700° C., and form a second oxide semiconductor film, to form, in the oxide semiconductor film, crystal portions in which the c-axes are aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film.
The oxide semiconductor film 106 is deposited while the substrate 102 is heated, whereby the concentration of an impurity such as hydrogen or water in the oxide semiconductor film 106 can be reduced. In addition, damage by sputtering can be reduced, which is preferable. The oxide semiconductor film 106 may be formed by an ALD method, an evaporation method, a coating method, or the like.
Note that when an oxide semiconductor film having crystallinity (single crystal or microcrystalline) other than a CAAC-OS film is formed as the oxide semiconductor film 106, there is no particular limitation on the deposition temperature.
The energy gap of the oxide semiconductor film 106 is preferably 2.8 eV to 3.2 eV, and is greater than that of silicon (1.1 eV). The minority carrier density of the oxide semiconductor film 106 is, for example, 10−9/cm3, which is much smaller than the intrinsic carrier density of silicon (1011/cm3).
Majority carriers (electrons) of the oxide semiconductor film 106 are only carriers flowing from a source of a transistor. Further, a channel formation region can be depleted completely. Thus, an off-state current of the transistor can be extremely small. The off-state current of the transistor including the oxide semiconductor film 106 is 10 yA/μm or smaller at room temperature and is 1 zA/μm or smaller at 85° C. to 95° C., which is preferably small
In the case of an n-channel transistor, the off-state current in this specification is current that flows between a source electrode and a drain electrode when the potential of a gate electrode is lower than or equal to 0 V with the potential of the source electrode as a reference potential while the potential of the drain electrode is higher than those of the source electrode and the gate electrode. Alternatively, in the case of a p-channel transistor, the off-state current in this specification is current that flows between a source electrode and a drain electrode when the potential of a gate electrode is higher than or equal to 0 V with the potential of the source electrode as a reference potential while the potential of the drain electrode is lower than those of the source electrode and the gate electrode.
Further, the subthreshold swing (S value) of the transistor including the oxide semiconductor film 106 is small. Further, the transistor has high reliability.
Note that the oxide semiconductor film 106 may have a structure in which a plurality of oxide semiconductor films is stacked. For example, the oxide semiconductor film 106 may have a stacked-layer structure of a first oxide semiconductor layer and a second oxide semiconductor layer which are formed using metal oxides with different compositions. For example, the first oxide semiconductor layer may be formed using a three-component metal oxide, and the second oxide semiconductor layer may be formed using a two-component metal oxide. Alternatively, for example, both the first oxide semiconductor layer and the second oxide semiconductor layer may be formed using three-component metal oxides.
Further, the constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer are made to be the same and the composition ratio of the constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer may be made to be different. For example, the first oxide semiconductor layer may have an atomic ratio of In:Ga:Zn=1:1:1 and the second oxide semiconductor layer may have an atomic ratio of In:Ga:Zn=3:1:2. Alternatively, the first oxide semiconductor layer may have an atomic ratio of In:Ga:Zn=1:3:2 and the second oxide semiconductor layer may have an atomic ratio of In:Ga:Zn=2:1:3.
At this time, one of the first oxide semiconductor layer and the second oxide semiconductor layer, which is closer to the gate electrode (on a channel side), preferably contains In and Ga at a proportion of In>Ga. The other which is farther from the gate electrode (on a back channel side) preferably contains In and Ga at a proportion of In Ga. In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier conduction, and when the percentage of In content in the oxide semiconductor is increased, overlap of the s orbital is likely to be increased. Therefore, an oxide having a composition of In>Ga has higher mobility than an oxide having a composition of In≦Ga. Further, in Ga, the formation energy of oxygen vacancy is larger and thus oxygen vacancy is less likely to occur, than in In; therefore, the oxide having a composition of In≦Ga has more stable characteristics than the oxide having a composition of In>Ga. Accordingly, an oxide semiconductor containing In and Ga at a proportion of In>Ga is used on a channel side, and an oxide semiconductor containing In and Ga at a proportion of In≦Ga is used on a back channel side, so that mobility and reliability of the transistor can be further improved.
Further, when the oxide semiconductor film 106 is formed to have a stacked structure, the first oxide semiconductor layer and the second oxide semiconductor layer may be formed using oxide semiconductor layers having different crystallinity. That is, the oxide semiconductor film 106 may be formed by combining a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, and an oxide semiconductor having crystallinity (e.g., a CAAC-OS) as appropriate. When an amorphous oxide semiconductor is applied to at least either the first oxide semiconductor layer or the second oxide semiconductor layer, internal stress or external stress of the oxide semiconductor film is relieved, variation in characteristics of a transistor is reduced, and reliability of the transistor can be further improved. On the other hand, an amorphous oxide semiconductor easily absorbs an impurity such as hydrogen, which serves as a donor, and oxygen deficiency is easily generated; therefore, the amorphous oxide semiconductor film is likely to be n-type. Accordingly, an oxide semiconductor having crystallinity (e.g., a CAAC-OS) is preferably used as the oxide semiconductor layer on a channel side.
As for the composition and crystallinity of the oxide semiconductor film 106 in the case where the oxide semiconductor film 106 has a stacked structure, for example, a stacked structure of an amorphous oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=1:1:1 and a crystalline oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=3:1:2 from the oxide film 104 side, and a stacked structure of a crystalline oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=1:1:1 and a crystalline oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=3:1:2 from the oxide film 104 side are given. With such a structure, crystallinity of the oxide semiconductor film 106 in the vicinity of the gate insulating film 108 can be improved, and mobility can be increased because the percentage of indium content in the oxide semiconductor in the vicinity of the gate insulating film 108 is larger than that in the oxide semiconductor on the oxide film 104 side. As another stacked structure, a stacked structure of a crystalline oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=3:1:2 and a crystalline oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=1:1:1 may be used. With such a structure, crystallinity of the oxide semiconductor in the vicinity of the gate insulating film 108 can be improved. Further, as another stacked structure, a stacked structure of an amorphous oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=1:1:1 and an amorphous oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=3:1:2, or a stacked structure of an amorphous oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=3:1:2 and an amorphous oxide semiconductor with an atomic ratio in the neighborhood of In:Ga:Zn=1:1:1 may be used. With such a structure, a constituent element of the oxide film 104 can be prevented from entering the oxide semiconductor film 106 in the vicinity of the gate insulating film 108.
Further, in the oxide semiconductor film 106, it is preferable that the channel formation region 106a be an oxide semiconductor having crystallinity (e.g., a CAAC-OS) and the low-resistance regions 106c be an amorphous oxide semiconductor. For example, after the oxide semiconductor film 106 including the channel formation region 106a is formed using a CAAC-OS film, the low-resistance regions 106c are made to be n-type or amorphous because the crystal structure of the CAAC-OS film cannot be maintained, by reaction with a metal film, doping treatment, or the like.
[Detailed Description of First Gate Insulating Film]
Silicon oxide, gallium oxide, silicon oxynitride, or the like can be used for the first gate insulating film 108a. It is preferable that the first gate insulating film 108a include oxygen in a portion which is in contact with the oxide semiconductor film 106. In particular, the first gate insulating film 108a preferably contains oxygen at an amount that exceeds at least the stoichiometry. For example, in the case where a silicon oxide film is used as the first gate insulating film 108a, a film of SiO2+α (α>0) is preferably used. With the use of the silicon oxide film as the first gate insulating film 108a, oxygen can be supplied to the oxide semiconductor film 106 and favorable electric characteristics can be obtained.
The first gate insulating film 108a can have a thickness greater than or equal to 1 nm and less than or equal to 500 nm, for example. There is no particular limitation on a method for forming the first gate insulating film 108a; for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate.
[Detailed Description of Second Gate Insulating Film]
Aluminum oxide, silicon nitride, aluminum oxynitride, silicon nitride oxide, or the like can be used for the second gate insulating film 108b. The second gate insulating film 108b is preferably a film which can prevent oxygen from being released from the first gate insulating film 108a. The second gate insulating film 108b can be formed using a high-k material such as hafnium oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium silicate to which nitrogen is added (HfSiOxNy (x>0, y>0)), hafnium aluminate (HfAlxOy (x>0, y>0)), or lanthanum oxide. By using such a material, gate leakage current can be reduced.
As described in this embodiment, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. Note that the structure of the gate insulating film 108 is not limited thereto and may have a single-layer structure or a stacked structure of three or more layers.
The second gate insulating film 108b can have a thickness greater than or equal to 1 nm and less than or equal to 500 nm, for example. There is no particular limitation on a method for forming the second gate insulating film 108b; for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate.
[Detailed Description of Gate Electrode]
For the gate electrode 110, it is possible to use a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials, for example. Alternatively, the gate electrode 110 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3—SnO2, which is abbreviated to ITO in some cases), indium zinc oxide (In2O3—ZnO), or any of these metal oxide materials containing silicon or silicon oxide can be used. The gate electrode 110 can be formed to have a single-layer structure or a stacked structure using any of the above materials. There is no particular limitation on a method for forming the gate electrode 110, and a variety of deposition methods such as an evaporation method, a PE-CVD method, a sputtering method, and a spin coating method can be employed.
[Detailed Description of Metal Oxide Insulating Film]
A material containing one or more elements selected from aluminum, indium, titanium, tin, tungsten, and zinc can be used for the metal oxide insulating films 114. For example, when aluminum or titanium is used for a metal film and reacts with the oxide semiconductor film 106, aluminum oxide or titanium oxide can be formed. The thickness of the metal oxide insulating films 114 can be greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 1 nm and less than or equal to 10 nm, more preferably greater than or equal to 2 nm and less than or equal to 5 nm. There is no particular limitation on a method for forming the metal oxide insulating films 114; for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate.
[Detailed Description of Sidewall Insulating Film]
The sidewall insulating films 112 are preferably formed using a material which does not react with the metal film to be formed later by heat treatment. For example, a single layer or a stacked layer using any of nitrides such as silicon nitride, aluminum nitride, and gallium nitride can be used. There is no particular limitation on a method for forming the sidewall insulating films 112, and a variety of film formation methods such as an evaporation method, a PE-CVD method, a sputtering method, and a spin coating method can be used.
[Detailed Description of Protective Insulating Film]
The protective insulating film 116 is preferably formed using an inorganic insulating film and may be formed as a single layer or a stacked layer using any of oxide insulating films such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, and a hafnium oxide film. Further, over the above oxide insulating film, a single layer or a stacked layer using any of nitride insulating films such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, and an aluminum nitride oxide film may be formed. For example, as a stacked layer, a silicon oxide film and an aluminum oxide film can be formed in this order over the gate electrode 110 by a sputtering method. There is no particular limitation on a method for forming the protective insulating film 116; for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, an ALD method, or the like can be employed as appropriate.
Alternatively, in particular, a dense inorganic insulating film is preferably formed as the protective insulating film 116. For example, an aluminum oxide film can be formed by a sputtering method. By forming an aluminum oxide film having high density (a film density of 3.2 g/cm3 or higher, preferably 3.6 g/cm3 or higher), a shielding effect (blocking effect) of preventing the protective insulating film 116 from transmitting both oxygen and an impurity such as hydrogen or moisture which might enter the oxide semiconductor film 106 can be obtained. Therefore, in and after the manufacturing process, the aluminum oxide film functions as a protective film to prevent an impurity such as hydrogen or moisture, which causes a change of the oxide semiconductor film 106, from being mixed into the oxide semiconductor film 106 and to prevent oxygen from being released, which is a main constituent material of the oxide semiconductor film 106. Note that the film density can be measured by Rutherford backscattering spectrometry (RBS) or X-ray reflection (XRR).
[Detailed Description of Interlayer Insulating Film]
The interlayer insulating film 118 is preferably formed using an inorganic insulating film and may be formed as a single layer or a stacked layer using any of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and a silicon nitride oxide film. There is no particular limitation on a method for forming the interlayer insulating film 118; for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, an ALD method, or the like can be employed as appropriate.
[Detailed Description of Source Electrode and Drain Electrode]
As the source electrode 120a and the drain electrode 120b, for example, a metal film containing an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten can be used. Alternatively, the source electrode 120a and the drain electrode 120b may have a structure in which a film of a high-melting-point metal such as titanium, molybdenum, or tungsten, or a nitride film of any of these metals (e.g., a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) is stacked on either or both of the bottom surface and the top surface of a metal film of aluminum, copper, or the like. Further, a conductive film used for the source electrode 120a and the drain electrode 120b may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3—SnO2, abbreviated to ITO), or indium zinc oxide (In2O3—ZnO) can be used. The conductive film used for the source electrode and the drain electrode can be formed with a single-layer structure or a stacked structure using any of the above materials. There is no particular limitation on a method for forming the conductive film, and a variety of deposition methods such as an evaporation method, a PE-CVD method, a sputtering method, and a spin coating method can be employed.
Note that details of the other components will be described in <Method 1 for Manufacturing Semiconductor Device> below, with reference to FIGS. 2A to 2E, FIGS. 3A to 3E, and FIGS. 4A to 4D.
<Method 1 for Manufacturing Semiconductor Device>
An example of a method for manufacturing the semiconductor device illustrated in FIGS. 1A and 1B of this embodiment will be described below with reference to FIGS. 2A to 2E, FIGS. 3A to 3E, and FIGS. 4A to 4D.
First, the substrate 102 is prepared, and then the oxide film 104 and the oxide semiconductor film 106 including a channel formation region are formed over the substrate 102 (see FIG. 2A).
The substrate 102 may be subjected to plasma treatment or the like before the oxide film 104 is formed. As plasma treatment, reverse sputtering in which an argon gas is introduced and plasma is generated can be performed. The reverse sputtering refers to a method in which an RF power source is used for application of voltage to the substrate 102 side in an argon atmosphere so that plasma is generated in the vicinity of the substrate 102 to modify a surface of the substrate. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used. The reverse sputtering can remove particle substances (also referred to as particles or dust) attached to the surface of the substrate 102.
The oxide semiconductor film 106 can be formed by a wet etching method or a dry etching method. An etching gas such as BCl3, Cl2, or O2 can be used in the dry etching method. Further, a dry etching apparatus using a high-density plasma source such as electron cyclotron resonance (ECR) or inductive coupled plasma (ICP) can be used to improve a dry etching rate. An end portion of the oxide semiconductor film 106 is preferably tapered at an angle of 20° to 50°.
The oxide film 104 and the oxide semiconductor film 106 are preferably formed successively without exposure to the air because an impurity element such as moisture or hydrogen contained in the air can be prevented from entering the interface between the oxide film 104 and the oxide semiconductor film 106.
In a formation step of the oxide semiconductor film 106, it is preferable that hydrogen or water be contained in the oxide semiconductor film 106 as little as possible. For example, it is preferable that the substrate 102 over which the oxide film 104 is already formed be preheated in a preheating chamber of a sputtering apparatus as pretreatment for formation of the oxide semiconductor film 106 so that impurities such as hydrogen and moisture adsorbed to the substrate 102 and the oxide film 104 are removed and exhausted. Note that the temperature of the preheating is preferably set such that no oxygen, or little oxygen, if any, is released from the oxide film 104. Further, the oxide semiconductor film 106 is preferably formed in a deposition chamber from which remaining moisture has been exhausted.
To remove the moisture in a preheating chamber and the deposition chamber, an entrapment vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an exhaustion unit may be a turbo pump provided with a cold trap. From the preheating chamber and the deposition chamber which are evacuated with a cryopump, a hydrogen atom, a compound containing a hydrogen atom such as water (H2O) (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the concentration of an impurity such as hydrogen or moisture in the oxide semiconductor film 106 can be reduced.
In this embodiment, the oxide semiconductor film 106 is formed by a sputtering method using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1 or a metal oxide target having an atomic ratio of In:Ga=2:1. Note that the target used for forming the oxide semiconductor film 106 is not limited to the targets including the above materials and having the above ratios. The oxide semiconductor film 106 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. The target used for forming the oxide semiconductor film 106 preferably has crystallinity; that is, a single crystal target, a polycrystalline target, or the like is preferably used. With the use of the target having crystallinity, a formed thin film also has crystallinity. In particular, the formed thin film tends to have a c-axis-aligned crystal.
In addition, shortly after the oxide semiconductor film 106 is deposited, it is preferable that the oxide semiconductor film contain oxygen at an amount that exceeds the stoichiometry, i.e., the oxide semiconductor films be supersaturated. As an example, in the case where the oxide semiconductor film 106 is deposited by a sputtering method, the deposition is preferably performed under the condition where the proportion of oxygen in a deposition gas is large, and in particular, the deposition is preferably performed in an oxygen atmosphere (an oxygen gas: 100%). For example, in the case where an In—Ga—Zn-based oxide (IGZO) is to be used for the oxide semiconductor film 106 and the deposition is performed under the condition where the proportion of oxygen in the deposition gas is large (in particular, in an atmosphere of an oxygen gas of 100%), Zn release from the film can be suppressed even when the deposition temperature is 300° C. or higher.
Further, when the oxide semiconductor film 106 is formed using the metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1, the composition of the thin film formed over the substrate is different from that of the target in some cases. For example, when the metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 is used, the composition of the oxide semiconductor film 106, which is a thin film, becomes In:Ga:Zn=1:1:0.6 to 1:1:0.8 [atomic ratio] in some cases, although it depends on the deposition conditions. This is because in deposition of the oxide semiconductor film 106, Zn is sublimed, or because a sputtering rate differs between the components of In, Ga, and Zn.
Accordingly, in order to form a thin film having a desired composition ratio, the composition of the metal oxide target needs to be adjusted in advance. For example, in order to make the composition of the oxide semiconductor film 106, which is a thin film, be In:Ga:Zn=1:1:1 [atomic ratio], the composition of the metal oxide target is preferably In:Ga:Zn=1:1:1.5 [atomic ratio]. In other words, the percentage of Zn content in the metal oxide target is preferably made higher in advance. The composition of the target is not limited to the above value, and can be adjusted as appropriate depending on the deposition conditions or the composition of the thin film to be formed. Further, it is preferable to increase the percentage of Zn content in the metal oxide target because in that case, the obtained thin film can have higher crystallinity.
The relative density of the metal oxide target is higher than or equal to 90% and lower than or equal to 100%, preferably higher than or equal to 95%, more preferably higher than or equal to 99.9%. With the use of a metal oxide target with a high relative density, the formed oxide semiconductor film 106 can be dense.
As a sputtering gas used for depositing the oxide semiconductor film 106, it is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed.
After the oxide semiconductor film 106 is formed, the oxide semiconductor film 106 may be subjected to heat treatment. The temperature of the heat treatment is higher than or equal to 300° C. and lower than or equal to 700° C., or lower than the strain point of the substrate. The heat treatment can remove excess hydrogen (including water and a hydroxyl group) from the oxide semiconductor film 106. Note that the heat treatment is also referred to as dehydration treatment (dehydrogenation treatment) in this specification and the like in some cases.
The heat treatment can be performed in such a manner that, for example, an object to be processed is introduced into an electric furnace in which a resistance heater or the like is used and heated at 450° C. in a nitrogen atmosphere for one hour. The oxide semiconductor film 106 is not exposed to the air during the heat treatment so that the entry of water and hydrogen can be prevented.
A heat treatment apparatus is not limited to the electric furnace and may be an apparatus for heating an object to be processed by thermal conduction or thermal radiation from a medium such as a heated gas. For example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon is used.
As the heat treatment, for example, a GRTA process may be performed as follows. The object is put in a heated inert gas atmosphere, heated for several minutes, and taken out of the inert gas atmosphere. The GRTA process enables high-temperature heat treatment for a short time. Moreover, the GRTA process can be employed even when the temperature exceeds the upper temperature limit of the object. Note that the inert gas may be switched to a gas containing oxygen during the process.
Note that as the inert gas atmosphere, an atmosphere that contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like is preferably used. The purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is, for example, 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the concentration of an impurity is 1 ppm or lower, preferably 0.1 ppm or lower).
The dehydration treatment (dehydrogenation treatment) might be accompanied by release of oxygen which is a main constituent material of the oxide semiconductor film 106 to lead to a reduction in oxygen. Oxygen deficiency exists in a portion where oxygen is released in the oxide semiconductor film 106, and a donor level which leads to a change in the electrical characteristics of a transistor is formed owing to the oxygen deficiency. Therefore, in the case where the dehydration treatment (dehydrogenation treatment) is performed, oxygen is preferably supplied to the oxide semiconductor film 106. By supply of oxygen to the oxide semiconductor film 106, oxygen deficiency in the oxide semiconductor film 106 can be repaired.
The oxygen deficiency in the oxide semiconductor film 106 may be repaired in the following manner for example: after the oxide semiconductor film 106 is subjected to the dehydration treatment (dehydrogenation treatment), a high-purity oxygen gas, a high-purity nitrous oxide gas, or ultra dry air (the moisture amount is less than or equal to 20 ppm (−55° C. by conversion into a dew point), preferably less than or equal to 1 ppm, more preferably less than or equal to 10 ppb, in the measurement with the use of a dew point meter of a cavity ring down laser spectroscopy (CRDS) system) is introduced into the same furnace. It is preferable that water, hydrogen, or the like not be contained in the oxygen gas or the nitrous oxide gas. The purity of the oxygen gas or the nitrous oxide gas which is introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher (i.e., the impurity concentration in the oxygen gas or the nitrous oxide gas is preferably 1 ppm or lower, more preferably 0.1 ppm or lower).
As an example of a method for supplying oxygen to the oxide semiconductor film 106, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be added to the oxide semiconductor film 106 in order to supply oxygen to the oxide semiconductor film 106. An ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be employed as a method for adding oxygen.
As another example of a method for supplying oxygen to the oxide semiconductor film 106, oxygen may be supplied to the oxide semiconductor film 106 in such a manner that the oxide film 104, the gate insulating film 108 to be formed later, or the like is heated and part of oxygen is released. In particular, in this embodiment, oxygen that is released from the oxide film 104 is preferably supplied to the oxide semiconductor film 106.
As described above, after the oxide semiconductor film 106 is formed, it is preferable that the dehydration treatment (dehydrogenation treatment) be performed to remove hydrogen or moisture from the oxide semiconductor film 106, so that the oxide semiconductor film 106 is highly purified so as to include as few impurities as possible, and oxygen whose amount is reduced in the dehydration treatment (dehydrogenation treatment) be added to the oxide semiconductor film 106 or oxygen be supplied to repair oxygen deficiency in the oxide semiconductor film 106. In this specification and the like, supplying oxygen to the oxide semiconductor film 106 may be expressed as oxygen adding treatment. Alternatively, making the oxide semiconductor film 106 contain oxygen at an amount that exceeds the stoichiometry may be expressed as treatment for making an oxygen-excess state.
Note that the case is described where dehydration treatment (dehydrogenation treatment) and oxygen adding treatment are performed after the oxide semiconductor film 106 is processed into an island shape; however, an embodiment of the disclosed invention is not construed as being limited to the case. Such treatment may be performed before the oxide semiconductor film 106 is processed into an island shape. Alternatively, after the interlayer insulating film 118 is formed, which is to be formed later, heat treatment may be performed so that oxygen is supplied from the oxide film 104, the gate insulating film 108, or the like to the oxide semiconductor film 106.
In this manner, hydrogen or moisture is removed from the oxide semiconductor film 106 by the dehydration treatment (dehydrogenation treatment) and oxygen deficiency therein are repaired by the oxygen adding treatment, whereby the oxide semiconductor film can be an i-type (intrinsic) or substantially i-type oxide semiconductor film. The oxide semiconductor film formed in such a manner contains extremely few (close to zero) carriers derived from a donor, and the carrier concentration thereof is lower than 1×1014/cm3, preferably lower than 1×1012/cm3, more preferably lower than 1×1011/cm3.
It is preferable that the oxide semiconductor film 106 be highly purified and hardly contain an impurity such as copper, aluminum, or chlorine. In a process for manufacturing a transistor, it is preferable to select steps as appropriate where such an impurity might not be mixed into the oxide semiconductor film 106 or be attached onto a surface thereof. In the case where such an impurity is attached onto the surface of the oxide semiconductor film 106, the oxide semiconductor film 106 is preferably exposed to oxalic acid, dilute hydrofluoric acid, or the like or subjected to plasma (e.g., N2O plasma) treatment, for example, so that the impurity on the surface of the oxide semiconductor film 106 can be removed. Specifically, the oxide semiconductor film 106 has a copper concentration of 1×1018 atoms/cm3 or lower, preferably 1×1017 atoms/cm3 or lower, an aluminum concentration of 1×1018 atoms/cm3 or lower, and a chlorine concentration of 2×1018 atoms/cm3 or lower.
The oxide semiconductor film 106 is preferably highly purified by sufficient removal of an impurity such as hydrogen or sufficient supply of oxygen so as to be supersaturated with oxygen. Specifically, the oxide semiconductor film 106 has a hydrogen concentration of 5×1019 atoms/cm3 or lower, preferably 5×1018 atoms/cm3 or lower, more preferably 5×1017 atoms/cm3 or lower. Note that the concentration of hydrogen in the oxide semiconductor film 106 is measured by secondary ion mass spectrometry (SIMS). In order that the oxide semiconductor film 106 is supersaturated with oxygen by sufficient supply of oxygen, it is preferable that an insulating film containing excess oxygen (e.g., a silicon oxide film) be provided so as to cover and be in contact with the oxide semiconductor film 106.
As the insulating film containing excess oxygen, a silicon oxide film or a silicon oxynitride film including a large amount of oxygen by adjusting deposition conditions as appropriate in a PE-CVD method or a sputtering method is used. To make excess oxygen be further contained in the insulating film, oxygen is added to the insulating film by an ion implantation method, an ion doping method, or plasma treatment.
Further, in the case where the hydrogen concentration in the insulating film containing excess oxygen is 7.2×1020 atoms/cm3 or higher, variations in initial characteristics of transistors are increased, a channel length dependence of electrical characteristics of a transistor is increased, and a transistor is significantly degraded in the BT stress test; therefore, the hydrogen concentration in the insulating film containing excess oxygen is set to lower than 7.2×1020 atoms/cm3. In other words, the hydrogen concentration in the oxide semiconductor film 106 is preferably lower than or equal to 5×1019 atoms/cm3, and the hydrogen concentration in the insulating film containing excess oxygen is preferably lower than 7.2×1020 atoms/cm3.
Further, a blocking film (e.g., an aluminum oxide film) that suppresses oxygen release from the oxide semiconductor film 106 is preferably formed to cover the oxide semiconductor film 106 and to be provided outside the insulating film containing excess oxygen.
The oxide semiconductor film 106 is covered with the insulating film containing excess oxygen or the blocking film, so that the oxide semiconductor film 106 can be in a state in which oxygen the amount of which is approximately the same as the stoichiometry is contained or in a supersaturated state in which oxygen which exceeds the stoichiometry is contained.
Next, the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b), and a conductive film 109 are formed over the oxide semiconductor film 106 (see FIG. 2B).
Next, a resist mask is formed over the conductive film 109 through a photolithography step, selective etching is performed to form the gate electrode 110, and then the resist mask is removed. Thus, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106 (see FIG. 2C).
Note that the resist mask for forming the gate electrode 110 may be formed by an inkjet method, in which case manufacturing costs can be reduced because a photomask is not used. The gate electrode 110 may be etched by either dry etching or wet etching, or by both of them.
Next, with the use of the gate electrode 110 as a mask, dopant 142 is selectively introduced into the oxide semiconductor film 106 through the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b). In the introduction of the dopant 142, the gate electrode 110 serves as a mask, so that the channel formation region 106a is formed in a region of the oxide semiconductor film 106, which overlaps with the gate electrode 110, and the impurity regions 106b are formed in regions into which the dopant 142 is introduced (see FIG. 2D).
The dopant 142 is an impurity that changes the conductivity of the oxide semiconductor film 106. One or more selected from the following can be used as the dopant 142: Group 15 elements (typical examples thereof are nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).
The dopant 142 can be introduced into the oxide semiconductor film 106 through another film (e.g., the gate insulating film 108) by an implantation method. As the method for introducing the dopant 142, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In that case, it is preferable to use a single ion of the dopant 142, or a fluoride ion or chloride ion thereof.
The introduction of the dopant 142 may be controlled by setting as appropriate the implantation conditions such as the acceleration voltage and the dosage, or the thickness of the film through which the dopant passes. In this embodiment, phosphorus is used as the dopant 142, whose ion is implanted by an ion implantation method. Note that the dosage of the dopant 142 may be greater than or equal to 1×1013 ions/cm2 and less than or equal to 5×1016 ions/cm2.
The concentration of the dopant 142 in the impurity regions 106b is preferably higher than or equal to 5×1018/cm3 and lower than or equal to 1×1022/cm3.
The dopant 142 may be introduced while the substrate 102 is heated.
The introduction of the dopant 142 into the oxide semiconductor film 106 may be performed plural times, and the number of kinds of dopant may be plural.
In the case where the oxide semiconductor film 106 is formed using an oxide semiconductor having crystallinity (e.g., a CAAC-OS), the impurity regions 106b preferably become an amorphous oxide semiconductor by the introduction of the dopant 142. In other words, the channel formation region 106a is an oxide semiconductor film having crystallinity, and the impurity regions 106b are an amorphous oxide semiconductor. In a cross section taken along the channel length direction, the oxide semiconductor film 106 including adjacent regions having different crystal structures in the lateral direction is formed. With such a structure, oxygen deficiency or hydrogen which is an impurity in the channel formation region 106a is extracted to the impurity regions 106b which is an amorphous oxide semiconductor, so that the channel formation region 106a can be further purified.
Next, an insulating film 111 is formed over the gate insulating film 108 (specifically, over the second gate insulating film 108b) and the gate electrode 110 (see FIG. 2E).
Then, the insulating film 111 is etched, so that the sidewall insulating films 112 are formed. Thus, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction (see FIG. 3A).
The sidewall insulating films 112 can be formed in a self-aligned manner by performing a highly anisotropic etching step on the insulating film 111. As an example of an etching method, a dry etching method is preferably employed. As an etching gas used for dry etching, for example, a gas including fluorine such as trifluoromethane, octafluorocyclobutane, or tetrafluoromethane can be used. A rare gas or hydrogen may be added to the etching gas. As the dry etching method, a reactive ion etching (RIE) method in which high-frequency voltage is applied to a substrate is preferably used.
Note that the sidewall insulating films 112 may be formed in such a manner that a resist mask is formed over the insulating film 111 and etching is performed.
Next, after the formation of the sidewall insulating films 112, part of the gate insulating film 108 is removed with the use of the gate electrode 110 and the sidewall insulating films 112 as masks, so that the surface of the oxide semiconductor film 106 (specifically, part of the impurity regions 106b) is exposed (see FIG. 3B).
Note that the gate insulating film 108 may be processed in the formation of the sidewall insulating films 112.
Next, a metal film 113 is formed over the oxide film 104, the oxide semiconductor film 106, the gate electrode 110, and the sidewall insulating films 112. Thus, the metal film 113 is formed in contact with part of the oxide semiconductor film 106 (see FIG. 3C).
A metal material selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc can be used for the metal film 113. In this embodiment, an aluminum film with a thickness of 10 nm is formed by a sputtering method.
Next, heat treatment is performed in the state where the metal film 113 and the oxide semiconductor film 106 (specifically, the part of the impurity regions 106b) are in contact with each other, so that the metal element is introduced into the oxide semiconductor film 106 from the metal film 113 and the low-resistance regions 106c including the metal element are formed. Further, oxygen is diffused into the metal film 113 from the oxide film 104 and the oxide semiconductor film 106 by the heat treatment, so that the metal film 113 is selectively oxidized. Thus, metal oxide insulating films 113a are formed. Note that in the oxide semiconductor film 106, the channel formation region 106a is formed under the gate electrode 110, the impurity regions 106b are formed under the sidewall insulating films 112, and the low-resistance regions 106c are formed in contact with the metal oxide insulating films 113a (see FIG. 3D).
The heat treatment is preferably performed at a temperature higher than or equal to 300° C. and lower than or equal to 700° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C. under an inert gas atmosphere or reduced pressure. The inert gas atmosphere is preferably an atmosphere which contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like. The heat treatment is preferably performed in an atmosphere in which the surface of the metal film 113 is not oxidized by the heat treatment. Further, the heating time can be set as appropriate by a practitioner such that the oxide semiconductor film 106 and the metal film 113 can react with each other.
By such heat treatment, oxidation of the metal film 113 does not proceed from its surface but proceeds from a portion in contact with the oxide film 104 or the oxide semiconductor film 106. Therefore, the metal oxide insulating films 113a can be formed in regions in contact with the oxide film 104 and the oxide semiconductor film 106, and the metal film 113 remains in another region.
Next, the metal film 113 is removed. Thus, the metal oxide insulating films 114 are formed (see FIG. 3E).
For example, in the case where aluminum is used for the metal film, the metal film 113 can be removed by a wet etching method using an etchant such as HCl, H2SO4, H3PO4, or H2C2O4. However, the method for removing the metal film 113 is not limited thereto. Depending on the materials of the metal film 113 and the metal oxide insulating films 114, a practitioner can select an etchant or an etching method as appropriate as long as etching selectivity is ensured.
Next, the protective insulating film 116 and the interlayer insulating film 118 are formed to cover the oxide film 104, the gate electrode 110, the sidewall insulating films 112, and the metal oxide insulating films 114 (see FIG. 4A).
Then, a resist mask is formed in a desired region over the interlayer insulating film 118, and the interlayer insulating film 118, the protective insulating film 116, and the metal oxide insulating films 114 are selectively etched; thus, opening portions reaching the low-resistance regions 106c are formed (see FIG. 4B).
Next, a conductive film 119 is formed over the interlayer insulating film 118 and in the opening portions (see FIG. 4C).
Next, a resist mask is formed in a desired region over the conductive film 119, and the conductive film 119 is selectively etched; thus, the source electrode 120a and the drain electrode 120b are formed (see FIG. 4D).
Through the above manufacturing steps, the semiconductor device shown in FIGS. 1A and 1B can be manufactured.
As described in this embodiment, one of the technical ideas of the present invention is as follows. By reaction between an oxide semiconductor film and a metal film, low-resistance regions are formed in the oxide semiconductor film including a channel formation region in a self-aligned manner and part of the metal film is oxidized to form metal oxide insulating films for covering the low-resistance regions. Then, another part of the metal film, which is not oxidized, is removed. Thus, the metal oxide insulating films can prevent release of oxygen contained in an oxide film and the oxide semiconductor film. Accordingly, oxygen can be favorably supplied to the oxide semiconductor film including the channel formation region from the oxide film, and a transistor with stable electric characteristics can be provided.
The method and structure described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 2
In this embodiment, a modification example of the semiconductor device described in Embodiment 1, and a method for manufacturing a semiconductor device, which is different from that described in Embodiment 1, will be described with reference to FIGS. 5A and 5B, FIGS. 6A to 6E, FIGS. 7A to 7E, and FIGS. 8A to 8D. Note that portions similar to those in FIGS. 1A and 1B, FIGS. 2A to 2E, FIGS. 3A to 3E, and FIGS. 4A to 4D are denoted by the same reference numerals, and description thereof is skipped.
<Structure Example 2 of Semiconductor Device>
FIGS. 5A and 5B are a plan view and a cross-sectional view of a top-gate self-aligned transistor as an example of a semiconductor device. FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line X2-Y2 in FIG. 5A. Note that in FIG. 5A, some components of the transistor (e.g., the gate insulating film 108) are not illustrated for simplification.
The semiconductor device illustrated in FIGS. 5A and 5B includes the substrate 102, the oxide film 104 formed over the substrate 102, the oxide semiconductor film 106 which is formed over the oxide film 104 and includes the channel formation region 106a and the low-resistance regions 106c and low-resistance regions 106d having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c and the low-resistance regions 106d, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, and the sidewall insulating films 112 which are formed over the metal oxide insulating films 114 and formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. The low-resistance regions 106c and the low-resistance regions 106d include at least a metal element included in the metal oxide insulating films 114.
In addition, the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the gate electrode 110, the source electrode 120a and the drain electrode 120b electrically connected to the low-resistance regions 106c, and the interlayer insulating film 118 may be included.
Note that as illustrated in FIG. 5B, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
The oxide semiconductor film 106 includes the channel formation region 106a, the low-resistance regions 106c, and the low-resistance regions 106d. The low-resistance regions 106c and the low-resistance regions 106d can be formed in a self-aligned manner. Specifically, after the oxide semiconductor film 106 including the channel formation region 106a is formed, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106. Then, part of the gate insulating film 108 is removed with the use of the gate electrode 110 as a mask; thus, a surface of the oxide semiconductor film 106 is exposed. After that, a metal film is formed in contact with part of the oxide semiconductor film 106 and heat treatment is performed in the state where the oxide semiconductor film 106 is in contact with the metal film so that a metal element is introduced into the oxide semiconductor film 106 from the metal film; thus, the low-resistance regions 106d including the metal element are formed. Further, the metal film which is in contact with the oxide film 104 and the oxide semiconductor film 106 is selectively oxidized by the heat treatment, whereby the metal oxide insulating films 114 are formed. The metal film is removed. After that, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. Then, dopant is selectively introduced into the oxide semiconductor film 106 through the metal oxide insulating films 114 with the use of the gate electrode 110 and the sidewall insulating films 112 as masks, so that the low-resistance regions 106c are formed.
With such a structure, the low-resistance regions 106c and the low-resistance regions 106d are formed in the oxide semiconductor film 106 in a self-aligned manner, and the metal oxide insulating films 114 are formed over the low-resistance regions 106c and the low-resistance regions 106d. The metal oxide insulating films 114 can effectively prevent entry of an impurity to the oxide semiconductor film 106 or release of oxygen included in the oxide film 104 and the oxide semiconductor film 106. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed.
Further, in the oxide semiconductor film 106, the low-resistance region 106d having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at high concentration. The low-resistance regions 106d are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at low concentration. With such a structure, a potential difference between the source and the drain, which is associated with the channel formation region 106a, can be reduced, and the semiconductor device can be highly reliable.
The structure of the semiconductor device described in this embodiment is different from that of the semiconductor device described in Embodiment 1 in that the low-resistance region 106d having resistance different from that of the low resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. Further, the shapes of the gate insulating film 108, the metal oxide insulating films 114, and the sidewall insulating films 112 in this embodiment are different from those in Embodiment 1.
Note that components that can be used for the semiconductor device in this embodiment can be similar to those in Embodiment 1; therefore, detailed description thereof is omitted.
Note that the details of other components are described in <Method 2 for Manufacturing Semiconductor Device> below, with reference to FIGS. 6A to 6E, FIGS. 7A to 7E, and FIGS. 8A to 8D.
<Method 2 for Manufacturing Semiconductor Device>
An example of a method for manufacturing the semiconductor device illustrated in FIGS. 5A and 5B of this embodiment will be described below with reference to FIGS. 6A to 6E, FIGS. 7A to 7E, and FIGS. 8A to 8D.
First, the substrate 102 is prepared, and then the oxide film 104 and the oxide semiconductor film 106 including a channel formation region are formed over the substrate 102 (see FIG. 6A).
Next, the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b), and the conductive film 109 are formed over the oxide semiconductor film 106 (see FIG. 6B).
Next, a resist mask is formed over the conductive film 109 through a photolithography step, selective etching is performed to form the gate electrode 110, and then the resist mask is removed. Thus, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106 (see FIG. 6C).
Next, part of the gate insulating film 108 is removed with the use of the gate electrode 110 as a mask, so that the surface of the oxide semiconductor film 106 is exposed (see FIG. 6D).
Note that the gate insulating film 108 may be processed in the formation of the gate electrode 110.
Next, the metal film 113 is formed over the oxide film 104, the oxide semiconductor film 106, and the gate electrode 110. Thus, the metal film 113 is formed in contact with part of the oxide semiconductor film 106 (see FIG. 6E).
A metal material selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc can be used for the metal film 113. In this embodiment, an aluminum film with a thickness of 10 nm is formed by a sputtering method.
Next, heat treatment is performed in the state where the metal film 113 and the oxide semiconductor film 106 are in contact with each other, so that the metal element is introduced from the metal film 113. Thus, the low-resistance regions 106d including the metal element are formed and the channel formation region 106a is formed under the gate electrode 110. Further, oxygen is diffused into the metal film 113 from the oxide film 104 and the oxide semiconductor film 106 by the heat treatment, so that the metal film 113 is selectively oxidized. Thus, the metal oxide insulating films 113a are formed (see FIG. 7A).
The heat treatment is preferably performed at a temperature higher than or equal to 300° C. and lower than or equal to 700° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C. under an inert gas atmosphere or reduced pressure. The inert gas atmosphere is preferably an atmosphere which contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like. The heat treatment is preferably performed in an atmosphere in which the surface of the metal film 113 is not oxidized by the heat treatment. Further, the heating time can be set as appropriate by a practitioner such that the oxide semiconductor film 106 and the metal film 113 can react with each other.
By such heat treatment, oxidation of the metal film 113 does not proceed from its surface but proceeds from a portion in contact with the oxide film 104 or the oxide semiconductor film 106. Therefore, the metal oxide insulating films 113a can be formed in regions in contact with the oxide film 104 and the oxide semiconductor film 106 and the metal film 113 remains in another region.
Next, the metal film 113 is removed. Thus, the metal oxide insulating films 114 are formed (see FIG. 7B).
For example, in the case where aluminum is used for the metal film, the metal film 113 can be removed by a wet etching method using an etchant such as HCl, H2SO4, H3PO4, or H2C2O4. However, the method for removing the metal film 113 is not limited thereto. Depending on the materials of the metal film 113 and the metal oxide insulating films 114, a practitioner can select an etchant or an etching method as appropriate as long as etching selectivity is ensured.
Next, the insulating film 111 is formed over the metal oxide insulating films 114 and the gate electrode 110 (see FIG. 7C).
Then, the insulating film 111 is etched, so that the sidewall insulating films 112 are formed. Thus, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction (see FIG. 7D).
The sidewall insulating films 112 can be formed in a self-aligned manner by performing a highly anisotropic etching step on the insulating film 111. In addition to the materials mentioned in [Detailed Description of Sidewall Insulating Film] in Embodiment 1, an oxide film formed of silicon oxide, silicon oxynitride, or the like can be used as the sidewall insulating films 112.
Note that the sidewall insulating films 112 may be formed in such a manner that a resist mask is formed over the insulating film 111 and etching is performed.
Next, the dopant 142 is selectively introduced into the oxide semiconductor film 106 through the metal oxide insulating films 114 with the use of the gate electrode 110 and the sidewall insulating films 112 as masks. In the oxide semiconductor film 106, the channel formation region 106a is formed under the gate electrode 110, the low resistance regions 106d are formed under the sidewall insulating films 112, and the low-resistance regions 106c are formed in contact with the metal oxide insulating films 114 (see FIG. 7E).
The dopant 142 is an impurity that changes the conductivity of the oxide semiconductor film 106. One or more selected from the following can be used as the dopant 142: Group 15 elements (typical examples thereof are nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).
The dopant 142 can be introduced into the oxide semiconductor film 106 through another film (e.g., the metal oxide insulating films 114) by an implantation method. As the method for introducing the dopant 142, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In that case, it is preferable to use a single ion of the dopant 142, or a fluoride ion or chloride ion thereof.
The introduction of the dopant 142 may be controlled by setting as appropriate the implantation conditions such as the acceleration voltage and the dosage, or the thickness of the film through which the dopant passes. In this embodiment, phosphorus is used as the dopant 142, whose ion is implanted by an ion implantation method. Note that the dosage of the dopant 142 may be greater than or equal to 1×1013 ions/cm2 and less than or equal to 5×1016 ions/cm2.
The dopant 142 may be introduced with the substrate 102 heated.
The introduction of the dopant 142 into the oxide semiconductor film 106 may be performed plural times, and the number of kinds of dopant may be plural.
Although the case where the dopant 142 is introduced is described in this embodiment, the present invention is not limited thereto. It is possible that the dopant 142 is not introduced so that the oxide semiconductor film 106 includes the low-resistance regions 106d and does not include the low-resistance regions 106c. 
Next, the protective insulating film 116 and the interlayer insulating film 118 are formed to cover the gate electrode 110, the sidewall insulating films 112, and the metal oxide insulating films 114 (see FIG. 8A).
Then, a resist mask is formed in a desired region over the interlayer insulating film 118, and the interlayer insulating film 118, the protective insulating film 116, and the metal oxide insulating films 114 are selectively etched; thus, opening portions reaching the low-resistance regions 106c are formed (see FIG. 8B).
Next, the conductive film 119 is formed over the interlayer insulating film 118 and in the opening portions (see FIG. 8C).
Next, a resist mask is formed in a desired region over the conductive film 119, and the conductive film 119 is selectively etched; thus, the source electrode 120a and the drain electrode 120b are formed (see FIG. 8D).
Through the above manufacturing steps, the semiconductor device shown in FIGS. 5A and 5B can be manufactured.
As described in this embodiment, one of the technical ideas of the present invention is as follows. By reaction between an oxide semiconductor film and a metal film, low-resistance regions are formed in the oxide semiconductor film including a channel formation region in a self-aligned manner and part of the metal film is oxidized to form metal oxide insulating films for covering the low-resistance regions. Then, another part of the metal film, which is not oxidized, is removed. Thus, the metal oxide insulating films can prevent release of oxygen contained in an oxide film and the oxide semiconductor film. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed. Accordingly, oxygen can be favorably supplied to the oxide semiconductor film including the channel formation region from the oxide film, and a transistor with stable electric characteristics can be provided.
The method and structure described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 3
In this embodiment, a modification example of the semiconductor devices described in Embodiments 1 and 2, and a method for manufacturing a semiconductor device, which is different from those described in Embodiments 1 and 2, will be described with reference to FIGS. 9A and 9B, FIGS. 10A to 10D, FIGS. 11A to 11D, and FIGS. 12A to 12C. Note that portions similar to those in FIGS. 1A and 1B, FIGS. 2A to 2E, FIGS. 3A to 3E, FIGS. 4A to 4D, FIGS. 5A and 5B, FIGS. 6A to 6E, FIGS. 7A to 7E, and FIGS. 8A to 8D are denoted by the same reference numerals, and description thereof is skipped.
<Structure Example 3 of Semiconductor Device>
FIGS. 9A and 9B are a plan view and a cross-sectional view of a top-gate self-aligned transistor as an example of a semiconductor device. FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along line X3-Y3 in FIG. 9A. Note that in FIG. 9A, some components of the transistor (e.g., the gate insulating film 108) are not illustrated for simplification.
The semiconductor device illustrated in FIGS. 9A and 9B includes the substrate 102, the oxide film 104 formed over the substrate 102, the source electrode 120a and the drain electrode 120b formed over the oxide film 104, the oxide semiconductor film 106 which is formed over the oxide film 104, the source electrode 120a, and the drain electrode 120b and includes the channel formation region 106a and the low-resistance regions 106c having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, the sidewall insulating films 112 which are formed over the gate insulating film 108 and formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction, and the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the gate electrode 110. The low-resistance regions 106c include at least a metal element included in the metal oxide insulating films 114. Further, the interlayer insulating film 118 may be formed over the protective insulating film 116.
The source electrode 120a and the drain electrode 120b are electrically connected to the low-resistance regions 106c. 
Note that as illustrated in FIG. 9B, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
The oxide semiconductor film 106 includes the impurity region 106b having resistance different from that of the low-resistance regions 106c between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c and the impurity regions 106b can be formed in a self-aligned manner. Specifically, after the oxide semiconductor film 106 including the channel formation region 106a is formed, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106. Then, dopant is selectively introduced into the oxide semiconductor film 106 through the gate insulating film 108 with the use of the gate electrode 110 as a mask, so that the impurity regions 106b are formed. After that, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. Then, part of the gate insulating film 108 is removed with the use of the gate electrode 110 and the sidewall insulating films 112 as masks; thus, a surface of the oxide semiconductor film 106 is exposed. After that, a metal film is formed in contact with part of the oxide semiconductor film and heat treatment is performed in the state where the oxide semiconductor film 106 is in contact with the metal film so that a metal element is introduced into the oxide semiconductor film 106 from the metal film; thus, the low-resistance regions 106c including the metal element can be formed. Further, the metal film which is in contact with the oxide semiconductor film 106 is selectively oxidized by the heat treatment, whereby the metal oxide insulating films 114 are formed. The metal film is removed.
With such a structure, the low-resistance regions 106c and the impurity regions 106b are formed in the oxide semiconductor film 106 in a self-aligned manner, and the metal oxide insulating films 114 are formed over the low-resistance regions 106c. The metal oxide insulating films 114 can effectively prevent entry of an impurity to the oxide semiconductor film 106 or release of oxygen included in the oxide film 104 and the oxide semiconductor film 106. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed.
Further, in the oxide semiconductor film 106, the impurity region 106b having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at high concentration. The impurity regions 106b are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at low concentration. With such a structure, a potential difference between the source and the drain, which is associated with the channel formation region 106a, can be reduced, and the semiconductor device can be highly reliable.
The structure of the semiconductor device described in this embodiment is different from that of the semiconductor device described in Embodiment 1 in that the source electrode 120a and the drain electrode 120b are formed under the oxide semiconductor film 106 (specifically, under the low-resistance regions 106c).
Note that components that can be used for the semiconductor device in this embodiment can be similar to those in Embodiments 1 and 2; therefore, detailed description thereof is omitted.
Note that the details of other components are described in <Method 3 for Manufacturing Semiconductor Device> below, with reference to FIGS. 10A to 10D, FIGS. 11A to 11D, and FIGS. 12A to 12C.
<Method 3 for Manufacturing Semiconductor Device>
An example of a method for manufacturing the semiconductor device illustrated in FIGS. 9A and 9B of this embodiment will be described below with reference to FIGS. 10A to 10D, FIGS. 11A to 11D, and FIGS. 12A to 12C.
First, the substrate 102 is prepared. Then, the oxide film 104 and a conductive film are formed over the substrate 102. A resist mask is formed over the conductive film and the conductive film is selectively etched, so that the source electrode 120a and the drain electrode 120b are formed. After that, the oxide semiconductor film 106 including a channel formation region is formed over the oxide film 104, the source electrode 120a, and the drain electrode 120b (see FIG. 10A).
Next, the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b) and the conductive film 109 are formed over the oxide semiconductor film 106, the source electrode 120a, and the drain electrode 120b (see FIG. 10B).
Next, a resist mask is formed over the conductive film 109 through a photolithography step, selective etching is performed to form the gate electrode 110, and then the resist mask is removed. Thus, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106 (see FIG. 10C).
Next, with the use of the gate electrode 110 as a mask, the dopant 142 is selectively introduced into the oxide semiconductor film 106 through the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b). In the introduction of the dopant 142, the gate electrode 110 serves as a mask, so that the channel formation region 106a is formed in a region of the oxide semiconductor film 106, which overlaps with the gate electrode 110, and the impurity regions 106b are formed in regions into which the dopant 142 is introduced (see FIG. 10D).
The dopant 142 is an impurity that changes the conductivity of the oxide semiconductor film 106. One or more selected from the following can be used as the dopant 142: Group 15 elements (typical examples thereof are nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).
The dopant 142 can be introduced into the oxide semiconductor film 106 through another film (e.g., the gate insulating film 108) by an implantation method. As the method for introducing the dopant 142, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In that case, it is preferable to use a single ion of the dopant 142, or a fluoride ion or chloride ion thereof.
The introduction of the dopant 142 may be controlled by setting as appropriate the implantation conditions such as the acceleration voltage and the dosage, or the thickness of the film through which the dopant passes. In this embodiment, phosphorus is used as the dopant 142, whose ion is implanted by an ion implantation method. Note that the dosage of the dopant 142 may be greater than or equal to 1×1013 ions/cm2 and less than or equal to 5×1016 ions/cm2.
The concentration of the dopant 142 in the impurity regions 106b is preferably higher than or equal to 5×1018/cm3 and lower than or equal to 1×1022/cm3.
The dopant 142 may be introduced with the substrate 102 heated.
The introduction of the dopant 142 into the oxide semiconductor film 106 may be performed plural times, and the number of kinds of dopant may be plural.
In the case where the oxide semiconductor film 106 is formed using an oxide semiconductor having crystallinity (e.g., a CAAC-OS), the impurity regions 106b preferably become an amorphous oxide semiconductor by the introduction of the dopant 142. In other words, the channel formation region 106a is an oxide semiconductor film having crystallinity, and the impurity regions 106b are an amorphous oxide semiconductor. In a cross section taken along the channel length direction, the oxide semiconductor film 106 including adjacent regions having different crystal structures in the lateral direction is formed. With such a structure, oxygen deficiency or hydrogen which is an impurity in the channel formation region 106a is extracted to the impurity regions 106b which is an amorphous oxide semiconductor, so that the channel formation region 106a can be further purified.
Next, the insulating film 111 is formed over the gate insulating film 108 (specifically, over the second gate insulating film 108b) and the gate electrode 110 (see FIG. 11A).
Then, the insulating film 111 is etched, so that the sidewall insulating films 112 are formed. Thus, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction (see FIG. 11B).
The sidewall insulating films 112 can be formed in a self-aligned manner by performing a highly anisotropic etching step on the insulating film 111. As an example of an etching method, a dry etching method is preferably employed. As an etching gas used for dry etching, for example, a gas including fluorine such as trifluoromethane, octafluorocyclobutane, or tetrafluoromethane can be used. A rare gas or hydrogen may be added to the etching gas. As the dry etching method, a reactive ion etching (RIE) method in which high-frequency voltage is applied to a substrate is preferably used.
Note that the sidewall insulating films 112 may be formed in such a manner that a resist mask is formed over the insulating film 111 and etching is performed.
Next, after the formation of the sidewall insulating films 112, part of the gate insulating film 108 is removed with the use of the gate electrode 110 and the sidewall insulating films 112 as masks, so that the surface of the oxide semiconductor film 106 (specifically, part of the impurity regions 106b) is exposed (see FIG. 11C).
Note that the gate insulating film 108 may be processed in the formation of the sidewall insulating films 112.
Next, the metal film 113 is formed over the oxide semiconductor film 106, the gate electrode 110, the sidewall insulating films 112, the source electrode 120a, and the drain electrode 120b. Thus, the metal film 113 is formed in contact with part of the oxide semiconductor film 106 (see FIG. 11D).
A metal material selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc can be used for the metal film 113. In this embodiment, an aluminum film with a thickness of 10 nm is formed by a sputtering method.
Next, heat treatment is performed in the state where the metal film 113 and the oxide semiconductor film 106 (specifically, the part of the impurity regions 106b) are in contact with each other, so that the metal element is introduced from the metal film 113 and the low-resistance regions 106c including the metal element are formed. Further, oxygen is diffused into the metal film 113 from the oxide semiconductor film 106 by the heat treatment, so that the metal film 113 is selectively oxidized. Thus, the metal oxide insulating films 113a are formed. Note that in the oxide semiconductor film 106, the channel formation region 106a is formed under the gate electrode 110, the impurity regions 106b are formed under the sidewall insulating films 112, and the low-resistance regions 106c are formed in contact with the metal oxide insulating films 113a (see FIG. 12A).
The heat treatment is preferably performed at a temperature higher than or equal to 300° C. and lower than or equal to 700° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C. under an inert gas atmosphere or reduced pressure. The inert gas atmosphere is preferably an atmosphere which contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like. The heat treatment is preferably performed in an atmosphere in which the surface of the metal film 113 is not oxidized by the heat treatment. Further, the heating time can be set as appropriate by a practitioner such that the oxide semiconductor film 106 and the metal film 113 can react with each other.
By such heat treatment, oxidation of the metal film 113 does not proceed from its surface but proceeds from a portion in contact with the oxide semiconductor film 106. Therefore, the metal oxide insulating films 113a can be formed in regions in contact with the oxide semiconductor film 106 and the metal film 113 remains in another region.
Next, the metal film 113 is removed. Thus, the metal oxide insulating films 114 are formed (see FIG. 12B).
For example, in the case where aluminum is used for the metal film, the metal film 113 can be removed by a wet etching method using an etchant such as HCl, H2SO4, H3PO4, or H2C2O4. However, the method for removing the metal film 113 is not limited thereto. Depending on the materials of the metal film 113 and the metal oxide insulating films 114, a practitioner can select an etchant or an etching method as appropriate as long as etching selectivity is ensured.
Next, the protective insulating film 116 and the interlayer insulating film 118 are formed to cover the gate electrode 110, the sidewall insulating films 112, the metal oxide insulating films 114, the source electrode 120a, and the drain electrode 120b (see FIG. 12C).
Through the above manufacturing steps, the semiconductor device shown in FIGS. 9A and 9B can be manufactured.
As described in this embodiment, one of the technical ideas of the present invention is as follows. By reaction between an oxide semiconductor film and a metal film, low-resistance regions are formed in the oxide semiconductor film including a channel formation region in a self-aligned manner and part of the metal film is oxidized to form metal oxide insulating films for covering the low-resistance regions. Then, another part of the metal film, which is not oxidized, is removed. Thus, the metal oxide insulating films can prevent release of oxygen contained in an oxide film and the oxide semiconductor film. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed. Accordingly, oxygen can be favorably supplied to the oxide semiconductor film including the channel formation region from the oxide film, and a transistor with stable electric characteristics can be provided.
The method and structure described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 4
In this embodiment, a modification example of the semiconductor devices described in Embodiments 1 to 3, and a method for manufacturing a semiconductor device, which is different from those described in Embodiments 1 to 3, will be described with reference to FIGS. 13A and 13B, FIGS. 14A to 14D, FIGS. 15A to 15D, and FIGS. 16A to 16C. Note that portions similar to those in FIGS. 1A and 1B, FIGS. 2A to 2E, FIGS. 3A to 3E, FIGS. 4A to 4D, FIGS. 5A and 5B, FIGS. 6A to 6E, FIGS. 7A to 7E, FIGS. 8A to 8D, FIGS. 9A and 9B, FIGS. 10A to 10D, FIGS. 11A to 11D, and FIGS. 12A to 12C are denoted by the same reference numerals, and description thereof is skipped. In addition, detailed description of the same portions is not repeated, either.
<Structure Example 4 of Semiconductor Device>
FIGS. 13A and 13B are a plan view and a cross-sectional view of a top-gate self-aligned transistor as an example of a semiconductor device. FIG. 13A is a plan view and FIG. 13B is a cross-sectional view taken along line X4-Y4 in FIG. 13A. Note that in FIG. 13A, some components of the transistor (e.g., the gate insulating film 108) are not illustrated for simplification.
The semiconductor device illustrated in FIGS. 13A and 13B includes the substrate 102, the oxide film 104 formed over the substrate 102, the source electrode 120a and the drain electrode 120b formed over the oxide film 104, the oxide semiconductor film 106 which is formed over the oxide film 104, the source electrode 120a, and the drain electrode 120b and includes the channel formation region 106a and the low-resistance regions 106c and the low-resistance regions 106d having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c and the low-resistance regions 106d, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, the sidewall insulating films 112 which are formed over the metal oxide insulating films 114 and formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction, and the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the gate electrode 110. The low-resistance regions 106c and the low-resistance regions 106d include at least a metal element included in the metal oxide insulating films 114. Further, the interlayer insulating film 118 may be formed over the protective insulating film 116.
The source electrode 120a and the drain electrode 120b are electrically connected to the low-resistance regions 106c. 
Note that as illustrated in FIG. 13B, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
The oxide semiconductor film 106 includes the channel formation region 106a, the low-resistance regions 106c, and the low-resistance regions 106d. The low-resistance regions 106c and the low-resistance regions 106d can be formed in a self-aligned manner. Specifically, after the oxide semiconductor film 106 including the channel formation region 106a is formed, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106. Then, part of the gate insulating film 108 is removed with the use of the gate electrode 110 as a mask; thus, a surface of the oxide semiconductor film 106 is exposed. After that, a metal film is formed in contact with part of the oxide semiconductor film 106 and heat treatment is performed in the state where the oxide semiconductor film 106 is in contact with the metal film so that a metal element is introduced into the oxide semiconductor film 106 from the metal film; thus, the low-resistance regions 106d including the metal element are formed. Further, the metal film which is in contact with the oxide film 104 and the oxide semiconductor film 106 is selectively oxidized by the heat treatment, whereby the metal oxide insulating films 114 are formed. The metal film is removed. After that, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. Then, dopant is selectively introduced into the oxide semiconductor film 106 through the metal oxide insulating films 114 with the use of the gate electrode 110 and the sidewall insulating films 112 as masks, so that the low-resistance regions 106c are formed.
With such a structure, the low-resistance regions 106c and the low-resistance regions 106d are formed in the oxide semiconductor film 106 in a self-aligned manner, and the metal oxide insulating films 114 are formed over the low-resistance regions 106c and the low-resistance regions 106d. The metal oxide insulating films 114 can effectively prevent entry of an impurity to the oxide semiconductor film 106 or release of oxygen included in the oxide film 104 and the oxide semiconductor film 106. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed.
Further, in the oxide semiconductor film 106, the low-resistance region 106d having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at high concentration. The low-resistance regions 106d are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at low concentration. With such a structure, a potential difference between the source and the drain, which is associated with the channel formation region 106a, can be reduced, and the semiconductor device can be highly reliable.
The structure of the semiconductor device described in this embodiment is different from that of the semiconductor device described in Embodiment 1 in that the source electrode 120a and the drain electrode 120b are formed under the oxide semiconductor film 106 (specifically, under the low-resistance regions 106c) and that the low-resistance region 106d having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. Further, the shapes of the gate insulating film 108, the metal oxide insulating films 114, and the sidewall insulating films 112 in this embodiment are different from those in Embodiment 1.
Note that components that can be used for the semiconductor device in this embodiment can be similar to those in Embodiments 1 to 3; therefore, detailed description thereof is omitted.
Note that the details of other components are described in <Method 4 for Manufacturing Semiconductor Device> below, with reference to FIGS. 14A to 14D, FIGS. 15A to 15D, and FIGS. 16A to 16C.
<Method 4 for Manufacturing Semiconductor Device>
An example of a method for manufacturing the semiconductor device illustrated in FIGS. 13A and 13B of this embodiment will be described below with reference to FIGS. 14A to 14D, FIGS. 15A to 15D, and FIGS. 16A to 16C.
First, the substrate 102 is prepared. Then, the oxide film 104 and a conductive film are formed over the substrate 102. A resist mask is formed over the conductive film and the conductive film is selectively etched, so that the source electrode 120a and the drain electrode 120b are formed. After that, the oxide semiconductor film 106 including the channel formation region is formed over the oxide film 104, the source electrode 120a, and the drain electrode 120b (see FIG. 14A).
Next, the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b) and the conductive film 109 are formed over the oxide semiconductor film 106, the source electrode 120a, and the drain electrode 120b (see FIG. 14B).
Next, a resist mask is formed over the conductive film 109 through a photolithography step, selective etching is performed to form the gate electrode 110, and then the resist mask is removed. Thus, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106 (see FIG. 14C).
Next, part of the gate insulating film 108 is removed with the use of the gate electrode 110 as a mask, so that the surface of the oxide semiconductor film 106 is exposed (see FIG. 14D).
Note that the gate insulating film 108 may be processed in the formation of the gate electrode 110.
Next, the metal film 113 is formed over the oxide semiconductor film 106, the gate electrode 110, the source electrode 120a, and the drain electrode 120b. Thus, the metal film 113 is formed in contact with part of the oxide semiconductor film 106 (see FIG. 15A).
A metal material selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc can be used for the metal film 113. In this embodiment, an aluminum film with a thickness of 10 nm is formed by a sputtering method.
Next, heat treatment is performed in the state where the metal film 113 and the oxide semiconductor film 106 are in contact with each other, so that the metal element is introduced from the metal film 113. Thus, the low-resistance regions 106d including the metal element are formed and the channel formation region 106a is formed under the gate electrode 110. Further, oxygen is diffused into the metal film 113 from the oxide semiconductor film 106 by the heat treatment, so that the metal film 113 is selectively oxidized. Thus, the metal oxide insulating films 113a are formed (see FIG. 15B).
The heat treatment is preferably performed at a temperature higher than or equal to 300° C. and lower than or equal to 700° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C. under an inert gas atmosphere or reduced pressure. The inert gas atmosphere is preferably an atmosphere which contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like. The heat treatment is preferably performed in an atmosphere in which the surface of the metal film 113 is not oxidized by the heat treatment. Further, the heating time can be set as appropriate by a practitioner such that the oxide semiconductor film 106 and the metal film 113 can react with each other.
By such heat treatment, oxidation of the metal film 113 does not proceed from its surface but proceeds from a portion in contact with the oxide semiconductor film 106. Therefore, the metal oxide insulating films 113a can be formed in regions in contact with the oxide semiconductor film 106 and the metal film 113 remains in another region.
Next, the metal film 113 is removed. Thus, the metal oxide insulating films 114 are formed (see FIG. 15C).
For example, in the case where aluminum is used for the metal film, the metal film 113 can be removed by a wet etching method using an etchant such as HCl, H2SO4, H3PO4, or H2C2O4. However, the method for removing the metal film 113 is not limited thereto. Depending on the materials of the metal film 113 and the metal oxide insulating films 114, a practitioner can select an etchant or an etching method as appropriate as long as etching selectivity is ensured.
Next, the insulating film 111 is formed over the metal oxide insulating films 114 and the gate electrode 110 (see FIG. 15D).
Then, the insulating film 111 is etched, so that the sidewall insulating films 112 are formed. Thus, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction (see FIG. 16A).
The sidewall insulating films 112 can be formed in a self-aligned manner by performing a highly anisotropic etching step on the insulating film 111. In addition to the materials mentioned in [Detailed Description of Sidewall Insulating Film] in Embodiment 1, an oxide film formed of silicon oxide, silicon oxynitride, or the like can be used as the sidewall insulating films 112.
Note that the sidewall insulating films 112 may be formed in such a manner that a resist mask is formed over the insulating film 111 and etching is performed.
Next, the dopant 142 is selectively introduced into the oxide semiconductor film 106 through the metal oxide insulating films 114 with the use of the gate electrode 110 and the sidewall insulating films 112 as masks. In the oxide semiconductor film 106, the channel formation region 106a is formed under the gate electrode 110, the low resistance regions 106d are formed under the sidewall insulating films 112, and the low-resistance regions 106c are formed in contact with the metal oxide insulating films 114 (see FIG. 16B).
The dopant 142 is an impurity that changes the conductivity of the oxide semiconductor film 106. One or more selected from the following can be used as the dopant 142: Group 15 elements (typical examples thereof are nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).
The dopant 142 can be introduced into the oxide semiconductor film 106 through another film (e.g., the metal oxide insulating films 114) by an implantation method. As the method for introducing the dopant 142, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In that case, it is preferable to use a single ion of the dopant 142, or a fluoride ion or chloride ion thereof.
The introduction of the dopant 142 may be controlled by setting as appropriate the implantation conditions such as the acceleration voltage and the dosage, or the thickness of the film through which the dopant passes. In this embodiment, phosphorus is used as the dopant 142, whose ion is implanted by an ion implantation method. Note that the dosage of the dopant 142 may be greater than or equal to 1×1013 ions/cm2 and less than or equal to 5×1016 ions/cm2.
The dopant 142 may be introduced with the substrate 102 heated.
The introduction of the dopant 142 into the oxide semiconductor film 106 may be performed plural times, and the number of kinds of dopant may be plural.
Although the case where the dopant 142 is introduced is described in this embodiment, the present invention is not limited thereto. It is possible that the dopant 142 is not introduced so that the oxide semiconductor film 106 includes the low-resistance regions 106d and does not include the low-resistance regions 106c. 
Next, the protective insulating film 116 and the interlayer insulating film 118 are formed to cover the gate electrode 110, the sidewall insulating films 112, the metal oxide insulating films 114, the source electrode 120a, and the drain electrode 120b (see FIG. 16C).
Through the above manufacturing steps, the semiconductor device shown in FIGS. 13A and 13B can be manufactured.
As described in this embodiment, one of the technical ideas of the present invention is as follows. By reaction between an oxide semiconductor film and a metal film, low-resistance regions are formed in the oxide semiconductor film including a channel formation region in a self-aligned manner and part of the metal film is oxidized to form metal oxide insulating films for covering the low-resistance regions. Then, another part of the metal film, which is not oxidized, is removed. Thus, the metal oxide insulating films can prevent release of oxygen contained in an oxide film and the oxide semiconductor film. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed. Accordingly, oxygen can be favorably supplied to the oxide semiconductor film including the channel formation region from the oxide film, and a transistor with stable electric characteristics can be provided.
The method and structure described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 5
In this embodiment, modification examples of the semiconductor devices described in Embodiments 1 to 4 will be described with reference to FIGS. 17A and 17B and FIGS. 18A and 18B. Note that portions similar to those in FIGS. 1A and 1B, FIGS. 2A to 2E, FIGS. 3A to 3E, FIGS. 4A to 4D, FIGS. 5A and 5B, FIGS. 6A to 6E, FIGS. 7A to 7E, FIGS. 8A to 8D, FIGS. 9A and 9B, FIGS. 10A to 10D, FIGS. 11A to 11D, FIGS. 12A to 12C, FIGS. 13A and 13B, FIGS. 14A to 14D, FIGS. 15A to 15D, and FIGS. 16A to 16C are denoted by the same reference numerals, and description thereof is skipped.
First, a structure of a semiconductor device, which is different from that of the semiconductor device described in Embodiment 1, will be described below with reference to FIGS. 17A and 17B.
<Structure Example 5 of Semiconductor Device>
FIGS. 17A and 17B are a plan view and a cross-sectional view of a top-gate self-aligned transistor as an example of a semiconductor device. FIG. 17A is a plan view and FIG. 17B is a cross-sectional view taken along line X5-Y5 in FIG. 17A. Note that in FIG. 17A, some components of the transistor (e.g., the gate insulating film 108) are not illustrated for simplification.
The semiconductor device illustrated in FIGS. 17A and 17B includes the substrate 102, the oxide film 104 formed over the substrate 102, the oxide semiconductor film 106 which is formed over the oxide film 104 and includes the channel formation region 106a and the low-resistance regions 106c having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, and the sidewall insulating film 112 which is formed over the gate insulating film 108 and formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. The low-resistance regions 106c include at least a metal element included in the metal oxide insulating films 114.
In addition, the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating film 112, and the gate electrode 110, the interlayer insulating film 118 formed over the protective insulating film 116, and the source electrode 120a and the drain electrode 120b electrically connected to the low-resistance regions 106c may be included.
Note that as illustrated in FIG. 17B, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
The oxide semiconductor film 106 includes the impurity region 106b having resistance different from that of the low-resistance regions 106c between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c and the impurity regions 106b can be formed in a self-aligned manner. Specifically, after the oxide semiconductor film 106 including the channel formation region 106a is formed, a stack of the gate insulating film 108 and the gate electrode 110 is formed over the oxide semiconductor film 106. Then, dopant is selectively introduced into the oxide semiconductor film 106 through the gate insulating film 108 with the use of the gate electrode 110 as a mask, so that the impurity regions 106b are formed. After that, the sidewall insulating film 112 is formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction. Then, part of the gate insulating film 108 is removed with the use of the gate electrode 110 and the sidewall insulating film 112 as masks; thus, a surface of the oxide semiconductor film 106 is exposed. After that, a metal film is formed in contact with part of the oxide semiconductor film and heat treatment is performed in the state where the oxide semiconductor film 106 is in contact with the metal film so that a metal element is introduced into the oxide semiconductor film 106 from the metal film; thus, the low-resistance regions 106c including the metal element can be formed. Further, the metal film which is in contact with the oxide film 104 and the oxide semiconductor film 106 is selectively oxidized by the heat treatment, whereby the metal oxide insulating films 114 are formed. The metal film is removed.
With such a structure, the low-resistance regions 106c and the impurity regions 106b are formed in the oxide semiconductor film 106 in a self-aligned manner, and the metal oxide insulating films 114 are formed over the low-resistance regions 106c. The metal oxide insulating films 114 can effectively prevent entry of an impurity to the oxide semiconductor film 106 or release of oxygen included in the oxide film 104 and the oxide semiconductor film 106. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed.
Further, in the oxide semiconductor film 106, the impurity region 106b having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at high concentration. The impurity regions 106b are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at low concentration. With such a structure, a potential difference between the source and the drain which are associated with the channel formation region 106a can be reduced, and the semiconductor device can be highly reliable.
The shapes of the gate electrode 110 and the sidewall insulating film 112 of the semiconductor device in this embodiment are different from those of the semiconductor device in Embodiment 1.
Note that components that can be used for the semiconductor device in this embodiment can be similar to that in Embodiment 1; therefore, components that are different from the components in Embodiment 1 will be described below.
The gate electrode 110 can be formed using a resist mask which is formed by a photolithography method or the like and subjected to a slimming process to have a finer pattern. As the slimming process, an ashing process in which oxygen in a radical state (oxygen radical) or the like is used can be employed, for example. Note that Embodiment 2 and Embodiment 4 can be referred to for the method for forming the impurity regions 106b. 
The sidewall insulating film 112 can be formed by etching with the use of a resist mask formed by a photolithography method or the like. The sidewall insulating film 112 needs to be formed in contact with at least the side surfaces of the gate electrode 110, and a structure in which an upper surface of the gate electrode 110 is covered with the sidewall insulating film 112, which is illustrated in FIG. 17B, is also an allowable structure of the sidewall insulating film 112.
As in the semiconductor device illustrated in FIGS. 17A and 17B, the gate electrode 110 is preferably reduced in size because a transistor can be miniaturized. Further, it is more preferable that contact regions of the low-resistance regions 106c and the source and drain electrodes 120a and 120b be made closer to the gate electrode 110 in accordance with reduction of the gate electrode 110 in size as appropriate.
Next, a structure of a semiconductor device, which is different from that of the semiconductor device described in Embodiment 1, will be described below with reference to FIGS. 18A and 18B.
<Structure Example 6 of Semiconductor Device>
FIGS. 18A and 18B are a plan view and a cross-sectional view of a top-gate self-aligned transistor as an example of a semiconductor device. FIG. 18A is a plan view and FIG. 18B is a cross-sectional view taken along line X6-Y6 in FIG. 18A. Note that in FIG. 18A, some components of the transistor (e.g., the gate insulating film 108) are not illustrated for simplification.
The semiconductor device illustrated in FIGS. 18A and 18B includes the substrate 102, the oxide film 104 formed over the substrate 102, the oxide semiconductor film 106 which is formed over the oxide film 104 and includes the channel formation region 106a and the low-resistance regions 106c having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, an insulating film 122 formed over the gate electrode 110, and the sidewall insulating films 112 which are formed over the gate insulating film 108 and formed on side surfaces of the gate electrode 110 and the insulating film 122 in a cross section taken along the channel length direction. The low-resistance regions 106c include at least a metal element included in the metal oxide insulating films 114.
In addition, the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the insulating film 122, the interlayer insulating film 118 formed over the protective insulating film 116, and the source electrode 120a and the drain electrode 120b electrically connected to the low-resistance regions 106c may be included.
Note that as illustrated in FIG. 18B, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
The oxide semiconductor film 106 includes the impurity region 106b having resistance different from that of the low-resistance regions 106c between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c and the impurity regions 106b can be formed in a self-aligned manner. Specifically, after the oxide semiconductor film 106 including the channel formation region 106a is formed, a stack of the gate insulating film 108, the gate electrode 110, and the insulating film 122 is formed over the oxide semiconductor film 106. Then, dopant is selectively introduced into the oxide semiconductor film 106 through the gate insulating film 108 with the use of the gate electrode 110 and the insulating film 122 as masks, so that the impurity regions 106b are formed. After that, the sidewall insulating films 112 are formed on the side surfaces of the gate electrode 110 and the insulating film 122 in a cross section taken along the channel length direction. Then, part of the gate insulating film 108 is removed with the use of the gate electrode 110, the insulating film 122, and the sidewall insulating films 112 as masks; thus, a surface of the oxide semiconductor film 106 is exposed. After that, a metal film is formed in contact with part of the oxide semiconductor film and heat treatment is performed in the state where the oxide semiconductor film 106 is in contact with the metal film so that a metal element is introduced into the oxide semiconductor film 106 from the metal film; thus, the low-resistance regions 106c including the metal element can be formed. Further, the metal film which is in contact with the oxide film 104 and the oxide semiconductor film 106 is selectively oxidized by the heat treatment, whereby the metal oxide insulating films 114 are formed. The metal film is removed.
With such a structure, the low-resistance regions 106c and the impurity regions 106b are formed in the oxide semiconductor film 106 in a self-aligned manner, and the metal oxide insulating films 114 are formed over the low-resistance regions 106c. The metal oxide insulating films 114 can effectively prevent entry of an impurity to the oxide semiconductor film 106 or release of oxygen included in the oxide film 104 and the oxide semiconductor film 106. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed.
Further, in the oxide semiconductor film 106, the impurity region 106b having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. The low-resistance regions 106c are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at high concentration. The impurity regions 106b are, in other words, regions into which an impurity imparting n-type conductivity to the oxide semiconductor film 106 is introduced at low concentration. With such a structure, a potential difference between the source and the drain which are associated with the channel formation region 106a can be reduced, and the semiconductor device can be highly reliable.
The structure of the semiconductor device described in this embodiment is different from that of the semiconductor device described in Embodiment 1 in that the insulating film 122 is formed over the gate electrode 110. Further, the shapes of the sidewall insulating films 112 in this embodiment are different from those in Embodiment 1.
Note that components that can be used for the semiconductor device in this embodiment can be similar to that in Embodiment 1; therefore, a component that is different from the components in Embodiment 1 will be described below.
[Detailed Description of Insulating Film]
The insulating film 122 is preferably formed using a material which does not react with the metal film to be formed later by heat treatment. For example, a single layer or a stacked layer using any of nitrides such as silicon nitride, aluminum nitride, and gallium nitride can be used. There is no particular limitation on a method for forming the insulating film 122, and a variety of film formation methods such as an evaporation method, a PE-CVD method, a sputtering method, and a spin coating method can be used.
In the formation of the metal oxide insulating films 114, the insulating film 122 can prevent the gate electrode 110 from being directly exposed to an etching gas, an etchant, or the like when the metal film is removed. Note that Embodiment 2 and Embodiment 4 can be referred to for the formation method of the impurity regions 106b. 
As described in this embodiment, one of the technical ideas of the present invention is as follows. By reaction between an oxide semiconductor film and a metal film, low-resistance regions are formed in the oxide semiconductor film including a channel formation region in a self-aligned manner and part of the metal film is oxidized to form metal oxide insulating films for covering the low-resistance regions. Then, another part of the metal film, which is not oxidized, is removed. Thus, the metal oxide insulating films can prevent release of oxygen contained in an oxide film and the oxide semiconductor film. Further, since the metal film is removed, unnecessary capacitance due to the metal film is not formed. Accordingly, oxygen can be favorably supplied to the oxide semiconductor film including the channel formation region from the oxide film, and a transistor with stable electric characteristics can be provided.
The methods and structures described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 6
In this embodiment, an example of a structure which includes the semiconductor device described in this specification, can hold stored data even when not powered, and does not have a limitation on the number of write cycles will be described with reference to drawings.
FIGS. 19A to 19C illustrate an example of a structure of the semiconductor device. FIGS. 19A to 19C illustrate a cross-sectional view, a plan view, and a circuit diagram, respectively, of the semiconductor device. Here, FIG. 19A corresponds to a cross section along line C1-C2 and line D1-D2 in FIG. 19B.
The semiconductor device illustrated in FIGS. 19A and 19B includes a transistor 260 including a first semiconductor material in a lower portion, and a transistor 300 including a second semiconductor material in an upper portion. As the transistor 300 including the second semiconductor material, the semiconductor device described in Embodiment 3 can be employed. Note that any of the semiconductor devices described in the other embodiments can also be employed.
Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (e.g., silicon) and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor, such as single crystal silicon, can operate at high speed easily. On the other hand, a transistor including an oxide semiconductor enables charge to be held for a long time owing to its characteristics.
Although all the transistors are n-channel transistors here, it is needless to say that p-channel transistors can be used.
The transistor 260 illustrated in FIG. 19A includes a channel formation region 216 provided in a substrate 200 including a semiconductor material (a single crystal semiconductor substrate in this embodiment), impurity regions 220 with the channel formation region 216 provided therebetween, intermetallic compound regions 224 in contact with the impurity regions 220, a gate insulating film 208 provided over the channel formation region 216, and a gate electrode 210 provided over the gate insulating film 208. Note that a transistor whose source electrode and drain electrode are not illustrated in a drawing may be referred to as a transistor for the sake of convenience. Further, in such a case, in description of a connection of a transistor, a source region and a source electrode are collectively referred to as a “source electrode”, and a drain region and a drain electrode are collectively referred to as a “drain electrode”. That is, in this specification, the term “source electrode” may include a source region.
An element isolation insulating film 206 is provided over the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an insulating film 230 are provided to cover the transistor 260. Note that for high integration, it is preferable that, as illustrated in FIG. 19A, the transistor 260 do not have a sidewall insulating film. On the other hand, when the characteristics of the transistor 260 have priority, the sidewall insulating film may be formed along a side surface of the gate electrode 210 and the impurity regions 220 may include a region having a different impurity concentration.
The transistor 260 formed using a single crystal semiconductor substrate can operate at high speed. Therefore, when the transistor is used as a reading transistor, data can be read at high speed. Insulating films are formed so as to cover the transistor 260 after the transistor 260 is formed, and then the transistor 300 can be formed. As treatment prior to formation of the transistor 300, CMP treatment is performed on the insulating films, whereby the insulating film 228 and the insulating film 230 which are planarized are formed and, at the same time, an upper surface of the gate electrode 210 is exposed.
As the insulating film 228, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be used typically. As the insulating film 230, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film can be used. The insulating film 228 and the insulating film 230 can be formed by a plasma CVD method, a sputtering method, or the like.
Alternatively, an organic material such as a polyimide-based resin, an acrylic-based resin, or a benzocyclobutene-based resin can be used for the insulating film 228. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material) or the like. In the case of using an organic material, the insulating film 228 may be formed by a wet method such as a spin coating method or a printing method.
Note that in this embodiment, a silicon nitride film is used as the insulating film 228, and a silicon oxide film is used as the insulating film 230.
The oxide semiconductor film 106, the source electrode 120a, and the drain electrode 120b are formed over the insulating film 230 which is sufficiently planarized by polishing treatment (such as CMP treatment). Note that the average plane roughness of a surface of the insulating film 230 is preferably less than or equal to 0.15 nm.
The transistor 300 illustrated in FIG. 19A includes an oxide semiconductor film in the channel formation region. Here, the oxide semiconductor film 106 included in the transistor 300 is preferably highly purified. By using a highly purified oxide semiconductor, the transistor 300 can have extremely favorable off-state current characteristics.
The transistor 300 includes the source electrode 120a and the drain electrode 120b formed over the insulating film 230, the oxide semiconductor film 106 which is formed over the insulating film 230, the source electrode 120a, and the drain electrode 120b and includes the channel formation region 106a and the low-resistance regions 106c having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, the sidewall insulating films 112 which are formed over the gate insulating film 108 and formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction, and the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the gate electrode 110. The low-resistance regions 106c include at least a metal element included in the metal oxide insulating films 114. Further, the interlayer insulating film 118 is formed over the protective insulating film 116.
The source electrode 120a and the drain electrode 120b are electrically connected to the low-resistance regions 106c. Further, in the oxide semiconductor film 106, the impurity region 106b having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. 
Note that as illustrated in FIG. 19A, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
Since the off-state current of the transistor 300 is small, stored data can be held for a long time by using this transistor. In other words, power consumption can be sufficiently reduced because a semiconductor memory device in which refresh operation is unnecessary or the frequency of refresh operation is extremely low can be provided.
Further, in a region overlapping with the source electrode 120a of the transistor 300, an insulating film 305 formed in the same step as the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b), and a conductive film 306 formed in the same step as the gate electrode 110 are formed. The source electrode 120a, the insulating film 305, and the conductive film 306 form a capacitor 364. In other words, the source electrode 120a of the transistor 300 serves as one electrode of the capacitor 364, and the conductive film 306 serves as the other electrode of the capacitor 364. Note that in the case where a capacitor is not needed, the capacitor 364 may be omitted. Alternatively, the capacitor 364 may be separately formed over the transistor 300.
Insulating films 307 formed in the same step as the sidewall insulating films 112 of the transistor 300 are provided on side surfaces of the conductive film 306.
The protective insulating film 116 and the interlayer insulating film 118 are provided over the transistor 300 and the capacitor 364, and a wiring 308 for connecting the transistor 300 to another transistor is provided over the interlayer insulating film 118. The wiring 308 is formed in an opening portion formed in the protective insulating film 116, the interlayer insulating film 118, and the like, and is electrically connected to the drain electrode 120b through the low-resistance region 106c. 
In FIGS. 19A and 19B, the transistor 260 and the transistor 300 are provided so as to at least partly overlap with each other. The source region or the drain region of the transistor 260 is preferably provided so as to overlap with part of the oxide semiconductor film 106. Further, the transistor 300 and the capacitor 364 are provided so as to overlap with at least part of the transistor 260. For example, the conductive film 306 of the capacitor 364 is provided so as to overlap with at least part of the gate electrode 210 of the transistor 260. With such a planar layout, the area occupied by the semiconductor device can be reduced; thus, higher integration can be achieved.
Next, an example of a circuit configuration corresponding to FIGS. 19A and 19B is illustrated in FIG. 19C.
In FIG. 19C, a first wiring (1st Line) is electrically connected to one of the source electrode and the drain electrode of the transistor 260, and a second wiring (2nd Line) is electrically connected to the other of the source electrode and the drain electrode of the transistor 260. A third wiring (3rd Line) is electrically connected to one of the source electrode and the drain electrode of the transistor 300, and a fourth wiring (4th Line) is electrically connected to a gate electrode of the transistor 300. The gate electrode of the transistor 260 and the other of the source electrode and the drain electrode of the transistor 300 are electrically connected to one electrode of the capacitor 364. A fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 364.
The semiconductor device having the circuit configuration in FIG. 19C utilizes a characteristic in which the potential of the gate electrode of the transistor 260 can be held, and can thus write, hold, and read data as follows.
Writing and holding of data will be described. The potential of the fourth wiring is set to a potential at which the transistor 300 is turned on, whereby the transistor 300 is turned on. Thus, the potential of the third wiring is supplied to the gate electrode of the transistor 260 and the capacitor 364. In other words, a predetermined charge is supplied to the gate electrode of the transistor 260 (i.e., writing of data). Here, charge for supply of a potential level or charge for supply of a different potential level (hereinafter referred to as Low level charge and High level charge) is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 300 is turned off, so that the transistor 300 is turned off. Thus, the charge given to the gate electrode of the transistor 260 is held (holding).
Since the off-state current of the transistor 300 is extremely small, the charge of the gate electrode of the transistor 260 is held for a long time.
Next, reading of data is described. By supplying an appropriate potential (reading potential) to the fifth wiring while a predetermined potential (constant potential) is supplied to the first wiring, the potential of the second wiring varies depending on the amount of charge held in the gate electrode of the transistor 260. This is because in general, when the transistor 260 is an n-channel transistor, an apparent threshold voltage Vth_H in the case where High level charge is given to the gate electrode of the transistor 260 is lower than an apparent threshold voltage Vth_L in the case where Low level charge is given to the gate electrode of the transistor 260. Here, an apparent threshold voltage refers to the potential of the fifth wiring, which is needed to turn on the transistor 260. Thus, the potential of the fifth wiring is set to a potential V0 existing between Vth_H and Vth_L, whereby charge given to the gate electrode of the transistor 260 can be determined. For example, in the case where High level charge is given in writing, when the potential of the fifth wiring is set to V0 (>Vth_H), the transistor 260 is turned on. In the case where Low level charge is given in writing, even when the potential of the fifth wiring is set to V0 (<Vth_L), the transistor 260 remains in an off state. Therefore, the stored data can be read by the potential of the second wiring.
Note that in the case where memory cells are arrayed to be used, only data of desired memory cells needs to be read. In the case where data is not read, a potential at which the transistor 260 is turned off regardless of the state of the gate electrode, that is, a potential lower than Vth_H may be supplied to the fifth wiring. Alternatively, a potential at which the transistor 260 is turned on regardless of the state of the gate electrode, that is, a potential higher than Vth_L may be supplied to the fifth wiring.
When a transistor having a channel formation region formed using an oxide semiconductor and having extremely small off-state current is used in the semiconductor device in this embodiment, the semiconductor device can store data for an extremely long time. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).
Further, in the semiconductor device in this embodiment, a high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike in a conventional non-volatile memory, it is not necessary to inject and extract electrons into and from a floating gate, and thus a problem such as deterioration of a gate insulating layer does not occur at all. In other words, the semiconductor device according to an embodiment of the present invention does not have a limit on the number of times of writing, which is a problem in a conventional non-volatile memory, and reliability thereof is drastically improved. Furthermore, data is written depending on the on state and the off state of the transistor, whereby high-speed operation can be easily achieved.
The method and structure described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 7
In this embodiment, a structure which includes the semiconductor device described in any of Embodiments 1 to 5, can hold stored data even when not powered, does not have a limitation on the number of write cycles, and is different from the structure described in Embodiment 6, is described with reference to FIGS. 20A and 20B and FIGS. 21A and 21B.
FIG. 20A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 20B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 20A will be described, and then, the semiconductor device illustrated in FIG. 20B will be described.
In the semiconductor device illustrated in FIG. 20A, a bit line BL is electrically connected to a source electrode or a drain electrode of a transistor 330, a word line WL is electrically connected to a gate electrode of the transistor 330, and the source electrode or the drain electrode of the transistor 330 is electrically connected to a first terminal of a capacitor 354.
The transistor 330 including an oxide semiconductor has extremely small off-state current. For that reason, the potential of the first terminal of the capacitor 354 (or a charge accumulated in the capacitor 354) can be held for an extremely long time by turning off the transistor 330.
Next, writing and holding of data in the semiconductor device (a memory cell 350) illustrated in FIG. 20A will be described.
First, the potential of the word line WL is set to a potential at which the transistor 330 is turned on, so that the transistor 330 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 354 (writing). After that, the potential of the word line WL is set to a potential at which the transistor 330 is turned off, so that the transistor 330 is turned off. Thus, the potential of the first terminal of the capacitor 354 is held (holding).
Because the off-state current of the transistor 330 is extremely small, the potential of the first terminal of the capacitor 354 (or the charge accumulated in the capacitor) can be held for a long time.
Secondly, reading of data will be described. When the transistor 330 is turned on, the bit line BL which is in a floating state and the capacitor 354 are electrically connected to each other, and the charge is redistributed between the bit line BL and the capacitor 354. As a result, the potential of the bit line BL is changed. The amount of change in potential of the bit line BL fluctuates depending on the potential of the first terminal of the capacitor 354 (or the charge accumulated in the capacitor 354).
For example, the potential of the bit line BL after charge redistribution is (CB×VB0+C×V)/(CB+C), where V is the potential of the first terminal of the capacitor 354, C is the capacitance of the capacitor 354, CB is the capacitance of the bit line BL (hereinafter also referred to as bit line capacitance), and VB0 is the potential of the bit line BL before the charge redistribution. Therefore, it can be found that assuming that the memory cell 350 is in either of two states in which the potentials of the first terminal of the capacitor 354 are V1 and V0 (V1>V0), the potential of the bit line BL in the case of holding the potential V1 (=(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the bit line BL in the case of holding the potential V0 (=(CB×VB0+C×V0)/(CB+C)).
By comparing the potential of the bit line BL with a predetermined potential, data can be read.
As described above, the semiconductor device illustrated in FIG. 20A can hold charge that is accumulated in the capacitor 354 for a long time because the off-state current of the transistor 330 is extremely small. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be stored for a long time even when power is not supplied.
Next, the semiconductor device illustrated in FIG. 20B will be described.
The semiconductor device illustrated in FIG. 20B includes memory cell arrays 351a and 351b including a plurality of memory cells 350 illustrated in FIG. 20A as a memory circuit in an upper portion, and a peripheral circuit 353 in a lower portion which is necessary for operation of the memory cell arrays 351a and 351b. Note that the peripheral circuit 353 is electrically connected to the memory cell arrays 351a and 351b. 
In the structure illustrated in FIG. 20B, the peripheral circuit 353 can be provided under the memory cell arrays 351a and 351b. Thus, the size of the semiconductor device can be decreased.
It is preferable that a semiconductor material of the transistor provided in the peripheral circuit 353 be different from that of the transistor 330. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. Alternatively, an organic semiconductor material or the like may be used. For example, a transistor including a single crystal semiconductor material can operate at sufficiently high speed. Therefore, a circuit (e.g., a logic circuit or a driver circuit) which needs to operate at high speed can be favorably achieved by the transistor.
Note that FIG. 20B illustrates, as an example, the semiconductor device in which two memory cell arrays of the memory cell arrays 351a and 351b are stacked; however, the number of memory cells to be stacked is not limited thereto. Three or more memory cell arrays may be stacked.
Next, a specific structure of the memory cell 350 illustrated in FIG. 20A will be described with reference to FIGS. 21A and 21B.
FIGS. 21A and 21B illustrate an example of a structure of the memory cell 350. FIG. 21A is a cross-sectional view of the memory cell 350, and FIG. 21B is a plan view of the memory cell 350. Here, FIG. 21A corresponds to a cross section taken along line F1-F2 and line G1-G2 in FIG. 21B.
The transistor 330 illustrated in FIGS. 21A and 21B can have the same structure as the transistor in Embodiment 3. Note that any of the structures of the transistors described in the other Embodiments may be employed.
The transistor 330 includes the source electrode 120a and the drain electrode 120b formed over an insulating film 274, the oxide semiconductor film 106 which is formed over the insulating film 274, the source electrode 120a, and the drain electrode 120b and includes the channel formation region 106a and the low-resistance regions 106c having resistance lower than that of the channel formation region 106a, the metal oxide insulating films 114 formed in contact with the low-resistance regions 106c, the gate insulating film 108 formed over the oxide semiconductor film 106, the gate electrode 110 which is formed in contact with the gate insulating film 108 and overlaps with the channel formation region 106a, the sidewall insulating films 112 which are formed over the gate insulating film 108 and formed on the side surfaces of the gate electrode 110 in a cross section taken along the channel length direction, and the protective insulating film 116 formed over the metal oxide insulating films 114, the sidewall insulating films 112, and the gate electrode 110. The low-resistance regions 106c include at least a metal element included in the metal oxide insulating films 114. Further, the interlayer insulating film 118 is formed over the protective insulating film 116.
The source electrode 120a and the drain electrode 120b are electrically connected to the low-resistance regions 106c. Further, in the oxide semiconductor film 106, the impurity region 106b having resistance different from that of the low-resistance regions 106c is formed between the channel formation region 106a and each of the low-resistance regions 106c. 
Note that as illustrated in FIG. 21A, the gate insulating film 108 preferably has a stacked structure of the first gate insulating film 108a and the second gate insulating film 108b. In the stacked structure of the gate insulating film 108, the first gate insulating film 108a is an oxide film containing excess oxygen and the second gate insulating film 108b is an insulating film having a blocking function, whereby oxygen can be supplied to the oxide semiconductor film 106 (particularly the channel formation region 106a), and an impurity can be prevented from entering the oxide semiconductor film 106 (particularly the channel formation region 106a) or oxygen can be prevented from being released upward from the first gate insulating film 108a. For example, a silicon oxynitride film can be used as the first gate insulating film 108a and an aluminum oxide film can be used as the second gate insulating film 108b. 
Since the off-state current of the transistor 330 is small, stored data can be held for a long time by using this transistor. In other words, power consumption can be sufficiently reduced because a semiconductor memory device in which refresh operation is unnecessary or the frequency of refresh operation is extremely low can be provided.
Further, in a region overlapping with the source electrode 120a of the transistor 330, an insulating film 335 formed in the same step as the gate insulating film 108 (the first gate insulating film 108a and the second gate insulating film 108b) and a conductive film 336 formed in the same step as the gate electrode 110 are formed. The source electrode 120a, the insulating film 335, and the conductive film 336 form a capacitor 354. In other words, the source electrode 120a of the transistor 330 serves as one electrode of the capacitor 354, and the conductive film 336 serves as the other electrode of the capacitor 354. Note that in the case where a capacitor is not needed, the capacitor 354 may be omitted. Alternatively, the capacitor 354 may be separately formed over the transistor 330.
Insulating films 337 formed in the same step as the sidewall insulating films 112 of the transistor 330 are provided on side surfaces of the conductive film 336.
The protective insulating film 116 and the interlayer insulating film 118 are provided over the transistor 330 and the capacitor 354, and a wiring 272 connected to an adjacent memory cell is provided over the interlayer insulating film 118. The wiring 272 is formed in an opening portion formed in the interlayer insulating film 118, the protective insulating film 116, and the metal oxide insulating film 114, and is electrically connected to the drain electrode 120b of the transistor 330 through the low-resistance region 106c. Note that the wiring 272 may be directly connected to the drain electrode 120b. The wiring 272 corresponds to the bit line BL in the circuit diagram in FIG. 20A.
In FIGS. 21A and 21B, the drain electrode 120b of the transistor 330 can also function as a source electrode of a transistor included in an adjacent memory cell. With such a planar layout, the area occupied by the semiconductor device can be reduced; thus, higher integration can be achieved.
As described above, the plurality of memory cells formed in multiple layers each include a transistor including an oxide semiconductor. Since the off-state current of the transistor including an oxide semiconductor is small, stored data can be held for a long time by using this transistor. In other words, the frequency of refresh operation can be extremely lowered, which leads to a sufficient reduction in power consumption.
A semiconductor device having a novel feature can be obtained by being provided with both a peripheral circuit including the transistor including a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed) and a memory circuit including the transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small). In addition, with a structure where the peripheral circuit and the memory circuit are stacked, the degree of integration of the semiconductor device can be increased.
As described above, a miniaturized and highly integrated semiconductor device having stable electric characteristics can be provided.
This embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
Embodiment 8
In this embodiment, examples of application of the semiconductor device described in any of the above embodiments to portable devices such as a mobile phone, a smartphone, and an e-book reader will be described with reference to FIGS. 22A and 22B, FIG. 23, FIG. 24, and FIG. 25.
In portable devices such as a mobile phone, a smartphone, and an e-book reader, an SRAM or a DRAM is used to store image data temporarily. This is because response speed of a flash memory is low and thus a flash memory is not suitable for image processing. On the other hand, an SRAM or a DRAM has the following characteristics when used for temporary storage of image data.
In an ordinary SRAM, as illustrated in FIG. 22A, one memory cell includes six transistors, that is, transistors 801 to 806, which are driven with an X decoder 807 and a Y decoder 808. The transistors 803 and 805, and the transistors 804 and 806 form inverters, and high-speed driving can be performed therewith. However, an SRAM has a disadvantage of large cell area because one memory cell includes six transistors. Provided that the minimum feature size of a design rule is F, the area of a memory cell in an SRAM is generally 100 F2 to 150 F2. Therefore, a price per bit of an SRAM is the most expensive among a variety of memory devices.
In contrast, in a DRAM, as illustrated in FIG. 22B, a memory cell includes a transistor 811 and a storage capacitor 812, which are driven with an X decoder 813 and a Y decoder 814. One cell includes one transistor and one capacitor and thus the area of a memory cell is small. The area of a memory cell of a DRAM is generally less than or equal to 10 F2. Note that in the case of a DRAM, a refresh operation is always necessary and power is consumed even when a rewriting operation is not performed.
However, the area of the memory cell of the semiconductor device described in any of the above embodiments is about 10 F2 and frequent refreshing is not needed. Therefore, the area of the memory cell is reduced, and power consumption can be reduced.
Next, FIG. 23 illustrates a block diagram of a portable device. A portable device shown in FIG. 23 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, a touch sensor 919, an audio circuit 917, a keyboard 918, and the like. The display 913 includes a display portion 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an IF 909. In general, the memory circuit 912 includes an SRAM or a DRAM; by employing the semiconductor device described in any of the above embodiments for the memory circuit 912, writing and reading of data can be performed at high speed, data can be held for a long time, and power consumption can be sufficiently reduced.
Next, FIG. 24 illustrates an example in which the semiconductor device described in any of the above embodiments is used for a memory circuit 950 in a display. The memory circuit 950 illustrated in FIG. 24 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. Further, the memory circuit is connected to a display controller 956 which reads and controls image data input through a signal line (input image data) and data stored in the memory 952 and the memory 953 (stored image data), and is also connected to a display 957 which displays an image based on a signal from the display controller 956.
First, image data (input image data A) is formed by an application processor (not shown). The input image data A is stored in the memory 952 through the switch 954. The image data (stored image data A) stored in the memory 952 is transmitted to the display 957 through the switch 955 and the display controller 956, and is displayed on the display 957.
In the case where the input image data A is not changed, the stored image data A is read from the memory 952 through the switch 955 by the display controller 956 normally at a frequency of approximately 30 Hz to 60 Hz.
Next, for example, when data displayed on the screen is rewritten by a user (that is, in the case where the input image data A is changed), new image data (input image data B) is formed by the application processor. The input image data B is stored in the memory 953 through the switch 954. The stored image data A is read periodically from the memory 952 through the switch 955 even during that time. After the completion of storing the new image data (the stored image data B) in the memory 953, from the next frame for the display 957, the stored image data B starts to be read, transmitted to the display 957 through the switch 955 and the display controller 956, and displayed on the display 957. This reading operation is continued until another new image data is stored in the memory 952.
Accordingly, image data is alternately written and read in the memories 952 and 953 so as to be displayed on the display 957. The memories 952 and 953 are not necessarily different memories, and a single memory may be divided to be used. By employing the semiconductor device described in any of the above embodiments for the memory 952 and the memory 953, data can be written and read at high speed and held for a long time, and power consumption can be sufficiently reduced.
Next, FIG. 25 illustrates a block diagram of an e-book reader. FIG. 25 includes a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.
Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit 1007 in FIG. 25. The memory circuit 1007 has a function of temporarily storing the contents of a book. For example, users use a highlight function in some cases. When users read an e-book reader, they sometimes want to mark a specified place. This marking refers to a highlight function, and users can make difference from other places by, for example, changing the color of a letter displayed, underlining a word, making a letter bold, or changing the font type of a letter. That is, there is a function of storing and holding information of a place specified by users. In order to save information for a long time, the information may be copied into the flash memory 1004. Even in such a case, by employing the semiconductor device described in any of the above embodiments, writing and reading of data can be performed at high speed, data can be held for a long time, and power consumption can be sufficiently reduced.
As described above, the semiconductor device in any of the above embodiments is mounted on each of the portable devices described in this embodiment. Therefore, it is possible to obtain a portable device which is capable of reading data at high speed, storing data for a long time, and reducing power consumption.
The methods and structures described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.
This application is based on Japanese Patent Application serial no. 2012-011160 filed with Japan Patent Office on Jan. 23, 2012, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising:
an oxide semiconductor film comprising a channel formation region and a first region;
a gate insulating film over and in contact with the oxide semiconductor film;
a first insulating film over and in contact with the first region, the first insulating film comprising an oxide of a metal element;
a gate electrode over and in contact with the gate insulating film, the gate electrode overlapping with the channel formation region; and
a second insulating film over and in contact with the gate electrode and the first insulating film,
wherein an entire top surface of the first insulating film is lower than a bottom surface of the gate electrode,
wherein the first region comprises the metal element, and
wherein an entire end portion of the first region is covered with the first insulating film.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises In, Ga, and Zn.

3. The semiconductor device according to claim 1, further comprising:
a sidewall insulating film on a side surface of the gate electrode,
wherein the second insulating film is over and in contact with the sidewall insulating film,
wherein the oxide semiconductor film comprises a second region between the first region and the channel formation region, the second region overlapping with the sidewall insulating film, and
wherein a resistance of the first region differs from a resistance of the second region.

4. The semiconductor device according to claim 1, wherein the gate insulating film comprises a first gate insulating film and a second gate insulating film over the first gate insulating film.

5. The semiconductor device according to claim 1,
wherein the oxide semiconductor film comprises chlorine, and
wherein the oxide semiconductor film has a chlorine concentration of 2×1018 atoms/cm3 or lower.

6. The semiconductor device according to claim 1,
wherein the channel formation region comprises crystal portions,
wherein c-axes of the crystal portions are aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed, and
wherein a direction of an a-axis of one of crystal portions is different from a direction of an a-axis of another of crystal portion.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises In, Sn, and Zn.

8. A semiconductor device comprising:
an oxide film;
an oxide semiconductor film over the oxide film, the oxide semiconductor film comprising a channel formation region and a first region having a resistance lower than the channel formation region;
a gate insulating film over and in contact with the oxide semiconductor film;
a first insulating film over and in contact with the first region, the first insulating film comprising an oxide of a metal element;
a gate electrode over and in contact with the gate insulating film, the gate electrode overlapping with the channel formation region, and
a second insulating film over and in contact with the gate electrode and the first insulating film,
wherein an entire top surface of the first insulating film is lower than a bottom surface of the gate electrode,
wherein the first region comprises the metal element, and
wherein the oxide film is capable of supplying oxygen to the oxide semiconductor film, and
wherein an entire end portion of the first region is covered with the first insulating film.

9. The semiconductor device according to claim 8, wherein the oxide semiconductor film comprises In, Ga, and Zn.

10. The semiconductor device according to claim 8, wherein the gate electrode is in contact with the gate insulating film.

11. The semiconductor device according to claim 8, further comprising:
a sidewall insulating film over the gate insulating film and on a side surface of the gate electrode;
a third insulating film over the second insulating film; and
an electrode electrically connected to the first region,
wherein the second insulating film is over and in contact with the sidewall insulating film.

12. The semiconductor device according to claim 11, wherein the electrode is one of a source electrode and a drain electrode.

13. The semiconductor device according to claim 11, wherein the oxide semiconductor film comprises an impurity region between the channel formation region and the first region, the impurity region having a resistance different from a resistance of the first region.

14. The semiconductor device according to claim 8, further comprising:
a sidewall insulating film over the first insulating film and on a side surface of the gate electrode;
a third insulating film over the second insulating film; and
an electrode electrically connected to the first region,
wherein the second insulating film is over and in contact with the sidewall insulating film.

15. The semiconductor device according to claim 8, further comprising:
an electrode over the oxide film, wherein the oxide semiconductor film is over the oxide film and the electrode;
a sidewall insulating film over the gate insulating film and on a side surface of the gate electrode; and
a third insulating film over the second insulating film,
wherein the second insulating film is over and in contact with the sidewall insulating film.

16. The semiconductor device according to claim 15, wherein the oxide semiconductor film comprises an impurity region between the channel formation region and the first region, the impurity region having a resistance different from a resistance of the first region.

17. The semiconductor device according to claim 8, further comprising:
an electrode over the oxide film, wherein the oxide semiconductor film is over the oxide film and the electrode;
a sidewall insulating film over the first insulating film and on a side surface of the gate electrode; and
a third insulating film over the second insulating film.

18. The semiconductor device according to claim 8, wherein the first insulating film comprises one or more elements selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, and zinc.

19. The semiconductor device according to claim 8,
wherein the oxide semiconductor film comprises a second region,
wherein the channel formation region is interposed between the first region and the second region, and
wherein each of the first region and the second region comprises one or more elements selected from aluminum, indium, titanium, tin, tungsten, nickel, molybdenum, zinc, phosphorus, arsenic, antimony, boron, nitrogen, helium, neon, argon, fluorine, and chlorine.

20. The semiconductor device according to claim 8, wherein the oxide semiconductor film comprises an oxide comprising one or more elements selected from indium, zinc, gallium, tin, hafnium, zirconium, titanium, scandium, yttrium, cerium, neodymium, and gadolinium.

21. The semiconductor device according to claim 8,
wherein the channel formation region comprises crystal portions,
wherein c-axes of the crystal portions are aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed, and
wherein a direction of an a-axis of one of crystal portions is different from a direction of an a-axis of another of crystal portion.

22. The semiconductor device according to claim 8, wherein the oxide semiconductor film comprises In, Sn, and Zn.