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National Bureau of Standards

NBS Technical Note 1230

A Precision Programmable Step Generator

for Use in Automated Test Systems

H, K. Schoenwetter, D. R. Flach, T. M. Souders, and B. A. Bell
TM he National Bureau of Standards' was established by an act of Congress on March 3, 1901. The

g Bureau's overall goal is to strengthen and advance the nation's science and technology and facilitate their effective application for public benefit. To this end, the Bureau conducts research and provides: (1) a

basis for the nation's physical measurement system, (2) scientific and technological services for industry and

government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety.

The Bureau's technical work is performed by the National Measurement Laboratory, the National

Engineering Laboratory, the Institute for Computer Sciences and Technology, and the Institute for Materials

Science and Engineering

.

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Provides the national system of physical and chemical measurement;

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'Hcadguaricrs and [.aboraiories ai Gailhersburg, MD, unless oiherwise noted; mailing address CoHhersburg, MD 20899. 'Some divisions wiihin the ccnicr arc located at Boulder, CO 80303. 'Located at Boulder, CO, with some elements at Gailhersburg, MD.
NBS

RESEARCH

INFORMATION CENTER

.^o

NBS Technical Note 1230 1^-

A Precision Programmable Step Generator

for Use in Automated Test Systems

H. K. Schoenwetter, D. R. Flach, T. M. Souders, and B. A. Bell

Electrosystems Division

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Gaithersburg, MD 20899

Sponsored in part by:

Sandia National Laboratories

Albuquerque, NM 87185

December 1986

U.S. Department of Commerce

Malcolm Baldrige, Secretary

National Bureau of Standards

Ernest Ambler, Director
National Bureau of Standards Technical Note 1 230

Natl. Bur. Stand. (U.S.), Tech. Note 1230, 104 pages (Dec. 1986)

CODEN: NBTNAE

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1986

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington DC 20402
TABLE OF CONTENTS

Page

LIST OF FIGURES v

LIST OF TABLES vi

ABSTRACT I

1. INTRODUCTION 1

2. THEORY OF OPERATION 3

2.1 Step Generator Requirements 3

2.2 Design Approaches 4

2.2.1 Prior Techniques 4

2.2.2 Present Design 6

3. GENERAL DESCRIPTION OF SYSTEM 9

3.1 Output Circuit 9

3.2 Control Unit 13

3.2.1 General Description 13

3.2.2 Backplane Wiring 19

3.2.3 IEEE-488 Interface 19

3.2.3.1 Purpose of Interface 19

3.2.3.2 Controller/Interface Operation 27

3.2.3.3 Listen Handshake Circuits 29

3.2.3.4 Interface Address Decoder 30

3.2.3.5 Code Converter 31

3.2.3.6 Board Address Decoder 31

3.2.4 DAC/OA Board 32

3.2.5 Timing Board 35

3.2.6 Output Board 39

3.2.7 Fixed Power Supplies 43

4. DRIVER SOFTWARE 44

4.1 VSG Driver Program 44

4.1.1 Coding to the Storage Registers 44

4.1.1.1 DAC/OA Board String Variable DAC $ 44

4.1.1.2 Timing Board String Variable Time $ 45

4.1.1.3 Output Board String Variable "XX" 46

4.2 Computer/ IEEE-488 Interface Code 46

iii
TABLE OF CONTENTS (cont.)

Page

5. SPECIFICATIONS 48

6. OPERATING INSTRUCTIONS 49

7. TESTING 54

7.1 Static Testing 54

7.2 Measurement of Voltage Step Characteristics 54

7.3 Exponential Waveform Errors ... 58

7.4 Duty Cycle Dependence 61

8. CONCLUSIONS 62

9. ACKNOTTLEDGMENTS 62

10. REFERENCES 63

APPENDIX A 64

APPENDIX B 69

Iv
LIST OF FIGURES

Page

Figure 2.1 Functional diagram of the NBS reference flat pulse

generator (RFPG) 5

Figure 2.2 Precision step generator. The pulse level following a voltage step transition is deterrained by V^. Amplitude

and polarity of the transition are determined by current I,

which is a linear function of Vg. Voltage ranges are "^5 and - 1 V from outputs H and L, respectively. Pulse width

and repetition rate are determined by the TTL input from

the timing circuit 7

Figure 3.1 Automated test system. The step generator consists of the

control unit and the output circuit. All functions shown

in the control unit are programmable via the IEEE-488 bus,

except for the fixed power supplies 10

Figure 3.2 Functional diagram of the step generator output circuit .... 11

Figure 3.3 Simplified diagram of the output circuit for producing

positive voltage steps. Transistors Ql and Q2 perform

the function of switch S in figure 2.2 12

Figure 3.4 Output circuit schematic diagram 15

Figure 3.5 Photograph showing the step generator output circuit

connected to an oscilloscope 17

Figure 3.6 Complete block diagram of the control unit 18

Figure 3.7 Front panel view of the control unit 20

Figure 3.8 Backplane wiring 21

Figure 3.9 Circuit board locations in the control unit 23

Figure 3.10 IEEE-488 interface board 25

Figure 3.11 DAC/OA board 33

Figure 3.12 Timing board 37

Figure 3.13 Output board 41

V
LIST OF FIGURES (cont.)

Page

Figure 6.1 Front panel connectors. Connector J4 permits external

synchronization of the TTL timing signals output by J5

and J6 . The signal from J5 is delayed 150 ns relative

to that from J6. The umbilical cable to the step

generator output circuit is connected to J7 . DSI is an LED for power ON/OFF indication 51

Figure 6.2 Rear panel connectors and power switch (SI). J9 is the

power line connector (120 V) with an integral 3 A fuse.

The IEEE-488 bus to the controller is connected to J8 52

Figure 7.1 Least squares fit in ppm of linearity error of V2 from

+5 V to -5 V, with quantization error removed 55

Figure 7.2 Basic sampling voltage tracker (SVT). Input waveform

f(t) is sampled (compared with voltage Vq) at instants

in time coinciding with the trailing edge of strobe pulses . . 56

Figure 7.3 Automatic voltage tracker system used to measure transition characteristics of voltage steps from the

step generator 57

Figure 7.4 Plot generated by the system shown in figure 7.3 of a -3 to +3 V transition of the step generator, when loaded

with 30 pF capacitance 59

Figure 7.5 Peak detector using snail Hg hearing aid batteries,

1.4 V each. Reverse bias on the diode is determined by

the number of batteries employed. Shunt capacitance of

the diode is less than 1 pF. The terminating resistance

is typically less than 180 ^ 60

Figure 7.6 Upper trace shows peak detector response to a +2 V

transition of V-^ (lower trace). Sweep speed is

10 ns/cm and detector sensitivity is 0.25 percent of

2 V FSR/cm. The initial narrow pulse in detector

output is caused by shunt capacitance of the detector

diode (see Fig. 7.5). The waveform following this

pulse accurately represents the transition of V^ 60

LIST OF TABLES

Table 1. Typical Performance Specifications 48

Table 2. Functions and Voltages for Connector J7 Pins 53

vi
A PRECISION PROGRAMJIABLE STEP GENERATOR

FOR USE IN AUTOMATED TEST SYSTEMS

H. K. Schoenwetter, D, R. Flach, T, M. Souders, and B. A. Bell

ABSTRACT

A precision voltage step generator has been designed for use in automated

systems to test the dynamic response of waveform recorders and other

instruments. The programmable pulse parameters include transition polarity,

pulse length, and repetition rate. The initial and final levels of voltage

steps are each programmable within the range of - 1 V for a 50 ^ termination

and within - 5 V for a high impedance load. Voltage steps within these ranges

settle to within '^- 0.02% of full scale range (FSR) in less than 22 and 26 ns,

respectively, for small load capacitance. The corresponding transition

durations are approximately 6 and 7 ns.

1. INTRODUCTION

The NBS Step Generator was designed for use in automated test systems to

characterize the transient response of waveform recorders, oscilloscopes, and

other instruments. In particular, the system was intended for testing

waveform recorders and digitizing oscilloscopes with resolutions of 8 to 10

bits and bandwidths up to 50 MHz. The step generator system has been used to

test a wide range of high performance waveform recorders. Tests were made on these units to determine: static errors, including offset, gain, linearity,

and noise; transfer functions, including step response, impulse response, and

frequency response; and transient errors, including dynamic linearity,

settling time, transition duration, and transient thermal errors. Several of

these test methods are described in a previous paper [1] , which is reproduced

in Appendix A.

The step generator was designed to output programmable voltage pulses,

with one well-defined transition per period, the beginning and terminating

levels of which are designated Vi and V2 . (The transition from V2 to Vi is

less well characterized, and is not relied upon for most measurements.)

Either single shot or repetitive pulses can be generated, with the repetition

rate and duty cycle programmable over many orders of magnitude. The initial

and final levels defining the steps are each programmable within the range of

± 1 V for a 50 f^ termination and within - 5 V for a high impedance load.

Voltage steps within these ranges settle smoothly, with no overshoot, to

within 0.1% of full scale range in less than 15 and 19 ns, respectively, for

small load capacitance. The corresponding 10-90 percent transition durations

are approximately 6 and 7 ns. The voltage step waveform has been

characterized by independent means, and has been shown to approximate an

NBS received the IR-100 Award for this system, which was selected by the

Research and Development Magazine as one of the 100 most significant new products of 1986.

Numbers in brackets refer to the literature references listed on p. 53 of

this report.
exponential response. At high values of output capacitance, the more slowly

rising waveform becomes sufficiently close to an exponential that it can be

used for dynamic measurements of linearity errors. Since the information

yielded from these measurements is important for characterizing a waveform

recorder, these tests are routinely performed using two capacitance fixtures

(small modules) supplied with the system.
2. THEORY OF OPERATION

2.1 Step Generator Requirements

A step generator (SG) design was sought for use in automatic test systems

to characterize waveform recorders with resolutions up to 10 bits and

bandwidths up to 50 MHz (rise time of 7 ns for a 6 dB/octave response

roll-off). Commercial pulse generators are not accurate enough for these

tests, and laboratory step generator designs lack the overall test capability

required, including wide-range programmability of the pulse parameters. An

earlier NBS design had an accuracy that approached the required performance

[3,7], as described in the next section. The minimum SG requirements for

comprehensive and accurate testing of these waveform recorders follows.

(1) The initial level, Vi, and the final level, V2, of voltage transitions

should be independently adjustable, and each should have a range of at least

- 5 V for high impedance loads. The corresponding range for 50 ^ loads should

be ± IV. These levels should be accurately related to measurable dc values

for accurate calibration,

(2) The transition duration (10-90% rise time, Tj^) of the voltage steps

should be less than 7 ns.

(3) The voltage step should settle to within ± 0.1% and ^- 0.02% of V2 in less

than 22 ns and 27 ns, respectively, measured from the 10% amplitude point.

(4) The output impedance of the SG should be essentially resistive for

frequencies ranging from dc to several times the upper cutoff (- 3 dB)

frequency of the test instrument. A passive output circuit is preferred.

(5) The SG output circuit should be packaged for direct connection to the test

device, to avoid losses (and pulse distortion) from a connecting cable.

(6) The pulse width and pulse repetition rate should be independently

selectable, with pulse widths ranging from 50 ns to 5 ms, and repetition rates

up to 5 MHz. After settling to level V2 with ± 0.02% accuracy, the voltage

must remain within these error bounds for all pulse widths.

(7) All pulse parameters should be programmable, so that the SG may be used in

automatic test systems.

A practical level of accuracy for a settled voltage step is 1/2 LSB of

the waveform recorder under test. Thus, in item 1, if the static accuracy of

V2 is - 0,03%, the settling error (item 3) should be no more than - 0.02% for

a 10-bit recorder. For an 8-bit recorder, the allowable settling error could

be as large as ± 0.17%, etc. The accuracy of Vi should be at least - 2%.

The rise and settling times given in (2) and (3) are minimum requirements

for the application. Smaller values would Simplify the error analysis of the

test recorders.
Item 4 is desired so that overshoot and ringing in the voltage step are minimal if the input circuit of the test instrument has significant parasitic

reactances (lead inductance and shunt capacitance, etc.)

Item 5 is very important, since a terminated connecting cable greatly

increases the settling time (ST). When an unterminated cable is used, cable

capacitance or voltage reflections may increase the ST. The effects of a connecting cable on ST are discussed in [2].

In item 6, pulse widths of several milliseconds are desirable for

measuring thermal transients in the test instruments.

2.2 Design Approaches

2.2,1 Prior Techniques

In previous years, tunnel diodes and mercury relays have been employed in

SGs to yield rise times as low as 20 ps and 39 ps, respectively [3], However,

these SGs had poor settling characteristics, i.e., the uncertainty of the

voltage after transitions was 1 to 2 percent, or larger [4, 5].

In an effort to obtain step-like waveforms of known amplitude and

flatness, a number of SGs or waveform standards have been developed at NBS

,

using various techniques. For example, reference 6 describes the development

of a solid-state waveshaping filter that yields a 1/4 V step with a transition

duration of 400 ps, when the filter is excited by a tunnel diode SG. The

output waveform of the filter has a smooth transition with negligible

aberrations; however, ST information is not available.

The reference flat pulse generator (RFPG) described in [3] and [7] has

the following important characteristics : (1) the initial and final voltage

levels of the transitions are calibrated from dc measurement; (2) the

transition duration of the voltage steps is very small; and (3) the output

voltage is flat after settling. This SG employs very fast precision Schottky

diode switching circuits to obtain an output step of - 0.50 V to 0.00 V.

The basic RFPG circuit is shown functionally in figure 2.1. Current 1^

flows through diode D2 and the 25 ^ parallel resistance of Rg and load

resistance R^; thus, VQ(t) = 0.5 V. When the control pulse is applied,

switch S changes from position 1 to position 2. Diode Dl conducts 10 mA for a nodal current balance and D2 is reverse biased and becomes nonconducting.

Therefore, VQ(t) rapidly approaches V, In practice, the current switching

by S is performed by an NPN emitter-coupled differential switch pair, and I^

and I2 are current sources employing PNP and NPN transistors, respectively.

3 These papers also briefly describe or reference other pulse generators or waveform standards that have been developed for testing high-speed

instruments.
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The baseline of the output step differs from V by less than 10 UV, and the

top line equals 0.5 V- 0.1%, assuming R^ = Rg*

The measured transition duration of this generator is 600 ps, and the

measured ST to ± 0.2% accuracy is approximately 8 ns. ST Uiaasureraents to

better than 0.2% were not available for this instrument. However, the RFPG

was not specifically designed for settling accuracies better than 1%. The

RFPG has other limitations which reduce its suitability for the applications

considered here. These include inadequate step size, and the inability to

select other initial and final step voltages.

2.2.2 Present Design

Figure 2.2 is a functional diagram of the SO that was designed to meet

the preceeding specifications [8]. Two output ranges are provided: a- 5 V

range from output H, intended for high-impedance loads, and a

"^ 1 V range from

output L for 50 ^ loads. Operation is as follows: the voltage-to-current

converter linearly converts programmable voltage Vg to current I over the

range of - 80 mA. When the TTL input is HIGH, current I is steered to output

2 of switch S. Output voltage V^ is determined by the programmable voltage

V^ and the ratio (R2 + R3)/(R1 + R2 + R3 ) formed by the resistive voltage

divider. Hence, Vfj = V^/2. When the TTL input is LOW, current I is

steered to output 1 of S, changing Vy by IRp, where Rp is the parallel

resistance of Rl and (R2 + R3). Thus, Vy = V^/2 + IRp. Resistance

Rp, equal to 125 ii^ , is also the source impedance for V^. The low-level

output Vl is equal to V^/5. When output L is used, the 50 '^ terminating

resistor R3 shown in figure 2.2 is actually the input impedance of the test

device; otherwise a 50 fi! coaxial termination is used.

Switch S operates within a few nanoseconds after the TTL input changes

state. Also, when it switches current I from terminal 1 to terminal 2, all

active elements are isolated from terminal 1. Consequently, the transition

from (V^/2 + IRp) to V^/2, is an exponential waveform determined by Rp

and the total capacitance between terminal 1 and ground. Since the transition

to V^/2 involves only passive elements, it can be much more accurately

characterized than the reverse transition, which involves active elements.

Therefore, the transition to V^/2 is recommended for waveform recorder

testing. The initial and final levels of this transition have been designated

Vi and V2 . Output voltage V^Ct) has a smaller settling time than Vy(t),

but has essentially the same waveshape. The pulsewidth and repetition rate

are determined by the timing circuit, which is under computer control, as are programmable voltage supplies A and B, via the IEEE-488 bus. In practice, the

timing circuit is a programmable pulse generator with TTL-type output pulses.

Since rapid load current changes cause output voltage transients in most

voltage supplies, dummy load R4-R5 and complementary switching circuits in

current switch S and the voltage-to-current converter are employed to maintain

constant load currents for voltage supplies A and B, Also, terminal 3, placed

physically close to Rl , is carefully bypassed so that the impedance to ground

is essentially zero for the frequency range of interest. In order to enhance

the effective accuracies of V^ and V^, corrections to the resistance

ratios and values of V^ can be stored in a computer for later application to

test data. Since the relative heat dissipation in Rl and (R2 + R3) varies

with changes in V^, I, and pulse duty cycle, resistors Rl and R2 (metal

film) were chosen to have small temperature coefficients.
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The circuits shown in the dotted outline comprise the output circuit of

the SG, and are contained in a small package ("test head") which may be

connected directly to the instrument under test. The programmable voltage

supplies and timing circuit are contained in a separate support package, which

is designated the control unit.
3. GENERAL DESCRIPTION OF SYSTEM

The NBS Step Generator (SG) is designed to output programmable voltage

pulses, with one well-defined transition per period, the beginning and

terminating levels of which are designated Vi and V2 • The SG consists of the

output circuit and the control unit, which were described briefly in section

2.2.2. As mentioned previously, the system also includes two capacitance

modules for dynamic linearity measurements.

Figure 3.1 shows the SG in an automated test system. Overall control is

provided via the IEEE-488 bus, for which an internal interface (not shown) has

been provided. The waveform recorder under test is also interfaced to the

controller via this bus. The output circuit of the step generator is a small

test head which connects directly to the input terminal of the waveform

recorder under test. The control unit provides the power, precision dc

voltage levels (V^, Vg), polarity selection pulses, and timing pulses

necessary to control the parameters of the voltage steps generated in the

output circuit.

3.1 Output Circuit

The step generator output circuit, shown in figure 3.2 is packaged in a small, lightweight container that is separate from the voltage supplies and

timing circuit. Output connectors H and L are male BNC connectors which

permit direct connection to a waveform recorder, or other measuring device,

without the use of a coaxial cable. The step generator actually consists of

two, essentially complementary, voltage step generators-one for each polarity

of transition. A simplified schematic diagram of the circuit used for

producing positive voltage steps is shown in figure 3.3. Transistors Ql and

Q2 perform the function of switch S in figure 3.2, switching current I to

terminal 1 or I' to terminal 2. Collector currents I and I' are proportional

to the common base current gains of Ql and Q2 , and typically differ by less

than two percent. The magnitude of I is approximately ( (Example: for a 6V step at connector H, I = 48 mA and Vg

iAt

Vb -8.3)/125.

^ 14. 3V).

Schottky TTL buffers Ul and U2 provide the drive currents for Q3 and Q4 , which

alternately bias Ql and Q2 off. Operation is as follows: prior to the TTL

input pulse, the outputs of Ul and U2 are LOW and HIGH, respectively, so that

Q3 is biased off and Q4 is conducting. Therefore, Q2 is biased off and Ql

conducts current I to terminal H, yielding an output voltage V^ = V^/2+IRp, Upon application of the TTL pulse at time Ti , the outputs of Ul

and U2 switch to HIGH and LOW levels, respectively, switching Q3 on and Q4

off. This action switches Ql off and Q2 on. Consequently, voltage Vjj

switches to level V^/2.

Except for some modification of the TTL buffer circuits and the biasing

of the lower pair of transistors, the circuit for producing negative voltage

steps is essentially the complement of the circuit shown in figure 3.3. A

latching DPDT relay is employed to connect Ql or its complementary counterpart

to connector H or to ground. A second DPDT relay is used to apply - 5 V to

Q3 , Q4 , Ul , U2 , or their counterparts. Thus, programming the SG includes

pulsing the appropriate relay windings to select the voltage step polarity.

Diodes Dl and D2 protect Ql and Q2 when these transistors are disabled.
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12
A detailed diagram of the complete output circuit is shown in figure 3.4.

The circuits for producing negative and positive voltage steps are shown on

the left and right sides of the drawing, respectively. The functions of some

of the components/circuits not shown in figure 3.3 are given below:

(1) Clipping diodes CR4-CR9 and CR15-CR20 are used to keep transistor pairs

Q3 , Q4 , and Q7 , 08 out of saturation, respectively. Preventing saturation

permits pulse repetition rates up to 10 MHz.

(2) Diodes CR2 , CR3 , and CR13, CR14 minimize switching transients,

capacitlvely coupled to the collector circuits of Ql and Q5

,

respectively.

(3) R40 and R41 are selected for minimum settling time for negative and

positive transitions, respectively.

(4) Capacitors C30-C41 were added to minimize the effect of capacitive loading

of voltage supply V^, when large capacitors are connected across output

H for dynamic linearity tests (discussed later).

The numbered leads, ranging from 1 to 18, refer to umbilical connector pin

numbers.

Figure 3.5 is a photograph showing connector L (± 1 V range) of the

output circuit connected to an oscilloscope. Since the oscilloscope has a high input impedance, a 50 ohm coaxial termination is required. The output

circuit test head dimensions are approximately 7.6 x 7.6 x 3.8 cm, excluding

connectors, and its weight is approximately 200 g.

3.2 Control Unit

3.2.1 General Description

Figure 3.6 shows a complete block diagram of the control unit. Overall

control is provided via the IEEE-488 bus for which an Internal listener

interface has been provided. This bus interface, in turn, drives a system bus

to distribute data for controlling the operating parameters of the step

generator output circuit (test head). These parameters are: the pulse

repetition rate, pulse length, voltage step polarity, and the initial and

final voltage levels (Vi , V2 , respectively) of the step. The ranges of the

pulse parameters are as follows:

Pulse repetition rate: 153 Hz to 5 MHz

Pulse length: 20 ns to ~ 6 ms Duty cycle: approximately 5% to 95%

Vi, V2: ± 5 V

Polarity of transition: either + or -

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The most critical of these parameters is V2 , which is equal to V^/2.

For a given (selected) value of V2 , V^ should be invariant over the complete

ranges of the other parameters. Also, the resolutions in the selection of V2

and Vi are determined by the resolutions of V^ and Vg (0.02A% for V^ and

0.09% for Vg). The details of the circuits that determine the pulse

parameters is given in later sections. A photograph of the control unit is

shown in figure 3.7.

3.2.2 Backplane Wiring

The backplane wiring and connectors for the plug-in circuit boards are shown in figure 3.8. The circuit boards and 108-pin mating connectors are numbered according to their position in the card cage (see figure 3.9). As

mentioned previously, the IEEE-488 bus is connected to J8 (rear panel) of the

control unit. Eight-conductor and eighteen-conductor flat cables are used to

connect J8 to the connector (#3) for the IEEE-488 interface board. These pin

connections are outlined by dashed lines.

It is seen that control signals from the interface board are sent only to

the Timing, DAC/OA, and Output boards (boards 5, 7, and 9, respectively). The

pin numbers (A6, B6 , C12, etc.) to which wires are connected are used to

designate the signal lines on the schematic drawings for these four boards.

The regulated voltage supplies required for powering the step generator

control unit and output circuit are mounted on boards 11, 15, 19, and 23.

Also, the frequency synthesizer board (FREQ, SYN. ) is not employed in the

present application.

3.2.3 IEEE-488 Interface

A schematic diagram of the IEEE-488 interface circuit board is shown in

figure 3.10. These circuits represent a hardware (chip level) implementation

of an IEEE-488 interface having the following functions: acceptor handshake

function, device clear function, and listener function, extended to honor

secondary addresses [9]. The following sections provide a detailed

description of the design of this particular implementation.

The components of the IEEE-488 bus are the data bus, the transfer bus,

and the management bus. Transceiver ICs UOl and U02 interface with the data

bus (signals DI01-DI08), and transceiver ICs U03 and U04 interface with the

transfer and management buses. The transfer bus handles handshake duties and

includes the three signal lines DAV (data valid), NDAC (data not accepted),

and NRFD (not ready for data). Of the five signal lines in the management

bus, only the ATN (attention) and IFC (interface clear) lines are used in this

application,

3.2.3.1 Purpose of Interface

Three circuit boards in the control unit are used to control the pulse

parameters of the SG, and a certain amount of information must be stored on these boards to quantify these parameters. Shown in the following table are

the bits of information used to quantify each parameter, the number of memory

chips (ICs) used to store this information, and the circuit board location.

4 These interface buffers have inverters in the input/output lines from/ to the

IEEE-488 bus.

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The values chosen for each of these parameters can be those entered via

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chosen by a computer program. In either case, the purpose of the interface

board is to see to it that the data required to quantify the voltage step

parameters are directed to the correct boards, and are accompanied by chip

address codes so that each memory chip receives the intended data word.

The chip address decoder located on each board distributes the data words

to the correct memory chips on that board, based on the chip address codes

received from the interface board.

3.2.3.2 Controller/Interface Operation

A cursory description of the procedure followed by the controller and the

interface circuits to perform the required interface functions is given

below. Except for DAV signals, the detailed handshake activity will be

omitted. A more detailed description of the circuits outlined by dotted lines

in figure 3.10 is given in later sections. This procedure is for sending data

words to the DAC/OA circuit board from the controller.

Controller Action

(1) ATN line set low.

(2) Primary address put on lines

DIOl(LSB) - D108 (1st data

byte). DAV signal sent, i.e.,

DAV line set low, then high.

(3) Secondary address sent

(2nd data byte).

DAV signal sent.

Interface Response

Address decoders U17 , U18, and U19

are partly enabled. With DAV signals,

(action 2) address decoders U17, U18,

and U19 are fully enabled.

This address is compared with primary

listen address stored in interface

address decoder. If addresses are equal, primary address flag is "set"

in interface address flipflop U22.

This address is compared with

secondary listen address stored in

interface address decoder. If

addresses are equal, secondary address

flag is set in U22, and output 2Q high

enables U15A and U15B.

Note: l=low state (<0.8V), 0=high state (>2.0V), per the IEEE-488 standard

[10]. "Low" and "high" in this discussion also refer to TTL level

negative true logic levels.

27
(4) "Selected Device Clear'

command sent.

(5) ATN line set high.

(6) 3rd data byte sent. 1st

3 bits contain board

address information. DAV

signal sent.

(7) A th data byte sent (first

4-bit data word for DAC/OA

board). DAV signal sent.

(8) 5th data byte sent (second

4-bit data word for DAC/OA

board).

Signal sent via U15A and U26 clears

chip address counter U23 to zero. (Code output from U23 is (0000)2).

U15C is enabled via U15B which allows

DAV signal to clock the chip address

counter U23 (see action 7).

1st 3 bits of data byte are applied

to board address register U24. Code

applied to register is assumed to be

(000)2.

Positive DAV pulse is sent via U15C

to U16B and U28A. Leading edge of

pulse latches board address into U24

;

trailing edge increases count in U23

by one. Board address decoder then

activates line 15 of U06-U09 when

strobed by the outputs from U23.

4-bit data word from board data bus

lines A6 , B6 , A5 , B5 is latched into

chip Ul of DAC/OA board (see figure

3.11) by its chip address decoder U7

,

since code output of U23 of interface

board is (0001)2. Data latch signal

from UIO is timed with leading edge

of DAV pulse. Leading edge of DAV

pulse cannot affect U24 as before

since (0001)2 code from U23 disables

U16B. Therefore, the board address

does not change. U16C is enabled,

however, allowing DAV to latch board

address into UIO, thus activating data

latch signal to the DAC/OA board.

Trailing edge of DAV increases count

in U23 to (0010)2.

4-bit data word is latched into chip

U2 of DAC/OA board by its chip address

decoder U7; latch signal timed with

leading edge of next DAV pulse as before.

The above procedure continues until no more data words are to be sent to the

DAC/OA board. Then, the unaddressing sequence follows steps (a) through (e)

below.

Controller Action

(a) ATN line set low.

(b) Unlisten command issued, i.e.,

(00111111)2 sent.

Interface Response

With step (c), address decoders

U17, U18, and U19 are enabled.

28
(c) DAV line set low.

(d) DAV line set high.

(e) ATN line set high.

Inputs 1 and 13 of U22 are set

low clearing interface address

flipflop of address flag information.

2Q output of U22 set low.

Inputs 1 and 13 of U22 are reset high.

NRFD and NDAC are set low via U14A and

U27. (See next section 3.2.3.3 for

details ).

The overall procedure starting with step (1), and ending with step (e), is now

repeated for sending data words to the timing and output circuit boards, with

the board address changing to (001)2, and then (010)2 ii^ step 6.

3.2,3.3 Listen Handshake Circuits

These circuits are outlined by dott ed li nes shown in figure 3.10. The

handshake circuits send combinations of NRFD and NDAC to U04 , in response to

the ATN and DAV signals sent by the controller. The handshake process is

fully described in Appendix B of [10].

A handshake sequence is executed by the controller and the interface over

the transfer bus each time a byte is transferred over the data bus. Since

NRFD and NDAC on the IEEE-488 bus each have two states, the two quantities

taken together have a total of four different states (11, 10, 01, 00).

The 1,1 state indicates that the interface is not ready for data (NRFD=1)

and has not accepted data (NDAC=1). In this state, communication

is temporarily held up on the bus. This state can arise, e.g., if

ATN is high and the primary and secondary address flags have not been

"set" in the interface address flipflop.

The 0,1 state indicates that the interface is ready for data (NRFD=0) and is

not accepting data (NDAC=1). Thus, the interface is prepared to

receive messages.

The 1,0 state indicates that the interface is not ready for data (NRFD=1)

because it is in the process of accepting data (NDAC=0),

The 0,0 state is an error condition.

Between receiving messages from the controller, the NRFD and NDAC lines

of the listen handshake circuits are high so that NRFD and NDAC on the

IEEE-488 bus are low and in the 1,1 state. After the controller sets the ATN

line low, the normal handshake sequence is as follows: data is put on the data

bus when the state is (0,1) indicating that the interface is ready for data.

After allowing time for the data to settle, DAV (data valid) is set low by the

controller. After DAV is set low, the handshake circuits set NRFD low,

followed by NDAC being set high (state 1,0). The latter step tells the

controller that the interface has received the data (or address) byte.

Following the (1, 0) state, a certain minimum time, Tp, is required for the

controller to return DAV to the high state. The circuits in the interface

board will function properly with a wide range of Tq values. After DAV is

29
set high, the NRFD/NDAC state is returned to (0, 1), ready for another

handshake cycle. After the message has been received, the controller then

sets the ATN line high, and the following inputs are applied to the handshake

circuits: (1) the output from U15B is low, (2) the DAV line is high, (3) the

ATN and ATN lines are high and low, respectively. Consequently, NRFD and NDAC

are set low via U14A, U27 , and U14C, U14D.

3.2.3.4 Interface Address Decoder

These circuits are used to decode primary and secondary listen addresses

on the data bus, the "Selected Device Clear" command, and the unlisten

command. The manner in which the address decoder decodes these addresses and

commands will be discussed. Handshake responses will be omitted for the sake

of brevity.

Primary Listen and Secondary Addresses

After setting the ATN line low, the controller puts the primary address

(00101000)2 on the data bus and sets the DAV line low. To recognize this

primary listen address the three inputs to OR gate U12A must all go low, thus

providing a rising edge to the ICK clock input of dual J-K flipflop U22. ATN

low and DAV low enable U17, U18, and U19 (3 line to 8 line decoders). Since

bit 7 on the data bus is 0, pin 10 of UOl is low, and pin 15 of U17 and pin 13

of U12A are low. Also, since bit 6 is 1 , pin 6 of UOl is high and pin 2 of

U12A is low. Finally, the first five bits also agree with address 8 set by

switch SI. Therefore, output 6 (U21) of comparator pair U20 , U21 will be high

and pin 1 of U12A low. With all inputs of U12A set low, pin 3 of U22 goes

high and IQ is set low, as is pin 8 of U13A. Thus, the primary address has

been "captured" off the IEEE-488 bus, and the primary address flag "set".

With ATN still low, the controller puts the secondary address (01101100)2

on the bus and sets DAV low. U17, U18, and U19 are again enabled. It can be

shown that inputs 9, 10, and 11 of U12B are now low, causing input 9 of U13A

to go low. Since pin 8 was previously set low, the positive-going output of

U13A is applied to pin 11 of U22, setting 2Q high. Therefore, the secondary

address is now captured and the secondary address flag set. It is seen that

output 2Q has also set input 9 of U15A and input 1 of U15B high, thus enabling

these gates. These conditions are necessary for the operation of the

remaining circuits. Also, if U15B were not enabled, the handshake circuits

would set the NRFD, NDAC state to (0,0), an error condition as previously

mentioned.

Selected Device Clear (SDC) Command

This IEEE-488 bus command clears the chip address counter U23 to zero. The controller keeps ATN low and issues the SDC command, (00000100)2. When

DAV is set low by the controller, U17, U18, and U19 are enabled, and the

outputs from UOl and U02 cause all inputs of UllB to go low. Output 12 of

UllB goes high, and since U15A was previously enabled, a clear signal is

applied to U23, setting outputs QA, QB, QC, and QD of the counter to low

(output code of (0000)2). These lows are applied to pins 2, 3, 11, and 12 of

U13C and U13D, producing a high at pin 6 of U16A and pin 2 of U16B, enabling

the latter. Note that after the first count has been given to U23 , U16B is

then disabled and U16C is enabled. (See steps 6, 7, and 8 of section

3.2.3.2).

30
Unlisten Command

When no more data bytes are to be sent, which is determined by the

controller, the ATN line is set low and the unaddressing sequence begins.

(See step (a)-(e) of section 3.2.3.2). With ATN set low, the controller

issues the unlisten command (00111111)2« The controller also sets DAV low,

enabling U17, U18, and U19. The above code sets lines 3, 6, 10, and 14 of U02

and lines 3 and 6 of UOl high. Line 10 of UOl is set low. It can be seen

that these inputs to U17, U18, and U19 cause lows on the inputs of U12C and,

therefore, a low at input 1 (1 CLR) and input 13 (2 CLR) of U22. This signal

clears flipflop U22 of address flags. When DAV goes high, inputs 1 and 13 of

U22 are set high. The controller may then proceed to issue an untalk command

(10111111)2, to which only the handshake circuits respond. The controller

sets ATN high, ending the command sequence.

3.2.3.5 Code Converter

IC U05 is a 4-bit binary full adder which is used to translate ASCII

characters to hexi decimal digits. Lines 3, 6, 10, and 14 of U02 and line 3 of

UOl are connected to the adder, as shown in Fig. 3.10. If the incoming data

is an ASCII "0" to "9", the adder takes no action. If the incoming data is an ASCII "A" to "F" (the signal applied to Bl and B4 is high), a 9 is added to

the first 4 bits to obtain a sequence of numbers in the range of to 15.

This allows entry of the hex digits, A to F, from the controller keyboard or

in a program mode. The data output lines of U05 are connected by backplane

wiring to the three control unit circuit boards mentioned previously. The

inactive boards cannot access this data, however, because the chip address

lines are held high and the chip address decoder receives no latch signals.

3.2.3.6 Board Address Decoder

This circuit employs ICs U06-U10. The three lines of the board address

register U24 are connected to the inputs of U06 through UIO, which are three

line to eight line decoders. For example, if the register output is (000)2,

output Yo (pin 15) of the five chips is active. If the register output is

(001)2, output Y (pin 14) of the five chips, is active, etc. Outputs Y3

through Y7 are not used. Outputs Yq are connected to the DAC/OA board,

outputs Yi to the timing board, and outputs Y2 to the output board. Outputs

which are inactive at any time are held higho

Outputs QA, QB, QC, and QD of chip address counter U23 are applied to pin

4 (G2A) of U06, U07, U08, and U09, respectively, and are used to latch the

active output lines of U06-U09. These lines are connected to the chip address

decoder located on the activated board. The decoder determines which chip is

to receive the data sent to the board. Each chip address is latched into the

decoder by a data latch signal received from the active output line of UIO.

The latch signal occurs when DAV is passed through U16C and U28C to pin 4

(G2A) of UIO.

Succeeding data bytes are handled by the interface in the same way, with

the chip address counter advancing one count with each DAV pulse. Thus, the

counter and ICs U06-U09 serve as a chip address encoder. When all chips have

received data for the selected board, the chip address counter is reset to zero as before by the SDC command, and the process just outlined is repeated

for the next board, etc.

31
3.2.4 DAC/OA Board

The DAC/OA board contains the circuits necessary to generate voltage

V^and Vg (see figure 3,11). If Vi and V? are the initial and final

voltage levels of the desired voltage step, respectively, then

and

Va = 2 * V2 ,

Vg = sign (V2-V1) *( V2 - Vi + 8.3),

where * indicates multiplication, the sign function is -1 if V2 > Vi, and is +

1 if V2 < Vi . In order to have approximately 10% overrange capability for V2

and Vi , the ranges for V^ and Vg are set at ^11 V and ±20 V, respectively.

Voltages V^ and Vg are generated by a pair of D/A converters (DACs)

with output amplifiers (OAs). Since the DACs for both supplies have an output

range of - 10 V, the nominal amplifier gains for the V^ and Vg supplies

are set at 1.1 and 2.0 respectively. Therefore, these ratios are used for

R2/R1 and R4/R3, respectively, in amplifiers U^ and Ug.

If V'a 3nd Vg are the output voltages from DAC A and DAC B,

respectively, then

V, = - 0.909091* V, ,

, A A

and , Vg = - (1/2)* Vg .

The networks in the output circuits of amplifiers UA and UB, including CI and

C2, are recommended by the manufacturer to improve the load transient

response.

Complementary offset binary coding is used for both DACs. Registers Ul , U2

,

and U3 provide the input code for DAC A and registers U4 , U5 , and U6 provide

the input code for DAC B.

The inputs to the chip address decoder (U7) are obtained from outputs Yq

of U06-U09 of the board address decoder shown in figure 3.10. As the input

code changes one bit at a time from (0001)2 to (0110)2, 4-bit data words from

the board data bus are sequentially loaded into registers Ul through U6. The

data latch signal on line C8 and on 01 and G2 of U7 is the gated DAV pulse

from the IEEE-488 interface board. Since the selected output line of U7 goes

low when Gl and G2 go low, the flipflops in the selected register are triggered on the leading (negative going) edge of DAV. The complete process

by which the address code and the data words are obtained (for registers

U1-U6) is explained in section 3.2.3.

The board address (0000)2 and the six 4-bit data words, needed to

establish V'^ and Vg, are contained in a 7-digit hexadecimal word string,

which may be entered via the keyboard or a computer program. The make-up of

the DAC/OA board word string is discussed further in section 4., DRIVER

SOFTWARE.

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3.2.5 Timing Board

The circuits on the timing board (see figure 3.12) control the pulse

repetition period and the pulse length of the voltage steps as well as the

internal/external clock choice. The inputs to the chip address decoder Ull are obtained from outputs Yl of U06-U09 of the board address decoder shown in

figure 3.10. As the input code changes one bit at a time from (1001)2 to

(1010)2, 4-bit data words from the board data bus are sequentially loaded into

registers Ul through UIO. The latching signal on line C14 and Gl and G2 is

the gated DAV pulse from the IEEE-488 interface board, and appears on the

selected output line of Ull. The data word is latched into the selected

register by the leading edge of this pulse after it is inverted by one of the

U18 or U19 inverters.

The data words (codes) that have been latched into registers U3-U10 are preset into counters U21-U28 once each output pulse repetition period. Timing

of the presetting occurs with the first negative transition of the clock

signal after the load input (pin 9) of the counters is set low.

The pulse repetition period of the step generator is determined by the

code value preset into counters U21 through U24 , and equals the complement of

this code times the (10 MHz) clock period. When these counters receive a full

count, the code values in registers U3-U6 are preset into these counters. The

code values In registers U7-U10 are also preset into counters U25 through U28

at the same time. These latter ICs are used to control the pulse length,

which is discussed next.

Outputs 3 and 6 of Ul are applied to U12 to select either the internal

clock (U16) pulses or the external clock pulses from line A17. Outputs 11 and

14 of Ul are applied to U13 to select the means of controlling the pulse

length. The function table for U13 is shown below:

B A ICo ICi IC2 IC3 lY

1.

2.

3. L L L X X X L

4. L L H X X X H

5. H H x X X L L

6. H H X X X H H

Thus, when inputs A and B are both low the output waveform (at lY) Is

determined by the input pulse to ICq. The length of this pulse is

determined by the binary code preset into counters U25 through U28, and is

equal to the complement of this code times the (10 MHz) clock period. Pulse

lengths ranging from 100 ns to ~6 ms may be selected (see section 4.1.1.2).

This same pulse is applied to U20 and delay line U15, and appears at the

output of U29 and input IC3 of U13. However, this pulse Is terminated by the

delayed pulse through U15. Therefore, the length of the pulse at IC3 equals

the delay of U15 , which is programmed via U2 . This method provides for pulse

lengths in the range of 15 to 165 ns (see section 4,1.1.2). The pulse at IC3

appears at output lY of U13 when Inputs A and B are both high. Output pin lY

35


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is connected via A20 and C29 to pin 2 of U3 on the Output Board (see figure

3.13). The function table also shows that steady-state values are produced at

lY for HL and LH combinations of A and B, respectively. Therefore, dc levels

of either VI or V2 , as well as transitions between these levels, can be

selected for the step generator output by programming the states of the A and

B inputs to U13.

The complete process by which the chip address code and the data words

are obtained (for the registers Ul-UlO) is explained in section 3.2.3.

The board address (001)2) pulse length and repetition period,

internal/external clock choice, and other quantities are selected by an 11

digit hexadecimal word string, which may be entered via the keyboard or a computer program. The composition of the timing board word string is

described in section 4., DRIVER SOFTWARE.

3.2.6 Output Board

The circuits for selecting the polarity of voltage steps, under program

control, are located on the output board and shown in figure 3.13. Also shown

are circuits for receiving an external TTL compatible clock signal, and for

outputting TTL timing signals.

External clock pulses, input at J4 , are applied to U4 using a coaxial

cable, and the output of U4 is applied to C30 and routed to A17 of the timing

board. The TTL timing signal received from the timing board is wired to have

both an undelayed output and an output with 150 ns delay, obtained by using

delay line U5. These outputs are available at J6 and J5, respectively.

A TTL level pulse of at least 1.5 ms duration is required from Ql to set

the relays in the step generator output circuit for negative steps. A similar

pulse is required at the output of Q2 to set the relays for positive steps.

The corresponding logic states for the signal lines leading to Ql and Q2 are

as follows:

U6 Input (pin no.) U2

1 1 1 L M3Q2QJ_Q

(1) xxLH xxHL

(2) xxHL xxLH

(3) XX LL xxHH

States (1) and (2) must be latched into U2 and held for at least 1.5 ms to

operate the relays. The logic levels for the U6 inputs may be changed after

the signals are latched into U2. Thus, three different input words are required from the board data bus: (xx01)2, (xxl0)2, and (xx00)2.

Operation of these relay driver circuits can be described with an example. Assume that state (3) exists initially and that a negative

transition is desired. The procedural steps described in 3.2.3.2 are followed, except that the board address is (010)2 and the board address

decoder activates lines 13 (Y2 ) of U06-U10 on the IEEE-488 interface board.

Also, from the fourth data byte (step 7), the 4-bit data word sent to the

input of U6 is (xx01)2. The second DAV signal, applied to U6 via Ul , latches

the data word into U2 and the Ql output goes high. The controller now issues

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41

the unaddressing sequence (steps (a)-(e)) of section 3.2.3.2. When the

sequence is complete, the controller repeats the above procedure, except that

this time the data word applied to U6 is (xx00)2. This sets the output of Ql

to the low state. The time consumed between corresponding points in the two

commands is approximately 5 ras , and determines the relay latching pulse

length. The procedure is the sane for a positive transition, except that the

first data word applied to U6 is (0010)2 for activating Q2. Transistors Q3

and Q4 are not used in this application,

3.2.7 Fixed Power Supplies

Several fixed, regulated power supply voltages are required for powering

the circuits boards described in the previous sections (see figure 3.9). The + 5 V and - 5 V power supplies (1.5 A each), required for the step generator

test head, are mounted on board 15. The ± 15 V supply (one module), required

for the test head, is mounted on board 11. Also mounted on the latter board

is the ± 15 V supply (one module), required for operating the DACs on board

7. All 15 V supplies have a 200 mA capacity. The + 26 V and - 26 V supplies

(300 mA each), mounted on board 19, are required to operate the output

amplifiers (U^, Ug) on board 7. In addition to the board-mounted

supplies, a 3 A, 5 V logic supply is mounted on the rear panel of the control

unit.

43
4. DRIVER SOFTWARE

4.1 VSG Driver Program^

The VSG driver program is listed in Appendix B. The numeric and string

variables and the line labels used in this program are all defined there.

Also given are flow charts for each of the user definable keys and for GOSUB

2500, the main routine used to calculate codes needed for the DACs (see figure

3.11).

The VSG driver program facilitates operating the step generator

system by the user-definable keys of the computer (controller/processor),

(see section 6. OPERATING INSTRUCTIONS). The program generates the necessary

board string variables from the pulse parameter values entered on the

keyboard. Each string variable identifies the circuit board that controls the

parameter (or parameters) being quantified by the keyboard entries, and the

data words to be sent to specific registers on the board. In addition to

computing data words from the parameter values, the program also flags

unacceptable (illegal) parameter values, such as Vi = V2 or pulse length > pulse period.

4.1.1 Coding to the Storage Registers

The IEEE-488 bus interface board has an adder circuit in the data lines

to the registers in the control unit. Allowable ASCII symbols that can be set are 0-9, A, B, C, D, E and F. When letters A-F are sent, bit 5 of the ASCII

character enables the adder and adds 9 to bits 1 to 4 (bit 1 = LSB) to obtain

a hexidecimal code. This allows use of characters A-F from the keyboard or in

a programmable mode. In the explanations of the string variable for each

board, the use of 0-9 and A-F refer to ASCII inputs from the computer to the

IEEE-488 interface.

Note: to ensure reliable loading of data into storage registers, the

internal/external clock is turned off while loading data (see the timing board

functions in section 4.1.1.2).

4.1.1.1 DAC/OA Board String Variable DAC $

Position

Code

1 2 LSHD

3 + 1

4 MSHD

5 LSHD

6 + 1

7 MSHD

Each position

4 bits wide

Bit location in

each position:

Position Number

LSB +1 +2 MSB

The notation, voltage step generator (VSG), is used interchangeably with

numeric variable Vsg (in Appendix B) , and step generator (SG).

44
LSHD = least significant hex digit; + 1 = second hex digit

MSHD = most significant hex digit

LSB = least significant bit; + 1 = second bit; + 2 = third bit

MSB = most significant bit

Position 1: Board address. Set to "0" for DAC/OA board address.

Positions 2-4: Hex code for DAC A. Coding is complementary offset binary

and output voltage range of DAC A is +/- 10 volts.

Positions 5-7: Hex code for DAC B. Coding is complementary offset binary

and output voltage of DAC B is +/- 10 volts.

Note: See restrictions in section 3.2.4 regarding allowable voltages when

positive or negative transitions are used.

4.1.1.2 Timing Board String Variable Time $

1 2 3 4 5 6 7 8 9

1 10 11

1 Func Delay LSHD + 1 +2 MSHD LSHD + 1 +2 MSHD

POSITION FUNCTION

12

3

4-7

5-11

Board address

Selects timing board functions

Program pulse length using delay line

Sets the voltage-step generator drive frequency

Sets the pulse length

Position 1 Position 2 Set to "1", the timing board address

Selects timing board functions

Code

"O* Numeric variables C1=0, C2=0; internal clock, VSG drive

frequency, and pulse length set by programmable counterS(

"I"

2"

Numeric variables Cl=l, C2=0; external clock, VSG drive

frequency, and pulse length set by programmable counters.

Numeric variables Cl=2, C2=0; turn internal/external clock

off.

"5" Numeric variables Cl=l, C2=4; initial level output, the

internal/external clock is turned off.

Numeric variables Cl=l, C2=8; final level output, the

internal/external clock is turned off.

"C" Numeric variables C1=0, C2=12; pulse length set with delay

line using internal clock. This must be set before using

Key 5.

"D" Numeric variables Cl=l, C2=12; pulse length set with delay

line using external clock. This must be set before using

Key 5.

45
Position 3:

Positions 4-7

Positions 8-11

Program pulse length using delay line. This is used after

"C" or "D" set in position 2. The coding is in one hex

digit, "0" = smallest step size of 15 ns (the initial

delay), then in 10 ns steps to 165 ns for "F". Minimum step

size that propagates thru the system is about 35 ns, a "2". Note: pulse length must be set to a value greater than

one multiplied by (internal or external clock periods).

Divide the internal/external clock frequency by an integer

from 2 to 65,535 to obtain the VSG drive frequency. Coding

for each digit is in hexadecimal.

Set the pulse length in clock periods (internal or external)

multiplied by an integer from 1 to 65,534. Coding for each

digit is in hexadecimal. Note: when setting up the VSG

drive frequency, the pulse length must be less than the

period of the VSG drive frequency.

4.1.1.3 Output Board String Variable "XX"

i

I

Position:

Code

122C

Each position

4 bits wide

Position 1: Board address. Set to a

"2" for output board address.

Position 2: Transition code (polarity of step change).

Code

"0" Normal and initialization setting.

"2" Positive transition; should be set to "2" for about

5 ms , then set back to "0".

"1" Negative transition; should be set to "1" for about

5 ms, then set back to "0".

4.2 Computer/ IEEE-488 Interface Code

Decimal 7 is a selection code used by the HP9000 series 200 computer to

address the accessory slot in the computer where the IEEE-488(GP1B) interface

is installed. This interface select code is not sent out on the IEEE-488

bus. The following two examples illustrate the use of this code.

Example 1: Selected Device Clear

CLEAR 70812 = Selected device clear,

where 08 is the primary listen address set by SI on the interface board

(figure 3.10) and 12 is the secondary address. After the primary and

secondary address are set in the address register, the selected device clear

command is executed.

46
Example 2: Output data

OUTPUT 70812; AXX ... XX, - where

A = board address (0, 1 or 2)

XX ... XX = ASCII data to storage registers.

The storage register for the board address is IC U24 on the IEEE-488 interface

board.

47
5. SPECIFICATIONS

The performance specifications of the NBS Step Generator system are given

below in Table 1. Static, step, and exponential waveform errors are given in

terms of either the 10 V full scale range (FSR) or the 2 V FSR. The polarity

selected by the operator corresponds to the transition between Vi and V2, the

initial and final values of a step, respectively. Settling times to within

± 0.1% of FSR and within* 0.02% of FSR are listed under "Step Limitations".

Self-heating effects on the V2 level are listed under "Duty Cycle Dependence".

Table 1 Typical Performance Specf ications

Static Errors Level V2 Level Vi

0.01 1.0 % FSR

0.01 1.0 % FSR

0.008 0.5

0.012 0.024 % FSR

<500 <500 yv p-p

Offset (software corrected)

Gain (software corrected)

Linearity (Max.

)

Quantization uncertainity

Noise (40 MHz BW)

Step Limitations ± 5 V Range ^ 1 V Range

Transition Duration 7 Settling Time

0.1% 19

0.02% 26

Equivalent Bandwidth 50

Droop /Flatness /Aberrations

After Settling <0.02 <0.02

ns

15 ns

22 ns

58 MHz

% FSR

Exponential Waveform Errors 0. 55 Vs 27.5 us

Deviation From Ideal Waveform

Max. 0.05*

rms 0.01*

0.02**

0.01**

% FSR

% FSR

*Not including 1st 10% of waveform. **Not including 1st 5% of waveform.

Duty Cycle Dependence

V2 Level Change With Duty Cycle (5-95%)

0=100 ms <0.02

Max. Final Change (30 s) <0.05

% FSR

% FSR

Ranges of Other Pulse Parameters:

. Pulse Repetition Rate - 153 Hz to 3.3 MHz; to 5 MHz with external clock

. Pulse Length - 20 ns to ~ 6 ms

. Duty Cycle - approximately 5% to 95%

48
6. OPERATING INSTRUCTIONS

Drawings of the front and rear panels of the NBS Step Generator control

unit are shovm in Figs. 6.1 and 6.2. The control unit should first be checked

out for correct operation before connecting the umbilical cable of the test

head to the front panel. The functions and voltages for connector J7 pins are listed in Table 2. The signals on pins 1-5 are generated under computer

control. After correct operation of the control unit has been verified,

connect the test head umbilical to connector J7 . Connector J2 (- 1 V range)

of the test head must be terminated in a 50 ^ impedance, either a coaxial

termination or the input impedance of the instrument under test. Connector J3

which accepts the timing signal, may be connected to either J5 or J6.

The primary address of the control unit has been set to 8. If the

address must be changed, the address switch is located on the IEEE-488

Interface Board (//3). To gain access, the front panel must first be removed,

and the board pulled from the chasis (see installation instructions sent with

instrument). Addresses 1-31 may be set with the address switch. The switch

is coded in binary negative true logic, where the MSB is position 1 and the

LSB is position 5. The secondary address of the control unit is 12, and is

hard-wired into the interface board.

The software for operating the control unit was written in BASIC 3.0

language for use with HP 9000 series 200 computers. The accompanying driver

software permits simple selection and entry of all programmable functions.

The basic features with user definable key numbers include:

Key Initiation routine. The step generator must be initialized before

using the remainder of the driver software. The initialization

parameters (for the 10 MHz internal clock) are:

- repetition rate is 50 kHz

- pulse length is 5.0 Ps (50 clock periods)

- transition is positive

- initial level is - 1 V - final level is + 1 V

- internal clock is selected

- programmable frequency and pulse length mode selected

- clock is enabled

49
Key 1 Reserved for future use.

Key 2 Sets the polarity of the transition, and the final and initial voltage

levels for the - 5 V range.

Key 3 Sets the repetition rate of the output step pulse train with a range of

153 Hz to 5.0 MHz using the internal clock. The software calculates

the closest allowed frequency to the one selected, based on the

requirement that the clock frequency be an integral multiple of the

selected frequency.

Key 4 Sets the pulse length (duration of the final level) in increments of

100 ns v7hen using the internal clock, otherwise in increments of the

external clock period.

Key 5 Sets the pulse length using a programmable delay line to obtain pulses

shorter than those obtainable with key 4, This function will have

been previously set with keys 7 or 8. The pulse length is set in 10 ns increments from 20 ns to 160 ns. When using this key, the pulse length

set by key 4 must be set to 200 ns or greater.

Key 6 Sets the pulse length and frequency by an integer procedure. The pulse

length is set by entering the desired number of clock periods of the

internal or external clock. The period of repetition is similarly set

by entering an integer multiplier (2-65,535) of the clock period.

Pulse lengths greater than the period of repetition should not be

entered.

Key 7 Displays on the screen the timing board functions and codes needed to

obtain these functions. Variables Ci and C2 are entered to obtain the

functions.

Key 8 Permits entering Ci and C2 without displaying the timing board

functions.

Key 9 Reserved for future use.

Key 10 Status. Gives the repetition rate, pulse length, transition polarity,

voltage levels, and clock selected (internal or external).

Key 11 Change the transition. The initial and final voltage levels are interchanged.

Key 12 Enables/disables clock.

Key 13 Change the final voltage level.

Key 14 Change the initial voltage level.

Keys 15-20 Reserved for future use.
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Table 2

Functions and Voltages for Connector J7 Pins

Values Given for V^ and Vg are Outside Limits

(See Note at Bottom of Table)

Pin No. Function/ Volt age

I & 2 V^/i 11 V

3 Vg/t 20 V

4 Neg. Pol. Relay Drive/TTl. Pulses approx. 5 ms wide

5 Pos. Pol. Relay Drive/TTL. Pulses approx. 5 ms wide.

6 & 7 N. C.

8 & 9 Supply/ + 5 V + 0.2 V

10 Supply/ - 5 V -t 0.2 V

II & 12 N. C.

13 & 14 V^ Return/0 V

15 Vg Return/0 V

16 Relay Returns /O V

17 Supply/ + 15 V ± 0.3 V

18 Supply/ - 15 V -t 0.3 V

19 ± 15 V Return/0 V

20 & 21 + 5 V Return/0 V

22 - 5 V Return/0 V

23 & 24 N. C.

Note: Under program control, V^ = 2 * V2 and

Vg = sign (V2-Vi)*( V2-V1I+8.3), where

* indicates multiplication, the sign function is

-1 if V2 > Vi, and is + 1 if

V2 < Vi . V2 = Vi is a disallowed condition.

53
7 . TESTING

7.1 Static Testing

The static errors of the NBS Step Generator system have been measured

over the full range at the step generator's output terminals using a precision

DVM. Offset and gain errors are corrected in the system software using data

from periodic calibration. The measured maximum independently based linearity

error at the V2 level is 0.008 percent of full-scale range. Figure 7.1 is a typical linearity error plot of V2.

The noise at the generator's output has also been measured at the - 5 V

output terminal, with the peak-to-peak value found to be less than 500 yV in a 40 MIlz bandwidth.

A Complete list of the static errors for both of the V2 and Vi levels of

voltage steps is given in Table 1 of section 5. SPECIFICATIONS. Also shown in

that table is the quantization uncertainty. This uncertainty is caused by the

lack of resolution in the programmable power supplies (V^, Vg), from which

V2 and Vi are derived.

If the device under test (DUT) has a 50 ^ input impedance, connector J2

(- 1 V range) should be connected to the DUT input without using a coaxial

termination (see section 3.1). Voltage uncertainty, caused by DUT input

impedance uncertainty, can be removed by static measurements of V2 and Vi.

Static measurements can be made at the DUT input with a DVM by placing a BNC

T-connector between J2 and the DUT input.

7.2 Measurement of Voltage Step Characteristics

A sampling voltage tracker (SVT), peak detector circuits, and a sampling

oscilloscope were used to characterize the output waveforms of the step

generator. The SVT and peak detector were used for settling time (ST)

measurements, and the SVT and sampling oscilloscope were used for transition

duration measurements. The sampling voltage tracker has been used previously

for similar measurements [2], [8], [11], [12], and [13].

The basic SVT consists of a high-speed sampling comparator and a voltage

integrator in a feedback loop, and can be represented by figure 7.2. The

strobe pulses, 5 to 10 ns wide, cause the input waveform f(t) to be sampled

(compared with the output voltage Vq of the integrator) at instants in time

coinciding with the trailing edges of these pulses. Assume that the period of

f(t) is T and that the value f(ti) is to be measured. Then, the strobe pulses

must be timed to sample f(t) at times ti , ti + T, ti + 2T* •

• . The result of

these comparisons is to drive Vp positive or negative until it nearly equals

the value of f(t) at the instants of comparison. If some other value of f(t),

say f(t2), is to be measured, f(t) must be sampled at times t2, t2 + T, t2 + 2T,***, etc.

The SVT was employed in the automatic measuring system shown in figure

7.3 with the delay generator programmed to have delay steps (increments) of

0.5 ns. The maximum allowable voltage range for the comparator in the SVT is

54
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m+6

i^

M-l

CM >

4-1

i-l U •

i-i "O

<u OJ>

>^

i-> td T-4 0)

>-. (-1 TO

tu !-i C

•H

u

I—1 u

<v

<4-l c E •H a 4-1 a CO

C^ c •H •H 4-1 c

4-1 CO •H 3

>4-l cr

CO 4=

OJ 4J

l-i •H

CO 5 3

cr #^

Cfi >

4-1 u~\

Cfi 1 CO

0)

i-I 4J

in

in (S inI in

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(±4

d0dd3 Ndd

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UJ CO

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cc -J H 3

CO a. ^

bOC

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w

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CO> 03

4-1 4J C 3 CO O. 4J C tn M e • •H CO

(U • 4-) CO /-s CO ,H ^ 2 U di o U bO i-i a: CO 4J U 4-1 CO

CO <-t M o ««

4J > O

0)

X 0) bO 4-1 bo

CO T* "O fHO "O bO > (V c

bO CO i-t C O. -H •H S CO iH O »-l O. O 4J e ^

CO 0)

CO "O ^

0) 4.*

O rH

•H

a x:

CO e 4J

CO CO -H

PQ CO ^

5. u. H- ^

lii tST

CM

bO

•H <

56
co

•H • tJ t-i •H o

00 J.I c to

CO 1-1 u 0) JJ c

0) 0) 00 u3 o03 <u

to XJ s

03

0) o J=

4J 4J

•ra 6

(U o

tou 3 U-l S tc

(U

a

4-1 <u m 4J >^ 00

OD

0)

M bo

(U CO ^ 4J o .H

to

O

M >

4-) IM

<u o

bO

ca 0) 4J o

iH •H o 4J > to •H o V4

1-( (U 4J 4-) <0 o s CO o Ur 4J CO 3 x: < o

en•bO

•H

1^

57
± 3 V. The TTL pulses applied to the output circuit are delayed 150 ns to

approximately match the minimum delay of the delay generator. Figure 7.4 is a plot of a -3 to + 3 V transition of the step generator, when loaded with 30 pF

capacitance, a typical input capacitance for waveform recorders. Based on tabulated DVM readings, the transition duration (10-90 percent rise time) was

11 ns and the STs to within ± 0.1 and - 0.02 percent of FSR were 35 and 39 ns,

respectively. When the load capacitance was decreased to 6 pF, the input

capacitance of the measuring system, the corresponding STs decreased to 19 and

26 ns. The transition duration decreased to 7 ns. ST measurements, using a peak detector, agreed with the above values to within - 10 percent.

The peak detector used for negative transitions is shown in figure 7.5.

Battery and diode polarities are reversed for positive transitions. The

voltage step (applied to the female BNC connector) is adjusted so that the

diode conducts during approximately the last 1 percent of the voltage

transition. This permits the latter part of a transition to be examined,

using a sensitive range of the oscilloscope.

The Schottky diode shown in figure 7.5 has minimum forward conductances

of 1 mA and 75 mA at forward voltages of 400 mV and 1 V, respectively. Its

shunt capacitance is less than 1 pF. The sensitivity of the detector is

calibrated by observing the change in oscilloscope deflection of the upper

trace of figure 7.6 caused by a known change in V^. Since the detector is

calibrated using a change in dc voltage, it can also be used to measure very

slowly charging voltages such as thermal drift (see section 7.4). The

self-heating change of the diode with to 100% duty cycle change causes a computed change in the detector output of 0.05 mV. With a 2 mV/cm scope

deflection sensitivity, this corresponds to 0.02 cm deflection change, which

is negligible.

Figure 7.6 shows a ST measurement of a 2 V transition from connector L,

using a peak detector with negligible input capacitance (~3 pF) and a calibrated sensitivity of 0.25 percent of FSR/cm. The sweep speed was

10 ns/cm. Since the minimum battery voltage is 1.4 V and the diode forward

drop is ~0.3 V, the ST of the 2V output was obtained using approximately a 0.3 to + 1.7 V transition.

Deviations from flatness (droop, aberrations, etc.) can be measured to

within approximately - 0.01% of FSR, using a peak detector. This quantity,

along with other voltage step limitations are summarized in Table 1 of

section 5. SPECIFICATIONS.

7.3 Exponential Waveform Errors

Exponential waveforms having transition durations (risetimes) of 0.55 Vs

and 27.5 Vs are available for dynamic linearity testing of waveform recorders,

using external capacitors. The deviation of thesQ waveforms from the true

exponential response has been determined using the sampling voltage tracker to measure the waveforms, and then fitting the data to an ideal model of the form

Y = Ao-Aie"^'^ using a nonlinear least-squares curve fitting routine. The

maximum values of the residuals of the curve fitting are given in Table 1 of

section 5.

58
CO+O

4-1 cn b-i 1 CU

CO

Oen

14-1 o x:

4-1 CO -H . ^

r-« -a

CU (U p -o 3 m

bC o

•H rH

14-1

d c <u •H ^& 3 •^ o u

x: o m 4J

c3 E K

(U q;

4-1

d

CO 0) >. bC w a

0) 0) x: 4-t 4J CO

t^ cu 43 ^4J -o

(U M-l u O • TO 0) ^ c O

1) o c d -H TO U 4J 4-) sC -H T^

CO o

4.)

C TO

O TOa

-1

M TO eu 4-) o

-*

ft r^•bO

•H

fa

59
FE

B Nr''(^HHh«T^^° °

MALE BNC

SCILLOSCOPE

I

Fig, 7.5 Peak detector using small H^ hearing aid batteries, "" 1.4 V

each. Reverse bias on the diode is determined by the number of

batteries employed. Shunt capacitance of the diode is less than 1 pF. The terminating resistance is typically less than 180 fi.

Fig. 7.6 Upper trace shows peak detector response to a +2 V transition of

Vl (lower trace). Sweep speed is 10 ns/cm and detector

sensitivity is 0.25 percent of 2 V FSR/cm. The Initial narrow

pulse in detector output is caused by shunt capacitance of the

detector diode (see Fig. 7.5). The waveform following this pulse

accurately represents the transition of V^.

60
The software used to compute these residuals employs an algorithm based on a Gauss-Newton approach [14].

A few practical difficulties are encountered in using the capacitor

modules. With the 0.55 Vs unit, ringing was significant for approximately the

first 50 ns of the transition. With the 27.5 Ms unit, some slumping of V^

was encountered during a transition. This effect was minimized by using

additional filter capacitance in the output circuit of the step generator (see

section 3.1).

7.4 Duty Cycle Dependence

In many high speed circuits, transient thermal imbalances often arise,

causing effects such as droop, or "thermal tails", and duty cycle dependence.

These effects have been measured for the step generator, using peak detector

circuits to discriminate very small changes in the step level following

switching. For these measurements, pulse repetition rates ranging from 1 kHz

to less than 10 Hz were employed. Changes of less than 0.02 percent in the

first 100 ms were noted in the final level when changing the duty cycle

between five and ninety five percent, for 10 V steps. The changes increased

to a maximum of less than 0.05 percent, after about 30s. For the latter

measurement, a single shot step and a scope with a free-running sweep were

used (see section 7.2 for detector characteristics).

61
8. CONCLUSIONS

A precision programmable step generator system, designed for use in

automated test systems, has been described. The step generator is intended

for testing waveform recorders and digitizing oscilloscopes with resolutions

of 8 to 10 bits and bandwidths up to 50 MHz. Fast, accurate settling,

together with the programmability of step levels, duty cycles, and repetition

rates provides the means for testing the dynamic and thermal characteristics

of waveform recorders and digitizing scopes. These characteristics include

step response, impulse response, and frequency response; transient

characteristics, including dynamic linearity, settling time, transition

duration, and transient thermal errors, can also be tested. All voltage

levels in the system are also programmable. These levels can be used for

static measurements to determine the offset, gain, linearity, and noise of the

waveform recorder or digitizing scope under test.

9 . ACKNOWLEDGEMENTS

The authors are grateful to P. S. Hetrick for AVT software and

calibration assistance, to M, E. Parker for packaging and technician help, and

to R. H. Palm for preparation of SO drawings and technician help. They would

also like to thank Ms. Y, Dube, Mrs. M. E. Sullivan, and Mrs. B. Meiselman for

their help in preparing this report.

62
10. REFERENCES

[I] T.M. Souders, D.R. Flach, and H.K, Schoenwetter , "Transient Response

Characterization of Waveform Recorders," Digest of Technical Papers,

5th IEEE Pulse Power Conference, Arlington, VA, pp. 352-355, June 1985.

[2] H.K. Schoenwetter, "Settling Time Measurements," NBS Special Publication

707, Digital Methods in Waveform Metrology , edited by B.A. Bell, Oct.

1985. (Oct. 1983 Seminar, NBS, Gaithersburg, MD)

[3] J.R. Andrews, B.A. Bell, and E.E. Baldwin, "Reference Flat Pulse

Generator," Nat. Bur. Stand. (U.S.) Tech Note 1067, Oct. 1983.

[4] G.J. Frye, "A Predictable Subnanosecond Pulse Generator," IEEE Trans.

Instrum. Meas. , vol. IM-17, no. 4, pp. 324-329, Dec. 1968.

[5] B.J. Elliott, "Picosecond Pulse Measurement of the Conduction Current

Versus Voltage Characteristics of Semiconductor Materials with Bulk

Negative Differential Conductivity," IEEE Trans. Instrum. Meas.,

vol. IM-17, no. 4, pp. 330-332, Dec. 1968.

[6] R.A. Lawton, N.S. Nahman, and J.M. Bigelow, "A Solid State Reference

Waveform Standard," IEEE Trans. Instrum. Meas., vol. IM-33 , no. 3,

pp. 201-205, Sept. 1984.

[7] J.R. Andrews, B.A. Bell, N.S. Nahman, and E.E. Baldwin, "Reference

Waveform Flat Pulse Generator," IEEE Trans. Instrum. Meas. vol. IM-32,

no. 1, pp. 27-32, Mar. 1983.

[8] H.K. Schoenwetter, "A Programmable Precision Voltage-Step Generator for

Testing Waveform Recorders," IEEE Trans. Instrum. Meas., vol. IM-33,

no. 3, pp. 196-200, Sept. 1984.

[9] Reference Manual, "4051 GPIB Hardware Support," Part No. 070-2270-00,

Tektronix, Inc., Beaverton, OR, Rev. July 1981.

[10] IEEE Std. 488-1978, "IEEE Standard Digital Interface for Programmable

Instrumentation," Revision of ANSI/IEEE Std. 488-1975, Institute of

Electrical and Electronics Engineers, Inc., 345 East 47th St., New York,

NY 10017.

[II] S.P. McCabe III, "A Sampling Voltage Tracker for Analyzing High Speed

Waveforms," M.S. Thesis, Univ. CA, Los Angeles, 1975.

[12] R.R. Castleberry and C.L. Robertson, "One-Chip DAC Delivers Composite

Video Signal," Electron. Des., pp. 105-112, Sept. 1, 1983.

[13] J. Halpert and M. Koen, "A Waveform Digitizer for Dynamic Testing of

High Speed Data Conversion Components," in Dig. 1983 Int. Test Conf .

,

(Philadelphia, PA), Oct. 1983.

[14] "Plot 50, Statistics Volume 4 (Nonlinear Problems)," Tektronix, Inc.,

Beaverton, OR, 1977.

63
APPENDIX A

The following paper describes a number of test methods for characterizing

waveform recorders, employing the NBS Step Generator in an automated system.

This paper is reprinted from the Digest of Technical Papers , 5th IEEE Pulse

Power Conference, Arlington, VA, June 1985.

64
TRANSIENT RESPONSE CHARACTERIZATION

OF WAVEFORM RECORDERS

T.M. Souders, D.R. Flach, and H.K. Schoenwetter

Electronic Instrumentation and Metrology

Electrosystems Division

National Bureau of Standards

Gaithersburg, MD 20899

Funded in part by: Sandia National Laboratories

Test methods for characterizing the transient response

of waveform recorders are presented, together with

typical test results. The methods, based on the use of a precision, programmable step generator developed

at NBS, are suitable for recorders having up to 10 bits of resolution and 100 MHz bandwidth.

Introduction

Waveform recorders are subject to a number of types of errors which can limit their ability to accurately

characterize transient signals [1, 2, 3, 4].

Principle among these are dynamic linearity errors,

impulse response and settling time limitations,

transient thermal errors, and time base jitter. An automated measurement system based on a precision

programmable step generator has been developed for

characterizing such errors in waveform recorders

having up to 10-bits of resolution, and bandwidth-: on the order of 100 MHz.

The test system is designed to output programmable

voltage pulses, with one well-defined transition per period, the beginning and terminating levels of which

are designated Vi and V2. (The transition from V2 to

Vi Is less well characterized, and is not relied upon for most measurements.) Either single shot or repetitive pulses can be generated, with the

repetition rate and duty cycle program-mable over many

orders of magnitude. The initial and final levels

defining the steps are each programmable within the

range of ± 1 V'for a 50 n termination and within

± 5 V for a high Impedance load. Voltage steps within

these ranges settle smoothly, with no overshoot, to within 0.1* of full scale range in less than 15 and

19 ns, respectively, for small load capacitance. The

corresponding 10-90 percent transition durations are approximately 6 ns and 7 ns. The voltage step

waveform has been characterized by independent means,

and has been shown to approximate a simple exponential

response. At high values of output capacitance, the more slowly rising waveform becomes sufficiently close

to an ideal exponential that it can be used for

dynamic measurements of linearity errors.

System Description

A block diagram of the complete test system is given

in figure 1. Overall control is provided via the IEEE 488 bus, for which an internal listener interface has

been provided. The waveform recorder under test is also Interfaced to the controller via this bus. To minimize load capacitance, the output circuit of the

step generator has been designed as a small hand-sized

package which connects directly to the Input terminals

in the same fashion as many sampling heads for

sampling oscilloscopes. The generator's power and

control signals are provided by a separate support

package via a flexible umbilical cable.

A functional diagram of the output circuit of the step

generator is shown In figure 2. A more detailed

IEEE 488

LISTENER INTERFACE —Tv

c IEEE 488 BUS

^

TIMING

REP. RATE DUTY CYCLE

V

CONTROLLER PROCESSOR

OAC-A

LEVEL Va

::= OAC-B

LEVEL Vt ^

POLARITY SELECT

RELAY DRIVE

OUTPUT

CIRCUIT WAVEFORM

RECO

UNOE

tl-UKM \ I ORDER jf

R TEST P

POWER

SUPPLIES

Fig. 1. Block diagram of test system.

Va from

DAC-A

TTL SIGNAL FROM TIMING

CIRCUIT

Vb from

DAC-B

Fig. 2. Simplified diagram of step generator output

circuit.

description can be found In reference [5]. Two output

ranges are provided: a *5 V range from output H, intended for high Impedance loads, and a *1 V range

from output L for 50 fl loads. When output L is used,

the 50 £J terminating resistor shown in the figure is actually the Input impedance of the test device;

otherwise, a 50 n coaxial termination is used. The

precision step is generated by switching the current

source from position 1 to 2. After switching, all active elements are isolated from terminal 1. Consequently, the transition is essentially an exponential waveform determined by the 125 n output

resistance and the total capacitance between terminal

H and ground.

As was previously mentioned, highly accurate exponential waveforms are produced by the generator at higher levels of output capacitance. These waveforms

are readily obtained by shunting output terminal H

65
with high quality capacitors contained in small in-line enclosures which can be connected directly to the output terminal H.

Dynamic Linearity Testing

Exponential waveforms having transition durations of

0.55 vs or longer are available for dynamic linearity

testing using external capacitors. The deviation of

these waveforms from the true exponential response has

been determined using a sainpling voltage tracker [6] to measure the waveforms, and then fitting an ideal

model of the form Y Ai - Aae^t to the data using a nonlinear least-squares curve fitting routine. The errors in these waveforms, as indicated by the

residuals of the curve fitting process, are less than

0.05% as shown in Table 1.

TABLE 1

Performance Specifications

Static Errors V2 Vi

Offset 0.01 1.0 % FSR Gain 0.01 1.0 % FSR Linearity (Max) 0.02 0.5 % FSR Noise (40 MHz BW) <500 <500 pV p-p

Step Limitations ±5 V ± 1 V

Transition Duration

Settling Time O.IX 0.02X

Equivalent Bandwidth

Droop/Abberations

After Settling

Exponential

Waveforms

19

2650

152258

ns

nsns MHz

<0.02 <0.02 % FRS

0.55 MS 27.5 ys

Deviation From

Ideal Waveform (Max) 0.05 0.01 % FSR

rms 0.01 0.006 % FSR

Duty Cycle Dependence

Vz Level Change With Duty Cycle (5X-95X)

0-100 ms <0.02 % FSR

Max. Final Change (30 s) <0.05 X FSR

Dynamic linearity measurements are made In the same way by digitizing the exponential waveforms with the

recorder under test. Once the waveform has been

recorded, the linearity errors are computed from the

residuals of the curvefit.

Results of two dynamic linearity tests, one performed

on a 10-bit, 60 MHz (sampling rate) recorder and the

other on an 8-bit, 200 MHz unit, are presented In figures 3 and 4. The first shows the linearity errors

(residuals) of the recorder tested with a waveform

having a 27.5 u% transition duration. The maximum and rms errors are 1.5 and 0.42 least significant bits

(LSB), respectively. Figure 4 shows the errors with

an exponential Input having a 0.55 us transition

duration. For this instrument, the maximum and rms errors are 1.3 and 0.46 LSB. In both cases, the ideal

maximum and rms error limits are 0.5 and 0.29 LSB,

respectively.

Dynamic linearity measurements of this type include errors resulting from ideal quantization uncertainty

and time base jitter, as well as differential and Integral linearity errors.

I.Sp

Fig. 3.

1.5

20 30

TIME (|t«)

Dynamic linearity errors of 10-bit, 60 tfiz recorder with exponential input signal having

27.5 us transition duration.

2.0 TIME (|i«)

Fig. 4. Dynamic linearity errors of 8-b1t, 200 MHz recorder with exponential input signal having

0.55 vs transition duration.

Step Response Measurements

Measurements of step, Inpulse, and frequency response,

as well as transition duration and settling time can.

In principle, all be made directly using the step

generator, simply by recording the response to a step,

and calculating the desired parameters from the

recorded data. In practice, however, two points must

be taken Into consideration. First, the sampling rate

of the test recorder limits the effective bandwidth of

the measurement. Because of aliasing errors which

result when using a wideband input step, this

limitation makes it Impossible to characterize the

66
1024 f

512

250 500

TIME (m)

760 1000

Fig. 5. Step response of 10-bit, 60 MHz recorder,

measured using equivalent time method

(0.98 ns / sample).

290 soo

TIME (n») 7S0 1000

F1g. 6. Impulse response calculated from step

response data of figure 5.

frequency response with reasonable accuracy. The

second point is that the input step itself has finite

equivalent bandwidth (see Table 1), and for very fast

recorders, its frequency response may not be flat

enough to ignore.

The sampling rate limitation can often be overcome by

extracting equivalent time sampling data from a single

record, provided that the repetition rate of the input

step is selected appropriately, as follows. Set the

ratio of the sample rate, fg, to the step repetition

rate fp, so that (N-l) < (fg/fr) < N, where N Is some integer,

phaselocked.

1.0

thus not allowing fj and f^ to be

With the step generator, this is accomplished using an external, programmable frequency synthesized source.

If, under these conditions, every Nth sample is taken

from the record of length M, then the resulting M/N

data points will represent equivalent time samples of the original waveform. The exact repetition rate

needed to obtain one complete period sampled in equivalent time can be calculated, given a choice of

N, from

% ' (fj / N) (N/M + 1).

Note that N/M is the reciprocal of the number of

samples that will be in the final record, so that this

ratio determines the number of equivalent time samples

in one period of the input step. It can be seen from

this relationship that the measurement bandwidth is directly proportional to the record length. The

interval between the equivalent time samples is given

by

At - N(l/f^ . 1/Nf^).

Problems imposed by the limited bandwidth of the step

generator can be overcome to some extent, by

mathematically deconcolving its response from the

recorded response of the waveform recorder under test

[7]. The ability to accurately measure the input step

using independent, equivalent time techniques makes it possible to at least double the effective bandwidth of measurements made with the step generator. In a future paper, the application and results of deconvolutlon techniques will be presented.

Some typical test results are given In figures 5-8 for

a 10-bit, 60 MHz recorder. These plots give. In order, recorded step response, impulse response,

frequency response (showing the computed 3 dB point at

0.9

100 FREQUENCY (MHz)

200

Fig. 7. Frequency response calculated from impulse

response data of figure 6. The bandwidth

(3 dB point) thus measured is 17 MHz vs.

15 MHz claimed by the manufacturer.

17 MHz), and settling with apparent undershoot of approximately 8 LSBs. Equivalent time sampling was

used for all measurements except settling time, with

an equivalent sampling interval of 0.98 ns.

To illustrate the utility of such data in predicting

the response of a particular waveform recorder *i*ien digitizing real-world signals, figure 9 presents an example in which a double exponential waveform is considered. The figure shows an ideal waveform

(0.125/10 us rise/fall time) together with the

response error predicted by convolving it with the

measured impulse response. Distortion, causing error

In the peak value on the order of 7 LSBs, is plotted

in figure 9-b. To arrive at an overall estimate of the errors which would likely occur when digitizing

such a candidate waveform, the dynamic linearity

errors, as presented in figure 3, should also be

Included.

Testing of Transient Thermal Response

It is common practice to calibrate waveform recorders

using static measurement methods. These data are used, if deemed necessary, to correct the actual data

obtained when transient waveforms are recorded. In fact, such a process is used in the self calibration

67
1010

3 1000

090

oso

^r-«^*^^^

rw-rfjuttrnmutmamtm

970 I—Ll 1 1 1 I I I I I I

I I I I I I 1.07 2.13 3.20 4.27 6.33 6.40 7.47 8.63 TIME Un)

Fig. 8. Expanded view of step response of 10-bit,

60 Wz recorder, showing 8 LSB undershoot and settling time of approximately 6 ps to 1 LSB.

1.0 -

I

0.5 -

* 1.0 1-

t o.s\-

B

<" -0.6 o

wU -1.0 o

lU

ac

»• -1.6

-2.0 U

0.63 1.07 H 1 1 1

1 2.13 2.67 3.20 TIME (|m)

- Error lr« p«ak valu* s 0.76%

3.73 4.27

(b)

Fig. 9. Ideal double exponential input waveform with

0.125/10 ws rise/fall time (a), and predicted

response error (b).

CD(0

O

BC

tr

UJ

TIME (ps) 128 256 384 512 640 768 896 1024

-20 i

Fig. 10. Transient thermal response of 10-b1t, 20 MHz

recorder.

routines of several commercial recorders. Unfortunately, even for very slow events, the waveform

recorder will likely respond differently to transient

signal levels than to dc levels, primarily because of internal transient thermal imbalances which can have

rather long time constants. Because these effects are related to signal power, they are nonlinear and thus cannot be represented simply by a transfer function.

The magnitude of these effects are easily measured

with the step generator however, by first recording

one half cycle of a low frequency square wave, and then subtracting from it the record of a dc signal

having the same value as the recorded level of the square wave. If transient thermal errors are present,

they will appear in the resulting difference between

the two records. Figure 10 shows the results of such

a test in which a 500 Hz square wave of nearly full scale amplitude has been used. The recording of the upper level of the square wave has been subtracted

from a recording of the equivalent dc level. Note the initial overshoot of about 30 ps duration, followed by

the long, slowly decaying tail. The peak errors are 12 LSBs.

Conclusions

The step response test system that has been described

is capable of accurately measuring many error parameters that are important in assessing the overall

transient response of waveform recorders. Fast, accurate settling, together with the programmability

of step levels, duty cycles, and repetition rates provides the means needed to measure and separate both

linear and nonlinear effects, and to provide

information relevant to both the time and frequency

domains.

Additional work under way in this area includes the

development of a faster generator test head, with a goal of a 2 ns transition duration and settling to 0.1% in 8 ns. This capability would permit the measurement of 10-bit recorders having bandwidths as high as 350 MHz.

References

[1] D. R. Flach, "Steady-State Tests of Waveform

Recorders," NBS Special Publ. 643, June 1982.

[2] B. E. Peetz, "Dynamic Testing of Waveform Recorders," IEEE Trans. Instrum. Meas., vol. IM-32,

March 1983.

[3] R. A. Malewski, T. R. McComb, and M. M. C. Collins, "Measuring Properties of Fast Digitizers

Employed for Recording HV Impulses," IEEE Trans. Instrum. Meas., vol. IM-32, March 1983.

t4] K. Schon, H. Korff, and R. Malewski, "On the

Dynamic Performance of Digital Recorders for HV Impulse Measurement," Fourth International

Symposium on High Voltage Engineering, paper

66.05, Athens, September 1983.

[5] H. K. Schoenwetter, "A Programmable Precision

Voltage-Step Generator for Testing Waveform

Recorders," IEEE Trans. Instrum. Meas., vol.

IM-33, no. 3, September 1984.

[6] S. P. McCabe III, "A Sampling Voltage Tracker for

Analyzing High Speed Waveforms," M. S. Thesis,

U. of CA, 1975.

[7] N. S.Nahman and M. E. Guillaume, "Deconvolutlon

of Time Domain Waveforms In the Presence of Noise," Nat. Bur. Stand. (U.S.) Tech. Note 1047. 68
APPENDIX B

Appendix B contains the documentation for the VSG driver program. This

program is written in the Hewlett-Packard BASIC 3.0 language. Pages 60

through 68 contain the program listing. A brief description of each numeric

variable is given in pages 69 to 71, and a brief description of each string

variable is given on pages 71 and 72. The line labels used in the program are listed on pages 72 through 74, with a short description of the function

performed when that section of the program is executed. If a line label is

executed when a softkey is pressed, this is indicated by the key number in

brackets below the line label. Pages 75 through 87 contain flow charts for

each of the defined softkeys and for GOSUB 2500, the main routine used to

calculate digital code for the DACs on the DAC/OA board.

69
18 ON KEY 3

ZZ ON KEY 4

ZB ON KEY 5

30 ON KEY E

34 ON KEY 7

ftppendix B

VSG Driver Program

t REM DRF VSGDRIVER; 07/1B/8G; DISC D, NATIONAL BUREAU OF STANDARDS

Z Start: \ Program remains in a loop at line 80, label Loop

3 OFF KEY

10 ON KEY LABEL "INITALIZE" GOSUB Init I Initalize the support unit

14 ON KEY Z LABEL "TRS,VZ,V1" GOSUB Trvls I Set transition, initial, final level

LABEL "VSG freq" GOSUB Vsgfreq ! Set repetition rate of VSG

LABEL "PULSE LENGTH " GOSUB Pulse_length I Set pulse duration

LABEL "DELAY LINE" GOSUB Delayline I Set duration uith delay line

LABEL "INTEGER" GOSUB Integer I Set Pulse_int and Freq_int

LABEL "FUNCTIONS" GOSUB Card 1 Displays functions on timing card

38 ON KEY 8 LABEL "ENTER C1,CZ" GOSUB ClcZ I Enter timing control characters

4Z ON KEY 9 LABEL " Menu Z

" GOTO MenuZ I To next menu

44 ON KEY 10 GOSUB Status ! Display status of VSG parameters

4G ON KEY 1 1 GOSUB Changetr ( Suitch transition, voltage levels remain same

50 ON KEY IZ GOSUB Ckon_off \ Cycle clock. ON/OFF or OFF/ON

5Z ON KEY 13 GOSUB Ch_f_vl I Enter neu final voltage level

54 ON KEY 14 GOSUB Ch_i_vl ! Enter neu initial voltage level

80 Loop: GOTO Loop I Program remains here until a Soft Key is pressed

90 PAUSE

100 Init: 1 setup voltage step generator parameters: Frequency= 50 KHz,

105 I pulse length 50 periods (5.0 uS

>

110 Vsg=7081Z ! IEEE-488 address of vsg support unit

115 REM

1Z0 CLEAR Vsg ! Used to reset chip address counter to zero, must aluays be

1Z1 I executed before sending neu data strings to the boards.

IZZ ! In this program, it is normally executed after a command

1Z3 1 string is sent

1Z5 OUTPUT Vsg;"lZ" I Turn the clock off

130 CLEAR Vsg I Chip address counter to zero

135 Clear_crt$=CHR${Z55)iCHR$(75) ! Used to clear CRT screen

140 REM

145 REM

150 REM Set frequency to Freq/100 (100 KHz), pulse length 50 periods

155 OUTPUT Vsg;"10AC9FFDCFF" I Timing board string

1B0 CLEAR Vsg I Chip address counter to zero

1G5 OUTPUT Vsg;" 10"; ! Clock on

170 CLEAR Vsg

174 OPTION BASE 1 I Louer bound of arrays is one

175 DIM Bindac_hJ[3] ,Bindac_a$[31 ,K$t31 ,DacSt71 ,Time$[ 111

185 RESTORE 190

190 DATA -1 ,1 ,1 ,"0GGGC3C" I Data for inital izat ion

195 DATA "XKX" ,"10AC9FFDCFF",1 ,"BGG","C3C",100,50

Z00 READ Init_vl ,Final_vl ,Tr,Dac$, X$, Times, Tr,Bindac_a$,Bindac_bS

Z10 READ Freq_int,Pulse_int

ZZ5 REM Set positive transition

Z30 GOSUB Pos tr

70
Z35 REM Set initial level -1 volt, final level +1 volt

Z40 OUTPUT Vsg;Dac$ I Uord string to DAC/Oft board

Z45 CLEAR Vsg

Z50 RETURN I Exit Init

450 REM

455 REM PRINT "1=+ TR. Z= -TR, 3=N0P , 4=N0P"

4B0 INPUT "ENTER CONTROL CHARACTER=" ,Tr ! Produce a pulse at output of

4G1 REM Q1, QZ, Q3 or Q4. Only Q1 and QZ connected to outside

463 IF Tr<l THEN 4B0 I Error check for valid Tr

4B4 IF Tr>4 THEN 4G0 I " 4G5 IF Tr=l THEN GOSUB Pos_tr ! Positive transition pulse

470 IF Tr=Z THEN GOSUB Neg_tr ! Negative transition pulse

475 IF Tr=3 THEN GOSUB Pulse_q3 I Not connected off the board

480 IF Tr=4 THEN GOSUB Pulse_q4 ! Not connected off the board

485 RETURN ! Exit subroutine 4B0

500 Pos_tr: I Set positive transition on vsg

50Z OUTPUT Vsg;"Zr'

504 CLEAR Vsg

50G OUTPUT Vsg;"Z0"

508 CLEAR Vsg

510 RETURN I Exit Pos_tr

5Z0 Neg_tr: I Set negative transition on the Vsg

5ZZ OUTPUT Vsg;"ZZ"

5Z4 CLEAR Vsg

5ZE OUTPUT Vsg;"Z0"

5Z8 CLEAR Vsg

530 RETURN \ Exit Neg_tr

540 Pulse_q3: I NOP, not used, produces a pulse at Q3

54Z OUTPUT Vsg;"Z4"

544 CLEAR Vsg

54G OUTPUT Vsg;"Z0"

548 CLEAR Vsg

550 RETURN ! Exit Pulse_q3

5G0 Pulse_q4: I NOP, not used, produces a pulse at Q4

5GZ OUTPUT Vsg;"Z8"

5G4 CLEAR Vsg

5GB OUTPUT Vsg:"Z0"

5G8 CLEAR Vsg

570 RETURN I Exit Pulse_q4

B00 Card: \ Display functions available on the timing card

G10 OUTPUT Z;Clear_crt$; I Clear CRT screen

Et5 PRINT " #*#»#»«»»*#»###TIMING CARD FUNCTIONS**» »»** **»**»"

GZ0 PRINT "CTRL CHARACTER FUNCTION SELECTED"

INTERNAL CLOCK"

EXTERNAL CLOCK"

PROG. FREQ S. PULSE LENGTH"

OUTPUT FREQ. DIVIDER COUNTERS"

PULSE LENGTH SET BY DELAY LINE KEY « 5"

G50 PRINT "Cl=l,CZ=4 INITIAL LEVEL OUTPUT " G55 PRINT "Cl=1.CZ=a FINAL LEVEL OUTPUT"

GB0 PRINT "Cl=Z,CZ=0 TURN CLOCK OFF"

GGZ ClcZ: \ Enter CI & CZ uiithout displaying timing card menu

GB5 INPUT "ENTER CONTROL CHARACTERS C1,CZ",C1,CZ

G70 REM PRINT CI .CZ

71

BZ5 PRINT " C1=0

G30 PRINT " Cl = l G35 PRINT " CZ=0

G40 PRINT " CZ=4

G45 PRINT " CZ=1Z
G75 C3=C1+CZ I Conpu-fce character for digit Z in TimeS. This is a Hex digit

G80 Xx$=IVflL$(C3,lG)

B81 PRINT Times I Uord string for Timing board

G82 PRINT Xx$ I Value of C3 in Hex

G85 Time$=TimeSt 1 ; 11 &Kx$[41 &TimeS[ 31

G8G PRINT TimeS I Uord string for Timing board output to support unit

G90 OUTPUT Vsg; Times • Starts neu function defined by CI and CZ

G95 CLEAR Vsg

700 RETURN I Exit Card or ClcZ:

7Z5 Ckon_off: I Cycle clock ON/OFF or OFF/ON

730 CkS=Time$[2; 11 I Hex digit in position Z contains the clock ctrl hit

735 Pos=IVAL(CkS,1G)

740 REM Complement the clock ctrl bit (Znd bit) in position Z 745 Posl=BINEOR(Pos,Z)

750 CkS=IVALS(Posl , IG) \ Hex digit 4 contains neu clock ctrl bit

755 Time$=TimeS[ 1

; 1 1 &CkS[41 &Time$[ 31

7G0 OUTPUT Vsg; TimeS • Neu uord string to Timing board

7G5 CLEAR Vsg

775 RETURN I Exit Ckon_off

1500 Ck_off: ! Turn clock off if on, do not change other bits in position Z 1505 Ck_onS=Time$[ 1 ;Z1 • Save for clock turn on

1510 Ck 1 S=Time$[ Z ; 11 I Get clock control character

1520 Cklctrl=IVAL(CklS,1G)

1530 CkZS=IVAL$(Ck1ctrl,Z) \ Bit 15 contains the clock control bit

1540 IF CkZSC 15? n="l" THEN 1G00 ! Clock off, no action required

1550 CkZctrl=BINEOR(Cklctrl,Z) • Complement the clock control bit

15G0 CkZ$=IVALS(CkZctrl ,1G) ! Clock control hex character uith clock bit off

1570 Ck3$="r'&CkZS[41 \ Assemble string

1580 OUTPUT VsgiCk3$; ! Turn clock off, string sent to Timung board

1590 CLEAR Vsg

1G00 RETURN I Exit Ck_off

Z000 Trvls: ! Set transition, initial, final voltage level

Z010 REM DAC Va uith amplifier Ua; -11/+11 volts; Ctrl=1 Gain

Z0Z0 REM DAC Vb uith amplifier Ub; -Z0/+Z0 volts; Ctrl=Z Offset

Z030 REM Tr=l positive transition; Tr=Z negative transition

Z040 REM ENTER TRANSITION, FINAL, INITIAL VOLTAGE LEVEL

Z050 INPUT "ENTER Tr , Final_vl, Init_vl=" ,Tr ,Final_vl ,Init_vl

Z0G0 IF Tr=l OR Tr=Z THEN Z100 I Valid entry for transition uhen true

Z075 BEEP Z00,.Z

Z0e0 PRINT "Tr=";Tr;" IS ILLEGAL ENTRY, Tr=1 IS + TRANS, Tr=Z IS - TRANS"

Z090 GOTO Trvls I Reenter the transition

Z100 Final_vlrg: I Check range of final voltage level for +/- transition

Z110 IF Final_vl<=-4. 9975585 OR Final_vl>4. 9975585 THEN Z 1 30

Z1Z0 GOTO ZZ00 ! This line executed uhen voltage valid

Z130 REM Final voltage range error statement

Z140 BEEP Z00,.3

Z150 PRINT "FINAL VOLTAGE LEVEL= ";Final_vl;" VOLTS IS OUT OF RANGE"

Z1G0 PRINT "FINAL VOLTAGE RANGE IS -4.9975585 TO +4.9975585 VOLTS"

Z170 GOTO Z04O I Final voltage level not valid, reenter another value

ZZ00 Init_vlrg: I Check range of initial voltage level for +/- transition

Z210 IF Tr=l THEN ZZ50 •. Check range of initial voltage level for + transition

Z220 IF Tr=Z THEN Z350 1 Check range of initial voltage level for - transition

ZZ50 REM Positive transition, initial voltage level check

Z2B0 IF Init_vl>=Final_vl THEN ZZ90 I Invalid voltage uhen true

72
ZZ7® IF Init_vl<-4. 9975585 THEN 2310 I Invalid voltage uhen irue

ZZ80 GOTO Z430 ! Passed all voltage checks, compute DAC codes, etc.

ZZ90 PRINT "INITIftL VOLTAGE LEVEL>= FINAL LEVEL NOT ALLOUED ON + TRANSITION"

ZZ95 BEEP ZOO,.

3

Z300 GOTO Z040 I Voltage levels not valid, enter neu ones Z310 PRINT "INITIAL VOLTAGE=" ; Init_vl ; " IS < -4.9975585 VOLTS, OUTSIDE OF RANGE

Z315 BEEP Z0O,.Z

Z3Z0 GOTO ZO40 I Voltage levels not valid, enter neu ones Z350 REM Negative transition, initial voltage level check

Z355 IF Init_vl>4. 9975585 THEN Z410 I Invalid voltage uhen true

Z3B0 IF Init_vl<=Final_vl THEN Z390 I Invalid voltage uhen true

Z380 GOTO Z500 •. Passed all voltage checks, COMPUTE dac codes, etc.

Z390 PRINT "INITIAL VOLTAGE <= FINAL VOLTAGE LEVEL NOT ALLOUED ON - TRANS."

Z395 BEEP Z00,.Z

Z400 GOTO Z040 ! Voltage levels not valid, enter neu ones Z410 PRINT "INITIAL VOLTAGES > 4.997585 ARE OUTSIDE OF RANGE"

Z415 BEEP Z00,.Z

Z4Z0 GOTO Z040 ! Voltage levels not valid, enter neu ones Z430 REM • End of voltage level checks

Z440 GOSUB Z500 • To output of the voltages

Z450 RETURN I Exit Trvls

Z500 Oacv_s: I Compute voltages and binary codes needed for DAC Va & Vb outputs

Z510 GOSUB Z800 \ DAC Vb voltages and code calculations

Z5Z0 GOSUB Z900 \ DAC Va voltage and code calculation

Z530 REM Compute DAC codes

Z540 REM GOSUB 3000 I Can be used as an entry if Ctrl is set for calculating a

Z541 REM DAC VOLTAGE

Z550 PRINT "Init_vl= ";Init_vl

Z5B0 PRINT "Final_vl =";Final_vl

Z570 GOSUB 1500 ( Turn clock off

Z580 OUTPUT Vsg;DacS ! Output neu Va and Vb voltages

Z590 CLEAR Vsg

ZG00 OUTPUT Vsg;Ck_on$; I Turn clock on

ZB10 CLEAR Vsg

ZGZ0 IF Tr=l THEN GOSUB 500 ! Set positive transition

ZG30 IF Tr=Z THEN GOSUB 5Z0 I Set negative transition

ZG33 PRINT Dac$ 1 String sent to DAC/OA board

ZB40 RETURN ! Exit Trvls

Z800 Dac_vb: I DAC Vb voltage calculation

Z810 REM Output at amplifier Ub, -Z0/+Z0 volts, Ctrl = Z Z8Z0 Xdacb=-SGN(Final_vl-Init_vl)»(ABS(Final_vl-Init_vl)+8.3) 1 Mult by -0.5

Z8Z1 REM for DAC Vb output voltage

Z830 Xdacbl=-.5»Kdacb I Save if needed later

Z840 Vdac='-.5*Xdacb \ Voltage for DAC code calculation

Z850 Ctrl^Z I DAC Vb calculations

Z8B0 GOSUB 3000 \ Do DAC code calculations

Z870 RETURN I Exit Dac_vb

Z900 Dac_va: ! DAC Va voltage calculation

2910 REM Output at amplifier Ua of -tl/+ll volts

Z9Z0 Ydaca=1.818181*Final_vl I DAC A OUTPUT V

Z930 Ydacal=-Ydaca 1 Save IF NEEDED LATER

Z935 Vdac=-Ydaca I Voltage for DAC code calculation

Z940 Ctrl=l I DAC Va calculations

73
2950 GOSUB 30^0 I DflC code calculation

Z9G0 RETURN I Exii Dac_va

3000 Code: ( Compute complementary offset binary codes for the tZ hit DAC'S

3010 REM Entry voltage is variable Vdac

30Z0 REM Ctrl= Z for DAC Vb u/ Ub output +/- Z0 volts

3030 REM Ctrl= 1 for DAC Va u/ Ua output +/- 11 volts

3040 REM

3050 Vdac3=Vdac+10 \ Add 10 volt offset so no minus values

30G0 Lsb_s=Vdac3»Z04.8+. 4999999 I Put Vdac3 in LSB's of a IZ bit DAC

30GZ IF Ctrl=1 THEN Rau_lsh_l=Lsb_s ! Save for use in removing digitizing

30E3 IF Ctrl=Z THEN Rau_lsb_Z=Lsb_s I digitizing errors

3070 Lsb_s=INT(Lsb_s) ! Digitize Vdac3

3090 REM Convert LSB's to Hex code

3100 Hex1$=IVAL$(Lsb_s,lB)

3110 X«=Hexl$lZl ! Use first 3 Hex digits (IZ bit DAC ' s

)

3115 X$=REV$(X$) ( Reversal of digits needed to match DAC registers

3120 IF Ctrl=l THEN GOSUB Bindaca I Binary code for DAC Vb

3130 IF Ctrl = Z THEN GOSUB Bindacb •. Binary code for DAC Va

3140 RETURN I Exit Code

3150 Bindacb: ! Binary code for DAV Vb, Ctrl=Z

3157 V$=XS

3158 V$=TRIM$(V$>

3150 Bindac_b$=X$

3170 Dac$="0"&Bindac_a$&V$ ! Assemble string for DAC/OA board

3180 RETURN I Exit Bindacb

3Z00 Bindaca: '. Binary code for DAC Va, Ctrl=l

3Z10 Bindac_a$=X$

3Z20 Dac$="0"iBindac_a$&V$ 1 Assemble string for DAC/OA board

322Z PRINT Dac$;"DAC A"

3Z30 RETURN I Exit Bindaca

4000 Vsgfreq: •. Enter Vsg drive frequency based on 10 MHz internal clock

4010 PRINT "CLOCK FREQUENCY RANGE 153 TO 3.333 MHZ UITH 10 MHZ INTERNAL CLOCK"

4011 PRINT '"HIGHEST SQUARE FREQUENCY IS Z,5 MHZ UITH INTERNAL CLOCK"

4020 INPUT "ENTER VSG DRIVE FREQUENCY IN HZ" ,Vsgf reql

4030 REM Vsgfreql is user entered frequency, calculations belou for closest

4031 REM frequency system can output. Clock frequency is divided by an integer

4032 REM to produce the Vsg drive frequency.

4040 Freq_int=INT(( 10000000/Vsgf reql )+. 4999999) I Closest Vsg drive freq

4041 REM positive integer to the user entered freq. INT/EXT clock divided by

4042 REM this integer. Minimum value can be entered is 3

4050 IF Pulse_int>=Freq_int THEN 4090 I Go to error statement

40G0 PRINT "CLOSEST Vsg FREQUENCY IS "; 10000000/ Freq_int

4070 REM

4080 GOTO 4Z00 I Passed error statements, output freq to Vsg

4090 REM Error statement, pulse length > Vsg freq

4095 BEEP Z00,.Z

4100 PRINT "PULSE LENGTH TOO LONG FOR Vsg FREQUENCY"

4110 PRINT "PULSE LENGTH=" }Pulse_int ; " PERIODS"

4120 PRINT "MAX Vsg FREQUENCY"" ;( 10000000/ (Pulse_int+1 )

)

4130 GOTO 4010 1 Reenter the Vsg frequency

4140 REM Divide the INT/EXT clock frequency by an integer to find Vsg drive

4141 REM frequency

4150 REM Max integer is E5535, positive values only

4160 REM Time$= " 10YXXXXGGGG"

74
4170 REM No error statement in this routine

4180 INPUT "INT/EXT CLOCK FREQ DIVISOR (INTEGER, MAX= G5535)= ".FrecLint

4190 REM

4Z00 REM Target from 4080, do calculations to output Vsg freq

4Z10 REM

4ZZ0 Freq_intZ=G553G-Freq_int 1 Put in format to load registers in support unit

4Z30 OUTPUT Vsg;"lZ"; I Turn clock off

4Z40 CLEftR Vsg

4Z50 F$=DVALS(Freq_intZ, IB) I Compute string for Timing board

4Z51 FS=FSt51 I Last 4 digits contain the clock digits

4ZG0 FS=REV$(F$) I Formatting for output to registers

4Z70 Time$=Time$t 1 ;31iF$&.Time$t8] 1 Assemble string for Timing board

4Z80 OUTPUT Vsg; Time* I Output to Timing board

4Z90 CLEAR Vsg

4300 RETURN ! Exit Vsgfreq:

5000 Pulse_length: 1 Set pulse length uith 10 MHz internal clock

5010 REM Pulse length is duration of final voltage level

50Z0 INPUT "ENTER PULSE LENGTH IN NANOSECONDS (UNITS OF 100)=" ,Plength

5030 Pulse_int = INT((Plength+49. 99993 )/100)-l I To nearest 1(2)0 nS; -1 added for neu timing board ( 10-Jul-8G)

5040 IF Pulse_int>=Freq_int THEN 5070 I To error statement

5050 Pulse_intZ=G553G-Pulse_int ( Format for the output registers

50G0 GOTO 5170 I To output pulse length to Vsg

5070 REM Error statement, pulse length > clock frequency

5075 BEEP Z00,.Z

5080 PRINT "PULSE LENGTH TOO LONG FOR CLOCK FREQUENCY"

5090 PRINT "FREQUENCY=": 10000000/Freq_int

51(2)0 REM

5110 PRINT "MAXIMUM PULSE LENGTH^" ; ( Freq_int- 1 ) l<2Xa; " NANOSECONDS"

51 Z0 GOTO 50Z0 ! Reenter the pulselength

5130 REM Enter the length of the pulse < freq division

5140 REM Pulse length = integer*clock period

51B0 REM

5170 Pulse_intZ=G5535-Pulse_int ! Format for timing board registers

5180 OUTPUT Vsg;"lZ"; 1 Turn clock off

5190 CLEAR Vsg

5Z00 P$=DVAL$(Pulse_intZ,lB) 1 Compute the Timing board string

5Z01 P$=P$[51 I Last 4 digits contain the pulse length information

5Z10 PS=REV$(P$) ! Reverse the digits to match the timing board registers

5ZZ0 Time$=Time$[ I ;71&.PS I Assemble Timing board string

5Z30 OUTPUT Vsg; Time* t Output to timing board

5Z40 CLEAR Vsg

5Z50 RETURN ! Exit Pulse_length:

5500 Integer: I Enter the pulse length & Vsg drive uith positive integers

5510 INPUT "FREQ DIVISOR, PULSE LENGTH CLOCK PERIODS" ,Freq_int ,Pulse_int

55Z0 Freq_int=INT( Freq_int ) \ Minimum value Is +3

5530 Pulse_int=INT(Pulse_int ) I Minimum value is +1

5531 Pulse_int=Pulse_int-t I Needed for neu timing board (15-JUL-8B> the

5532 I minus one 5540 IF Pulse_int>=Freq_lnt THEN 1 To error statement if true

5550 BEEP Z00,.Z

55G0 PRINT "ERRORl FREQ DIVISOR <= CLOCK PERIOD, MUST BE >" 5570 GOTO 5510 I Enter neu pulse length

5580 END IF

75
5590 GOSUB 517© 1 Enter pulse length

5G00 GOSUB 4ZZ0 I Enter Vsg drive freq

5G10 RETURN \ Exit Integer : G0®0 Delayline: \ Set pulse length uith programmable delay line

6001 IF Pulse_int<Z OR Freq_int<3 THEN 1 Error condition if true for P.D.L.

G00Z PRINT "PULSE LENGTH MUST BE GREATER THEN 1 CLOCK PERIOD UHEN USING"

G003 PRINT "PROGRAMMABLE DELAY LINE AND CLOCK FREQUENCY DIVISOR GREATER THEN 3"

G004 BEEP Z00,,Z

G005 GOTO G070 1 Execute return, need to change timing board parameters

G00B END IF

G010 PRINT "PULSE LENGTH IS PROGRAMMABLE IN IB TEN NANOSECOND STEPS 1-lG"

GOZ0 INPUT "STEP SIZE 1 TO 1G=" ,Delay_line

G030 Xx 1$=IVAL$( Delay_line-1 , IB) I Subtract one so range is one Hex digit

G040 Time$=Time$[ 1 ;Zl&Xxl$[41&TimeS[41 ! Last digit of Xx 1 $ contains P.D.L. code

G050 OUTPUT Vsg; Times 1 Output delay line data to Timing board

G0G0 CLEAR Vsg

G070 RETURN ! Exit Delayline

G400 Status: I Print out the current Vsg system parameters

B410 OUTPUT Z;Clear_crt$i

G4Z0 PRINT "++++44+++++++ CURRENT VSG PARAMETERS +++++++++++++++++++++"

G430 SELECT Time$lZ;ll \ Print out the current function on the timing card

G440 CASE "0"

G450 PRINT "INTERNAL CLOCK ON"

G4G0 PRINT "PULSE LENGTH SET USING PROGRAMMABLE COUNTERS"

G470 CASE "1"

G480 PRINT "EXTERNAL CLOCK ON"

6490 PRINT "PULSE LENGTH SET UITH PROGRAMMABLE COUNTERS"

6500 REM

G510 CASE "Z"

G5Z0 PRINT "TURN INTERNAL/EXTERNAL CLOCK OFF"

G530 REM

6540 CASE "5"

6550 PRINT "INTERNAL/EXTERNAL CLOCK OFF"

6560 PRINT "OUTPUT SET AT INITIAL LEVEL"

6570 CASE "9"

6580 PRINT "INTERNAL/EXTERNAL CLOCK OFF"

6590 PRINT "OUTPUT SET AT FINAL LEVEL"

6G00 CASE "C"

GG10 PRINT "INTERNAL CLOCK ON"

GGZ0 PRINT "PULSE LENGTH SET BY DELAY LINE"

6630 D=IVAL(Time$[3; 11 ,1G>

6G40 PRINT "PULSE LENGTH=" ; ( D+ 1 )• 10} " NANOSECONDS"

6650 CASE "D"

6660 PRINT "EXTERNAL CLOCK ON:"

GG70 PRINT "PULSE LENGTH SET UITH DELAY LINE"

6680 D=IVAL(Time$[3;ll ,16)

6690 PRINT "PULSE LENGTH=" ; ( D+1 )• 10; " NANOSECONDS"

6700 END SELECT

6710 PRINT "USE OF KEY IZ (Ckon_off ) MAKES CLOCK ON OR OFF INDETERMINATE"

G7Z0 PRINT "VOLTAGE STEP GENERATOR REPETITION ''RATE = " ; 10000000/Freq_int

;

6730 PRINT " HZ"

6740 PRINT "PULSE LEN6TH=" ; (Pulse_int+1 )• 100; " NANOSECONDS IF PROGRAMMABLE"

6750 PRINT "COUNTERS IN USE"

6760 Tr$="POSITIVENEGATIVE"

76
G770 PRINT TrS[(Tr-1 )»8+1;81;" TRftNSITION"

G780 PRINT "FlNftL LEVEL =" ;Final_vl ; " VOLTS"

6790 PRINT "INITIAL LEVEL =";Init_vl;" VOLTS"

G80O PRINT " IF EXTERNAL CLOCK IN USE:"

G810 PRINT "DIVIDE THE CLOCK FREQUENCY BY" |Freq_int ; " TO OBTAIN THE"

G8Z0 PRINT "VSG REPETITION RATE"

G830 PRINT "MULTIPLY THE CLOCK PERIOD BY" ;Pulse_ln-t + 1 ; " TO OBTAIN THE"

G840 PRINT "PULSE LENGTH"

G850 PRINT "Tine$=";Tiine«;" " ; G8G0 PRINT "Dac$=";Dac«

G870 PRINT " NOTE: PULSE LENGTH IS DURATION OF FINAL VOLTAGE LEVEL"

G880 RETURN \ Ex it Status

7000 Ch_f_vl: ! Enter neu final voltage level, transition unchanged

7010 PRINT "PRESENT FINAL LEVEL=" ; Final_vl ; " VOLTS"

70Z0 INPUT "ENTER NEU FINAL VOLTAGE LEVEL=" ,Neu_f vl

7030 Flag=0 •. Flag is set to 1 uhen a disalloued voltage is entered

7040 IF Tr=t THEN GOSUB 7Z00 I Calculations and error statements

7050 IF Tr=Z THEN GOSUB 7300 I Calculations and error statements

70G0 IF Flag=l THEN 7010 I Disalloued voltage has been entered

7070 RETURN ! Exit Ch_f_vl

7Z00 Chl_f_vl: I Positive transition< change final voltage level

7Z10 IF Init_vl>=Neu_fvl THEN \ If false, valid voltage

7ZZ0 BEEP Z00, .Z 7Z30 PRINT "FINAL LEVEL <= INITIAL LEVEL NOT ALLOUED ON POSITIVE TRANSITION"

7Z40 Flag=l I Reenter final voltage level

7Z50 GOTO 7Z90 I Execute return statement

7ZG0 END IF \ End of error statement

7Z70 Final_vl=Neu_f vl I Valid neu final voltage level

7Z80 GOSUB Z500 I Enter neu final_vl

7Z90 RETURN I Exit Chl_f_vl

7300 ChZ_f_fl: \ Negative transition, change final voltage level

7310 IF Init_vl<=Neu_fvl THEN ! If false, valid voltage

73Z0 BEEP Z0O,.Z

7330 PRINT "FINAL LEVEL >= INITAL LEVEL NOT ALLOUED ON NEGATIVE TRANSITION"

7340 Flag=l ! Reenter final volteige level

7350 GOTO 7390 I Execute return statement

73G0 END IF I End of error statement

7370 Final_vl=Neu_f vl • Valid neu final voltage level

7380 GOSUB Z500 I Enter neu Final_vl

7390 RETURN I Exit ChZ_f_vl

7500 Ch_i_vl : ( Change initial voltage level, transition unchanged

7510 PRINT "PRESENT INITIAL LEVEL=" ; Init_vl ; " VOLTS"

75Z0 INPUT "NEU INITIAL VOLTAGE LEVEL=" ,Neu_ivl

7530 Flag=0 I Flag is set to 1 uihen disalloued voltages are entered

7540 IF Tr=1 THEN GOSUB 7G00

7550 IF Tr=Z THEN GOSUB 7800

75G0 IF Flag=l THEN 7510 \ Disalloued initial voltage level entered

7570 RETURN I Exit Ch_i_vl

7G00 Chl_i_vl: [ Positive transition< change initial level

7B10 IF Neu_ivl>=Final_vl THEN I If false , valid voltage

7GZ0 BEEP Z0O..Z

7G30 PRINT "INITIAL VOLTAGE LEVEL>= FINAL VOLTAGE LEVEL NOT ALLOUED + TRANS.'

7B40 Flag=l I Reenter initial voltage level

7G50 GOTO 7G90 I Execute return statement

77
7GG0 END IF

7G70 Init_vl=Neu_ivl ( Valid initial voltage level

7G80 G05UB Z50O I Enter neui initial voltage level

7630 RETURN I Exit Chl_i_vl

7800 ChZ_i_vl: \ Negative transition, change initial level

7810 IF Neu_ivl<=Final_vl THEN ! If false, valid voltage

7820 BEEP 200,.

Z

7830 PRINT "INITIflL LEVEL<= FINftL LEVEL NOT ALLOUED ON NEGATIVE TRANSITION"

7840 Flag=l I Reenter initial voltage level

7850 GOTO 7890 I Execute return statement

78G0 END IF

7870 Init_vl=Neij_ivl I Valid neu initial voltage level

7880 GOSUB 2500 I Enter neu Init_vl

7890 RETURN I. Exit Ch2_i_vl

8000 Changetr: I Change the transition

8010 REM Final and initial levels are exchanged

8020 IF Tr=l THEN I Change the transition

8030 Tr=2

8040 ELSE

8050 Tr=l

80G0 END IF

8070 Exchange l=Final_vl I Interchange the initial

8080 Exchange2=Init_vl \ and final voltage levels

8090 Final_vl=Exchange2

8100 Init_vl=Exchangel I Interchange complete

8110 GOSUB 2500 I. Enter neu Tr & voltafe levels

8120 RETURN ! End Changetr:

12155 User:! user defined routine

1Z1G0 PRINT "User"

1Z1G5 RETURN I Exit User

1Z170 END ! End of VSG Driver

78
NUMERIC VftRIRBLES

CI

CZ

C3=Ct+CZ

Cklctrl

Control characier for entering tining card functions.

Contains the tuo least significant hits.

Control character for entering timing card functions.

Contains the tuo most significant bits.

Hex control character for entering timing card functions,

Decimal value of the second character of TimeS, contains

the clock on/clock off control bit.

CkZctrl Clock control bit in Cklctrl is complemented, neu

decimal value.

Ctrl Selects computation for DAC A or DftC Bj t= DAC A;

Z= DAC B.

Delay_line

Exchange 1

ExchangeZ

Final_vl

Flag

In Status routine: Length of pulse uhen set by delay

line =(D+1)»10 nanoseconds. D is the decimal value of

the hex character programmed into position 3 of TimeS

to set the pulse length.

Length of pulse uhen using programmable delay line,

entered by operator, range 1-lG, corresponds to a range of 10-160 nanoseconds.

Used, uith ExchangeZ, to interchange the initial and

final voltage levels in the change transition routine.

Used, uith Ex change 1 , to interchange the initial and

final voltage levels in the change transition routine.

The value of the final voltage (Level VZ in instructions).

In Trvls:, it is an entry variable.

Used in the Ch_f_vl: (Change final voltage level only)

and Ch_i_vl: (Change initial voltage level only) routines

Flag= calculate neu voltage level,

Flag=l illegal voltage level entry, reenter a neu voltage

level

.

Freq_int A positive integer greater then one. The internal/external

clock frequency is divided by Freq_int to obtain the Vsg

drive frequency. This is positions 4-7 of Time$.

Freq_lntZ =65536 - Freq_int. Put In fornat for loading registers

in support unit.

Init_vl The value of the initial voltage level (Level VI in the

instructions). In Trvls:, it is an entry variable.

Lsb_8 This is the value in least significant bits of the

variable Vdac+10. The entry variable Vdac in routine Code:

is converted to a positive offset voltage by adding 10 to it,

then digitizing it to the nearest IZ bit LSB. Lsb_6 is

79
then converted to the complementary offset code that is

sent to the DAC registers.

Neu fvl

Neu ivl

Used in Ch_f_vl: to enter a neu final voltage level. If

Neu_fvl is a valid voltage, then Final_vl is the neu

final voltage level.

Used in Ch_i_vl: to enter a neu initial voltage level. If

Neu_ivl is a valid voltage level, then Init_vl is the neu initial voltage level.

Plength Used in Pulse_length: to enter a neu value of pulse

length in nanoseconds. Entered in increments of \(d<d

nanoseconds

.

Pos Decimal value of Ck$, the hex digit in position Z of TineS.

Bit Z of Ck$ contains the clock control bit.

Post Decimal value of Pos uith the clock control bit complemented

to turn the clock on if off, or off if on.

Pulse_int f\ positive integer less than Freq_int. The pulse length

(duration of final voltage level) is equal to clock

period*Pulse_int . This is in positions 8-11 of TimeS.

t4ote: Pulse_int entered from keyboard has one subtracted

from it, therefore Pulse_int used in program uill he one

less then the keyboard entry.

Pul(se__int Z

Rau._lsbs

Tr

=G553B-Pulse_int . Put in a format to load registers in the

support unit.

Undigitized value of Lsb_s. Not used in this program

Sets the transition. Tr=l is positive transition (initial

level to final level), Tr=Z is negative transition (final

level to initial level).

Vdac

Vdac3

Voltage used for DAC A and B code calculations.

=Vdac+10. Forces voltage to be a positive number from

to Z0 to facilitate conversion to LSB's and code calculations,

Vsg IEEE-488 identification of the the voltage-step generator

support unit. Initially set to 708tZ in line 110.

Vsgfreql User entered Vsg drive frequency in Vsgfreq: routine.

Converted to Freq_int by the relationship

Freq_int=INT( 10. 000. 000/(Vsgfreq)+0. 4999999) based on the

internal 10 MHz clock.

Xdacb The output voltage, uhen multiplied by -0.5, needed from

DAC B to produce the programmed output levels.

Xdacb

1

Ydaca

=-0,5»Xdacb. Save if needed for later use.

The output voltage, uhen multiplied by -t, needed from DAC A

to produce the programmed output levels.

80
Ydacal =(-t)*Ydaca. Save if needed for later use.

STRING VARIABLES

Bindac_a$ Set equal to X$, this is the code sent to the registers

for DAC A.

Bindac_b$ Set equal to X$ , this is the code sent to the registers

for DAC B.

Ck$ Hex character in position Z of TimeS. Contains the clock

control hit in position Z.

CklS Hex character in position Z of Time$. Used in Ckon_off: routine.

Contains the clock control bit in position Z.

CkZ$ String of Cklctrl in binary. Bit 15 contains the clock

control bit.

Ck3S ="l"&CkZl41. Used to turn the clock off in line 1580.

Saved for future use.

Ck_on$ Saved to turn the clock back-on, after use of Ck3$ to turn

clock off.

Clear_crt$ =CHR$( Z55)&CHR$( 75) . Use, uith OUTPUT Z statement, to

clear CRT screen.

Dac$ Contains the DAC coding to the support unit storeige registers.

Format is "0AAABBB".

"®"=Board Address.

"AAA"=coding DAC A

"BBB"=coding DAC B

F$ Hex code for dividing the clock frequency by Freq_int. Used

in Vsgfreq: routine. This is a four digit code inserted

into TimeS in positions 4-7.

HexlS Hex string obtained from Lsb_s. The first three digits

contain the coding for the IZ bit DAC's.

P$ Hex code for dividing the clock frequency by Pulse_int.

Equivalent to multiplying the clock frequency by Pulse_int

to find the pulse length. This is a four digit code inserted

into positions 8-11 of TimeS,

TimeS Contains the coding to the timing card storage registers.

Format=" IGLFFFFPPPP"

" t"=Board Address

"G"=Function Select Code

"L"=Programmable delay line coding

"FFFF"=Divide the clock frequency by a four digit hex

number to set the Vsg drive frequency.

"PPPP"=Divide the clock frequency by a four digit hex

81
number to set the duration of the final voltage level.

(Pulse Length).

Tr$ ="POSlTIVENEGflTIVE". Substring of used in Status: routine

to indicate positive or negative transition.

V$ Set equal to X$ in lines 3157 and 3210. Intermediate

storage of the coding to DAC's A and B,

X$ =Hexl$[Z]. After reversal of digits, contains the hex code

sent to the storage registers for DAC's A and B.

Xx$ Digit tuo of TimeS uhen used in Card: routine.

XxlS Programmable delay line code of one hex digit inserted

into position three of TimeS.

LINE LABELS

Bindaca: Assemble the code for DAC A into Dac$. Ctrl=1 is used to

access this routine.

Return at line 3230.

Bindacb: Assemble the code for DAC B into Dac$. Ctrl=2 is used to access this routine.

Return at 3180.

CIcZ: Enter CI and CZ without displaying the timing card menu.

[Key 81 Entry variables are Ct and CZ , routine can he entered at line G75

if these are set.

Return at line 700

Card: Display the functions available on the timing card. Variables

[Key 71 CI and C2 are entered to implement these functions. Can be

entered at line 675 if CI and CZ are set [no displayl

.

Return at line 700.

Ch1_f_vl: Check positive transition, final voltage level, error

statement. Lies uithin Ch_f_vl: routine.

Ch1_i_vl: Check positive transition, initial voltage level, error statement. Lies uithin Ch_i_vl: routine.

Ch2_f_vl: Check negative transition, final voltage level, error

statement. Lies uithin Ch_f_vl routine.

Ch2_i_vl: Check negative transition, initial voltage level, error

statement. Lies uithin Ch_i_vl routine.

Ch_f_vl: Change the final voltage level without changing transition

[Key 131 or initial voltage level. Entry variable is Neu_f vl , uhen

determined to be valid, Final_vl is set equal to Neu_fvl.

Can be entered at line 7030 if Neu_fvl is set.

Return at 7070.

82
Ch_i_vl: Change ihe initial voltage level uiithout changing the transition

IKey 141 or the final voltage level. Entry variable is NeiJ_ivl , uhen

determined to be valid, Init_vl is set equal to Neu_ivl.

Can be entered at line 7530 if Neu_ivl is set.

Return at 707®.

Changetr: Transition is changed, initial and final voltage levels

[Key 111 are interchanged, and the neu transition and voltage levels

are output.

Return at 8120.

Ck_off: Before entering any neu data to the storage registers, the

clock is turned off to ensure reliable loading of the

storage registers. The clock off routine turns the clock off

uiithout changing any other settings. The string Ck_on$ is used

for turning the clock back on. Return at 1G00.

Ckon_off: Cycle the clock on/off or off /on. The clock control bit in

[KEY IZl Tine! is also changed to reflect the clock on/off status.

Return at 770.

code: Calculations to obtain the complementary offset binary code

code to load the DAC registers using OacS.

Return at 3140.

Dac_va: DAC A calculations for the voltage necessary to output the

programmed initial and final voltage levels.

Return at 3140.

Dac_vb: DAC B calculations for the voltage necessary to out put the

programmed initial and final voltage levels.

Return at line Z870.

Dacv_s: Compute and output the voltages and binary codes for

DAC's A and B to obtain the programmed initial and final

voltage levels using DacS.

Return at line ZB40.

Oelayline: Set the pulse length uith the programmable delay line. Entry

IKey 51 variable is Delay_line. Can be entered at line B030 if

Delay_line is set.

Return at line B070.

Final_vlrg: Check the value of Final_vl to determine if a valid voltage.

Lies uithin Trvls: routine.

Init: Set up the Voltage-step generator parameters. After executing

IKey 01 a RUN statement, Init: must be executed. Parameters set

include Tr , Dad, Time*, Bindac_aS, Bindac_b$, Init_vl , Final_vl,

Freq Int. Pulse_int and Vsg.

Return at line Z50.

Init_vlrg: Check the value of Init_vl to determine if a valid voltage.

Lies uithin Trvls: routine.

83
Integer: Enter the pulse length and Vsg drive frequency using positive

[Key El integers. Freq_int and Pulse_int are the entry variables.

One is subtracted froin Pulse_int entry so neu Pulse_int

is one less then the value entered.

Can be entered at line 5540 if Freq_int and Pulse_int are set.

Return at line 5610.

Loop: After RUN is executed, program remains at line 90 using

a GOTO Loop statement. After a key is pressed, when execution

of the subroutine associated uith that key is completed,

the program returns to Loop:

.

Neg_tr: Sets the negative transition.

Return at line 530.

Pos_tr: Sets the positive transition.

Return at line 510.

Pulse_length: Set the pulse length based on the 10 MHz internal clock.

[Key 41 Pulse length is entered in units of 100 nanoseconds.

Return at line 5Z50.

Pulse_q3: Not used. Produces a pulse at transistor Q3 output.

Return at line 550.

Pulse_q4: Not used. Produces a pulse at transistor C)4 output.

Return at 570.

Start: Line Z. Not used, going to Start: equivalent to a RUN

statement

.

Program remains in a loop at Loop:

.

Status: Prints on CRT the current Voltage-step generator parameters.

[Key 101 Return at line G880.

Trvls: Set a neu transition, neu final voltage level, and a

[Key Zl neu initial voltage level. Entry variables are Tr , Final_vl

and Init_vl. Can be entered at line Z060 if these three

variables are already set.

Return at line 2G40.

User: A user defined subroutine.

[Key 91 Return at line 121G5.

Vsgfreq: Enter the Voltage-step generator drive frequency based

[Key 31 on the 10 MHz internal clock. Entry variable is Vsgf reql

.

Can be entered at line 4040 if Vsgf reql is already set

Return at line 4300.

FLOU CHARTS

Flou charts are given for each of the defined keys and GOSUB Z50O,

the main routine used to calculate codes needed for the DAC's. After a RUN

statement is executed , the program reimains in a loop at line 80 "Loop:",

and all operations are from the Softkeys.

84
c

Dacv

\/

Z3

2500

2520

2550

PRINT

Final_vl

Init vl

\/

2570

2580

OUTPUT

Dac_$

To Vsg

©

GOSUB 2500 or Dacs_s

GOSUB 2800

Dac_vb

DAC B

Voltage

Calculations

2860

GOSUB 2900

Dac_va

DAC A

Voltage

Calculations

2950

GOSUB

1500

GOSUB 3000

Code

DAC Binary

Code

Calculations

3120. 3130

3200

GOSUB

Bindaca

=2 GOSUB

Bindacb 3150

GOSUB 3000

Code

DAC Binary

Code

Calculations

3020, 3030

= 1

Ck_off

Turn Clock

Off

3200

= 2

GOSUB

Bindaca

3150

GOSUB

Bindacb

85
©

\/ 2600

c

Turn

Clock

On

\/

2630

\/

2640

RETURN

= 2

Pos_tr

Set Positive

Transition

GOSUB

520

Neg_tr

Set Negative

Transition

86
Key GOSUB Init

No

GOTO Loop

>

Execute

Subroutine

c

Key

>

>-- Display

"Init"

Init:

Init:

Initialize

Voltage-Step

Generator

Q7

Lines 100 To

250
Key 2 Enter Polarity of transition.

Final and Initial Voltage Levels

No

Key 2

>

::^ y 2000

\''

Yes

\/

2500

GOSUB

2500 or Dacv s:

_ Display

"TRS, V2, VI"

GOSUB 2000

or Trvls:

Enter the transitions,

Final Volage Level

,

Initial Voltage Level

Calculate and

Output Transition,

Initial and Final Voltage

Levels to the Support Unit

88
Key 3 GOSUB Vsgfreq

4000 or VsgFreq:

Display

"Vsg freq"

Calculations

to format

Freq_lnt into

Time$

\/

4270

4280

OUTPUT to

Support

Unit

Time$

Vsgfreql used

to calculate

freq int

Freq_int

Compared

with Pulse int

RETURN

at 4300

89
Key 4 GOSUB Pulse_Length

C

Key 4

5120

> I Display

"Pulse Length'

5000 or

Enter

Plength

5180

Pulse_int

Calculated

from Plength

Compared with

FrecL_int

Turn

Clock

Off

\/

5200

Format

Pulse_int

into Tlme$

\/

OUTPUT

Time$ to

Support

Unit

RETURN

at 5250

90
Key 5 GOSUB Delayline

Key 5 >

Display

"Delay Line"

6000 or Delayline:

Pulse_int > 1 and

Freq Int > 3 ?

Enter

Delay linei

Range is

integer 1-16

corresponding to

10-160 nanoseconds

\/

Format

Delay_line

into

Time$

\/

Note: Delay line

function must be set

with card: routine,

C1=0 or 1, C2=12

before using Key 5.

OUTPUT to

Support

Unit

Time$

If Pulse_int and

freq_int not valid

must be entered

correctly
Key 6 Gosub Integer

c Key 6

^

>

Display

"Integer"

Enter

Freq^int / __

5500 or Integer

\/

5610

Range Freq_int,

I Integers > 1 Integers only

Pulse_int < _ FrecL_int

Valid Entry

GOSUB 5170

Enter and

Output

Pulse Length

Based on Pulse int

GOSUB 4220

Enter and

Output Vsg

Drive Frequence

Based on Freq_int

92
Key 7 Key 8

GOSUB card

GOSUB Clc2

(^ ^ey 7 y-

>

_J Display

"Functions"

600 or card

Display

Timing Card)

Functions

Display on CRT

Timing Card

Functions Available

\/

665 or card:

Enter

CI and

C2 662

or Clc2:

cjziiyDisplay

"Enter CI, C2"

\/ L _

Format

CI and C2

into

Time$

Enter CI and

C2 without

displaying the

timing card

functions

\/

r OUTPUT

Time$

to the

Support Unit

Key 7 93
Key 9 GOSUB User

Key 10 GOSUB Status

(^ Key 9 ^

>

Display

"User"

\J/ User:

A User

Defined

Subroutine

Loop

No

c

Key 10

>

)

6400 or Status:

Display

Current

System

Parameters

\/

on CRT or Current

Printer is

Device

r status: ^

V RETURN J

94
Key 11 GOSUB Changetr

Key 12 GOSUB Ckon_off

CEi^

> 8000 or Changetr:

Changetr

Polarity,

Interchange

Voltage Levels

Yes

Output New

Transition Polarity

Interchange final

and initial voltage

levels.

GfiiO

>

725 or Ckon off

Complement

Clock Control

Bit in

Time$

fOUTPUT to /

the Support

Unit

Time$ /

770

CCkon_off \

RETURN J

Turn Internal/External

Clock on if off,

or off if on

95
Key 13 GOSUB ch f vl

Q Key 13 ^

Tr=2

GOSUB

7300 or ch2 fl:

No

GOSUB

2500

OUTPUT new

Final vl

flag = 1

-^^

7000 or ch f Iv:

Enter

New_fl

flag =

Enter

New Final

Voltage Level

Tr=l

GOSUB

7200 or

chl f vl ^ No

\/

J^

\/

70760

Yet

GOSUB

2500

OUTPUT New

Final vl

96
Key lA GOSUB ch_i_vl

Key lA

7500 or ch i vl

Enter

New_ivl

flag «

Enter

New Initial

Voltage Level

Tr = 2

GOSUB 7800

or ch2 i vl:

N/

Tr?

Tr = 1

No

flag = 1 ^ No

V

GOSUB

2500

OUTPUT New

Init vl

Ji^

flag = 1

x^

flag = 1

Yes

GOSUB 7600

or chl i vl

ge

GOSUB

2500

OUTPUT New

Init vl

97
NBS-n4A (REV. 2-8C) U.S. DEPT. OF COMM.

BIBLIOGRAPHIC DATA

SHEET (See instructions)

1. PUBLICATION OR

REPORT NO.

NBS/TN-1230

2. Performing Organ. Report No, 3. Publication Date December 1986

4. TITLE AND SUBTITLE

A Precision Programmable Step Generator for Use

in Automated Test Systems

5. AUTHOR(S)

H.K. Schoenwetter, D.R. Flach, T.M. Souders, and B.A. Bell

6. PERFORMING ORGANIZATION (I f joint or otiier than NBS. see instructions)

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

Gaithersburg, MD 20899

7. ContracL^Grant No.

8. Type of Report & Period Covered

Final

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street. City. State, Z'.P)

Same as item 6

10. SUPPLEMENTARY NOTES

QJ Document describes a computer program; SF-185, FIPS Software Summary, is attached.

11. ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant

bibliography or literature survey, mention it here)

A precision voltage step generator has been designed for use in automated

systems to test the dynamic response of waveform recorders and other

instruments. The programmable pulse parameters include transition polarity,

pulse length, and repetition rate. The initial and final levels of voltage

steps are each programmable within the range of - 1 V for a 50 51 termination

and within - 5 V for a high impedance load. Voltage steps within these ranges

settle to within - 0.02% of full scale range (FSR) in less than 22 and 26 ns

,

respectively, for small load capacitance. The corresponding transition

durations are approximately 6 and 7 ns.

12. KEY WORDS (Six to twelve entries; alpliabetical order; capitalize only proper names; and separate key words by semicolon sj automated test systems; programmable step generator; pulse generator; rise time;

settling time; transition duration; waveform recorder testing

13. AVAILABILITY

g^ Unlimited

[^ For Official Distribution. Do Not Release to NTIS

K5^ Order From Superintendent of Documents, U.S. Government Printing Office, Washington, D.C.

" 20402. P ] Order From National Technical Information Service (NTIS), Springfield, VA. 22161

14. NO. OF

PRINTED PAGES

104

15. Price

USCOMM-DC 6043-P80
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