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NIST SPECIAL PUBLICATION 400-93

U.S. DEPARTMENT OF COMMERCE/Technology Administration

National Institute of Standards and Technology

h-QC

100

.U57

1994

400-93
The National Institute of Standards and Technology was established in 1988 by Congress to "assist industry in the development of technology . . . needed to improve product quality, to modernize

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Semiconductor Measurement Technology:

Design and Testing

Guides for the CMOS and

Lateral Bipolar-on-SOI

Test Library

Janet C. Marshall and Mona E. Zaghloul *

Semiconductor Electronics Division

Electronics and Electrical Engineering Laboratory

National Institute of Standards and Technology

Gaithersburg, MD 20899

* School of Engineering and Applied Science

George Washington University

Washington, DC 20052

March 1994

U.S. DEPARTMENT OF COMMERCE, Ronald H. Brown, Secretary

TECHNOLOGY ADMINISTRATION, Mary L. Good, Under Secretary for Technology

NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY, Arati Prabhakar, Director

Issued March 1994
National Institute of Standards and Technology Special Publication 400-93

Natl. Inst. Stand. Technol. Spec. Publ. 400-93, 138 pages (March 1994)

CODEN: NSPUE2

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1994

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402-9325
Semiconductor Measurement Technology:

Design and Testing Guides for the CMOS and

Lateral Bipolar-on-SOI Test Library

Table of Contents

Page

Abstract 1

1. Introduction 2

2. The NIST9 SOI/SIMOX Process 3

2.1 Implant doses and energies for the SIMOX process 4

2.2 Processing sequence for NIST9 5

3. Lateral Bipolar and CMOS-on-SOI Design 6

4. Updated SOI/SIMOX Technology File 8

5. Test Library 10

6. Test Chip NIST8 12

7. Test Wafer NIST9 14

8. Conclusions 16

9. Acknowledgments 17

10. References 17

Appendix A — Sideviews of the 14 SOI/SIMOX Processing Mask Steps Used to Fabricate

NIST9 79

Appendix B - Abbreviated SOI/SIMOX Technology File 86

Appendix C - Test algorithm KEYSiv 93

Appendix D - Test algorithm KEYSvt 100

Appendix E — Test algorithm INY 108

Appendix F — Test algorithm SRAM 113

Appendix G - SPICE file for an N-Channel MOSFET 119

Appendix H — SPICE file for an inverter 120

Appendix I — SPICE file for a ring oscillator 122

Appendix J — SPICE file for a ring oscillator using H-gate MOSFETs 126

Appendix K - SPICE file for an SRAM 130

iii
List of Figures

Page

1. Simplifed block diagram for the computer procedure KEYS 19

2. Key to the shading in the figures 20

3. P-channel MOSFET found in the test library, NIST8, and NIST9 , . 21

4. TV-channel MOSFET found in the test library, NIST8, and NIST9 22

5. Minimum-sized ^-channel MOSFET found in the test library, NIST8,

and NIST9 23

6. Circular ^-channel MOSFET found in the test library, NIST8, and NIST9 24

7. Circular w-channel MOSFET with no channel contact found in the test

library, NIST8, and NIST9 25

8. H-gate MOSFET found in the test library, NIST8, and NIST9 26

9. Italic H-gate MOSFET found in the test library, NIST8, and NIST9 27

10. T-gate MOSFET found in the test library, NIST8, and NIST9 28

1 1 . H-gate MOSFET with source-to-channel tie found in the test library, NIST8,

and NIST9 29

12. T-gate MOSFET with source-to-chamnel tie found in the test library, NIST8

and NIST9 30

13. TV-channel MOSFET with source-to-channel tie found in the test library and NIST9 31

14. TV-channel depletion-mode MOSFET found in the test library and NIST9 32

15. First bipolar design (npri) on NIST9 with the base contact beside the emitter

and with a full implant 33

16. Second bipolar design (npn) on NIST9 with the base contact beside the emitter

and with a half implant 34

17. Third bipolar design {npn) on NIST9 with the base contact below the gate and

with a full implant 35

18. Fourth bipolar design {npn) on NIST9 with the base contact below the gate and

with a half implant 36

19. Fifth bipolar design {npn) on NIST9 with an n-channel MOSFET gate connected to

its base 37

20. Cell structure of the test library with module count 38

21. Module spacings used in the test library, NIST8, and NIST9 39

22. Cell structure of NIST8 40

23. Subcell structure of NIST8 41

24. CMOS Test Chip, NIST8 42

25. Static RAM module DDM found in the test library, NIST8, and NIST9 43

iv
List of Figures (continued)

Page

26. Ring oscillator module EEM found in the test library, NIST8, and NIST9 44

27. H-gate MOSFET ring oscillator module GGM found in the test library, NIST8, and

NIST9 45

28. Large n-channel MOSFETs for radiation investigations (module OOM) found in the

test library, NIST8, and NIST9

.

46

29. Circuit diagram of the static RAM cell (and how to test it)

.

47

30. Cell structure of the SOI/SIMOX test wafer NIST9 48

31. Processing module AAM found in the test library and NIST9 49

32. Processing module AAM1 found in the test library and NIST9 50

33. Micromachining module IRM found in the test library and NIST9 51

34. OH breath analyzer 52

List of Tables

Page

1. Doses and Energies for the Implantations on NIST9 53

2. Mask Processing Sequence for NIST9 54

3. Magic Layer Used for MOSFET Gates or a Shield for Bipolar Devices and the Mask

Numbers Involved in the Processing 55

4. Magic Layers, CIF Names, and Calma Numbers Associated with the SOI Masks 56

5. Magic Layers, CIF Names, and Calma Numbers Associated with the MOSIS CMOS

Masks 57

6. Module Cell Names, Dimensions, and Pad Arrangement for the Different Module

Sizes Followed by the MOSFET Dimensions and Sample Subcell Name for the

2 by 16 Small Medium, and Large Modules 58

7. Method Used to Make a Medium Module into a Small Module on NIST9 . 59

8. Module Name, Label, and Description for the Large 10 by 7 Modules ............... 60

9. Module Name, Label, and Description for the 2 by 16 Modules, the 12 by 2

Modules, the 10 by 2 Modules, and the 2 by 11 Module 64

10. List of Large 10 by 7 Modules in the Test Library Organized by Function 68

1 1 . List of All But the Large 1 0 by 7 Modules in the Test Library Organized by

Function 69

v
List of Tables (continued)

Page

12. List of Modules Consisting of MOSFETs Found in the Test Library with a Sample

Subcell Name Given 70

13. List of Modules Consisting of Meanders Found in the Test Library 71

14. Capacitors on Modules CCM and CCM1 Found in the Test Library 72

15. Capacitors on Modules CCM2 through CCM9 Found in the Test Library 73

16. List of Modules Containing Dynamic Circuits Found in the Test Library with a Sample

Subcell Name Given 74

17. Organization of the Modules on NIST8 75

18. Method Used to Get Submicrometer Dimensions on NIST8 76

19. Organization of the Large 10 by 7 Modules on NIST9 77

20. Organization of All the Modules Except the Large 10 by 7 Modules on NIST9 78

vi
Semiconductor Measurement Technology:

Design and Testing Guides for the CMOS and

Lateral Bipolar-on-SOI Test Library

J. C. Marshall

Semiconductor Electronics Division

National Institute of Standards and Technology

Gaithersburg, MD 20899

and

M. E. Zaghloul

National Institute of Standards and Technology

and School of Engineering and Applied Science

George Washington University

Washington, DC 20052

Abstract

Design and testing guides have been developed for the test library from which test chip

NIST8 and test wafer NIST9 were derived. They were designed for use in process monitoring and device parameter extraction to evaluate and compare CMOS (Complementary

Metal-Oxide-Semiconductor) test structures, including devices and circuits, fabricated on

both bulk silicon and SOI (Silicon-on-Insulator), specifically SIMOX (Separation by the

IMplantation of OXygen), wafers. The test library consists of both CMOS-on-SOI and

lateral bipolar-on-SOI modules. From it, 20 modules were assembled to create CMOS test chip NIST8 that was fabricated using a standard bulk CMOS foundry through the MOSIS service. SOI/SIMOX test wafer NIST9 contains approximately 1000 modules and was

also assembled from modules in this test library. Fourteen processing masks are used to

fabricate depletion-mode MOSFETs, lateral bipolar devices, and CMOS MOSFETs with

source-to- channel ties. The SOI/SIMOX technology file used with the Magic VLSI layout

editor was modified to include the layers necessary to generate these 14 processing masks.

This modification is discussed, and unique test structure designs are presented.

Key words: bipolar; CAD; CMOS; Magic; NIST8; NIST9; SOI; technology file; test chip;

test structure

1
1. Introduction

This document is the design and testing guide for the generic test library from which

test chip NIST8 and test wafer NIST9 were derived. This test library is intended for

researchers in industry, university, and government laboratories who are initiating an SOI

process. NIST8 and NIST9 were designed for process monitoring and device parameter

extraction to evaluate and compare CMOS (Complementary Metal-Oxide-Semiconductor)

test structures, including devices and circuits, fabricated on both bulk silicon and SOI

(Silicon-on-Insulator) wafers. The test library was designed for the SOI technology known

as SIMOX (Separation by the IMplantation of OXygen).

Prom this library, a CMOS test chip NIST8 was assembled and submitted to MOSIS [1] for fabrication in a standard CMOS foundry on conventional bulk silicon wafers. Also, a

lateral bipolar and CMOS-on-SOI test wafer NIST9 was assembled from this test library.

An SOI/SIMOX process for the fabrication of NIST9 is described in section 2 to provide

a brief process overview for sample test structure designs which will follow.

The SOI/SIMOX test chips NIST3 and NIST4 that preceded the design of the test li- brary are described in the references [2,3]. A substantial number of additional designs

are incorporated into the test library and are described in section 3. These designs include depletion-mode MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors),

lateral bipolar devices, and CMOS MOSFETs with source-to-channel ties that require 14

processing masks.

The "technology file" used with the CAD graphic layout editor Magic* [4] was modified

to include the layers necessary to realize the 14 processing masks needed to build the

test library, as well as modifications made since NIST3 and NIST4 were built. This is discussed in section 4. Magic is running under OpenWindows 2.0 on a Sun SPARCsystem

300 running SunOS 4.1.2.

Section 5 describes the test library from which a variety of modules can be assembled to

create a new test chip or test wafer, or the modules can be used as "drop-in's." This section

explains the philosophy behind the module sizes, dimensions, placements, nomenclature,

architecture, and so forth. Each one of the modules described in this section is designed

to facilitate packaging.

NIST8 is a CMOS test chip that was assembled from 20 modules in the test library. It is

* In this report, commercial equipment, instruments, and computer programs are identified to specify the procedure adequately. This does not imply recommendation or endorsement by NIST, nor does it imply that the equipment or program is the best available for

the purpose. In spite of the authors' experiences that the programs perform correctly on

every set of data which has been tried, there can be no assurance that the program will

perform equally well on all (possibly anomalous) data. Therefore, both the authors and

NIST assume no liability for possible losses resulting from the use of these programs.

2
described in section 6 and is a CMOS-on-SOI design converted to a CMOS on bulk silicon

design via the technology file. NIST8 was tested on the HP 4062UX Semiconductor Process

Control System, and the testing results were evaluated using the computer procedure

KEYS (linKing softwarE to analYze waferS) [5]. KEYS links SUXES (Stanford University

eXtractor of modEl parameters) [6], SPICE (a Simulation Program with Integrated Circuit

Emphasis) [7], and STAT2 [8] to facilitate integrated circuit evaluation. A simplified block

diagram for KEYS is given in figure 1. The CMOS data from NIST8 can be presented and

compared with the SOI/SIMOX data from NIST9 once it is fabricated and tested.

The SOI/SIMOX test wafer, NIST9, is presented in section 7. It describes its formation,

organization, and the test structures that were included from the test library. The processing modules which include the alignment marks were strategically placed to ease the

task of mask alignment. To study parameter variations across NIST9, a test module was

designed and placed such that the data will be very comprehensive.

Section 8 presents the conclusions.

The test library (from which NIST8 and NIST9 were derived) contains modules that can

be used to:

1. Monitor a CMOS or SOI process

2. Extract device or circuit parameters

3. Compare parameters from different device and circuit designs

4. Evaluate a CMOS or SOI process

5. Compare different CMOS and/or SOI processes via correlation coefficients and

wafer maps which yield conclusions for future designs and processes.

For information on obtaining this test library, NIST8, NIST9, and the SOI/SIMOX technology file, please contact:

J. C. Marshall

NIST, Bldg. 225, Room B-360

Gaithersburg, MD USA 20899

Telephone: 1-301-975-2049

Email: marshall@sed.eeel.nist.gov

For easier interpretation of the test structures, this author can be contacted for the supplement to this document [9] which is available in color.

2. The NIST9 SOI/SIMOX Process

NIST9 was designed for a robust NIST SOI process using SIMOX which has a 0.15 //m

silicon layer. The processing sideviews for the 14 mask steps are shown in Appendix A.

Below is a list of these processing masks used to fabricate NIST9, in the order in which

they are used, with the added distinction of clear or dark field:

1. Island (clear field mask)

3
2. JVwell/n-channel implant (dark field mask)

3. Pwell/p- channel implant (dark field mask)

4. .AT-channel MOSFET source-to-channel tie implant (dark field mask)

5. P-channel MOSFET source-to-channel tie implant (dark field mask)

6. Depletion-implant (dark field mask)

7. JV+poly gate implant (dark field mask)

8. P+ poly gate implant (dark field mask)

9. Polysilicon (clear field mask)

10. Source/drain n+ -implant (dark field mask)

11. Substrate contact or subcon (dark field mask)

12. Source/drain and substrate jf1" -implant (dark field mask)

13. Contacts (dark field mask)

14. Ml (clear field mask)

Of the 14 processing masks specified above the following are implant masks:

1. iVwell/n-channel implant

2. Pwell/p-channel implant

3. iV-channel MOSFET source-to-channel tie implant (also called the ntie implant)

4. P-channel MOSFET source-to-channel tie implant (also called the ptie implant)

5. Depletion-implant (d-implant)

6. i\T+poly gate implant

7. P+ poly gate implant

8. Source/drain n+ -implant

9. Source/drain and substrate p

+-implant

In the next section, 2.1, the implant doses and energies chosen for these nine implantations

are specified. Section 2.2 presents the rationale behind the processing sequence and mask

selection in order to realize depletion-mode MOSFETs, lateral bipolar devices, and CMOS

MOSFETs with source-to-channel ties.

2.1 Implant doses and energies for the SIMOX process

Nine implantations are used in the processing of NIST9. Five of these are n-type phosphorus implants, and four are p-type boron implants. The primary target for all of these

implants is the SOI/SIMOX silicon island (which has a typical thickness of 0.15 fim) except

for the npoly and ppoly implants which are targetted for the CVD deposited polysilicon

(which has a typical thickness of 0.50 jum).

The implantation energies were chosen such that the peak concentration is placed half

way into the implanted medium. This ensures that the devices are fully depleted and that

the doping concentration is uniform throughout. The implanted energies listed in table 1 were selected based on the tables in reference [10]. These energies were slightly altered

due to processing equipment limitations. It is possible to redesign the process formula to

accomodate thicker or thinner silicon thicknesses which will allow for either a partially or

fully depleted technology.

4
For the fabrication of NIST9, the nwell and pwell doses were chosen to yield threshold

voltages of approximately 0.8 volts using n+ and p

+ polysilicon gates for the n- and pchannels, respectively.

The channel dose for the n-channel depletion-mode MOSFETs was chosen to be approximately twice the well doping, a sufficient dose to overcome the pre-existing pwell implant

and sufficient to fully deplete it.

The doses for the n- and p- source/drain implantations were chosen to be 3.0 x 1015 cm-2.

The dose of the ptie (ntie) implant was chosen to be approximately midway between the

dose of the nwell (pwell) implant and that of the n-implant (p-implant). The ptie (ntie)

implant, as well as being the source-to-channel tie for the p-channel (n-channel) MOSFETs,

doubles as the base implant of the bipolar npn (pnp) device. The dose chosen is midway

between the dose of the collector which uses the nwell (pwell) implant and the dose of

the emitter which uses the n-implant (p-implant). This helps ensure that proper bipolar

action occurs. Also, this dosage is sufficient to electrically tie the source to the channel

within a diode drop. (The ties eliminate the need for an extra contact, thereby conserving

silicon area.)

The doses for the npoly (ppoly) implant were considered standard at 5.0 X 1014 cm-2

.

2.2 Processing sequence for NIST9

The mask sequence used to fabricate NIST9 is specified in table 2. Because of the additional structures (n-channel depletion-mode MOSFETs, lateral bipolar devices, and MOSFETs with source-to-channel ties) included on NIST9 (which were not included on NIST3

and NIST4), several additional masks are required, and the following issues need to be

addressed:

1. How should the ntie, ptie, and d-implants be ordered ?

2. How should the npoly and ppoly implants be ordered ?

3. How should the substrate contacts be handled to avoid step coverage problems ?

4. How should the p-implant be ordered ?

5. Are lateral bipolar devices possible ?

With respect to the first issue, in order to electrically tie the source to the channel, the

source-to-channel ties (or implants) must occur before the polysilicon deposition and after

the well implants. Also, the d-implant needs to occur within these bounds. The order of

these three implants (ntie, ptie, and d-) is not critical.

The structures in the test library are designed to improve circuit performance by doping

the polysilicon gate with the same doping as the source and drain [11-13]. Therefore, the

npoly and ppoly implants are included in the processing immediately after the polysilicon

film deposition, yet before the polysilicon patterning (see table 2).

With respect to the third issue, the substrate contacts were designed to improve step

5
coverage by bringing the metal down to the substrate in two steps as opposed to one large

step. The first contact opening to the substrate (using the subcon mask) is large (30 fim),

and the second contact op sning (us: lg t! : >ntacts . , : k] hole is smaller (14 fim).

The p-implant occurs after the substrate contact definition (subcon). The substrate contacts are designed for use with a p-substrate or an n-substrate. In this work, a p-substrate

is used and is recommended; therefore, the j?-implant occurs after the subcon definintion.

The p-implant is placed in the substrate contact area to help create a good ohmic contact

for the aluminum-to-substrate connection. If an n-substrate is used, the n-implant occurs

after the substrate contact definition.

With respect to the fifth issue and following the processing sequence specified in table 2,

lateral bipolar devices can be included in the design and fabrication of the test library

and NIST9 with the inclusion of nine appropriately chosen and placed implants in the

processing sequence. Considering the bipolar npn (pnp) devices, the nwell (pwell) implant can be used for the collector, the ptie (ntie) implant for the base, and the n-implant (pimplant) for the emitter. These lateral npn and pnp bipolar device designs are described

in the next section.

There are many different n- and p-channel MOSFET designs and lateral npn and pnp

bipolar device designs included in the test library with various sizes and shapes. On

NIST9, five different bipolar designs are included for the npn devices and five for the pnp

devices; however, the figures and the discussion which follow refer only to the npn devices.

In this section, the following MOSFET and bipolar device designs are described (fig. 2 can be used to discern the layers for all the designs in this guide):

1. P-channel MOSFET (fig. 3)

2. iV-channel MOSFET (fig. 4)

3. Minimum-sized n-channel MOSFET (fig. 5)

4. Circular MOSFET (fig. 6)

5. Circular MOSFET with no channel contact (fig. 7)

6. H-gate MOSFET (fig. 8)

7. Italic H-gate MOSFET (fig. 9)

8. T-gate MOSFET (fig. 10)

9. H-gate MOSFET with source-to-channel tie (fig. 11)

10. T-gate MOSFET with source-to-channel tie (fig. 12)

11. JV- channel MOSFET with source-to-channel tie (fig. 13)

12. Depletion-mode MOSFET (fig. 14)

13. Lateral bipolar (npn) device with the base contact beside the emitter and with

the emitter implant incorporating the collector and emitter (fig. 15)

14. Lateral bipolar (npn) device with the base contact beside the emitter (fig. 16)

15. Lateral bipolar (npn) device with the base contact below the emitter and with

the emitter implant incorporating the collector and emitter (fig. 17)

6
16. Lateral bipolar (npn) device with the base contact below the emitter (fig. 18)

17. Lateral bipolar (npn) device as an n-channel MOSFET with the gate connected

to the channel or base (fig. 19)

Figure 3 shows the basic j9-channel MOSFET design found in the test library. In this

figure, the gate extends beyond the island edge. This decreases the leakage around the

gate.

Figure 4 shows the basic n-channel MOSFET design found in the test library. Selected

MOSFET dimensions in figure 4 were decreased, resulting in the MOSFET shown in

figure 5. Note that the n-channel MOSFET gates use the n+poly gate implant, and the

jj-channel MOSFET gates (fig. 3) use the p

+poly gate implant.

Figure 6 is a circular MOSFET with a contact to the channel, and figure 7 is a circular

MOSFET without this channel contact. These circular MOSFETs require substantial area and are more difficult to design than the basic MOSFETs. Since the gates are circular,

there can be no leakage around the gate edge since there is no edge. Therefore, they are considered to be more hardened to increased levels of radiation.

Figure 8 shows an H-gate MOSFET. As the name implies, the gate is in the shape of an "H." The italic H-gate MOSFET is shown in figure 9, and the T-gate MOSFET is shown in figure 10. The H-gate MOSFET and T-gate MOSFET each with a source-tochannel tie are shown in figures 11 and 12, respectively. These source-to-channel ties

eliminate the need for the channel contact which, in turn, conserves silicon area.

The implant for the source-to-channel tie for the MOSFETs has the same dopant type as the source and drain diffusion. As can be seen in figure 13 for an n-channel MOSFET with

a source-to-channel tie, the ntie implants extend approximately half way into the channel

area, extend beyond the island edges, and define which side of the MOSFET is the source.

Figure 14 gives an example of a typical depletion-mode MOSFET. For this structure,

the depletion implant incorporates the channel area and extends 2 /zm beyond it in all directions. This 2-/xm extension occurs when the CIF (Caltech Intermediate Form) file is created.

The first lateral bipolar (npn) design can be found in figure 15. As can be seen in this

figure, the nwell implant encompasses the whole island. The j?tie implant which defines the

base reaches approximately halfway under the polysilicon (a later step in the process). The

n-implant occurs after the polysilicon patterning, is self-aligned, and goes from collector

to emitter. When viewing the structure from left (collector contact) to right (emitter

contact), the collector starts off heavily n-doped until it reaches the gate when the true

collector is simply nwell. The base edge which is located half way under the polysilicon

is j?-type (j?tie). On the other side of the polysilicon, the n-implant overwhelmes the ptie

implant to become the emitter which completes the first lateral npn bipolar device design.

In this design, the base width is approximately half the width of the polysilicon. To design

the npn (pnp) lateral bipolar devices, the Magic layer etch (petch) was created (see table 3),

7
enabling the vertical construction of island, nwell, nndiff, npoly, and poly (island, pwell,

ppdiff, ppoly, and poly).

The second bipolar (npn) design can be found in figure 16. It is similar to the previous

design except, instead of starting at the collector contact, the n-implant starts on top of

the polysilicon and encompasses the emitter. The collector contact does have n-implant

inside it for a good ohmic contact to the nwell island, but the implant does not extend to

the polysilicon in this case.

The third bipolar (npn) design shown in figure 17 is similar to the first design shown

in figure 15 except the base contact is below the emitter contact (assuming the top of

the figure is considered the top and the bottom of the figure is considered the bottom).

Similarly, the fourth bipolar (npn) design shown in figure 18 is similar to the second design

shown in figure 16 except the base contact is below the emitter contact.

The fifth bipolar design can be found in figure 19. This is an n-channel MOSFET with

the gate connected to the channel or base.

4. Updated SOI/SIMOX Technology File

Magic is the VLSI layout editor used to design the test library, NIST8, and NIST9. It includes a technology file which allows the user to modify it according to their needs. It specifies the layers, their interaction, the design rules, and the layer selection for each mask.

The design rules are similar to those used to design NIST3 and NIST4 [2] . An abbreviated

version of the SOI/SIMOX technology file used to design the test library, NIST8, and

NIST9 is given in Appendix B.

Table 4 is a brief reference table that indicates which Magic layers correspond to which

mask for NIST9. It allows one to obtain this information without sorting through the

technology file. Table 5 yields this information for NIST8.

The main differences between the current SOI/SIMOX technology file and the one used to

build SOI/SIMOX test chips NIST3 and NIST4 [2,3] in order to fabricate depletion-mode

MOSFETs, lateral bipolar devices, and CMOS MOSFETs with source-to-channel ties are:

1. The addition of the following Magic layers:

a. JVtie - this implant is done before the polysilicon deposition, and it has

the effect of electrically tying the channel potential to within a diode

drop of the source potential for an n-channel MOSFET. This implant

also doubles as the base implant for the lateral bipolar pnp devices.

b. Ptie - this implant is done before the polysilicon deposition, and it has

the effect of electrically tying the channel potential to within a diode

drop of the source potential for a p-channel MOSFET. This implant

also doubles as the base implant for the lateral bipolar npn devices.

c. Dimplant - the d-implant (depletion-mode implant) was included for the

construction of n-channel depletion-mode MOSFETs.

d. Dfet - the dfet (depletion-mode MOSFET) was added to the Magic

8
technology file to distinguish between the different MOSFETs on the

CAD system. The dfet layer implies that there is dimplant underneath

this polysilicon gate.

e. Ppoly - this implant layer was added so that the polysilicon can be

implanted with boron for improved performance of the p-channel MOSFETs [11-13].

f. JVpoly - this implant layer was added so that the polysilicon can be

implanted with phosphorus. Poly was the Magic layer used for NIST3

and NIST4. If poly (or npoly) is specified for NIST9, it implies that this

polysilicon will be implanted with phosphorus.

g. Ppc - this contact (ppoly contact) is the ppoly-to-metall contact which

is specified whenever p-implanted polysilicon is to contact metall.

h. Pc - this contact (poly contact) is the npoly-to-metall contact which is specified whenever n-implanted polysilicon is to contact metall.

i. Etch - this layer was added to the Magic technology file in order for

Magic to place n-doped polysilicon over nndiff, nwell, and island. This

polysilicon, which is implanted with phosphorus, is used as a shield for

the npn bipolar devices and can be etched away after the p-implant if desired.

j. Petch - this layer was added to the Magic technology file in order for

Magic to place p-doped polysilicon over ppdifi, pwell, and island. This

polysilicon, which is implanted with boron, is used as a shield for the pnp

bipolar devices and can be etched away after the p-implant if desired.

k. Open - if this layer is specified, the raw silicon substrate will be exposed

to air after processing such that during the post-processing anisotropic

etch, the silicon can be etched away. This etching (or micromachining)

is done to realize suspended structures [14].

1. Hole - this layer appears only on the contact mask. This opening in the

oxide is used in the SIMS (secondary ion mass spectroscopy) structures

to facilitate the measurement of doping densities on modules AAM5 and

AAM6.

m. Legend - this layer was added to the technology file to aid in labeling

the pads for probing purposes. This layer does not appear in the CIF

file. n. Legend.backgound - this layer was added to the technology file to aid in

rapidly placing the labels within the pads. This layer does not appear

in the CIF file.

2. The layer "pad" is used to specify a bond pad. Its dimensions (before CIF) are 112 /xm by 112 fim in the test library, and the layer dimensions (after CIF) for

NIST9 are:

a. Island (112 ^m x 112 fim)

b. Polysilicon (108 fim x 108 fim)

c. JVpoly implant (108 fim x 108 /mi)

d. Contact (92 fim x 92 fim)

9
e. Metall (104 /im x 104 /mi)

The pad layer dimensions (after CIF) for NIST8 are:

a. Polysilicon (112 /xm x 112 /mi)

b. Metall (108 /mi x 108 /mi)

c. Polycontact (106 fim x 106 /mi)

d. Metal2 (104 /mi x 104 /tin)

d. M2c (102 /mi x 102 /mi)

e. Glass (100 /mi x 100 /mi)

3. For the layer "jjpad," all the above layers in item 2 for NIST9 are included except

the layer "ppoly implant" replaces "npoly implant" with the same dimensions.

Ppad is used to specify a bond pad whenever p-implanted polysilicon is used to

make the pad connection.

4. The substrate contact is treated differently and must be designed differently to

obtain working contacts. Additional information can be found in the section

called "Processing Sequence for NIST9."

5. Test Library

New test chips can be custom designed from the modules in the test library or the modules

can be used as "drop-in's." From the test library, test chip NIST8 and test wafer NIST9

were built. A module is a single (or group of) test structure(s) which can be tested by

the single positioning of one set of probes. There are five different sizes of modules (i.e.,

five different probe pad configurations); however, each module can be considered small,

medium, or large depending on the sizes of MOSFETs chosen within the module. (There

are five different probe pad configurations, but only one or two different probe cards are needed for testing.)

Figure 20 shows the outline of the test library with the corresponding possible module count

given the existing organization. There are 686-2 by 16 modules, 130-12 by 2 modules, 90-

10 by 7 modules, 72-10 by 2 modules, and 22-2 by 11 modules. This results in a total of

1000 modules, given the layout of modules shown whose area is equivalent to a quarter of a 10.16-cm (4-in.) wafer. (A 2 by 16 module implies there are 2 columns and 16 rows of

probe pads. This naming convention is true for all the other modules except for the 10 by

7 module. For this module there are 10 pads along the top, 10 pads along the bottom, 7

pads along each side, and the middle area is for circuitry.)

The five different module sizes shown in figure 20 are given in table 6. All the piobe pads

have a 200-/tm center-to- center spacing. The cell nomenclature for these modules is also

included in this table. For example, a 12 by 2 module could be called "aaS," "ooM,"

"qqL," etc. The five different module types given in table 6 can be small, medium, or large depending

on the MOSFET sizes chosen (the pad arrangements and module dimensions remain the

same). The cell names of the small modules end with an "S," the names for the medium

modules end with an "M," and for the large modules the cell names end with an "L." The

10
lower portion of table 6 gives the nominal MOSFET dimensions for the small, medium,

and large 2 by 16 modules along with a sample subcell name which is descriptive of the

MOSFET's dopant type, design, and channel dimensions.

To convert a medium module into a small module, the procedure is given in table 7. This

is a difficult task involving submicrometer dimensions and, therefore, grid alterations. It

is the last thing that is done because a .mag file magnified by a factor of 10 is needed

to design using submicrometer dimensions. Therefore, after the entire wafer is designed

except for the submicrometer dimensions, a CIF file is generated and read back in an

order of a magnitude larger. The submicrometer dimensions are then designed into the

file while considering the scale factor. The CIF file is created using a scale factor which

reduces the design by a factor of 10 and is sent to the mask makers. This resulting .cif

file will retain the submicrometer character of the design; however, if this file is read back

into Magic without magnification, the submicrometer dimensions will be rounded to the

nearest micrometer and any .cif file generated by this .mag file will exhibit the rounded

numbers and not the submicrometer dimensions. Therefore, creating the submicrometer

dimensions should be the last thing that is done before submitting a design to the mask

makers.

The 2 by 16 module is defined to be the basic module. Given a 2 by 16 probe pad

arrangement with a center-to-center pad spacing of 200 /im, it is possible to fit a MOSFET

with a channel area of 50 /mi by 50 /mi between these pads. Any pad spacing larger than

200 /mi would result in a lot of unused silicon area. Inside a 2 by 16 module, it is possible to

put six MOSFETs with individual connections to the source, gate, drain, and channel. For

this work, the substrate contact connections can be shared with neighboring MOSFETs.

Each of the six MOSFETs within the 2 by 16 module has different channel dimensions.

Also, the pad dimensions are large enough (112 /xm by 112 /mi) such that they can be

wire bonded (exposed metal area on NIST9 is 104 fim by 104 /mi). Individual packaged

modules are also possible for these narrow 2 by 16 modules [15].

The final wafer or chip can be separated using a wafer saw. The 2 by 16 modules are placed

next to each other conserving the 200-/xm center-to-center pad spacing. If the modules are separated, the narrow-bladed saw will pass through the center of the neighboring 2 by 16

modules. These sacrificed modules can be probed beforehand, or they can be duplicated

on the chip or wafer.

The large 10 by 7 modules are needed because most circuits will not fit within the 2 by

16 probe-pad arrangement. A circuit could be placed to the right of a 2 by 16 probe-pad

arrangement with the wiring routed to the appropriate pads; however, if these circuits are to be irradiated, the probes will shield parts of the circuit from the radiation while it

is being tested. Therefore, the large 10 by 7 modules have 30 pads along the periphery

(including the corners). There are 10 pads located along the top, 10 pads along the bottom,

and 7 pads on each side.

The remaining three module types are sacrificial modules used adjacent to the 2 by 16

modules and/or the large 10 by 7 modules. As shown in figure 20, the horizontal 12 by 2

modules are placed above and below the 2 by 16 modules. If a 2 by 16 module is packaged,

11
the 12 by 2 modules will be sacrificed on the ends, thus keeping intact the 2 by 16 modules

above and below the one to be packaged. In addition to the 12 by 2 modules, the 10 by

2 horizontal modules are used as the sacrificial modules above and below the large 10 by

7 modules. These large 10 by 7 modules were arranged together, in this case along the

bottom, to minimize the sawing task. And the remaining 2 by 11 modules are placed along

the bottom row of large 10 by 7 modules. The module arrangement is highly versatile.

Perhaps it is desired to package the horizontal (12 by 2 or 10 by 2) modules in which case a different approach to module placement is recommended.

Figure 21 shows the module spacings for the various modules. The module-to-module

spacing occurs in multiples of 200 /im due to the center-to-center probe-pad spacing of

200 /xm. This facilitates the placement of modules.

All MOSFETs are oriented in the same way for ease in testing. That is, the gate is the

upper left-hand probe pad, the drain is the upper right, the source the lower left, and the

channel is the lower right-hand probe pad. For a p-type substrate, the substrate connection

will be either the pad directly above the drain pad or the pad directly below the channel

pad depending upon the MOSFET's location within the 2 by 16 module arrangement. For

an n-type substrate, the substrate connection is either the pad directly above the gate pad

or the pad directly below the source pad. Given the MOSFET's location within the 2 by

16 module arrangement, the substrate connections will be in the same place on other 2 by

16 MOSFET modules. Figure 21 gives the MOSFET and substrate contact locations for

four of the five module types which have a different number of probe pads and, therefore, can accommodate a different number of MOSFETs and substrate contact arrangements.

(MOSFETs are not routinely pinned out on the large 10 by 7 modules since they fit in a more reasonable space on the other four module types.)

Table 8 lists the large 10 by 7 modules that are available in the test library. This list for the

2 by 16 modules, and the other miscellaneous modules is found in table 9. A listing of the

large 10 by 7 modules in table 8 organized by function is given in table 10 with a comparable

list of the modules in table 9 given in table 11. These lists are further subdivided into

tables 12 through 16 which list the different MOSFETs, meanders, capacitors, and dynamic

circuits.

6. Test Chip NIST8

To compare and contrast bulk CMOS and SOI processes, test chip NIST8 was constructed

from various modules in the test library. It is a CMOS-on-SOI design that was converted

to a CMOS on bulk silicon design via the technology file given in Appendix B. The CIF

file created by Magic's technology file was submitted to MOSIS for fabrication on a 2.0-/xm

(lambda=1.0) processing run. An nwell process was used; however, a pwell process would

have resulted in working parts as well.

The size of NIST8 (x=4410 //m, y=6800 /zm) was chosen to accommodate fabrication by

MOSIS. NIST8 is composed of four large 10 by 7 modules, twelve 2 by 16 modules, one 12

by 2, and three 10 by 2 modules. Figure 22 shows the cell structure of NIST8, figure 23

shows the subcell structure of NIST8, and table 17 includes the dopant type and device

12
sizes on a row and column basis. Figure 24 shows the actual layout of NIST8. The 2 by

16 modules on NIST8 include:

1. Module AM - JV-channel MOSFETs (with various lengths and widths) (see fig. 4)

2. Module BM - P-channel MOSFETs (with various lengths and widths) (see fig. 3)

3. Module CM - Minimumly designed n-channel MOSFETs (see fig. 5)

4. Module DM - Circular n- and p-channel MOSFETs with a well contact (see fig. 6)

5. Module KM - Circular n- and p-channel MOSFETs without a well contact (see % 7)

6. Module EM - H-gate MOSFETs (see fig. 8)

7. Module UM - Italic H-gate MOSFETs (see fig. 9)

8. Module FM - T-gate MOSFETs (see fig. 10)

9. Module VM - Inverters

10. Module XM - Alignment structures

11. Module AaM - Square n-channel MOSFETs

12. Module BbM - Square p-channel MOSFETs

The large 10 by 7 modules include:

1. Module DDM - An SRAM (see fig. 25)

2. Module EEM - A 23-stage ring oscillator using regular MOSFETs (see fig. 26)

3. Module GGM - A 23-stage ring oscillator using H-gate MOSFETs (see fig. 27)

4. Module OOM - Large n-channel MOSFETs for radiation investigations (see fig. 28)

And the horizontal modules include:

1. Module aaM - iV-channel MOSFETs

2. Module bbbM - P-channel MOSFETs

3. Module aaaM - Unusually sized n-channel MOSFETs

4. Module cccM - Unusually sized p-channel MOSFETs

In the test library, the substrate contacts are placed at strategic locations on each 2 by

16 module such that each test structure is adjacent to one. This is intended only for SOI

processing. For the CMOS processing of NIST8, the "substrate" connections disappear

after a CIF file is generated. In other words, what was a substrate contact, becomes metal

and p-implant, the construction of which has no purpose in CMOS. The pads labeled "W"

for "well" on NIST8 are used to bias the CMOS devices which are sufficient to probe the

MOSFETs and circuits on NIST8.

NIST8 requires the use of submicrometer dimensions in the alignment structures on module

XM. A method to obtain submicrometer dimensions on NIST8 is given in table 18. This

was the last thing done before submission to MOSIS.

All of the test structures on NIST8 (excluding the ring oscillators which were probed

manually) were probed using an HP 4062UX Semiconductor Process Control System. The

test algorithms can be found in Appendices C through F. They perform the following:

1. the test algorithm KEYSiv (Appendix C) obtains the IV data points for n- or

13
p-channel MOSFETs,

2. KEYSvt (Appendix D) obtains the Ids versus Vqs curves for various values of

VBS, 3. the test algorithm INV (Appendix E) obtains the Vjjv versus Vout data for

inverters, and

4. the test algorithm SRAM (Appendix F) plots the output of the SRAM given

various input stimulus.

All of these algorithms acquire data suitable for the evaluation procedure KEYS [5]. The

circuit diagram of the static RAM cell (and how to test it) is given in figure 29.

An example SPICE file for the MOSFETs, inverters, regular ring oscillators, H-gate ring

oscillators, and SRAM can be found in Appendices G through K. These were used in the

compui 3i pi d :edure KE k S,

7. Test Wafer NIST9

SOI/SIMOX test wafer NIST9 is comprised of numerous modules taken from the test library and organized such that they would fit onto a quarter of a 10.16-cm (4-in.) wafer.

This quarter-wafer constraint is to accommodate a 7.62-cm (3-in.) based fabrication facility

at NIST. To maximize the use of the SIMOX wafers, the 10.16-cm (4-in.) wafers were sawed

into quarters and then processed. Actually, the radius of NIST9 (if it were a whole wafer)

needed to be approximately 6 mm less than 5.08 cm (2 in.) to facilitate handling and

equipment constraints.

To easily align the masks, the locations for the main processing module, called AAM (the

only expanded module shown in fig. 30), are critical. This module, shown in figure 31,

contains the alignment marks. The alignment marks on this module are viewed and paired

with the alignment marks on another AAM processing module for mask alignment. These

main processing modules need to be separated by approximately 2.54 cm (1 in.). If they

are much closer, the alignment microscope cannot see both modules at once, and alignment

becomes a more difficult task.

The horizontal processing module AAM1 (fig. 32) appears below each main AAM module.

Module AAMl's purpose is to help grossly align those masks which have a dark field.

NIST9 includes many of the modules from the test library. The placement of the modules

on NIST9 (fig. 30) is similar to the module placement in the test library (fig. 20) except

that more large 10 by 7 modules occupy the lower portion and right-hand portion of the

wafer (without sacrificial modules surrounding them). These large 10 by 7 modules are the

process monitor modules (called AAM2 through AAM6) which will be sacrificed during

the processing. They include structures for the following:

1. cross sections for SEM,

2. SIMS targets for doping concentrations, and

3. MOSFETs to probe during processing.

14
Table 19 was used to help organize the other large 10 by 7 modules, and table 20 was used

to help organize the 2 by 16 modules that are detailed in tables 8 and 9, respectively,

To study parameter variations across the wafer, the 2 by 16 module CcM was designed.

This 2 by 16 module includes the following:

1 . a 6-/xm polysilicon cross bridge resistor,

2. an n-channel MOSFET with L=6 /xm and W=6 /xm,

3. a p-channel MOSFET with L=6 /xm and W=12 /xm,

4. an inverter with L=6 /xm, Wn =6 /xm, and Wp =12 /xm, and

5. a jp-channel MOSFET with L=6 /xm and W=6 /xm.

This is referred to as the KEYS module in table 20 which occupies every other 2 by 16

module slot on the wafer. The MOSFETs and inverters on this module can be tested on the

HP 2062UX using the test algorithms in Appendices C, D, and E. The data from these test structures can be evaluated (and wafer maps obtained) by the computer procedure KEYS.

Also, the horizontal 12 by 2 module bbM includes the same structures listed above except

for the p- channel MOSFET with L=6 /xm and W=6 /xm. On this horizontal module, the

structures are rotated 90 deg to make horizontal and vertical parameter mapping possible.

The remaining 2 by 16 modules include the following:

1. MOSFETs - oriented such that the gate is the upper-left-hand probe pad, the

drain is the upper-right-hand probe pad, the source is the lower-left, and the

channel is the lower-right. The IV characteristics and threshold voltage data can be compared for the differently designed MOSFETs with the same channel

dimensions. The differently designed MOSFETs include:

a. N- and p-channel MOSFETs (with and without source-to-channel ties)

b. Depletion-mode MOSFETs

c. Circular MOSFETs (with and without channel contacts)

d. H-gate MOSFETs with the same dimensions as the T-gate MOSFETs

(with and without source-to- channel ties)

e. Italic H-gate MOSFETs

f. T-gate MOSFETs (with and without source-to-channel ties)

2. Contact resistors

3. Cross-bridge resistors

4. Inverters

5. E-beam X-ray alignment structures

6. Lateral bipolar npn and pnp devices

The large 10 by 7 modules are intended to be used for radiation studies. The circuitry

is within the area to be bonded, and therefore, the probes will not block any incoming

radiation. The large 10 by 7 modules on NIST9 include the following:

1. The processing modules

2. Large capacitors from which to obtain various capacitance values

3. Three different varieties of meanders of different types

15
4. Ring oscillators pinned out for a 2 by 16 or a square probe card. All the different

ring oscillators use the same pinout. The different 23-stage ring oscillator modules

include the following MOSFET designs:

a. N- and p-channel MOSFETs (with and without source-to-channel ties)

b. Circular MOSFETs (with and without channel contacts)

c. H-gate MOSFETs (with and without source-to- channel ties)

d. T-gate MOSFETs (with and without source-to-channel ties)

5. SRAMs using n- and p-channel MOSFETs and circular MOSFETs

6. Diodes

7. Van der Pauws (dopant resistivity devices)

8. Suspended structures including MOSFETs, diodes, resistors, and an OH breath

analyzer (see fig. 33)

The OH breath analyzer (fig. 34) [16] is a micromachined structure which suspends the

central trampoline-like area by the support arms. This suspension occurs after the NIST9

wafer is selectively protected with glass (which is not included in the 14-mask process) and

then a post-processing anisotropic etch [14] is performed which etches away the raw silicon

exposed in the designed open areas. After a sufficient amount of time in the etch solution, a large inverted pyramidal pit is formed whose rectangular base edges are adjacent to the

inside dimensions of the p-implant, which is an effective etch stop, leaving the island with

the diffused resistor mainly encompassed in oxide and suspended in air. On the right of this

suspended island are contacts to the island and a glass cut covering both these contacts.

When the diffused resistor heats the suspended island up to 300 °C, if the glass opening is covered with a thin layer of bismuth, the resistance between those two contacts will change

significantly in the presence of OH which can come from the breath of an intoxicated

individual.

8. Conclusions

With the experience gained from the design, fabrication, and testing of NIST3 and NIST4

[2,3], a test library, NIST8, and NIST9 were designed to evaluate and compare CMOS test structures, including devices and circuits, fabricated on both bulk silicon and SOI/SIMOX

wafers. This is the design and testing guide for the test library, NIST8, and NIST9.

The test library was created from which the CMOS test chip NIST8 was designed and

subsequently fabricated through MOSIS (on bulk silicon only), and the SOI/SIMOX test wafer NIST9 (a 14-mask process) was designed for fabrication at the NIST processing

facility or for outside users of this design.

The processing sequence for the NIST9 SOI/SIMOX process was presented in section 2

along with the implant doses and energies chosen for the nine implantations which are optimized for fully depleted devices on 0.15 fim silicon on buried oxide. These nine implantations made it possible to realize depletion-mode MOSFETs, lateral bipolar devices,

and CMOS MOSFETs with source-to-channel ties, the designs of which are presented in

section 3. Suspended structures were also designed which will require a protective glass

coating (NIST9 does not have this) and a subsequent post-processing etch.

16
The technology file of Magic (the CAD graphic layout editor used in this work) was modified to make the design of the 14-mask SOI/SIMOX process possible. This technology

file converts the CMOS and lateral bipolar SOI design of the test library into the CMOS

design of test chip NIST8 and/or the SOI design of test wafer NIST9. This is done in the

"cifoutput" section of the technology file. Given the test results from NIST9, the CMOS device and circuit parameters from NIST8

can be presented and compared with the SOI device and circuit parameters from NIST9.

Using the computer procedure KEYS, the parameters from the IV characteristics for the

different MOSFET and circuit designs included on NIST8 and NIST9 can be evaluated,

parameter correlation coefficients can be obtained, and parameter wafer maps can be

generated, yielding conclusions for future designs and processes.

9. Acknowledgments

We would like to thank P. Roitman, L. W. Linholm, and F. F. Oettinger for their support

in making this project possible. Inputs from the NIST Processing Facility, especially D.

B. Novotny and J. E. Luther, in regards to their needs with respect to our design are acknowledged. For comments on this report, we thank C. A. Zincke, L. W. Linholm, F.

F. Oettinger, R. L. Mattis, and especially G. J. Campisi. We appreciate the editorial

assistance of E. J. Walters and J. M. Rohrbaugh, and we thank R. J. Mele for graphics

support.

10. References

[l] Richardson, L., et al., MOSIS User Manual, University of Southern California (1988).

[2] Marshall, J. C, Cresswell, M. W., Ellenwood, C. H., Linholm, L. W., Roitman, P.,

and Zaghloul, M. E., The Design Guide for CMOS-on-SIMOX Test Chips, NIST3 and

NIST4, NISTIR 4889 (January 1993).

[3] Marshall, J. C, Cresswell, M. W., Ellenwood, C. H., Linholm, L. W., Roitman, P., and

Zaghloul, M. E., The Test Guide for CMOS-on-SIMOX Test Chips, NIST3 and NIST4,

NISTIR 4890 (January 1993).

[4] Scott, W., Mayo, R., Hamachi, G., and Ousterhout, J., 1986 VLSI Tools: Still More

Works by the Original Artists, Computer Science Division (EECS), Univ. of California,

Berkeley, Report No. UCB/CSD 86/272 (December 1985).

[5] Marshall, J. C, and Mattis, R. L., Semiconductor Measurement Technology: Evaluating

a Chip, Wafer, or Lot Using SUXES, SPICE, and STAT2, NIST Special Publication

400-90 (April 1992).

[6] Doganis, K., and Dutton, R. W., SUXES: Stanford University Extractor of Model

Parameters (Users Manual), U.S. Army Research Office Contract No. DAAG-29-80-KC-0013 and DARPA Contract No. MDA903-79-C-0257, Integrated Circuits Laboratory,

Stanford University, Stanford (November 1982).

17
7] Nagel, L. W., SPICE2: A Computer Program to Simulate Semiconductor Circuits,

Memorandum No. ERL-M520, Electronics Research Laboratory, University of California, Berkeley (May 1975).

[8] Mattis, R. L., Semiconductor Measurement Technology: A FORTRAN Program for

Analysis of Data from Microelectronic Test Structures, NBS Special Publication 400-

75 (July 1983); Matttis, R. L., and Zucker, R., Release Notes for STAT2 Version 1.31:

An Addendum to NBS Special Publication 400-75, NBSIR 83-2779 (November 1983);

Mattis, R. L., Release Notes for STAT2 Version 1.7: An Addendum to NBS Special

Publication 400-75, NBSIR 86-3333 (March 1986).

[9] Marshall, J. C. and Zaghloul, M. E., Color Supplement to NIST Special Publication

400-93: Semiconductor Measurement Technology: Design and Testing Guides for the

CMOS and Lateral Bipolar-on-SOI Test Library, NISTIR 5324 (March 1994).

[10] Colclaser, R. A., Microelectronics: Processing and Device Design (John Wiley &z Sons,

Inc., 1980), pp. 152-153.

[11] El-Kareh, B., Abadeer, W., and Tonti, W., Design of Submicron PMOSFETs for

DRAM Array Applications, IEEE International Electron Devices Meeting, December

1991, 13.7, pp. 379-384.

[12] Oikawa, K., Ando, S., Ando, N., Horie, H., Toda, Y., and Hijiya, S., P-f Polysili- con Gate P-MOSFETs Using BC1 Implantation, IEEE International Electron Devices

Meeting, December 1991, 3.8, pp. 79-82.

[13] Mogami, T., Johansson, L., Sakai, I., and Fukuma, M., Hot-Carrier Effects in Surface

Channel PMOSFETs with BF2- or Boron-Implanted Gate, IEEE International Electron

Devices Meeting, December 1991, 19.3, pp. 533-536.

[14] Marshall, J. C, Parameswaran, M., Zaghloul, M. E., and Gaitan, M., High-Level CAD

Melds Micromachined Devices with Foundries, IEEE Circuits and Devices 8 (6), 10-17

(November 1992).

[15] Conversations with G. Harman (bonding/packaging expert), NIST, Gaithersburg, Md.

[16] Conversations with M. Parameswaran (micromachining expert), Simon Fraser University, Burnaby, British Columbia.

18
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Figure 3. P-channel MOSFET found in the test library, NIST8, and NIST9.

21
Figure 4. JV-channel MOSFET found in the test library, NIST8, and NIST9.

22
Figure 5. Minimum-sized n-channel MOSFET found in the test library, NIST8, and NIST9.

23
24
Figure 7. Circular n-channel MOSFET with no channel contact found in the test library,

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25
Figure 8. H-gate MOSFET found in the test library, NIST8, and NIST9.

26
Figure 9. Italic H-gate MOSFET found in the test library, NIST8, and NIST9.

27
Figure 10. T-gate MOSFET found in the test library, NIST8, and NIST9.

28
Figure 11. H-gate MOSFET with source-to-channel tie found in the test library, NIST8,

and NIST9.

29
30
Figure 13. JV-channel MOSFET with source-to- channel tie found in the test library and

NIST9.

31
Figure 14. JV-channel depletion-mode MOSFET found in the test library and NIST9.

32
33
I

Figure 16. Second bipolar design (npn) on NIST9 with the base contact beside the emitter

and with a half implant.

34
Figure 17. Third bipolar design (npn) on NIST9 with the base contact below the gate

and with a full implant.

35
Figure 18. Fourth bipolar design (npn) on NIST9 with the base contact below the gate

and with a half implant.

36
Figure 19. Fifth bipolar design (npn) on NIST9 with an n-channel MOSFET gate

connected to its base.

37
51

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Figure 20. Cell structure of the test library with module count.

38
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Figure 21. Module spacings used in the test library, NIST8, and NIST9.

39
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DDM EEM

DDM_0

BbM

EEM_0

0

cccM

cccM 0

GGM

!bM_0

OOM

GGM_0 OOM_0

Figure 22. Cell structure of NIST8.

40
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42



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Figure 30. Cell structure of the SOI/SIMOX test wafer NIST9.

48
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52
Table 1 - Doses and Energies for the Implantations on NIST9

IMPLANT MASK DOPANT DOSES AND ENERGIES (ASSUMING T=0.15 DM)

1. JVwell Phosphorus 8x1

11 /cm2 « 50 keV S .33xl016 /cm3

2. Pwell Boron 8x10" /cm2 20 keV 5 .33xl016 /cm3

3. Nile Phosphorus 3xl013 /cm2 a 50 keV 2 .0xl0 18 /cm3

4. Ptie Boron 3xl013 /cm2 20 keV 2 .0xl0 18 /cm3

5. D-implant Phosphorus 2xl012 /cm2 « 50 keV 1 .33xl017 /cm3

6. N-implant Phosphorus 3xl015 /cm2 50 keV 2 .0xl020 /cm3

7. P- implant Boron 3xl015 /cm2 20 keV 2 .0xl020 /cm3

IMPLANT MASK DOPANT DOSES AND ENERGIES (ASSUMING T=0.50 UM)

8. jVpoly Phosphorus 5xl014 /cm2 180 keV = 1.0xl019 /cm3

9. Ppoly Boron 5xl014 /cm2 « 60 keV = 1.0xl019 /cm3

53
Table 2 - Mask Processing Sequence for NIST9

CIF CALM CLEAR (C) OR

MASK NAME NUMBER* DARK (D) FIELD

1. Island SIL 1 C

2. JVwell SWN 2 D

3. Pwell SWP 3 D

4. iVtie SNT 4 D

5. Ptie SPT 5 D

g D — t TTiT* 1 ft n +; XJ ±1UU J- GL1L U SDF nU

7. iVpoly SNP 7 D

8. Ppoly SPP 8 D

9. Polysilicon SPG 9 C

10. i^-implant SND 10 D

11. Subcon SCS 11 D

12. P- implant SPD 12 D

13. Contacts SCT 13 D

14. Ml SMF 14 C

15. Glass

(optional)

SOG 15 D

: x = 44,820 fim y = 45,020 fxm (before and after CIF)

The smallest dimension for each mask was 1 /xm appearing in subcell

chevron. mag.

* Mask data can be presented to the mask maker using Calma numbers as well

as CIF names.

54
Table 3 - Magic Layer Used for MOSFET

Devices and the Mask Numbers Involved

Gates or a Shield for Bipolar

in the Processing

FET OR

BIPOLAR

STRUCTURE

MAGIC

LAYER

MASKS

USED

1. n-channel MOSFET gates

(and surrounding poly)

poly 7 & 8 (poly ft npoly)

2. p-channel MOSFET gates

(and surrounding poly)

ppoly 7 ft 9 (poly ft ppoly)

3. most npn shields

(and surrounding poly)

etch 7 ft 8 (poly ft npoly)

4. most pnp shields

(and surrounding poly)

petch 7 ft 9 (poly ft ppoly)

55
Table 4 - Magic Layers, CIF Names, and Calma Numbers (as found in the

Cifoutput Section of the Technology File) Associated with the SOI Masks

MASK MAGIC LAYERS SOI CALMA

DEFINITION INCLUDED CIF NAME NUMBER

1. alllsland,

pad, ppad

il , ilc

pad, ppad

SIL 1

2. allNwell nw , nwc SWN 2

3. allPwell pw.pwc StfP 3

4. ntie ntie SNT 4

5. ptie ptie SPT 5

6. dfet.grow 200

dimplant

df et

dimplant

SDF 6

7. pad, ppad

shrink 200

allNpoly , allPpoly

,

etch, petch

grow 100, shrink 100

pad .ppad

poly,ppoly,pc,ppc

nf et , df et , pf e

t

ndpc,pdpc

etch, petch

SPG 7

8. pad, shrink 200

allNpoly , et ch

grow 100, shrink 100

pad

poly ,nf et ,df et

pc,ndpc,etch

SNP 8

9. ppad, shrink 200

allPpoly , petch

grow 100, shrink 100

ppad

ppoly rr J iPf et 'XT ppc,pdpc, petch

SPP 9

10. allNdiff ndiff , ndc , nndiff , nwc

nfet ,df et ,ndpc

SND 10

11. substrate,

subcon , open

substrate

subcon , open

SCS 11

12. allPdiff pdiff , pdc , ppdiff , pwc

pf et ,pdpc

SPD 12

13. subcon , pad , ppad

contacts

shrink 200

open, hole

subcon , pad , ppad

Tl H f* T\Af TlCTf T> <"* ILLiLo y UULw y ILVfW y WWW

pc,ppc,ilc

ndpc,pdpc

open, hole

SCT 13

14. pad, ppad

shrink 400

allMetall

grow 200, shrink 200

pad , ppad

ml , pc , ppc , ndpc , pdpc

ndc , pdc , nwc , pwc

ilc, subcon

SMF 14

15. pad, ppad

shrink 600

glass, open

pad, ppad

glass

open

SOG 15

56
Table 5 - Magic Layers, CIF Names, and Calma Numbers (as found in the Cifoutput Section of the Technology File) Associated with the MOSIS CMOS Masks

MASK MAGIC LAYERS CMOS CALMA

DEFINITION INCLUDED CIF NAME NUMBER

7.

10.

11

12

allNwell

allPwell

pad

shrink 400

allMetal2

pad

shrink 200

allMetall ,m2c

allPoly

pad

allNdiff

allPdiff

and alllsland

pad

shrink 400

m2c

shrink 100

ndiff ,nf et

grow 200

allNdiff

pdiff ,pf et

grow 200

allPdiff

ndc , pdc , pwc , nwc

shrink 200

pad

shrink 100

pc , ndpc , pdpc

shrink 200

pad

shrink 600

glass

nw , nwc

pw,pwc

pad

m2

m2c

pad, ml ,pc,ppc

ndpc, pdpc

ndc, pdc

nwc, pwc

ilc, subcon

m2c

poly,ppoly,pc,ppc

nf et ,pf et ,df et

ndpc, pdpc

pad

ndiff , ndc

nndiff ,nwc

nf et ,df et ,ndpc

pdiff ,pdc

ppdiff ,pwc

pf et , pdpc

il,ilc

pad

m2c

ndiff ,nf et

ndc , nndiff , df et

nwc, ndpc

pdiff ,pf et

pdc, ppdif

f

pwc, pdpc

ndc , pdc , pwc , nwc

pad

pc, ndpc, pdpc

CWN

CWP

CMS

CMF

CPG

CAA

pad

glass

CVA

CSN

CSP

CCA

CCP

COG

10

11

12

57
Table 6 - Module Cell Names, Dimensions, and Pad Arrangement for the

Different Module Sizes Followed by the MOSFET Dimensions and Sample

Subcell Name for the 2 by 16 Small, Medium, and Large Modules

MODULE NAMES DIMENSIONS PAD ARRANGEMENT

1. AAS to ZZS

AAM to ZZM

AAL to ZZL

DLM,IRM,DI0,DI01

width = 1912 fim

height = 1312 fim

10 by 7

30 pads

(10 top, 10 bottom

7 right, 7 left)

AS to ZS

AM to ZM

AL to ZL

AaM to ZzM

width = 312 fim

height = 3112 fim

2 by 16

3. aaS to zzS

aaM to zzM

aaL to zzL

width = 2312 fim

height = 312 fim

12 by 2

aaaS to zzzS

aaaM to zzzM

aaaL to zzzL

AAM1

width = 1912 fim

height = 312 fim

10 by 2

aaaaS to zzzzS

aaaaM to zzzzM

aaaaL to zzzzL

width = 312 fim

height = 2112 fim

2 by 11

MODULE SIZE MOSFET CHANNEL DIMENSIONS SAMPLE SUBCELL NAME

A. Small modules L = 0.2, 0.3, 0. 4, 0.5, 0.6, 0. 8 fim pl02w6

(ending with 'S') W = 6 fim

B. Medium modules L = 2, 3, 4, 5, 6, 8 fim nl2w6

(ending with 'M') W = 6 fim

C. Large modules L = 12, 13, 14, 15, 16, 18 fim nll2w6min

(ending with 'L') V = 6 fim

58
Table 7 - Method Used to Make a Medium Module into a Small Module on NI5T9

% cd~/simox

X cp BM.mag B.mag

'/, magic B

change label to BS

delete the cells

rename the cells for the appropriate dimensions

replace the cells in the module

change labeled dimensions

:cif ostyle asis

: cif

: writeall

: quit

'/, cd~/simoxsub

'/, cp ~Vsimox/B . cif

'/, magic -Tsimox junk

:cif istyle inlOx

:cif read B

: writeall

: quit

'/, cp B.mag BlOO.mag

'/, rm B.mag

'/, magic B100

use the appropriate subcon cells (e.g., subconupS and subconS)

edit the cells for the correct submicron dimensions

:writeall

:quit

'/, cp BlOO.mag BS.mag

'/, magic waferS

: get cell BS

: writeall

: quit

59
Table 8 - Module Name, Label, and Description for the Large 10 by 7 Modules

MODULE MODULE LABEL DESCRIPTION

S M L

AAM

AAM2

PROC

PROC-RES

- AAM3 -

- AAM4 -

PROC-TRAN

PROC-ITRAN

- AAM5 -

- AAM6 -

- BBM -

PROC-SIMS

PROC-SIMS

NXTORS

- CCM -

- CCM1 - - CCM2 -

CAPS *

CAPS * CAPS

Processing structures

Processing structures

Two resistors with L=500 fim, W=1500 /xm

1. nwell = channel

nndiff = source/drain

2 . pwell = channel

ppdiff = source/drain

Processing structures

Two transistors with L=500 fim, V=1500 fim

1. n-channel MOSFET

2. p-channel MOSFET

Processing structures

Two interdigitated MOSFETs

(7-1500 fim x 10 /xm gates)

1. n-channel MOSFET

2. p-channel MOSFET

Two MOSFETs to probe during processing

1. n-channel MOSFET, L=10 fim, W=20 fim

2. p-channel MOSFET, L=10 fim, W=20 fim

Processing structures - 6 SIMS targets

(500 fim x 500 fim) for:

nwell, ntie, ndiff

pwell, ptie , and pdiff

Processing structures - 6 SIMS targets

(500 fim x 500 /xm) for:

il, poly, ml

dimplant , ppoly, and m2

Circular MOSFETs, multi-edged MOSFETs,

many-fingered MOSFETs, and regular MOSFETs

with same channel length - except for the

one in the middle

- gate = box 17x17 /xm with 7 reps

- source/drain = box 20x20 fim with 10 rep

- L=20 fim W=27r(30)=188.4 /xm " Lm,d=500 fim Wmtd=50 fim

Capacitors with and without body contact

(200 x 200 fim)

Miscellaneous capacitors (200 x 200 fim)

Capacitor (1312 x 1530 fim)

60
- CCM3 - CAPS

- COM4 - CAPS

- CCM5 - CAPS

- CCM6 - CAPS

- CCM7 - CAPS

- CCM8 - CAPS

- CCM9 - CAPS

DDS DDM DDL SRAM

EES EEM EEL RING23

- FFM - CIRC23

GGS GGM GGL RINGHG

HHS HHM HHL RINGTG

IIS IIM IIL TIE23

- ml /sub 22 pF with tox=8000 A

Capacitors (1300 x 775 /xm) - ml/il 22 pF with tox=4000 A

- ml/poly 18 pF with tox=5000 A

Capacitors (1300 x 775 /xm) - poly/sub 22 pF with tox=4000 A

- il/sub 22 pF with tox=4000 A

Capacitors (1300 x 775 /xm) - ppoly/sub 22 pF with tox=4000 A

- ml/ppoly 18 pF with tox=5000 A

Capacitors (625 x 775 /xm) - poly/il 86 pF with tox=500 A

- ppoly/il 86 pF with tox=500 A

- ppoly/nndiff tox=500 A

- ppoly/ppdiff tox=500 A

Capacitors (1312 x 1530 /xm) - ml/poly/il/sub

Capacitors (1312 x 1530 /xm) - ml/ppoly/il/sub

Capacitors (625 x 775 /xm) - poly/il 86 pF with tox=500 A

- ppoly/il 86 pF with tox=500 A

- poly/nndiff tox=500 A

- poly/ppdiff tox=500 A

1-bit static RAM

- with selected SRAM parts pinned out

23-stage ring oscillator

- ringinv (period=88) , amp, nand

nringinv

pringinv

Wn /Ln

= 24/6

Vp /Lp = 48/6

Ring oscillator with circular MOSFETs

- ampcirc

- ngate box 5x5 /xm with 3 reps L=6 /xm - nS/D box 8x8 /xm with 5 reps

Wn=27r(13)=81.7 fim

Wp =164 /xm

Ring oscillator with H-gate MOSFETs

Ring oscillator with T-gate MOSFETs

Ring oscillator with MOSFETs using

source-to-channel ties

(period=56) - nl2w6tie

ringtie

61
JJS JJM JJL

KKS KKH KKL

- LLM -

- MMM -

- NNM -

- NNM1 -

OOS 00M OOL

- PPM -

- QQM -

- QQM1 -

- RRM -

- SSM -

- TTM -

- TTM1 -

- TJTJM -

- VVM -

- WWM -

HGTIE

TGTIE

CIRCNOC

SRAMCIRC

VANPAUW

VANPAUW

NXTORS

IL

POL

PPOL

Ml

M2

POLIL

PPOLIL

M2IL

M2P0L

M1IL

- XXM - M1POL

Ring oscillator with H-gate MOSFETs using

source-to-channel ties

Ring oscillator with T-gate MOSFETs using

source-to-channel ties

Ring oscillator with circular MOSFETs

with NO channel contact

ampcircnoc

1-bit static RAM using circular MOSFETs

- with selected SRAM parts pinned out

sramcellcirc

ampc ire

Wn=82 fim

Wp=6xWn =492 /im

Van der Pauw structures

Lm»d = 500 fim Vmid = 50 /xm

Van der Pauw structures (using jppoly plate)

l*mid = 500 fim Vmid = 50 /zm

Multi-edge MOSFETs, multi-fingered MOSFETs,

and italic H-gate MOSFETs

Island meander structure

- checks shorts, opens

edges, straight

horiz , vert

make Kelvin measurement too

Poly meander structure

Ppoly meander structure

Ml meander structure

M2 meander structure

Poly/island step coverage meander structure

- checks poly/island step coverage

- detects poly/island shorts

- checks continuity

- horiz, vert

Ppoly/island step coverage meander structure

M2/island step coverage meander structure

M2/poly step coverage meander structure

Ml/island contact meander structure

- tests step coverage

- integrity of glass between ml and

island

- detects ml/island shorts

- checks continuity

- horiz, vert

Ml/poly contact meander structure

62
XXM1

YYM

ZZM

DLM

IRM

DIG

- DI01 -

M1PPOL

M2M1 * SUB

THREADDIS

IR74X150

NDIODE

PDIODE

Ml/ppoly contact meander structure

M2/ml contact meander structure

Substrate contact meander structure

- tests continuity of ml into subcon

- horiz, vert

Threading dislocation structures

Suspended structures

A meandering ndiode

- for lifetime measurements

A meandering pdiode

- for lifetime measurements

* This module appears in the test library but not on NIST9.

Also, no small modules appear on N1ST9.

FOR THE LARGE 10 BY 7 MODULES:

S (Small) L=2 fim W„=24 fim

M (Medium) L=6 fim Wp=48 fim

L (Large) L=10 fim

63
Table 9 - Module Name, Label, and Description for the 2 by 16 Modules,

the 12 by 2 Modules, the 10 by 2 Modules, and the 2 by 11 Module

MODULE MODULE LABEL DESCRIPTION

S M L

1. The 2 by 16 ModulesAS AM AL

BS BM BL

CS CM CL

- DM -

ES EM EL

FS FM FL

- GM GL

HS HM HL

IS IM IL

JS JM JL

- KM -

- LM -

NCHAN

PCHAN

NMIN

CIRC

HG

TG

TI2

DFET

HGTIE

TGTIE

CIRCNOC

CONRES

iV-channel MOSFETs

- nl2w6

- contacts 8x8

P-channel MOSFETs

- pl2w6

- contacts 8x8

Minimum sized MOSFETs

- nl2w6min

- contacts 8x8

Circular MOSFETs

- nl6w82circ

- contacts 8x8

H-gate MOSFETs

- nl2w20hg

- contacts 8x8

T-gate MOSFETs

- nl2w20tg

- contacts 8x8

MOSFETs with source-to-channel tie

- nl2w20tie

- contacts 8x8

Depletion-mode MOSFETs

- dl2w6

- contacts 8x8

H-gate MOSFETs with source-to-channel tie

- nl2w20hgtie

- contacts 8x8

T-gate MOSFETs with source-to-channel tie

- nl2w20tgtie

- contacts 8x8

Circular MOSFETs with no channel contact

- nl6w82circnoc

- contacts 8x8

Contact resistors

- conpoly4x4, conndiff4x4, conpdiff4x4,

conil4x4

64
- MM - CONRES Contact resistors

- conpoly6x6, conndiff6x6, conpdiff6x6,

conil6x6

- NM - CONRES Contact resistors

- conpoly8x8, conndiff8x8, conpdiff8x8,

coni!8x8

- OM - CONRES Contact resistors

- conpolyl6xl6, conndiff 16x16,

conpdiff 16x16, coni!16xl6

- PM - CONRES * Contact resistors

- convia4x4, conisl4x4, connw4x4,

conpw4x4, convia4x4, conisl4x4

- PM1 - CONRES Contact resistors

- conppoly4x4, conisl4x4, connw4x4,

conpv4x4, conppoly4x4, conisl4x4

- QM - CONRES * Contact resistors

- constringvia, constringpol,

constringndiff , constringpdiff

,

constringvia, constringpol

- QM1 - CONRES Contact resistors

- constringppol, constringpol,

constringndiff, constringpdiff

,

constringppol, constringpol

RS RM RL CB * Cross bridges

- cbm2, cbml, cbpol

RSI RM1 RL1 CB Cross bridges

- cbppol, cbml, cbpol

SS SM SL CB Cross bridges

- cbnd, cbpd, cbnfet

TS TM TL CB Cross bridges

- cbnw, cbpw, cbpfet

US UM UL ITHG Italic H-gate

- nl2w6ithg

VS VM VL INVS Inverters

- inv3, inv4, inv5, inv6

WS WM WL INVL Inverters

- inv7, inv8, inv9, invlO

- XM - ALI * E-beam X-ray alignment structures - 4 /zm - m2vanpauw, mlvanpauw,

- alignviamla, alignviamlb

- YM - ALI * E-beam X-ray alignment structures - 4 fim - mlavanpauw, polvanpauw,

- alignconpolya, alignconpolyb

- ZM - ALI * E-beam X-ray alignment structures - 4 fim

65
AaM -

BbM -

CcM - DdM -

EeM -

FfM -

GgM r

HhM -

IiM -

JjM -

KkM -

L1M -

MmM -

NnM -

OoM -

PpM -

NSQUARE

P SQUARE

KEYS

BICMOS

ALI

ALI

BICMOS

ALI

BICMOS

BICMOS

BICMOS

BICMOS

BICMOS

BICMOS

BICMOS

BICMOS

- mlbvanpauw, ilvanpauw,

- alignconila, alignconilb

Unusually- sized n-channel MOSFETs

3/3, 4/4, 5/5, 6/6, 10/10, 20/20,

30/30, 6/30, 30/6

Unusually-sized p-channel MOSFETs

3/3, 4/4, 5/5, 6/6, 10/10, 20/20,

30/30, 6/30, 30/6

KEYS structures

Lateral bipolar structures - npn

- base contact beside the emitter

- implant all the way across

E-beam X-ray alignment structures - 8 fim - poly/ml

E-beam X-ray alignment structures - 8 /xm - il/ml

Lateral bipolar structures - pnp

- base contact beside the emitter

- implant all the way across

E-beam X-ray alignment structures - 8 fim - ppoly/ml

Lateral bipolar structures - npn

- base contact beside the emitter

- implant 1/2 way across

Lateral bipolar structures - pnp

- base contact beside the emitter

- implant 1/2 way across

Lateral bipolar structures - npn

- base contact below gate

- implant all the way across

Lateral bipolar structures - pnp

- base contact below gate

- implant all the way across

Lateral bipolar structures - npn

- base contact below gate

- implant 1/2 way across

Lateral bipolar structures - pnp

- base contact below gate

- implant 1/2 way across

Lateral bipolar structures - npn

- like an n-channel M0SFET with the

gate connected to the base

Lateral bipolar structures - pnp

- like a p-channel M0SFET with the

66
gate connected to the base

2. The 12 by 2 Modules

- aaM - NODD Unusually-sized n-channel MOSFETs

- bbM - KEYS KEYS structures (horizontal)

3. The 10 by 2 Modules

- AAMI - PROC

- aaaM - NODD

- bbbM - PODD

- cccM - PODD

4. The 2 by 11 Module

- aaaaM - KEYS * KEYS structures

Processing structures

Unusually-sized n-channel MOSFETs

Unusually-sized channel MOSFETs

Unusually-sized p-channel MOSFETs

* This module appears in the test library but not on NIST9.

Also, no small modules appear on N1ST9.

FOR THE 2 BY 16 MODULES:

S (Small) L=0.2, 0.3, 0.4, 0.5, 0.6, 0.8 fim

M (Medium) L=2, 3, 4, 5, 6, 8 fim W=6 /xm

L (Large) L=12, 13, 14, 15, 16, 18 fj,m

67
Table 10 - List of Large 10 by 7 Modules in the Test Library Organized by

Function

MODULE FUNCTION

CCM.CCMl

CCM2-CCM9

Capacitors - see tables 14 and 15

PPM-ZZM

QQM1,TTM1,XXM1

Meanders - see table 13

DDM-MMM

DDS-EES, DDL-EEL

GGS-KKS , GGL-KKL

Dynamic circuits - see table 16

AAM Processing structures

BBM Circular, multi-edged, many-fingered,

and regular MOSFETs

NNM.NNMl Van der Pauw dopant resistivity test structures

OOM

OOS.OOL

Multi-edge MOSFETs , multi-fingered MOSFETs,

and italic H-gate MOSFETs

DLM Threading dislocation structures

IRM Suspended structures

DI0,DI01 Meandering diodes

68
Table 11 - List of All But the Large 10 by 7 Modules in the Test LibraryOrganized by Function

MODULE FUNCTION

AM-KM,UM

AS-CS.AL-CL

ES-FS ,EL-GL

HS-JS.HL-JL

US.UL

MOSFETS - see table 12

LM-QM

PM1 , QH1

RM-TM

RS-TS, RL-TL

RS1,RM1,RL1

Contact resistors

Cross-bridges

VM-WM

VS-WS, VL-WL

XM-ZM

EeM, FfM, HhM

AaM, BbM

aaM , aaaM

,

bbbM, cccM

Inverters

E-beam x-ray alignment structures

Unusually-sized MOSFETs

CcM, bbM,

aaaaM

KEYS structures

DdM, GgM

IiM, JjM

KkM, L1M

MmM, NnM

OoM, PpM

AAMI

Lateral bipolar structures

Processing structures

69
Table 12 - List of Modules Consisting of MOSFETs Found in the Test Library

with a Sample Subcell Name Given

MODULE

S M L

FUNCTION SAMPLE SUBCELL NAME

AS AM AL n- channel MOSFETs nl2w6

- GM GL n-channel MOSFETs with a source-to-channel tie

nl2w20tie

CS CM CL minimum sized n-channel

MOSFETs

nl2w6min

BS BM BL p-channel MOSFETs pl2w6

HS HM HL depletion-mode MOSFETs dl2w6

- DM - WJ.iTCttJ.ai n it ^11 1 at n7* TM An/4 CLILU. n»^n5mnAl Jt wXLcLXlXLcJX MOSFETs

ti"1 RoR9ri T*r>

- KM - circular n- and p-channel

nusr£iis with no cnannex

contact

nl6w82circnoc

ES EM EL H-gate n-channel MOSFETs nl2w20hg

13T«? TMjLii TTJ.i-1 nH—gai/6 ira+a n-rfiBTinal 74 ciicuiilex Mfl nujrLis QPFTo

with a source-to-channel

tie

US UM UL italic H-gate n-channel

MOSFETs

nl2w6ithg

FS FM FL T-gate n-channel MOSFETs nl2w20tg

JS JM JL T-gate n-channel MOSFETs

with a source-to-channel

tie

nl2w20tgtie

AaM, aaM, aaaM unusually- sized n-channel MOSFETs

BbM, bbbM, cccM unusually-sized p-channel MOSFETs

70
Table 13 - List of Modules Consisting of Meanders Found in the Test Library

TYPE OF MEANDER MODULE LAYER(S) INVOLVED

1. INDIVIDUAL MEANDERS - checks for shorts and opens at corners and along

straight lines for horizontal and vertical alignments

- Kelvin measurements are possible

- 597 corners for the 8-/im meander

- 567 corners for the 3-, 4-, and 6-fim meanders

PPM island

QQM poly

QQM1 pp°iy

RRM ml

SSM m2

2. STEP COVERAGE MEANDERS - checks for step coverage, shorts, and

continuity for horizontal and vertical alignments

- for two levels that do NOT have a contact between them

- 1631 crossings

TTM poly/il

TTM1 ppoly/il

UUM m2/il

VVM m2/poly

3. CONTACT MEANDERS - tests step coverage, tests the integrity of the glass

between the two layers, detects shorts between the two layers,

and checks continuity for horizontal and vertical alignments

- for two levels that DO have a contact between them

- 1232 contacts

WWM ml/il

XXM ml /poly

XXM1 ml/ ppoly

YYM m2/ml

4. SUBSTRATE CONTACT MEANDER - tests continuity of metall into a substrate

contact (horizontal and vertical alignments are considered)

- 993 contacts

ZZM sub

71
Table 14 - Capacitors on Modules CCM and CCM1 Found in the Test Library

LAYER1 LAYER2 SUBCELL NAME MODULE

m2 ml capmlm2 (over il) CCM

poly capm2pol (over il) CCM

il capm2il CCM

sub capm2 CCM

ml poly capmlpol (over il) CCM

ppoly capmlppol (over il) CCM1

il capmlil CCM

sub (without il) capml CCM

poly il cappolil CCM

cappolnw CCM1

cappolpw CCM1

nwell/ nndiff capchann CCM1

pwell/ ppdiff capchanp CCM1

sub (without il) cappol CCM

ppoly il capppolil * * * CCM1

sub (without il) capppol CCM1

il sub capil CCM

capnw CCM1

cappw CCM1

capn CCM1

capp CCM1

The capacitance can be calculated using the equation:

C (in pF) = eox(A)/tox

where

eox = 8.85e-6 pF//xm

A = area in fim

2 tox in fim

72
Table 15 - Capacitors on Modules CCM2 through CCM9 Found in the Test Library

LAYER

1

LAYER2 DIMENSIONS MODULE

ml poly (1300x775 fim2

) 18 pF with tox=5000 A CCM3

ppoly (1300x775 /zm2

) 18 pF with tox=5000 A CCM5

il (1300x775 /zm2

) 22 pF with tox=4000 A CCM3

sub (1312x1530 /zm2

) 22 pF with tox=8000 A CCM2

poly/il/sub (1312x1530 /zm2

) CCM7

ppoly/il/sub (1312x1530 /zm2

) CCM8

poly il (625x775 /zm2

) 86 pF with tox=500 A CCM6.9

sub (1300x775 /zm2 ) 22 pF with tox=4000 A COM4

nndif

f

(625x775 /zm2

) tox=500 A CCM9

ppdif

f

(625x775 /zm2

) tox=500 A CCM9

ppoly il (625x775 /zm2

) 86 pF with tox=500 A CCM6.9

sub (1300x775 /zm2

) 22 pF with tox=4000 A CCM5

nndiff (625x775 /zm2

) tox=500 A CCM6

ppdif

f

(625x775 /zm2

) tox=500 A CCM6

il sub (1300x775 /zm2 ) 22 pF with tox=4000 A CCM4

The capacitance can be calculated using the equation:

C (in pF) = eox(A)/tox

where

eox = 8.85e-6 pF/izm

A = area in fim

2 tox in fim

The capacitor areas have been adjusted such that the capacitance is greater

than 10 pF.

73
Table 16 - List of Modules Containing Dynamic Circuits Found in the Test

Library with a Sample Subcell Name Given

DYNAMIC

CIRCUIT

MODULE

S M L SAMPLE SUBCELL NAME MOSFETS USED

RING OSCILLATORS

EES EEM EEL amp n- and p-channel

MOSFETs

IIS IIM ILL amptie MOSFETs with

source-to-channel ties

FFM ampcirc circular MOSFETs with

channel contacts

LLM ampcircnoc circular MOSFETs with

no channel contacts

GGS GGM GGL amphg H-gate MOSFETs

JJS JJM JJL amphgtie H-gate MOSFETs with

source-to-channel ties

HHS HHM HHL amptg T-gate MOSFETs

KKS KKM KKL amptgtie T-gate MOSFETs with

source-to-channel ties

STATIC RAMS

DDS DDM DDL

- MMM - sramcell

sramcellcirc

n- and ^-channel MOSFETs

circular MOSFETs

74
Table 17 - Organization of the Modules on NIST8

CI C2 C3 C4 C5 C6 C7 C8 C9 CIO Cll

AM BM CM DM KM EM UM FM VM XM AaM

NCHAN PCHAN NMIN CIRC CIRCNOC HG ITHG TG INV ALI NSQ.

Rl | L2 1 L2 1 L2 | L6 | L6 | L2 | L2 | L2 1 L3 | L3

W6 W6 1 W6 | W82 j W82 | W20 | W6 | W20 W3

N P N N N N N N N

R2 L3 L3 L3 L9 L9 L3 | L3 L3 L4

W6 W6 | W6 W79 | W79 | W20 | W6 | W20 W4

N P N N N N N N N

R3 L4 L4 1 L4 | L12 | L12 | L4 | L4 | L4 L4 | | L5

W6 W6 | W6 W107| W107| W20 | W6 | W20 W5

N P N N N N N N N

R4 L5 L5 L5 | L6 | L6 | L5 | L5 | L5 L6 L8

W6 W6 1 W6 | W82 | W82 | W20 | W6 | W20 W8

N P N P P N N N 1 1 N

R5 L6 L6 L6 | L9 | L9 L6 | L6 | L6 LIO

W6 W6 W6 W79 | W79 | W20 | W6 | W20 WIO

N P N P P N N N N

R6 L8 L8 L8 L12 | L12 | L8 L8 L8 LIO | L30

W6 W6 1 W6 | W107| W107| W20 | W6 | W20 W30

N P 1 N P P N N N N

R7 L6 L6 NODD L6 L6 | L50 | L6 LIO NUDD Lo L30

W3 W4 aaM W5 W8 W50 | WIO W6 aaaM W30 W6

N N N N N N N N N

R8 L3

W3 | P R9C3 PSQU R9C9

R9 SRAM L4 j RING23

DDM W4 | P EEM

L5 | RIO | L6 L6 PODD L6 L6 W5 | L6 LIO PODD L6 L30

W3 W4 bbbM W5 W8 P WIO W6 cccM W30 W6

pr pr rp pr p pr pr p L8 | Rll | W8 | 00M NXTORS

PBbM | R12 | R12C3 LIO | L20 L20 L20

RINGHG W10 | W120 W1760 W120

GGM P

R13 | L30 | L20 L20 L20

W30 j W80 W1320 W80

P 1

75
Table 18 - Method Used To Get Submicrometer Dimensions on NIST8

1. Check CIF file for everything except submicromet er dimensions

$ cd nist8100 nist8.mag lx

$ magic nist8 nist8.cif lx

ciflx (MOSIS)

: quit

$ magic -Tsimox blank

cif istyle lx (MOSIS)

:cif read nist8

CHECK CIF

: quit

2. Make submicromet er file

$ cd nist8100

$ magic nist8

ciflx (MOSIS)

: quit

$ magic -Tsimox blank

:cif istyle mosis (SCE) inlOx

: cif read nist8

f ,z :load nist8

edit to proper dimensions (the whole hierarchy)

: edit

: save alignviamlOO

: edit

: save xmlOO

: edit

: save nist8100 (of selected files) nist8100.mag lOx

:cif ostyle out-lOx

: cif write nist8100 (send this) nist8100.cif lx

: quit

3. Check the CIF file to be sent

$ magic -Tsimox blank

cif istyle lx (MOSIS)

:cif read nist8100

CHECK CIF (especially submicrometer dimensions)

: quit

4. Check for submicrometer dimensions

$ vi nist8100.cif

/alignviaml

76
Table 19 - Organization of the Large 10 by 7 Modules on NIST9

PRELIMINARY CALCULATIONS:

1 processing x2= 2 + 2 inside

1 B module x2= 2

8 capacitors x2=16

10 medium rings/srams x2=20

7 large rings/srams x2=14

2 van der Pauw x2= 4

2 0 modules x2= 4

10 meanders x2=20

1 threading x2= 2

1 suspended x4= 4+2 inside

2 diodes x2= 4

Total modules 92+4 inside

Possible slots 92

NUM MODULES ABBREVIATED PLACEMENTS (e.g., A=AAM, K=KKM)

SIZE ABBREVIATED DESCRIPTION (e.g., pr=processing)

14 - - C6AEFGHI JKLDMBA

MISC c pr rings (M) sr-m pr

M

14 - C5 IR DL E G H I J K D 0M 0L N Nl

MISC c ir dl rings (L) sr vp....

L

16

MISC B C7 DI DI1 P Q Ql R T II H X XI Z C7 C5

M c diodes . .meanders caps..

16 0M C2 C4 C9 E F G H I J K L D M C3 C8

M caps rings(M) sr-m caps..

16 0L N C3 C8 IR E G H I J K D IR C6 C2 C9

L vp caps... .ir rings (L) sr ir caps

16 DL Nl DI DI1 P Q Ql R T 11 W X XI Z C4 IR

MISC dl vp diodes . .meanders c ir

77
Table 20 - Organization of All the Modules Except the Large 10 by 7 Modules

on NIST9

PRELIMINARY CALCULATIONS

22 MOSFETs (M + L) 106 modules

6 contact resistors (M) x 3 iterations

6 cross bridges (M + L)

4 inverters (M + L) 318 modules

3 e-beam structures (M) 382 possible spaces

2 unusually-sized (M)

10 bipolar (M) 64 extra spaces

-46 KEYS only

53 total modules

53 KEYS modules interleaved 18 extra spaces for MOSFETs/KEYS

so 9 extra MOSFET modules

106 modules

Therefore the abbreviated sequencing (e.g., A=AM, U=UM) is:

A-K,U, V,W, Aa,Bb, Dd,Gg,Ii-Pp, L-T, Ee,Ff,Hh

MOSFETs inv square bipolar cr,cb x-ray

NOTES:

1. KEYS modules alternate with the 2 by 16 modules (top to bottom)

(There are 3+ repetitions of the 2 by 16 modules)

4K4K4K4K

3K3K3K3K3K3K4K4K4K

3K3K3K3K3K3K3K3K3K3K3K3K3K3K

3K3K3K3K3K3K3K3K3K3K3K3K3K3K3K3K3K3K3K

3K3K3K3K3K3K3K3K3K3K3K3K3K3K2K2K2K2K2K2K2K2K2K2K

2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K2K

proc.K2K2K2K2K2K2K2K2K2K2K2K2K2K2KlKlKlKlKlKlKlKlKlKlKlKlKlKlKproc.K

1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K1K

4K4K-K-K-K-K-K-K-K-K-K-K-K-K-K-K

K-K-K-K-K-K-K-K-K-K-K-K-K-K-K-K

K-K-K-K-K-K-K-K-K-K-K-K-K-K-K-K

2. AAM1 appears below each AAM processing module

3. Horizontal modules (top to bottom)

2 KEYS (bbM)

4 KEYS

5 KEYS

7 KEYS

8 KEYS

10 KEYS

12 KEYS

13 KEYS

12 cccM, 2 AAM1

15 KEYS

16 aaaM

16 KEYS

16 bbbM

16 aaM

4. Border problem files = 0M, XM, YM, ZM, EeM, FfM, HhM

CCM3, CCM4, CCM5, CCM6, CCM9, WWM, XXM, XXM1 , YYM, ZZM

78
APPENDIX A - Sideviews of the 14 SIMOX Processing Mask Steps

Used to Fabricate NIST9

STED 1 - ISLAND (a clear field mask)

1500A ISLAND ISLAND ISLAND

4000A SiO.

p-Si

(10-30Qcm)

STEP 2 - A/WELL (a dark field mask)

in

ISLAND ISLAND

SiO,

Si

79
STEP 3 - PWELL (a dark field mask)

P~ P~ III V V t

SiO.

Si

STEP 4 - A/TIE IMPLANT (a dark field mask)

n

Si

80
81
STEP 8 - PPOLY IMPLANT

Si02

Si

82
STEP 9 - POLYSILICON (a clear field mask)

SiQ2

Si

STEP 10 - A/IMPLANT (a dark field mask)

SiQ2

83
PPOLY WFET DFET

SiQ2

Si

STEP 12 - PIMPLANT (a dark field mask)

84
85
APPENDIX B - Abbreviated SOI/SIMOX Technology File

/* —

* simox.tech — The SIMOX Technology File for I ambda=l .0

*

types /* ti les */

/* primary layers */

glass glass

glass open

meta 1 3 meta 1 2c , meta 1 3 , m2c , v i a , m2contact

metal 2 meta 1 2,m2, purple

meta 1 1 meta 1 1

, ml , b I ue active polysi I icon, red, poly, p,npoly

active ppoly

glass etch, netch

glass petch

active ndiffusion, green, ndiff

active pdiff usion,brown,pdiff

active nndiff

active ppdiff

meta 12 ntie,nbody_tie,n_xtor_bodytie,tie

meta 12 ptie,pbody_tie,p_xtor_bodytie

we I I nwel I , nw we I I pwe I I , pw

meta 1 2 d imp I ant

island island, i

I ,yel low

island pad

island ppad

island substrate, subst

active legend we I I I egb , I egend background

/* Contacts */

active po I ycontact , pcontact , pc

active ppo I ycontact, ppc

act i ve ndpcontact , ndpc

active pdpcontact, pdpc

active ndcontact, ndc

active pdcontact, pdc

active nwcontact, nwc active pwcontact,pwc

glass hole, contact

meta II i I contact, i Ic meta I 1 subcon

/* Transistors */

active ntransistor, nfet

86
active ptransi stor, pf et

active dtransistor ; dfet

end

fdefine allMetal2 m2,m2c

#def i ne all SomeMl ml , pc/ml , ppc , ndpc/ml , pdpc/ml , ndc/ml , pdc/ml

fdefine allMetall a I ISomeMl,nwc/ml,pwc/ml, i lc/ml,subcon/ml

fdefine allPolyl po I y , pc/act i ve, ppc, nf et,df et, ndpc/acti ve fdefine allPoly a I IPolyl,ppoly,pfet,pdpc/acti ve fdefine allNpoly poly, pc/act i ve, nfet,dfet, ndpc/acti ve fdefine allPpoly ppoly ,ppc,pfet,pdpc/acti ve fdef ine al INdiff ndiff ,ndc/acti ve,nndiff , nwc/acti ve, nfet,dfet, ndpc/acti ve #def ine a I IPdiff pdiff ,pdc/acti ve,ppdiff ,pwc/active,pfet,pdpc/acti ve fdef ine al ISomeD ndiff , pdiff ,ndc/active,pdc/active,ndpc/active,pdpc/active

fdefine al IDiff al ISomeD, nndiff ,ppdiff ,nwc/active,pwc/acti ve,nfet,pfet

fdefine allDiffO nndiff ,ppdiff ,nwc/active,pwc/acti ve fdef i ne all Nwe I I nw, nwc/act i ve fdefine allPwell pw, pwc/acti ve #def i ne a I I Is I and i

I , i I c/i

I

fdefine a I I Sub subst , subcon/subst

c i f output

style photronix

sea I ef actor 100

layer SWN a I INwel

I

cat ma 2 1 layer SWP a I IPwel

I

calma 3 1 layer SIL a I I Is I and , pad, ppad

calma 1 1 layer SMF pad, ppad

shrink 400

or a I IMeta 1

1

grow 200

shrink 200

calma 14 1

layer SPG pad, ppad

shrink 200

or a I I Npo I y , a I I Ppo I y , etch , petch

grow 100

shrink 100

calma 7 1 layer SNP pad

shrink 200

or a I I Npo I y, etch

grow 100

shrink 100

ca I ma 8 1

87
layer SPP ppad

shrink 200

or a I IPpoly,petch

grow 100

shrink 100

ca I ma 9 1 layer SND a I INdiff

calma 10 1

layer SPD al IPdiff

calma 12 1 layer SNT ntie

calma 4 1

layer SPT ptie

calma 5 1

layer SDF dfet

grow 200

or dimplant

calma 6 1

layer SCT subcon, pad, ppad

shrink 800

or ndc , pdc , nwc , pwc , pc , ppc , i I c , ndpc , pdpc

shrink 200

or open, hole

calma 13 1

layer SCS subcon, substrate, open

calma 11 1

/* layer SOG pad, ppad

shrink 600

or glass, open

calma 15 1

*/

style mosis(SCE)outlx

sea I efactor 100

layer CWN al INwe I I ca I ma 1 1

layer CWP a I IPwel

I

ca I ma 2 1 layer CMS pad

shrink 400

or a I I Meta 1

2

ca I ma 3 1

layer CMF pad

shrink 200

or a I I Meta 1 1 , m2c

ca I ma 4 1

layer CPG al IPoly,pad

calma 5 1 layer CM a I INdiff ,a I IPdiff

and a I I Island

88
ca I ma 6 1 layer CVA m2c

shrink 100

calma 7 1

layer CVA pad

shrink 500

ca I ma 7 1

layer CSN ndiff,nfet

grow 200

or al INdiff

calma 8 1 layer CSP pdiff,pfet

grow 200

or al IPdiff

calma 9 1 layer CCA ndc,pdc,pwc,nwc

shrink 200

calma 10 1 layer CCP pc , ndpc , pdpc

shrink 200

calma 11 1

layer CCP pad

shrink 300

calma 11 1

layer COG pad

shrink 600

or glass

calma 12 1

c if input

style photronix

sea I ef actor 100

layer nw SWN

layer pw SWP

layer ml SMF

layer poly SNP

layer ppoly SPP

layer ndiff SND

layer pdiff SPD

layer nndiff SND

and SWN

layer ppdiff SPD

and SWP

layer ndiff SND

and-not SWN

layer pdiff SPD

and-not SWP

layer ntie SNT

89
layer ptie SPT

layer nfet SPG

and SND

and-not SWN

layer pfet SPP

and SPD

and-not SWP

layer dfet SPG

and SND

and SDF

layer d imp I ant SDF

and-not SPG

layer etch SPG

and SND

and SWN

layer petch SPG

and SPD

and SWP

layer hole SCT

and-not SMF

layer i lc SCT

and SIL

and SMF

layer ndc SCT

and SND

and SMF

and SIL

layer pdc SCT

and SPD

and SMF

and SIL

layer nwc SCT

and SND

and SWN

and SMF

and SIL

layer pwc SCT

and SPD

and SWP

and SMF

and SIL

layer pc SCT

and SPG

and SMF

and-not SND

and-not SPD

ayer ppc SCT

and SPP

and SMF
and-not SND

and-not SPD

layer ndpc SCT

and SPG

and SMF

and SND

layer pdpc SCT

and SPP

and SMF

and SPD

layer i I SIL

layer substrate SCS

and-not SCT

layer subcon SCT

and SCS

and SMF

layer ppoly SPP

and-not SWP

layer glass SOC

layer open SCT

and SCS

and-not SMF

and-not SPD

and SOG

ca Ima SWN 2 * ca Ima SWP 3 * ca Ima SIL 1 * ca Ima SMF 14 * ca Ima SPG 7 * ca Ima SNP 8 * ca Ima SPP 9 * ca Ima SND 10 * ca Ima SPD 12 * ca Ima SNT 4 * ca Ima SPT 5 * ca Ima SDF 6 * ca Ima SCT 13 * ca Ima SCS 11 * calma SOG 15 *

le mosis(SCE) inlx sea I efactor 100

layer nw CWN

layer pw CWP

layer m2c CVA

layer m2 CMS
layer ml CMF

layer poly CPG

layer i I CAA

layer nndiff CSN

and CWN

layer ppdiff CSP

and CWP

layer ndiff CSN

and-not CWN

layer pdiff CSP

and-not CWP

layer nfet CPG

and CAA

and CSN

layer pfet CPG

and CAA

and CSP

layer pdc CCA

and CAA

and CSP

and CMF

layer ndc CCA

and CAA

and CSN

and CMF

layer pwc CCA

and CAA

and CSP

and CMF

and CWP

layer nwc CCA

and CAA

and CSN

and CMF

and CWN

layer pc CCP

and CPG

and CMF

and-not CSN

and-not CSP

layer ndpc CCP

and CPG

and CMF

and CSN

layer pdpc CCP

and CPG

and CMF

and CSP

layer glass COG
APPENDIX C - Test Algorithm KEYSiv

APPENDIX C — Test algorithm KEYSiv (the program used to obtain the IV

data points on NIST8)

50 SUB Keysiv_mos (W$ , R$ , C$ , INTEGER Pins (*), REAL Width, Length , Type$ , Vgs (*), Vds

(

60 Keysiv mos: ! ************************************************

70

RE-STORE "/users/marshall/icms/ALG/BASIC/Keysiv_MOS"

LOADSUB ALL FROM " /usr/pcs/ lib/XYGRAPH" ***************************************************************************

Programmers Janet Marshall

160 ! Date 04/20/1992 12:35 : 45

170 ! Revised 04/20/1992 12:35 :45

180 ! Device Class MOSFET

190 ! Description Mosfet drain current measurement at specified

200 ! Vds, Vgs, Vbs and Vss.

210 1 Procedure

220 I 230 ! Input Variables:

240 ! 250 ! 260 ! 270 !

# Name Type Size Description

Measurement Parameters

280 ! 1 W S Wafer Letter

290 ! 2 R s Row Number

300 1 3 C s Column Number

310 ! 320 ! Device Terminals:

330 ! 1 Gate I Gate terminal

340 ! 2 Drain I Drain terminal

350 ! 3 Source I Source terminal

360 ! 4 Bulk I Bulk terminal

370 ! 5 Sub I Substrate contact

380 ! 6 Chuck I Wafer chuck

390 ! 400 ! Device Parameters:

410 ! 1 Width R um, Mask channel width

420 ! 2 Length R urn, Mask channel length

430 ! 3 Type C Channel type (P/N)

440 ! 450 ! Output Variables:

460 ! 470 ! 480 ! 490 !

# Name Type Size Description

Output Parameters:

500 ! 1 Vgs A 13 Gate Voltage

510 ! 2 Vds A 13 Drain Voltage

520 ! 3 Idsl A 13 Drain Current (1)

530 ! 4 Ids2 A 13 Drain Current (2)

540 ! 5 Ids3 A 13 Drain Current (3)

550 ! 6 Vbs R Substrate Voltage ***************************************************************************

! INPUT "Number of points in a sweep = ",M

93
610 M=13

620 OPTION BASE 1 630 ! 64 0 INTEGER Gate , Drain , Source , Substrate , Line ,I,K,M,N,P,Q,T, Current

650 INTEGER Numberl , Number2

660 REAL Vsource

670 ! 680 ALLOCATE Ids (M) , Id (13, M)

690 DIM Vdsl(3) ,Vds2 (10) ,Idl(3) ,Id2 (10)

700 DIM Vgate_min(3) , Vgate_max ( 3 ), Vgate_step (3

)

710 DIM Start (3) , Stop (3)

720 DIM File$[40] ,Dir$[40] ,Concat$[40]

730 DIM String_l$[40] , String_2$ [ 40 ]

, String_3$ [40]

740 DIM String_4$[40] , String_5$ [ 40 ], String_6$ [ 40

]

750 DIM Y$[2] ,Z$[1]

760 ! 770 ! =============================================================

780 ! 790 ! Determine the filename

800 ! 810 ! PRINT "C$ = " ,C$

820 "PRINT "Y$ = ",Y$

830 1PRINT "Z$ = ",Z$

840 ! 850 R$="0"

860 IF Length=2.0 THEN R$="l"

870 IF Length=3.0 AND (Width=6.0 OR Width=20.0) THEN R$="2"

880 IF Length=4.0 AND (Width=6.0 OR Width=20.0) THEN R$="3"

890 IF Length=5.0 AND (Width=6.0 OR Width=20.0) THEN R$="4"

900 IF Length=6.0 AND (Width=6.0 OR Width=20.0) THEN R$="5"

910 IF Length=8.0 AND (Width=6.0 OR Width=20.0) THEN R$="6"

920 ! 930 IF Width=82. AND Type$="N" THEN R$="l"

940 IF Width=82. AND Type$="P" THEN R$="4"

950 IF Width=79. AND Type$="N" THEN R$="2"

960 IF Width=79. AND Type$="P" THEN R$="5"

970 IF Width=107. AND Type$="N" THEN R$="3"

980 IF Width=107. AND Type$="P" THEN R$="6"

990 ! 1000 IF Type$="P" THEN GOTO 1270

1010 ! 1020 ! N-channel devices

1030 ! 1040 IF Length=Width AND Length=3 . THEN R$="l"

1050 IF Length=Width AND Length=4 . THEN R$="2 11 1060 IF Length=Width AND Length=5. THEN R$="3"

1070 IF Length=Width AND Length=8 . THEN R$="4"

1080 IF Length=Width AND Length=10. THEN R$="5 M 1090 IF Length=Width AND Length=30. THEN R$="6"

1100 IF Length=Width AND Length=50. THEN R$="7"

1110 IF Length=Width AND Length=50. THEN C$="6"

1120 ! 1130 IF R$="0" THEN R$="7"

1140 ! 1150 IF R$="7" AND Width=3 . THEN C$="l"

1160 IF R$="7" AND Width=4 . THEN C$="2"

1170 IF R$="7" AND Width=5 . THEN C$="4"

1180 IF R$="7" AND Width=8 . THEN C$="5"

1190 IF R$="7" AND Width=10. THEN C$="7"

1200 IF R$="7" AND Length=10. THEN C$="8"

94
1210 IF R$="7" AND Width=30. THEN C$="10"

12 2 0 IF R$="7" AND Length=3 0. THEN C$="ll"

1230 GOTO 1490

1240 ! 1250 ! P-channel devices

1260 ! 1270 IF Length=Width AND Length=3 . THEN R$="8"

1280 IF Length=Width AND Length=4 . THEN R$="9"

1290 IF Length=Width AND Length=5. THEN R$="10"

1300 IF Length=Width AND Length=8 . THEN R$="ll"

1310 IF Length=Width AND Length=10. THEN R$="12"

13 2 0 IF Length=Width AND Length=3 0. THEN R$="13"

1330 IF R$="10" THEN GOTO 1610

1340 ! 1350 IF R$="0" THEN R$="10"

1360 ! 1370 IF R$="10" AND Width=3 . THEN C$="l"

1380 IF R$="10" AND Width=4 . THEN C$="2"

1390 IF R$="10" AND Width=5. THEN C$="4"

14 00 IF R$='M 10 M- AND Width=8 . THEN C$="5"

1410 IF R$="10" AND Width=10. THEN C$="7"

1420 IF R$="10" AND Length=10. THEN C$="8"

1430 IF R$="10" AND Width=30. THEN C$="10"

1440 IF R$="10" AND Length=30. THEN C$="ll"

1450 GOTO 1610

1460 ! 1470 ! Chip OOM

1480 ! 1490 IF C$<>"0" THEN GOTO 1610

1500 IF Width=120 OR Width=1760 THEN R$="12"

1510 IF Width=80 OR Width=1320 THEN R$="13"

1520 IF Width>1000 THEN C$="9"

1530 ! 1540 IF Pins(2)=18 OR Pins(l)=8 THEN C$="7"

1550 IF Pins(2)=46 OR Pins(2)=48 THEN C$="ll"

1560 1PRINT "Pins(2)=";Pins(2)

1570 1PRINT "Pins(l)=";Pins(l)

1580 ! 159 0 ! ======================================================================== 1600 ! 1610 Dir$="/users/marshall/nist8data/"

1620 1 1630 File$=Type$&"W" &W$&"R"&R$&"C"&C$&" . DAT"

1640 ! 1650 Concat$=Dir$&File$

1660 ! 1670 ! PRINT Concat$

1680 ! 1690 ! 1700 ! 1710 ! Specify default mass storage

1720 ! 1730 !MASS STORAGE IS ":, 600,1"

1740 ! 1750 ! Create ASCII data file with 10 sectors on the specified

1760 ! mass storage device (:, 600,1)

1770 ! 1780 ON ERROR GOTO File_exists

1790 CREATE ASCII Concat$,10

1800 File exists: OFF ERROR

95
1810 ! 1820 ! Assign (or open) an I/O path name to the file

1830 ! 1840 ASSIGN @Path_l TO Concat$

1850 ! 1860 I 1870 ! 18 8 0 Init_system

1890 ! 1900 ! Define measurement pins

1910 ! 1920 Gate=Pins(l)

1930 Drain=Pins (2)

1940 Source=Pins (3)

1950 Substrate=Pins (4)

1960 ! 1970 ! Connect pins to sources

1980 ! 1990 Connect (FNSmu ( 1) , Drain)

2 000 Connect ( FNSmu ( 2 )

, Gate

)

2010 Connect (FNGnd, Source)

2020 Connect (FNSmu (3) , Substrate)

2030 ! 2040 ! Force bias conditions

2050 ! 2060 IF Type$="N" THEN S=1.0

2070 IF Type$="P" THEN S=-1.0

2080 ! 2090 Vsub=0*S

2100 Set_smu(2) ! SET INTEGRATION TIME TO MEDIUM

2110 Force_v ( Substrate ,Vsub)

2120 ! 2130 ! Define variables

2140 ! 2150 N=0

2160 P=l

2170 Vgate_min(l) =. 1*S

218 0 Vgate_min(2)=.5*S

2190 Vgate_max(l)=. 35*S

22 00 Vgate_max(2)=5.0*S

2210 Vgate_step(l)=. 1*S

2220 Vgate_step(2)=.5*S

22 3 0 lds_max=0.

2240 ! 2250 Line=l

2260 Range=10.0*S

2270 Start(l)=.l*S

2280 Start(2)=.5*S

2290 Stop(l)=.3*S

2300 Stop(2)=5.0*S

2 310 Number 1=3

2320 Number2=10

2330 ! 2340 Hold=1.0

2350 Dstep=.01

2360 Compl=.01*S

2370 ! 2 380 Current=2

2390 Irange=l.E-2*S

2400 !

96
2410 ! 2420 ! Sweep Vds given Vgs THEN next Vgs

2430 ! 2 44 0 FOR Vgate=Vgate_min(P) TO Vgate_max(P) STEP Vgate_step (P)

2 4 50 Force_v(Gate, Vgate)

2460 ! 2470 Q=l

2480 Set_iv (Drain, Line, Range, Start (Q) ,Stop(Q) , Number 1 , Hold, Dstep , Compl)

2490 Sweep_iv (Drain, Current, Irange, Idl (*) , Vdsl (*)

)

2500 Q=2

2510 Set_iv(Drain, Line, Range, Start(Q) ,Stop(Q) , Number2 , Hold, Dstep, Compl)

2520 Sweep_iv (Drain, Current, Irange, Id2 (*) ,Vds2 (*)

)

2530 ! 254 0 N=N+1

2550 T=0

2560 FOR T=l TO 3 2570 Vds (T) =Vdsl (T)

2580 Ids(T)=Idl(T)

2590 Id (N , T) =Ids (T)

2600 IF ABS ( Ids (T) ) >ABS ( Ids_max) THEN Ids_max=Ids (T)

2610 NEXT T

2 62 0 FOR T=4 TO 13

2630 Vds(T)=Vds2 (T-3)

2640 Ids(T)=Id2 (T-3)

2650 Id(N,T)=Ids(T)

2660 IF ABS ( Ids (T) ) >ABS ( Ids_max) THEN Ids_max=Ids (T)

2 67 0 NEXT T

2680 ! 2690 ! PRINT "N=" ; N

; "Vgate=" ; Vgate

2700 1PRINT "Vds=";Vdsl(*) ;Vds2 (*)

2710 I PRINT M Ids=";Ids(*)

2720 Vgs(N)=Vgate

2730 NEXT Vgate

2740 ! 2750 IF P=2 THEN GOTO 2790

2760 P=2

2770 GOTO 2440

2780 ! 2 7 90 ! Draw axes

2800 ! 2810 Disable_port

2820 IF lds_max=0. THEN Ids_max=100.

283 0 CLEAR SCREEN

2840 IF S=-l THEN GOTO 2870

2850 Lingraphl(0,6*S / 0,Ids_max,"Vds","Ids","N-channel IV at Vbs=0V" , 1 , 1

, "Vgs"

)

2860 GOTO 2890

2870 Lingraphl(0,6*S,0,Ids_max,"Vds","Ids","P-channel IV at Vbs=0V" , 1, 1, "Vgs")

2880 ! 2890 ! Plot an Id vs. Vd curve for a given Vg value

2900 ! 2910 K=l

292 0 FOR K=l TO 13

2930 1=1

2940 FOR 1=1 TO 13

2950 ! PRINT "I=" ; I

; "K=" ;K 2960 Ids(I)=Id(K,I)

2970 NEXT I 2980 ! 2990 MOVE 0,0

3000 1=1

97
3010 FOR 1=1 TO 13

3020 PLOT Vds ( I )

, Ids ( I

)

3030 NEXT I

3 04 0 NEXT K

3050 ! 3 060 PRINT " " 3070 PRINT "Width=", Width

3080 PRINT "Length=" / Length

3090 PRINT "Type=" ,Type$

3100 PRINT " " 3110 PRINT Concat$

3120 PRINT " " 313 0 PRINT " " 314 0 PRINT 11 " 3150 PRINT " " 3160 PRINT " " 3170 PRINT " " 3180 PRINT " 11 3190 PRINT 11 " 3200 1PRINT "Vds=" ;Vds(*)

3 210 ! PRINT "Vgs=" ;Vgs(*)

3220 ! 3230 I *************************************************

3240 ! 3250 ! Data for KEYS in the following:

3260 ! 3270 ! Vds(13)

3280 ! Vgs(13)

3290 ! Id(13,13)=Id(Vg,Vd) Vg and Vd not defined

3300 ! Vsub

3310 ! 3320 Disable_port

3330 ! 3340 ! Write the data to the file

3350 ! 3360 OUTPUT String_l$ ; "Vds Vgs Vbs Ids"

3370 OUTPUT String_6$ USING "/ , / , 21A, /

" ; String_l$

3380 OUTPUT @Path_l ; String_6$

3390 1=1

3400 FOR 1=1 TO 13

3410 K=l

3420 FOR K=l TO 13

3430 OUTPUT String_2$ USING "SD. DDDE, /

" ; Vds (K)

3440 OUTPUT @Path_l ; String_2$

3450 ! 3460 OUTPUT String_3$ USING "SD.DDDE,/";Vgs(I)

3470 OUTPUT @Path_l ; Str ing_3

$

3480 ! 3 490 OUTPUT String_4$ USING "SD. DDDE, /"; Vsub

3500 OUTPUT @Path_l;String_4$

3510 ! 3520 OUTPUT String_5$ USING "SD . DDDE , /

" ; Id ( I , K)

3530 OUTPUT @Path_l ; String_5$

3 54 0 NEXT K

3550 NEXT I 3560 ! 3570 ! Close the I/O path

3580 ! 3 59 0 ASSIGN @Path_l TO * 3600 !

98
3 610 !**********************************^

3620 I 3630 GOSUB Debuginfo

3640!

3650 SUBEXIT

3660!

3670 Debuginfo: ! display input values

3680 PRINTER IS CRT

3690 ! PRINT "algorithm <Keysiv_MOS>"

3700 1PRINT " W = ",W$

3710 ! PRINT " R = " ,R$

3720 ! PRINT " C = ",C$

373 0 RETURN

3 74 0 SUBEND

3750 !

99
APPENDIX D - Test Algorithm KEYSvt

APPENDIX D — Test algorithm KEYSvt (the program used to obtain the Ids versus Vgs curves on NIST8)

SUB Keysvt_mos (W$ , R$ , C$ , INTEGER Pins (*), REAL Width, Length, Type$ ,Vbs (*) ,Vt (

Keysvt mos : ! **********************************************************

 "**  *********************************************************************

RE-STORE "/users/marshall/icms/ALG/BASIC/Keysvt_MOS"

LOADSUB ALL FROM " /usr/pcs/ lib/XYGRAPH"

130 i **********************************************************************

140

!

150 Programmers : Janet Marshall

160!

170! Date : 04/17/1992 12:10: 55

180

!

Revised : 04/17/1992 12:10: 55

190! Device Class : MOSFET

200! Description : Mosfet drain current measurement at specified

210 ! : Vds,Vgs,Vbs and Vss

.

220 ! Procedure : 230

240 ! Input Variables:

250

260

270

280

! # Name Type Size Description

! Measurement Parameters

290 ! 1 W S Wafer Letter

300 ! 2 R S Row Number

310 ! 3 C S Column Number

320

330 ! Device Terminals:

340 ! 1 Gate I Gate terminal

350 ! 2 Drain I Drain terminal

360 ! 3 Source I Source terminal

370 ! 4 Bulk I Bulk terminal

380 ! 5 Sub I Substrate contact

390 ! 6 Chuck I Wafer chuck

400

410 ! Device Parameters:

420 ! 1 Width R um, Mask channel width

430 ! 2 Length R um, Mask channel length

440 ! 3 Type C Channel type (P/N)

450

460 ! Output Variables:

470

480

490

500

! # Name Type Size Description

! Output Parameters:

510 ! 1 Vbs A 4 Backgate bias

520 ! 2 Vt A 4 Threshold voltage ***************************************************************************

! INPUT

Q=50

OPTION

i

"Number of points in a sweep = ",Q

BASE 1

100
610 INTEGER Gate , Drain , Source , Sub

620 INTEGER Line , I , J , K , M, N , P , Q , T, Current

63 0 INTEGER Number, M_max

640 REAL Vsub

650 ! 660 ALLOCATE Ids (Q) , Vgs (Q) , Id ( 5 , Q) , Yn ( 5 , Q)

670 DIM Yint (50) , Ycalc(50) ,X(50) , Y(50)

680 DIM File$[40] ,Dir$[40] ,Concat$[40]

690 DIM String_l$[40] , String_2$ [40] , String_3$ [40] , String_4$ [ 40]

700 ! 710 ! =========================================================

720 ! 73 0 ! Determine the filename

740 I 750 R$="0"

760 IF Length=2.0 THEN R$="l"

7 70 IF Length=3.0 AND (Width=6.0 OR Width=20.0) THEN R$="2"

780 IF Length=4.0 AND (Width=6.0 OR Width=20.0) THEN R$="3"

790 IF Length=5.0 AND (Width=6.0 OR Width=20.0) THEN R$="4"

800 IF Length=6.0 AND (Width=6.0 OR Width=20.0) THEN R$="5"

810 IF Length=8.0 AND (Width=6.0 OR Width=20.0) THEN R$="6"

820 ! 830 IF Width=82. AND Type$="N" THEN R$="l"

840 IF Width=82. AND Type$="P" THEN R$="4"

850 IF Width=79. AND Type$="N" THEN R$="2"

860 IF Width=79. AND Type$="P" THEN R$="5"

870 IF Width=107. AND Type$="N" THEN R$="3"

880 IF Width=107. AND Type$="P" THEN R$="6"

890 ! 900 IF Type$="P" THEN GOTO 1170

910 ! 920 I N-channel devices

930 ! 940 IF Length=Width AND Length=3 . THEN R$="l"

950 IF Length=Width AND Length=4 . THEN R$="2"

960 IF Length=Width AND Length=5. THEN R$="3"

970 IF Length=Width AND Length=8. THEN R$="4"

980 IF Length=Width AND Length=10. THEN R$="5"

990 IF Length=Width AND Length=30. THEN R$="6"

1000 IF Length=Width AND Length=50. THEN R$="7"

1010 IF Length=Width AND Length=50. THEN C$="6"

1020 1 1030 IF R$="0" THEN R$="7 M 1040 • 1050 IF R$="7" AND Width=3 . THEN C$="l"

1060 IF R$="7" AND Width=4 . THEN C$="2"

1070 IF R$="7" AND Width=5 . THEN C$="4"

1080 IF R$="7" AND Width=8 . THEN C$="5"

1090 IF R$="7" AND Width=10. THEN C$="7"

1100 IF R$="7" AND Length=10. THEN C$="8"

1110 IF R$="7" AND Width=30. THEN C$="10"

1120 IF R$="7" AND Length=30. THEN C$="ll"

1130 GOTO 1390

1140 I 1150 ! P-channel devices

1160 ! 1170 IF Length=Width AND Length=3 . THEN R$="8"

1180 IF Length=Width AND Length=4 . THEN R$="9"

1190 IF Length=Width AND Length=5. THEN R$="10"

12 00 IF Length=Width AND Length=8 . THEN R$="ll"

101
1210

1220

1230

1240

1250

1260

1270

1280

1290

1300

1310

1320

1330

1340

1350

1360

1370

1380

1390

1400

1410

1420

1430

1440

1450

1460

1470

1480

1490

1500

1510

1520

1530

1540

1550

1560

1570

1580

1590

1600

1610

1620

1630

1640

1650

1660

1670

1680

1690

1700

1710

1720

1730

1740

1750

1760

1770

1780

1790

1800

IF Length=Width AND Length=10. THEN R$="12"

IF Length=Width AND Length=3 0. THEN R$="13"

IF R$="10" THEN GOTO 1490

IF R$="0" THEN R$="10"

IF R$=

IF R$=

IF R$=

IF R$=

IF R$=

IF R$=

IF R$=

IF R$=

:"10"

= "10"

= "10"

= "10"

= "10"

= "10"

= "10"

= "10"

GOTO 1490

AND Width=3.

AND Width=4.

AND Width=5.

AND Width=8.

AND Width=10

AND Length=10

THEN C$="l"

THEN C$="2"

THEN C$="4"

THEN C$="5"

THEN C$="7"

THEN C$="8"

AND Width=3 0. THEN C$="10"

AND Length=3 0. THEN C$="ll"

Chip OOM

IF C$<>"0" THEN GOTO 1490

IF Width=120 OR Width=1760 THEN R$="12"

IF Width=80 OR Width=1320 THEN R$="13"

IF Width>1000 THEN C$="9"

i IF Pins(2)=18 OR Pins(l)=8 THEN C$="7"

IF Pins(2)=46 OR Pins(2)=48 THEN C$="ll"

ir$="/users/marshall/nist8data/"

ile$="W"&W$&"R"&R$&"C"&C$&"VB.DAT"

Concat$=Dir$&File$

PRINT Concat$

Specify default mass storage

MASS STORAGE IS ": ,600,1"

Create ASCII data file with 10 sectors on the specified mass storage device (:, 600,1)

ON ERROR GOTO File_exists

CREATE ASCII Concat$,10

File_exists: OFF ERROR

i

! Assign (or open) an I/O path name to the file

i ASSIGN @Path 1 TO Concat$

Init_system

i

! Define measurement pins

i Gate=Pins (1)

102
1810 Drain=Pins (2)

1820 Source=Pins (3)

1830 Sub=Pins(4)

1840 ! 1850 I Connect pins to sources

1860 ! 1870 Connect (FNSmu(l) , Drain)

1880 Connect (FNSmu (2) , Gate)

1890 Connect (FNGnd, Source)

1900 Connect (FNSmu (3) , Sub)

1910 ! 1920 ! Force bias conditions

1930 ! 1940 IF Type$="N" THEN S=l . 0 1950 IF Type$="P" THEN S=-1.0

1960 ! 1970 Vds=.2*S

198 0 Set_smu(2) ! SET INTEGRATION TIME TO MEDIUM

1990 Force_v (Drain, Vds)

2000 ! 2010 ! Define variables

2020 ! 2030 P=0

2 04 0 Vbs_min=0.*S

2050 Vbs_max=-9 . 0*S

2060 Vbs_step=-3 . 0*S

2070 lds_max=0.

2080 ! 2090 Line=l

2100 Vrange=10.0*S

2110 Start=.l*S

2120 Stop=5.0*S

213 0 Number=50

2140 ! 2150 Hold=1.0

2160 Dstep=.01

2170 Icompl=.01*S

2180 ! 2190 Current=2

2200 Irange=.01*S

2210 ! 22 2 0 PRINT " " 22 3 0 PRINT " " 2240 ! 2 2 50 ! Sweep Vgs given Vbs THEN next Vbs

2260 ! 2270 FOR Vsub=Vbs_min TO Vbsjmax STEP Vbs_step

2 2 80 Force_v(Sub, Vsub)

2290 ! 2 3 00 Set_iv (Gate, Line, Vrange, Start, Stop, Number , Hold, Dstep, Icompl)

2310 Sweep_iv (Drain, Current, Irange, Ids (*) , Vgs (*)

2320 ! 23 3 0 P=P+1

2340 ! PRINT "P=" ;P; "Vbs=" ;Vsub

2350 ! PRINT "Vgs=" ; Vgs ( *

2 3 60 ! PRINT " Ids=" ; Ids ( *

2370 Vbs(P)=Vsub

2380 1=1

2390 FOR 1=1 TO 50

2400 Yn(P,I)=Ids(I)

103
2410

2420

2430

Id(P, I)=Ids(I)

IF ABS(Ids(I) ) >ABS(Ids_max) THEN Ids_max=Ids ( I

)

NEXT I 2440 ! 24 50 NEXT Vsub

2460 ! 2470 Disable_port

2480 ! 24 90 ! Draw axes

2500 ! 2510 CLEAR SCREEN

2520 IF lds_max=0. THEN Ids_max=100

.

2530 IF S=-l THEN GOTO 2560

2540 Lingraphl (0, 6*S, 0, Idsjmax, "Vgs" , "Ids" , "N-channel Vt at Vds=. 2V" , 1, 1, "Vbs"

2550 GOTO 2580

2560 Lingraphl (0, 6*S, 0, Idsjmax, "Vgs", "Ids" , "P-channel Vt at Vds=-. 2V" , 1, 1, "Vbs

2570 ! 2580 ! Plot an Id vs. Vg curve for a given Vbs value

2590 ! 2600 K=l

2 610 FOR K=l TO 4 2620 1=1

2630 FOR 1=1 TO Q

2640 Ids(I)=Yn(K,I)

2650 NEXT I

2730 NEXT K

2740 ! 27 50 PRINT " " 2760 PRINT "Width=", Width

2770 PRINT "Length=" , Length

2780 PRINT "Type=" ,Type$

2790 PRINT " " 2800 PRINT Concat$

2810 PRINT " " 282 0 ! PRINT "Vgs=" ;Vgs (*)

2830 ! PRINT "Vbs=" ; Vbs ( *)

2840 1PRINT "Ids=" ;Ids(*)

2850 ! 2860 ! Data for Id vs. Vg curves in the following:

2660

2670

2680

2690

2700

2710

2720

MOVE 0,0

1=1

FOR 1=1 TO Q

PLOT Vgs (I) , Ids (I)

NEXT I

! PRINT "K=" ;K; "1= " ; I

; " Q= " ;

Q

2870

2880

2890

2900

2910

2920

2930

2940

2950

2960

2970

2980

2990

3000

T=0

Vsub=Vbs_min

FOR Vsub=Vbs_min TO Vbs_max STEP Vbs_step

*****************************************************

Vds

Vgs (50)

Id(5,50)=Id(Vbs,Vg)

Vbs(4)

Find Vt for the different values of Vbs

Vbs and Vg not defined

104
3 010 i Sweep the Id vs. Vg curve

3020 I 3 03 0 T=T+1

3040 1=1

3050 FOR 1=1 TO Q

3060 X(I)=Vgs(I)

3070 Y(I)=Yn(T,I)

3080 NEXT I 3090 ! 3100 Slope_max=l. E-ll

3110 Rms_max=0

312 0 Xint_max=0.

313 0 M_max=0

3140 N=5

3150 M=l

3160 FOR M=l TO 45

3170 ! 318 0 GOTO Lnfit

3190 ! 3200 Back: Z=0

3210 IF ABS (Slope) >ABS(Slope_max) THEN M_max=M

3220 ! PRINT "Slope=" /Slope; "Slope_max=" ;Slope_max; "M_max=" ;M_max; "M="

3 230 IF ABS (Slope) >ABS(Slope_max) THEN Xint_max=Xint

3240 IF ABS (Slope) >ABS (Slope_max) THEN Rms_max=Rms

3250 IF ABS (Slope) >ABS (Slope_max) THEN Slope_max=Slope

3260 ! PRINT "Xint=" , Xint ; "M=" ;M

3270 ! 3280 NEXT M

3290 ! 3 3 00 Vt (T)=Xint_max-. 5*Vds

3310 PRINT "Vbs= M ;Vsub;"Vt=" ;Vt (T) ; "M_max=" ;M_max

3320 ! 33 3 0 NEXT Vsub

3 3 40 PRINT " "

3 3 50 PRINT " "

3 3 60 PRINT " "

3 370 GOTO Stop

3380 ! 3 3 90 ;*********************************************************

3400 ! 3410 ! Subroutine LNFIT (N,M, X, Y, Slope, Xint , Rms)

3420 ! 3430 ! N = # points

3440 ! M = start value of dimension

3450 ! 3460 !DIM X(l) , Y(l)

3470 !DIM Yint(lOl) ,Ycalc(101)

3480 ! 3490 Lnfit: 1=0

3 500 Sumx=0

3510 Sumy=0

3 52 0 Sumxy=0

3 53 0 Sumxx=0

3540 ! 3 550 FOR I=M TO M+N-l

3560 1PRINT "X=";X(I) ;"Y=";Y(I)

357 0 Sumx=Sumx+X ( I

3 58 0 Sumy=Sumy+Y ( I

3 590 Sumxy=Sumxy+X ( I

) *Y(I)

3 600 Sumxx=Sumxx+X(I) *X(I)

105
3610 NEXT I 3620 ! 3630 Anums=N*Sumxy-Sumx*Sumy

3 64 0 ! PRINT "Anums=" ; Anums

3 650 Anumi=Sumxx*Sumy-Sumx*Sumxy

3660 ! PRINT "Anumi=" ; Anumi

3670 Den=N*Sumxx-Sumx*Sumx

3 680 ! PRINT "Den=";Den

3690 IF Den=0 THEN GOTO 3780

3700 Slope=Anums/Den

3710 ! PRINT "Slope="; Slope

3720 Yint(M)=Anumi/Den

3730 IF Anums=0. THEN Xint=999

3740 IF Anums=0. THEN GOTO 3780

3750 Xint=-Anumi/Anums

3760 ! PRINT "Xint=" ; Xint

3770 ! 3780 ! Determine the RMS deviation in the Y direction

3790 ! 3800 J=0

3810 Squ=0

3 82 0 FOR J=M TO M+N-l

3830 Ycalc(J)=Slope*X(J)+Yint(M)

3840 Squ=Squ+(Y(J) -Ycalc(J) ) "2

3850 NEXT J

3860 ! 3870 Rms=SQRT(Squ/N)

3880 ! 3890 GOTO Back

3900 ! ****************************************************

3950 ! Vt(4)

3960 ! 3970 Stop: Disable_port

3980 ! 3990 ! Write data to the file

4000 ! 4010 OUTPUT String_4$;"Vbs then Vt values"

4020 OUTPUT String_l$ USING "/ , / , 18A, /" ;String_4$

4 03 0 OUTPUT @Path_l;String_l$

4040 K=l

4050 FOR K=l TO 4 4060 OUTPUT String_2$ USING "DDD . DDD , /

" ; Vbs (K)

4 07 0 OUTPUT @Path_l;String_2$

3910

3920

3930

3940 Vbs (4

Data for KEYS in the following

4080

4090

4100

4110

4120

4130

4140

4150

4160

4170

4180

4190

4200!

GOSUB Debuginfo

ASSIGN ©Path 1 TO *

NEXT K

! Close the I/O path

i****************************************************

OUTPUT

OUTPUT

String_3$ USING "DDD. DDD, /" ;Vt (K)

@Path_l ; Str ing_3

$

106
4210 SUBEXIT

4220!

4230 Debuginfo: ! display input values

424 0 PRINTER IS CRT

4250 ! PRINT "algorithm <Keysvt_MOS>"

4260 ! PRINT " W = ",W$

4270 ! PRINT " R = " , R$

4280 ! PRINT " C = " ,C$

4290 RETURN

4300 SUBEND

4310 !
APPENDIX E - Test Algorithm INV

APPENDIX E — Test algorithm INV (the program used to obtain the Vin

versus Vout curves on NIST8)

50 SUB Inv_inv(W$,R$, C$, INTEGER Pins (*), REAL Nwidth, Nlength, Pwidth, Plength, Vou

60 Inv inv: ! ************************************************

70

RE-STORE 'Vusers/marshall/icms/ALG/BASIC/InvJtNV"

LOADSUB ALL FROM "/usr/pcs/ lib/XYGRAPH" **************************************************************************

Programmers : Janet Marshall

Date

Revised

Device Class

Description

Procedure

04/21/1992 12:22:10

04/21/1992 12:22:10

INVERTER

Mosfet drain current measurement at specified

: Vds,Vgs,Vbs and Vss.

Input Variables:

# Name Type Size Description

Measurement Parameters:

1 W S

2 R S

3 C S

Device Terminals:

1 VCC I

2 VSS I

3 NW I 4 PW I

5 IN I

6 OUT I

7 Chuck I Device Parameters:

1 NWidth R

2 NLength R

3 PWidth R

4 PLength R

Output Variables:

# Name Type Size

Wafer Letter

Row Number

Column Number

Vcc terminal

Vss terminal

N-well terminal

P-well terminal

Data input

Data output

Wafer chuck

urn, Mask n-channel width

urn, Mask n-channel length

um, Mask P-channel width

um, Mask P"•channel length

Description

Output Parameters:

1 Vout A

2 Vin A

51 Output Voltage

51 Input Voltage ***************************************************************************

OPTION BASE 1

i INTEGER Vcc , Vss , Nwel 1 , Pwell , In , Out

INTEGER I,J,M,N,Q

108
610

620

630

640

650

660

670

680

690

700

710

720

730

740

750

760

770

780

790

800

810

820

830

840

850

860

870

880

890

900

910 I 920

930

940

950

960

970

980

990

1000

1010

1020

1030

1040

1050

1060

1070

1080

1090

1100

1110

1120

1130

1140

1150

1160

1170

1180

1190

1200

INTEGER Line, Voltage, Number

Q=51

ALLOCATE X(Q) ,Y(Q) ,Yint(Q) ,Ycalc(Q)

DIM File$ [40] ,Dir$[40] ,Concat$[40]

DIM String_l$[40] , String_2$ [40] , String_3 $ [ 40 ]

, String_4$ [40]

Determine the filename

C$="9"

IF Nlength=3.0 THEN R$="l"

IF Nlength=4.0 THEN R$="3"

IF Nlength=6.0 THEN R$="4"

IF Nlength=10.0 THEN R$="6"

iDir$=" /users/marshal 1 /data/"

iFile$= II W"&W$& M R"&R$&"C"&C$&"IV.DAT"

Concat$=Dir$&File$

PRINT Concat$

Create ASCII data file with 10 sectors

ON ERROR GOTO File_exists

CREATE ASCII Concat$,10

ile exists: OFF ERROR

Assign (or open) an I/O path name to the file

ASSIGN §Path 1 TO Concat$

Init_system

Define measurement pins

Vcc=Pins (1)

Vss=Pins (2)

Nwell=Pins(3)

Pwell=Pins (4)

In=Pins (5)

Out=Pins (6)

Connect pins to sources

Connect (FNSmu (3) ,Vcc)

Connect (FNGnd, Vss)

Connect (FNSmu (3) ,Nwell)

Connect (FNGnd, Pwell)

Connect ( FNSmu ( 2 ), In)

Connect ( FNSmu ( 1 ), Out)

Force bias conditions

109
1210 Vdd=5.0

1220 Set_smu(2) ! SET INTEGRATION TIME TO MEDIUM

12 3 0 Force_v(Vcc,Vdd)

1240 Force_v(Nwell, Vdd)

1250 ! 1260 ! Define variables

1270 ! 1280 Line=l

1290 Range=10.0

1300 Start=0.

1310 Stop=5.0

132 0 Number=51

1330 ! 1340 Hold=1.0

1350 Dstep=.01

1360 Icompl=.01

1370 ! 1380 Voltage=l

1390 Vrange=10.0

1400 ! 1410 ! Sweep Vin to get Vout

1420 ! 14 3 0 Set_iv( In, Line, Range, Start, Stop, Number , Hold, Dstep, Icompl)

144 0 Sweep_iv(Out, Voltage, Vrange, Vout (*) , Vin(*)

)

1450 ! 1460 ! Draw axes

1470 ! 1480 Disable_port

1490 CLEAR SCREEN

1500 PRINT " " 1510 ! 1520 Lingraphl( 0,6, 0,6," Vin", "Vout", "Vout vs. Vin", 1,1)

1530 ! 154 0 ! Plot an Id vs. Vg curve for a given Vbs value

1550 ! 1560 MOVE 0,0

1570 FOR 1=1 TO Q

1580 PLOT Vin(I) , Vout (I)

1590 X(I)=Vin(I)

1600 Y(I)=Vout(I)

1610 IPRINT "Vin=";Vin(I) ; "Vout=" ; Vout (I)

1620 NEXT I 1630 ! 164 0 ! Data for Vout vs. Vin curves in the following:

1650 ! 1660 ! Vin(51)

1670 ! Vout(51)

1680 ! 1690 J***************************************************************

1700 ! 1710 ! Find the values of Vout and Vin where the maximum slope exists

1720 ! 1730 ! 1740 ! Sweep the Vout vs. Vin curve

1750 ! 1760 N=5

1770 FOR M=l TO 47

1780 ! 179 0 GOTO Lnfit

1800 !

110
1810 Back: IF ABS (Slope) >ABS (Slope_max) THEN M_max=M

1820 IF ABS (Slope) >ABS (Slope_max) THEN Slope_max=Slope

1830 ! 1840 NEXT M

1850 i 1860 PRINT "Vin="

;

1870 PRINT ii ti 1880 PRINT Concat$

1890 PRINT ti ii 1900 PRINT H ii 1910 PRINT n ii 1920 PRINT H ii 1930 PRINT it ii 1940 PRINT H ii 1950 PRINT I ii 1960 PRINT ii ii 1970 PRINT ii ii 1980 PRINT ii ii 1990 PRINT ii ii 2000 j 2010 GOTO Stop

2020

2030 t ************

2040

2050 ! Subroutine

2060

2070 ! N = # point

*********************************************************

M = start value of dimension

DIM X(l) , Y(l)

DIM Yint(lOl) , Ycalc(lOl)

2080

2090

2100

2110

2120

2130 Lnfit: 1=0

214 0 Sumx=0

2150 Sumy=0

2160 Sumxy=0

2170 Sumxx=0

2180 ! 219 0 FOR I=M TO M+N-l

2200 1PRINT "X=";X(I) ;"Y=";Y(I)

2 210 Sumx=Sumx+X(I)

2220 Sumy=Sumy+Y (I)

2230 Sumxy=Sumxy+X ( I

) *Y(I)

2240 Sumxx=Sumxx+X ( I

) *X(I)

2250 NEXT I 2260 ! 2270 Anums=N*Sumxy-Sumx*Sumy

2280 1PRINT "Anums=" ;Anums

2290 Anumi=Sumxx*Sumy-Sumx*Sumxy

2300 'PRINT "Anumi=" ;Anumi

2 310 Den=N*Sumxx-Sumx*Sumx

2320 ! PRINT "Den=";Den

2330 IF Den=0 THEN GOTO 2410

2340 Slope=Anums/Den

2350 1PRINT "Slope=" /Slope

2360 Yint(M)=Anumi/Den

2370 IF Anums=0. THEN Xint=999

2380 IF Anums=0. THEN GOTO 2410

2 3 90 Xint=-Anumi/Anums

2400 !

Ill
2410 ! Determine the RMS deviation in the Y direction

2420 ! 2430 J=0

2440 Squ=0

24 50 FOR J=M TO M+N-l

2460 Ycalc(J)=Slope*X(J)+Yint(M)

2470 Squ=Squ+(Y(J) -Ycalc(J) ) "2

2480 NEXT J

2490 ! 2 500 Rms=SQRT(Squ/N)

2510 ! 2 52 0 GOTO Back

2 53 0 !****************************************************

2540 ! 2550 Stop: Disable_port

2560 ! 2570 ! Write the data to the file

2580 ! 2590 OUTPUT Str ing_l$ ; "Vin Vout"

2600 OUTPUT String_2$ USING "/ , / , 8A, /" ;String_l$

2 610 OUTPUT @Path_l;String_2$

2620 1=1

2630 FOR 1=1 TO 51

2640 OUTPUT String_3$ USING "SD . DDD, /

" ; Vin (I)

2 650 OUTPUT @Path_l ; String_3$

2660 ! 2 67 0 OUTPUT String_4$ USING "SD . DDD , /

" ; Vout (I)

2680 OUTPUT @Path_l ; Str ing_4

$

2690 NEXT I 2700 ! 2710 ! Close the I/O path

2720 ! 2730 ASSIGN @Path_l TO * 2740 ! 2750 J ****************************************************

2760!

2770 GOSUB Debuginfo

2780!

279 0 SUBEXIT

2800!

2810 Debuginfo: ! display input values

282 0 PRINTER IS CRT

2830 ! PRINT "algorithm <INV_MOS>"

2840 ! PRINT " W = ",W$

2850 ! PRINT " R = " , R$

2860 ! PRINT " C = " , C$

2870 RETURN

2880 SUBEND

2890 !

112
APPENDIX F - Test Algorithm SRAM

APPENDIX F — Test algorithm SRAM (the program used to determine the

functionality of the static RAM on NIST8)

SUB Sram_sra(W$,R$,C$, INTEGER Pins(*),REAL Nwidth, Nlength, Pwidth, Plength)

Sram sra : !********************************************************

RE-STORE "/users/marshall/icms/ALG/BASIC/Sram_SRA"

LOADSUB ALL FROM "/usr/pcs/lib/XYGRAPH"

120

!

***************************************************************

130

140

!

Programmers : Janet Marshall

150

!

160 Date : 04/21/1992 13:19 : 17

170 1 Revised : 04/21/1992 13:19 : 17

180

!

Device Class : SRAM

190

!

Description : Mosfet drain current measurement at specified

200 Vds,Vgs,Vbs and Vss

.

210 ! Procedure : 220

230 ! Input Variables:

240

250

260

270

! # Name Type Size Description

! Measurement Parameters

280 ! 1 W S Wafer Letter

290 ! 2 R S Row Number

300 ! 3 C s Column Number

310

320 ! Device Terminals:

330 ! 1 VCC I Vcc terminal

340 ! 2 VSS I Vss terminal

350 ! 3 NW I N-well terminal

360 ! 4 PW I P-well terminal

370 ! 5 WSEL I Write select

380 ! 6 RWSEL I Read-write select

390 ! 7 LAT I Data latch

400 ! 8 BIT I Bit

410 ! 9 BITBAR I Bitbar

420 ! 10 DATA I Data

430 ! 11 DATAB I Databar

440 ! 12 CHUCK I Wafer chuck

450

460 I Device Parameters:

470 ! 1 NWidth R urn, Mask n-channel width

480 ! 2 NLength R um, Mask n-channel length

490 ! 3 PWidth R um, Mask p-channel width

500 ! 4 PLength R um, Mask p-channel length

510

520 ! Output Variables:

530

540

550

! # Name Type Size Description

Output Parameters: none ***************************************************************************

i

113
610 OPTION BASE 1 620 ! 630 INTEGER Rwsel , Vcc , Nwel 1 , Latch , Pwel 1 , Bitbar , Databar , Bit , Data , Vss , Wsel

64 0 INTEGER I,J,M,N,Q

650 Q=13

660 ! 670 ALLOCATE Datao (Q) , Databaro (Q) , Ind (Q+l)

680 ALLOCATE Biti (Q) , Bitbari (Q) , Rw (Q) , W (Q) , Lat (Q)

690 DIM File$[40] ,Dir$[40] ,Concat$[40]

700 DIM String_l$[40] , String_2$ [40] , String_3$ [ 40 ], String_4$ [40]

710 ! 720 ! ===================================================================

730 ! 740 I Determine the filename

750 ! 760 Dir$=" /users/marshal 1/data/"

770 ! 780 File$= ,I W"&W$&"R,l &R$&"C"&C$& 1, SR.DAT ,l 790 ! 800 Concat$=Dir$&File$

810 ! 820 ! Create an ASCII data file with 10 sectors

830 ! 840 ON ERROR GOTO File_exists

850 CREATE ASCII Concat$,10

860 File_exists: OFF ERROR

870 I 880 ! Assign (or open) and I/O path name to the file

890 ! 900 ASSIGN @Path_l TO Concat$

910 ! 92 0 ! ===^==^========; ====================;=======.========================:===

930 ! 940 Init_system

950 ! 960 ! Define measurement pins

970 ! 980 Rwsel=Pins (6)

990 Vcc=Pins(l)

1000 Nwell=Pins(3)

1010 Latch=Pins(7)

1020 Pwell=Pins(4)

1030 Bitbar=Pins(9)

1040 Databar=Pins(ll)

1050 Bit=Pins(8)

1060 Data=Pins(l0)

1070 Vss=Pins(2)

1080 Wsel=Pins(5)

1090 ! 1100 ! Connect pins to sources

1110 ! 1120 Connect (FNSmu ( 1) , Data)

113 0 Connect ( FNSmu ( 2 ), Latch

)

1140 Connect (FNSmu (3) , Rwsel)

1150 Connect (FNSmu (4) , Databar)

1160 ! 1170 Connect (FNAux ( 1) , Wsel)

1180 ! 1190 Connect (FNAux (2) , Vcc)

1200 Connect (FNAux (2) , Nwel 1)

114
1210 Connect (FNAux (2) , Bit)

1220 i 12 3 0 Connect (FNGnd,Vss)

1240 Connect (FNGnd, Pwell)

1250 Connect (FNGnd, Bitbar)

Force the INITIAL bias conditions

1260

1270

1280

12 9 0 Vgnd=0.

13 00 Vdd=5.0

1310 Value=Vdd

13 2 0 Valuebar=Vgnd

1330 1=0

1340 J=l

1350 Ind(J)=J

1360 ! 13 7 0 Force_v(Vcc,Vdd)

1380 Force_v(Nwell,Vdd)

1390 Force_v(Bit, Value)

1400 ! 1410 Force_v (Latch, Vgnd)

1420 Force_v(Rwsel, Vgnd)

14 3 0 Force_v(Wsel, Vgnd)

1440 ! 1450 Measure_v(Data,Datao(J) ) 1460 Measure_v(Databar,Databaro(J) ,0)

1470 ! 14 8 0 PRINT "I",-J 1490 ! PRINT "Dataout=" ;Datao(J) ; "Databarout=" ; Databaro (J)

1500 ! PRINT "Dataout=" ;Datao(J)

1510 Biti (J)=Value

1520 Bitbari(J)=Valuebar

1530 Rw(J)=0.

1540 W(J)=0.

1550 Lat(J)=0.

1560 J=J+1

1570 Ind(J)=J

1580

1590

1600

1610 PRINT 11 " 1620 1=1+1

163 0 Force_v (Latch, Vdd)

164 0 Force_v(Rwsel, Vdd)

1650 Force_v(Wsel, Vdd)

1660 WAIT 1 1670 Force_v( Latch, Vgnd)

1680 Force_v(Rwsel, Vgnd)

1690 Force_v(Wsel, Vgnd)

1700 ! 1710 Measure_v(Data,Datao(J)

)

1720 Measure_v (Databar, Databaro (J)

)

17 3 0 PRINT "W";J

1740 1PRINT "Dataout=";Datao(J) ; "Databarout=" /Databaro (J)

1750 ! PRINT "Dataout=" ;Datao(J)

1760 Biti(J)=Value

1770 Bitbari(J)=Valuebar

1780 Rw(J)=5.

1790 W(J)=5.

1800 Lat(J)=5.

Perform a WRITE

115
1810 J=J+1

1820 Ind(J)=J

1830 ! 1840 ! Change the Datain

1850 ! 1860 IF 1=2 OR 1=4 THEN GOTO 2080

1870 Connect (FNSmu( 6) ,Bitbar)

1880 Connect (FNGnd, Bit)

1890 Value=0.

1900 Valuebar=5.0

1910 Force_v(Bitbar , Valuebar)

192 0 Execute

1930 ! 1940 Measure_v (Data , Datao (J)

)

1950 Measure_v (Databar , Databaro (J)

)

1960 PRINT "D" ;J

1970 1PRINT "Dataout=" ;Datao(J) ; "Databarout=" ; Databaro (J)

1980 ! PRINT "Dataout=";Datao(J)

1990 Biti(J)=Value

2000 Bitbari (J) =Valuebar

2010 Rw(J)=0.

2020 W(J)=0.

2030 Lat(J)=0.

2040 J=J+1

2050 Ind(J)=J

2060 GOTO 2300

2070 ! 2080 ! Rechange the Datain

2090 ! 2100 Connect (FNSmu( 6) , Bit)

2110 Connect ( FNGnd, Bitbar)

2120 Value=5.0

213 0 Valuebar=0.

2140 Force_v(Bit, Value)

2150 Execute

2160 ! 2170 Measure_v (Data, Datao (J)

)

2180 Measure_v( Databar, Databaro (J)

)

2190 PRINT "D";J

2200 I PRINT "Dataout=";Datao(J) ; "Databarout=" ; Databaro (J)

2210 ! PRINT "Dataout=";Datao(J)

2220 Biti(J)=Value

2230 Bitbari (J) =Valuebar

2240 Rw(J)=0.

2250 W(J)=0.

2260 Lat(J)=0.

227 0 J=J+1

2280 Ind(J)=J

2290 ! 23 00 ! Perform a READ

2310 ! 2320 WAIT 1 23 3 0 Force_v(Rwsel,Vdd)

2 340 Force_v(Wsel, Vgnd)

2 3 50 Force_v( Latch, Vgnd)

2360 ! 2370 Measure_v (Data, Datao (J)

)

2380 Measure_v (Databar, Databaro (J)

)

2390 PRINT "R";J;"*"

2400 1PRINT "Dataout=" ;Datao(J) ; "Databarout=" ; Databaro (J)

116
2410 ! PRINT M Dataout=" ;Datao(J)

2420 Biti(J)=Value

2430 Bitbari(J)=Valuebar

2440 Rw(J)=5.

2450 W(J)=0.

2460 Lat(J)=0.

247 0 J=J+1

2480 Ind(J)=J

2490 ! 2 500 Force_v(Rwsel,Vgnd)

2510 IF 1=4 THEN GOTO 2540

2520 GOTO 1590

2530 ! 2 54 0 ! Draw axes

2550 ! 2560 Disable_port

2570 CLEAR SCREEN

2580 ! 2590 Lingraphl (0,Q+1, 0, 6, "Time" , "Datain" , "Datain vs. Time" ,1,1, "SRAM"

)

2600 ! 2610 I Plot Datain vs. Time

2620 ! 2 63 0 MOVE 0,0

2640 M=l

2 650 FOR M=l TO Q

2660 PLOT Ind(M) ,Biti(M)

2670 1PRINT "Ind";Ind(M) ; "Datain=" ; Biti (M)

2680 NEXT M

2690 ! 2700 ! Draw axes

2710 ! 2720 Lingraphl (0,Q+1, 0,6, "Time" , "Dataout" , "Dataout vs. Time" , 1 , 4

, "SRAM"

)

2730 ! 274 0 ! Plot Data vs. Time

2750 ! 2760 MOVE 0,0

2770 M=l

2780 FOR M=l TO Q

2790 PLOT Ind(M) ,Datao(M)

2800 JPRINT "Ind";Ind(M) ; "Data=" ;Datao (M)

2810 NEXT M

2820 ! 283 0 ! Draw axes

2840 ! 2850 Lingraphl (0,Q+1, 0, 6, "Time" , "Rwsel" , "Rwsel vs. Time" , 1 , 3

, "SRAM"

)

2860 ! 2870 ! Plot Rwsel, Wsel, or Latch vs. Time

2880 1 Rw(J), W(J), Lat(J)

2890 ! 2900 MOVE 0,0

2910 M=l

2920 FOR M=l TO Q

2930 PLOT Ind(M),Rw(M)

2940 ! PRINT "Ind" ; Ind (M) ; "Rwsel=" ;Rw(M)

2950 NEXT M

2960 ! 2 97 0 ! Draw axes

2980 ! 2990 Lingraphl (0,Q+1, 0,6, "Time", "Databarout" , "Databarout vs. Time" , 1, 2

, "SRAM")

3000

117
3010

3020

3030

3040

3050

3060

3070

3080

3090

3100

3110

3120

3130

3140

3150

3160

3170

3180

3190

3200

3210

3220

3230

3240

3250

3260

3270

3280

3290

3300

3310

3320

3330

3340!

3350

3360!

3370

3380

3390

3400

3410

3420

3430

3440

3450

! Plot Databarout vs. Time

i MOVE 0,0

M=l

FOR M=l TO Q

PLOT Ind(M) ,Databaro(M)

! PRINT "Ind";Ind(M) ; "Databaro=" ; Databaro (M)

NEXT M

Data for Datao vs. Time curves in the following:

Datao (5)

Databaro (5)

Time (5) **********************************************

Disable_port

PRINT Concat$

Write the data to the file

OUTPUT String_l$;"SRAM Data"

OUTPUT String_2$ USING "/ , / , 15A, /" ;String_l$

OUTPUT @Path_l;String_2$

i

! Close the I/O path

ASSIGN @Path_l TO *

i

i ****************************************************

GOSUB Debuginfo

SUBEXIT

Debuginfo: ! display input values

PRINTER IS CRT

•PRINT "algorithm <Sram_SRA>"

! PRINT " W = ",W$

•PRINT " R = ",R$

! PRINT " C = ",C$

RETURN

SUBEND

118
APPENDIX G - SPICE File for an TV-Channel MOSFET

* Appendix G - SPICE file (named ivcharn.cel) for an n-channel MOSFET

*

* f i I ename = [ma rsha I I . s i mox] n i stSmod . f i

** FILENAME = NMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODN NMOS LEVEL=2 LD=O.250OOOU TOX=413.000008E-10

+ NSUB=6.294117E+15 VT0=O. 807671 KP=4 . 465000E-05 GAMMA=0.5467

+ PHI=0.6 U0=534.071 UEXP=. 16209 UCRIT=90795 .

+ DELTA=1. 01989 VMAX=57490.9 XJ=0.250000U LAMBDA=3 . 494828E-02

+ NFS=5.034625E+12 NEFF=1 NSS=1 .000000E+10 TPG=1. 000000

+ RSH=28. 380000 CGDO=3.135421E-10 CGSO=3.135421E-10 CGBO=3.907717E-10

+ CJ=9.308500E-05 MJ=0. 693518 CJSW=5 . 398300E-10 MJSW=0. 284549 PB=0. 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.28 urn ** FILENAME = PMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODP PMOS LEVEL=2 LD=0.152257U TOX=413.000008E-10

* NSUB=7.140277E+15 VTO=-0 . 807327 KP=2 . 383000E-05 GAMMA=0.5823

+ PHI=0.6 U0=284.969 UEXP=0 . 231562 UCRIT=15586.3

+ DELTA=0. 920741 VMAX=45761.7 XJ=0.250000U LAMBDA=5 . 083543E-02

+ NFS=7.553318E+11 NEFF=1.001 NSS=1 .OOOOOOE+10 TPG=-1 .000000

+ RSH=87. 650000 CGD0=1 .909559E-10 CGS0=1 . 909559E-10 CGB0=3 . 770536E-10

* CJ=2.500000E-04 MJ=0. 545647 CJSW=3 . 174900E-10 MJSW=0. 330136 PB=0. 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.20 urn

* FILENAME = IVCHARN . FIL

* NOTE: Use with MODEL. FIL to make IVCHARN.CEL

* N-CHANNEL MOS OUTPUT CHARACTERISTICS

*Ml 1 2 0 0 MODN L=3.0UM W=6.0UM AD=12.5P AS=12.5P PD=15U

+ PS=15U NRD=2.0 NRS=2.0

*VD 3 0

VG 2 0

VIDS 3 1

*

. OPTIONS NODE NOPAGE

.DC VD 0 5 .5 VG 0 5 1

.PLOT DC I (VIDS)

.END

119
APPENDIX H - SPICE File for an Inverter

* Appendix H - SPICE file (named i nverter .eel) for an inverter

** filename = [marshal I . simox] nist8mod.fi I

* FILENAME = NMODEL . FIL (parameters from NIST8 MOSIS run)

*.MODEL MODN NMOS LEVEL=2 LD=0.250000U TOX=413.000008E-10

+ NSUB=6.294117E+15 VT0=O. 807671 KP=4 . 465000E-05 GAMMA=0.5467

+ PHI=0.6 110=534.071 UEXP=. 16209 UCRIT=90795.9

+ DELTA=1. 01989 VMAX=57490.9 XJ=0.250000U LAMBDA=3 . 494828E-02

* NFS=5.034625E+12 NEFF=1 NSS=1 .OOOOOOE+10 TPG=1. 000000

+ RSH=28. 380000 CGDO=3.135421E-10 CGS0=3. 135421 E-10 CGBO=3.907717E-10

+ CJ=9.308500E-05 MJ=0. 693518 CJSW=5 . 398300E-10 MJSW=0 . 284549 PB=0 . 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.28 urn *

* FILENAME = PMODEL . FIL (parameters from NIST8 MOSIS run)

*.MODEL MODP PMOS LEVEL=2 LD=0.152257U TOX=413.000008E-10

+ NSUB=7.140277E+15 VTO=-0 . 807327 KP=2 . 383000E-05 GAMMA=0.5823

+ PHI=0.6 U0=284.969 UEXP=0 . 231562 UCRIT=15586.3

+ DELTA=0. 920741 VMAX=45761.7 XJ=0.250000U LAMBDA=5 . 083543E-02

+ NFS=7.553318E+11 NEFF=1.001 NSS=1 .OOOOOOE+10 TPG=-1 .000000

+ RSH=87. 650000 CGD0=1 . 909559E-10 CGS0=1 .909559E-10 CGBO=3.770536E-10

+ CJ=2.500000E-04 MJ=0. 545647 CJSW=3 . 174900E-10 MJSW=0. 330136 PB=0. 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.20 urn *

*

*

* FILENAME = INVERTER. FIL

.SUBCKT INVERT 12 3

*Ml 100 1 0 0 MODN L=3.00UM W=6.00UM AD=84P AS=84P PD=40U

+ PS=40U NRD=2.0 NRS=2.0

M2 100 1 3 3 MODP L=3.00UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

Rl 100 2 300

CI 2 0 50P

*.ENDS INVERT

XI 1 2 3 INVERT

*VIN 1 0

VCC 3 0 5V

*.OPTIONS LIMPTS=500

120
.DC VIN 0.5 4.5 0.1

.PLOT DC V(2)

.END
APPENDIX I - SPICE File for a Ring Oscillator

* Appendix I - SPICE file (named ring. eel) for a ring oscillator

*

* filename = [marshal I .simox] nist8mod.fi I

* FILENAME = NMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODN NMOS LEVEL=2 LD=0.250000U TOX=413.000008E-10

+ NSUB=6.294117E+15 VT0=O. 807671 KP=4 . 465000E-05 GAMMA=0.5467

+ PHI=0.6 UO=534.071 UEXP=. 16209 UCRIT=90795 .

9

+ DELTA=1. 01989 VMAX=57490.9 XJ=0 . 250000U LAMBDA=3 . 494828E-02

+ NFS=5.034625E+12 NEFF=1 NSS=1 .OOOOOOE+10 TPG=1. 000000

+ RSH=28. 380000 CGDO=3.135421E-10 CGSO=3.135421E-10 CGB0=3 .907717E-10

+ CJ=9.308500E-05 MJ=0. 693518 CJSW=5.398300E-10 MJSW=0 . 284549 PB=0 . 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.28 urn *

* FILENAME = PMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODP PMOS LEVEL=2 LD=0.152257U TOX=413.000008E-10

+ NSUB=7.140277E+15 VTO=-0 . 807327 KP=2 . 383000E-05 GAMMA=0.5823

+ PHI=0.6 U0=284.969 UEXP=0 . 231562 UCRIT=15586 .

3

+ DELTA=0. 920741 VMAX=45761.7 XJ=0.250000U LAMBDA=5 . 083543E-02

+ NFS=7.553318E+11 NEFF=1.001 NSS=1 .OOOOOOE+10 TPG=-1 .000000

+ RSH=87. 650000 CGD0=1 . 909559E-10 CGS0=1 .909559E-10 CGB0=3 . 770536E-10

+ CJ=2.500000E-04 MJ=0. 545647 CJSW=3.174900E-10 MJSW=0. 330136 PB=0 . 800000

* Weff = Wdrawn - Delta_W

* The suggested DeltaW is -0.20 urn

* f i lename - RING.FIL

*

* FILENAME = OUTBUF.FIL

*.SUBCKT OUTBUF 12 3 4 5 6

*Ml 2 1 0 0 MODN L=6.0UM W=6.0UM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

M2 2 1 3 3 MODP L=6.0UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

Rl 2 200 175

CI 200 0 .043P

*M3 4 200 0 0 MODN L=6.0UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

M4 4 200 3 3 MODP L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

R2 4 400 250

C2 400 0 .043P

*M5 5 400 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

122
+ PS=72U NRD=0.5 NRS=0.5

M6 5 400 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

R3 5 500 350

C3 500 0 .043P

*M7 600 500 0 0 MODN L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

M8 600 500 3 3 MODP L=6.0UM W=96.0UM AD=1152P AS=1152P PD=216U

+ PS=216U NRD=0.125 NRS=0.125

R4 600 6 300

C4 6 0 1PF

.ENDS OUTBUF

* FILENAME = NAND.FIL

*.SUBCKT NAND 12 3 4 5

*Ml 4 1 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

M2 500 1 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

*M3 500 2 4 0 MODN l_=6.0UM W=24 . OUM AD=288P AS=288P PD=72U

PS=72U NRD=0.5 NRS=0.5

M4 500 2 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

Rl 500 5 250

CI 5 0 .043P

*.ENDS NAND

* FILENAME = INVERT. FIL

.SUBCKT INVERT 12 3

*Ml 100 1 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

PS=72U NRD=0.5 NRS=0.5

M2 100 1 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

Rl 100 2 250

CI 2 0 .043P

*.ENDS INVERT

X25 201 202 3 204 1 NAND

*XI 1 2 3 INVERT

X2 2 4 3 INVERT

123
X3 4 5 3 INVERT

X4 5 6 3 INVERT

X5 6 73 INVERT

X6 7 8 3 INVERT

X7 8 9 3 INVERT

X8 9 10 3 INVERT

X9 10 11 3 INVERT

X10 11 12 3 INVERT

Xll 12 13 3 INVERT

*RCIR 13 130 10

CCIR 130 0 .088P

*X13 130 14 3 INVERT

X14 14 15 3 INVERT

X15 15 16 3 INVERT

X16 16 17 3 INVERT

X17 17 18 3 INVERT

X18 18 19 3 INVERT

X19 19 20 3 INVERT

X20 20 21 3 INVERT

X21 21 22 3 INVERT

X22 22 23 3 INVERT

X23 23 24 3 INVERT

*X24 24 102 3 104 105 106 OUTBUF

*RLOOP 24 201 635

CLOOP 201 0 .073P

*.IC V(l)=5 V(2)=0 V(4)=5 V(5)=0 V(6)=5 V(7)=0 V(8)=5

.IC V(9)=0 V(10)=5 V(11)=0 V(12)=5 V(13)=0 V(14)=5 V(15)=0

.IC V(16)=5 V(17)=0 V(18)=5 V(19)=0 V(20)=5

K

* .IC V(21)=0 V(22)=5 V(23)=0 V(24)=5

• IC V(102)=0 V(104)=5 V(105)=0 V(106)=5

*.IC V(201)=5 V(202)=0 V(204)=0

.IC V(3)=5

*VCC 3 0 5V

VA 202 0 5V

*VA 202 0 PULSE (OV 5V 20NS 5NS 5NS 150NS 200NS)

•OPTIONS VNTOL=10UV LIMPTS=500 ITL4=50 ITL5=0

.TRAN l.ONS 400NS 200NS UIC

*

* node 1 = right after NAND

* node 24 = right before NAND and OUTBUF

* node 106 = OUTPUT

124
* node 202 = NAND enabler

*.PLOT TRAN V(l)

.PLOT TRAN V(24)

.PLOT TRAN V(106)

.PLOT TRAN V(202)

*.END
APPENDIX J - SPICE File for a Ring Oscillator Using H-Gate MOSFETs

* Appendix J - SPICE file (named ri nghg.cel) for a ring oscillator using H-gate

* MOSFETs

*

* f i I ename = [marsha I I . s i mox] n i st8mod . f i

I

* FILENAME = NMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODN NMOS LEVEL=2 LD=0.250000U T0X=413. 000008E- 10

+ NSUB=6.294117E+15 VT0=O. 807671 KP=4 . 465000E-05 GAMMA=0.5467

+ PHI=0.6 U0=534.071 UEXP=. 16209 UCRIT=90795 .

9

+ DELTA=1. 01989 VMAX=57490.9 XJ=0.250000U LAMBDA=3 . 494828E-02

+ NFS=5.034625E+12 NEFF=1 NSS=1 .OOOOOOE+10 TPG=1. 000000

+ RSH=28. 380000 CGDO=3.135421E-10 CGSO=3.135421E-10 CGB0=3 . 907717E-10

+ CJ=9.308500E-05 MJ=0. 693518 CJSW=5 . 398300E-10 MJSW=0 . 284549 PB=0. 800000

* Weff = Weirawn - Delta_W

* The suggested Delta_W is -0.28 urn

* FILENAME = PMODEL . FIL (parameters from NIST8 MOSIS run)

*.MODEL MODP PMOS LEVEL=2 LD=0.152257U T0X=413 .000008E-10

+ NSUB=7.140277E+15 VTO=-0 . 807327 KP=2 . 383000E-05 GAMMA=0.5823

+ PHI=0.6 U0=284.969 UEXP=0 . 231562 UCRIT=15586 .3 + DELTA=0. 920741 VMAX=45761.7 XJ=0 . 25OOO0U LAMBDA=5 . 083543E-02

+ NFS=7.553318E+11 NEFF=1.001 NSS=1 .OOOOOOE+10 TPG=-1 .000000

+ RSH=87. 650000 CGD0=1 . 909559E-10 CGS0=1 . 909559E-10 CGB0=3 . 770536E-10

+ CJ=2.50OOOOE-04 MJ=0. 545647 CJSW=3 . 174900E-10 MJSW=0 . 330136 PB=0. 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.20 um

*

* f i I ename = RINGHG . FIL

* FILENAME = OUTBUF.FIL

.SUBCKT OUTBUF 12 3 4 5 6

*Ml 2 1 0 0 MODN L=6.0UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

M2 2 1 3 3 MODP L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

Rl 2 200 500

CI 200 0 .070P

*M3 4 200 0 0 MODN L=6.0UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

M4 4 200 3 3 MODP L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

R2 4 400 575

C2 400 0 .070P

*

126
M5 5 400 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

M6 5 400 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

R3 5 500 710

C3 500 0 .070P

*M7 600 500 0 0 MODN L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

M8 600 500 3 3 MODP L=6.0UM W=96.0UM AD=1152P AS=1152P PD=216U

+ PS=216U NRD=0.125 NRS=0.125

R4 600 6 300

C4 6 0 1PF

*.ENDS OUTBUF

* FILENAME = NAND.FIL

.SUBCKT NAND 12 3 4 5

*Ml 4 1 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

M2 500 1 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

*M3 500 2 4 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

M4 500 2 3 3 MODP L=6.0UM W=48 . OUM AD=576P AS=576P PD=120U

* PS=120U NRD=0.25 NRS=0.25

Rl 500 5 575

CI 5 0 .070P

*.ENDS NAND

* FILENAME = INVERT. FIL

*.SUBCKT INVERT 12 3

*Ml 100 1 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

M2 100 1 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

Rl 100 2 575

CI 2 0 .070P

*.ENDS INVERT

X25 201 202 3 204 1 NAND

127
XI 1 2 3 INVERT

X2 2 4 3 INVERT

X3 4 5 3 INVERT

X4 5 6 3 INVERT

X5 6 73 INVERT

X6 7 8 3 INVERT

X7 8 9 3 INVERT

X8 9 10 3 INVERT

X9 10 11 3 INVERT

X10 11 12 3 INVERT

XII 12 13 3 INVERT

*RCIR 13 130 10

CCIR 130 0 .088P

*X13 130 14 3 INVERT

X14 14 15 3 INVERT

X15 15 16 3 INVERT

X16 16 17 3 INVERT

X17 17 18 3 INVERT

X18 18 19 3 INVERT

XI 9 19 20 3 INVERT

X20 20 21 3 INVERT

X21 21 22 3 INVERT

X22 22 23 3 INVERT

X23 23 24 3 INVERT

*X24 24 102 3 104 105 106 OUTBUF

*RLOOP 24 201 1000

CLOOP 201 0 .073P

*

• IC V(l)=5 V(2)=0 V(4)=5 V(5)=0 V(6)=5 V(7)=0 V(8)=5

.IC V(9)=0 V(10)=5 V(11)=0 V(12)=5 V(13)=0 V(14)=5 V(15)=0

.IC V(16)=5 V(17)=0 V(18)=5 V(19)=0 V(20)=5

• IC V(21)=0 V(22)=5 V(23)=0 V(24)=5

IC V(102)=0 V(104)=5 V(105)=0 V(106)=5

.IC V(201)=5 V(202)=0 V(204)=0

.IC V(3)=5

*VCC 3 0 5V

VA 202 0 5V

*VA 202 0 PULSE (OV 5V 20NS 5NS 5NS 150NS 200NS)

*.OPTIONS VNTOL=10UV LIMPTS=500 ITL4=50 ITL5=0

.TRAN l.ONS 200NS UIC

** node 1 = right after NAND

*

128
* node 24

* node 106

* node 202

= right before NAND and OUTBUF

= OUTPUT

= NAND enabler

.PLOT TRAN V(l)

.PLOT TRAN V(24)

.PLOT TRAN V(106)

.PLOT TRAN V(202)

*.END

129
APPENDIX K - SPICE File for an SRAM

* Appendix K - SPICE file (named sram.cel ) for an SRAM

* filename - [marshal I .simox] nist8mod.fi I

* FILENAME = NMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODN NMOS LEVEL=2 LD=0 . 250000U TOX=413.000008E-10

+ NSUB=6.294117E+15 VT0=O. 807671 KP=4 . 465000E-05 GAMMA=0.5467

+ PHI=0.6 UO=534.071 UEXP=. 16209 UCRIT=90795 .

9

+ DELTA=1. 01989 VMAX=57490.9 XJ=0.250000U LAMBDA=3 . 494828E-02

+ NFS=5.034625E+12 NEFF=1 NSS=1 .OOOOOOE+10 TPG=1 . 000000

+ RSH=28. 380000 CGDO=3.135421E-10 CGS0=3. 135421 E-10 CGBO=3.907717E-10

+ CJ=9.308500E-05 MJ=0. 693518 CJSW=5 .398300E-10 MJSW=0 . 284549 PB=0 . 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.28 urn *

* FILENAME = PMODEL.FIL (parameters from NIST8 MOSIS run)

*.MODEL MODP PMOS LEVEL=2 LD=0.152257U TOX=413.000008E-10

+ NSUB=7 . 140277E+15 VTO=-0 . 807327 KP=2 . 383000E-05 GAMMA=0 . 5823

+ PHI=0.6 U0=284.969 UEXP=0 . 231562 UCRIT=15586.3

+ DELTA=0. 920741 VMAX=45761.7 XJ=0.250000U LAMBDA=5 . 083543E-02

+ NFS=7.553318E+11 NEFF=1.001 NSS=1 .OOOOOOE+10 TPG=-1 .000000

+ RSH=87. 650000 CGD0=1 .909559E-10 CGS0=1 .909559E-10 CGB0=3 . 770536E-10

+ CJ=2.500000E-04 MJ=0. 545647 CJSW=3 . 174900E-10 MJSW=0. 330136 PB=0 . 800000

* Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.20 urn *

* filename = sram.fi I

* FILENAME = OUTBUF.FIL

*.SUBCKT OUTBUF 12 3 4 5 6

*Ml 2 1 0 0 MODN L=6.0UM W=6.0UM AD=72P AS=72P PD=36U

* PS=36U NRD=2.0 NRS=2.0

M2 2 1 3 3 MODP L=6.0UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

Rl 2 200 175

CI 200 0 .043P

*M3 4 200 0 0 MODN L=6.0UM W=12.0UM AD=144P AS=144P PD=48U

+ PS=48U NRD=1.0 NRS=1.0

M4 4 200 3 3 MODP L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

+ PS=72U NRD=0.5 NRS=0.5

R2 4 400 250

C2 400 0 .043P

*M5 5 400 0 0 MODN L=6.0UM W=24.0UM AD=288P AS=288P PD=72U

130
+ PS=72U NRD=0.5 NRS=0.5

M6 5 400 3 3 MODP L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

R3 5 500 350

C3 500 0 .043P

*M7 600 500 0 0 MODN L=6.0UM W=48.0UM AD=576P AS=576P PD=120U

+ PS=120U NRD=0.25 NRS=0.25

M8 600 500 3 3 MODP L=6.0UM W=96.0UM AD=1152P AS=1152P PD=216U

+ PS=216U NRD=0.125 NRS=0.125

R4 600 6 300

C4 6 0 50PF

*.ENDS OUTBUF

Ml 4 2 1 0 MODN L=6.0UM W=6.0UM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

M2 4 2 3 3 MODP L=6.0UM W=36.0UM AD=432P AS=432P PD=96U

+ PS=96U NRD=0,33 NRS=0.33

*M3 2 4 1 0 MODN L=6.0UM W=6.0UM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

M4 2 4 3 3 MODP L=6.0UM W=36.0UM AD=432P AS=432P PD=96U

+ PS=96U NRD=0.33 NRS=0.33

*M5 4 5 101 0 MODN L=6.0UM W=6.0UM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

M6 9 7 101 0 MODN L=6.0UM W=6 . OUM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

*M7 2 5 201 0 MODN L=6.0UM W=6.0UM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

M8 10 7 201 0 MODN L=6 . OUM W=6 . OUM AD=72P AS=72P PD=36U

+ PS=36U NRD=2.0 NRS=2.0

*XI 101 102 3 104 105 106 OUTBUF

X2 201 202 3 204 205 206 OUTBUF

*.IC V(1)=0 V(5)=0 V(7)=0 V(9)=0 V(10)=5

.IC V(2)=0 V(4)=5

*.IC V(2)=5 V(4)=0

.IC V(101)=0 V(102)=5 V(104)=0 V(105)=5 V(106)=0

.IC V(201)=5 V(202)=0 V(204)=5 V(205)=0 V(206)=5

.IC V(3)=5

VCC 3 0 5V

VLATCH 1 0 PULSE (OV 5V 5NS 5NS 5NS 100NS 200NS)

VLATCH 1 0 OV

VRWSEL 5 0 PULSE (OV 5V IONS 5NS 5NS 100NS 200NS)

VWSEL 7 0 PULSE (OV 5V 15NS 5NS 5NS 100NS 200NS)

131
VWSEL 7 0 OV

VBIT 9 0 OV

VBITBAR 10 0 5V

*

. OPTIONS VNTOL=10UV LIMPTS=500 ITL4=50 ITL5=0

.TRAN l.ONS 200NS UIC

*.PLOT TRAN V(l)

.PLOT TRAN V(2)

.PLOT TRAN V(4)

.PLOT TRAN V(101)

.PLOT TRAN V(106)

.PLOT TRAN V(201)

.PLOT TRAN V(206)

*.END

132 U.S. GOVERNMENT PRINTING OFFICE: 1994-300-568/03018


i tX kJ J. Technical Publications

Periodical

Journal of Research of the National Institute of Standards and Technology — Reports NIST

research and development in those disciplines of the physical and engineering sciences in which

the Institute is active. These include physics, chemistry, engineering, mathematics, and computer

sciences. Papers cover a broad range of subjects, with major emphasis on measurement

methodology and the basic technology underlying standardization. Also included from time to time

are survey articles on topics closely related to the Institute's technical and scientific programs.

Issued six times a year.

Nonperiodicals

Monographs — Major contributions to the technical literature on various subjects related to the

Institute's scientific and technical activities. Handbooks — Recommended codes of engineering and industrial practice (including safety codes)

developed in cooperation with interested industries, professional organizations, and regulatory

bodies.

Special Publications — Include proceedings of conferences sponsored by NIST, NIST annual

reports, and other special publications appropriate to this grouping such as wall charts, pocket

cards, and bibliographies.

Applied Mathematics Series — Mathematical tables, manuals, and studies of special interest to

physicists, engineers, chemists, biologists, mathematicians, computer programmers, and others

engaged in scientific and technical work.

National Standard Reference Data Series — Provides quantitative data on the physical and chemical

properties of materials, compiled from the world's literature and critically evaluated. Developed

under a worldwide program coordinated by NIST under the authority of the National Standard

Data Act (Public Law 90-396). NOTE: The Journal of Physical and Chemical Reference Data

(JPCRD) is published bimonthly for NIST by the American Chemical Society (ACS) and the

American Institute of Physics (AIP). Subscriptions, reprints, and supplements are available from

ACS, 1155 Sixteenth St., NW, Washington, DC 20056.

Building Science Series — Disseminates technical information developed at the Institute on building

materials, components, systems, and whole structures. The series presents research results, test methods, and performance criteria related to the structural and environmental functions and the

durability and safety characteristics of building elements and systems.

Technical Notes — Studies or reports which are complete in themselves but restrictive in their treatment of a subject. Analogous to monographs but not so comprehensive in scope or definitive

in treatment of the subject area. Often serve as a vehicle for final reports of work performed at NIST under the sponsorship of other government agencies.

Voluntary Product Standards — Developed under procedures published by the Department of

Commerce in Part 10, Title 15, of the Code of Federal Regulations. The standards establish

nationally recognized requirements for products, and provide all concerned interests with a basis

for common understanding of the characteristics of the products. NIST administers this program

in support of the efforts of private-sector standardizing organizations.

Consumer Information Series — Practical information, based on NIST research and experience,

covering areas of interest to the consumer. Easily understandable language and illustrations provide useful background knowledge for shopping in today's technological marketplace.

Order the above NIST publications from: Superintendent of Documents, Government Printing Office,

Washington, DC 20402.

Order the following NIST publications— FIPS and NISTIRs—from the National Technical Information

Service, Springfield, VA 22161.

Federal Information Processing Standards Publications (FIPS PUB) — Publications in this series

collectively constitute the Federal Information Processing Standards Register. The Register serves

as the official source of information in the Federal Government regarding standards issued by

NIST pursuant to the Federal Property and Administrative Services Act of 1949 as amended,

Public Law 89-306 (79 Stat. 1127), and as implemented by Executive Order 11717 (38 FR 12315,

dated May 11, 1973) and Part 6 of Title 15 CFR (Code of Federal Regulations).

NIST Interagency Reports (NISTIR)— A special series of interim or final reports on work

performed by NIST for outside sponsors (both government and non-government). In general,

initial distribution is handled by the sponsor; public distribution is by the National Technical

Information Service, Springfield, VA 22161, in paper copy or microfiche form.
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