# Patent

## Title
Operation scheme for programming charge trapping non-volatile memory

## Abstract

A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage to the control gate at one of a predetermined set of gate voltage levels selected in response to the determined data value. Programming parameters are controlled to establish a self-converging threshold state that is determined by the selected gate voltage. In this manner, the threshold voltage converges on a target threshold corresponding with the determined data value for the memory cell. Program verify operations are reduced or eliminated in various embodiments, reducing the overall time required for the program operation, and improving device performance. A second portion of the program operation can include verify operations to improve threshold margins across the array.

## Background
RELATED APPLICATIONS
The present application claims the benefit of U.S. Provisional Application No. 60/580,518, filed 17 Jun. 2004.
The present application is a continuation-in-part of U.S. patent application Ser. No. 10/765,292; entitled CIRCUIT AND METHOD FOR PROGRAMMING CHARGE STORAGE MEMORY CELLS; filed: 27 Jan. 2004 now U.S. Pat. No. 6,937,511; invented by Tzu-Hsuan Hsu and Chao-I Wu, and said application is incorporated by reference as if fully set forth herein.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to a programming operation for charge trapping memory.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
One basic technique used in many prior art devices to inject charge into the charge storage element is known as hot electron injection. Hot electron injection involves applying a high-voltage to a control gate on the memory cell, a high-voltage to the drain, and ground or a low-voltage to the source. This biasing arrangement causes current to flow in the channel, and hot electrons are injected from the channel into the charge storage element because of the electric field established by the high control gate voltage. A SONOS-type cell that is programmed using hot electron injection is referred to as an NROM cell herein.
There are many variations on biasing schemes used for hot electron injection. One basic problem being addressed by these variations arises because the memory cells in a large array do not all behave uniformly during a programming operation. Therefore, for a given program pulse, there is a wide distribution in the amount of charge injected into the charge storage elements of memory cells in the array on a single device. The wide distribution of charge after a program pulse makes it difficult to predict the threshold voltage of the memory cell. Accordingly, algorithms have risen which attempt to account for the distribution in charge, and typically involve applying a program pulse and then executing a verify operation to test the threshold of the memory cell after the pulse. If the threshold has not reached the target threshold after the first pulse, then the programming is retried, followed by another verify operation, and so on. A discussion of this issue is provided in Bloom et al., U.S. Pat. No. 6,396,741, entitled PROGRAMMING OF NONVOLATILE MEMORY CELLS, issued May 28, 2002. See also, Chang et al., U.S. Pat. No. 6,320,786, entitled METHOD OF CONTROLLING MULTI-STATE NROM, issued Nov. 20, 2001; and Parker, U.S. Pat. No. 6,219,276, entitled MULTILEVEL CELL PROGRAMMING, issued Apr. 17, 2001.
Some conventional program methods are based on algorithms which apply constant drain voltage, on algorithms which step the drain voltage during the program operation, and on algorithms which step the gate voltage during the program operation. These algorithms as applied to NROM however do not lead to convergence of the threshold voltage after many pulses, and require a verify operation to determine the end of the operation. The verify operation is time-consuming, and requires complex program algorithms and supporting circuitry. In floating gate flash memory, while some program algorithms may self-converge, the programming speed and accuracy can be improved.
It is desirable therefore to provide a programming algorithm for charge storage memory cells which is self-converging, eliminating or reducing the need for verify operations, and reducing the time required for the program operation. Furthermore, it is desirable to provide a programming algorithm which is self-converging at more than one target threshold level to allow multiple bit storage in a single memory cell.
SUMMARY OF THE INVENTION
The present invention provides a method for self-converging programming of a multiple-bit per cell, charge storage memory cell having a source and a drain in a substrate, a charge storage element and a control gate. In one embodiment, the method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage to the control gate at one of a predetermined set of gate voltage levels selected in response to the determined data value. Programming parameters are controlled to establish a self-converging threshold state that is determined by the selected gate voltage. In this manner, the threshold voltage converges on a target threshold corresponding with the determined data value for the memory cell. Program verify operations are reduced or eliminated in various embodiments, reducing the overall time required for the program operation, and improving device performance.
Embodiments of the method include:

    
    
        determining a data value from one of more than two data values to be stored in the memory cell;
        applying a gate voltage to the control gate relative to a reference voltage, a source voltage to the first terminal relative to the reference voltage, and a drain voltage to the second terminal relative to the reference voltage, in a program operation to induce charge transfer by hot electron injection to the charge storage element to establish a threshold voltage for the memory cell; and
        holding the gate voltage substantially constant at one of a predetermined set of gate voltages in response to the determined data value during a portion of the program operation in which the voltage threshold converges on a target threshold corresponding with the determined data value.
    
    


In yet other embodiments of the invention, the procedure for cells storing only two or storing more than two data values, includes applying a sequence of drain voltage pulses having pulse heights to the second terminal of the memory cell during the program operation, the sequence of drain voltage pulses including a first set of pulses applied during said portion of the program operation, without verify operations between the pulses, and a second set of pulses applied during a second portion of the program operation, and including applying verify pulses between at least two successive pulses in the second set of pulses.
In charge trapping memory cell technologies, like SONOS-type cells, multilevel data can be stored in each side of the cell, in embodiments of the present invention.
The present invention is also embodied by an integrated circuit memory that comprises a memory array including decoding circuitry to select memory cells for programming. The integrated circuit includes a voltage supply circuit coupled to the memory array and adapted to apply a gate voltage, a source voltage and a drain voltage to the control gate, source and drain respectively of memory cells in the array. A program controller is coupled to the decoding circuit and to the voltage supply circuit. The program controller is adapted to execute program operations as described above.
The invention is applicable to charge storage memory cells programmed by hot electron injection, including NROM cells in which charge is trapped in a charge trapping layer formed of silicon nitride, or other material, and floating gate flash memory cells in which charge is trapped in a conductive floating gate formed of polysilicon.
Implementations of the present invention require fewer program pulses and shorter programming times than prior art approaches. Also, over-programming is avoided because of the self-convergence of the threshold. The level of the self-converged threshold voltage can be well-controlled according to implementations of the present invention, allowing for realizations of multiple memory states in charge storage memory cells. According to embodiments of the invention, the target threshold can be selected by setting the gate voltage to a level corresponding with the data values to be stored, while reducing the times required for verify operations.
Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified diagram of an NROM memory cell with program pulse voltages according to an embodiment of the present invention.
FIG. 2 is a simplified diagram of an integrated circuit memory device based on NROM memory cells with a self-convergence programming algorithm according to an embodiment of the present invention.
FIG. 3 illustrates voltages applied during a programming operation according to an embodiment of the present invention with two bits per cell.
FIG. 4 is a graph of the threshold voltage versus programming time, showing results for the programming operation illustrated in FIG. 3.
FIG. 5 illustrates voltages applied during a programming operation according to an embodiment of the present invention with three bits per cell.
FIG. 6 is a graph of the threshold voltage versus programming time, showing results for the programming operation illustrated in FIG. 6.
FIG. 7 illustrates voltages applied during a programming operation according to an embodiment of the present invention, including a first portion without verify operations and a second portion with verify operations.
FIG. 8 is a graph of the threshold voltage versus programming time, showing results for the programming operation illustrated in FIG. 7.
FIG. 9 is a simplified flowchart for a programming algorithm according to embodiments of the present invention.
FIG. 10 is a simplified flowchart for a programming algorithm according to embodiments of the present invention, with programming and verify pulses after a first self-converging portion of the operation.



DETAILED DESCRIPTION
A detailed description of embodiments of the present invention is provided with reference to FIGS. 1–10.
FIG. 1 is a simplified diagram of an NROM memory cell suitable for use in embodiments of the present invention. The memory cell is implemented in a semiconductor substrate 100. The cell includes a source 101 and a drain 102 formed by respective diffusion regions, separated by a channel in the substrate 100. A control gate 103 overlies the channel. A charge storage element, such as charge trapping layer 104, is isolated by an insulator 106 such as silicon dioxide or silicon oxynitride between the charge trapping layer 104 and the control gate 103 and an insulator, such as gate dielectric 105 comprising silicon dioxide or silicon oxynitride between the charge trapping layer 104 and the channel. The charge trapping layer 104 comprises silicon nitride or silicon oxynitride in typical NROM cells. In other embodiments, other charge trapping material, such as Al2O3, HfOx, ZrOx, or other metal oxide can be used to form memory cells. Charge symbolized by electrons “e” is trapped in the nitride layer, when the cell is biased for hot electron programming.
In order to program the memory cell by hot electron injection, control circuitry on the integrated circuit applies a source voltage VS to the source 101 (such as ground potential), a drain voltage VD to the drain 102 (a sequence of pulses increasing incrementally or a constant voltage), a gate voltage VG to the control gate 103 (a constant voltage in the example shown set at a level which corresponds to a self-convergent threshold voltage corresponding with one of more than two data values for a multibit cell), and a substrate voltage VB to the substrate 100. The bias arrangement results in hot electron injection, caused by current flowing in the channel which supplies hot electrons to be injected through the gate dielectric 105 near the drain, and which converges on a threshold, as explained in more detail below.
FIG. 2 is a simplified block diagram of an integrated circuit including a memory array 200 implemented using NROM memory cells with self-converging program operations implemented by a state machine. Other embodiments use memory cells with charge storage elements other than a silicon nitride charge trapping layer, as used in a typical NROM cell, such as conductive floating gates as used in typical flash memory cells, and charge trapping layers comprising materials other than nitride. A row decoder 201, responsive to addresses on bus 205, is coupled to a plurality of word lines 202 arranged along rows in the memory array 200. A column decoder 203, responsive to addresses on line 205, is coupled to a plurality of bit lines 204 arranged along columns in the memory array 200. Addresses are supplied on bus 205 to column decoder 203 and row decoder 201. Sense amplifiers are provided in block 206, and coupled to the column decoder 203 via data bus 207. Data is supplied via the data-in line 211 from input/output ports on the integrated circuit to the data-in structures (not shown). Data is supplied via the data-out line 212 from the sense amplifiers in block 206 to input/output ports on the integrated circuit.
In some embodiments, resources for controlling the reading, programming and erasing of memory cells in the array 200 are included on the chip. According to embodiments of the present invention, a self-converging program operation is implemented. These resources include read/erase/program supply voltage sources represented by block 208, and the state machine 209, which are coupled to the array 200, the decoders 201, 203 and other circuitry on the integrated circuit, which participate in operation of the device.
The supply voltage sources 208 are implemented in various embodiments using charge pumps, voltage regulators, voltage dividers and the like as known in the art, for supplying various voltage levels, including negative voltages, used in the read, erase and program operations.
The state machine 209 supports read, erase and program operations. The state machine 209 can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the state machine. The program operation of the present invention, which is self-converging in some embodiments, is described with reference to FIGS. 3–10.
FIG. 3 illustrates the applied gate and drain voltages for a programming operation for an NROM cell as shown in FIG. 1, according to one embodiment of the invention. The programming operation is designed to establish a target threshold voltage in the memory cell by injecting charge into the charge trapping layer 104. The programming operation includes applying a source voltage VS such as ground or another reference potential, to the source of a selected memory cell, a drain voltage VD to the drain of a selected memory cell as shown on trace 301, a gate voltage VG to the control gate of a selected memory cell which is selected from one of the predetermined gate voltages that correspond with a data value to be stored in the cell, as shown on traces 302–304, and a substrate bias VB such as ground or another reference voltage. As can be seen in FIG. 3, the programming operation includes applying a sequence of drain pulses having pulse heights, where the pulse heights are substantially constant at about 5 volts, for example, during the operation. The gate voltage VG is held substantially constant at a selected level, which correlates with the target threshold voltage. As illustrated, a gate voltage on trace 302 of about 8 volts corresponds with a data value of <10>, and a target threshold of about 2.5 volts. A gate voltage at the level of trace 303 of about 10 volts corresponds with a data value of <01>, and a target threshold of about 3.1 volts. A gate voltage on trace 304 of about 12 volts corresponds with a data value of <00>, and a target threshold of about 3.7 volts. The <11> data value is represented by the erased lowest threshold state, which is achieved using hot hole injection or other processes that add positive charge or remove negative charge from the charge trapping structure. In the particular example shown in FIG. 3, the drain voltage VD is applied in a sequence of about ten pulses about 1.0 microsecond long with constant pulse height of about 5 volts. Of course other pulse widths and pulse heights can be utilized as suits a particular embodiment.
The pulses may be applied with intervals of zero voltage between the pulses. In self-converging program algorithms according to the present invention, in which no verify step is executed, the number of pulses (or amount of program time) is predetermined at a count that can be empirically determined to establish the target threshold voltage reliably across the memory array. As demonstrated by the experimental results described below, self-convergence can be achieved in a relatively small amount of time, so that on the order of 10 microseconds of program time (about 10 pulses) may be needed in various embodiments of the invention.
FIG. 4 shows threshold voltage versus programming time for the program algorithm explained with reference to FIG. 3. The reverse read threshold for the VD constant, VG at level 302 near 8 volts algorithm is seen to converge on the target threshold shown at level 400. The reverse read threshold for the VD constant, VG at the level 303 near 10 volts algorithm is seen to converge on the target threshold shown at level 401. The reverse read threshold for the VD constant, VG at the level of trace 304 near 12 volts algorithm is seen to converge on the target threshold shown at level 402. The reverse read threshold for the VD constant, VG at level near 14 volts (not illustrated in FIG. 3) is seen to converge on the target threshold shown at level 403.
FIG. 5 illustrates the applied gate and drain voltages for a programming operation for an NROM cell as shown in FIG. 1, according to an embodiment of the invention storing three bits per cell, and using a stepped drain voltage. The programming operation is designed to establish a target threshold voltage in the memory cell by injecting charge into the charge trapping layer 104. The programming operation includes applying a source voltage VS such as ground or another reference potential, to the source of a selected memory cell, a drain voltage VD to the drain of a selected memory cell as shown on trace 501, a gate voltage VG to the control gate of a selected memory cell which is selected from one of the predetermined gate voltages that correspond with a data value to be stored in the cell, as shown on traces 502–508, and a substrate bias VB such as ground or another reference voltage. As can be seen in FIG. 5, the programming operation includes applying a sequence of drain pulses having pulse heights, where the pulse heights increase from about 7 volts to about 9 volts, for example, during the operation. The gate voltage VG is held substantially constant at a selected level, which correlates with the target threshold voltage.
FIG. 6 shows threshold voltage versus programming time for the program algorithm explained with reference to FIG. 5. As illustrated, a gate voltage on trace 502 of about 6 volts corresponds with a data value of <110>, and a target threshold level 600 of about 1.4 volts. A gate voltage on trace 503 of about 8 volts corresponds with a data value of <101>, and a target threshold level 601 of about 2.2 volts. A gate voltage on trace 504 of about 10 volts corresponds with a data value of <100>, and a target threshold level 602 of about 3.1 volts. A gate voltage on trace 505 of about 12 volts corresponds with a data value of <011>, and a target threshold level 603 of about 4.0 volts. A gate voltage on trace 506 of about 14 volts corresponds with a data value of <010>, and a target threshold level 604 of about 4.8 volts. A gate voltage on trace 507 of about 16 volts corresponds with a data value of <001>, and a target threshold level 605 of about 5.6 volts. A gate voltage on trace 508 of about 18 volts corresponds with a data value of <000>, and a target threshold level 606 of about 6.3 volts. The results of applying a gate voltage of about 20 volts is shown as well, converging on a target threshold level 607 of about 8.0 volts. The <111> data value is represented by the erased, lowest threshold state, providing 8 threshold levels corresponding to the 8 data values stored for 3 bits of data. In the particular example shown in FIG. 3, the drain voltage VD is applied in a sequence of about ten pulses about 1.0 microsecond long, with increasing amplitude of 0.2 volts per step, increasing from about 7 volts to about 9 volts. Of course other pulse widths and pulse heights can be utilized as suits a particular embodiment.
In the embodiments shown in FIGS. 3 and 5, there are no program verify operations between the program pulses. Rather, a predetermined number of pulses is applied, and because of the self-converging nature of the program operation, the algorithm is finished after that number of pulses is applied. A verify step can be applied at the end of the pulse sequence to ensure that the cell did not fail.
In alternative algorithms, a second portion of the program operation can be applied after a self-converging set of pulses, as shown in FIGS. 3 and 5. The second portion includes verify steps to provide better control over cell variations. An example operation with a first portion without verify and a second portion with verify is shown in FIG. 7. The programming operation shown in FIG. 7 includes a first portion 710 executed first in time that includes applying a source voltage VS such as ground or another reference potential, to the source of a selected memory cell, a drain voltage VD to the drain of a selected memory cell as shown on trace 701, a gate voltage VG to the control gate of a selected memory cell which is selected from one of the predetermined gate voltages that correspond with a data value to be stored in the cell, as shown on trace 702, and a substrate bias VB such as ground or another reference voltage. As can be seen in FIG. 7, the first portion 710 of the programming operation includes applying a sequence of drain pulses having pulse heights, where the pulse heights are substantially constant at about 5 volts, for example, during the operation. The gate voltage VG is held substantially constant at a selected level, which correlates with the target threshold voltage at a first target level 712 slightly less than the target program verify threshold. In the second portion 711 of the program operation, the gate voltage is set to a second target level 713 corresponding with the target program verify level, supporting a verify operation, then a gate voltage pulse 714 is applied in parallel with the next drain voltage pulse. Then the gate voltage is set to the verify level 715, and a gate voltage pulse 716 is applied in parallel with the next drain voltage pulse. The process continues until a successful verify, or until a maximum number of retries.
FIG. 8 shows threshold voltage versus programming time for the two portions of the program algorithm explained with reference to FIG. 7. In the first portion 711, the read threshold converges on a first target level 801, that corresponds with the data value to be stored. In the second portion of the program operation, the read threshold increases to the final target threshold 802. The first portion proceeds rapidly, because there are no verify operations. The second portion converges rapidly because a small change in threshold is need, and includes verify operations that improve threshold margins across the array. The programming bias arrangement during the second portion need not be a self converging arrangement, but can be adapted for fast closure on the target threshold, including, but not limited to, constant gate voltage with constant drain voltage, constant gate voltage with stepped drain voltage, stepped gate voltage with constant drain voltage, and a combination of gate voltage stepping with drain voltage stepping.
FIGS. 9 and 10 illustrate basic program operations implementing techniques described above. In FIG. 9, the process begins with a program command to store a particular data value in a selected memory cell (block 900). The gate voltage for the selected cell is set to a voltage level in response to the particular data value (block 901). Then, the self-converging program pulse sequence, as illustrated in FIG. 3 or FIG. 5, is executed, including applying a program pulse (block 902), determining whether the predetermined pulse count has been reached (block 903). If at block 903, the pulse count has not been reached, then the algorithm loops back to block 902 to apply a next pulse. If at block 903, the predetermined pulse count has been reached, then the sequence of programming pulses is completed. A verify operation is executed (block 904) in this example after the sequence of pulses for the program operation is complete. If the cell successfully verifies, then the program operation is completed (block 905). If at block 904, the verify operation fails, then the program operation fails (block 906). After a failed program operation, the sequence can be retried, or a true failure can be indicated, depending on the particular implementation.
FIG. 10 illustrates the program operation described above with reference to FIG. 7. In FIG. 10, the process begins with a program command to store a particular data value in a selected memory cell (block 910). The gate voltage for the selected cell is set to a voltage level in response to the particular data value (block 911). Then, the first portion of the self converging program pulse sequence, as illustrated in FIG. 7, is executed, including applying a program pulse (block 912), determining whether the predetermined pulse count has been reached (block 913). If at block 913, the pulse count has not been reached, then the algorithm loops back to block 912 to apply a next pulse. If at block 913, the predetermined pulse count has been reached, then the set of pulses, without verify, for the first portion of the program operation is completed. Next, in this example, a verify operation is executed (block 914). If the cell successfully verifies, then the program operation is completed (block 915). If at block 914, the verify did not succeed, then a program pulse for the second portion of the program operation is applied (block 916). Next, it is determined whether the maximum number of retry pulses has been applied at block 917. If not, then the algorithm loops back to block 914 to perform a verify operation. If at block 917, the maximum count has been reached, then a true failure is indicated (block 918).
As described herein, improved programming speed and reliability can be achieved by controlling the programming parameters including drain voltage, source voltage, pulse width and programming time under a fixed gate voltage to achieve a self-saturated read threshold VT. The gate voltage is selected according to the data value to be stored, to define the multiple saturated threshold states for multiple level cell applications. In some embodiments, a program-verify level is set that is higher than the saturated threshold state, so that no verify operation is required during the programming sequence. Also, using a self-saturated programming operation including two steps can be applied, including a first portion without verify, and a second portion with verify. According to the two-step operation, during a first portion of the program sequence without verify, the target threshold state is achieved which is less than the program verify level that corresponds with the target data value. During a second portion, program pulses are applied with a program verify step to reduce the threshold voltage to improve the distribution of thresholds in the array.
For NROM, NROM-type and floating gate flash memory, self-saturated read thresholds are predetermined, fixed gate voltages, while controlling the other programming parameters. The threshold level and of the voltage margin around a threshold level for multilevel operation can be controlled by adjusting the gate voltage. Program verify time can be eliminated or reduced in the programming operation to improve device performance. Also, the two-step programming method is provided, where the first step is executed without verify, and the second step is executed with verify, reducing the time required for program verify while allowing precision control of the threshold voltage distribution.
The present invention provides a high speed, self-converging algorithm for programming NROM and related non-volatile memory based on charge storage structures. The algorithm is applicable as well to floating gate flash memory cells.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

## Claims

1. A method for programming a multi-level charge storage memory cell having a first terminal and a second terminal acting as a source and a drain in a substrate, a charge storage element, and a control gate, comprising:
determining a data value from one of more than two data values to be stored in the memory cell;
applying a gate voltage to the control gate relative to a reference voltage, a source voltage to the first terminal relative to the reference voltage, and a drain voltage to the second terminal relative to the reference voltage, in a program operation to induce charge transfer by hot electron injection to the charge storage element to establish a threshold voltage for the memory cell; and
holding the gate voltage substantially constant at one of a predetermined set of gate voltages in response to the determined data value during a portion of the program operation in which the voltage threshold converges on a target threshold corresponding with the determined data value.

2. The method of claim 1, wherein the operation is self-converging during a portion of the program operation in which the voltage threshold converges on an ending threshold.

3. The method of claim 1, wherein the applying includes applying a sequence of drain voltage pulses having pulse heights to the second terminal of the memory cell during said portion of the program operation and increasing the pulse heights of the drain voltage pulses in at least two successive pulses in the sequence.

4. The method of claim 1, wherein the applying includes applying a sequence of drain voltage pulses having pulse heights to the second terminal of the memory cell during the program operation, the sequence of drain voltage pulses including a first set of pulses applied during said portion of the program operation, without verify operations between the pulses, and a second set of pulses applied during a second portion of the program operation, and including applying verify pulses between at least two successive pulses in the second set of pulses.

5. The method of claim 1, including coupling the substrate to the reference voltage during the operation.

6. The method of claim 1, wherein said charge storage element in the memory cell comprises a non-conductive charge trap.

7. The method of claim 1, wherein said charge storage element in the memory cell comprises a conductive floating gate.

8. The method of claim 1, wherein said memory cell comprises an NROM cell.

9. The method of claim 1, wherein said memory cell comprises a flash memory cell.

10. An integrated circuit, comprising:
a memory array including decoding circuitry to select memory cells for programming, the memory cells having first and second terminals in a substrate acting as sources and drains, a charge storage element, and a control gate, wherein the memory cell is adapted to store more than two data values;
a voltage supply circuit coupled to the memory array adapted to apply a gate voltage, a source voltage and a drain voltage to the control gate, first terminal and second terminal, respectively, of memory cells in the array; and
a program controller coupled to the decoding circuitry and to the voltage supply circuit, the program controller adapted to execute a self-converging program operation for a selected memory cell to induce charge transfer by hot electron injection to the charge storage element and establish one of a set of threshold voltages corresponding with a respective one of the more than two data values in the selected memory cell, the program operation including
determining a data value from one of more than two data values to be stored in the memory cell;
applying a gate voltage to the control gate relative to a reference voltage, a source voltage to the first terminal relative to the reference voltage, and a drain voltage to the second terminal relative to the reference voltage, in a program operation to induce charge transfer by hot electron injection to the charge storage element to establish a threshold voltage for the memory cell; and
holding the gate voltage substantially constant at one of a predetermined set of gate voltages in response to the determined data value during a portion of the program operation in which the voltage threshold converges on a target threshold corresponding with the determined data value.

11. The integrated circuit of claim 10, wherein the applying includes applying a sequence of drain voltage pulses having pulse heights to the second terminal of the memory cell during said portion of the program operation and increasing the pulse heights of the drain voltage pulses in at least two successive pulses in the sequence.

12. The integrated circuit of claim 10, wherein the applying includes applying a sequence of drain voltage pulses having pulse heights to the second terminal of the memory cell during the program operation, the sequence of drain voltage pulses including a first set of pulses applied during said portion of the program operation, without verify operations between the pulses, and a second set of pulses applied during a second portion of the program operation, and including applying verify pulses between at least two successive pulses in the second set of pulses.

13. The integrated circuit of claim 10, including holding the gate voltage substantially constant during said portion of the program operation.

14. The integrated circuit of claim 10, wherein the substrate is coupled to the reference voltage during the operation.

15. The integrated circuit of claim 10, wherein said charge storage element in the memory cell comprises a non-conductive charge trap.

16. The integrated circuit of claim 10, wherein said charge storage element in the memory cell comprises a conductive floating gate.

17. The integrated circuit of claim 10, wherein said memory cell comprises an NROM cell.

18. The integrated circuit of claim 10, wherein said memory cell comprises a flash memory cell.