# Patent

## Title
Apparatus and method of controlling single-input-multi-output systems

## Abstract

An apparatus and method is disclosed for automatically controlling single-input-multi-output (SIMO) systems or processes. The control output signals of a plurality of single-input-single-output (SISO) automatic controllers are combined by a combined output setter so that these SISO controllers are converted to a multi-input-single-output (MISO) automatic controller based on certain criteria; and its resulting controller output signal is able to manipulate only one actuator to control a plurality of continuous process variables or attempt to minimize a plurality of error signals between the setpoints and their corresponding process variables. Without the need of building process mathematical models, this inventive apparatus and method is useful for automatically controlling unevenly paired multivariable systems or processes where there are less system inputs than outputs including but not limited to industrial furnaces, rapid thermal processing (RTP) chambers, chemical mechanical planarization (CMP) systems, and distillation columns.

## Background
The subject of this patent relates to automatic control of single-input-multi-output (SIMO) systems including industrial processes, equipment, facilities, buildings, homes, devices, engines, robots, vehicles, aircraft, space-vehicles, appliances and other systems, and more particularly to a method and apparatus for automatically controlling two or more continuous process variables by manipulating only one actuator.
In control system applications, it is relatively easy to control single-input-single-output (SISO) systems or multi-input-multi-output (MIMO) systems that have the same amount of manipulated variables as system inputs and controlled process variables as system outputs. In practice, we often have to deal with unevenly paired multivariable systems, where the number of manipulated variables is greater or smaller than the controlled process variables. Depending on the number of system inputs and outputs, we categorize them as multi-input-single-output (MISO) systems and single-input-multi-output (SIMO) systems. These systems are much more difficult to control using conventional control methods.
In U.S. patent application No. 60/474,688, we presented a method and apparatus for controlling MISO systems. In this patent, we introduce a method and apparatus for controlling SIMO systems.
Single-input-multi-output (SIMO) systems are found in situations where one manipulated variable affects 2 or more process variables that need to be controlled. In these cases, there are no other manipulated variables that we can use to form several single-input-single-output (SISO) systems or one evenly paired multi-input-multi-output (MIMO) system. For instance,

    
    
        An industrial furnace for glass melting or metal reheating typically has multiple temperature zones that need to be controlled. The number of fuel flows manipulated by control valves is typically less than the total number of temperature zones measured. In this case, we may have to design the control system to include one evenly paired MIMO system and one or more 1-input-2-output (1×2) systems.
        A Rapid Thermal Processing (RTP) chamber for semiconductor wafer treatment or space material testing has many temperature zones to control. The temperature setpoints can ramp up from room temperature to a few thousand degrees Fahrenheit within 30 seconds and then ramp down. The control objective is to force each temperature point to tightly track its setpoint trajectory. However, since the number of lamps used to heat the chamber may be less than the number of temperature zones to be controlled, we are facing an unevenly paired multivariable system.
        A Chemical Mechanical Planarization (CMP) system for semiconductor wafer planarization applies pressure to the polishing pad to control the thickness of the thin film deposited on the wafer. The number of pressure actuators is typically less than the number of measured thickness points. When the wafer size increases from 200 mm to 300 mm and higher, this problem becomes more severe since the measured thickness points will increase dramatically. We then have to deal with a large number of SIMO systems to control one CMP system.
        A distillation column used for separating a liquid or vapor mixture into component fractions of desired purity has many process variables. A reboiler brings the liquid at the bottom to the boiling point where the component with a lower boiling point will evaporate. Plates inside the column shell enhance the separation. The reboiler steam flow is usually the appropriate manipulated variable to use to control the bottom temperature as well as the temperature of multiple plates. In this case, we have to control a 1×2 or 1×M system.
    
    


Theoretically, a 1×M system with 1 input and M outputs, where M=2, 3, . . . is not controllable since manipulating only one input variable in its range cannot force its M output variables to move to any point within their ranges. In practice, a typical approach is to control the most important process variable and leave the other variables uncontrolled. In the distillation column example, the bottom temperature may be controlled but the plate temperatures are only monitored or loosely controlled by manipulating the reflux. In this patent, we introduce the method and apparatus to control single-input-multi-output (SIMO) systems.



In the accompanying drawing:
FIG. 1 is a block diagram illustrating a 2-input-1-output (2×1) Model-Free Adaptive (MFA) controller that controls a 1-input-2-output (1×2) system.
FIG. 2 is a block diagram illustrating the architecture of a 2-input-1-output (2×1) Model-Free Adaptive (MFA) controller.
FIG. 3 is a block diagram illustrating the simplified architecture of a 2-input-1-output (2×1) Feedback/Feedforward Model-Free Adaptive (MFA) controller.
FIG. 4 is a drawing illustrating a mechanism of a Combined Output Setter that combines 2 controller outputs into one controller output.
FIG. 5 is a block diagram illustrating a 3-input-1-output (3×1) Model-Free Adaptive (MFA) controller that controls a 1-input-3-output (1×3) system.
FIG. 6 is a block diagram illustrating the simplified architecture of a 3-input-1-output (3×1) Model-Free Adaptive (MFA) controller.
FIG. 7 is a block diagram illustrating the simplified architecture of a 3-input-1-output (3×1) Feedback/Feedforward Model-Free Adaptive (MFA) controller.
FIG. 8 is a drawing illustrating a mechanism of a Combined Output Setter that combines 3 controller outputs into one controller output.
FIG. 9 is a block diagram illustrating an M-input-1-output (M×1) Model-Free Adaptive (MFA) controller that controls a 1-input-M-output (1×M) system.
FIG. 10 is a block diagram illustrating the simplified architecture of an M-input-1-output (M×1) Model-Free Adaptive (MFA) controller.
FIG. 11 is a block diagram illustrating the simplified architecture of an M-input-1-output (M×1) Feedback/Feedforward Model-Free Adaptive (MFA) controller.
FIG. 12 is a drawing illustrating a mechanism of a Combined Output Setter that combines M controller outputs into one controller output.
FIG. 13 is a block diagram illustrating a 2-input-1-output (2×1) proportional-integral-derivative (PID) controller that controls a 1-input-2-output (1×2) system.
FIG. 14 is a block diagram illustrating an M-input-1-output (M×1) proportional-integral-derivative (PID) controller that controls a 1-input-M-output (1×M) system.
FIG. 15 is a block diagram illustrating a multi-input-single-output (MISO) controller that controls a single-input-multi-output (SIMO) system.



The term “mechanism” is used herein to represent hardware, software, or any combination thereof. The term “process” is used herein to represent a physical system or process with inputs and outputs that have dynamic relationships.
DESCRIPTION
A. 2-Input-1-Output Model-Free Adaptive (MFA) Controller
FIG. 1 illustrates a 2-input-1-output (2×1) MFA controller that controls a 1-input-2-output (1×2) system. The control system comprises a 2-input-1-output (2×1) MFA controller 8, a 1-input-2-output (1×2) system 10, and signal adders 11, 12, 13, and 14. The signals shown in FIG. 1 are as follows:
r1(t), r2(t)—Setpoint 1 and Setpoint 2.
x1(t), x2(t)—System outputs of the 1×2 system.
d1(t), d2(t)—Disturbance 1 and 2 caused by noise or load changes.
y1(t), y2(t)—Measured process variables of the 1×2 system,

y1(t)=x1(t)+d1(t); and y2(t)=x2(t)+d2(t).

e1(t), e2(t)—Error between the setpoint and measured process variable,

e1(t)×r1(t)−y1(t); and e2(t)=r2(t)−y2(t).

u(t)—Output of the 2×1 MFA Controller.
The control objective is for the controller to produce output u(t) to manipulate the manipulated variable so that the measured process variables y1(t) and y2(t) track the given trajectory of their setpoints r1(t) and r2(t), respectively, under variations of setpoint, disturbance, and process dynamics. In other words, the task of the MFA controller is to minimize the error e1(t) and e2(t) in an online fashion.
Since there is only one manipulated variable, minimizing errors for both loops may not be possible. The control objective then can be defined as (i) to minimize the error for the more critical loop of the two, or (ii) to minimize the error for both loops with no weighting on the importance so that there may be static errors in both loops.
We select the objective function for the MFA control system as




  
    
      
        
          
            
              
                
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The minimization of E1s(t) and E2s(t) is achieved by (i) the regulatory control capability of the MFA controller, whose output u(t) manipulates the manipulated variable forcing the process variables y1(t) and y2(t) to track the given trajectory of their setpoints r1(t) and r2(t), respectively; and (ii) the adjustment of the MFA controller weighting factors that allow the controller to deal with the dynamic changes, large disturbances, and other uncertainties of the control system.
FIG. 2 illustrates the architecture of a 2-input-1-output Model-Free Adaptive (MFA) controller. Two multilayer neural networks 17, 18 are used in the design of the controller. Each neural network has one input layer 19, 20, one hidden layer 21, 22 with N neurons, and one output layer 23, 24 with one neuron.
Since both neural networks in each controller are identical, we will drop the subscript in the following equations to simplify. The input signal e(t) to the input layer 19, 20 is first converted to a normalized error signal E1 with a range of −1 to 1 by using the normalization unit 25, 26, where N(·) denotes a normalization function. The output of the normalization unit 25, 26 is then scaled by a scaling function L(·) 15, 16:




  
    
      
        
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The value of E1 at time t is computed with function L(·) and N(·):





  
    
      
        
          
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where Kc>0 is defined as controller gain and Tc is the user selected process time constant. Kc is used to compensate for the process steady-state gain and Tc provides information for the dynamic behavior of the process. When the error signal is scaled with these parameters, the controller's behavior can be manipulated by adjusting the parameters.

The E1 signal then goes iteratively through a series of delay units 27, 28, where z−1 denotes the unit delay operator. A set of normalized and scaled error signals E2 to EN is then generated. In this way, a continuous signal e(t) is converted to a series of discrete signals, which are used as the inputs to the neural network. These delayed error signals Ei, i=1, 2, . . . N, are then conveyed to the hidden layer through the neural network connections. This is equivalent to adding a feedback structure to the neural network. Then the regular static multilayer neural network becomes a dynamic neural network.
A Model-Free Adaptive controller uses a dynamic block such as a dynamic neural network. A dynamic block is just another name for a dynamic system, whose inputs and outputs have dynamic relationships.
Each input signal can be conveyed separately to each of the neurons in the hidden layer 21, 22 via a path weighted by an individual weighting factor wij, where i=1, 2, . . . N, and j=1, 2, . . . N. The inputs to each of the neurons in the hidden layer are summed by adder 29, 30 to produce signal pj. Then the signal pj is filtered by an activation function 31, 32 to produce qj, where j denotes the jth neuron in the hidden layer.
A piecewise continuous linear function ƒ(x) mapping real numbers to [0,1] is used as the activation function in the neural network as defined by




  
    
      
        
          
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where a is an arbitrary constant and b=1/2.

Each output signal from the hidden layer is conveyed to the single neuron in the output layer 23, 24 via a path weighted by an individual weighting factor hj, where j=1,2, . . . N. These signals are summed in adder 33, 34 to produce signal z(·), and then filtered by activation function 35, 36 to produce the output o(·) of the neural network 17, 18 with a range of 0 to 1.
A de-normalization function 37, 38 defined by

D(x)=100x,  (5)

maps the o(·) signal back into the real space to produce the controller signal v(t).

The algorithm governing the input-output of the controller is seen by the following difference equations:




  
    
      
        
          
            
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where the variable of function ƒ(·) is in the range specified in Equation (4b), and o(n) is bounded by the limits specified in Equations (4a) and (4c). The controller signal v(t) becomes





  
    
      
        
          
            
              
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where n denotes the nth iteration; o(t) is the continuous function of o(n); D(·) is the de-normalization function; and Kc(·)>0, the controller gain 41, 42, is a parameter used to adjust the magnitude of the controller. This is the same parameter as in the scaling function L(·) 15, 16 and is useful to fine tune the controller performance or keep the system stable.

An online learning algorithm as described in U.S. Pat. No. 6,556,980 B1 is an example of one algorithm that can be used to continuously update the values of the weighting factors of the MFA controller as follows:

Δwij(n)=a2ηe(n)Ei(n)hj(n),  (10)

Δhj(n)=aηe(n)qj(n).  (11)

The equations (1) through (11) work for both process direct-acting or reverse acting types. Direct-acting means that an increase in the process input will cause its output to increase, and vice versa. Reverse-acting means that an increase in the process input will cause its output to decrease, and vice versa. To keep the above equations working for both direct and reverse acting cases, e(t) is calculated differently based on the acting type of the process as follows:

e(t)=r(t)−y(t), if direct acting  (12a)

e(t)=−[r(t)−y(t)]. if reverse acting  (12b)

This is a general treatment for the process acting types. It applies to all Model-Free Adaptive controllers to be introduced below.
We can consider that there are two single-input-single-output (SISO) MFA controllers 44 and 46 in this design with input signals e1(t) and e2(t), and output signals v1(t) and v2(t). Then the Combined Output Setter 48 can be used to combine the signals v1(t) and v2(t) to produce the controller output u(t).
FIG. 3 is a block diagram illustrating the simplified architecture of a 2-input-1-output (2×1) Feedback/Feedforward Model-Free Adaptive (MFA) controller. The 2×1 Feedback/Feedforward MFA controller 58 comprises two SISO MFA controllers 50, 51, two Feedforward MFA controllers 52, 53, two signal adders 54, 55, and one Combined Output Setter 56.
The compensation-type Feedforward MFA controller described in the U.S. Pat. No. 6,556,980 B1 is an example of how a Feedforward MFA controller is designed. Due to the adaptive capability of the feedback MFA controller, we can design a Feedforward MFA controller with a first-order dynamic block as follows:




  
    
      
        
          
            
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where D(S) and Yf(S) are the Laplace transform of signals d(t) and yf(t), the input and output signals of the Feedforward controller, respectively, Gfs(S) is the Laplace transfer function of the Feedforward controller, Kcf is the feedforward gain, Tcf is the feedforward time constant, and Ksf is the feedforward sign factor. We can select the constants Kcf, Tcf, and Ksf based on the basic understanding of the process. The system can also be fine tuned by adjusting these constants.

The control signals u1(t) and u2(t) are calculated based on the following formulas:

u1(t)=ν1(t)+νƒ1(t),  (14a)

u2(t)=ν2(t)+νƒ2(t),  (14b)

where ν1(t) and ν2(t) are the feedback MFA controller outputs and νƒ1(t) and νƒ2(t) are the Feedforward MFA controller outputs. There may be cases where there is only one active feedforward controller. If FFC1 is inactive, νƒ1(t)=0 and then u1(t)=ν1(t). If FFC2 is inactive, νƒ2(t)=0 and then u2(t)=ν2(t).

FIG. 4 is a drawing illustrating a mechanism of a Combined Output Setter that can combine 2 controller outputs u1(t) and u2(t) into one controller output u(t). By moving the knob R 60, we can adjust the amount of control signals u1(t) and u2(t) to be contributed to the actual controller output u(t), which can be calculated based on the following formula:

u(t)=Ru1(t)+(1−R)u2(t),  (15)

where 0≦u(t)≦100; 0≦R≦1; and R is a constant.

Here we introduce an alternative mechanism for the Combined Output Setter based on the controller gains. The formula to combine multiple controller outputs into one output using controller gains follows:




  
    
      
        
          
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where Kc1, and Kc2 are MFA controller gains for SISO MFA 1 and SISO MFA 2, respectively. This allows the 2×1 MFA controller to dynamically tighten the more important loop of the two. We can easily set a higher controller gain for the more important loop to minimize its error as the highest priority and allow the other loop to be relatively in loose control. On the other hand, we can also easily set both controller gains at an equal value so that both loops are treated with equal importance.

Both mechanisms represented in Equations (15) and (16) can be used as the Combined Output Setter 48 and 56 in FIG. 2 and FIG. 3, respectively.
To expand the design, we can rescale the control output signal u(t) from its 0% to 100% range to an engineering value range by using a linear function. In addition, control limits and constraints can be applied to these signals for safety or other reasons to limit the control actions. These design concepts can be readily applied to all the controllers presented in this patent.
B. 3-Input-1-Output Model-Free Adaptive Controller
FIG. 5 illustrates a 3-input-1-output (3×1) MFA controller that controls a 1-input-3-output (1×3) system. The control system comprises a 3-input-1-output (3×1) MFA controller 62, a 1-input-3-output (1×3) system 64, and signal adders 65, 66, 67, 68, 69, and 70. The signals shown in FIG. 5 are as follows:
r1(t), r2(t), r3(t)—Setpoint 1, 2 and 3.
x1(t), x2(t), x3(t)—System outputs of the 1×3 system.
d1(t), d2(t), d3(t)—Disturbance 1, 2, and 3 caused by noise or load changes.
y1(t), y2(t), y3(t)—Measured process variables of the 1×3 system,

y1(t)=x1(t)+d1(t); y2(t)=x2(t)+d2(t); and y3(t)=x3(t)+d3(t).

e1(t), e2(t), e3(t)—Error between the setpoint and measured process variable,

e1(t)=r1(t)−y1(t); e2(t)=r2(t)−y2(t); and e3(t)=r3(t)−y3(t).

u(t)—Output of the 3×1 MFA Controller.
The control objective is for the controller to produce output u(t) to manipulate the manipulated variable so that the measured process variables y1(t), y2(t), and y3(t) track the given trajectory of their setpoints r1(t), r2(t), and r3(t), respectively, under variations of setpoint, disturbance, and process dynamics. In other words, the task of the MFA controller is to minimize the error e1(t), e2(t), and e3(t) in an online fashion.
Since there is only one manipulated variable, minimizing errors for all three loops may not be possible. The control objective then can be defined as (i) to minimize the error for the most critical loop, or (ii) minimize the error for all 3 loops with no weighting on the importance so that there may be static errors in all loops.
FIG. 6 illustrates the simplified architecture of a 3-input-1-output Model-Free Adaptive (MFA) controller 78. It includes 3 SISO MFA controllers 72, 73, and 74, and a Combined Output Setter 76. Each of the SISO MFA controllers can be the same as described in the 2×1 MFA controller case. The controller output signals v1(t), v2(t), and v3(t) are used as inputs to the Combined Output Setter 76 to produce the controller output u(t).
FIG. 7 is a block diagram illustrating the simplified architecture of a 3-input-1-output (3×1) Feedback/Feedforward Model-Free Adaptive (MFA) controller. The 3×1 Feedback/Feedforward MFA controller 89 comprises three SISO MFA controllers 79, 80, 81, three Feedforward MFA controllers 82, 83, 84, three signal adders 85, 86, 87, and one Combined Output Setter 88. The design of the Feedforward MFA controllers can be the same as described in the 2×1 Feedback/Feedforward MFA controller case.
The control signals u1(t), u2(t), and u3(t) are calculated based on the following formulas:

u1(t)=ν1(t)+νƒ1(t),  (17a)

u2(t)=v2(t)+νƒ2(t),  (17b)

u3(t)=ν3(t)+νƒ3(t)  (17c)

where ν1(t), ν2(t), and ν3(t) are the feedback MFA controller outputs and νƒ1(t), νƒ2(t), and νƒ3(t) are the Feedforward MFA controller outputs. If a Feedforward MFA controller is not active, its νƒj(t)=0, then uj(t)=νj(t), j=1, 2, 3.

FIG. 8 is a drawing illustrating a mechanism of a Combined Output Setter that can combine 3 controller outputs u1(t), u2(t), and u3(t) into one controller output u(t). By moving the knobs R1 and R2, we can adjust the amount of control signals u1(t), u2(t), and u3(t) to be contributed to the actual controller output u(t), which can be calculated based on the following formula:

u(t)=R1u1(t)+R2u2(t)+(1−R1−R2)u3(t),  (18)

where 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; 0≦R1+R2≦1; and R1 and R2 are constants.

Similar to the 2×1 case, the controller gain weighted Combined Output Setter algorithm is given in the following formula:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  c1
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  c2
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  c3
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  3
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
    
      
        (
        
          19
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              K
              c1
            
            +
            
              K
              c2
            
            +
            
              K
              c3
            
          
        
        ,
      
    
    
      
        (
        
          19
          ⁢
          b
        
        )
      
    
  




where Kc1, Kc2 and Kc3 are MFA controller gains for SISO MFA 1, 2, and 3, respectively. This allows the 3×1 MFA controller to dynamically tighten the most important loop of the three. We can easily set a higher controller gain for the most important loop to minimize its error and allow the other loops to be relatively in loose control. We can also set these 3 controller gains at an equal value so that all loops are treated with equal importance. Both mechanisms represented in Equations (18) and (19) can be used as the Combined Output Setter 76 and 88 in FIG. 6 and FIG. 7, respectively.

C. Single-Input-Multi-Output Model-Free Adaptive Controller

FIG. 9 illustrates an M-input-1-output (M×1) MFA controller that controls a 1-input-M-output (1×M) system. The control system comprises an M-input-1-output (M×1) MFA controller 94, a 1-input-M-output (1×M) system 96, and signal adders 98, 99, 100, 102, 103, and 104. The signals shown in FIG. 9 are as follows:
r1(t), r2(t), . . . , rM(t)—Setpoint 1, 2, . . . , M.
x1(t), x2(t), . . . , xM(t)—System outputs of the 1×M system.
d1(t), d2(t), . . . , dM(t)—Disturbance 1, 2, . . . , M caused by noise or load changes.
y1(t), y2(t), . . . , yM(t)—Measured process variables of the 1×M system,

y1(t)=x1(t)+d1(t); y2(t)=x2(t)+d2(t); . . . ; and yM(t)=xM(t)+dM(t).

e1(t), e2(t), . . . , eM(t)—Error between the setpoint and measured process variable,

e1(t)=r1(t)−y1(t); e2(t)=r2(t)−y2(t); . . . ; and eM(t)=rM(t)−yM(t).

u(t)—Output of the M×1 MFA Controller.
The control objective is for the controller to produce output u(t) to manipulate the manipulated variable so that the measured process variables y1(t), y2(t), . . . , yM(t) track the given trajectory of their setpoints r1(t), r2(t), . . . , rM(t), respectively, under variations of setpoint, disturbance, and process dynamics. In other words, the task of the MFA controller is to minimize the error e1(t), e2(t), . . . , eM(t) in an online fashion.
Since there is only one manipulated variable, minimizing errors for all M loops may not be possible. The control objective then can be defined as (i) to minimize the error for the most critical loop, or (ii) to minimize the error for all M loops with no weighting on the importance so that there may be static errors in all loops.
FIG. 10 illustrates the simplified architecture of an M-input-1-output Model-Free Adaptive (MFA) controller 114. It includes M SISO MFA controllers 106, 107, 108 and a Combined Output Setter 112. Each of the SISO MFA controllers can be the same as described in the 2×1 MFA controller case. The controller output signals v1(t), v2(t), . . . , vM(t) are used as inputs to the Combined Output Setter 112 to produce the controller output u(t).
FIG. 11 is a block diagram illustrating the simplified architecture of an M-input-1-output (M×1) Feedback/Feedforward Model-Free Adaptive (MFA) controller. The M×1 Feedback/Feedforward MFA controller 128 comprises M SISO MFA controllers 116, 117, 118, M Feedforward MFA controllers 119, 120, 121, M signal adders 122, 123, 124, and one Combined Output Setter 126. The design of the Feedforward MFA controllers can be the same as described in the 2×1 Feedback/Feedforward MFA controller case.
The control signals u1(t), u2(t), . . . , uM(t) are calculated based on the following formulas:

u1(t)=ν1(t)+νƒ1(t),  (20a)

u2(t)=ν2(t)+ν2(t)  (20b)

uM(t)=νM(t)+νƒM(t),  (20c)

where ν1(t), ν2(t), . . . , νM(t) are the feedback MFA controller outputs and νƒ1(t), νƒ2(t), . . . , νƒM(t) are the feedforward MFA controller outputs. If a Feedforward MFA controller is not active, its νƒj(t)=0, then uj(t)=νj(t), j=1, 2, . . . , M.

FIG. 12 is a drawing illustrating a mechanism of a Combined Output Setter that can combine M controller outputs u1(t), u2(t), . . . , uM(t) into one controller output u(t). By moving the knobs R1, R2, . . . , RM-1, we can adjust the amount of control signals u1(t), u2(t), . . . , uM(t) to be contributed to the actual controller output u(t), which can be calculated based on the following formula:

u(t)=R1u1(t)+R2u2(t)+ . . . +(1−R1− . . . −RM-1)uM(t),  (21)

where M=3, 4, 5, . . . ; 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; and R1, R2, . . . , RM-1 are constants.

Similarly, a controller gain weighted Combined Output Setter algorithm is given in the following formula:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  c1
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  c2
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  K
                  cM
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
    
      
        (
        
          22
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              K
              c1
            
            +
            
              K
              c2
            
            +
            ...
            +
            
              K
              cM
            
          
        
        ,
      
    
    
      
        (
        
          22
          ⁢
          b
        
        )
      
    
  




where Kc1, Kc2, . . . , KcM are MFA controller gains for SISO MFA 1, 2, and M, respectively. This allows the M×1 MFA controller to dynamically tighten the most important loop. We can easily set a higher controller gain for the most important loop to minimize its error as the highest priority and allow the other loops to be relatively in loose control. We can also set these M controller gains at an equal value so that all loops are treated with equal importance.

Both mechanisms represented in Equations (21) and (22) can be used as the Combined Output Setter 112 and 126 in FIG. 10 and FIG. 11, respectively.
To expand the design, we can rescale the control output signal u(t) from its 0% to 100% range to an engineering value range by using a linear function. In addition, control limits and constraints can be applied to these signals for safety or other reasons to limit the control actions.
D. 2-Input-1-Output PID Controller
FIG. 13 illustrates a 2-input-1-output (2×1) PID controller that controls a 1-input-2-output (1×2) system. The control system comprises a 2-input-1-output (2×1) PID controller 134, a 1-input-2-output (1×2) system 136, and signal adders 137, 138, 139, and 140. Within the 2×1 PID controller 134, there are two SISO PID controllers 142, 143 and one Combined Output Setter 144. The signals shown in FIG. 13 are as follows:
r1(t), r2(t)—Setpoint 1 and Setpoint 2.
x1(t), x2(t)—System outputs of the 1×2 system.
d1(t), d2(t)—Disturbance 1 and 2 that are caused by noise or load changes.
y1(t), y2(t)—Measured process variables of the 1×2 system,

y1(t)=x1(t)+d1(t); and y2(t)=x2(t)+d2(t).

e1(t), e2(t)—Error between the setpoint and measured process variable,

e1(t)=r1(t)−y1(t); and e2(t)=r2(t)−y2(t).

u(t)—Output of the 2×1 PID Controller.
u1(t), u2(t)—Output of SISO PID 1 and PID 2.
The control objective is for the controller to produce output u(t) to manipulate the manipulated variable so that the measured process variables y1(t) and y2(t) track the given trajectory of their setpoints r1(t) and r2(t), respectively. In other words, the task of the 2×1 PID controller is to minimize the error e1(t) and e2(t) in an online fashion.
Since there is only one manipulated variable, minimizing errors for both loops may not be possible. The control objective then can be defined as (i) to minimize the error for the more critical loop of the two, or (ii) to minimize the error for both loops with no weighting on the importance so that there may be static errors in both loops.
The standard PID algorithm has the following form:




  
    
      
        
          
            
              u
              j
            
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              K
              p
            
            ⁢
            
              {
              
                
                  e
                  ⁡
                  
                    (
                    t
                    )
                  
                
                +
                
                  
                    1
                    
                      T
                      i
                    
                  
                  ⁢
                  
                    ∫
                    
                      
                        e
                        ⁡
                        
                          (
                          t
                          )
                        
                      
                      ⁢
                      
                        d
                        t
                      
                    
                  
                
                +
                
                  
                    T
                    d
                  
                  ⁢
                  
                    
                      d
                      
                        e
                        ⁡
                        
                          (
                          t
                          )
                        
                      
                    
                    
                      d
                      t
                    
                  
                
              
              }
            
          
        
        ,
      
    
    
      
        (
        23
        )
      
    
  




where Kp is the Proportional Gain, Ti is the Integral Time in second/repeat, Td is the Derivative Time in repeat/second, and uj(t) is the output of the jth PID, j=1, 2.

The Combined Output Setter illustrated in FIG. 4 can be used to combine the two SISO PID controller outputs u1(t) and u2(t) into one controller output u(t). By moving the knob R, we can adjust the amount of control signals u1(t) and u2(t) to be contributed to the actual controller output u(t), which can be calculated based on the following formula:

u(t)=Ru1(t)+(1−R)u2(t),  (24)

where 0≦u(t)≦100; 0≦R≦1; and R is a constant.

A controller gain weighted Combined Output Setter algorithm is given in the following formula:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  
                    p
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                
                  
                    K
                    
                      p
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    K
                    
                      p
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  
                    p
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                
                  
                    K
                    
                      p
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    K
                    
                      p
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
    
      
        (
        25
        )
      
    
  




where Kp1 and Kp2 are proportional gains for PID 1 and PID 2, respectively. This allows the 2×1 PID controller to dynamically tighten the more important loop of the two. We can easily set a higher proportional gain for the more important loop to minimize its error as the highest priority and allow the other loop to be relatively in loose control. We can also easily set both controller gains at an equal value so that both loops are treated with equal importance.

Both mechanisms represented in Equations (24) and (25) can be used as the Combined Output Setter 144 in FIG. 13.
To expand the design, we can rescale the control output signal u(t) from its 0% to 100% range to an engineering value range by using a linear function. In addition, control limits and constraints can be applied to these signals for safety or other reasons to limit the control actions.
Since PID is not an adaptive controller, proper manual tuning of its parameters Kp, Ti, and Td is required. When process dynamics change, frequent manual tuning of the parameters may be required. Model-Free Adaptive (MFA) controllers will outperform the PIDs because of their adaptive capability.
E. Multi-Input-Single-Output PID Controller
FIG. 14 illustrates an M-input-1-output (M×1) PID controller that controls a 1-input-M-output (1×M) system. The control system comprises an M-input-1-output (M×1) PID controller 146, a 1-input-M-output (1×M) system 148, and signal adders 149, 150, 151, 152, 153, and 154. Within the M×1 PID controller 146, there are M SISO PID controllers 155, 156, 157 and one Combined Output Setter 158. The signals shown in FIG. 14 are as follows:
r1(t), r2(t), . . . , rM(t)—Setpoint 1, 2, . . . , M.
x1(t), x2(t), . . . , XM(t)—System outputs of the 1×M system.
d1(t), d2(t), . . . , dM(t)—Disturbance 1, 2, . . . , M caused by noise or load changes.
y1(t), y2(t), . . . , yM(t)—Measured process variables of the 1×M system,

y1(t)=x1(t)+d1(t); y2(t)=x2(t)+d2(t); . . . ; and yM(t)=xM(t)+dM(t).

e1(t), e2(t), . . . , eM(t)—Error between the setpoint and measured process variable,

e1(t)=r1(t)−y1(t); e2(t)=r2(t)−y2(t); . . . ; and eM(t)=rM(t)−yM(t).

u(t)—Output of the M×1 PID Controller.
u1(t), u2(t), . . . , uM(t)—Output of SISO PID 1, 2, . . . , M, respectively.
The control objective is for the controller to produce output u(t) to manipulate the manipulated variable so that the measured process variables y1(t), y2(t), . . . , yM(t) track the given trajectory of their setpoints r1(t), r2(t), . . . , rM(t), respectively. In other words, the task of the PID controller is to minimize the error e1(t), e2(t), . . . , eM(t) in an online fashion.
Since there is only one manipulated variable, minimizing errors for all M loops may not be possible. The control objective then can be defined as (i) to minimize the error for the most critical loop, or (ii) to minimize the error for all M loops with no weighting on the importance so that there may be static errors in all loops.
The standard PID algorithm has the following form:




  
    
      
        
          
            
              u
              j
            
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              K
              p
            
            ⁢
            
              {
              
                
                  e
                  ⁡
                  
                    (
                    t
                    )
                  
                
                +
                
                  
                    1
                    
                      T
                      i
                    
                  
                  ⁢
                  
                    ∫
                    
                      
                        e
                        ⁡
                        
                          (
                          t
                          )
                        
                      
                      ⁢
                      
                        d
                        t
                      
                    
                  
                
                +
                
                  
                    T
                    d
                  
                  ⁢
                  
                    
                      d
                      
                        e
                        ⁡
                        
                          (
                          t
                          )
                        
                      
                    
                    
                      d
                      t
                    
                  
                
              
              }
            
          
        
        ,
      
    
    
      
        (
        26
        )
      
    
  




where Kp is the Proportional Gain, Ti is the Integral Time in second/repeat, Td is the Derivative Time in repeat/second, and uj(t) is the output of the jth PID, j=1, 2, . . . M.

Similarly, we can expand the 2×1 case to the M×1 case. The Combined Output Setter illustrated in FIG. 12 can be used to combine M PID controller outputs u1(t), u2(t), . . . , uM(t) into one controller output u(t). By moving the knobs R1, R2, . . . , RM-1, we can adjust the amount of control signals u1(t), u2(t), . . . , uM(t) to be contributed to the actual controller output u(t), which can be calculated based on the following formula:

u(t)=R1u1(t)+R2u2(t)+ . . . +(1−R1− . . . −RM-1)uM(t),  (27)

where M=3, 4, 5, . . . , 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; and R1, R2, . . . , RM-1, are constants.

Similarly, a controller gain weighted Combined Output Setter algorithm is given in the following formula:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  
                    p
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  
                    p
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  K
                  pM
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
    
      
        (
        
          28
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              K
              
                p
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              K
              
                p
                ⁢
                
                  
                
                ⁢
                2
              
            
            +
            ...
            +
            
              K
              pM
            
          
        
        ,
      
    
    
      
        (
        
          28
          ⁢
          b
        
        )
      
    
  




where Kp1, Kp2, . . . , KpM are proportional gains for PID 1, 2, . . . , M, respectively. This allows the M×1 PID controller to dynamically tighten the most important loop. We can easily set a higher proportional gain for the most important loop to minimize its error as the highest priority and allow the other loops to be relatively in loose control. We can also set these M proportional gains at an equal value so that all loops are treated with equal importance. Both mechanisms represented in Equations (27) and (28) can be used as the Combined Output Setter 158 in FIG. 14.

Since PID is a general-purpose controller, the 2×1 and M×1 PID controllers presented in this patent apply to all alternative forms of PID algorithms. They may be P only, PI, PD, or PID controllers, in analog or digital formulas, with various definitions of variables, parameters and units, etc. This Mxl PID controller with the Combined Output Setter will be more powerful than a single-input-single-output PID controller when controlling a 1×M system. However, since it is not an adaptive controller, it may not be able to handle large dynamic changes in the systems. Proper manual tuning of PID parameters is always required. The M×1 Model-Free Adaptive (MFA) controller presented in this patent is a more preferred solution for controlling a 1×M system.
F. Multi-Input-Single-Output Controller
FIG. 15 illustrates a multi-input-single-output (MISO) controller that controls a single-input-multi-output (SIMO) system. The control system comprises a multi-input-single-output (MISO) controller 160, a single-input-multi-output (SIMO) system 162, and signal adders 164, 165, 166, 168, 169, and 170. Within the MISO controller 160, there are M single-input-single-output (SISO) controllers 172, 173, 174 and one Combined Output Setter 176. The signals shown in FIG. 15 are as follows:
r1(t), r2(t), . . . , rM(t)—Setpoint 1, 2, . . . , M.
x1(t), x2(t), . . . , xM(t)—System outputs of the SIMO system.
d1(t), d2(t), . . . , dM(t)—Disturbance 1, 2, . . . , M caused by noise or load changes.
y1(t), y2(t), . . . , yM(t)—Measured process variables of the SIMO system,

y1(t)=x1(t)+d1(t); y2(t)=x2(t)+d2(t); . . . ; and yM(t)=xM(t)+dM(t).

e1(t), e2(t), . . . , eM(t)—Error between the setpoint and measured process variable,

e1(t)=r1(t)−y1(t); e2(t)=r2(t)—y2(t); . . . ; and eM(t)=rM(t)−yM(t).

u(t)—Output of the MISO Controller.
u1(t), u2(t), . . . , uM(t)—Output of SISO controller C1, C2, . . . , CM.
The control objective is for the controller to produce output u(t) to manipulate the manipulated variable so that the measured process variables y1(t), y2(t), . . . , yM(t) track the given trajectory of their setpoints r1(t), r2(t), . . . , rM(t), respectively. In other words, the task of the MISO controller is to minimize errors e1(t), e2(t), . . . , eM(t) in an online fashion.
Since there is only one manipulated variable, minimizing errors for all M loops may not be—possible. The control objective then can be defined as (i) to minimize the error for the most critical loop, or (ii) to minimize the error for all M loops with no weighting on the importance so that there may be static errors in all loops.
The MISO controller comprises M single-input-single-output (SISO) controllers 172, 173, 174. Without losing generality, we assume the control outputs for the SISO controllers C1, C2, . . . , CM are calculated based on the following formulas, respectively:

u1(t)=f(e1(t),t, P11, P12, . . . , P1l)  (29a)

u2 (t)=f(e2(t),t, P21, P22, . . . , P2l,  (29b)

uM(t)=f(eM(t),t, PM1, PM2, . . . , PMt),  (29c)

where t is time, P11, P12, . . . , P1l are tuning parameters for controller C1, P21, P22, . . . , P21 are tuning parameters for controller C2, . . . , and PM1, PM2, . . . , PM1 are tuning parameters for controller CM.

The Combined Output Setter illustrated in FIG. 12 can be used to combine M SISO controller outputs u1(t), u2(t), . . . , uM(t) into one controller output u(t). By moving the knobs R1, R2, . . . , RM-1, we can adjust the amount of control signals u1(t), u2(t), . . . , uM(t) to be contributed to the actual controller output u(t), which can be calculated based on the following formula:

u(t)=R1u1(t)+R2u2(t)+ . . . +(1−R1− . . . −RM-1)uM(t),  (30)

where M=3, 4, 5 . . . , 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; and R1, R2, . . . , RM-1 are constants.

Similarly, a controller gain weighted Combined Output Setter algorithm is given in the following formula, assuming the controller gain is the first parameter P1:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  P
                  11
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  P
                  21
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  P
                  M1
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
    
      
        (
        
          31
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              P
              11
            
            +
            
              P
              21
            
            +
            ...
            +
            
              P
              M1
            
          
        
        ,
      
    
    
      
        (
        
          31
          ⁢
          b
        
        )
      
    
  




where P11, P21, . . . , PMl are gains for controller C1, C2, . . . , CM, respectively. This allows the MISO controller to dynamically tighten the most important loop. We can easily set a higher controller gain for the most important loop to minimize its error as the highest priority and allow the other loops to be relatively in loose control. We can also set these M controller gains at an equal value so that all loops are treated with equal importance. Both mechanisms represented in Equations (30) and (31) can be used as the Combined Output Setter 176 in FIG. 15.

This is a general case example of converting M single-input-single-output (SISO) controllers including but not limited to Model-Free Adaptive (MFA) controllers, or proportional-integral-derivative (PID) controllers, or any other form of SISO controllers to a multi-input-single-output (MISO) controller to control a single-input-multi-output (SIMO) system.

## Claims

1. A multi-input-single-output controller for a process having a plurality of process outputs which are controlled by one controller output applied to one actuator whose output is the input of said process, said controller comprising:
a) a plurality of neural networks each including:
i) an error input representative of the difference between a predetermined setpoint and one of said process outputs;
ii) a normalization unit for normalizing said error input to a predetermined range of values;
iii) a scaling function for scaling said normalized error input to produce a value E1 of the form






  
    
      E
      1
    
    =
    
      
        
          K
          c
        
        
          T
          c
        
      
      ⁢
      
        N
        ⁡
        
          (
          
            e
            ⁡
            
              (
              t
              )
            
          
          )
        
      
    
  
  ,




 or an equivalent thereof, in which Kc is the controller gain; Tc is the user-selected time constant of said process; N(·) is the normalization function of said normalization unit; and e(t) is the value of said error input at any given time;
iv) a layer of input neurons having as their inputs successively time-delayed values of E1;
v) a layer of hidden neurons each having as its output the sum of individually weighted ones of said successively time-delayed values of E1;
vi) an output neuron having as its output the sum of a first function of the individually weighted outputs of said hidden neurons;

vii) a control signal which is at least in part the denormalized value of a second function of the output of said output neuron; and
b) said control signals of said plurality of neural networks being combined by a combined output setter to produce said controller output.

2. The controller of claim 1, in which said control signal of each neural network is the sum of said denormalized value and the value Kc e(t), or an equivalent thereof.

3. The controller of claim 1, in which the said plurality is 2.

4. The controller of claim 3, in which said controller output is generated by the said combined output setter in the form:


u(t)=Rv1(t)+(1−R)v2(t)


or an equivalent thereof, in which 0≦u(t)≦100; 0≦R≦1; R is a constant; and v1(t) and v2(t) are said control signals of the said neural networks.

5. The controller of claim 3, in which said controller output is generated by the said combined output setter in the form:




  
    
      u
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              1
            
          
          
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
        ⁢
        
          
            v
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              2
            
          
          
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
        ⁢
        
          
            v
            2
          
          ⁡
          
            (
            t
            )
          
        
      
    
  
  ,




or an equivalent thereof, in which 0≦u(t)≦100; Kc1 and Kc2 are user-selected controller gains for each of the said neural network, respectively; and v1(t) and v2(t) are said control signals of the said neural networks.

6. The controller of claim 3, in which there are two additional feedforward controllers and the combined feedback and feedforward controller signals u1(t) and u2(t) are of the form


u1(t)=v1(t)+vƒ1(t)



u2(t)=v2(t)+vƒ2(t)


or an equivalent thereof, in which v1(t) and v2(t) are the said control signals of the said neural networks, respectively; and vf1(t) and vf2(t) are the feedforward controller outputs.

7. The controller of claim 6, in which said controller output is generated by the said combined output setter in the form:


u(t)=Ru1(t)+(1−R)u2(t),


or an equivalent thereof, in which 0≦u(t)≦100; 0≦R≦1; R is a constant; and u1(t) and u2(t) are the combined feedback and feedforward controller signals.

8. The controller of claim 6, in which said controller output is generated by the said combined output setter in the form:




  
    
      u
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              1
            
          
          
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
        ⁢
        
          
            u
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              2
            
          
          
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              K
              
                c
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
        ⁢
        
          
            u
            2
          
          ⁡
          
            (
            t
            )
          
        
      
    
  
  ,




or an equivalent thereof, in which 0≦u(t)≦100; Kc1 and Kc2 are user-selected controller gains for each of the said neural network, respectively; and u1(t) and u2(t) are the combined feedback and feedforward controller signals.

9. The controller of claim 1, in which the said plurality is 3.

10. The controller of claim 9, in which said controller output is generated by the said combined output setter in the form:


u(t)=R1v1(t)+R2v2(t)+(1−R1−R2)v3(t),


or an equivalent thereof, in which 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; 0≦R1+R2≦1; R1 and R2 are constants; and v1(t), v2(t), and v3(t) are said control signals of the said neural networks.

11. The controller of claim 9, in which said controller output is generated by the said combined output setter in the form:




  
    
      u
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              1
            
          
          
            K
            sum
          
        
        ⁢
        
          
            v
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              2
            
          
          
            K
            sum
          
        
        ⁢
        
          
            v
            2
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              3
            
          
          
            K
            sum
          
        
        ⁢
        
          
            v
            3
          
          ⁡
          
            (
            t
            )
          
        
      
    
  
  ,
  
    

  
  ⁢
  
    
      K
      sum
    
    =
    
      
        K
        
          c
          ⁢
          
            
          
          ⁢
          1
        
      
      +
      
        K
        
          c
          ⁢
          
            
          
          ⁢
          2
        
      
      +
      
        K
        
          c
          ⁢
          
            
          
          ⁢
          3
        
      
    
  
  ,




or an equivalent thereof, in which 0≦u(t)≦100; Kc1, Kc2, and Kc3 are user-selected controller gains for each of the said neural network, respectively; and v1(t), v2(t), and v3(t) are said control signals of the said neural networks.

12. The controller of claim 9, in which there are three additional feedforward controllers and the combined feedback and feedforward controller signals u1(t), u2(t) and u3(t) are of the form


u1(t)=v1(t)+vƒ1(t)



u2(t)=v2(t)+vƒ2(t)



u3(t)=v3(t)+vƒ3(t)


or an equivalent thereof, in which v1(t), v2(t), and v3(t) are the said control signals of the said neural networks, respectively; and vf1(t), vf2(t), and vf3(t) are the feedforward controller outputs.

13. The controller of claim 12, in which said controller output is generated by the said combined output setter in the form:


u(t)=R1u1(t)+R2u2(t)+(1−R1−R2)u3(t)


or an equivalent thereof, in which 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; 0≦R1+R2≦1; R1 and R2 are constants; and u1(t), u2(t), and u3(t) are the combined feedback and feedforward controller signals.

14. The controller of claim 12, in which said controller output is generated by the said combined output setter in the form:




  
    
      u
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              1
            
          
          
            K
            sum
          
        
        ⁢
        
          
            u
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              2
            
          
          
            K
            sum
          
        
        ⁢
        
          
            u
            2
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            
              c
              ⁢
              
                
              
              ⁢
              3
            
          
          
            K
            sum
          
        
        ⁢
        
          
            u
            3
          
          ⁡
          
            (
            t
            )
          
        
      
    
  
  ,
  
    

  
  ⁢
  
    
      K
      sum
    
    =
    
      
        K
        
          c
          ⁢
          
            
          
          ⁢
          1
        
      
      +
      
        K
        
          c
          ⁢
          
            
          
          ⁢
          2
        
      
      +
      
        K
        
          c
          ⁢
          
            
          
          ⁢
          3
        
      
    
  
  ,




or an equivalent thereof, in which 0≦u(t)≦100; Kc1, Kc2, and Kc3 are user-selected controller gains for each of the said neural network, respectively; and u1(t), u2(t), and u3(t) are the combined feedback and feedforward controller signals.

15. The controller of claim 1, in which the said plurality is M.

16. The controller of claim 15, in which said controller output is generated by the said combined output setter in the form:


u(t)=R1v1(t)+R2v2(t)+ . . . +(1−R1− . . . −RM-1)vM(t),


or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; R1, R2, . . . , RM-1 are constants; and v1(t), v2(t), . . . , vM(t) are said control signals of the said neural networks.

17. The controller of claim 15, in which said controller output is generated by the said combined output setter in the form:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  cl
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  v
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  c2
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  v
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  K
                  cM
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  v
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              K
              c1
            
            +
            
              K
              c2
            
            +
            ...
            +
            
              K
              cM
            
          
        
        ,
      
    
  




or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; Kc1, Kc2, . . . , KcM are user-selected controller gains for each of the said neural network, respectively; and v1(t), v2(t), . . . , vM(t) are said control signals of the said neural networks.

18. The controller of claim 15, in which there are M additional feedforward controllers and the combined feedback and feedforward controller signals u1(t), u2(t), . . . , uM(t) are of the form


u1(t)=v1(t)+vƒ1(t)



u2(t)=v2(t)+vƒ2(t)



. . .



uM(t)=vM(t)+vƒM(t),


or an equivalent thereof, in which v1(t), v2(t), . . . , vM(t) are the said control signals of the said neural networks, respectively; and v1(t), v2(t), . . . , vfM(t) are the feedforward controller outputs.

19. The controller of claim 18, in which said controller output is generated by the said combined output setter in the form:


u(t)=R1u1(t)+R2u2(t)+ . . . +(1−R1− . . . −RM-1)uM(t),


or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; 0≦R1≦1; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; R1, R2 . . . , RM-1 are constants; and u1(t), u2(t), . . . , uM(t) are the combined feedback and feedforward controller signals.

20. The controller of claim 18, in which said controller output is generated by the said combined output setter in the form:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  cl
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  c2
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  K
                  cM
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              K
              c1
            
            +
            
              K
              c2
            
            +
            ...
            +
            
              K
              cM
            
          
        
        ,
      
    
  




or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; Kc1, Kc2, . . . , KcM are user-selected controller gains for each of the said neural network, respectively; and u1(t), u2(t), . . . , uM(t) are the combined feedback and feedforward controller signals.

21. A multi-input-single-output PID controller for a process having a plurality of process outputs which are controlled by one controller output applied to one actuator whose output is the input of said process, said controller comprising:
a) a plurality of PID controllers in the form





  
    
      
        u
        j
      
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        K
        p
      
      ⁢
      
        {
        
          
            e
            ⁡
            
              (
              t
              )
            
          
          +
          
            
              1
              
                T
                i
              
            
            ⁢
            
              ∫
              
                
                  e
                  ⁡
                  
                    (
                    t
                    )
                  
                
                ⁢
                
                  d
                  t
                
              
            
          
          +
          
            
              T
              d
            
            ⁢
            
              
                d
                
                  e
                  ⁡
                  
                    (
                    t
                    )
                  
                
              
              
                d
                t
              
            
          
        
        }
      
    
  
  ,



 or an equivalent thereof, in which Kp is the proportional gain; Ti is the integral time; Td is the derivative time; and uj(t) is the output of the jth PID, j=1, 2, . . . M; and
b) said control signals of said plurality of PID controllers being combined by a combined output setter to produce said controller output.

22. The controller of claim 21, in which the said plurality is 2.

23. The controller of claim 22, in which said controller output is generated by the said combined output setter in the form:


u(t)=Ru1(t)+(1−R)u2(t),


or an equivalent thereof, in which 0≦u(t)≦100; 0≦R≦1; R is a constant; and u1(t) and u2(t) are the outputs of the said PID controllers.

24. The controller of claim 22, in which said controller output is generated by the said combined output setter in the form:




  
    
      u
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          
            K
            p1
          
          
            
              K
              p1
            
            +
            
              K
              p2
            
          
        
        ⁢
        
          
            u
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      +
      
        
          
            K
            p2
          
          
            
              K
              p1
            
            +
            
              K
              p2
            
          
        
        ⁢
        
          
            u
            2
          
          ⁡
          
            (
            t
            )
          
        
      
    
  
  ,




or an equivalent thereof, in which 0≦u(t)≦100; Kp1 and Kp2 are user-selected PID controller gains, respectively; and u1(t) and u2(t) are the outputs of the said PID controllers.

25. The controller of claim 21, in which the said plurality is M.

26. The controller of claim 25, in which said controller output is generated by the said combined output setter in the form:


u(t)=R1u1(t)+R2u2(t)+ . . . +(1−R− . . . −RM-1)uM(t),


or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; R1, R2, . . . , RM-1 are constants; and u1(t), u2(t), and uM(t) are the outputs of the said PID controllers.

27. The controller of claim 25, in which said controller output is generated by the said combined output setter in the form:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  K
                  p1
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  K
                  p2
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  K
                  pM
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              K
              p1
            
            +
            
              K
              p2
            
            +
            ...
            +
            
              K
              pM
            
          
        
        ,
      
    
  




or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; Kp1, Kp2, . . . , KpM are user-selected PID controller gains, respectively; and u1(t), u2(t), and uM(t) are the outputs of the said PID controllers.

28. A multi-input-single-output controller for a process having a plurality of process outputs which are controlled by one controller output applied to one actuator whose output is the input of said process, said controller comprising:
a) a plurality of single-input-single-output (SISO) controllers C1, C2, . . . , CM in the form


u1(t)=ƒ(e1(t),t, P11, P12, . . . , P1l),



u2(t)=ƒ(e2(t),t, P21, P22, . . . , P2l),



. . .



uM(t)=ƒ(eM(t),t, PM1, PM2, . . . , PMl),


 or an equivalent thereof, in which M=1, 2, 3, 4, 5 . . . ; t is time; P11, P12, . . . , P11 are tuning parameters for controller C1; P21, P22, . . . , P2l are tuning parameters for controller C2; . . . ; and PM1, PM2 . . . , PMl are tuning parameters for controller CM; and
b) said control signals of said plurality of the SISO controllers being combined by a combined output setter to produce said controller output.

29. The controller of claim 28, in which said controller output is generated by the said combined output setter in the form:


u(t)=R1u1(t)+R2u2(t)+ . . . +(1−R1− . . . −RM-1)uM(t),


or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; 0≦R1≦1; 0≦R2≦1; . . . ; 0≦RM-1≦1; 0≦R1+R2+ . . . +RM-1≦1; R1, R2, . . . , RM-1 are constants; and u1(t), u2(t), and uM(t) are the outputs of the said SISO controllers, respectively.

30. The controller of claim 28, in which said controller output is generated by the said combined output setter in the form:




  
    
      
        
          
            u
            ⁡
            
              (
              t
              )
            
          
          =
          
            
              
                
                  P
                  11
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  1
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            
              
                
                  P
                  12
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  2
                
                ⁡
                
                  (
                  t
                  )
                
              
            
            +
            ...
            +
            
              
                
                  P
                  M1
                
                
                  K
                  sum
                
              
              ⁢
              
                
                  u
                  M
                
                ⁡
                
                  (
                  t
                  )
                
              
            
          
        
        ,
      
    
  
  
    
      
        
          
            K
            sum
          
          =
          
            
              P
              11
            
            +
            
              P
              21
            
            +
            ...
            +
            
              P
              M1
            
          
        
        ,
      
    
  




or an equivalent thereof, in which M=3, 4, 5, . . . ; 0≦u(t)≦100; P11, P21, . . . , PM1 are gains for controller C1, C2, . . . , CM, respectively; and u1(t), u2(t), and uM(t) are the outputs of the said SISO controllers, respectively.

31. The controller of claim 1, 21, or 28, in which said combined output setter includes individual controls that can be set freely within said output range to produce said controller output.

32. The controller of claim 1, 21, or 28, in which the said controller output is re-scalable from the 0 to 100 range to an engineering value range by using a linear function.

33. The controller of claim 1, 21, or 28, in which the said controller output is arranged to include selectable control limits or control constraints.

34. The controller of claim 1, 21, or 28, in which said controller is a computer program embodied in a digital medium.