# Patent

## Title
Method to improve CMFB phase margin of variable-output-bandwidth mixer

## Abstract

An improved method and apparatus for using common mode feedback to maintain a predetermined DC level for an intermediate frequency output signal. A common mode feedback capacitor-select switch module is operable to use a bandwidth control signal from a radio interface of a wireless device to selectively connect a plurality of common mode feedback capacitors to an operational amplifier, thereby generating a common mode feedback signal as an input to an active mixer conversion gain module. The predetermined combination of common mode feedback capacitors is used in combination with a plurality of bandwidth capacitors to generate an overall capacitance that maintains the bandwidth of the system at a predetermined value. A predetermined capacitance value is “shifted” from the bandwidth capacitor bank to the CMFB capacitor bank, thereby providing an overall ratio that maintains the bandwidth while defining a predetermined capacitance connected to the operational amplifier to generate a desired common mode feedback signal that maintains the phase margin of the output signal at a predetermined level.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed in general to wireless communication systems. In one aspect, the present invention relates to a method and system for controlling the common mode feedback phase margin of a variable-output-bandwidth mixer in a wireless communication device.
2. Related Art
Communication systems are known to support wireless and wire-lined communications between wireless and/or wire-lined communication devices. Such communication systems range from national and/or international cellular telephone systems to the Internet to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth (BT), advanced mobile phone services (AMPS), digital AMPS, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS) and/or variations thereof.
Depending on the type of wireless communication system, a wireless communication device (such as a cellular telephone, two-way radio, personal digital assistant (PDA), personal computer (PC), laptop computer, home entertainment equipment, etc.) communicates directly or indirectly with other wireless communication devices. For direct communications (also known as point-to-point communications), the participating wireless communication devices tune their receivers and transmitters to the same channel or channels (e.g., one of the plurality of radio frequency (RF) carriers of the wireless communication system) and communicate over the tuned channel(s). For indirect wireless communications, each wireless communication device communicates directly with an associated base station (e.g., for cellular services) and/or an associated access point (e.g., for an in-home or in-building wireless network) via an assigned channel. To complete a communication connection between the wireless communication devices, the associated base stations and/or associated access points communicate with each other directly, via a system controller, via the public switched telephone network, via the Internet, and/or via some other wide area network.
Wireless communication devices typically communicate with one another using a radio transceiver (i.e., receiver and transmitter) that may be incorporated in, or coupled to, the wireless communication device. The transmitter typically includes a data modulation stage, one or more intermediate frequency stages, and a power amplifier. The data modulation stage converts raw data into baseband signals in accordance with a particular wireless communication standard. The intermediate frequency stages mix the baseband signals with one or more local oscillations to produce RF signals. The power amplifier amplifies the RF signals prior to transmission via an antenna. In direct conversion transmitters/receivers, conversion directly between baseband signals and RF signals is performed. The receiver is typically coupled to an antenna and includes a low noise amplifier, one or more intermediate frequency stages, a filtering stage, and a data recovery stage. The low noise amplifier receives inbound RF signals via the antenna and amplifies them. The intermediate frequency stages mix the amplified RF signals with one or more local oscillations to convert the amplified RF signal into baseband signals or intermediate frequency (IF) signals. The filtering stage filters the baseband signals or the IF signals to attenuate unwanted out of band signals to produce filtered signals. The data recovery stage recovers raw data from the filtered signals in accordance with the particular wireless communication standard.
Wireless communication devices for multimedia audio and video applications generally require a higher data rate than is currently available with devices operating under the 802.11(a), (b), and (g) standards. Several draft standards (such as the 802.11(n) draft standard) have been proposed to implement faster data rates for wireless devices. Wireless devices operating under these standards will be capable of providing data rates up to 200 Mbps. Since these standards have not been finalized, they will be referred to generically as 802.11(x) herein.
Active common mode feedback (CMFB) is a very effective way to set the DC level of a down conversion module employing an adaptive mixer used in a wireless communication device. In general, most design criteria for wireless transceivers require 45 degrees of phase margin in the output of the adaptive mixer. In down conversion modules wherein resistance loads and bandwidth-compensating capacitors are used to control the gain and bandwidth of an output signal, however, it is very common to have a phase margin for the output signal which falls below the desired design criteria. There is a need, therefore, for an improved down conversion module that employs common mode feedback to control the DC level of the output signal.
SUMMARY OF THE INVENTION
The objects, advantages and other novel features of the present invention will be apparent from the following detailed description when read in conjunction with the appended claims and attached drawings. In an embodiment of the invention, a common mode feedback module is used to maintain a predetermined DC level for an intermediate frequency output signal. In this embodiment of the invention, a common mode feedback capacitor-select switch module is operable to use the bandwidth control signal from the radio interface to selectively connect a plurality of common mode feedback capacitors operably connected to an operational amplifier, thereby generating a common mode feedback signal as an input to an active mixer conversion gain module. In this embodiment of the invention, the predetermined combination of common mode feedback capacitors is used in combination with a plurality of bandwidth capacitors to generate an overall capacitance that maintains the bandwidth of the system at a predetermined value. A predetermined capacitance value is “shifted” from the bandwidth capacitor bank to the CMFB capacitor bank, thereby providing an overall ratio that maintains the bandwidth while defining a predetermined capacitance connected to the operational amplifier to generate a desired common mode feedback signal that maintains the phase margin of the output signal at a predetermined level.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of a wireless communication system in accordance with the present invention.
FIG. 2 is a schematic block diagram of a wireless communication device in accordance with the present invention.
FIG. 3 is a schematic block diagram of a wireless interface device in accordance with the present invention.
FIG. 4 is a schematic block diagram of the down-converter module of the wireless interface device illustrated in FIG. 3.
FIG. 5 is a flow chart description for using the present invention to improve the phase margin of a common mode feedback phase margin of a variable-output-bandwidth mixer.



DETAILED DESCRIPTION
A method and apparatus for an improved wireless communication system is described. While various details are set forth in the following description, it will be appreciated that the present invention may be practiced without these specific details. For example, selected aspects are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. Some portions of the detailed descriptions provided herein are presented in terms of algorithms or operations on data within a computer memory. Such descriptions and representations are used by those skilled in the field of communication systems to describe and convey the substance of their work to others skilled in the art. In general, an algorithm refers to a self-consistent sequence of steps leading to a desired result, where a “step” refers to a manipulation of physical quantities which may, though need not necessarily, take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It is common usage to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. These and similar terms may be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated or otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions using terms such as processing, computing, calculating, determining, displaying or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and/or transforms data represented as physical, electronic and/or magnetic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
FIG. 1 illustrates a wireless communication system 10 in which embodiments of the present invention may operate. As illustrated, the wireless communication system 10 includes a plurality of base stations and/or access points 12, 16, a plurality of wireless communication devices 18–32, and a network hardware component 34. The wireless communication devices 18–32 may be laptop host computers 18 and 26, personal digital assistant hosts 20 and 30, personal computer hosts 32, cellular telephone hosts 28, an 802.11a WLAN device 23, an 802.11g WLAN device 22 and/or an 802.11(x) device 24. The details of the wireless communication devices will be described in greater detail with reference to FIGS. 2–4.
As illustrated, the base stations or access points 12, 16 are operably coupled to the network hardware 34 via local area network connections 36, 38. The network hardware 34 (which may be a router, switch, bridge, modem, system controller, etc.) provides a wide area network connection 42 for the communication system 10. Each of the base stations or access points 12, 16 has an associated antenna or antenna array to communicate with the wireless communication devices in its area. Typically, the wireless communication devices register with a particular base station or access point 12, 16 to receive services from the communication system 10. For direct connections (i.e., point-to-point communications), wireless communication devices communicate directly via an allocated channel. Regardless of the particular type of communication system, each wireless communication device includes a built-in radio and/or is coupled to a radio. The radio includes a highly linear amplifier and/or programmable multi-stage amplifier as disclosed herein to enhance performance, reduce costs, reduce size, and/or enhance broadband applications.
FIG. 2 is a schematic block diagram illustrating a radio implemented in a wireless communication device that includes the host device or module 50 and at least one wireless interface device, or radio transceiver 59. The wireless interface device may be built in components of the host device 50 or externally coupled components. As illustrated, the host device 50 includes a processing module 51, memory 52, peripheral interface 55, input interface 58 and output interface 56. The processing module 51 and memory 52 execute the corresponding instructions that are typically done by the host device. For example, in a cellular telephone device, the processing module 51 performs the corresponding communication functions in accordance with a particular cellular telephone standard. For data received from the wireless interface device 59 (e.g., inbound data), the peripheral interface 55 provides the data to the processing module 51 for further processing and/or routing to the output interface 56. The output interface 56 provides connectivity to an output display device such as a display, monitor, speakers, etc., such that the received data may be displayed. The peripheral interface 55 also provides data from the processing module 51 to the wireless interface device 59. The processing module 51 may receive the outbound data from an input device such as a keyboard, keypad, microphone, etc. via the input interface 58 or generate the data itself. For data received via the input interface 58, the processing module 51 may perform a corresponding host function on the data and/or route it to a wireless interface device 59 via the peripheral interface 55.
The wireless interface device 59 includes a host interface 100, a media-specific access control protocol (MAC) layer module 102, a physical layer module (PHY) 104, a digital-to-analog converter (DAC) 103, and an analog to digital converter (ADC) 105. Typically, transmit data coming from the host device 50 is presented to the MAC 102, which in turn presents it to the PHY 104. The PHY 104 processes the transmit data (scrambling, encoding, modulation, etc.) and then transmits its output to the DAC 103 for conversion to an analog signal. The DAC output is then gained and filtered and passed to the front end module 61 or 66. On the receive side, the front end module (61 or 66) output is gained and filtered, then passed to an ADC 105 for conversion to a digital signal. This digital signal is processed (demapped, decoded, descrambled, etc.) by the PHY 104 and the bits are passed through the MAC 102 to the host 50 for delivery to the output interface 56. As will be appreciated, the modules in the wireless interface device are implemented with a communications processor and an associated memory for storing and executing instructions that control the access to the physical transmission medium in the wireless network.
In addition to a first radio transceiver circuit and RF front end 61 (that may or may not be integrated on a common substrate with the wireless interface 59), a second radio transceiver circuit and RF front end 66 is provided and coupled to the wireless interface device 59. For example, the first radio transceiver circuit and RF front end circuit 61 transforms baseband data into a 2.4 GHz signal in accordance with the 802.11g standard, while the second radio transceiver circuit and RF front end circuit 66 transforms baseband data into a 5 GHz signal in accordance with the 802.11a or 802.11x standard.
The external device 65 includes its own wireless interface device for communicating with the wireless interface device of the host device. For example, the host device may be personal or laptop computer and the external devices 65 may be a headset, personal digital assistant, cellular telephone, printer, fax machine, joystick, keyboard, desktop telephone, or access point of a wireless local area network.
FIG. 3 is a schematic block diagram of a wireless interface device (i.e., a radio) 60 which includes a host interface 62, digital receiver processing module 64, an analog-to-digital converter (ADC) 66, a filtering/gain module 68, a down-conversion stage 70, a receiver filter 71, a low noise amplifier 72, a transmitter/receiver switch 73, a local oscillation module 74, memory 75, a digital transmitter processing module 76, a digital-to-analog converter (DAC) 78, a filtering/gain module 80, a mixing up-conversion stage 82, a power amplifier 84, a transmitter filter module 85 and an antenna control 77. The transmitter/receiver switch 73 is coupled to the antenna control 77 through which an antenna 86 is coupled to the wireless interface device. As will be appreciated, the antenna 86 may be a polarized antenna, dual-band antenna with a diplexor, a directional antenna and/or may be physically separated to provide a minimal amount of interference. In addition, the antenna 86 may be used for either transmitting or receiving signals, depending on the switching specified by the transmit/receive switch 73.
The digital receiver processing module 64, the digital transmitter processing module 76 and the memory 75 execute digital receiver functions and digital transmitter functions in accordance with a particular wireless communication standard. The digital receiver functions include, but are not limited to, digital baseband frequency conversion, demodulation, constellation demapping, decoding and/or descrambling. The digital transmitter functions include, but are not limited to, scrambling, encoding, constellation mapping, modulation and/or digital baseband frequency conversion. The digital receiver and transmitter processing modules 64, 76 may be implemented using a shared processing device, individual processing devices, or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry and/or any device that manipulates signals (analog and/or digital) based on operational instructions. The memory 75 may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when the processing module 64, 76 implements one or more of its functions via a state machine, analog circuitry, digital circuitry and/or logic circuitry, the memory storing the corresponding operational instructions may be embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry and/or logic circuitry.
In operation, the wireless interface device 60 receives outbound data 94 from the host device via the host interface 62. The host interface 62 routes the outbound data 94 to the digital transmitter processing module 76, which processes the outbound data 94 to produce digital transmission formatted data 96 in accordance with a particular wireless communication standard, such as IEEE 802.11 (including all current and future subsections), Bluetooth, etc. The digital transmission formatted data 96 will be a digital base-band signal or a digital low IF signal, where the low IF typically will be in the frequency range of one hundred kilohertz to a few megahertz. Subsequent stages convert the digital transmission formatted data to an RF signal using a PHY module 104 and radio transmission circuitry, and may be implemented as follows. The digital-to-analog converter 78 converts the digital transmission formatted data 96 from the digital domain to the analog domain. The filtering/gain module 80 filters and/or adjusts the gain of the analog signal prior to providing it to the radio interface module 35. For transmission in accordance with a first signaling protocol (e.g., IEEE 802.11g, or 802.11x), the radio interface module 35 provides the filtered/adjusted analog signal to the up-conversion module 82. The mixing stage 82 directly converts the analog baseband or low IF signal into an RF signal based on a transmitter local oscillation clock 83 provided by local oscillation module 74. The power amplifier 84 amplifies the RF signal to produce outbound RF signal 98, which is filtered by the transmitter filter module 85. Antenna switching control signals provided to the transmit/receive switch module 73 and antenna control module 77 route the outbound RF signal 98 for transmission to a targeted device such as a base station, an access point and/or another wireless communication device via antenna 86.
In accordance with a selected embodiment whereby a signal is to be received in accordance with a first signaling protocol (e.g., IEEE 802.11g or 802.11x), the wireless interface device 60 receives an inbound RF signal 88 from antenna 86 via antenna switch module 73 which was transmitted by a base station, an access point, or another wireless communication device. The inbound RF signal is converted into digital reception formatted data, either directly or through an intermediate frequency conversion process which may be implemented as follows. The antenna control module 77 and transmit/receive switch module 73 provide the inbound RF signal 88 to the receiver filter module 71, where the receiver filter 71 bandpass filters the inbound RF signal 88. The receiver filter 71 provides the filtered RF signal to low noise amplifier 72, which amplifies the signal 88 to produce an amplified inbound RF signal. The low noise amplifier 72 provides the amplified inbound RF signal to the down conversion module 70, which directly converts the amplified inbound RF signal into an inbound low IF signal or baseband signal based on a receiver local oscillation clock 81 provided by local oscillation module 74. The down conversion module 70 provides the inbound low IF signal or baseband signal to the filtering/gain module 68 via the radio interface 35. The filtering/gain module 68 filters and/or gains the inbound low IF signal or the inbound baseband signal to produce a filtered inbound signal. The analog-to-digital converter 66 converts the filtered inbound signal from the analog domain to the digital domain to produce digital reception formatted data 90. The digital receiver processing module 64 decodes, descrambles, demaps, and/or demodulates the digital reception formatted data 90 to recapture inbound data 92 in accordance with the particular wireless communication standard being implemented by wireless interface device. The host interface 62 provides the recaptured inbound data 92 to the host device (e.g., 50) via the peripheral interface (e.g., 55).
As will be appreciated, the wireless communication device described herein may be implemented using one or more integrated circuits. For example, the host device 50 may be implemented on one integrated circuit, the digital receiver processing module 64, the digital transmitter processing module 76 and memory 75 may be implemented on a second integrated circuit, the remaining components of the wireless interface device 60 may be implemented on a third integrated circuit and the second transceiver and antenna section 40 may be implemented in a fourth integrated circuit. Alternatively, the MAC 102, PHY 104 and radio transceiver 61 may be implemented as one integrated circuit, the FEM 109 may be implemented as a second integrated circuit and the second transceiver and antenna section 40 may be implemented as a third integrated circuit. As another alternate example, the wireless interface device 60 may be implemented on a first integrated circuit and the second transceiver and antenna section 40 may be implemented in a second integrated circuit. As yet another example, the wireless interface device 60 and the second transceiver and antenna section 40 may be implemented in a single integrated circuit. In addition, the processing module 51 of the host device and the digital receiver and transmitter processing modules 64 and 76 may be a common processing device implemented on a single integrated circuit. Further, the memory 52 and memory 75 may be implemented on a single integrated circuit and/or on the same integrated circuit as the common processing modules of processing module 51 and the digital receiver and transmitter processing module 64 and 76.
Details relating to the adaptive mixer 80 of the present invention can be seen by referring to FIG. 4. As will be understood by those of skill in the art, the gain of the conversion gain mixer is proportional to the load resistance RL, i.e., Gain∝gmRL. Furthermore, those of skill in the art will understand that the conversion gain mixer has a characteristic capacitance and the bandwidth associated with the mixer is determined by an RC constant. Therefore, the bandwidth of the mixer can be controlled by changing the capacitance. Specifically, the bandwidth of the output signal of the mixer is inversely proportional to the RC constant, i.e., Bandwidth∝1/RC. Therefore, if the gain of the mixer is changed by modifying the load resistance, RL, the RC constant that affects the mixer bandwidth will also be changed. If the gain is modified by changing the load resistance, the capacitance will also need to be changed to maintain a predetermined bandwidth. These gain and bandwidth properties of the adaptive mixer 80 will be discussed in greater detail hereinbelow.
As is shown in FIG. 4, the down converter 70 comprises an adaptive mixer 80 that includes a conversion gain module 82 that receives an RF input signal from the active mixer input module 84. The active mixer input module 84 receives an RF signal from low noise amplifier 72 and a local oscillation input signal from local oscillation module 74. The conversion gain module 82 converts the RF input signal to generate an intermediate frequency (IF) output signal that it provided to the radio interface 35. Operation of the conversion gain module 82 is controlled by the gain control module 86 and the bandwidth control module 88.
As was discussed hereinabove, the radio interface module 35 generates control signals that are used to control operation of the various components in the wireless interface. For operation of the down converter 70, the radio interface generates bandwidth and gain control signals. The gain control signal is provided as an input to resistor select switch module 92 of the gain control module 86. The resistor select switch module 92 is operable to select one or more resistors that are used to provide a load resistance to cause the conversion gain module 82 to provide a predetermined gain factor for the conversion of the input RF signal to the IF signal. The gain control signal is also provided as an input to bandwidth control logic module 90, which is operable to generate an input signal to capacitor select switch module 96, thereby causing a predetermined combination of capacitors in capacitor bank 98 to provide a capacitor input signal to the bandwidth compensation interface 100.
The gain compensation interface 95 provides a load resistance (RL) that is used by the conversion gain generator 84 to determine the gain factor for generating the output intermediate frequency signal. Likewise, the bandwidth compensation interface 100 provides a conversion gain capacitor value that is used by the conversion gain generator to determine the bandwidth for the intermediate frequency output signal.
In the method and apparatus of the present invention, the bandwidth of the mixer is modified subsequent to changing the gain to maintain the system at a predetermined bandwidth. In one embodiment of the invention, resistor and capacitor combinations are provided for three different bandwidths. Specifically, bandwidths adjustment are provided for RF input signals at 10 MHz, 20 MHz, and 40 MHz.
Referring again to FIG. 4, the common mode feedback module 102 comprises an operational amplifier 104 and a common mode feedback capacitor select switch module 106 that is operably connected to a common mode feedback capacitor bank. The operational amplifier receives the IF signal and a reference signal as its inputs. The capacitors of the common mode capacitor bank 108 are connected between one of the IF signal input and the output terminal of the operational amplifier 104. The common mode feedback selector switch module 106 receives the bandwidth control signal generated by the radio interface unit 35 and in response thereto generates a control signal to select a predetermined number of capacitors contained in the CMFB capacitor bank 108. The capacitors in the capacitor bank 108 are operably connected to one input terminal and the output terminal of the operational amplifier 104.
In one embodiment of the invention, the common mode feedback module 102 is used to maintain a predetermined DC level for the intermediate frequency output signal. In this embodiment of the invention, a common mode feedback capacitor select switch module 106 is operable to use the bandwidth control signal to selectively activate a plurality of capacitors in a common mode feedback capacitor bank 108. The selectively activated capacitors are operably connected to the operational amplifier 104, thereby generating a common mode feedback signal as an input to the active mixer input module 84.
In this embodiment of the invention, the predetermined combination of common mode feedback capacitors is used in combination with a plurality of bandwidth capacitors to generate an overall conversion gain capacitance that maintains the bandwidth of the system at a predetermined value. In an embodiment of the present invention, a portion of the conversion gain capacitance value is “shifted” from the bandwidth capacitor bank to the CMFB capacitor bank, thereby providing an overall ratio that maintains the desired bandwidth while defining a predetermined capacitance connected to the operational amplifier to generate a desired common mode feedback signal that maintains the phase margin of the output signal at a predetermined level. For example, if a selected capacitance value, e.g., 500 fF is required to maintain a predetermined bandwidth, a portion of this capacitance, e.g. 250 fF, can be “shifted” as a capacitance provided by the CMFB capacitor bank 108. The desired bandwidth will be maintained because the total required capacitance is provided by the combination of the bandwidth capacitor bank 98 and the CMFB capacitor bank 108. The portion of the capacitance provided by the CMFB capacitor bank also provides the necessary CMFB compensation.
FIG. 5 is a flow chart of the processing steps for implementing the present invention. In step 140, the initial gain and the initial bandwidth is set for the adaptive mixer 80. In step 142, a test is conducted to determine whether there has been a change in the gain control signal. If the result of the test conducted in step 142 indicates that no change in the gain control signal has occurred, processing proceeds to step 144 and the current gain setting is maintained. Processing then returns to step 142. If, however, the results of the test conducted in step 142 indicate that the gain control signal has changed, processing proceeds to step 146, wherein the gain control signal is used to modify the value of the load resistance RL using the resistor bank 94. The bandwidth for the adaptive mixer is then adjusted in step 147 as illustrated by dashed line 149. Processing then returns to step 148 wherein a test is conducted to determine whether there has been a change in the bandwidth control signal. If the results of the test conducted in step 148 indicate that there has not been a change in the desired bandwidth, the current bandwidth settings are maintained in step 150 and processing returns to step 142. If, however, the results of the test conducted in step 148 indicate that there has been a change in the bandwidth control signal, processing proceeds to step 147 wherein the bandwidth is adjusted by further changing the BW capacitance. Processing then proceeds to step 154 wherein a test is conducted to determine whether the current phase margin is within desired limits. If the result of the test conducted in step 154 indicates that the current phase margin is within desired limits, processing returns to step 142 and processing proceeds as discussed hereinabove. If, however, the result of the test conducted in step 154 indicates that the current phase margin is not within desired limits, processing proceeds to step 156 wherein a portion of the capacitance is shifted from the bandwidth capacitor bank to the CMFB capacitor bank 108. Processing returns to step 154 for a subsequent measurement of the phase margin. If the result of the step conducted in step 154 indicates that the phase margin is within desired limits, processing proceeds again to step 142 as discussed hereinabove. If, the results of the subsequent tests conducted in step 154 indicates that the phase margin is still not within desired limits, processing proceeds to step 156 and the processing steps are repeated until the test conducted in step 154 indicates that the phase margin is within desired limits.
OTHER EMBODIMENTS
Other embodiments are within the following claims.
Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.

## Claims

1. An adaptive mixer, comprising:
a conversion gain module operable to receive a radio frequency signal and to generate an intermediate frequency signal therefrom at a predetermined gain and at a predetermined first bandwidth and a predetermined phase margin, wherein said predetermined first bandwidth is determined by a predetermined conversion gain capacitance;
a common mode feedback module operable to receive a reference signal and said intermediate frequency signal and to generate a common mode feedback signal as an input to said conversion gain module, thereby maintaining the phase margin of said intermediate output signal at a predetermined level, wherein said common mode feedback signal is controlled by a common mode feedback capacitance and wherein a portion of said conversion gain capacitance for said conversion gain module is provided by said common mode feedback capacitance in said common mode feedback module.

2. The adaptive mixer of claim 1, wherein the output of said common mode capacitance comprises a selected combination of capacitors in a common mode feedback capacitor bank.

3. The adaptive mixer of claim 1, wherein said common mode capacitor bank is controlled by a bandwidth control logic module.

4. The adaptive mixer of claim 1, wherein said intermediate frequency output signal is provided to a radio interface that is operably connected to baseband signal processing components, wherein said radio interface is operable to generate a gain control signal to control the bandwidth of said intermediate frequency output signal and wherein said bandwidth control signal is used to select said combination of capacitors comprising said common mode feedback capacitance.

5. The adaptive mixer of claim 1, wherein said adaptive mixer further comprises:
a gain control module operable to change the gain of said conversion gain module from a first gain to a second gain, thereby generating an intermediate frequency signal at a second gain, wherein said intermediate frequency signal generated at said second gain has a second bandwidth;
a bandwidth control module operable to change the bandwidth of said intermediate frequency signal from said second bandwidth to said first predetermined bandwidth.

6. The adaptive mixer of claim 5, wherein said first and second gains of said conversion gain module are defined by first and second load resistances of said conversion gain module.

7. The adaptive mixer of claim 6, wherein said gain control module is operable to change said gain of said conversion gain module from said first gain to said second gain by operably coupling said second load resistance to said conversion gain module.

8. The adaptive mixer of claim 7, wherein said bandwidth control module is operable to detect said second load resistance and is operable to change the bandwidth of said intermediate frequency signal from said second bandwidth to said first predetermined bandwidth upon detection of said second load resistance.

9. The adaptive mixer of claim 8,
wherein said predetermined first bandwidth and said second bandwidth are defined by first and second RC constants of said conversion gain module, and wherein the resistance component of said first and second RC constants is determined by said first and second load resistances corresponding to said first and second gains, and
wherein said bandwidth control module is operable to connect a conversion gain capacitance to said conversion gain module to cause said second RC constant to have a value corresponding to said predetermined first bandwidth.

10. The adaptive mixer of claim 9, wherein said conversion gain capacitance comprises the common mode feedback capacitance of said common mode feedback module.

11. A method of generating an intermediate frequency using an adaptive mixer, comprising:
receiving a radio frequency signal and using a conversion gain module to generate an intermediate frequency signal therefrom, wherein said intermediate frequency signal has a predetermined first bandwidth, a predetermined gain and a predetermined phase margin, wherein said predetermined first bandwidth is determined by a predetermined conversion gain capacitance; and
using said intermediate frequency signal and a reference signal to generate a common mode feedback signal as an input to said conversion gain module thereby maintaining the phase margin of said intermediate output signal at a predetermined level, wherein said common mode feedback signal is controlled by a common mode feedback capacitance and wherein a portion of said conversion gain capacitance for said conversion gain module is provided by said common mode feedback capacitance.

12. The method of claim 11, further comprising using a gain control module to change the gain of said conversion gain module from a first gain to a second gain, thereby generating an intermediate frequency signal at a second gain, wherein said intermediate frequency signal generated at said second gain has a second bandwidth and using a bandwidth control module to change the bandwidth of said intermediate frequency signal from said second bandwidth to said first predetermined bandwidth.

13. The method of claim 12, wherein said gain of said conversion gain module is changed from said first gain to said second gain by operably coupling a second load resistance to said conversion gain module.

14. The method of claim 13, wherein said first and second gains of said conversion gain module are defined by first and second load resistances of said conversion gain module.

15. The method of claim 14, wherein said second load resistance comprises a predetermined combination of resistors selected from a resistor bank module.

16. The method of claim 15, wherein said change from said first load resistance to said second load resistance is detected by a bandwidth control module that is operable to change the bandwidth of said intermediate frequency signal from said second bandwidth to said first predetermined bandwidth upon detection of said second load resistance.

17. The method of claim 16,
wherein said predetermined first bandwidth and said second bandwidth are defined by first and second RC constants of said conversion gain module, and wherein the resistance component of said first and second RC constants is determined by said first and second load resistances corresponding to said first and second gains, and
wherein said bandwidth control module is operable to connect a capacitance to said conversion gain module to cause said second RC constant to have a value corresponding to said predetermined first bandwidth.

18. The method of claim 17, wherein said conversion gain capacitance comprises a predetermined combination of capacitors in a conversion gain capacitor bank.

19. The method of claim 18, wherein said conversion gain capacitance comprises the common mode feedback capacitance of said common mode feedback module.

20. The method of claim 19, wherein said bandwidth control module is operable to allocate the total conversion gain capacitance between said common mode feedback capacitance and said capacitors in said conversion gain capacitor bank.

21. A wireless interface system that services communications between a wirelessly enabled host and at least one user input device, comprising:
a front end module operable to receive an incoming signal at an RF frequency;
a transceiver module operable to process said incoming signal at an RF frequency and to generate an intermediate (IF) frequency signal therefrom; wherein said transceiver module further comprises:
a conversion gain module operable to receive a radio frequency signal and to generate an intermediate frequency signal therefrom at a predetermined gain and at a predetermined first bandwidth and a predetermined phase margin, wherein said predetermined first bandwidth is determined by a predetermined conversion gain capacitance;
a common mode feedback module operable to receive a reference signal and said intermediate frequency signal and to generate a common mode feedback signal as an input to said conversion gain module thereby maintaining the phase margin of said intermediate output signal at a predetermined level, wherein said common mode feedback signal is controlled by a common mode feedback capacitance and wherein a portion of said conversion gain capacitance for said conversion gain module is provided by said common mode feedback capacitance in said common mode feedback module; and
processing circuitry operable to receive said IF frequency signal and to generate digital data signals therefrom.

22. The wireless interface device of claim 21 wherein the output of said common mode capacitance comprises a selected combination of capacitors in a common mode feedback capacitor bank.

23. The wireless interface device of claim 21 wherein said common mode capacitor bank is controlled by a bandwidth control logic module.

24. The wireless interface device of claim 21 wherein said intermediate frequency output signal is provided to a radio interface that is operably connected to baseband signal processing components, wherein said radio interface is operable to generate a gain control signal to control the bandwidth of said intermediate frequency output signal and wherein said bandwidth control signal is used to select said combination of capacitors comprising said common mode feedback capacitance.

25. The wireless interface device of claim 21, wherein said adaptive mixer further comprises:
a gain control module operable to change the gain of said conversion gain module from a first gain to a second gain, thereby generating an intermediate frequency signal at a second gain, wherein said intermediate frequency signal generated at said second gain has a second bandwidth;
a bandwidth control module operable to change the bandwidth of said intermediate frequency signal from said second bandwidth to said first predetermined bandwidth.

26. The wireless interface device of claim 25, wherein said first and second gains of said conversion gain module are defined by first and second load resistances of said conversion gain module.

27. The wireless interface device of claim 26, wherein said gain control module is operable to change said gain of said conversion gain module from said first gain to said second gain by operably coupling said second load resistance to said conversion gain module.

28. The wireless interface device of claim 27, wherein said bandwidth control module is operable to detect said second load resistance and is operable to change the bandwidth of said intermediate frequency signal from said second bandwidth to said first predetermined bandwidth upon detection of said second load resistance.

29. The wireless interface device of claim 28,
wherein said predetermined first bandwidth and said second bandwidth are defined by first and second RC constants of said conversion gain module, and wherein the resistance component of said first and second RC constants is determined by said first and second load resistances corresponding to said first and second gains, and
wherein said bandwidth control module is operable to connect a conversion gain capacitance to said conversion gain module to cause said second RC constant to have a value corresponding to said predetermined first bandwidth.

30. The wireless interface device of claim 29 wherein said conversion gain capacitance comprises the common mode feedback capacitance of said common mode feedback module.