# Patent

## Title
Integrated circuit with layout matched high speed lines

## Abstract

A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

## Background
RELATED APPLICATION
This is a divisional application of U.S. patent application Ser. No. 09/905,055, filed Jul. 12, 2001, now U.S. Pat. No. 6,571,380, titled “INTEGRATED CIRCUIT WITH LAYOUT MATCHED HIGH SPEED LINES” and commonly assigned, the entire contents of which are incorporated herein by reference.


TECHNICAL FIELD OF THE INVENTION
The invention relates to integrated circuits, and more particularly, to circuits with high speed interconnect lines.
BACKGROUND OF THE INVENTION
As the operating frequencies on modern integrated circuits have become increasingly higher, signal propagation timing constraints have become increasingly stricter. This is particularly the case for synchronous integrated circuits, where signals are expected at interfaces and inputs at specific times. A major source of signal propagation delay in modern integrated circuits is delay from resistive and capacitive loading. This potential for signal propagation delay due to RC loading has become even more of a predominant issue with the decreasing device sizes, spacing, and operating voltages of modern components.
The primary object of most common types of modern integrated circuit construction techniques is to increase operating speed and frequencies of integrated circuit device components by reducing device component sizes and operating voltages. While accomplishing this goal, however, the reduced device sizes decrease interconnect line cross section area, which has the effect of increasing the individual line resistances. The same reduction in feature size reduces the line-to-line spacing, increasing the interconnect line capacitance due to line-to-line capacitance effects. Both these effects adversely influence the RC loading of the interconnect lines in integrated circuits. This increased RC loading interferes with signal propagation speed and increase the likelihood of timing faults when the circuit is in operation.
Line resistance and line-to-line capacitance is particularly an issue in high speed lines that have longer run lengths or drive external buffers. Relatively long run lines typically have high RC time constants because of increased individual line resistance and capacitance, due to line length, line-to-line spacing, and bulk silicon effects. The increased line capacitance and resistance of such long run lines typically require the use of increased line voltage to counteract the increased RC time constant they engender and increase timing constraints.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce line-to-line capacitive effects and increased RC time constants in integrated circuits with reduced feature size. Additionally, there is a need for the ability to reduce interconnect line capacitance, and to have matched delays and RC time constants across grouped long run lines.
SUMMARY OF THE INVENTION
The above-mentioned problems with integrated circuit interconnect resistive and capacitive loading, and other problems, are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit comprises a set of interconnect lines of differing lengths implemented in close physical proximity, and running generally in parallel to each other, wherein the set of interconnect lines comprise, a subset of interconnect lines with a longer parallel run length than average for the set, and a subset of interconnect lines with a shorter parallel run length than average for the set, wherein each member of the subset of shorter run length interconnect lines is routed in between two members of the subset of longer run length interconnect lines, such that a space in between two members of the subset of longer run length interconnect lines left open when the short run line reaches the end of its parallel run length.
In another embodiment, an integrated circuit comprises an active circuit, a set of distributed circuits, and a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, wherein each member of the set of distributed circuits is coupled to at least one member of the set of distributed circuits, and wherein the set of conductors comprises, a subset of generally longer than average conductors, and a subset of generally shorter than average conductors, such that in a plan view each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors wherein a space occupied by the shorter conductor is not filled by another conductor or component when the shorter conductor reaches the end of its generally parallel run length, providing increased lateral separation.
In a further embodiment, a memory device comprises an address interface coupled to a first I/O buffer circuit, a first interconnect circuit coupled to the first I/O buffer circuit and to an address register, a data interface coupled to a second I/O buffer circuit, a second interconnect circuit coupled to the second I/O buffer circuit, a control interface coupled to a third I/O buffer circuit, and a third interconnect circuit coupled to the third I/O buffer circuit, wherein the first, second and third interconnect circuits each comprise a set of interconnect lines of differing lengths, implemented in close physical proximity, and running generally in parallel to each other, a subset of generally longer than average interconnect lines, and a subset of generally shorter than average interconnect lines, such that, in a plan view, each member of the subset of shorter interconnect lines is routed beside a member of the subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length, providing increased lateral separation.
In yet another embodiment, an integrated circuit comprises an active circuit, a set of distributed circuits, and a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, and each conductor having a line resistance, RL, a first capacitance, CB, due to a bulk substrate capacitance, and a second capacitance, CL, due to conductor to conductor capacitance effects, such that each conductor has a RC time constant of RL(CB+CL), and wherein each member of the set of conductors is coupled to the active circuit and to at least one member of the set of distributed circuits, such that the set of conductors comprises a subset of generally longer than average conductors, and a subset of generally shorter than average conductors, wherein an average RC time constant of the set of conductors is reduced by routing each member of the subset of shorter conductors beside a member of the subset of longer conductors, such that a space occupied by the shorter conductor is not filled by another conductor or component when the shorter conductor reaches the end of its generally parallel run length to reducing the second capacitance, CL, due to conductor to conductor capacitance effects.
A method of adjusting an integrated circuit for a reduced conductor capacitance comprises routing a first subset of generally longer conductors of a set of generally parallel and physically proximate conductors, and selectively routing a second subset of generally shorter conductors of the set of generally parallel and physically proximate conductors to reduce conductor to conductor capacitance, such that in a plan view each member of the second subset of generally shorter conductors is routed beside a member of the first subset of longer conductors such that a space occupied by the shorter conductor is not filled by another conductor or component when the shorter conductor reaches the end of its generally parallel run length, providing increased lateral separation.
Another method of adjusting an integrated circuit for a reduced interconnect line RC time constant comprises routing a first subset of generally longer interconnect lines of a set of generally parallel and physically proximate interconnect lines, selectively routing a second subset of generally shorter interconnect lines of the set of generally parallel and physically proximate interconnect lines to reduce interconnect line to interconnect line capacitance, wherein each member of the second subset of generally shorter interconnect lines is routed beside a member of the first subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length, and selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance.
A further method of adjusting an integrated circuit for a reduced conductor capacitance comprises forming a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, with each conductor having a first capacitance, CB, due to a bulk substrate capacitance and a second capacitance, CL, due to conductor to conductor capacitance effects, routing a subset of generally longer than average conductors of the set of conductors, and reducing the second capacitance, CL, due to conductor to conductor capacitance effects by routing a subset of generally shorter than average conductors of the set of conductors, such that in a plan view each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied by the shorter conductor is left open when the shorter conductor reaches the end of its generally parallel run length, providing a larger lateral separation.
An additional method of adjusting an integrated circuit for a reduced interconnect line RC time constant comprises forming a set of interconnect lines of differing lengths implemented in close physical proximity and running generally in parallel to each other with each interconnect line having a line resistance, RL, a first capacitance, CB, due to a bulk substrate capacitance, and a second capacitance, CL, due to interconnect line to interconnect line capacitance effects, such that the interconnect line has a RC time constant of RL(CB+CL), routing a subset of generally longer than average interconnect lines of the set of interconnect lines, and reducing the second capacitance, CL, due to interconnect line to interconnect line capacitance effects by routing a subset of generally shorter than average interconnect lines of the set of interconnect lines, wherein an average RC time constant of the set of interconnect lines is reduced by routing each member of the subset of shorter interconnect lines beside a member of the subset of longer interconnect lines such that a space occupied by the shorter interconnect line is left unfilled when the shorter interconnect line reaches the end of its generally parallel run length.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a prior art integrated circuit, showing high speed interconnect lines, output pads, and an output buffer stage.
FIG. 2 is a diagram of an integrated circuit with an embodiment of the present invention, showing high speed interconnect lines, output pads, and an output buffer stage.
FIG. 3 is a cross section diagram of an integrated circuit with an embodiment of the present invention, showing variable sized cross section interconnects.
FIGS. 4a and 4b are diagrams of additional integrated circuits with an embodiment of the present invention, showing high speed interconnect lines, output pads, and an output buffer stage.
FIG. 5 is a diagram of a memory device incorporating an embodiment of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.
The resistance of a given interconnect line in an integrated circuit is a product of its cross sectional area, resistivity of the material comprising the interconnect line, and the length of the interconnect. The longer an interconnect line, the higher its inherent resistance for a given cross sectional area and material. The larger the cross sectional area, the lower the resistance of the interconnect line for a given length and material. However, increasing the cross sectional area of an interconnect line also has the effect of increasing its inherent capacitance with other components, which can be an undesired result.
In general, there are two sources of capacitance loading for an interconnect line in an integrated circuit, capacitance to the bulk silicon of the integrated circuit, and capacitance to other interconnect lines physically close by. The capacitance of an interconnect line to the bulk silicon of an integrated circuit can be described as a function of permittivity, line width, line length, and the thickness of the oxide insulator layer the interconnect line is placed on. Line-to-line capacitance is an effect that increases with decreasing feature size and line spacing. Line-to-line capacitance is generally a product of line height, line-to-line spacing, permittivity, and the length of the space that the interconnect line is run in close proximity to another line. Line-to-line capacitance is cumulative and has with modern reduced feature size integrated circuits increased to become a non-trivial effect and to be considered with the capacitive effect of the bulk silicon on an interconnect line.
The RC time constant of a given interconnect line that effects the interconnect line's signal delay properties is a product of the inherent line resistance, R, and any inherent line capacitance, C, that is due to both the bulk silicon effects and the line-to-line capacitance. These undesired input RC time constants add to the propagation delay of signals through the circuit at a given signal voltage level, and can cause problems with setup and hold timing requirements for the signal.
FIG. 1 illustrates a simplified example of an integrated circuit of the prior art wherein a series of I/O buffers 100 are coupled to an active integrated circuit 104 with a series of high speed interconnect lines 102. As shown in FIG. 1, the interconnect lines 102 have long segments that parallel in close physical proximity other interconnect lines of the circuit, giving a high line-to-line capacitance component to the inherent line capacitances when the circuit is implemented in a modern reduced feature size integrated circuit. As shown in FIG. 1, the interconnect lines are also of varying lengths and have varying sections where they run parallel to each other. The interconnect lines are generally physically placed on the integrated circuit in order of increasing length, short 101 to long 103, allowing the shorter run interconnect lines to route to their respective destinations before the next longer length interconnect line routes to its destination. This leaves the interconnect lines, which have a shorter length with a smaller line resistance and with smaller capacitance. This capacitance is smaller for both line-to-line capacitance effects and bulk capacitance effects, than that of the longer length interconnect lines. Combined with the larger inherent resistance of the longer interconnect lines, which is larger than that of the shorter interconnect lines, the individual interconnect line RC time constants will vary within the high speed interconnect lines 102 of FIG. 1, with the long run lines having a larger RC time constant than the shorter run interconnects.
FIG. 2 illustrates a simplified example of an integrated circuit with an embodiment of the present invention. In the circuit of FIG. 2, a series of I/O buffers 106 are coupled to an active integrated circuit 110 with a series of high speed interconnect lines 108. As in FIG. 1, the interconnect lines 108 of FIG. 2 have long segments that run in parallel to other interconnect lines of the circuit. However, in the circuit of FIG. 2, the short run lines are placed in between the longer run lines in an alternating short-long-short-long pattern. As the short run lines reach the limit of their run length and fall off to route to their individual destination I/O buffer 106, spacing opens up along side the companion longer run interconnect lines. Because of this, there are not the same large sections where the interconnect lines 108 run in close proximity to each other, as in the integrated circuit of FIG. 1. Therefore, the circuit of FIG. 2 exhibits a smaller median line-to-line capacitance and RC time constant for a set of interconnect lines than that of FIG. 1. The interconnect line RC time constants in the circuit of FIG. 2, are smaller, on average, than a circuit of the prior art, and lead to circuit less signal propagation delay and less timing problems.
FIG. 3 is an illustration of a series of interconnect lines (112, 114, and 116) of an integrated circuit composed of a similar conducting material, typically metal or polysilicon, over a bulk silicon substrate 118. Also shown in FIG. 3 are schematic representations of sources of interconnect line capacitances; line to bulk capacitance (120, 122, and 124) and line-to-line capacitance (126 and 128).
The interconnects (112, 114, and 116) are of differing heights and widths, and therefore are of differing cross sectional area. As stated above, the resistance of an interconnect is a product of its cross sectional area, the resistivity of the material comprising the interconnect line, and the line length. Therefore, the differing cross sectional area of each interconnect line produces a differing interconnect line resistance for a given length. Generally though, the larger the cross sectional area of an interconnect, the lower the line resistance.
Unfortunately, increasing the area of an interconnect will also have the effect of increasing the line capacitance to both the bulk silicon substrate and the line-to-line capacitance. Thus, increasing the cross sectional area of an interconnect line to reduce the line resistance and therefore the RC time constant of the line will meet a point of diminishing returns, where the increased line capacitance will cancel out any reduction in the line resistance in its effect on the interconnect line RC time constant. However, if a balance in this resistance and capacitance is sought, the effect can be used to reduce the overall RC time constant to a minimum for a given interconnect line.
The ability to change the RC time constant of a given interconnect line by adjusting its cross sectional area can also be combined with another embodiment of the present invention as shown in the circuits of FIGS. 4a and 4b. 
In FIG. 4a, a circuit of high speed interconnects is shown, such as in the circuit of FIG. 2. In the circuit of FIG. 4a, a series of I/O buffers 130 are coupled to an active integrated circuit 134 with a series of high speed interconnect lines 132. The interconnect lines 132 of FIG. 4a have long segments that parallel the other interconnect lines of the circuit. As in the circuit of FIG. 2, the shorter lines are alternated between the longer lines. As the short lines reach the limit of their parallel run length and fall off to route to their individual destination I/O buffer 130, spacing opens up along side the companion longer interconnect lines, reducing the line-to-line capacitance effects on the long run lines. In addition, in the circuit of FIG. 4a, the longer run interconnect lines have a larger cross sectional area than the shorter run lines and thus have a lower resistance value per unit length. The longer run interconnect lines are shown heavier 133 in FIG. 4a to illustrate this.
In FIG. 4b, another circuit of high speed interconnects is shown, such as in the circuit of FIG. 2. In the circuit of FIG. 4b, a series of I/O buffers 180 are coupled to an active integrated circuit 184 with a series of high speed interconnect lines 182. The interconnect lines 182 of FIG. 4b have long segments that parallel the other interconnect lines of the circuit. As in the circuit of FIG. 2, the shorter lines are alternated between the longer lines. As the short lines reach the limit of their parallel run length and fall off to route to their individual destination I/O buffer 180, spacing opens up along side the companion longer interconnect lines reducing the line-to-line capacitance effects on the long run lines. In addition, as in the circuit of FIG. 4a, in the circuit of FIG. 4b the longer run interconnect lines have sections of a larger cross sectional area than that of the shorter run lines and thus have a lower resistance value per unit length for those sections. The sections of the longer run interconnect lines are shown heavier 186 in FIG. 4b to illustrate this. In the circuit of FIG. 4b the longer run interconnect lines initially have the same cross sectional area as the short run interconnect lines and flare out 188 to a larger cross sectional area after the short run lines fall off to take advantage of the increased line spacing. Therefore, the longer run interconnects of the circuit of FIG. 4b allow a lower line resistance to be achieved over an interconnect line of similar length. At the same time the longer run interconnects of FIG. 4b avoid an increase in line-to-line capacitance effects due to what would be a closer line spacing because of larger interconnect cross sectional area in the sections where they run in close parallel with the short run lines.
In implementation of the circuits of FIGS. 4a and 4b, a balance should be sought between any gain in capacitance from line cross sectional area, reduction in line-to-line capacitance due to routing, and reduction in line resistance to achieve an optimal interconnect line RC time constant. This time constant can be optimized for a single line of a group of interconnects, or to optimize the average RC of the group of interconnect lines it is utilized on. It is noted that the circuits of FIGS. 4a and 4b are for illustrative purposes and that other approaches for optimizing the RC time constants of a single line or a group of lines with the above techniques will be apparent to those skilled in the art.
FIG. 5 shows an illustration of a non-volatile memory device of an embodiment of the present invention. It is noted that the memory device of FIG. 5 is only shown as an example, and embodiments of the present invention can include multiple types of other integrated circuits (i.e., a processor, a volatile memory device, an ASIC, etc.). Memory devices are well known in the prior art, and the following description is intended only to be an overview of their operation and provide an example of their operation with an embodiment of the present invention.
The non-volatile memory device of FIG. 5 contains an array of nonvolatile floating gate memory cells arranged in columns coupled to bit lines as its main memory structure. In the memory device of FIG. 5, address values for the memory are received on the external address bus connections 136. The received address values are stored internal to the memory device and utilized to select the memory cells in the array to read and write data to. In the case of the memory device of FIG. 5, the internal address register is shown split with both a row address register 138 and column address register 140. The address values held in the row address register 138 and column address register 140 select a data word from the non-volatile memory cell array 142 through the coupled row decode 144 and column decode 146 circuits. The selected data word is read by the coupled sense amplifier circuit 148. Data values for the memory device of FIG. 5 are received and transmitted on the bi-directional data word interface 150. Internal to the memory device, data to be written to or from the memory array 142 is held in the Data buffer 152. Control of the memory device of FIG. 5 for both read operations and write operations is actuated by the internal control circuit 154. The control circuit 154 operates in response external control signals received on control signal external interface connections 156 and to internal events.
As shown in FIG. 5 all external signal connections to the memory device are coupled to internal I/O buffers on the internal integrated circuit chip (158, 160, and 162). I/O buffers are shown for each of the major interfaces, address I/O buffers 162, data I/O buffers 158, and control signal I/O buffers 160. Interconnect lines (164, 166, 168, and 170) are embodiments of the present invention and couple the I/O buffers (158, 160, and 162) to their corresponding active component input circuits that accept the incoming signals. These interconnect circuits will have lower RC time constants for the interconnect circuits and resulting propagation delays for better high speed and synchronous performance. Additionally, the grouped high speed lines in the memory device, the address interface 136, and the data interface 150, can be selectively adjusted to closely match each other in resistance, or capacitance. The RC time constant of an individual interconnect line in a group of high speed lines, for example, a control line, may be adjusted to optimize it for a given timing requirement. Alternatively, the overall RC time constant of the interconnect lines can be adjusted to make the RC time constant/propagation delay of the grouped high speed lines as minimal and as similar as possible for better high speed or synchronous operation.
CONCLUSION
A high speed interconnect line group for an integrated circuit is described, having an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line group incorporates a series of interconnect lines wherein shorter run lines are routed between longer run interconnect lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing on the remaining interconnect lines and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without critically increasing the line-to-line capacitance of these lines and adversely affecting the overall line RC time constant. The described invention allows line capacitances, resistances, and RC time constants to be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform signal propagation delay across all of the optimized group.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

## Claims

1. A memory device comprising:
an address interface coupled to a first I/O buffer circuit;
a first interconnect circuit coupled to the first I/O buffer circuit and to an address register, wherein the first interconnect circuit comprises,
a first set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other,
a subset of generally longer than average conductors of the first set of conductors, and
a subset of generally shorter than average conductors of the first set of conductors,
wherein each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied by each of the shorter conductors is not filled by another conductor or component when each of the shorter conductors reaches the end of its generally parallel run length;

a data interface coupled to a second I/O buffer circuit;
a second interconnect circuit coupled to the second I/O buffer circuit and to a data buffer, wherein the second interconnect circuit comprises,
a second set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other,
a subset of generally longer than average conductors of the second set of conductors, and
a subset of generally shorter than average conductors of the second set of conductors,
wherein each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied by each of the shorter conductors is not filled by another conductor or component when each of the shorter conductors reaches the end of its generally parallel run length;

a control interface coupled to a third I/O buffer circuit; and
a third interconnect circuit coupled to the third I/O buffer circuit and to a control circuit, wherein the third interconnect circuit comprises,
a third set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other,
a subset of generally longer than average conductors of the third set of conductors, and
a subset of generally shorter than average conductors of the third set of conductors,
wherein each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied each of the shorter conductors is not filled by another conductor or component when each of the shorter conductors reaches the end of its generally parallel run length.

2. The memory device of claim 1, wherein the memory device comprises non-volatile memory.

3. The memory device of claim 1, wherein the first, second, and third sets of conductors comprise metal or polysilicon.

4. The memory device of claim 1, wherein a placement in the first, second, and third sets of conductors of each member of the subset of generally longer conductors and subset of generally shorter conductors of the first, second, and third sets of conductors are routed to reduce individual conductor capacitance due to line-to-line capacitance.

5. The memory device of claim 1, wherein a placement in the first, second, and third sets of conductors of each member of the subset of generally longer conductors and subset of generally shorter conductors are placed to reduce an average RC time constant of the first, second, and third sets of conductors by selectively adjusting individual conductor capacitance due to line-to-line capacitance effects.

6. The memory device of claim 1, wherein a placement in the first, second, and third sets of conductors of each member of the subset of generally longer conductors and subset of generally shorter conductors are placed to reduce an average RC time constant of the first, second, and third sets of conductors by selectively adjusting individual conductor capacitance due to conductor to line capacitance effects and selectively adjusting inherent line resistance due to cross sectional area.

7. The memory device of claim 1, wherein a placement in the first, second, and third sets of conductors of each member of the subset of generally longer conductors and subset of generally shorter conductors are placed so as to reduce an average RC time constant of the first, second, and third sets of conductors by selectively adjusting individual conductor capacitance due to conductor to line capacitance and selectively adjusting inherent line resistance due to cross sectional area of the subsets of generally longer conductors.

8. The memory device of claim 1, wherein a placement in the first, second, and third sets of conductors of each member of the subset of generally longer conductors and subset of generally shorter conductors are placed so as to reduce an average RC time constant of the first, second, and third sets of conductors by selectively adjusting individual conductor capacitance due to conductor to line capacitance and selectively adjusting inherent line resistance due to a cross sectional area of the subsets of generally longer conductors such that the cross sectional area of each member of the subsets of generally longer conductors is increased after the shorter conductors routed beside them reach the end of their generally parallel run length.

9. A memory device comprising:
an address interface coupled to a first I/O buffer circuit;
a first interconnect circuit coupled to the first I/O buffer circuit and to an address register;
a data interface coupled to a second I/O buffer circuit;
a second interconnect circuit coupled to the second I/O buffer circuit;
a control interface coupled to a third I/O buffer circuit; and
a third interconnect circuit coupled to the third I/O buffer circuit, wherein each of the first, second and third interconnect circuits each comprises,
a set of interconnect lines of differing lengths implemented in close physical proximity and running generally in parallel to each other,
a subset of generally longer than average interconnect lines, and
a subset of generally shorter than average interconnect lines,
such that in a plan view each member of the subset of shorter interconnect lines is routed beside a member of the subset of longer interconnect lines such that a space occupied by each of the shorter interconnect lines is not filled by another interconnect line or component when each of the shorter interconnect lines reaches the end of its generally parallel run length, providing increased lateral separation.

10. The memory device of claim 9, wherein the memory device comprises non-volatile memory.

11. The memory device of claim 9, wherein the sets of interconnect lines of the first, second, and third interconnect circuits comprises metal or polysilicon.

12. The memory device of claim 9, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected to reduce an average RC time constant of the first, second, and third sets of interconnect lines by selectively adjusting individual interconnect line capacitance due to line-to-line capacitance effects.

13. The memory device of claim 9, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected to reduce an average RC time constant of the first, second, and third sets of interconnect lines by selectively adjusting individual interconnect line capacitance due to interconnect line-to-line capacitance effects and selectively adjusting inherent line resistance due to cross sectional area.

14. The memory device of claim 9, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected so as to reduce an average RC time constant of the first, second, and third sets of interconnect lines by selectively adjusting individual interconnect line capacitance due to interconnect line-to-line capacitance and selectively adjusting inherent line resistance due to cross sectional area of the subsets of generally longer interconnect lines.

15. The memory device of claim 9, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected so as to reduce the average RC time constant of the first, second, and third sets of interconnect lines by selectively adjusting an individual interconnect line capacitance due to interconnect line-to-line capacitance and selectively adjusting inherent line resistance due to cross sectional area of the subsets of generally longer interconnect lines such that a cross sectional area of each member of the subsets of generally longer interconnect lines is increased after the shorter interconnect lines routed beside them reach the end of their generally parallel run length.

16. A memory device comprising:
an address interface;
a first interconnect circuit coupled to the address interface;
a data interface;
a second interconnect circuit coupled to the data interface;
a control interface; and
a third interconnect circuit coupled to the control interface, wherein at least one of the first, second and third interconnect circuits comprise,
a set of interconnect lines of differing lengths running generally in parallel to each other,
a subset of generally longer than average interconnect lines, and
a subset of generally shorter than average interconnect lines,
such that in a plan view members of the subset of shorter interconnect lines are routed beside members of the subset of longer interconnect lines such that a space occupied by each of the shorter interconnect lines is not filled when each of the shorter interconnect lines reaches the end of its generally parallel run length.

17. The memory device of claim 16, wherein the memory device comprises non-volatile memory.

18. The memory device of claim 16, wherein at least one of the sets of interconnect lines of the first, second, and third interconnect circuits comprise metal or polysilicon.

19. The memory device of claim 16, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected to reduce an average RC time constant of the set of interconnect lines by selectively adjusting individual interconnect line capacitance due to line-to-line capacitance effects in at least one set of interconnect lines of the first, second, and third sets of interconnect circuits.

20. The memory device of claim 16, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected to reduce an average RC time constant of the set of interconnect lines by selectively adjusting individual interconnect line capacitance due to interconnect line-to-line capacitance effects and selectively adjusting inherent line resistance due to cross sectional area in at least one set of interconnect lines of the first, second, and third sets of interconnect circuits.

21. The memory device of claim 16, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected so as to reduce an average RC time constant of the set of interconnect lines by selectively adjusting individual interconnect line capacitance due to interconnect line-to-line capacitance and selectively adjusting inherent line resistance due to cross sectional area of the subset of generally longer interconnect lines in at least one set of interconnect lines of the first, second, and third sets of interconnect circuits.

22. The memory device of claim 16, wherein a placement of each member of the subset of generally longer interconnect lines and subset of generally shorter interconnect lines is selected so as to reduce an average RC time constant of the set of interconnect lines by selectively adjusting individual interconnect line capacitance due to interconnect line-to-line capacitance and selectively adjusting inherent line resistance due to cross sectional area of the subset of generally longer interconnect lines such that the cross sectional area of each member of the subset of generally longer interconnect lines is increased after the shorter interconnect lines routed beside them reach the end of their generally parallel run length in at least one set of interconnect lines of the first, second, and third sets of interconnect circuits.

23. A memory device comprising:
an interconnect circuit, wherein the interconnect circuit comprises,
a set of interconnect lines of differing lengths running generally in parallel to each other,
a subset of generally longer than average interconnect lines, and
a subset of generally shorter than average interconnect lines,
such that in a plan view members of the subset of shorter interconnect lines are routed beside members of the subset of longer interconnect lines such that a space occupied by each of the shorter interconnect lines is not filled when each of the shorter interconnect lines reaches the end of its generally parallel run length.

24. The memory device of claim 23, wherein the memory device comprises non-volatile memory.

25. The memory device of claim 23, wherein the set of interconnect lines comprise metal or polysilicon.