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NBS TECHNICAL NOTE 1067

•

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

Reference Flat Pulse Generator
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards' was established by an act of Congress on March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology

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the Institute for Computer Sciences and Technology.

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'Headquarters and Laboratories at Gaithersburg, MD, unless otherwise noted; mailing address Washington, DC 20234. 'Some divisions within the center are located at Boulder, CO 80303.
Reference Flat Pulse Generator

J. R. Andrews

B. A. Bell

E. E. Baldwin

Electromagnetic Fields Division

National Engineering Laboratory

National Bureau of Standards

Boulder, Colorado 80303

U.S. DEPARTMENT OF COMMERCE, Malcolm Baldrige, Secretary

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director

#,.-., iOIiAL BU5EA

s pf STANDARDS

LIBRARY

\0

"Ho, )0&

1^3

Issued October 1 983
National Bureau of Standards Technical Note 1067

Natl. Bur. Stand. (U.S.), Tech. Note 1067, 72 pages (Oct. 1983)

CODEN: NBTNAE

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1983

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402

Price $4.50

(Add 25 percent for other than U.S. mailing)
CONTENTS

Page

1. Introduction 1 1.

1

Background 1 1.2 Object i ves 2

1. 3 Report Organization 2

2. Basic Design Techniques 2

2. 1 Pri or Methods 2 2.2 Present Approach 6

2. 3 Prel i mi nary Specifications 9

3. Circuit Diagrams and Description 10 3.1 Clock, Delay, and Pulse Duration Circuits 10 3.2 Current-Switching Output Stages 10

3. 3 Power Suppl ies , 18

4. Modeling and Computer Simulation 18 4.1 Use of Extended-SCEPTRE 18 4.2 Simple Diode Circuit Analysis via Program TEST 20

4.3 Initial Modeling via Program RFPG 25 4.4 ECL Drive and Transistor Switching Model via Program TRAN 30 4.5 The Total Model via Program TRFPG 39

5. Summary 49

6. References 50 Appendix A. Flat Pulse Generator Parts List 51 Appendix B. Alignment/Calibration Procedures 56 Appendix C. Measurements of the Effective Time Constant ( Tg i

)

for the BFR 90 Transistor 58

Appendix D. Collector Capacitance Equivalency 63

i n

Reference Flat Pulse Generator

J. R. Andrews,* B. A. Bell,** and E. E. Baldwin 1

"

National Bureau of Standards

Boulder, Colorado 80303

A reference step-like pulse generator is described which has been developed at NBS. This generator can be used for accurately characterizing the step response of various kinds

of transient recording equipment (oscilloscopes, waveform recorders, transient digitizers,

etc.)- Basic design principles are given as well as complete circuit diagrams and descriptions. An analysis of the output stage of the generator is presented together with

the circuit models for developing a time-domain computer simulation program using extendedSCEPTRE. Preliminary specifications indicate that the NBS Reference Flat Pulse Generator

provides a negative-going reference transition duration (90 to 10 percent) of 600 ps, ±20

percent with baseline perturbations of less than ±2 percent for less than 5 ns.

Key words: available waveform; baseline; circuit analysis; flat pulse generator; modeling;

pulse delay; step response; topline; transfer standard; transition duration.

1. Introduction

1.1 Background

The need for a reference step-like waveform generator has become increasingly important for ac- curately characterizing the step response of oscilloscopes, transient recorders, and fast sampling

channels of digital measurement instruments and automatic test equipment (ATE). The measurement sys- tem response can be subtracted from the reference waveform to give the measurement system distortion

explicitly as a function of time (dynamic performance error). Equi valently , the reference waveform

can be deconvolved from the response of the measurement system (to the reference waveform) in order to obtain the system impulse response. Here and in the remainder of this technical note a nominal load

impedance of 50 Q has been assumed. When the load impedance is not 50 £2, additional analysis is re- quired (see, for example, ref. 1). By comparing the measurement waveforms and/or data with that of a reference waveform, the fidelity with which the measurement system can acquire the waveform can be

determined. The dynamic performance of a measurement system is often desired, together with its ability to measure dc or steady-state quantities.

For example, it is well known that skin effect losses in shielded conductors and coaxial cables cause their step response to approach a final dc level asymptotically [2,3]. Since all physically

realizable measuring devices require connectors, cables, wires, etc., transmission line effects on fast input signals are bound to occur. Hence, any measurement system will cause a certain amount of

distortion to an applied signal which causes the acquired waveform to differ.

From a practical point of view, it is often desirable to be able to calibrate the dc voltage

levels of the measurement system, as well as any time-dependent parameters. For this reason a voltage

* Presently with Picosecond Pulse Labs, Inc., P.O. Box 44, Boulder, Colorado.

**Electrosystems Division, National Engineering Laboratory.

t Formerly with the Electromagnetic Technology Division, National Engineering Laboratory.

''Certain commercial equipment, instruments, or materials are identified in this paper in order to adequately specify the experimental procedure. Such identification does not imply recommendation or endorsement by the National Bureau of Standards, nor does it imply that the materials or equipment

identified are necessarily the best available for the purpose.
step function, whose beginning and ending dc levels are cal ibratable, has considerable merit as a reference standard, particularly if the transition between these two levels is also well-behaved and

predictable. Such was the purpose for developing a Reference Flat Pulse Generator (RFPG) in the Electromagnetic Waveform Metrology Group at NBS [4].

1.2 Objectives

The main objective of developing an RFPG was to design, build, and model a pulse generator standard which can provide a step-like pulse waveform of known amplitude and flatness, together with a predictable transition duration between levels. Such a standard can then be used for the alignment

and calibration of pulse waveform measuring instrumentation.

As shown in figure 1-1, the step response of, say, an oscilloscope typically contains three

regions of interest in specifying its dynamic accuracy. The first one is the transition region in

which the important parameter is the transition duration, t

p (often referred to as rise time), which

is the time required for the response to pass from the proximal (or 10 percent) level to the distal

(or 90 percent) level [5], It is oftentimes difficult to ascertain the 10 and 90 percent levels of

input waveforms with sloping baselines and toplines. The calibratable beginning and ending levels

(topline and baseline, respectively) of the RFPG avoids this difficulty.

The second region of interest is the perturbation region immediately following the transition.

Ideally, the step response should smoothly and monotonical ly rise to the final dc (100 percent) level

and remain there. In practice, there are usually some small bumps, wiggles, overshoot, ringing, etc. This region is usually described by the peak-to-peak amplitude, V , of the ringing (as a percentage of

the full-scale step), and the time interval, t , required for the perturbations to disappear.

The third region of interest typically lasts over a relatively long settling time, t

s

, wherein

the response converges to (and stays within) a specified accuracy of the final dc value. Depending on charge storage and nonlinear saturation effects in the measurement and display circuits, and on the

closeness to the final dc level, this parameter can be difficult to determine [6]. As shown in figure 1-1, t„ and t

s are both usually measured starting at the mesial (or 50 percent) level of the step

response.

1.3 Report Organization

This report is divided into six sections and four appendices. Following this introductory sec- tion, sections 2 and 3 describe the design techniques, circuit details, and preliminary specifications

of the RFPG. Section 4 contains the circuit modeling, selected program listings, and computersimulated waveforms for analyzing the subject generator using SCEPTRE [7]. Appendix A contains the

list of parts used in the RFPG module. Appendix B provides the alignment procedure for making adjustments to the generator as a source for calibration purposes. Appendix C describes time constant meas- urements taken on rf switching transistors. Appendix D gives an analysis for approximating equivalent

capacitors.

2. Basic Design Techniques

2.1 Prior Methods

To date, there has not been available a flat pulse generation method which allows accurate determination (on a stable dc basis) of both the baseline and topline levels and wel 1 -characteri zed transition and perturbation regions (see fig. 1-1). Manufacturers - in the past have built step generators
Ideal input step function

time

Expanded vertical scale

Figure 1-1. Anatomy of a step-like pulse.

3
with varying success. In the subnanosecond region, tunnel diodes [8] or mercury wetted mechanical

switches [9] have typically been used. Tunnel diodes provide the fastest switching times, with 20 ps being typical. Such diodes provide low-level pulses of the order of 1/4 V. Their major limitation is the long-term sag in their output voltage due to internal heating of the junction. Thus, they cannot

be used for accurate calibration transfer from dc.

High voltage (tens to hundreds of volts) pulses can be generated using mercury switches. Transition durations as short as 39 ps have been obtained [10]. Disadvantages of mercury switches are: low

repetition rates, typically line frequency (60 Hz), limited life times, and pulse amplitude instabilities of the order of a percent. Another more subtle problem stems from the use of transmission lines

in the pulse generator design. A typical mercury switch pulse generator, figure 2-1, consists of a dc power supply, a charging resistor R

c

, a coaxial cable of impedance R Q with electrical delay length T

D and the switch [T

D

= 2£/(V

p

• C) where I is the cable length in meters, V

p is the propagation factor

in percent, and C is the speed of light in meters per second]. The cable is initially charged to the

voltage Vl^. When the switch is closed the line is discharged into the load resistor R|_. Ideally, if

R|_ = R

Q

then a rectangular output pulse will be produced [11]. The amplitude would be 1/2 Vbb and the

duration would be 2TD. This concept should produce an ideal pulse amplitude standard related precisely to a dc measurement of V^. In practice, there are problems. First, R Q

is usually not well

known, closer than perhaps one percent. Second, owing to skin effect and dielectric losses, real cables introduce significant pulse distortion which alters the waveshape from the ideal rectangular

pulse and reduces the amplitude.

Earlier work at NBS addressed the problems of sag and distortion [10]. One of the common design

defects with conventional pulse generators is the varying load on the generator's power supplies as the output pulse changes state. Depending on the dynamic regulation of the power supply, aberration

in the form of sag may appear in the generated topline and/or baseline.

One technique used by Andrews [10,12] to obtain a flac pulse consisted of a simple diode switch

(fig. 2-2). Initially, the switch S. (in reality a PNP transistor operated in saturation or cutoff)

is open. The constant current I. passes through the diode and R , producing the generator baseline

voltage -I R,» When the switch S is closed, the diode becomes reverse biased, thus disconnecting I Q from R . The output voltage thus changes rapidly to its topline value of zero volts. The pulse

generator system has a source resistance equal to R,. A constant current I. is always drawn from the

independent power supply -V. Thus, the topline and baseline determining elements are completely free

from power supply dynamic regulation problems. The only uncertainty in this circuit is in the transition region due to the switching transients of S. and the charge storage time in the diode. By using

a Schottky diode, the charge storage time may be minimized. With this circuit very flat pulses were obtained 20 ns after the positive-going transition.

To extend the flat pulse concept to the subnanosecond region, the mercury wetted switch was attractive [11]. Figure 2-3 shows such a flat pulse generator. Again, the power supply (+V) provides

a constant current I Q

, regardless of the switch condition (open or closed). With the switch open, the

baseline is zero volts. When the switch closes, the generator topline is I R . The equivalent generator source resistance is R.. Unfortunately, the disadvantages of the mercury switches, as mentioned

earlier, limited this approach.

Both of the above flat pulse generators also avoided the use of coaxial cables and their attendant distortion problems. Instead, the principle of design is the use of constant current sources steered to and away from the output load terminal via high-speed switching. The use of this technique
VL A For R L = R :

1/2 Vbb

h*-TD ^| time

H,

x

L

Rc

vw oa

Ro &

Rc »Ro

o—oRi

Figure 2-1. Typical mercury switch pulse generator.

Output —

Vbaseline= -, R 1 Vtopline =

Rgen = Ri

RFigure 2-2. Diode switch flat pulse generator.

^baseline =

vtopline= '0 R 1 Output Rgen = R 1

Figure 2-3. Mercury switch flat pulse generator.
was recognized and implemented by Andrews in 1970 [12]. Figure 2-4 shows the basic design of the

generator consisting of a constant current source I feeding the R, resistor having a typical value of

50.0 u. The L current source is turned off by means of the control gate so that a stable topline on the voltage output pulse is formed by I through R . When the control pulse turns on current source

I such that

l

i - \ - V

then the current flow to R, is zero, so that the baseline voltage is (ideally) zero. By using the

turn-off of an active device (I

2

), the transition in the output waveform is limited by the inherent

device switching speed and output capacitance. Flat-top pulses having a transition duration (10 percent to 90 percent) of about 2 ns with around 5 percent to 10 percent aberrations were obtained by

this method.

2.2 Present Approach

The present design approach used in the RFPG is shown in figure 2-5. The technique is very similar to the earlier concepts, particularly the one shown in figure 2-4. Two major improvements are provided, however, by the present approach with (1) inclusion of the output diode, and (2) control of the negative current source by means of switches SI and S2. The switching at t = t. causes rapid turn

off of the output diode by steering I down through switch S2. A stable baseline voltage of essentially zero volts is produced equal to the leakage current of the diode through R in parallel with R|_

(typically, -100 nA • 25 ft = -2.5 pV). With switch SI closed and S2 open, the upper positive constant

current source is steered through the output diode providing a constant, and therefore cal ibratable,

topline voltage of I Q through R

1 in parallel with R

L (typically, +20 mA • 25 Q = +500 mV). The rapid

transition from the topline to the baseline (less than 1 ns in the present RFPG), is caused by both

the use of fast, rf-switching transistors for SI and S2 and the sudden reverse bias seen by the output

diode. For best results, the diode is a passivated, Schottky barrier type having low turn-on voltage

and fast, charge-storage recovery time. Thus, this basic approach produces a fast step-like waveform

generator having two known output levels with a constant output impedance R..

The actual electronic circuit used to implement this approach is shown symbolically in figure

2-6. Q8 functions as the dc current source I dc . Ql and Q2 are the switches SI and S2. Ql and Q2

form an emitter-coupled differential-switch pair. They are driven in push-pull by the complementary

outputs of an ECL logic OR gate U13. Q3 is the current source for the emitters of Ql and Q2. I e must

be greater than I dc . Initially, the base of Ql is an ECL "1" (-0.9 V) and the base of Q2 is an ECL

"0" (-1.7 V). Thus, Q2 is off and Ql is on, conducting all the emitter current I e to ground. The current I dc from Q8 all passes through CR3 to R creating an open circuit output of 1.00 V (20 mA

x 50 a,). CR3 is conducting while CR2 is reverse biased and nonconducting. At t = t

Q U13 receives a pulse. The complementary outputs from U13 rapidly switch Ql off and Q2 on. Q2 now conducts all of the 30 mA emitter current I„. Thus, the collector of Q2 tries to pull 30 mA from the node connecting

CR3, CR2, and Q8. The only way for the nodal currents to balance is for Q8 to supply 20 mA, CR3 to become nonconducting, and CR2 to turn on and supply 10 mA. Thus, the desired function of turning off

CR3 and disconnecting I dc from the output is accomplished.

In actual practice, only the negative-going transition from 500 mV to -2.5 pV is considered as the reference step transition. It is far easier to control the transient behavior of CR3 turning off

than when it is turning back on. Figure 2-7 is a pair of photos taken of the main output pulse from

the RFPG.
+ v

ii = lo

Control

gate I

^baseline -

Vtopline = IfjRl Rgen = Rl

Pulse out

Control pulse

Ri II

"2 = l0

-V

Figure 2-4. Stable reference flat top pulse generator.

+ v

lo

S2

t = t

Output

1 °~"1

Rgen — Rl vtopline = InFMopen circuit) = Io(RiI|Rl) •baseline = n 8

-V

Figure 2-5. Present RFPG switching technique.

r

+ v

Q8.

CR2

J-L IT

ECLOR_J~|_

l dc = 20mA. CR3

rr&—W—r

i_r *

Rg < 50Q

l T sO [Q1 Q2l 1 ""

Gate

vtopllne = RQldc

Vbaseline — ~~ ^S'leakage SO

r

t

Q3l

l e = 30mA.

-V

Figure 2-6. Output stage of the RFPG.
(a) (b)

Figure 2-7. Photos of the main PULSE output from the prototype RFPG.

(a) 100 mV/cm--vertical sensitivity; 1 ns/cm--horizontal time base.

(b) Same vertical sensitivity with expanded 200 ps/cm time base.

10MHz

Crystal-based

clock circuit

Count-down,

pulse-width &

pulse-delay

circuits

r

Repetition

rate control

1kHz-1MHz

Currentswitched

output stage

Push-pull

ECL drive

-^-

Main pulse

delay control

0,100,200,300ns

Currentswitched

output stage

3.5 mm

| 50Q

coax

3.5mm

coax

50Q

Delayed main

output PULSE

50Q

TRIGGER pulse

50Q

Figure 2-8. Block diagram of complete RFPG.
A block diagram showing the complete RFPG is given in figure 2-8. The current-switched output

stage, of course, is critical in producing the reference step-like output waveform, and has been

briefly described above. The output pulse across the 50 o. generator source resistor is coupled to the

front panel N type connectors via nominal 50n, 3.5 mm rigid coaxial lines. A trigger output pulse is also provided from an identical output stage. It has the same specifications as the delayed main output pulse, except for a 50 percent duty cycle (10 percent duty cycle for the main pulse). A 10 MHz

crystal -based clock circuit is counted down to provide for selectable pulse repetition rates with

appropriate pulse-durations and selectable pulse delays for the main output pulse. The rep. rates,

delays, and duty cycles are all determined by digitally counting the 10 MHz (100 ns) clock pulses.

These circuits are implemented in emitter-coupled logic (ECL) to provide fast transition edges with

minimum jitter, particularly between the push-pull ECL drive to the current-switched output stages.

Figure 2-9 above shows the front panel of the NBS Reference Flat Pulse Generator.

2.3 Preliminary Specifications

Specifications are common to the pulse output and the trigger output unless noted otherwise.

Baseline: 0.00 V + 10 pV

Topline: 1.00 V open circuit, ±0.1 percent

Source impedance: 50.0 n, +0.5 percent

Reference transition: negative-going

Reference transition duration: 600 ps (90 percent to 10 percent), ±20 percent

Perturbations: Less than ±2 percent lasting for 5 ns or less

Second transition duration: 2 ns (10 percent to 90 percent), ±20 percent

Trigger to pulse delay: Selectable ns, 100 ns, 200 ns, or 300 ns, ±1/2 ns Jitter: 25 ps or less

Repetition rate: Selectable 1 MHz, 100 kHz, 10 kHz, or 1 kHz, ±0.01 percent

Duty cycle: 10 percent for pulse

50 percent for trigger

Internal working standards: 10 MHz crystal oscillator for time base

LM399H active zener for dc voltage

Selected 50 £2, SMA, microwave termination

Connectors: Type N female

Controls: Mode 0V, dc (1 V O.C.), or pulse

Construction: TEK TM500 single-wide plug-in kit

Power requirements: Supplied by TM500 main frame

Figure 2-9. Front panel of the NBS Reference Flat Pulse Generator.
3. Circuit Diagrams and Description

3.1 Clock, Delay, and Pulse Duration Circuits

Figure 3-1 is the circuit diagram for the clock, delay, and duration circuits. Figures 3-2

through 3-5 are the timing diagrams. The internal time standard for the generator is a 10 MHz crystal

oscillator Ul. The first section Ula provides a dc reference voltage to bias the second section Ulb

as a linear amplifier. The second section is a modified form of Colpitts crystal oscillator. The

third section Ulc provides squaring and buffering.

The 10 MHz clock is used to toggle a chain of 95H90 divided by 10 ICs, U2-U5. These counters

provide the basic repetition rates of the generator. Sla is used to select either 1 MHz, 100 kHz,

10 kHz, or 1 kHz. The output from Sla is labeled RESET. All the remaining logic functions are initiated by the negative going transition of the RESET square wave.

RESET and CLK are applied to the NOR gate U6a. When RESET goes to a "0", U6a then passes the

10 MHz CLK pulses creating the GATED CLK signal. The first GATED CLK pulse toggles a "1" into the

Trigger D flip-flop U7a. The Q output is the TRIG signal.

The pulse delay function is obtained by successively dividing the GATED CLK pulses using divide

by 2 flip-flops U7b and U8. The appropriate positive transition for ns, 100 ns, 200 ns, or 300 ns delay is selected via S2 and used to toggle a "1" into U9a, a D flip-flop. The Q output is the DELAYED PULSE. The R-C networks (Rl, C6, and C7; R2 and C8; and R3, C9, and C10) are adjustable delay

networks used to compensate for the propagation delays in the various delay ICs.

The specifications call for a 10 percent duty cycle for the pulse output. Thus, the duration of

the DELAYED PULSE is to be 100 ns, 1 us, 10 us, or 100 us, depending upon the repetition rate selected. This duration is accomplished by counting the appropriate number of 10 MHz clock pulses and

then clearing (pin 1) flip-flop U9a. When DELAYED PULSE goes to a "0", gate U6c then passes the GATED

CLK pulses to a chain of divide by 10 dividers, U10 to U12. The output of the appropriate divider is

selected by Sib and used to toggle a "1" into flip-flop U9b. The Q output from U9b clears U9a and

also U7b and U8 through the OR gate U6b. U7a and U9b are cleared by the positive transition of the

RESET square wave. Incidentally, this action causes the duty cycle of the trigger pulse to be 50 percent. RESET is also passed through U6b to ensure that U7b and U8 are reset properly at initial poweron.

The TRIG and DELAYED PULSE signals are passed through separate buffers U13 and U14 to provide

complementary, push-pull ECL drive to the trigger and pulse output stages. The operating states of these buffers are controlled by the MODE switch S3.

3.2 Current-Switching Output Stages

Figure 3-6 is the schematic diagram of the output stages. These stages are identical; therefore,

we will only discuss the trigger output stage. Section 2.2 described in detail the operation of this

particular circuit using the symbolic diagram in figure 2-6.

U15 is the internal dc voltage working standard. It is a temperature-controlled, active zener

voltage reference. U16, Q7, and Q8 function as the 20 mA dc current source. A dc voltage differential of 2 V between the +12 V bus and the (+) input to U16 is set by potentiometer R17. U16 forces

the potential across R20 to also be 2 V, thus establishing the emitter current of Q8 to be 20 mA. Due

to the high 3 (300 x 200) of the Darlington pair, Q7 and Q8, the composite collector current is almost

identically the same as the 20 mA emitter current.

10
DC

LU

LU

O

00

O

13 DC

Q. 1-

>15o

-t-> TOe

cuo

00

a;

11
Reset (U6-9)

CLK (Ul-7)

Gated Clock

(filtered; U7-15)

TRIG (U7-2)

DELAY

(U9-3)

Delayed pulse (U9-3)

U6-2

U9-6

Gated clock (U6-8)

Figure 3-2. Timing diagrams for 1 MHz repetition rate, ns delay.

12
Reset (U6-9)

Gated clock (U6-8)

TRIG (U7-2)

U7-6

U8-2

Delay (U9-15)

Delayed pulse (U9-3) =~=i^

U6-2

U9-6

U6-6

Figure 3-3. Timing diagrams for 1 MHz repetition rate, 100 ns delay.

13
Reset (U6-9)

Gated clock (U6-8)

TRIG (U7-2)

U7-6

U8-2

Delay (U9-15)

Delayed Pulse (U9-3)

U6-2

U9-6

U6-6

Figure 3-4. Timing diagrams for 1 MHz repetition rate, 200 ns delay.

14
Reset (U6-9)

Gated clock (U6-8)

TRIG (U7-2)

U7-7

U8-7

Delayed pulse (U9-3]

U6-2

U9-6

U6-6

Figure 3-5. Timing diagrams for 1 MHz repetition rate, 300 ns delay.

15
>

CM

>IT) CO

CO

10

CUcn

+->

C3

Q.

CD

o

oo

U3

CO

--JUU

16
DC

LUqO q;L1J DL O -1 r—W-

—

a.

0)

01

17
A less complex current source is used for the 30 mA emitter current for the differential switches

Ql and Q2. Q3 is the current source. CR1 is an LED which provides a 1.6 V reference voltage. This

reference, minus Q3's base-emitter drop of 0.6 V sets the voltage across R5 at 1 V. This voltage in turn forces the emitter current of Q3 to be 30 mA. The collector current of Q3 is also approximately

30 mA.

The other miscellaneous components are used primarily to control the switching transition. R32

and R33 improve the switching times of U13. L5 increases the output impedance of Q3 at high frequencies. R6 and L4 perform a similar function for Q7 and Q8. R35 and C13 eliminate a small amount of

damped ringing present in Q7 and 0.8. R34 and C40 eliminate a minor overshoot in the output waveform.

3.3 Power Supplies

Figure 3-7 is the schematic diagram of the power supplies for the generator. The requirements

are: +12 V at 45 mA, +15 V at 55 mA, and -5.2 V at 1 A (1.4 A worst case). The TM-500 mainframe is used to supply raw dc and ac power. The +33 V supply is first preregulated to +20 V using VR1, VR2,

and a mainframe pass transistor. The +20 V is then dropped to +15 V using U18. U19 further drops the

+15 V to +12 V. -5.2 V is supplied by three separate IC regulators, U20 through U22. The connections

to the output stages and various ECL circuits are such as to evenly distribute the load currents. The

top and bottom rails of the plug-in module housing the RFPG circuit card are used as heat sinks for

U18 through U22.

4. Modeling and Computer Simulation

4.1 Use of Extended-SCEPTRE

The motivation for doing computer analysis and simulation of the RFPG is that in order to have a waveform generator standard, one needs a theoretical basis for how the electronics generate the various electrical waveshapes. Circuit modeling, using known or measured parameters for the circuit

model, allows one to approximate the actual results and thereby predict the circuit performance from

basic principles.

The circuit analysis programs developed for the RFPG were written using extended-SCEPTRE. The

host computer for the extended-SCEPTRE software was a Control Data Corporation CYBER 170, model 750

system. Waveshape generation by computer simulation of the RFPG was conveniently obtained by accessing the CYBER 170 via a graphics terminal over a multiplexed hardwired link at 9600 baud. A FORTRAN

66 program known as DISSPLA, available on the CYBER 170, provided the capability for plotting the

transient analysis data obtained from a SCEPTRE run.

Besides the SCEPTRE application programs themselves, described in detail in the following sec- tions, other procedural program's were utilized. For example, a FORTRAN program was available, known

as PL0TSCP, which accessed the tape containing data from a SCEPTRE run, as well as the DISSPLA program, and provided options for title on graph, start and stop times, independent and dependent

variables, number of available points, running average, vertical scaling, etc. Another program, similar to PL0TSCP, was utilized for outputting data via a terminal having a paper tape punch.

Figure 4-1 shows the outline of a typical SCEPTRE program. Between the /JOB and /E0R statements

are typically a number of FORTRAN command instructions which set up the batch processing procedures

needed by the CYBER 170/750 system. The remainder of the program has somewhat of a fixed format with

the various headings shown. Getting the proper entries under each of these headings is the main problem towards generating a successful SCEPTRE program.

18
PROGRAM NAME

/JOB

Batch

1 Processing

Procedures

/EOR

CIRCUIT DESCRIPTION

ELEMENTS

DEFINED PARAMETERS

OUTPUTS

FUNCTIONS

EQUATIONS

TABLES

INITIAL CONDITIONS

RUN CONTROLS

END

Figure 4-1. Typical SCEPTRE program.

19
For the purpose of modeling the RFPG, the ability to utilize time-dependent, nonlinear circuit

elements provided for in SCEPTRE was essential [13]. In particular, primary dependent current sources

for ideal diodes proved to be especially convenient when combined with voltage or current dependent

capacitors. Secondary dependent current sources with nonlinear, table-entered, dependencies permitted

the development of an accurate model for the rf-switching transistors used in the output stage of the

RFPG.

Run controls for the SCEPTRE programs were relatively simple in that transient solutions were the

only mode of analysis desired. Consequently, a stop time is the only required entry to specify the

desired time interval for analysis. However, because the Runga-Kutta integration method was found to typically give the best results, this routine was also called for under the run controls section of

the programs.

4.2 Simple Diode Circuit Analysis via Program TEST

As a simple example of using SCEPTRE for modeling transient response, figure 4-2 shows the

SCEPTRE circuit for a diode in series with a load resistor, R. The diode is first modeled by its

dynamic forward resistance, r, junction capacitance, C, and package inductance, L. El is the driving

node voltage which is a time function, entered in the program by means of a table. By analogy to the

RFPG output stage, this is a very simple model of the switching mode for the current sources and the

output diode in series with the generator source resistor (in parallel with the output load resistor).

Hence, by assuming appropriate initial conditions (voltage on C and current through L), we can simulate the output voltage across R for various input time functions of El.

E1T is the driving node

voltage time function

9

r

I c

'+ ,D I ® | ^

L

i DIODE ? " ©"

R

When using lp = lo(expevD-l)

r = [0Od+Io)]- 1

= 0Id

Transfer function:

\ _ Q>Cs + 1

El

f r u 2 ,L+Kru

In—JLCs + (— J s + 1 ^R+r ;

* R+r ' Critical Damping:

L

or, RC i 2/TC

R = — ± 2/ L/C

c rC

For R = 0:

r

c - ^L/C

For r =

R = 2/L/C

c

Figure 4-2. Simple diode model for TEST program.

20
Straightforward Laplace transform analysis of this circuit (assuming zero initial conditions)

gives the transfer function,

El

( r 2 r L + RrC. ' v ; LCs 2 + ( J s + 1

where V^ is the voltage across R. For El a step function, it is well-known that the step response for

such a second-order system will depend on the roots or pole locations of the denominator polynomial.

These roots can, in general, be complex and are given by

,L + RrC, , / ,L + RrC, „ , r , , .„ hrrr) * V hrrr) - 4 Crt?) lc

s 15 s2

= . (2)

2 (7TJ—1 EC

Critical damping occurs when the square root term is zero (equal real roots). Underdamping occurs

when the quantity under the square root is negative (complex roots with both real and imaginary

parts), and an overdamped response occurs when this quantity is positive (both roots real and

unequal ).

Further algebraic manipulations for the critically damped case provide the critical value for r,

L

r c RC + 2/LC

or, for R,

R =^± 2 £ (4)

c rC u

For the extreme case where R + 0,

which is the well-known critical resistance of a paral lei -tuned rLC circuit. Similarly, for the

extreme case where r * °°,

R

c

- 2 J, (6)

which is the well-known critical resistance for a series-tuned RLC circuit. Letting R = 3r

c in eq (3), so that rc /(R + rc

) = 1/4 in eq (2),

r r - II I £ cl' c2 x/C 3x/C

Typical values of L and C for the Schottky diodes used in the RFPG are 2 nH and 1 pF, respectively.

Then

,

21
r ,

, r '2xl0

_9

1 /2xl0~ 9 Cl ' C2 V 10" 12 ' 3 V 10"12

= 10/20, WIO

= 44.72 n, 14.91 a.

Corresponding R values are 134.2 Q and 44.72 Q.

Figure 4-3 shows the SCEPTRE program, TEST1, for analyzing the step response of the diode-load

resistor circuit. As shown, El as a function of time is provided by table 1 which has five entries.

By applying a negative 1 V step, the program thus simulates the output branch circuit of the RFPG

(assuming negligible effects due to the 3.5 mm coaxial line). Because of the critical values chosen

for r (designated RS) and R (designated RL), the initial conditions for the capacitor voltage and

inductor current are the values given as 0.25 V and 0.01677 A, respectively.

Figure 4-4 is a plot of the waveforms generated by program TEST1. As expected, these responses

show critical damping of the R-r, L, C circuit described above. VRL, VRS, and VL are the voltage

waveforms across RL, RS, and L, respectively. For the typical values used, it can be seen that the

step response has died out in approximately 200 ps. Figure 4-5 shows that with RL = 25 ^ (the nominal

value), the response is overdamped, settling in about 300 ps. With RL again at 44.72 Q, but with a larger RS of 50 Q, figure 4-6 displays the resulting underdamped waveforms.

The nonlinear I-V characteristic of the diode, where its dynamic forward resistance varies

inversely with the diode current, was then added to create the TEST2 program. Figures 4-7 and 4-8

show the typical characteristic for the particular Schottky barrier diode used in the RFPG [14].

Figure 4-9 is a listing of the TEST2 program which indicates how SCEPTRE allows the simple entry for

the diode under ELEMENTS. The first argument inside the parenthesis is the value for I Q

, the reverse

"leakage" current, typically 100 nA. The second argument is the value for = e/kT which at room tem- perature (300 K) is the value 38.7. Note also the different initial conditions which must be satisfied in this case.

Figure 4-10 shows the resultant circuit waveforms with r replaced by the diode equation. Since

figure 4-5 shows an overdamped response for r = RS = 15 u, figure 4-10 is somewhat startling at first.

With a starting forward current of 0.0274 A (27.4 mA) , one would expect from figure 4-8 a more damped

response since r is typically less than 15 Q, for diode currents of about 2 to 3 mA or more. However,

figure 4-6 also supports the analysis that as r increases, the response grows underdamped. Thus we see that the time-dependent vanacion of r in the case of the actual diode is such as to cause an undershoot in the negative step response, as the diode current cuts off.

Further investigation into the nonlinear effects of the Schottky diode used in the RFPG were pur- sued, as will be described in the following sections. As a final example of modeling the diode-load

resistor output branch, however, figure 4-11 shows the listing for program TEST3 in which El, the

driving node voltage, is set up via table 1 to approximate the "double ramp" type of voltage waveform

actually observed in the RFPG. Figure 4-12 gives a plot of the resultant waveforms generated by program TEST3. The time base is five times longer than before for TEST2 and the values for C and L changed by a factor of four. Nevertheless, the undershoot in the response (VRL) of the simulated

waveform is seen to much more clearly approximate the actual observed output waveform (see fig. 2-7).

22
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E1T J-

^8-

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VRS 4

^s

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r

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0.1 0.2 0.3 0.1 O.S O.S 0.7 0.8 0.9 1 Ti.»e ( ns )

Fig ure 4-4. Step response from TEST1 program. Critical damping with RS = 14.91 Q and RL = 44.72 Q.

-§

\ VRL

VRS >

\ f— VL vV

O.I 0.2 0.3 0.4 O.S 0.6 0.7 0.8 0.9 1 TliM ( ns )

Fig Ure 4-5. Step response from TEST1 program. Overdamping with RS = 14.91 Q and RL = 25.0 a.

« \V

VRS

x

g

B

VRL -

^ R \\\ \

E9V

a >Ci

_> \)

>

\L-VL s

T \rV

s

1 ) .1 .2 .3 .4 .5 .6 .7 .8 .9 1 Tina ( ns )

Figure 4-6. Step response from TEST1 program. Underdamping With RS = 50.0 a and RL - 44.72 fi.

24
i

=

/////

\l\l\\\

L-L- ^- -50-

~^ oc

"""— *25°C Hrtiu"

"=- ->50"C ~"^

*IOO"C jl l\l /|^~*150'C

////// 1 1

'.Ofi.' 2R10 1N5712 50$r5835-

i i i ii LJU I i I inn

- FORWARD VOLTAGE IV) l f - FORWARD CURRENT ImAI

Figure 4-7. I-V curve showing typical tempera- ture variations for 5082-2835

Schottky diode.

Figure 4-8. Typical dynamic resistance (RD) versus forward current (Ip).

Thus it is that further modeling of the nonlinear RFPG output stage components was felt to be needed

in order to derive the approximate driving node voltage waveform.

4.3 Initial Modeling via Program RFPG

As described in sections 2.2 and 3.2, the output stage of the RFPG consists of positive and negative current sources that are steered by means of transistor switches (see figs. 2-5, 2-6, and 3-6).

An initial model that was used for simulating the output stage is shown in figure 4-13. Ideal diode

current JD1 and associated components CI, LI, and C4, together with R3, form the output branch of the

generator circuit. Similarly, JD2, C2, L2, and C5 represent the CR2 diode of figure 2-6 (CR2 and CR5

of fig. 3-6). CI and C2 are the voltage dependent junction capacitance, LI and L2 are the package

inductance, and C4 and C5 are the package capacitance of the diodes [14]. R2 and C3 are the filter

components for controlling part of the undershoot in the output waveform. Jl and J2 are the nominal

20 mA and 30 mA positive and negative constant current sources (33 mA value used in SCEPTRE program

for J2). To simulate the action of the switching transistors time-dependent resistors R1T and R2T are

uti lized.

Several versions of the program for. this model were developed in the process of experimenting

with component values, appropriate initial conditions, and the switching times/resistance levels of

the R1T and R2T resistors. Figure 4-14 shows the SCEPTRE program, RFPG10, which yielded fairly useful

results. In the topological listing under ELEMENTS, the voltage dependence of CI and C2 is provided

by table 2 which uses typical values provided by the manufacturer's data sheet [14]. Tables 1 and 3 provide the resistance versus time dependence of R1T and R2T, approximating the complementary

switching action of the BFR 90 rf switching transistors. These devices are rated for a current gainbandwidth product, fT

= 5 GHz (typical) at I c = 14 mA. Under INITIAL CONDITIONS are shown the two initial inductor currents and five initial capacitor voltages.

Figure 4-15 gives the resultant plots of the transient step-like output voltage across R3 and

driving node voltage across C5 for the RFPG10 program. The flatness of the waveforms at t = + indicates that the assumed values of the initial conditions is good. The wrinkle in the transition region

at about 0.45 ns is for the VC5 waveform which is identified by the black dots. There is a considerable (on the order of 20 percent) undershoot in the VR3 waveform which does not approximate reality

very well. However, as demonstrated in section 4.2, this difference is probably due to lack of the

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proper waveform for VC5. This poor approximation of the actual driving node voltage in turn is due to the 300 ps switching from 100 kfi (100 a) to 100 a (100 kn) for R1T (R2T). Nevertheless, the simulation does show that with such switching speed, a faster transition fall time than 600 ps could be

real ized.

4.4 ECL Drive and Transistor Switching Model via Program TRAN

Simple circuit modeling of the RFPG output stage, as described briefly in sections 4.2 and 4.3,

reveals that the 600 ps transition duration observed in the actual step-like output waveform is limited by the speed of the switching elements more than by the properties of the output currentsteering diodes. Consequently, work was undertaken to develop a model for the rf switching transistors used in the design of the RFPG and their associated complementary ECL input drive signals.

Figure 4-16 shows the schematic diagram of the SCEPTRE circuit used for this purpose. Node 14 corresponds to node 4 of the RFPG program with R9 at the collector of Q2 representing the load of the

RFPG output network. The rf switching transistors, Ql and Q2, are simulated by using a modified

Geller, Mantek, and Boyle (GMB) model for large-signal switching [15]. The J3 constant current source corresponds to J2 in the RFPG program. The remaining components provide the simulation of the ECL OR gate drive of the actual RFPG circuit.

Regarding the model used for the individual transistors, figure 4-17 shows a simple common- emitter equivalent circuit that was developed for the BFR 90 transistors. The primary difficulty

overcome with the use of this model is the effect of the nonlinear base-to-emitter characteristics of

the transistor when driven with low driving source impedances. The basic GMB model represents the

B'-E junction, from charge control theory, as the nonlinear forward resistance of the base-emitter

junction r Bi E (as employed in section 4.2 for the Schottky barrier diode analysis), in parallel with

two capacitors. One capacitor is the usual diffusion capacitance of the forward-biased base-emitter

junction. The other capacitor is a feedback capacitance due to the component of base current that

appears when the collector-to-base depletion layer varies as a function of collector base voltage.

The feedback effects of the collector-to-base space charge capacitance are then directly contained in

the solution of base current versus time when a finite load resistance (R3 in fig. 4-17) exists. An analysis to support this modified GMB model can be made by noting that for the forward biased baseemitter junction,

30
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e(v

R

, F - E3)

I R1F = I [exp - 1] (8)

so that

1 dI! K>r + I )• (9)

Ve dVB'E

B

' E °

where e = e/kT = 38.7 at T = 300 K, I Q is the base-emitter reverse saturation current, and E3 is an offset voltage described below. It is well known that when the junction transistor is switched by means of a large step of base-current, but does not saturate, the collector current is approximately

an exponential function of time [16]. The nonlinear GMB model shown in figure 4-17 simulates this

type of response by means of the time constant,

t

b

, = r B

, E CI (10)

which is considered to be invariant over the entire base current excursion. Consequently, CI is seen

to be a function of the nonlinear base-emitter current, since

Cl3 777" e V(I B'E

+

'o>- (11)

D L

Although the nonlinear network elements are constrained to maintain t ri invariant, the dynamic impedance seen looking into the base-emitter terminals is continuously variable during the resulting transient, as described in reference 15. Appendix C describes the measurement set-up and data taken for

determining an estimated value of t r

i for the BFR 90 transistor.

The forward-biased, base-emitter diode is thus modeled as before, except for an offset voltage

E3 = 0.617 V, which was determined by measurement of the BFR 90 base-emitter I-V characteristics, as shown in figure 4-18. For the ideal diode (see fig. 4-2),

VD =|ln [/ + 1]. (12)

o

Increasing the vertical scale (current sensitivity) in figure 4-18 shows that at I R

= 10 pA, V RE

= 730 mV. Using 8 = 38.7 as before and I Q

= 126 mA (average of reverse saturation current readings

taken with Keithley Model 150A nanoameter), then

1 .

r 10,000 ,, ,._ ., Vl877 1n ^26" + l] = "3mV.

By neglecting the voltage drop of I R through the bulk resistance r RR i at the 10 pA level (see

fig. 4-19), then

E3 = Enc[rcrT = V DC - Vn

= 730 - 113 = 617 mV. Urrot I tit U

The general expression for the static base-emitter I-V characteristic is given by

V BE

= VbB' + V D + E 0FFSET (13)

35
Figure 4-18. Typical BFR 90 base-emitter I-V characteristic.

Vertical : 100 pA/div.

Horizontal : 100 mV/div.

Collector circuit:

R

L = 150 n.

Vcc

= 4.97 V,

so that r RR i can be found from rearranging eq (13) and using eq (12) to give

1

I, V " Wt "

v

d V- Wri'" V

1

-

I. I. ;i4)

At I B

= 600 uA, V BE

s 850 mV. Hence, for the BFR 90 model,

0.850 - 0.617

Rl = r. 38.7

1 , r 600,000 ,, n l—r^— + 1] 126

= 23.6 fi. 600 x 10

The constant current source Jl in the GMB model is the leakage current of the back-biased collector-base junction, or the collector cutoff current Iq Rq given as 50 nA in the device specifications

[17]. J2 is a secondary dependent current source which is a nonlinear function of the base current

Id. Figure 4-20 shows the common-emitter collector characteristic for typical BFR 90 transistors.

For the 100 pA incremental steps of base current, a decreasing increment of collector current is observed. Thus, the 1(7 Ig ratio (ap£, or e) depends on current level and is best modeled by means of

a typical tabular relationship, as shown below. Finally, R2 in the model is the saturation resistance

of the collector characteristic, nominally of value 50 n. The saturation and storage time simulation

capabilities of the GMB model were not utilized in this development.

Figure 4-21 shows a listing of >the TRAN6E program used in conjunction with the SCEPTRE circuit

for the ECL drive and transistor switching simulation given in figure 4-16. The approximate ECL voltage drive waveforms for E1T and E2T, as reflected in tables 1 and 3, were determined by observing

nodes 3 and 10 with a sampling oscilloscope. Capacitors CI and C2 are dependent on their respective

base-emitter diode currents via eq (11) using = 38.7 and xgi = 5 ns. J2 and J5 are the secondary

current sources dependent on base currents JD1 and JD2, respectively. The values used in table 2 approximate the Iq/Iq relationship and were taken from corresponding Iq-Iq current values on a 5.2 V, 125 Q, load line drawn on the collector characteristics shown in figure 4-20.

36
, r BB' 'O-^VW 1 B'

'b V Ideal diode

-=- EOFFSET

Diode equation / curve shifted / by offset —s^ /

Actual

characteristic

(additional voltage drop due to te through r BB')

EOFFSET Vbe

Figure 4-19. Analysis of base-emitter characteristic.

Figure 4-20. Typical BFR 90 common-emitter collector characteristics. Vertical: 5 mA/div.

Horizontal: 1 V/div. Base current: 100 uA/step.

37
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38
Figures 4-22, 4-23, 4-24, and 4-25 show the results obtained via program TRAN6E for the ECL drive

and transistor switching simulation of figure 4-16. The ECL drive waveform in figure 4-22 approximates the ~2 ns logic swing from around -1.7 V to -0.957 V observed for E2T. It can be seen in figure

4-23 that by 2 ns (1 ns after E2T begins to change), the voltage across the base-emitter capacitor,

C2, of transistor Q2 has risen up to the 750 mV level. As previously determined from the base-emitter

characteristics (see fig. 4-18), appreciable base current now begins to build up in Q2. Figure 4-24

shows the JD2 waveform which peaks at ~0.67 mA a little after 3 ns. The corresponding rise in collector current J5 is seen in figure 4-25. Due to the saturation characteristic, J5 flattens out upon

reaching the 33 mA level at about 2.8 ns. Thus, as anticipated, the switching action of the BFR 90 transistors (and their associated complementary ECL input drive signals) is to produce a current steplike waveform which has a transition time on the order of 600 ps.

4.5 The Total Model via Program TRFPG

As shown in section 4.3, simple modeling of the output stage of the RFPG produces a simulated

output waveform with a much faster transition time and larger undershoot than observed on the actual

waveform. Lack of the proper driving node voltage waveform and a slower switching speed on the part

of the rf transistors/ECL input drive were likely causes. Section 4.4 above describes the development

of a model for the ECL drive and transistor switches (via program TRAN) which confirms the switching

speed supposition. To confirm the total model, then, R9 of figure 4-16 is replaced by the initial

output stage model of figure 4-13.

Figure 4-26 shows the merging of figures 4-13 and 4-16 used for programs RFPG and TRAN, respectively. Node 15 at the collector of Q2 is now the driving node for the output stage, corresponding to

node 4 of figure 4-13. The output diode and load resistor branch is designated by nodes 19 and 20.

Figures 4-27, 4-28, 4-29, and 4-30 show the results of SCEPTRE program TRFPG1, simulating the

total RFPG model using the same ECL drive signals as in figure 4-22. Figure 4-27 shows that the collector current J5 is maintained as before in figure 4-25. The voltage produced at node 15 (VC5) is shown in figure 4-28. The output diode current, JD4 is plotted in figure 4-29. The output voltage

waveform across R13 is given in figure 4-30, and can be seen to begin now to approximate reality. The

step-like output waveform is flat until the driving voltage at node 15 begins to fall at ~1.75 ns, which is where J5 begins to turn on. VC5 then decreases at a rate comensurate with the increase of

J5. Consequently, as analyzed in section 4.2, diode current JD4 decreases even more rapidly as the

output diode becomes reverse-biased into cutoff. As seen in the earlier analysis of the diode-load

resistor step response, however, the undershoot observed in the output waveform is highly dependent on the driving node voltage waveform, due to the parasitic reactances and nonlinear properties of the

diode.

Modifying the essential parts of the model for the RFPG shown in figure 4-26 so that the simulated waveforms better match the actual waveforms observed, therefore, is a matter of accounting for

various parasitic and distributed inductances and capacitances in the circuit which help to shape the

driving node voltage waveform. Small lead inductances (in the output circuit diodes and in the

connections to the driving node) and small capacitances, particularly associated with the driving

point node (node 15 in figure 4-26), have a very pronounced effect. Figure 4-31 shows a model, modified from figure 4-26, which gives a reasonably close approximation to the actual observed waveforms

of the RFPG. The additional inductances and capacitances (and their associated values) can be attributed to the actual physical devices and structure used in the construction of the RFPG. For example,

appendix D describes an analysis for approximating the value of C9 by knowing the typical value of the

39
no o

w °

I 7

Is

0) ' CD" o—' o

O Q

0.5 1 1.

2 2.5 3 3.5 4 TLme ( ns )

4.5

Figure 4-22. ECL drive waveform E2T from TRAN6E program.

0.5 1 1.5 2 2.5 3 Time ( ns )

3.5 4.5

Figure 4-23. Voltage across capacitor C2 in response to E2T (ECL

drive waveform of fig. 4-22) from TRAN6E program.

40
0.5 1 1.5 2 2.5 3 Time ( ns )

3.5 4.5

Figure 4-24. Transient current JD2 in response to ECL base drive from TRAN6E program.

fO

o_

X

enO o

(_ fM

CC in e —

c

(_ O

1 y 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TLme ( ns )

Figure 4-25. Collector current J5 of Q2 from TRAN6E program.

41
HIoeE

fO

t_enO3

CD

42
wo

/'

/

w to

J

1

X

t—

<C IO_ j= -

*>c

L.3O

1/1-

O- y 0.5 1 t.5 2 2.5 3 Time ( ns )

3.5 4.5

Figure 4-27. Collector current J5 of Q2 from TRFPG1 program.

Figure 4-28. Driving node voltage VC5 from TRFPG1 program.

43
fM

LD \

\

O

in cnTM \

o

L

ore

\

\

c

L

L3 iri \

O

in \

ro \

0.5 1 1.5 2 2.5 3 Time ( ns )

3.5 4.5

Figure 4-29. Output diode current JD4 from TRFPG1 program.

Figure 4-30. Resultant step-like output voltage waveform VR13 from TRFPG1 program.

44
%*

\

\ /

DC \ /

LLQ. OT~o

IH'

X

c

LL£0

FOO^YCO

o

©

He

Q-3 CO — LU

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in

oo

DC

CNJ o

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45
CD

in

«2 g

-\

tK "r

to

ID o

o n

CE> o 3 <N

D S \ > o> V

B

1 0.5 3.5 2.5 3 3.S Time I os )

4.5 5.5

Figure 4-32. Example of predicted available transition waveform from TRFPG3 program.

o

o

10 to o

uu

CC oLn- >

E

<D O-j o

1 O

s

c 5 ] 1 5 2 2. Tim

58

: 3

)

5 1 i .5 5 5.

Figure 4-33. Example of corresponding driving node voltage from TRFPG3 program.

46
IBB

.1 fe. ...

...

'•• I*

i ^M

'

i E

• Tr i 1 I

!

'

m I i

I

j

' "- i ,;.i L ;!

1 r-i -.

;'

... .

1

j -_. 4.1 i ! .

.-: f _.< J.-...L ,. , r«U

j

1

1 *A

Figure 4-34. Actual output waveform from the RFPG observed with a sampling oscilloscope. Vertical

100 mV/div. Horizontal: 1 ns/div.

Figure 4-35. Actual driving node voltage waveform from the RFPG observed with a sampling

oscilloscope. Vertical: 500 mV/div. Horizontal: 2 ns/div.

47
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48
collector-base capacitance of the BFR 90 transistor. The value of Cll, on the other hand, is an approximation of the effective capacitance to ground at the driving point node where the leads of 1)2, Rll, R12, and the two current steering diodes are all connected together in a relatively large solder

joint. The nanohenry values for L3-L7 are best estimates. Obviously, the better these parasitic and

distributed L-C values can be determined (by measurements or by calculations), the more exactly this

model can be made to approximate the actual waveforms of the RFPG.

Figure 4-32 shows an example of the predicted available transition waveform of the RFPG produced

by SCEPTRE program TRFPG3 in which the estimates of the above parasitic elements have been included.

Figure 4-33 is an example of the corresponding driving node voltage produced by the same program.

These simulated waveforms can be compared with the actual corresponding waveforms shown in figures

4-34 and 4-35, measured with a commercial sampling oscilloscope. The similarities between the simulated and observed waveforms are quite apparent, taking the different vertical and horizontal scales

into account. However, additional work remains to determine the exact error function between the

simulated and observed available transition waveforms, and thereby to improve the present model for

the RFPG. Figure 4-36 gives the listing of the SCEPTRE program TRFPG3.

5. Summary

This technical note contains the theory, circuit design, performance specifications, modeling,

and computer simulations which describe the NBS Reference Flat Pulse Generator (RFPG). Prior methods

used for generating flat baseline and topline pulse generators are discussed, together with their

limitations. The present approach used in the RFPG, i.e., steering constant current sources to the

load via a fast Schottky barrier diode, is thoroughly described. A complete circuit diagram and

description is given for the clock, delay, and pulse duration logic, the current-switching output

stages, and the regulated power supplies.

A considerable portion of the report is used to present the development of the circuit analysis

programs for the RFPG, written using extended-SCEPTRE hosted on a large computer system. The circuit

analysis of the nonlinear step response of a simple diode and series load resistor is used as the

basis for examining and evaluating the results obtained for the more complex switching structure of

the RFPG. These analyses show that the available transition waveform from the RFPG is also highly

dependent on the characteristics of the rf switching transistors used and the associated ECL logic

drive, as well as parasitic and distributed inductances and capacitances in the output stage of the

RFPG.

Finally, it is recommended that the efforts needed to determine a more exact error function be- tween the simulated and observed waveforms be pursued. This work can provide the basis for an improved model of the NBS RFPG by which to predict its performance when used as a pulse waveform gene- rator standard in either the laboratory or as a dynamic transport standard for field testing purposes.

The authors would like to acknowledge the helpful comments and guidance provided by other members

of the NBS technical staff in the development and modeling of the Reference Flat Pulse Generator, including N. S. Nahman, R. A. Lawton, and R. L. Peterson. The efforts of the NBS clerical staff in preparing this report are also gratefully acknowledged, including M. E. DeWeese and P. J. Rice.

49
6. References

[1] McCaa, W. D. ; Nahman, N. S. Generation of reference waveforms by uniform lossy transmission

lines. IEEE Trans. Instrum. Meas. IM-21(4): 382-390; 1972 November.

[2] Gans, W. L. ; Nahman, N. S. Shielded and balanced coaxial transmission lines--parametric meas- urements and instrumentation relevant to signal waveform transmission in digital service. Nat.

Bur. Stand. (U.S.) Tech. Note 1042; 1981 June.

[3] Holt, D. R. ; Nahman, N. S. Coaxial-line pulse-response error due to a planar skin-effect

approximation. IEEE Trans. Instr. Meas. IM-21 (4) : 515-519; 1972 November.

[4] Andrews, J. R. ; Bell, B. A.; Nahman, N. S. ; Baldwin, E. E. Reference waveform flat pulse generator. IEEE Trans. Instrum. Meas. IM-32(1): 27-32; 1983 March.

[5] a. IEEE standard pulse terms and definitions, IEEE Std. 194-1977:12; 1977 July 26.

b. IEEE standard, IEEE std. 181-

c. International Electrotechnical Commission publication 469-1 and 2, 1974. Part 1: Pulse

terms and definitions. Part 2: Pulse measurement and analysis, general consideration.

[6] Schoenwetter, H. K. High-accuracy settling time measurements. IEEE Trans. Instrum. Meas. IM-32(1): 22-26; 1983 March.

[7] Bowers, James C. ; Sedore, Stephen R. SCEPTRE: A computer program for circuit and systems

analysis. Englewood Cliffs, NJ: Prentice-Hall, Inc.; 1971. [8] Frye, G. J. A predictable subnanosecond pulse generator. IEEE Trans. Inst. Meas. IM-17 (4) :324-

329; 1968 December.

[9] Elliott, B. J. Picosecond pulse measurement of the conduction current vs. voltage characteristics of semiconductor materials with bulk negative differential conductivity. IEEE Trans. Inst. Meas. IM-17(4):330-332; 1968 December.

[10] Andrews, J. R. Picosecond pulse generators using microminiature mercury switches. Nat. Bur. Stand. (U.S.) NBSIR 74-377; 1974 March.

[11] Millman, J.; Taub, H. Pulse, digital & switching waveforms. New York, NY: McGraw-Hill; 1965. 101-104.

[12] Andrews, J. R. Stable reference flat top pulse generator. Nat. Bur. Stand. (U.S.) Memorandum

to N. S. Nahman and W. D. McCaa; 1970 January 16. [13] Becker, D. Extended SCEPTRE, Vol. 1. , user's manual. GTE Sylvania; 1974 December.

[14] Diode and transistor designer's catalogue. Hewlett-Packard Components, 79-83; 1980. [15] Geller, S. B. ; Mantek, P. A.; Boyle, D. R. A general junction-transistor equivalent circuit for use in large-signal switching analysis. IRE Transactions on Electronic Computers, 670-679; 1961

December.

[16] Ebers, J. J.; Moll, J. L. Large-signal behavior of junction transistors. Proc. IRE 42:1761-1772; 1954 December.

[17] RF data manual, second edition. Motorola Inc., 17-80/82; 1981.

50
Appendix A. Flat Pulse Generator Parts List

Integrated Circuits

IC1 1 i.C.L. NOR gate 95H03

IC2 divider 95H90

IC3 i 95H90

IC4 1 ii 95H90

IC5 1 n 95H90

IC6 1 NOR gate 95H03

IC7 Flip-flop 95H28

IC8 1 ii 95H28

IC9 1 ii 95H28

IC10 Divider 95H90

IC11 i M 95H90

IC12 i ii 95H90

IC13 NOR gate 95H03

IC14 i ii 95H03

IC15 1 Reference voltage source LM-399H

IC16 1 Yecision op-amp 0P-05C

IC17 I ii 0P-05C

1C18 \ /oltage regulator +15 V 7815

1C19 +12 V 7812

1C20 -5 V 7905

1C21 -5 V 7905

1C22 -5 V 7905

Transistors

Ql BFR90

Q2 BFR90

Q3 2N3904

Q4 BFR90

Q5 BFR90

Q6 2N3904

Q7 2N4250

Q8 2N3906

Q9 2N4250

Q10 2N3906

Diodes

CR1

CR2

CR3

CR4

CR5

CR6 CR7

Light emitting

Schottky diode

M ii

Light emitting

Schottky diode

ii ii

Rectifier, General -Purpose

HP-5082-4484

HP-2835

HP-2835

HP-5082-4484

HP-2835

HP-2835

IN4004

51
Diodes, cont. CR8 Rectifier, Gen CR9 ii ii

CR10 n ii

CR11 I n

CR12 n n

CR13 Zener diode

CR14 Zener " CR15 Light emitting

IN4004

IN5240

IN5240

HP-5082-4484

Resistors--±5% tolerance unless noted otherwise

Rl Composition 51 Q 1/4 W R2 n 51 n 1/4 W R3 ii 51 a 1/4 W R4 M 680 Q 1/4 W R5 ii 33 Q 1/4 W R6 ii 47 a 1/4 W R7 OSM termination 50 Q

R8 Selected, used on 1 y if needed

R9 Composition 680 a 1/4 W RIO ii 33 Q 1/4 W Rll ii 47 Q 1/4 W R12 OSM termination 50 a R13 Selected, used only if needed

R14 Composition 1 Kfi R15 Glass film 4.75 K 1% R16 Trimmer, multi- turn 1 Kft R17 ii 1 Kfi R18 Carbon film 1.82 Kft 1% R19 Composition 1.3 Kfi 1/4 W R20 Precision, wire wound 100 ft 0.1%

R21 Composition 1.3 Kft 1/4 W R22 Precision, wire wound 100 n 0.1%

R23 Not assigned

R24 n n

R25 Wire wound 1KH2U

R26 Composition 180 n 1/4 w R27 ii loo a 1/4 w R28 H 75 Q 1/8 W R29 n 150 Q 1/4 W R30 ii 150 Q 1/4 W R31 ii 220 Q 1/4 W R32 I 150 a 1/4 W R33 n 150 a 1/4 W R34 ii 75 a 1/8 W R35 n 220 Q 1/4 W R36 n 100 a 1/4 w

52
Capacitors

CI Disk ceramic

C2 Si 1 ver mi ca C3 Si 1 ver mi ca

C4 Si 1 ver mica

C5 Trimmer

C6 Silver mica

C7 Trimmer

C8 I

C9 Silver mica

CIO Trimmer

Cll Disk ceramic

C12 Unassigned

C13 Silver mica

C14 Disk ceramic

C15 Unassi gned

C16 Silver mica

C17 Ceramic

C18 11

C19 Electrolytic

C20 11

C21 Disk ceramic

C22 Electrolytic

C23 Disk ceramic

C24 Electrolytic

C25 Tantal urn C26 Electrolytic

C27 Disk ceramic

C28 Electrolytic

C29 Tantal urn C30 Electrolytic

C31 Disk ceramic

C32 Electrolytic

C33 Tantalum

C34 Electrolytic

C35 Disk ceramic

C36 n n

C37 ii ii

C38 Si 1 ver mica

C39 Disk ceramic

C40 Silver mica

C41-59 Disk ceramic

0.001 yF

270 pF

270 pF

33 pF

1.8-13 pF

50 pF

15-60 pF

15-60 pF

50 pF

15-60 pF

0.001 pF

3 pF

0.001 yF

3 pF

1 uF, 25 V

1 uF, 25 V 100 yF, 25 V 100 yF, 25 V 0.01 yF, 100 V 100 yF, 25 V 0.01 yF, 100 V

(2) 1000 yF, 25 V

1 yF, 35 V 100 yF, 25 V 0.05 yF

(2) 1000 yF, 25 V

1 yF, 35 V 100 yF, 25 V 0.05 yF

(2) 1000 yF, 25 V

1 yF, 35 V 100 yF, 25 V 0.05 yF

0.001 yF

0.01 yF, 25 V

5 pF

0.01 yF, 25 V

5 pF

0.01 yF, 100 V

(Not shown on schematic, these are bypass capacitors near each I.C. socket.)

53
Inductors

Connectors

Switches

Knobs

LI rf choke, miniature 51 yHy

L2-4 Ferrite beads

Output, Type N, OSN 410-101 or equal, 2 ea. Terminator, Type OSM, OSM-210-1 or equal, 2 ea. (Shoulder turned down to reduce size)

51 Rep. rate, 2 pole, 4 position miniature,

Alco switch MRB-2-5 or equal

52 Delay, 2 pole, 4 position miniature,

Alco switch MRB-2-5 or equal

53 Mode, 1 pole, 3 position center off toggle

Alco MTA 10SE or equal

Miniature, 1/8" for SI and S2, 2 ea.

Miscellaneous

Yl Crystal, 10 MHz, FM-2 case Socket, crystal, type FM-2

"

, I.C., low profile 16 pin D.I. P., 14 ea.

"

, I.C., 8 pin, Augat 8059-2G5 or equal, 2 ea.

"

, I.C., 4 pin, Augat 8059-4G4 or equal, 1 ea. Heat sink pads, 4 ea. Blank plug-in, Tektronix 040-0652-05

Coax line, semi-rigid, 3.5 mm, TFE, approx. 2 ft length

Printed circuit board, 1/16" thick G-10, double-sided foil pattern per

figure A-l.

54
Jumper on component side

Jumper on lower side

Figure A-l. Printed circuit board for RFPG.

(4.4" to 4.45" by 9.8" to 9.85" in size.

55
Appendix B. Alignment/Calibration Procedures

There are a minimal number of adjustments needed for maintaining the proper operation of this

generator. These involve the output resistance, dc output voltage levels, trigger repetition rate,

and delay (Trigger-to-Pulse) time.

A. Output Impedance Adjustments (Trigger and Pulse outputs)

1. Set the mode switch to V.

2. 'Connect an accurate ohmeter to the type-N output connector. Be sure that the ohmmeter

test voltage on the center conductor is positive.

3. Measure the dc resistance. If it is not 50.00 a. ± 0. 5 percent (may use a tighter specification if desired), then continue to step 4.

4. Select an SMA, microwave, 50 n termination, R7 (R12), whose dc resistance is very close

to, but slightly greater than, 50.00 u.

5. Compute the required shunt resistor, R8 (R13), using R8 = 50 x R7/(R7 + 50).

6. Select the nearest standard value 1/4W, carbon composition resistor for R8 (R13) and

install it with very short leads to the connection point of CR3 (CR6) and the 3. 5 mm coax. Use adequate heat sinking on the resistor during soldering.

7. Repeat steps 1 through 3.

B. Output Voltage Adjustment

1. Connect an accurate DVM to the type N output connector.

2. Set the DVM to the 1 V range.

3. Set the mode switch to V.

4. Check that the output voltage is 0.0 V ± 10 uV. If OK, go to step 6.

5. If the output is greater than +10 uV, then CR3 (CR6) has excessive leakage current and must be replaced.

6. Set the mode switch to DC.

7. Adjust R17 (R16) for a reading of 1.000 V + 1 mV on the DVM (a tighter specification may

be used if desired).

C. Repetition Rate Adjustment

1. Connect an accurate frequency counter to the Trigger output.

2. Set the repetition rate switch to 1000 kHz.

3. Set the mode switch to Pulse.

4. Adjust C5 to set the repetition rate to precisely 1.00 MHz ± 0.01 percent (+100 Hz).

D. Delay Adjustment

1. Use a dual channel, random sampling oscilloscope for these adjustments.

2. Remove the internal reverse termination, R7, on the Trigger channel. Connect an SMA,

10 dB pad and coaxial cable to this point. Connect the other end of the cable to the

scope trigger input.

3. Connect the ChA sampler to the SMA CLK (clock) output on PC board.

4. Connect the ChB sampler to the Pulse output.

5. Connect a 50 ft termination to the Trigger output.

6. Set the generator controls as follows:

Mode: Pulse, Repetition Rate: 1 MHz, and Delay: 200 ns.

56
CLK output

(see figure 3-1

PULSE or TRIGGER output

Figure B-l. Time delay adjustment waveforms. Vertical: 100 mV/div.

Horizontal: 2 ns/div. (or faster).

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22. 23.

Set the sampling scope controls as follows:

Mode: Random sampling, Dual Trace, 2 ns/cm, Trigger: as needed for stable display.

Adjust the time position control for a display similar to that shown in figure B-l. Adjust the individual vertical channel delay controls to minimize the time TD between

transitions.

Measure and record TD = _ _ ns. Connect the ChB sampler to Trigger output and the 50 Q, termination to Pulse output.

Adjust the scope time position control for the figure B-l display again.

Adjust C7 to set TD to precisely the value measured in step 9. Set the delay to ns. Connect the ChB sampler to Pulse output and the 50 n termination to the Trigger output.

Adjust the time position control for the figure B-l again.

Adjust C10 to set TD to precisely the value measured in step 9. Set the delay to 100 ns. Adjust the time position control for the figure B-l display again.

Adjust C8 to set TD to precisely the value measured in step 9. Set the delay to 300 ns. Adjust the time position control for the figure B-l display again.

Measure and record TD . TD, should equal TD , from step 9, +1/2 ns. Remove the 10 dB pad and replace the internal 50 Q, termination for the Trigger output.

57
Appendix C. Measurements of the Effective Time Constant (t„i)

for the BFR 90 Transistor

Besides the parameters that can be obtained from the base-emitter and collector-emitter characteristics, modeling of the BFR 90 transistor using the nonlinear GMB model [15] requires knowledge of

the effective collector current exponential response to a step of base current (common-emitter con- figuration). As described in reference 15, a charge-controlled model of the base-emitter junction

(and the associated differential equations) can be used to develop the following common-emitter equivalent circuit for simulation purposes:

'CBO

Rin B rBB

where:

Figure C-l. Common-emitter equivalent circuit (GMB model).

bulk or extrinsic base-emitter resistance

current-dependent base-emitter diode resistance, rg.£ sum of the base-emitter diffusion capacitance (

B

• E

) and a feedback capacitance (Cf)

representative of the collector-base depletion capacitance

*CB0

= l eaka 9e (cutoff) current of the collector-base junction

a

FE

= ic^BE' ^ ne common-emitter base to collector current gain, or beta (3)

r

s = collector saturation resistance

Although this equivalent circuit is useful for large signal switching analysis, operation in the

saturation region where storage time effects must be accounted for is not inherent to the use of the

BFR 90 switches used in the RFPG. Therefore, the saturation sensing diode and storage time circuit of the complete GMB model is not included in figure C-l.

The R'C time constant is denoted as Tgi where igi = (Cgi£ + Cf) rgi£. This time constant is con- sidered to be constant over the entire base current excursion even though the dynamic impedance

between the B'-E terminals is continuously variable during the transient step. As pointed out in reference 15, this variation is important when source impedances (R-j n

) are of low value since then the

input impedance affects the level of current from the driving source. For the RFPG, the driving

source to the BFR 90 transistors is the low impedance (~7 Q) output from an ECL logic OR gate. A measure of ig. then allows for a calculation of C since R' is determined from the base-emitter characteri sties.

58
+ V2

50Q

airline 90°SMA

®Tunnel

diode step

generator

(t

r<100ps)

1/8" microstrip

50Q

+ V1

1/8" microstrip

1—«e

4.7WQ

BFR90

SMA

50Q

Sampling

Oscilloscope

Figure C-2. BFR 90 time constant measurement circuit.

With a large value of R.j (so that L- = V^

n

/R-j n = constant) and ignoring the second-order effect

of IrBO' tne "instantaneous collector current can be expressed as

i c (t) s a

FE

I in

[l - exp(-t/T

B ,)]. :c-r

Time constant tdi is equal in value to the ~63 percent point of the collector current response to a base current step, measured with ]r ranging from cutoff to just saturation (with the desired value of

load resistor R

L in the collector circuit).

A test board using microstrip lines and miniature connectors for a broadband 50 ft environment

(developed for time domain reflectometry testing purposes) was used to make the tgi measurements. The

circuit board and test setups are shown in figure C-2.

The bias supplies VI and V2 were provided by a bank of NiCad batteries. R2 is the effective load

resistor (R|J as indicated in figure C-l. Using 50 Q, microstrip lines with 1/8 inch wide copper foil

on glass-epoxy printed circuit board, the step generator and sampling oscilloscope were connected via

miniature high-frequency connectors. Observation of the tunnel diode step generator with the sampling

scope output of the standard 50 Q air dielectric line indicated a step transition duration (t„) of

less than 100 ps.

Photographs taken of the step response of a typical BFR 90 transistor in the test circuit given

in figure C-2 are shown on figures C-3 and C-4.

The results of the step response tests run on three BFR 90 transistors are tabulated in the table

C. 1. The data from this table are plotted in figure C-5 showing that for large signal collector current swings up to approximately 30 ma (corresponding to load resistance of about 200 a), the effective

tdi is around 3 ns.

59
Start

Finish

(a)

Start

63% down

(3.78 div.

Finish

(b)

t

t

! * Start

63% point (1.2 div.)

Figure C-3. Step response (x b

i measurement) photos of a typical BFR 90 transistor (150 Q, load

resistance).

(a) Vertical: 5 mV/div. Horizontal: 10 ns/div. Test conditions: VI = V2 = 6.3 V, Rl = 6.2 kft, R2 = 150 n. V CE swing: 6 div p-p; +1.5 V (saturation), +4.9 V (cutoff).

(b) Vertical: 5 mV/div. Horizontal: 2 ns/div.. Test conditions: same as above. 63% x

6 div. = 3.78 div. x b. = 1.2 div. x 2 ns/div. = 2.4 ns.

60
Start

63% down

Finish

ft

63% point: t

b

' = 6/11 div. x 10 ns/div.

= 5.5 ns Start

Start

63% down

Finish

t

63% point : ti Start

= 1, = 625 div.

3 ns

x 5 ns/div.

Figure C-4. Step response

resistance).

(a) Vertical:

6.3 V, Rl = 6. (b) Vertical:

R2 = 620 SI. \

[x b

. measurement) of a typical BFR 90 transistor (300 n and 620 n load

6 div. p-p

2 kn, R2 =

6 di v. p-p

CE swing:

Horizontal: 10 ns/div. Test conditions: VI = 5.02 V, V2 = 300 n. V rF swing: +0.6 V (saturation), +5.8 V (cutoff).

Horizontal: 5 ns/div. Test conditions: same as above except

+0.6 V (saturation), +5.6 V (cutoff).

61
Table C. 1. Summary

Transistor number R 2 = 150 a

(ns)

R2 = 300

(ns)

R2 = 620 a

(ns)

5 2.4

6 2.0

3 l.E Ave.

5.45

5.2

5.0

2.07

6.25

8.4

7.9

5.22 7.52

) i

co 9.0

c

o 8.0

o

CD§ 7.0 —

c

nsc 6.0

c

.m 5.0

HT

c 4.0

03

-*—

£ 3.0 —

o

o

© 2.0 — ^Xs E

H 1.0 "'

I I

© Transistor #5

D Transistor #6

V Transistor #3

100 200 300 400 500

R2 (load resistor) in ohms

600

Figure C-5. Plot of tdi data on BFR 90 transistors.

62
Appendix D. Collector Capacitance Equivalency

Given the circuits shown in figures D-l and D-2 on the following page, it is desired to determine

the step response voltage at the collector node due to either the known collector-base capacitance or

an equivalent capacitance between collector and circuit common. Letting X(s) = £[x(t)] denote the

Laplace transform representation of the instantaneous value of the circuit variables for figure D-l,

then

I b (s) = I b

, e

(s) + I f (s), (D-l)

where, assuming zero initial conditions,

I f (s) = sC

f

V b

, c (s). (D-2)

The collector-base voltage V

b c (s ) is determined by

where V (s) = Ip (s )Rj, is the collector output node voltage. Since

I (s) = eI h

, Q (s) - I f (s) (D-4)

then

V

o

[s) = [Bl

b

, e (s) - I f (s)]R

£ (D-5;

or, by substituting for If(s), using eq (D-l),

V Q

(s) = Cl

b

. e (s)(l + S) - I b (s)]R r

(D-6)

By solving for V b

i (s) in eq (D-2), and using eq (D-3),

I b

, e (s)R

2 + V Q (s) = I f (s)/sC

f (D-7;

or,

R

2

C

f sI b'e

(s) + C f sV

o (s) = Ms) = Vs)

" Ve (s) - (D_8]

Solving for I b

i (s) gives

I (s) - CsV(s)

I ( S ) = — 1—2 . (D-9)

b'e V ; 1 + R

2

Cfs

v ;

Substituting for I b e

( s ) in eq (D-6),

I (s) - CsV(s)

V (S)= ^ l + R

2

C

f

s Kl + » - I„(s)]R

A

. (D-10)

63
ib(t) = lu(t)

Figure D-l. Simplified transistor model using collector-base capacitance for step response.

ib(t) = lu(t)

Figure D-2. Simplified transistor model using equivalent common-collector

capacitance for step response.

64
With appropriate rearrangement,

V (s

;b - R

2 c

fs)R£

i b (s)

o

v ; 1 + [R. + (1 + B)R ]C s' £ f

For i(j(t) = Iu(t), an input step of base current of I amperes, so that Ik(s) = I/s,

V (s) =

R,C £ s)R I 2 f

' £

o" ' s{l + [R 2 + (1 + e)R

£ ]C

f

s}

iD-ir

(D-12!

or,

V (s) =

BR I Z R,C R I 2

f £

o

K

' s{l + [R

2 + (1 + B)R ]C s 1 + [R 2 + (1 + B)R ]C s'

By using partial fraction expansion,

(D-13]

V s = —s

s +

1 [R 2 + (1 + B)R

£ ]Cf

R 9 R

( Li ji { R

2 + (1 + B)R

£

J

s +

1 [R, + (1 + B)R JC

£ f

:d-i4]

or,

V (s) = BR I[

i , V

T7—

]

V ' TT~> £

L S S + 1/t^ S + 1/t^

(D-15)

where: T j = [R

2 + (1 + B)RJl ]Cf

R R

R =

P

R

2 + (1 + 3)R

(

The step response voltage at the collector node is thus

V Q

(t) = BR £

I[1 - exp(-t/x 1 )] - R

p

I exp(-t/x1 (D-16)

For figure D-2,

il b

. e

(s) =3l

b (s). ;d-i7)

The load impedance at the collector node isVs) =

1 + R Cs

£

so that the collector output node voltage is

(D-18)

V (s) = 3l

b (s)Z

£

(s; [D-19]

65
or,

eVb(s)

£

which corresponds to eq (D-ll) for figure D-l. Again, for l^{s) = I/s, corresponding to an input step

of base current of I amperes,

BR I V (s) =

„ ri A r

, . (D-21)

By partial fraction expansion,

or ;

o

v

' s[l + R C s]'

i o

BR I BR I Vs

» -T- - —T- (D- 22)

s *inr

a o

where x_ = R^Cg. The step response voltage is then

V Q

(t) = BR^IEl - exp(-t/x 2 )]. (D-24)

For equivalent response times,

Tj = [R

2 + (1 + 5)R

£ ]Cf

- t

2 = R

£

C q

. (D-25)

For typical values, (1 + B)R^ » R

2

« Hence,

(1 + B)R

£ C

f

= R

x Co

, (D-26)

or,

c = (i + e)c

t

In the case for a BFR 90 transistor, from reference 17, typically

(D-27)

C

f

= Ccb = 0.5 pF

P = h FE = 25min t0 25W ( D " 28 >

From actual observed collector characteristics (see fig. 4-20), typical B values are 40 to 80. Using

B

= 60 and C

f

= 0.5 pF in eq (D-27),

CQ

(typical) a (61) 0.5 pF = 30.5 pF. (D-29)

A value of CQ

= C = 10 pF was found to produce good results in the TRFPG program model shown in figure 4-31.

66
NBS-1J4A (REV. 2-8C) U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET (See instructions)

1. PUBLICATION OR

REPORT NO. NBS TN-1067

2. Performing Organ. Report No 3. Publication Date

October 1983

4. TITLE AND SUBTITLE

Reference Flat Pulse Generator

5. AUTHOR(S)

J. R. Andrews, B. A. Bell, E. E. Baldwin

6. PERFORMING ORGANIZATION (If joint or other than NBS, see instructions)

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

7. Contract/Grant No.

8. Type of Report & Period Covered

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street. City. State, ZIP)

10. SUPPLEMENTARY NOTES

]] Document describes a computer program; SF-185, FIPS Software Summary, is attached.

11. ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant

bibliography or literature survey, mention it here)

A reference step-like pulse

at NBS. This generator can be used

of various kinds of transient recor transient digitizers, etc^.). Basic

circuit diagrams and descriptions,

is presented together with the circ

simulation proqram usinq extended-S

the NBS Reference Flat Pulse Genera

duration (90 to 10 percent) of 600

generator is described which has been developed

for accurately characterizing the step response

ding equipment (oscilloscopes, waveform recorders,

design principles are given as well as complete

An analysis of the output stage of the generator

uit models for developinq a time-domain computer

CEPTRE. Preliminary specifications indicate that

tor provides a negative-going reference transition

ps , ±2 percent after 5 ns.

12. KEY WORDS (Six to twelve entries; alphabetical order; capitalize only proper names; and separate key words by semicolons)

available waveform; baseline; circuit analysis; flat pulse generator;

modeling; step response; topline; transfer standard; transition duration

13. AVAILABILITY

[_vj Unlimited

| | For Official Distribution. Do Not Release to NTIS

[X^\ Order From Superintendent of Documents, U.S. Government Printing Office, Washington, D.C.

20402.

Q3] Order From National Technical Information Service (NTIS), Springfield, VA. 22161

14. NO. OF

PRINTED PAGES

72

15. Price

$4.50

.-'. U.S. GOVERNMENT PRINTING OFFICE: 1983—776-686/28 REGION NO. 8

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