# Patent

## Title
Semiconductor device and fabrication method thereof

## Abstract

A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

## Background
BACKGROUND
1. Field of the Invention
The present invention relates to semiconductors, and in particular to a semiconductor device with a copper contact or interconnect having TaN barrier at minimal thickness and fabrications thereof.
2. Description of the Related Art
Electrically conductive lines providing, for example, signal transfer are essential in electronic devices as well as semiconductor integrated circuit (IC) devices. Electrically conductive lines on different levels are connected by electrically conductive plugs in required position, providing a predetermined function.
Recently, fabrication using copper has been introduced to solve problems such as RC delay caused by feature size reduction responding to demands for increased integrity. Moreover, copper shows better heat conductivity, providing better electromigration (EM) resistance than conventional aluminum. Copper fabrication compatible with low-k dielectric material has become a popular interconnect process.
Nevertherless, one disadvantage of the copper fabrication is diffusion of copper to adjacent dielectric material, affecting reliability of the IC device. A metal barrier layer comprising material such as tantalum (Ta) or tantalum nitride (TaN) is thus provided for diffusion suppression. However, the tantalum (Ta) or tantalum nitride (TaN) barrier is normally formed by PVD such as sputtering at a thickness exceeding 100 Å.
Due to the critical dimension (CD) reduction of semiconductor devices, copper contacts, such as copper contact plugs are required in the front-end fabrication to electrically contact the active regions formed on a semiconductor substrate or a gate electrode of a transistor. Hence, thinner and more reliable diffusion barriers are needed to prevent undesired copper diffusion.
SUMMARY
Accordingly, embodiments of the invention provide a semiconductor device, comprising a substrate with at least one transistor formed thereon. A first dielectric layer covers the transistor and has an opening in the first dielectric layer to exposes an active region of the transistor. An atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.
A method for forming a semiconductor device is also provided, in which a substrate with at least one transistor covered by a first dielectric layer is provided. An opening is formed in the first dielectric layer to expose an active region of the transistor. A TaN barrier layer is conformably formed at a thickness less than 20 Å in the opening by atomic layer deposition (ALD) and a copper layer is formed over the TaN barrier layer to fill the opening.
A detailed description is given in the following with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIGS. 1, 3–6 are cross sections of a method for forming a semiconductor device with a copper interconnect and a copper contact according to an embodiment of the invention; and
FIG. 2 shows an exemplary method of injecting source and purge gases in atomic layer deposition 165 of FIG. 1.



DESCRIPTION
In this specification, expressions such as “overlying the substrate”, “above the layer”, or “on the film” simply denote a relative positional relationship with respect to the surface of the base layer, regardless of the existence of intermediate layers. Accordingly, these expressions may indicate not only the direct contact of layers, but also, a non-contact state of one or more laminated layers. By use of the term “low dielectric constant” or “low-k” herein, is meant a dielectric constant (k value) which is less than the dielectric constant of a conventional silicon oxide. Preferably, the dielectric constant of the low-k is less than about 3.9.
Fabrication of a semiconductor device with copper contacts according to embodiments of the invention is shown in following cross sections of FIGS. 1–6. In FIG. 1, a substrate 100, such as a silicon substrate, is first provided with a transistor formed thereon. The transistor comprises a gate insulating layer 110 and a gate electrode 130 sequentially formed over a portion of the substrate 100, functioning as a gate stack, and the gate electrode 130 is insulated from the substrate 100 by the gate insulating layer 110. The transistor further comprises a pair of source/drain regions 120 oppositely disposed in the substrate 100 adjacent to the gate electrode 130. Preferably, the gate electrode 130 is polysilicon and can be doped with impurities of suitable conductive type, and the source/drain regions 120 are N type or P type doped. Further, the transistor comprises insulating spacers 140 formed on opposite sidewalls of the gate stack, respectively.
A first dielectric layer 150, preferably a phosphorous-containing dielectric layer of phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), is formed over the substrate 100 and the transistor with an opening 160 formed therein. The opening 160 can be formed at a position related to one of the active regions such as the source/drain region 120 or the gate electrode 130 of the transistor. Herein, as shown in FIG. 1, the opening 160 formed in a position corresponding to one of the source/drain regions 120, exposing the top surface thereof is given as an example but is not restricted thereto.
Next, a tantalum nitride (TaN) barrier layer 170 at a thickness less than 20 Å is comfortably formed over the first dielectric layer 150 and in the opening 160. Thickness of the tantalum nitride (TaN) barrier layer 170 is preferably between 0 ̃50 Å and is formed by an atomic layer deposition (ALD) 165. The atomic layer deposition 165 can be performed by an atomic layer deposition cluster tool having multiple chambers (not shown). The TaN barrier layer 170 shows good step coverage in the opening 160 and enhanced electromigration resistance in a later formed conductive contact. Next, a thin copper seed layer 180 at a thickness of about 500 ̃1800 Å is then formed over the TaN barrier layer 170. The atomic layer deposition 165 will be further discussed later.
FIG. 2 shows an exemplary method for injecting gaseous reactants, purge gases and carrier gas during the atomic layer deposition 165. The atomic layer deposition 165 is performed by an atomic layer deposition (ALD) cluster tool having multiple process chambers at process pressure of about 0 ̃5 torr and at process temperature less than 300° C. When forming the TaN barrier layer 170, reactants used in the atomic layer deposition 165 include penta-dimethyl-amino-tantalum (PDMAT) and ammonia (NH3) with flow rates of about 0 ̃100 sccm and 0 ̃100 sccm per injunction, respectively. Further, carrier gas such as hydrogen (H2) or nitrogen (N2) at a flow rate between 0 ̃100 sccm is also used to carry the described reactants of the ALD deposition 165 into the process chamber. Moreover, gases such helium, nitrogen and argon with a total flow rate between 0 ̃100 sccm are used to purge reactants remaining in the process chamber. As shown in FIG. 2, a cycle of PDMAR-NH3 in cooperation with purge operations is performed by injecting a purge gas in pulses between the injection pulses. Thus a TaN layer 170 under a formation rate of about 1 ̃3 Å/per cycle. The pulse-on time for the source gas is about 0.01 ̃0.001 seconds. The TaN barrier layer 170 can thus be formed by at least described cycles.
Next, in FIG. 3, a thicker copper layer 190 is formed over the copper seed layer 170 and fills the opening by deposition 195. The deposition 195 can be performed by an electrochemical plating (ECP) or an electroless plating. Due to the formation of the TaN barrier layer 170, diffusion of the copper layer may be prevented and contact resistance reduced thereby.
In FIG. 4, a planarization step such as chemical mechanical polishing (CMP) performs to remove the portion of the copper layer 190, copper seed layer 180 and TaN barrier layer 170 above the first dielectric layer 150, leaving a contact plug 200 as an interconnect between the underlying transistor and a substantially formed conductive line (not shown). Herein, the contact plug 200 comprises a conformal TaN barrier layer 170a, a copper layer 190a and a copper seed layer 180a therebetween, contacting the source/drain region 120 of the transistor. In the described planarization step, for example CMP, the TaN barrier layer 170 is thin and can be simultaneously removed during the copper CMP, obviating the need for additional CMP on the TaN barrier layer 170.
In FIG. 5, a second dielectric layer 210 with a conductive line 220, such as a copper line, formed therewith, is formed over the first dielectric layer 150 by conventional line fabrication. Herein, a conformal metal barrier layer 215 is preferably provided between the conductive line 220 and the second dielectric layer 210. The metal barrier layer 215 can also be a TaN layer formed by the described atomic layer deposition 165. Thickness of the metal barrier layer 215 can be similar with the described TaN barrier layer 170a and thus provides a reliable conductive feature with reduced reduces sizes.
The second dielectric layer 210 can comprise a dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or a low-k dielectric material with dielectric constant less than 3.9. A third dielectric layer 230 with a contact via 240 therein is formed over the second dielectric layer 210, the contact via 240 electrically connecting to the conductive line 220. The third dielectric layer 230 can comprise a low-k dielectric material with dielectric constant less than 3.9. The contact via 240 comprises a metal barrier layer 250 and a conductive layer 260, and a seed layer (not shown) formed by, for example, conventional damascene process. The conductive layer 260 can be a copper layer and the metal barrier layer 250 can also be a TaN layer formed by the described atomic layer deposition 165. Herein, thickness of the metal barrier layer 250 can be similar with the described TaN barrier layer 170a and thus provides a reliable contact via with reduced sizes. Thus, one of the source/drain regions 120 is thus electrically connected by the contact plug 200, the conductive line 220 and the contact via 240 in the upper level.
Alternatively, the opening 160 can be formed in a position corresponding to the gate electrode 130 and the contact plug 200 comprised of a conformal TaN barrier layer 170a, a copper layer 190a and a copper seed layer 180a can be sequentially formed therein by fabrication steps illustrated in FIGS. 3–4, as shown in FIG. 6.
In addition, in FIG. 6, the second dielectric layer 210 with a conductive line 220, such as a copper line, and a metal barrier layer 215 formed therebetween, can be subsequently formed over the first dielectric layer 150 to electrically connect the conductive plug 200. Moreover, the third dielectric layer 230 with a contact via 240 comprised of the metal barrier layer 250 and the conductive layer 260, and a seed layer (not shown) therein can be subsequently formed over the second dielectric layer 210. The contact via 240 electrically connects the conductive line 220.
As shown in FIGS. 4 and 6, a semiconductor device with a copper contact is provided, comprising a substrate with at least one transistor thereon. A first dielectric layer covers the transistor and has an opening exposing an active region of the transistor. A TaN barrier layer is conformably formed in the opening by atomic layer deposition (ALD), having an ultra-thin thickness, and a copper layer is formed over the TaN barrier layer to fill the opening.
As shown in FIGS. 5 and 6, a copper interconnect is also provided on the semiconductor device, comprising an underlying conductive member (e.g. the conductive line 220) in a second dielectric layer. A third dielectric layer over the second dielectric layer has an opening therein, exposing a portion of the underlying conductive member. A TaN barrier layer conformally forms in the opening by atomic layer deposition (ALD) at minimal thickness, and a copper layer over the TaN barrier layer fills the opening.
The semiconductor devices with copper contact and copper interconnect as disclosed both utilizing an ultra-thin TaN barrier, formed with reduced thickness by ALD, providing optimal step coverage in openings, a reliable diffusion barrier to metals such copper, making it a good choice for use in sub-100 nm semiconductor fabrication technology, and functioning as a diffusion barrier for a structure with smaller CD. The TaN barrier also exhibits maximum adhesion between the copper seed layer and the dielectric layer.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

## Claims

1. A semiconductor device, comprising:
a substrate;
at least one transistor on the substrate;
a first dielectric layer on the transistor and having an opening exposing an active region of the transistor;
an atomic layer deposited (ALD) TaN barrier conformably lining the opening, at a thickness less than 20 Å; and
a copper layer over the atomic layer deposited (ALD) TaN barrier, filling the opening.

2. The semiconductor device of claim 1, wherein first dielectric layer comprises phosphorous-containing dielectric.

3. The semiconductor device of claim 2, wherein the phosphorous-containing dielectric is phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).

4. The semiconductor device of claim 1, wherein the active region is a source/drain region of the transistor.

5. The semiconductor device of claim 1, wherein the active region is a gate electrode of the transistor.

6. The semiconductor device of claim 1, further comprising a copper seed layer between the copper layer and the atomic layer deposited (ALD) TaN barrier.

7. A semiconductor device, comprising:
a substrate;
at least one transistor on the substrate;
a first dielectric layer covering the transistor and having an first opening exposing an active region of the transistor;
a first atomic layer deposited (ALD) TaN barrier conformably lining the first opening, at a thickness less than 20 Å;
a first copper layer over the first atomic layer deposited (ALD) TaN barrier, filling the first opening;
a second dielectric layer over the first dielectric layer and having a second opening that exposes a portion of the first copper layer;
a second atomic layer deposited (ALD) TaN barrier conformably lining the second opening, at a thickness less than 20 Å; and
a second copper layer over the second ALD TaN barrier layer, filling the second opening.

8. The semiconductor device of claim 7, wherein the second dielectric layer comprises phosphorous-containing dielectric.

9. The semiconductor device of claim 8, wherein the phosphorous-containing dielectric is phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).