# Patent

## Title
Electrostatic capacitance detecting device

## Abstract

The invention provides an electrostatic capacitance detection device. The electrostatic capacitance detection device can be formed of M individual power supply lines, N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines, each of the electrostatic capacitance detection elements is formed of a signal detection element and a signal amplification element, the signal detection element is formed of a capacitance detecting electrode and a capacitance detecting dielectric layer, the signal amplification element formed of a metal-insulator-semiconductor (MIS) type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer.

## Background
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electrostatic capacitance detection device, which reads surface contours of an object having a fine indentation, such as a fingerprint, by detecting an electrostatic capacitance, which changes according to the distance from the surface of the object.
2. Description of Related Art
Conventionally, an electrostatic capacitance detection device used for fingerprint sensor or the like is formed of a sensor electrode and a dielectric layer, provided on the sensor electrode, on a single crystal silicon substrate. See, for example, Japanese laid-open patent publication No. 11-118415, No. 12-346608, No. 13-56204 and No. 13-133213). FIG. 1 shows an operating principle of the conventional electrostatic capacitance detection device. A sensor electrode and a dielectric layer form an electrode and a dielectric layer of a capacitor, and a human body becomes the other electrode, which is grounded. The electrostatic capacitance CF of this capacitor changes depending on the indentation of a fingerprint contacting the surface of the dielectric layer. A capacitor having the electrostatic capacitance Cs is prepared on the semiconductor substrate, and the two capacitors are coupled in series and a predetermined voltage is applied thereon. This allows an electric charge Q to be generated between the two capacitors depending on the indentation of the fingerprint. The electric charge Q can be detected using a usual semiconductor technology, and surface contours of the object can be read.
SUMMARY OF THE INVENTION
However, because the conventional electrostatic capacitance detection devices are formed on a single crystal silicon substrate, there has been a problem that the devices are cracked when a finger is strongly pressed thereon when used for a fingerprint sensor. Furthermore, the fingerprint sensor inevitably requires a size of approximately 20 mm×20 mm for its application, and most of the area of the electrostatic capacitance detection device is dominated by a sensor electrode. The sensor electrode is, of course, formed on the single crystal silicon substrate, however, most area of the single crystal silicon substrate (beneath the sensor electrode), which is produced by consuming large amount of resources and labor, only plays a role of a supporting body. In other words, there has been a problem that the conventional electrostatic capacitance detection devices are not only expensive, but also have a large amount of waste and expense associated with their manufacture.
In addition, it is recently required strongly that a personal authenticating function is provided on cards, such as credit card and cash card, to enhance safety of cards. However, there has been a problem that the electrostatic capacitance detection devices manufactured on the conventional single crystal silicon substrate is not so flexible, therefore, the devices cannot be manufactured on a plastic substrate.
An object of the present invention is to provide an electrostatic capacitance detection device, which can operate stably, reduce unnecessary energy and labor during manufacturing, and can be manufactured on substrates other than the single crystal silicon substrate.
The invention is an electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance from the object. The electrostatic capacitance detection device can be formed of M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines. Each of the electrostatic capacitance detection elements can be formed of a signal detection element and a signal amplification element, the signal detection element is formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor. The reference capacitor can be formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode. The signal amplification element is formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer. Furthermore, a drain region of the MIS type thin film semiconductor device for signal amplification is connected to each of the individual power supply lines and the reference capacitor first electrode, and a gate electrode of the MIS type thin film semiconductor device for signal amplification is connected to the capacitance detecting electrode and the reference capacitor second electrode. A source region of the MIS type thin film semiconductor device for signal amplification is connected to the each of the individual output lines directly, or indirectly through a switching element. In the present invention, the dielectric layer of the reference capacitor and the gate insulating layer of the MIS type thin film semiconductor device for signal amplification are formed with a same material on a same layer. Furthermore, the reference capacitor first electrode and the semiconductor layer drain region are formed with a same material on a same layer. Furthermore, the reference capacitor second electrode and the gate electrode are formed with a same material on a same layer.
In the invention, using an area of the reference capacitor electrode of SR (μm2), a gate area of the MIS type thin film semiconductor device for signal amplification of ST (μm2), a thickness of the reference capacitor of tR (μm), a dielectric constant of the reference capacitor dielectric layer of ∈R, a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, the capacitance CR of the reference capacitor and the transistor capacitance of CT of the MIS type thin film semiconductor device for signal amplification are defined as

CR=∈0·∈R·SR/tR,

CT=∈0·∈ox·ST/tox

where ∈0 is the permittivity in vacuum, respectively, and using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), a dielectric constant of the capacitance detecting dielectric layer of ∈D, the element capacitance CD of the signal detection element is defined as

CD=∈0·∈D·SD/tD

where ∈0 is the permittivity in vacuum, and the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT. Sufficiently large generally means a difference of approximately ten times or more, therefore, in other words, the element capacitance CD satisfies a relation of

CD>10×(CR+CT),

whereas CR+CT is a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT. In the electrostatic capacitance detection device according to the present invention, the capacitance detecting dielectric layer is preferably located on the uppermost surface of the electrostatic capacitance detection device. When the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting the capacitance detecting dielectric layer, the capacitance CA of the object is defined as

CA=∈0·∈A·SD/tA

using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, an an area of the capacitance detecting electrode of SD, then the electrostatic capacitance detection device is configured so that CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object. As described above, if a difference of approximately ten times or more is recognized, it means sufficiently large, therefore, CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and the capacitance CA of the object satisfy a relation of

(CR+CT)>10×CA.

More ideally, the capacitance detecting dielectric layer is located on the uppermost surface of the electrostatic capacitance detection device, and using an area of the reference capacitor electrode of SR (μm2), a gate area of the MIS type thin film semiconductor device for signal amplification of ST (μm2), a thickness of the reference capacitor of tR (μm), a dielectric constant of the reference capacitor dielectric layer of ∈R, a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, the capacitance CR of the reference capacitor and the transistor capacitance of CT of the MIS type thin film semiconductor device for signal amplification are defined as

CR=∈0·∈R·SR/tR,

Ct=∈0·∈ox·ST/tox

where ∈0 is the permittivity in vacuum, respectively, and using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), a dielectric constant of the capacitance detecting dielectric layer of ∈D, the element capacitance CD of the signal detection element is defined as

CD=∈0·∈D·SD/tD

where ∈0 is the permittivity in vacuum, and the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and when the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting the capacitance detecting dielectric layer, the capacitance CA of the object is defined as

CA=∈0·∈A·SD/tA

using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of the capacitance detecting electrode of SD, then the electrostatic capacitance detection device is configured so that CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object. More specifically, the electrostatic capacitance detection device is configured so that the element capacitance CD, CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and the capacitance CA of the object satisfy a relation of

CD>10×(CR+CT)>100×CA.

The invention is an electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance from the object, wherein the electrostatic capacitance detection device is formed of M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines. Each of the electrostatic capacitance detection elements can be formed of a signal detection element and a signal amplification element. The signal detection element is formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor, the reference capacitor is formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode, the signal amplification element is formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer, and a part of the drain region and a part of the gate electrode of the MIS type thin film semiconductor device for signal amplification form an overlapped portion via a gate insulating layer, and the overlapped portion forms a reference capacitor. Specifically, the drain region side of semiconductor layer including a donor type or acceptor type impurity in the semiconductor layer forming a MIS type thin film semiconductor device for signal amplification becomes a reference capacitor first electrode, which is directly or indirectly coupled with the individual power supply lines. The gate electrode of the MIS type thin film semiconductor device for signal amplification is a common electrode with the reference capacitor second electrode, and coupled to the capacitance detecting electrode. The source region of the MIS type thin film semiconductor device for signal amplification is directly or indirectly coupled to the individual output lines.
In the invention, using a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer drain region, L1 (μm), a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer channel forming region, L2 (μm), a width of the gate electrode of W (μm), a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, the capacitance CR of the reference capacitor and the transistor capacitance of CT of the MIS type thin film semiconductor device for signal amplification are defined as

CR=∈0·∈ox·L1·W/tox,

CT=∈0·∈ox·L2·W/tox

where ∈0 is the permittivity in vacuum, respectively, and using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), a dielectric constant of the capacitance detecting dielectric layer of ∈D, the element capacitance CD of the signal detection element is defined as

CD=∈0·∈D·SD/tD

where so is the permittivity in vacuum, and the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT. Sufficiently large generally means a difference of approximately ten times or more, therefore, in other words, the element capacitance CD satisfies a relation of

CD>10×(CR+CT),

whereas CR+CT is a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT. In the electrostatic capacitance detection device according to the invention, the capacitance detecting dielectric layer is preferably located on the uppermost surface of the electrostatic capacitance detection device. When the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting the capacitance detecting dielectric layer, the capacitance CA of the object is defined as

CA=∈0·∈A·SD/tA

using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of the capacitance detecting electrode of SD, then the electrostatic capacitance detection device is configured so that CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object. As described above, if a difference of approximately ten times or more is recognized, it can mean sufficiently large, therefore, CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and the capacitance CA of the object satisfy a relation of

(CR+CT)>10×CA.

More ideally, the capacitance detecting dielectric layer is located on the uppermost surface of the electrostatic capacitance detection device, and using a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer drain region, L1 (μm), a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer channel forming region, L2 (μm), a width of the gate electrode of W (μm), a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, the capacitance CR of the reference capacitor and the transistor capacitance of CT are defined as

CR=∈0·∈ox·L1W/tox,

CT=∈0·∈ox·L2·W/tox where so is the permittivity in vacuum, respectively, and using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), a dielectric constant of the capacitance detecting dielectric layer of ∈D, the element capacitance CD of the signal detection element is defined as

CD=∈0·∈D·SD/tD

where so is the permittivity in vacuum, and the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and when the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting the capacitance detecting dielectric layer, the capacitance CA of the object is defined as

CA=∈0·∈A·SD/tA

using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of the capacitance detecting electrode of SD, then the electrostatic capacitance detection device is configured so that CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object. More specifically, the electrostatic capacitance detection device is configured so that the element capacitance CD, CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and the capacitance CA of the object satisfy a relation of

CD>10×(CR+CT)>100×CA.

The invention is an electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance from the object. The electrostatic capacitance detection device is formed of M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines, and furthermore, a power supply selecting circuit coupled to the M individual power supply lines. Each of the electrostatic capacitance detection elements can be formed of a capacitance detecting electrode, a capacitance detecting dielectric layer, a reference capacitor and a signal amplification element, the reference capacitor is formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode, the signal amplification element is formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer. In this case, a source region of the MIS type thin film semiconductor device for signal amplification element is directly or indirectly coupled to each of the individual output lines, a drain region of the MIS type thin film semiconductor device for signal amplification element is connected to each of the individual power supply lines and the reference capacitor first electrode, and a gate electrode of the MIS type thin film semiconductor device for signal amplification element is connected to the capacitance detecting electrode and the reference capacitor second electrode. In the electrostatic capacitance detection device according to the invention, the individual output lines are wired by the first wiring, the individual power supply lines are wired by the second wiring, the capacitance detecting electrode is wired by the third wiring, and the first, second, and third wirings are electrically insulated via the insulating layers.
The invention is an electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance from the object. The electrostatic capacitance detection device is formed of M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines, and furthermore, an output signal selecting circuit coupled to the N individual output lines. Each of the electrostatic capacitance detection elements is formed of a capacitance detecting electrode, a capacitance detecting dielectric layer, a reference capacitor and a signal amplification element, the output signal selecting circuit is formed of a common output line and a path gate for output signal, the reference capacitor is formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode, the signal amplification element is formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer, the path gate for output signal is formed of a MIS type thin film semiconductor device for output signal path gate, including a gate electrode, a gate insulating layer and a semiconductor layer.
In this case, a source region of the MIS type thin film semiconductor device for signal amplification element is directly or indirectly coupled to each of the individual output lines, a drain region of the MIS type thin film semiconductor device for signal amplification element is connected to each of the individual power supply lines and the reference capacitor first electrode, a gate electrode of the MIS type thin film semiconductor device for signal amplification element is connected to the capacitance detecting electrode and the reference capacitor second electrode, a source region of the MIS type thin film semiconductor device for output signal path gate is connected to the common output line, and a drain region of the MIS type thin film semiconductor device for output signal path gate is also coupled to each of the individual output line. Furthermore, a gate electrode of the MIS type thin film semiconductor device for output signal path gate is connected to an output line for output selection, which supplies a signal for selecting what individual output line is selected among N individual output lines. In the electrostatic capacitance detection device according to the present invention, the individual output lines and the common output line are wired by the first wiring, the individual power supply lines and the output line for output selection are wired by the second wiring, the capacitance detecting electrode is wired by the third wiring, and the first, second, and third wirings are electrically insulated via the insulating layers.
The invention is an electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance from the object. The electrostatic capacitance detection device can be formed of M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines, and furthermore, a power supply selecting circuit coupled to the M individual power supply lines, and an output signal selecting circuit coupled to the N individual output lines. Each of the electrostatic capacitance detection elements is formed of a capacitance detecting electrode, a capacitance detecting dielectric layer, a reference capacitor and a signal amplification element, the output signal selecting circuit is formed of a common output line and a path gate for output signal, the reference capacitor is formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode, the signal amplification element is formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer, the path gate for output signal is formed of a MIS type thin film semiconductor device for output signal path gate, including a gate electrode, a gate insulating layer and a semiconductor layer.
In this case, a source region of the MIS type thin film semiconductor device for signal amplification element is directly or indirectly coupled to each of the individual output lines, a drain region of the MIS type thin film semiconductor device for signal amplification element is connected to each of the individual power supply lines and the reference capacitor first electrode, a gate electrode of the MIS type thin film semiconductor device for signal amplification element is connected to the capacitance detecting electrode and the reference capacitor second electrode, a source region of the MIS type thin film semiconductor device for output signal path gate is connected to the common output line, and a drain region of the MIS type thin film semiconductor device for output signal path gate is connected to each of the individual output lines. Furthermore, a gate electrode of the MIS type thin film semiconductor device for output signal path gate is connected to an output line for output selection, which supplies a signal for selecting what individual output line is selected among N individual output lines. In the electrostatic capacitance detection device according to the invention, the individual output lines and the common output line are wired by the first wiring, the individual power supply lines and the output line for output selection are wired by the second wiring, the capacitance detecting electrode is wired by the third wiring, and the first, second, and third wirings are electrically insulated via the insulating layers.
A conventional technology using a single crystal silicon substrate (single crystal silicon sensor) can only form a small electrostatic capacitance detection device in a square shape of approximately having a few millimeter in each side on a plastic substrate, however, an electrostatic capacitance detection device having the same performance as the conventional single crystal silicon sensor can be realized with a thin film semiconductor device according to the present invention. Furthermore, a sensor area of the electrostatic capacitance detection device can be also increased to approximately 100 times easily, and additionally, this excellent electrostatic capacitance detection device can be formed on a plastic substrate. In addition, the indentation information of an object can be detected with significant high precision. As a result, when this electrostatic capacitance detection device is mounted, for example, on a smart card, an effect of remarkably enhanced security level for the card can be recognized. Furthermore, the conventional electrostatic capacitance detection device, using the single crystal silicon substrate, utilizes only a part of the electrostatic capacitance detection device for the single crystal silicon semiconductor, resulting in spending a lot energy and labor in waste. On the other hand, the invention eliminates the above described waste, and has an effect that is useful in preserving the global environment.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described with reference to the accompanying drawings, wherein like numerals reference like elements, and wherein:
FIG. 1 is a diagram explaining an operating principle in the conventional art;
FIG. 2 is a diagram explaining an operating principle in the present invention;
FIG. 3 is a diagram explaining an operating principle in the present invention;
FIG. 4A is a diagram explaining an element structure according to the present invention;
FIG. 4B is a diagram explaining an element structure according to the present invention;
FIG. 5 is a diagram explaining a principle of the present invention;
FIG. 6 is a diagram explaining an overall configuration of the present invention;
FIG. 7 is a diagram explaining a clock generator circuit of the present invention;
FIG. 8 is a diagram explaining a power supply selecting circuit configuration of the present invention
FIG. 9 is a diagram explaining an output signal selecting circuit configuration of the present invention;
FIG. 10 is a diagram explaining an information obtaining part circuit configuration of the present invention; and
FIG. 11 is a transfer characteristic diagram of a thin film semiconductor device used in the embodiment.



DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The invention manufactures an electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance with the object with a metal-insulator-semiconductor (MIS) type thin film semiconductor. Because the thin film semiconductor device is usually manufactured on a glass substrate, it is known as a technology, which inexpensively manufactures semiconductor integrated circuits requiring a large area and is specifically applied to liquid crystal display devices. Therefore, when the electrostatic capacitance detection device, which is applied to a finger print sensor or the like, is manufactured by the thin film semiconductor device, it is unnecessary to use an expensive substrate, such as a single crystal silicon substrate, which is manufactured by consuming large amount of energy, thereby capable of inexpensively manufacturing the device without consuming precious resources on the earth. Furthermore, as for the thin film semiconductor device, a semiconductor integrated circuit can be manufactured on a plastic substrate by using a transfer technology called as the SUFTLA (Japanese laid-open patent publication No. 11-312811 or S. Utsunomiya et. al. Society for Information Display p. 916 (2000)), therefore, the electrostatic capacitance detection device can be formed on the plastic substrate without using the single crystal silicon substrate.
A current technology for the thin film semiconductor device cannot manufacture the electrostatic capacitance detection device applying the conventional operating principle shown in FIG. 1. Because an electric charge Q induced between the two capacitors coupled in series is so small, the electric charge Q can be accurately read by using a single crystal silicon LSI technology, which allows a high precision detection, however, the transistor characteristic of the thin film semiconductor device is not so excellent as that of the single crystal silicon LSI technology and the characteristic deviation among thin film semiconductor devices is so large, therefore, the electric charge Q cannot be accurately read. Thus, the electrostatic capacitance detection device according to the invention is formed of M (M is an integer of one or more) individual power supply lines and N (N is an integer of one or more) individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines, wherein each of the electrostatic capacitance detection elements is formed of a signal detection element and a signal amplification element. The signal detection element can be formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor, and the electric charge Q is generated on the capacitance detecting electrode depending on the electrostatic capacitance. In the present invention, the electric charge Q is amplified and converted into current by the signal amplification element provided on each of the electrostatic capacitance detection elements. Specifically, the signal amplification element is formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer, wherein the gate electrode of the MIS type thin film semiconductor device for signal amplification is connected to the capacitance detecting electrode and either one of the electrodes of the reference capacitor (for example, the second electrode).
FIG. 2 shows an operating principle of the invention. Electric charges, which are generated between a capacitor having the electrostatic capacitance CS and a capacitor having the electrostatic capacitance CF that changes depending on surface contours of the object, change a gate voltage of the MIS type thin film semiconductor device for signal amplification. When a predetermined voltage is applied on the drain region of the thin film semiconductor device, a current I, flowing between the source and drain of the thin film semiconductor device, is significantly amplified depending on the induced electric charges Q. The induced electric charges Q are preserved without flowing to anywhere, therefore, the current I can be easily measured by increasing the drain voltage or extending the measuring time. Accordingly, the surface shape of the object can be measured with sufficient accuracy even using the thin film semiconductor device.
As described above, in the invention, the MIS type thin film semiconductor device for signal amplification is used as the signal amplification element. In this case, the MIS type thin film semiconductor device for signal amplification is also used as a capacitor having the electrostatic capacitance CS, and furthermore, a reference capacitor is provided to increase an electrostatic capacitance and enhance detecting sensitivity. In other words, in place of the electrostatic capacitance CS, a new electrostatic capacitance is to be a summation of the transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification and the capacitance CR of the reference capacitor, which is for increasing an electrostatic capacitance. This allows the adjustment of electric capacitance, and furthermore, the simplification of the structure and the manufacturing process. Furthermore, a high speed detecting operation can be realized by reducing a length of the semiconductor channel forming region. In addition, it is effective to combine the two power supply lines shown in FIG. 2 as a common power supply Vdd, because the redundant wirings in the electrostatic capacitance detection device can be omitted. FIG. 3 shows an equivalent circuit diagram relating to the operating principle in such a state. A capacitor having the electrostatic capacitance CF changing depending on surface contours of the object and a capacitor having the transistor capacitance CT are coupled in series, and at the same time, the capacitor having the electrostatic capacitance CF and a capacitor having the capacitance CR of the reference capacitor are coupled in series. Strictly speaking, the transistor capacitance CT is the electrostatic capacitance, formed between the drain electrode and the gate electrode of the MIS type thin film semiconductor device for signal amplification. In order to realize the configuration shown in FIG. 3, the source region of the MIS type thin film semiconductor device for signal amplification is connected to each of the individual output lines, the drain region of the MIS type thin film semiconductor device for signal amplification is connected to each of the individual power supply lines and the reference capacitor first electrode, and furthermore, the gate electrode of the MIS type thin film semiconductor device for signal amplification and the reference capacitor second electrode are coupled, then a voltage Vdd is applied on the individual power supply lines and the current I, changing depending on the surface contours of the object, is outputted from the individual output lines.
A structure of the electrostatic capacitance detection element realizing the invention is described with reference to FIG. 4. As for the MIS type thin film semiconductor device for signal amplification forming a signal amplification element of the electrostatic capacitance detection element, the essential requirements are a semiconductor layer including a source region, a channel forming region and a drain region, and a gate insulating layer and a gate electrode. A donor type or acceptor type impurity is doped into the semiconductor layer in the source region and the drain region, then an N type or P type semiconductor is formed. The gate electrode overlaps over the semiconductor layer drain region via the gate insulating layer, and a portion overlapped in this way becomes a reference capacitor. The reference capacitor is formed of a reference capacitor first electrode, a reference capacitor dielectric layer, and a reference capacitor second electrode.
As shown in FIG. 4(A), the first electrode becomes a common electrode with the drain region as a lower electrode, and the second electrode becomes a common electrode with the gate electrode as an upper electrode, however, either the first electrode or the second electrode may become the upper electrode. When a bottom gate type transistor, in which the gate electrode is located in a lower position with respect to the semiconductor layer, is used as the MIS thin film semiconductor device for signal amplification, the reference capacitor lower electrode becomes a common electrode with the gate electrode, and the drain region becomes a common electrode with the reference capacitor upper electrode, thereby to simplify the structure. The reference capacitor first electrode and the semiconductor layer drain region are formed with a same layer (semiconductor layer in which a impurity is doped) on the same layer (base protecting layer), and the reference capacitor second electrode and the gate electrode are also formed with a same layer (metallic layer) on a same layer (gate insulating layer). The gate electrode of the MIS thin film semiconductor device for signal amplification is connected to the capacitance detecting electrode, which is covered with a capacitance detecting dielectric layer. Thus, the semiconductor layer drain region and the reference capacitor first electrode have a same potential, and the gate electrode of the MIS thin film semiconductor device for signal amplification and the reference capacitor second electrode have a same potential and are coupled to the capacitance detecting electrode, thereby realizing the equivalent circuit shown in FIG. 3.
As for the configuration shown in FIG. 4(A), the reference capacitor and the signal amplification element are arranged to be overlapped with each other, thereby enhancing space-use efficiency, and realizing an electrostatic capacitance detection device having high sensitivity. Furthermore, prior to forming the gate electrode, the reference capacitor lower electrode and the drain region are formed, and after forming the gate electrode, the source region is formed by the self-alignment method (the source region is formed by ion implanting using the gate electrode as a mask), therefore, there is an effect that the channel forming region can be made smaller than the resolution level that a exposure device has. In general, the resolution of an exposure device is inferior to the alignment accuracy of the exposure device. For this reason, in the configuration of the invention, the channel forming region length is formed using the alignment precision of the exposure device, not the resolution of the exposure device, therefore, the size of the channel forming region length can be fined to the level of alignment precision, thereby realizing a high speed operation of the electrostatic capacitance detecting circuit.
In FIG. 4(A), the MIS thin film semiconductor device for signal amplification is covered with a first interlayer insulating layer. A first wiring is connected to the source region of the MIS thin film semiconductor device for signal amplification, and a second wiring is connected to the drain region of the MIS thin film semiconductor device for signal amplification. The individual output lines are formed by the first wiring and the individual power supply lines are formed by the second wiring. A second interlayer insulating layer is provided between the first wiring and the second wiring, and electrically insulates the first wiring and the second wiring. The capacitance detecting electrode, forming the signal detection element of each of the electrostatic capacitance detection elements, is connected to the gate electrode of the MIS thin film semiconductor device for signal amplification, and formed on a third interlayer insulating layer. The capacitance detecting electrode is wired by the third wiring. Between the second wiring and the third wiring, the third interlayer insulating layer is provided, and electrically insulates the second wiring and the third wiring. A parasitic capacitance, generated between the first wiring and the capacitance detecting electrode, can be minimized by wiring the capacitance detecting electrode with the third wiring, and a small amount of electrostatic capacitance can be detected with high sensitivity by minimizing the dielectric constant of the second interlayer insulating layer and the dielectric constant of the third interlayer insulating layer as much as possible. The capacitance detecting dielectric layer covers on the capacitance detecting electrode, and is located on the uppermost surface of the electrostatic capacitance detection device. The capacitance detecting dielectric layer also plays a role of protective layer for the electrostatic capacitance detection device.
As for the example shown in FIG. 4(A), the overlapped portion of the gate electrode and the drain electrode of the signal amplification element is the reference capacitor, however, the reference capacitor and the MIS thin layer transistor for amplifying signal may be separated from each other, as shown in FIG. 4(B). The reference capacitor and the thin layer transistor for amplifying signal are coupled via a conductive material, such as a doped semiconductor layer. The transistor for amplifying signal is preferably as small as possible in order to operate with a high speed. On the other hand, there exists an optimum capacitance value for a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT depending on the to-be-detected object. As for the configuration shown in FIG. 4(B), the transistor can be made smaller, and at the same time the value of CR+CT can be optimized, therefore, the sensitivity of the electrostatic capacitance detection device according to the present invention can be enhanced. A portion for a contact hole, conducting the individual power supply lines (second wiring) and the drain region, is preferably provided between the reference capacitor and the MIS type thin layer transistor for amplifying signal.
As for the above configuration, in order that the MIS type thin film semiconductor device for signal amplification according to the invention effectively conduct a function of the signal amplification, the transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification, the capacitance CR of the reference capacitor, and the element capacitance CD of the signal detection element have to be adequately determined. Next, a relation between these will be described with reference to FIG. 5.
At first, assume a situation that a protrusion portion of to-be-measured object contacts the capacitance detecting dielectric layer, and the object is electrically grounded. Specifically, assume a situation that the electrostatic capacitance detection device is used as a finger print sensor, and a ridge of a fingerprint contact on the surface of the capacitance detecting dielectric layer. By using an area of the reference capacitor electrode of SR(μm2), a length of the reference capacitor electrode of LR(μm), a width of the reference capacitor electrode of WR(μm), an area of the gate electrode of ST(μm2), a length of the gate electrode of LT(μm), and a width of the gate electrode of WT(μm) of the MIS type thin film semiconductor device for signal amplification, a thickness of the reference capacitor dielectric layer of tR(μm), a dielectric constant of the reference capacitor dielectric layer of ∈R, a thickness of the gate insulating layer of tox(μm), and a dielectric constant of the gate insulating layer of ∈ox, the capacitance CR of the reference capacitor and the transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification are defined as

CR=∈0·∈R·SR/tR=∈0·␣R·LR·WR/tR,

CT=∈0·∈ox·ST/tox=∈0·␣ox·LT·WT/tox

where ∈0 is the permittivity in vacuum, respectively. When the reference capacitor and the signal amplification element shown in FIG. 4(A) are integrally formed, using a length of the gate electrode, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and a drain region of the semiconductor film, L1 (μm), a length of the gate electrode, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and a semiconductor layer channel forming region, L2 (μm), a width of the gate electrode of W (μm), a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, the capacitance CR of the reference capacitor and the transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification are defined as

CR=∈0·∈R·SR/tR=∈0·∈ox·L1·W/tox,

CT=∈0·∈ox·ST/tox=∈0·∈ox·L2·W/tox

where ∈0 is the permittivity in vacuum, respectively. Furthermore, using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), and a dielectric constant of the signal detection element of ∈D, the element capacitance CD of the signal detection element is defined as

CD=∈0·∈D·SD/tD

where ∈0 is the permittivity in vacuum. The surface of object becomes a ground electrode for the element capacitance CD, and the capacitance detecting electrode is equivalent to the other electrode by interposing the capacitance detecting dielectric layer. Because the capacitance detecting electrode is connected to the gate electrode of the MIS type thin film semiconductor device for signal amplification and the reference capacitor second electrode, a capacitor having the element capacitance CD and a capacitor having the transistor capacitance CT are coupled in series, and at the same time, the capacitor having the element capacitance CD and a capacitor having the capacitance CR of the reference capacitor are coupled in series. A voltage Vdd is applied to the two capacitors coupled in series (FIG. 5(A)). Because the applied voltage is divided depending on the electrostatic capacitance, a voltage VGT, which is applied on the gate electrode of the MIS type thin film semiconductor device for signal amplification in this state, becomes as follows;




  
    V
    GT
  
  =
  
    
      V
      dd
    
    
      1
      +
      
        
          C
          D
        
        
          (
          
            
              C
              R
            
            +
            
              C
              T
            
          
          )
        
      
    
  




Therefore, when the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT,

CD>>(CR+CT)

the gate voltage is approximated as

VGT≈0

and the voltage is rarely applied to the gate electrode.
As a result, the MIS type thin film semiconductor device for signal amplification is in OFF state, and the current I becomes very small. After all, in order that the signal amplification element rarely flows current when a protrusion portion of the object corresponding to a ridge of a fingerprint contacts the electrostatic capacitance detection device, it is necessary to adjust a gate electrode area, a gate electrode length, a width of the gate electrode, a material of the gate insulating layer, a thickness of the gate insulating layer, an area of the reference capacitor electrode, a length of the reference capacitor electrode, a width of the reference capacitor electrode, a material of the reference capacitor dielectric layer, a thickness of the reference capacitor dielectric layer, an area of capacitance detecting electrode, a material of the capacitance detecting dielectric layer and a thickness of the capacitance detecting dielectric layer or the like, which form the electrostatic capacitance detection device, so that the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT. Sufficiently large generally means a difference of approximately ten times. In other words, it is satisfactory when the element capacitance CD satisfies a relation of

CD>10×(CR+CT),

whereas CR+CT is a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT. In this case, a ratio of VGT/Vdd becomes less than approximately 0.1 and the thin film semiconductor device cannot be in ON state. In order to reliably detect the protrusion portion of the object, it is important that the MIS type thin film semiconductor device for signal amplification is in OFF state when the protrusion portion of the object contacts the electrostatic capacitance detection device. Therefore, when a positive power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) N type transistor, in which a drain current does not flow when the gate voltage is nearly zero, is preferably used as the MIS type thin film semiconductor device for signal amplification. More ideally, an N type MIS type thin film semiconductor device for signal amplification, which satisfies a relation of




  
    
      
        
          
            0
            <
            
              0.1
              ×
              
                V
                dd
              
            
            <
            
              V
              min
            
          
          ,
        
        ⁢
        
          
        
      
    
  
  
    
      
        0
        <
        
          
            V
            dd
          
          
            1
            +
            
              
                C
                D
              
              
                (
                
                  
                    C
                    R
                  
                  +
                  
                    C
                    T
                  
                
                )
              
            
          
        
        <
        
          V
          min
        
      
    
  




whereas the Vmin is a gate voltage (minimum gate voltage), at which the drain current in transfer characteristic becomes the minimum, is used.
On the other hand, when a negative power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) P type transistor, in which a drain current does not flow when the gate voltage is nearly zero, is used as the MIS type thin film semiconductor device for signal amplification. Ideally, a P type MIS type thin film semiconductor device for signal amplification, which satisfies a relation of




  
    
      
        
          
            
              V
              min
            
            <
            
              0.1
              ×
              
                V
                dd
              
            
            <
            0
          
          ,
        
        ⁢
        
          
        
      
    
  
  
    
      
        
          V
          min
        
        <
        
          
            V
            dd
          
          
            1
            +
            
              
                C
                D
              
              
                (
                
                  
                    C
                    R
                  
                  +
                  
                    C
                    T
                  
                
                )
              
            
          
        
        <
        0
      
    
  




whereas the Vmin is a minimum gate voltage of the P type MIS type thin film semiconductor device for signal amplification, is used.
This allows the protrusion portion of object to be reliably detected in a state that the current I is in very small.
Next, assume a situation that the object does not contact the capacitance detecting dielectric layer and is apart from the capacitance detecting dielectric layer with an object distance of tA. In other words, a protrusion portion of the to-be-measured object is above the capacitance detecting dielectric layer, and the object is electrically grounded. Specifically, when the electrostatic capacitance detection device is used as a fingerprint sensor, assume detecting a state that a valley of a fingerprint is above the surface of the electrostatic capacitance detection device. As described above, it is preferable for the electrostatic capacitance detection device according to the present invention that the capacitance detecting dielectric layer is located at the uppermost surface of the electrostatic capacitance detection device. FIG. 5(B) shows an equivalent circuit diagram at this time. Because the surface of the object does not contact the capacitance detecting dielectric layer, a new capacitor, using air as a dielectric substance, is formed between the capacitance detecting dielectric layer and the surface of the object. This is called as the capacitance CA of the object, defined as

CA=∈0·∈A·SD/tA,

using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of capacitance detecting electrode of SD. Thus, in the state that the object is apart from the capacitance detecting dielectric layer, the transistor capacitance CT and the capacitance CR of the reference capacitor are coupled in parallel, the capacitors having the capacitance of (CR+CT), the element capacitance CD, and the capacitance CA of the object are coupled in series, and the voltage Vdd is applied on the capacitors (FIG. 5B). Because the applied voltage is divided into these capacitors depending on the electrostatic capacities, a voltage VGV, which is applied on the gate electrode of the MIS type thin film semiconductor device for signal amplification in this state becomes as follows.




  
    V
    GV
  
  =
  
    
      V
      dd
    
    
      1
      +
      
        
          1
          
            (
            
              
                C
                R
              
              +
              
                C
                T
              
            
            )
          
        
        ·
        
          (
          
            1
            
              
                1
                /
                
                  C
                  D
                
              
              +
              
                1
                /
                
                  C
                  A
                
              
            
          
          )
        
      
    
  




On the other hand, in the present invention, each of the electrostatic capacitance detection elements is made so as to satisfy the condition of

CD>>(CR+CT)

so that the drain current becomes significantly small when the object contacts the electrostatic capacitance detection device. Therefore, the VGV is further approximated to




  
    V
    GV
  
  ≈
  
    
      
        V
        dd
      
      
        1
        +
        
          
            C
            A
          
          
            (
            
              
                C
                R
              
              +
              
                C
                T
              
            
            )
          
        
      
    
    .
  




After all, when CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object,

(CR+CT)>>CA

the gate voltage VGV is as follows

VGV≈Vdd

and can be substantially equal to the power supply voltage Vdd.
As a result, the MIS type thin film semiconductor device for signal amplification can be in ON state, and the current I becomes significantly large. In order that the signal amplification element flows a large current when a recessed portion of the object corresponding to a valley of a fingerprint is above the electrostatic capacitance detection device, it is necessary to configure an gate electrode area, a gate electrode length, a width of the gate electrode, a material of the gate insulating layer, a thickness of the gate insulating layer, an area of the reference capacitor electrode, a length of the reference capacitor electrode, a width of the reference capacitor electrode, a material of the reference capacitor dielectric layer, a thickness of the reference capacitor dielectric layer, an area of the capacitance detecting electrode, a material of the capacitance detecting dielectric layer, and a thickness of the capacitance detecting dielectric layer, or the like, which form the electrostatic capacitance detection device, so that CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT is sufficiently larger than the capacitance CA of the object. As described above, sufficiently large means a difference of approximately ten times, therefore, it is satisfactory when CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and the capacitance CA of the object satisfy a relation of

(CR+CT)>10×CA.

In this case, a ratio of VGT/Vdd becomes larger than approximately 0.91, and the semiconductor device can be easily in ON state. To reliably detect the recessed portion of the object, it is important that the MIS type thin film semiconductor device for signal amplification becomes ON state when the recessed portion of the object approaches to the electrostatic capacitance detection device. When a positive power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) N type transistor is used as the MIS type thin film semiconductor device for signal amplification, and the threshold voltage Vth of this transistor is preferably smaller than the VGV.




  
    
      
        0
        <
        
          V
          th
        
        <
        
          
            V
            dd
          
          
            1
            +
            
              
                1
                
                  (
                  
                    
                      C
                      R
                    
                    +
                    
                      C
                      T
                    
                  
                  )
                
              
              ·
              
                (
                
                  1
                  
                    
                      1
                      /
                      
                        C
                        D
                      
                    
                    +
                    
                      1
                      /
                      
                        C
                        A
                      
                    
                  
                
                )
              
            
          
        
      
    
  
  
    
      
        
          0
          <
          
            V
            th
          
          <
          
            
              V
              dd
            
            
              1
              +
              
                
                  C
                  A
                
                
                  (
                  
                    
                      C
                      R
                    
                    +
                    
                      C
                      T
                    
                  
                  )
                
              
            
          
        
        ⁢
        
          
        
      
    
  




More ideally, an N type MIS type thin film semiconductor device for signal amplification, which satisfies a relation of

0<Vth<0.91×Vdd,

is used. On the other hand, when a negative power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) P type transistor is used as the MIS type thin film semiconductor device for signal amplification, and ideally, the threshold voltage Vth of the P type MIS type thin film semiconductor device for signal amplification is preferably larger than the VGV. More ideally, an N type MIS type thin film semiconductor device for signal amplification, which satisfies a relation of




  
    
      
        
          
            V
            dd
          
          
            1
            +
            
              
                1
                
                  (
                  
                    
                      C
                      R
                    
                    +
                    
                      C
                      T
                    
                  
                  )
                
              
              ·
              
                (
                
                  1
                  
                    
                      1
                      /
                      
                        C
                        D
                      
                    
                    +
                    
                      1
                      /
                      
                        C
                        A
                      
                    
                  
                
                )
              
            
          
        
        <
        
          V
          th
        
        <
        0
      
    
  
  
    
      
        
          
            
              V
              dd
            
            
              1
              +
              
                
                  C
                  A
                
                
                  (
                  
                    
                      C
                      R
                    
                    +
                    
                      C
                      T
                    
                  
                  )
                
              
            
          
          <
          
            V
            th
          
          <
          0
        
        ⁢
        
          
        
      
    
  




is used. On the other hand, when a negative power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) P type transistor is used as the MIS type thin film semiconductor device for signal amplification, and ideally, the threshold voltage Vth of the P type MIS type thin film semiconductor device for signal amplification is preferably larger than the VGV.
More ideally, a P type MIS type thin film semiconductor device for signal amplification, which satisfies a relation of

0.91×Vdd<Vth<0,

is used. This allows the recessed portion of the object to be detected securely in a state of the significant large current I.
After all, in order to accurately recognizes the indentation of the object by rarely flowing current in the signal amplification element when the protrusion portion of the object corresponding to a ridge of a fingerprint or the like contacts the electrostatic capacitance detection device, and at the same time, by flowing large current in the signal amplification element when the recessed portion of the object corresponding to a valley of a fingerprint or the like approaches the electrostatic capacitance detection device, it is necessary for the electrostatic capacitance detection element that the capacitance detecting dielectric layer is located on the uppermost of the electrostatic capacitance detection device, or to provide a conductive layer separated for each of the electrostatic capacitance detection elements on the capacitance detecting dielectric layer and to adjust a gate electrode area of ST (μm2), a gate electrode length of LT (μm), and a width of the gate electrode of WT (μm) of the MIS type thin film semiconductor device for signal amplification, a thickness of the gate insulating layer of ∈ox (μm), a dielectric constant of the gate insulating layer of ∈ox, an area of the reference capacitor electrode of SR (μm2), a length of the reference capacitor electrode of LR (μm), a width of the reference capacitor electrode of WR (μm), a thickness of the reference capacitor dielectric layer of tR (μm), a dielectric constant of the reference capacitor dielectric layer of ∈R, an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), a dielectric constant of the capacitance detecting dielectric layer of ∈D or the like so that the element capacitance CD is sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and ideally, the electrostatic capacitance detection device is configured so that CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object when the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting. More specifically, the electrostatic capacitance detection device is configured so that the element capacitance CD, CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, and the capacitance CA of the object satisfy a relation of

CD>10×(CR+CT)>100×CA.

Furthermore, when a positive power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) N type transistor is preferably used as the MIS type thin film semiconductor device for signal amplification, and the minimum gate voltage Vmin of this N type transistor satisfies a relation of



  
    0
    <
    
      0.1
      ×
      
        V
        dd
      
    
    <
    
      
        V
        
          min
          ⁢
          
            
          
        
      
      ⁢
      
        
      
      ⁢
      or
    
  




  
    0
    <
    
      
        V
        dd
      
      
        1
        +
        
          
            C
            D
          
          
            (
            
              
                C
                R
              
              +
              
                C
                T
              
            
            )
          
        
      
    
    <
    
      V
      min
    
  



And furthermore, ideally, an enhancement type N type transistor, in which the threshold voltage Vth is smaller than the VGV, that is, satisfying a relation of



  
    0
    <
    
      V
      th
    
    <
    
      0.91
      ×
      
        V
        dd
      
      ⁢
      
        
      
      ⁢
      or
    
  




  
    
      0
      <
      
        V
        th
      
      <
      
        
          V
          dd
        
        
          1
          +
          
            
              C
              A
            
            
              (
              
                
                  C
                  R
                
                +
                
                  C
                  T
                
              
              )
            
          
        
      
    
    ,
  



, is used.
On the other hand, when a negative power supply is used for the power supply voltage Vdd, an enhancement type (normally off type) P type transistor is preferably used as the MIS type thin film semiconductor device for signal amplification, and the minimum gate voltage Vmin of this P type transistor satisfies a relation of




  
    
      
        
          
            
              V
              min
            
            <
            
              0.1
              ×
              
                V
                dd
              
            
            <
            
              0
              ⁢
              
                
              
              ⁢
              or
            
          
          ⁢
          
            
          
        
      
    
    
      
        
          
            
              V
              min
            
            <
            
              
                V
                dd
              
              
                1
                +
                
                  
                    C
                    D
                  
                  
                    (
                    
                      
                        C
                        R
                      
                      +
                      
                        C
                        T
                      
                    
                    )
                  
                
              
            
            <
            0
          
          ⁢
          
            
          
        
      
    
  
  ⁢
  
    
  




And furthermore, ideally, an enhancement type P type transistor, in which the threshold voltage Vth is larger than the VGV, that is, satisfying a relation of




  
    0.91
    ×
    
      V
      dd
    
  
  <
  
    V
    th
  
  <
  
    0
    ⁢
    
      
    
    ⁢
    or
    ⁢
    
      
    
    ⁢
    
      
        V
        dd
      
      
        1
        +
        
          
            C
            A
          
          
            (
            
              
                C
                R
              
              +
              
                C
                T
              
            
            )
          
        
      
    
  
  <
  
    V
    th
  
  <
  0




, is used.
Next, an overall configuration of the electrostatic detecting device according to the present invention is described with reference to FIG. 6. The electrostatic capacitance detection device, which reads surface contours of an object, is formed of M (M is an integer one or more) individual power supply lines and N (N is an integer one or more) individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on the crossing points of the individual power supply lines and the individual output lines. Each of the electrostatic capacitance detection elements is formed of a capacitance detecting electrode, a capacitance detecting dielectric layer, a reference capacitor and a signal amplification element, and detects an electrostatic capacitance, which changes according to the distance with the object. Because the electrostatic capacitance detection elements are arranged in a matrix of M rows×N columns, each of the columns and the rows has to be sequentially scanned and each of the M×N electrostatic capacitance detection elements has to be selected in a proper order in order to read surface contours. An output signal selecting circuit determines in what order detected signals are read out from each of the electrostatic capacitance detection elements. The output signal selecting circuit is formed of a common output line and a path gate for output signal, and selects an individual output line from N individual output lines for outputting an output signal. The output signal selecting circuit operates using a clock signal supplied from a clock generator on the X side.
A circuit diagram of the clock generator is shown in FIG. 7. In order that the output signal selecting circuit selects an output signal to be outputted, the output signal selecting circuit preferably is formed of a shift register, a NAND gate and a buffer (FIG. 9). The shift register is configured by coupling a plurality of basic stages in series, whereas each of the basic stages is a series circuit of a flip-flop, formed of a clocked inverter and an inverter, and a clocked inverter. The outputs from the adjacent basic stages become the inputs to the NAND gate, and an output of the NAND gate is used as an output selecting signal after reverse-amplifying with the buffer. The output selecting signal is outputted to an output line for output selection, and controls an operation of the path gate for output signal (FIG. 10).
The signal amplification element in each of the electrostatic capacitance detection elements can be formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer. The path gate for output signal is formed of a MIS type thin film semiconductor device for output signal path gate, including a gate electrode, a gate insulating layer and a semiconductor layer. In the present invention, the source region of the MIS type thin film semiconductor device for signal amplification is connected to each of the individual output lines, the drain region of the MIS type thin film semiconductor device for signal amplification element is connected to each of the individual power supply lines and the reference capacitor first electrode, and the gate electrode of the MIS type thin film semiconductor device for signal amplification element is connected to the capacitance detecting electrode and the reference capacitor second electrode. (In FIG. 10, the source region, the drain region and the gate electrode of the MIS type thin film semiconductor device are indicated by S, D and G, respectively.) Thus, each of the individual power supply lines and the individual output lines are mutually coupled via the channel forming region, which responds to an electric charge Q detected by the capacitance detecting electrode.
In the invention, the source region of the MIS type thin film semiconductor device for output signal path gate is connected to the common output line, the drain region of the MIS type thin film semiconductor device for output signal path gate is connected to each of the individual output lines, and the gate electrode of the MIS type thin film semiconductor device for output signal path gate is connected to the output line for output selection, which supplies a signal for selecting what individual output line from the N individual output lines (FIG. 10). As described above, each of the output lines for output selection may be coupled to each of the output stages (reverse-amplified output of the NAND gate, which received outputs from the adjacent basic stages) of the shift register for output signal (in case of FIG. 10), or may be coupled each of the output stages of a decoder for output signal in place of the shift register for output signal. The shift register for output signal sequentially supplies the selection signals, which are transferred to the N output stages. Furthermore, the decoder for output signal selects a certain output stage from N output stages depending on the input signal to the decoder. Thus, the selection signal is sequentially inputted to the N path gates for output signal, as required, as a result, N individual output lines are electrically conducted to the common output line sequentially.
The power supply selecting circuit selects a certain individual power supply line from M individual power supply lines, and supplies power to the selected individual line. Whether each of the individual power supply lines can be selected or not depend on the presence or the absence of the power supply (FIG. 6). The power supply selecting circuit uses a clock signal supplied by a clock generator on the Y side. A circuit diagram of the clock generator is shown in FIG. 7. In order that the power supply selecting circuit selects a certain individual power supply line, the power supply selecting circuit preferably is formed of a shift register, a NAND gate and an inverter (FIG. 8). The shift register is configured by coupling a plurality of basic stages in series, whereas the basic stage is a series circuit of a flip-flop, formed of a clocked inverter and an inverter, and a clocked inverter. The outputs from the adjacent basic stages become the inputs to the NAND gate, and an output of the NAND gate is used as the power supply selecting signal after reverse-amplifying with the inverter. The power supply selecting signal is outputted to the each of the individual power supply lines. When the certain individual power supply line is selected in this way, the selected individual power supply line is conducted to the power supply Vdd. On the other hand, unselected individual power supply lines have a ground potential (Vss).
The power selection circuit may be coupled to each of the output stages (reverse-amplified output of the NAND gate, which received outputs from the adjacent basic stages) of the shift register, or may be coupled to each of the output stages of the decoder for power supply selection in place of the shift register shown in FIG. 8. The shift register for power supply selection sequentially supplies the selection signals, which are transferred to the M output stages. Furthermore, the decoder for power supply selection selects a certain output stage from M output stages depending on the input signal to the decoder. Thus, M individual power supply lines are conducted to the power supply (Vdd) sequentially or as required.
In order that the electrostatic capacitance detection device functions in this configuration, the individual output lines and the common output line are wired by the first wiring, the individual power supply lines and the output lines for output selection are wired by the second wiring, and the capacitance detecting electrode are wired by the third wiring. And the first, second, and third wirings have to be electrically insulated via the insulating layers. This configuration eliminates redundant wirings, thereby minimizes the parasitic capacitance generated between wirings, and detecting a small amount of electrostatic capacitance with high sensitivity.
Such an electrostatic capacitance detection element can be formed on a plastic substrate by using the above-described SUFTLA technology. A fingerprint sensor on a plastic substrate using the single crystal silicon technology is lack of practicability because it cracks in short period, and has an insufficient size. On the other hand, the electrostatic capacitance detection element on a plastic substrate according to the present invention can be used as a fingerprint sensor on a plastic substrate because there is no concern that it cracks even when the area is large enough to cover a finger on the plastic substrate. Specifically, the present invention realizes a smart card with a function of the personal authentication. The smart card with a function of the personal authentication can be used for a cash card (bank card), a credit card and an identification card (ID card), and remarkably improves security level for these cards, and has an excellent function of protecting the personal fingerprint information without leaking out of the card.
An electrostatic capacitance detection device, formed of a thin film semiconductor device, is manufactured on a glass substrate, and the electrostatic capacitance detection device is transferred onto a plastic substrate by using the SUFTLA technology, and then the electrostatic capacitance detection device is manufactured on the plastic substrate. The electrostatic capacitance detection device is formed of electrostatic capacitance detection elements, arranged in a matrix of 300 columns×300 rows. The matrix is a square of 20.32 mm in each side.
The substrate is made of polyethersulfone (PES) with a thickness of 400 μm. Each of the MIS type thin film semiconductor device for signal amplification, the MIS type thin film semiconductor device for output signal path gate, the MIS type thin film semiconductor device forming the selection circuit for output signal, the MIS type thin film semiconductor device forming the power supply selecting circuit is made of a thin layer transistor. Except for the MIS type thin film semiconductor device for signal amplification, the each thin layer transistor has a same cross-sectional structure, and an NMOS transistor is formed of a so-called lightly doped drain (LDD) structure thin layer transistor, and a PMOS transistor is formed the thin layer transistor of a self-aligned structure. The thin layer transistor forming the MIS type thin film semiconductor device for signal amplification is of a top gate type as shown in FIG. 4, whereas the source electrode side is of a self-aligned structure (the gate electrode end and the source region end are substantially matched), and the drain electrode side is of a non-self aligned structure (the gate electrode and the drain region have an overlapped portion). Because the drain electrode side is of the non-aligned structure, this portion becomes a reference capacitor. In other words, the signal amplification element and the reference capacitor are integrally formed.
The thin film semiconductor device can be made in a low temperature process, in which the maximum temperature is 425° C. The semiconductor layer is a polycrystal silicon thin layer obtained by the laser crystallizing method, having a thickness of 59 nm. And, the gate insulating layer is a silicon oxide layer having a thickness of 45 nm formed by the chemical vapor deposition method (CVD method), and the gate electrode is made of tantalum thin layer having a thickness of 400 nm. The dielectric constant of the silicon oxide layer forming the gate insulating layer is determined as approximately 3.9 by the CV measurement. The first interlayer insulating layer and the second interlayer insulating layer can be silicon oxide layer formed by the CVD method using tetraethylorthosilicate (TEOS: Si (OCH2CH3)4) and oxygen as materials. It is preferable that the first interlayer insulating layer is approximately 20% or more thicker than the gate electrode (400 nm for the embodiment), and thinner than the second interlayer insulating layer. This is because the gate electrodes can be securely covered and a short-circuit between the gate electrode and the first wiring or the second wiring can be prevented, and at the same time, the second interlayer insulating layer can be thickened. In the embodiment, the first interlayer insulating layer has a thickness of 500 nm.
The third interlayer insulating layer insulates the second wiring and the capacitance detecting electrode and prevents a short-circuit. The first wiring and the capacitance detecting electrode are insulated by the second interlayer insulating layer and the third insulating layer. Therefore, in order to minimize the parasitic capacitance generated between the first wiring and the capacitance detecting electrode, and to realize the electrostatic capacitance detection device with high sensitivity, it is preferable that the dielectric constant of the second interlayer insulating layer and the third interlayer insulating layer are as small as possible and their thickness are as thick as possible. However, when the total thickness of the silicon oxide deposited by the CVD method exceeds approximately 2 μm, the silicon oxide layer may be cracked and the yield may be lowered. Accordingly, a total thickness of the first interlayer insulating layer, the second interlayer insulating layer and the third interlayer insulating layer is set to approximately 2 μm or less. This increases the productivity of the electrostatic capacitance detection device.
As described above, because the second interlayer insulating layer and the third interlayer insulating layer are preferably thicker, they are made thicker than the first interlayer insulating layer. Ideally, the first interlayer insulating layer is approximately 20% or more thicker than the gate electrode, the second interlayer insulating layer and the third interlayer layer are thicker than the first interlayer insulating layer, and the total thickness of the first interlayer insulating layer, the second interlayer insulating layer the third interlayer layer is approximately 2 μm or less. In the embodiment, the second interlayer insulating layer has a thickness of 1 μm. The first wiring and the second wiring are made of aluminum having a thickness of 500 nm, and a width of the wiring is 5 μm. The common output line and the individual output lines are formed by the first wiring, and the individual power supply lines, the output lines for output selection, and the capacitance detecting electrode is formed by the second wiring. The gap between each of the individual power supply lines and the capacitance detecting electrode is 5 μm, and the gap between each of the individual output lines and the capacitance detecting electrode is also 5 μm.
In the embodiment, the pitch of the matrix forming the electrostatic capacitance detection device is 66.7 μm, and the resolution is set to 381 dpi (dots per inch). Accordingly, the capacitance detecting electrode has a size of 55.0 μm×55.0 μm. The capacitance detecting dielectric layer is formed by a silicon nitride layer having a thickness of 350 nm. The dielectric constant of the silicon nitride layer is approximately 7.5 by the CV measurement, therefore, the element capacitance CD becomes approximately 574 fF (femtoFarad). When the electrostatic capacitance detection device is supposed to be a fingerprint sensor, the capacitance CA of the object is calculated to be 0.54 fF when a valley of a fingerprint is above the surface of the electrostatic capacitance detection device because the indentation of the fingerprint is approximately 50 μm. On the other hand, the electrode length of the MIS type thin film semiconductor device for signal amplification is set to 7 μm, in which a length of the reference capacitor part (L1) is 4.5 μm, and a length of the transistor part (length of the channel forming L2) is 2.5 μm. Because a width of the gate electrode is 10 μm, a summation of the transistor capacitance CT and the capacitance CR of the reference capacitor becomes approximately 53.7 fF. Thus, the electrostatic capacitance detection element in the embodiment satisfies a relation of

CD>10×(CR+CT)>100×CA.

Accordingly, when the power supply voltage Vdd is set to 3.3 V, the VGT applied on the gate electrode of the MIS type thin film semiconductor device for signal amplification becomes 0.16 V when a ridge of a fingerprint contacts the surface of the electrostatic capacitance detection device, and the voltage VGV applied on the gate electrode becomes 3.22 V when a valley of a fingerprint is above the surface of the electrostatic capacitance detection device.
FIG. 11 shows a transfer characteristic of the MIS type thin film semiconductor device used in the embodiment. The shift register for output signal is of a CMOS structure, and each of the MIS type thin film semiconductor device for signal amplification and the MIS type thin film semiconductor device for output signal path gate is formed by an NMOS transistor. The minimum gate voltage Vmin of the MIS type thin film semiconductor device for signal amplification is 0.1 V, which does not satisfy a relation of

0<0.1×Vdd<Vmin,

however, the drain current is made smaller than 1 pA (10−12 A) with VGT=0.16, thereby, detecting the ridge of a fingerprint with ease. On the other hand, the threshold voltage Vth is 1.47 V, which satisfies a relation of

0<Vth<0.91×Vdd=3.00 V.

As a result, when a ridge of a fingerprint contacts the surface of the electrostatic capacitance detection device, the current value outputted from the signal amplification element becomes 5.6×10−13 A, which is significantly small. On the other hand, when a valley of a fingerprint is above the surface, a large current of 2.4×10−5 A is outputted from the signal amplification element, thereby, the indentation information such as a fingerprint can be detected with high precision.
While the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, preferred embodiments of the invention as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the spirit and scope of the invention.

## Claims

1. An electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to a distance with the object, comprising:
M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on crossing points of the individual power supply lines and the individual output lines,
each of the electrostatic capacitance detection elements being formed of a signal detection element and a signal amplification element,
the signal detection element being formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor,
the reference capacitor being formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode, and
the signal amplification element being formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer,
using an area of the reference capacitor electrode of SR (μm2), a gate electrode area of the MIS type thin film semiconductor device for signal amplification of ST (μm2), a thickness of the reference capacitor dielectric layer of tR (μm), a dielectric constant of the reference capacitor dielectric layer of ∈R, a thickness of the gate insulating layer of tox (μm), and a dielectric constant of the gate insulating layer of ∈ox, a capacitance CR (reference capacitor capacitance) of the reference capacitor and a transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification are defined as


CR=∈0·∈R·SR/tR,



CT=∈0·∈ox·ST/tox


where ∈0 is permittivity in vacuum, respectively; and
using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), and a dielectric constant of the capacitance detecting dielectric layer of ∈D, an element capacitance CD of the signal detection element is defined as


CD=∈0·∈D·SD/tD



where ∈0 is permittivity in vacuum, and
the element capacitance CD being sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT.

2. An electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to a distance with the object, comprising:
M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on crossing points of the individual power supply lines and the individual output lines; and
a drain region of the MIS type thin film semiconductor device for signal amplification being electrically coupled to the individual power supply lines and the reference capacitor first electrode, and a gate electrode of the MIS type thin film semiconductor device for signal amplification being coupled to the capacitance detecting electrode and the reference capacitor second electrode,
each of the electrostatic capacitance detection elements being formed of a signal detection element and a signal amplification element,
the signal detection element being formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor,
the reference capacitor being formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode,
the signal amplification element being formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer,
the capacitance detecting dielectric layer being located on an uppermost surface of the electrostatic capacitance detection device,
the object being apart from the capacitance detecting dielectric layer with an object distance of tA without contacting, a capacitance CA of the object being defined as


CA=∈0·∈A·SD/tA


using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of the capacitance detecting electrode of SD, and
CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, being sufficiently larger than the capacitance CA of the object.

3. An electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to a distance with the object, comprising:
M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on crossing points of the individual power supply lines and the individual output lines,
each of the electrostatic capacitance detection elements being formed of a signal detection element and a signal amplification element,
the signal detection element being formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor,
the reference capacitor being formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode, and
the signal amplification element being formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer,
using an area of the reference capacitor electrode of SR (μm2), a gate electrode area of the MIS type thin film semiconductor device for signal amplification of ST (μm2), a thickness of the reference capacitor dielectric layer of tR (μm), a dielectric constant of the reference capacitor dielectric layer of ∈R, a thickness of the gate insulating layer of tox (μm), and a dielectric constant of the gate insulating layer of ∈ox, a capacitance CR of the reference capacitor and a transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification are defined as


CR=∈0·∈R·SR/tR,



CT=∈0·∈ox·ST/tox


where ∈0 is the permittivity in vacuum, respectively; and
using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), and a dielectric constant of the capacitance detecting dielectric layer of ∈D, an element capacitance CD of the signal detection element is defined as


CD=∈0·∈D·SD/tD


where ∈0 is the permittivity in vacuum; and
the element capacitance CD being sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT; and
when the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting, the capacitance CA of the object is defined as


CA=∈0·∈A·SD/tA



using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of the capacitance detecting electrode SD; and
CR+CT, a summation of the capacitance CR the reference capacitor and the transistor capacitance CT, being sufficiently larger than capacitance CA of the object.

4. An electrostatic capacitance detection device for reading surface contours of an object by detecting an electrostatic capacitance, which changes according to the distance with the object, comprising:
M individual power supply lines and N individual output lines, arranged in a matrix of M rows×N columns, and electrostatic capacitance detection elements provided on crossing points of the individual power supply lines and the individual output lines;
each of the electrostatic capacitance detection elements being formed of a signal detection element and a signal amplification element;
the signal detection element being formed of a capacitance detecting electrode, a capacitance detecting dielectric layer and a reference capacitor;
the reference capacitor being formed of a reference capacitor first electrode, a reference capacitor dielectric layer and a reference capacitor second electrode;
the signal amplification element being formed of a MIS type thin film semiconductor device for signal amplification, including a gate electrode, a gate insulating layer and a semiconductor layer; and
a part of a drain region and a part of a gate region of the MIS type thin film semiconductor device for signal amplification forming an overlapped portion via the gate insulating layer, and an overlapped portion forms the reference capacitor.

5. The electrostatic capacitance detection device according to claim 4, using a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer drain region, L1 (μm), a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer channel forming region, L2 (μm), a width of the gate electrode of W (μm), a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, a capacitance CR of the reference capacitor and a transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification are defined as


CR=∈0·∈ox·L1·W/tox,



CT=∈0·∈ox·L2·W/tox

where ∈0 is the permittivity in vacuum, respectively; and
using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), and a dielectric constant of the capacitance detecting dielectric layer of ∈D, an element capacitance CD of the signal detection element is defined as


CD=∈0·∈D·SD/tD



where ∈0 is the permittivity in vacuum; and
the element capacitance CD being sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT.

6. The electrostatic capacitance detection device according to claim 4, the object being apart from the capacitance detecting dielectric layer with an object distance of tA without contacting, a capacitance CA of the object is defined as


CA=∈0·∈A·SD/tA

using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of capacitance detecting electrode of SD; and
CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, is sufficiently larger than the capacitance CA of the object.

7. The electrostatic capacitance detection device according to claim 4, the capacitance detecting dielectric layer being located on an uppermost surface of the electrostatic capacitance detection device, using a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer drain region, L1 (μm), a gate electrode length, which is an overlapped portion of the gate electrode of the MIS type thin film semiconductor device for signal amplification and the semiconductor layer channel forming region, L2 (μm), a width of the gate electrode of W (μm), a thickness of the gate insulating layer of tox (μm), a dielectric constant of the gate insulating layer of ∈ox, a capacitance CR of the reference capacitor and a transistor capacitance CT of the MIS type thin film semiconductor device for signal amplification are defined as


CR=∈0·∈ox·L1·W/tox,



CT=∈0·∈ox·L2·W/tox

where ∈0 is the permittivity in vacuum, respectively; and
using an area of the capacitance detecting electrode of SD (μm2), a thickness of the capacitance detecting dielectric layer of tD (μm), and a dielectric constant of the capacitance detecting dielectric layer of ∈D, an element capacitance CD of the signal detection element is defined as


CD=∈0·∈D·S/tD



where ∈0 is the permittivity in vacuum; and
the element capacitance CD being sufficiently larger than CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT; and
when the object is apart from the capacitance detecting dielectric layer with an object distance of tA without contacting, a capacitance CA of the object is defined as


CA=∈0·∈A·SD/tA



using the permittivity in vacuum of ∈0, a dielectric constant of air of ∈A, and an area of the capacitance detecting electrode of SD; and CR+CT, a summation of the capacitance CR of the reference capacitor and the transistor capacitance CT, being sufficiently larger than the capacitance CA of the object.