<PAGE>   1
                                                                   EXHIBIT 10.14

*CERTAIN INFORMATION WITHIN THIS EXHIBIT HAS BEEN OMITTED AND THE NON-PUBLIC
INFORMATION HAS BEEN FILED SEPARATELY WITH THE SEC. CONFIDENTIAL TREATMENT HAS
BEEN REQUESTED WITH RESPECT TO THE OMITTED PORTIONS.


                JOINT MARKETING AND TECHNICAL SUPPORT AGREEMENT

This agreement is entered into and effective November 14, 1997, (the "Effective
Date") by and between VIRAGE LOGIC, with a place of business at 1641A South Main
Street Milpitas CA, 95025, USA ("VIRAGE LOGIC"), and Chartered Semiconductor
Manufacturing Ltd., with a place of business at 60 Woodlands Industrial Park D,
Street 2, Singapore 738406 ("CHARTERED").

Whereas, the parties hereto desire to work together to develop and promote
customer benefits of the joint use of CHARTERED foundry and VIRAGE LOGIC
products and services.

Whereas, the parties hereto desire to enter into a worldwide non-exclusive
agreement that defines the technical and marketing support that each party will
provide to the other in support of mutual customers and prospects.

BACKGROUND

VIRAGE LOGIC is a full service VLSI design and ASIC Company and a leader in
ultra low power and high performance integrated circuit design. VIRAGE LOGIC
provides design and test solution to ASIC and COT customers.

CHARTERED is a dedicated foundry providing quality manufacturing service for
semiconductor companies worldwide. CHARTERED business focus is in wafer
fabrication for implementing the customer designs in silicon.

This agreement serves to clarify the strong cooperative relationship between
VIRAGE LOGIC and CHARTERED to coordinate areas of mutual interest in the future
offering and promotion of libraries and foundry service for the benefit of
mutual customers.

1. JOINT MARKETING

It is the intention of both parties to provide the greatest value to mutual
customers through the delivery of compatible and complementary products and
services. Both parties agree to start cooperation in the area of compiler, BIST,
and SRAM, potentially EEPROM and Flash in the future. In order to achieve these
ends, both parties agree to work together in the following area:

1.1     Provide the other party and mutual customers with technical, marketing,
        and sales support.

1.2     Introduce its customers to the products of the other party, when
        appropriate.

1.3     Use each other's logos in marketing literature described in this
        Agreement and upon the prior written approval of the other party.



<PAGE>   2
1.4     Issue press releases on significant achievements of this relationship.
        All formal press releases must be approved by both VIRAGE LOGIC and
        CHARTERED before they are issued. Both parties may comment on this
        relationship to customers, third party and the press without prior
        approval by the other party.

1.5     Promote each other's services in the COT market place. CHARTERED would
        promote VIRAGE LOGIC libraries as having been manufactured at CHARTERED
        and VIRAGE LOGIC would promote CHARTERED as foundry manufacturer meeting
        VIRAGE LOGIC standard.

2.      JOINT TEST CHIP AND SILICON VERIFICATION PROGRAM

CHARTERED and VIRAGE LOGIC will share the costs of model extraction and spice to
silicon correlation using the CHARTERED test chip or the VIRAGE LOGIC test chip.
The CHARTERED test chip would include a BSIM extract module for DC analysis, and
a performance module for AC characterization.

2.1     CHARTERED will be responsible for providing CHARTERED's test chip layout
        and test plans to VIRAGE LOGIC. VIRAGE LOGIC is free to adapt CHARTERED
        test chip, or design a new test chip at VIRAGE LOGIC's expense that best
        meet VIRAGE LOGIC's needs in silicon verifications.

2.2     For each new process technology, VIRAGE LOGIC can take advantage of
        riding on CHARTERED's test chip for such technology provided that VIRAGE
        LOGIC is able to tape-out before CHARTERED's pre-determined cut-off
        date. In the event VIRAGE LOGIC is unable to tape out by such date,
        VIRAGE LOGIC shall be responsible for the costs of mask and CHARTERED
        shall provide the silicon. If VIRAGE LOGIC is able to tape out before
        such date, CHARTERED shall include VIRAGE LOGIC's test chip of a
        reasonable size on CHARTERED's test chip without incurring masks or
        silicon costs to VIRAGE LOGIC. VIRAGE LOGIC hereby acknowledges that
        CHARTERED may make available such test chip to CHARTERED's customers and
        technology partners upon their request.

2.3     VIRAGE LOGIC will be responsible for the engineering and test costs for
        model extraction, performance characterization, and Spice to silicon
        correlation. All resulting records, reports and data are shared between
        VIRAGE LOGIC and CHARTERED.

2.4     CHARTERED will be responsible for running internal CHARTERED process
        monitoring modules on as needed basis to assure that the CHARTERED
        process is meeting CHARTERED specifications. If there are material
        changes to the process that warrant new model extraction and/or silicon
        verification, then the above model extraction and correlation sequence
        will, if agreed by both parties, be repeated as described above.



                                       2
<PAGE>   3
3.      CHARTERED RESPONSIBILITIES

To ensure the highest probability of success for our mutual customers, CHARTERED
hereby accepts the following responsibilities:

3.1     CHARTERED will provide VIRAGE LOGIC with the most updated CHARTERED
        Design Rules, Spice Models, Parasitic Extraction tables, and Biasing
        tables for production processes on the same schedule that it provides
        for its best customers based on CHARTERED test chip. CHARTERED reserves
        the right to make changes as needed but will consider the ramifications
        to VIRAGE LOGIC of such a change. It will be VIRAGE LOGIC discretion to
        decide if a re-generation of model and/or silicon verification at VIRAGE
        LOGIC's expense, is needed.

3.2     CHARTERED will support VIRAGE LOGIC through designated technical
        contacts, usually CHARTERED account managers, to facilitate the orderly
        flow of customer design data for mask making and wafer manufacturing.

3.3     CHARTERED will equip its sales channel with standard approved VIRAGE
        LOGIC sales and marketing collateral for promoting VIRAGE LOGIC offers
        to mutual customers and prospects.

3.4     CHARTERED will develop a press release which outlines the basic terms of
        this agreement. Final approval of this press release will be with VIRAGE
        LOGIC.

3.5     CHARTERED will support VIRAGE LOGIC's customers in the same manner as
        CHARTERED supports its customers in similar locations.

4.      VIRAGE LOGIC RESPONSIBILITIES

To ensure the highest probability of success for our mutual customers, VIRAGE
LOGIC hereby accepts the following responsibilities:

4.1     VIRAGE LOGIC will develop physical and logical design libraries based on
        CHARTERED rules. Based on market demand, CHARTERED will advise and
        VIRAGE LOGIC will choose which libraries to build using these rules.
        VIRAGE LOGIC will make all reasonable efforts to keep these libraries
        current with the CHARTERED Design Rules, and support mutual customers
        with such libraries.

4.2     VIRAGE LOGIC will equip its sales channel with approved CHARTERED sales
        and marketing collateral for promoting CHARTERED offers to mutual
        customers and prospects.



                                       3
<PAGE>   4
5.      CONTACTS AND REVIEWS

5.1     Quarterly review meeting will be held at a mutually agreed time and
        venue between CHARTERED and VIRAGE LOGIC to address any concerns or
        issues affecting mutual customers, and to assess the effectiveness of
        the sales effort and co-operative relationship.

5.2     VIRAGE LOGIC and CHARTERED Contacts

               VIRAGE LOGIC                 CHARTERED

        Engineering   Alex Shubat           Dong Khong / Bob Kwong

        Sales         Adam Kablanian

        Marketing     Adam Kablanian        S.Y. Tan - Stahel

6.      TERMS OF AGREEMENT AND CONFIDENTIALITY

6.1     This agreement shall remain in force for a period of three years from
        the Effective Date.

6.2     Either party hereto may terminate this Agreement without cause or reason
        by 90 days prior written notice to the other party during the term of
        this Agreement provided that the terminating party will fully cooperate
        with the other party to enable the customers to complete the tasks that
        were started prior to termination.

6.3     Both parties hereto agree to treat all information, materials, and
        documents, except for characterization data, provided by the other party
        in accordance with Non-Disclosure Agreement executed separately by both
        parties.

7.      TRADEMARKS AND USE OF NAMES

7.1     The use of the name or products of the other party or indication of this
        Agreement in the marketing and/or publicity materials of either party
        shall be subject to written approval of the other party, and such
        approval should not be unreasonably withheld or delayed. The requirement
        of written approval shall not apply to accurate factual listings of
        products publicly offered or supported by either party.

8.      GENERAL PROVISIONS

8.1     Neither party may assign its rights or obligations, or assign or
        sublicense any licenses granted under this Agreement without the prior
        written consent of the other party.



                                       4
<PAGE>   5
8.2     Neither party is authorized to act for or on behalf of the other party
        under this Agreement. Each party is an independent contractor. No
        commitments to customers on VIRAGE LOGIC library pricing, availability,
        routed density, quality, or reliability may be made by CHARTERED. No
        commitments to customers on CHARTERED wafer pricing wafer capacity,
        delivery dates, quality, or yield may be made by VIRAGE LOGIC.

8.3     The validity, performance and construction of this Agreement shall be
        governed by the Laws of the State of California.

8.4     If either party is challenged by a third party to be infringing the
        intellectual property rights of such third party with respect to the
        material or documents jointly developed or consented to by both parties,
        then the other party shall provide all reasonable assistance to the
        challenged party in defending against those claims. Such reasonable
        assistance shall include providing relevant documents, materials, and
        consulting.

8.5     No failure or delay by either party to enforce or take advantage of any
        provision or right under this Agreement shall constitute a subsequent
        waiver of that provision or right, nor shall it be deemed to be a waiver
        of any of the other terms and conditions of this Agreement.

8.6     In the event that any provision of this Agreement is prohibited by any
        law governing its construction, performance and enforcement, such
        provision shall be ineffective to the extent of such prohibition without
        invalidating thereby any of the remaining provisions of the Agreement.
        The captions of sections herein are intended for convenience only, and
        the same shall not be interpretive of the content of such section.

8.7     All notices and communications to be given under this Agreement shall be
        in writing and shall be deemed delivered upon hand delivery, upon
        acknowledged facsimile communication, or seven (7) days after deposit in
        the mail of the home country of the party, postage prepaid, by
        certified, registered or first class mail, addressed to the parties at
        the addresses set forth above.

9.      COPYRIGHT, PATENT, AND INDEMNITY

9.1     Indemnification by VIRAGE LOGIC

        VIRAGE LOGIC shall indemnify and defend (including attorney fees)
        CHARTERED and hold it harmless against any and all damages awarded by a
        court or payable in settlement (whether or not a legal proceeding is
        commenced) resulting from a claim against CHARTERED based upon an actual
        or alleged infringement of a third party's patent, mask work right,
        copyright trade secrets or other intellectual property right arising
        from CHARTERED's use of design



                                       5
<PAGE>   6
        modules, spice models, or testchips provided by VIRAGE LOGIC under this
        Agreement.

9.2     Indemnification by CHARTERED

        CHARTERED shall indemnify and defend (including attorney fees) VIRAGE
        LOGIC and hold it harmless against any and all damages awarded by a
        court or payable in settlement (whether or not a legal proceeding is
        commenced) resulting from a claim against VIRAGE LOGIC based upon an
        actual or alleged infringement of a third party's patent, mask work
        right, copyright, trade secrets or other intellectual property right
        arising from VIRAGE LOGIC's use of CHARTERED's design rules, Spice
        models, testchips, material, techniques, or process provided by
        CHARTERED under this Agreement.

9.3     Procedure

Neither party shall have any liability under this section 9 unless:

        (a)    the indemnifying party is promptly notified in writing of each
               notice and communication regarding such claim and given (at the
               indemnifying party's expense) the authority, information, and
               assistance necessary to present a defense; and

        (b)    The indemnifying party is offered sole control of the defense of
               such claim and of all negotiations for its settlement or
               compromise. The indemnified party may, at its expense,
               participate in the defense of such claim and in all negotiations
               for its settlement or compromise. If the indemnifying party does
               not assume control of the defense promptly after notice of the
               claim it shall be bound by the results obtained by the
               indemnified party with respect to such claim.

9.4     In no event shall either party's liability to each other arising out of
        sections 9.1 and 9.2, or out of any other provision in this Agreement
        exceed an aggregate of United States Dollars One Hundred Thousand
        (US$100,000).

9.5     Disclaimer

        THE FOREGOING STATES EACH PARTY'S ENTIRE LIABILITY AND OBLIGATION
        (EXPRESS, IMPLIED, STATUTORY OR OTHERWISE) WITH RESPECT TO INTELLECTUAL
        PROPERTY INFRINGEMENT OR CLAIMS THEREFOR REGARDING ANY OF THE
        INFORMATION EXCHANGED PURSUANT TO THIS AGREEMENT.

Acknowledged and agreed:

For VIRAGE LOGIC     /s/            For CHARTERED     /s/
                  -----------                    --------------



                                       6
<PAGE>   7
Title          President                    Title         SVP
               ---------------------                      ---

Date           10/27/97                     Date          11/4/97
               ---------------------                      -------



                                       7
<PAGE>   8
        ADDENDUM NO. 1 TO JOINT MARKETING AND TECHNICAL SUPPORT AGREEMENT

THIS ADDENDUM NO. 1, TOGETHER WITH EXHIBIT A is entered into and effective on
___________ 1999 (the "Effective Date") by and between Virage Logic Corporation
("Virage Logic"), a California corporation having its principal place of
business 46824 Lakeview Blvd., Fremont, CA 94538, USA and Chartered
Semiconductor Manufacturing Ltd. ("Chartered"), a Singapore company having, its
principal place of business at 60 Woodlands Industrial Park D, Street 2,
Singapore 738406, and is supplemental to a Joint Marketing and Technical Support
Agreement dated 4 November 1997 (the "Agreement").

WHEREAS:

In response to the market demand, the Parties have discussed and agreed to
revise the business model on which the Joint Marketing and Technical Support
Agreement was based. In accordance with those discussions, the Parties now
desire to incorporate the additional provisions to the Agreement.

IT IS AGREED AS FOLLOWS:

1. LIBRARIES

The terms of this Addendum No. 1 are only applicable to the following Virage
Logic Memory Compilers libraries that Virage Logic has developed for Chartered's
0.35um and 0.25um processes (the "Chartered/Virage Logic 0.35um/0.25um memory
compilers") pursuant to the Agreement:

-  0.35um PROCESS:

(i)     1 port High density compiler

-  0.25um PROCESS:

(i)     1 port High Density compiler (HD-Family)

(ii)    2 port High density compiler (HD-Family)

(iii)   1 port Register file

(iv)    2 port Register file

2. PRICING OPTION AND PAYMENTS

(a) Virage Logic agrees to grant twenty (20) compiler tokens to Chartered. The
compiler tokens may be exercised by Chartered to require Virage Logic to license
to Chartered customers any Chartered/Virage Logic 0.35um/0.25um memory compilers
on the payment by Chartered or customer of **% of Virage Logic's COT list prices
set out in Exhibit A together with Virage Logic's end-user maintenance fees
which shall not

<PAGE>   9
exceed 12% of the relevant list price per annum per site (all references to "$"
in this Addendum No. 1 shall mean United States dollars).

(b) In consideration of the receipt of the twenty (20) compiler tokens referred
to in Clause 2(a), Chartered agrees to pay the following royalties to Virage
Logic:

(i)     Subject to Clause 2(b)(vii) below, for each revenue bearing wafer
        manufactured at Chartered that incorporates any Chartered/Virage Logic
        0.35um/0.25um memory compilers ("Wafer"), Chartered shall pay to Virage
        Logic the following royalties, up to a maximum of **** per process ****
        Technology:

        (aa) **% of the Net Selling Price of each Wafer up to ****; and
             thereafter,

        (bb) **% of the Net Selling Price of each Wafer up to ****.

               In this Agreement, "Net Selling Price" shall mean the gross
               consideration (whether in cash or kind) received by Chartered
               from sales of Wafers less (i) normal and customary rebates, and
               cash and trade discounts actually taken, (ii) sales, use and/or
               other excise taxes or duties actually paid, (iii) the cost of any
               packages and packaging, (iv) insurance costs and outbound
               transportation charges prepaid or allowed, (v) import and/or
               export duties actually paid, and (vi) amounts allowed or credited
               due to returns. In addition, when a Wafer is sold in a packaged
               or tested form, the gross consideration (whether in cash or kind)
               received by Chartered for the purposes of calculating the Net
               Selling Price shall be less the costs of packaging and testing.

(ii)    The total amount of royalties that Chartered shall pay to Virage Logic
        pursuant to Clause 2(b)(i) above, over the life of the design using any
        Chartered/Virage Logic 0.35um/0.25um memory compiler shall be limited to
        **** per process technology and Chartered shall not be required to pay
        Virage Logic any royalties in excess of **** per process technology.

(iii)   Notwithstanding Clause 2(b)(i) above, in the event that a Wafer
        incorporates any libraries or other foundation IPs (i.e. Standard cells,
        I/0 and memories), of other vendors in addition to any Chartered/Virage
        Logic 0.35um/0.25um memory compilers. Virage Logic agrees that the
        percentages in Clause 2(b)(i)(aa) and 2(b)(i)(bb) above shall be reduced
        proportionately in accordance with the total number of vendors whose
        libraries and/or foundation IPs (i.e. standard cells, I/O and memories)
        are incorporated into the same wafer.



                                       2
<PAGE>   10
        By way of an example, if a Wafer incorporates any Chartered/Virage Logic
        0.35um/0.25um memory compiler and libraries or other foundation IPs
        (i.e. standard cells, I/O and memories), of two (2) other vendors, the
        percentages set out in Clauses 2(b)(i)(aa) and 2(b)(i)(bb) above shall
        each be reduced by two thirds.

(iv)    All royalty payments to be made by Chartered pursuant to Clause 2(b)(i)
        above shall be computed according to the actual amounts received by
        Chartered from customers as payment for the purchase of Wafers, and
        shall be paid by Chartered on a quarterly basis.

(v)     Payments to Virage Logic hereunder shall be made without deduction or
        withholding except that Chartered shall have the right to withhold from
        payments to Virage Logic any taxes that Chartered is required to
        withhold under any applicable law. Chartered shall provide Virage Logic
        with a certificate from the applicable tax authorities or other evidence
        reasonably required by Virage Logic to evidence such tax payment.

(vi)    Chartered shall keep for a period of two (2) years after each royalty
        payment hereunder records as may be necessary to determine and verify
        the royalty payments hereunder. Virage Logic is entitled at Virago
        Logic's cost to have such records of Chartered inspected by independent
        public accountant firms acceptable to Chartered, upon reasonable notice
        and not more than once a year.

(vii)   The foregoing provisions in Clauses 2(b)(i) to (vii) shall only apply to
        mutual customers' designs that incorporate the Chartered/Virage Logic
        0.35um/0.25um memory compilers that are taped-out to Chartered on or
        after the Effective Date.

(viii)  Virage Logic will make available the Chartered/Virage Logic
        0.35um/0.25um memory compilers and Chartered/Virage Logic 0.35um/0.25um
        Instances (and all Virage Logic's standard EDA views) by licensing the
        same directly to customers.

(ix)    Thc merging of physical libraries for customers using the libraries will
        be done by customers. Chartered, or Chartered appointed design houses
        (Rights to access subject to business terms agreed herein, but without
        rights to sub-license).

3.      TERM AND TERMINATION

(a)     This Addendum No. 1 shall remain in force for a period of three (3)
        years from the Effective Date.

(b)     Notwithstanding the foregoing, this Addendum No. 1 shall terminate if
        the Agreement is terminated, or either party terminates this Addendum
        No. 1, without cause or reason, by 90 days' written notice of
        termination to the other party. However, notwithstanding the termination
        of this Addendum, Chartered shall



                                       3
<PAGE>   11
        continue to pay royalties under the terms of this Addendum in respect of
        Wafers manufactured and sold to customers that have licensed the
        Chartered/Virage Logic 0.35um/0.25um memory compilers during the term of
        this Addendum No. 1.

(c)     The termination of this Addendum however caused shall be without
        prejudice to any obligations or rights of either party which have
        accrued prior to such termination and shall not affect any provision of
        this Addendum which is expressly or by implication provided to come into
        effect on or to continue in affect after such termination.

4.      SAVING AND INCORPORATION

(a)     Clause 6.1 of the Agreement is hereby deleted and substituted with the
        following provision:

        "6.1 This Agreement shall remain in force for a period of three (3)
        years from the Effective Date of this Addendum No. 1".

(b)     Save as expressly varied by the terms of this Addendum No. 1, the terms
        and conditions of the Agreement shall remain with full force and effect
        in all other respects.

(c)     The Agreement and this Addendum No. 1 shall be construed as one document
        and this Addendum No. 1 shall be deemed to be part of the Agreement.

5.      GOVERNING LAW

The validity, enforceability and construction of this Addendum No. 1 shall be
governed by the Laws of the State of California.

IN WITNESS WHEREOF the parties have entered into this Addendum No. 1 as of the
date first above written:

VIRAGE LOGIC                                CHARTERED SEMICONDUCTOR
                                            MANUFACTURING LTD.

/s/ ALEX SHUBAT                             /s/  ROB BAXTER
  ----------------------------------          ----------------------------------

Name: Alex Shubat for Adam Kablanian        Name: Rob Baxter

Title: President & CEO                      Title: Senior Vice President,
                                            Business Operations



                                       4
<PAGE>   12
                                    EXHIBIT A

LIST PRICES FOR CHARTERED/VIRAGE 0.35um/0.25um MEMORY COMPILERS AS OF 31 MARCH
1999 (REF. CLOSE 2)

(All references to $ shall mean United States Dollars)

-      0.35um PROCESS:

        (i)    1 port High density compiler:       ****

-      0.25um PROCESS:

        (i)    1 port High Density compiler:       ****
        (ii)   2 port High density compiler:       ****
        (iii)  1 port Register file:               ****
        (iv)   2 port Register file:               ****

For the purpose of this Addendum No. 1. compilers will be offered regardless of
whether the customer needs one instance or the complete compiler.

Acknowledged and agreed by:

VIRAGE LOGIC:                       CHARTERED:

/s/ ALEX SHUBAT                     /s/   ROB BAXTER
   -------------------------           --------------------------------
<PAGE>   13
            ADDENDUM NO. 2 TO JOINT MARKETING AND TECHNICAL SUPPORT
                                   AGREEMENT

THIS ADDENDUM NO. 2 is entered into and effective on ___________ 1999 (the
"Effective Date") by and between Virage Logic Corporation ("Virage Logic"), a
California corporation having its principal place of business at 46824 Lakeview
Blvd. Fremont, CA 94538, USA and Chartered Semiconductor Manufacturing Ltd
("Chartered"), a Singapore company having its principal place of business at 60
Woodlands Industrial Park D, Street 2, Singapore 738406, and is supplemental to
a Joint Marketing and Technical Support Agreement dated 4 November 1997 (the
"Agreement").

WHEREAS:-

In response to the market demand, Virage Logic and Chartered have entered into
Addendum No. 1 to the Agreement dated [   ] and have further agreed to extend
their cooperation as set out in the Agreement to the development of 0.18um
memory compliers, including but not limited to SRAMs. In connection with this
further agreement, the Parties have agreed to modify and supplement the
provisions of the Agreement.

IT IS AGREED AS FOLLOWS:-

1. CHARTERED RESPONSIBILITIES

To ensure that highest probability of success for mutual customers of Chartered
and Virage Logic, Chartered hereby accepts the following responsibilities:

1.1  In connection with the marketing of Virage Logic's products and services
to mutual and prospective customers, Chartered will promote Virage Logic as a
premier SRAM provider.

1.2  To support the development of the 0.18um memory compliers by Virage Logic,
Chartered agrees to pay a development fee of United States Dollars One Hundred
Thousand (US$100,000/-). The fee shall be paid as follows:

(a)  ****-to be paid within 30 days from the Effective Date
(b)  ****-to be paid within 30 days of first test chip tape out.

1.3  In addition to the development fee referred to in Section 1.2 of this
Addendum No. 2, Chartered agrees to pay Virage Logic royalties for the use of
any Chartered/Virage Logic 0.18um memory complier by mutual customers, on the
following terms and conditions:

(a)  Royalties will be based on **% of the Net Selling Price of each
revenue-bearing Wafer manufactured by Chartered that incorporates a
Chartered/Virage Logic memory complier.


                                       1

<PAGE>   14
In this Addendum, "Net Selling Price" shall mean the gross consideration
(whether in cash or kind) received by Chartered from sales of Wafers less (i)
normal and customary rebates, and cash and trade discounts actually taken, (ii)
sales, use and/or other excise taxes or duties actually paid, (iii) the cost of
any packages and packaging, (iv) insurance costs and outbound transportation
charges prepaid or allowed, (v) import and/or export duties actually paid, and
(vi) amounts allowed or credited due to returns. In addition, when a Wafer is
sold in a packaged or tested form, the gross consideration (whether in cash or
kind) received by Chartered for the purposes of calculating the Net Selling
Price shall be less the costs of packaging and testing.

(b)  Notwithstanding 1.3(a) above, in the event that a Wafer incorporates any
libraries or other foundation IP's; i.e., standard cells, I/O's and memories of
other vendors, in addition to any Chartered/Virage Logic 0.18um memory
compilers, Virage Logic agrees that the percentages in Section 1.3(a) above
shall be reduced proportionately in accordance with the total number of vendors
whose libraries and/or IPs are incorporated into the same wafer.

By way of an example, if a Wafer incorporates any Chartered/Virage Logic 0.18um
memory compiler and libraries or other foundation IPs of two (2) other vendors,
the percentages set out in Section 1.3(a) above shall each be reduced by two
thirds.

(c)  All royalties to be paid by Chartered pursuant to Section 1.3(a) above
shall be computed according to the actual amounts received by Chartered from
mutual customers as payment for the purchase of Wafers, and shall be paid by
Chartered on a quarterly basis.

(d)  Payments to Virage Logic hereunder shall be made without deduction or
withholding, except that Chartered shall have the right to withhold from
payments to Virage Logic any taxes that Chartered is required to withhold under
any applicable law. Chartered shall provide Virage Logic with a certificate
from the applicable tax authorities or other evidence reasonably required by
Virage Logic to evidence such tax payment.

2. VIRAGE LOGIC RESPONSIBILITIES

To ensure that highest probability of success for mutual customers of Chartered
and Virage Logic, Virage Logic hereby accepts the following responsibilities:

2.1  Virage Logic will develop and deliver all 0.18um memory compilers to
Chartered. In order to facilitate the tapeout of the test chip, Virage will
deliver a test chip with the memory compilers below to Chartered for silicon
validation by 30 September 1999.

(a)  Single Port Synchronous memory compiler
(b)  Dual Port Synchronous memory compiler


                                       2


<PAGE>   15
3.  Term and Termination

(a) This Addendum No. 2 shall remain in force for a period of three (3) years
from the Effective Date.

(b) Notwithstanding the foregoing, this Addendum No. 2 shall terminate if the
Agreement is terminated or expired and not renewed, or either party terminates
this Addendum No. 2, without cause or reason, by 90 days' notice of termination
to the other party.

4.  Saving and Incorporation

(a) Section 6.1 of the Agreement is hereby deleted and substituted with the
following provision:

    "6.1 This Agreement shall remain in force for a period of three (3) years
         from the Effective Date of Addendum No. 2 to this Agreement."

(b) Save as expressly varied by the terms of this Addendum No. 2, the terms and
conditions of the Agreement shall remain with full force and effect in all
other respects.

(c) The Agreement, Addendum No. 1 to the Agreement and this Addendum No. 2
shall be construed as one document and this Addendum No. 2 shall be deemed to
be part of the Agreement.

5.  Governing Law

The validity, enforceability and construction of this Addendum No. 2 shall be
governed by the Laws of the State of California.

IN WITNESS WHEREOF the parties have entered into this Addendum No. 2 as of the
date first above written:

VIRAGE LOGIC                               CHARTERED SEMICONDUCTOR
                                           MANUFACTURING LTD.

/s/ ADAM KABLANIAN                         /s/ ROB BAXTER
-----------------------------------       -------------------------------------

NAME: Adam Kablanian                      NAME: Rob Baxter

TITLE: President & CEO                    TITLE: Senior Vice President,Business
                                                 Operations

DATE:                                     DATE:

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        ADDENDUM NO. 3 TO JOINT MARKETING AND TECHNICAL SUPPORT AGREEMENT

THIS ADDENDUM NO. 3 is entered into and effective on June 7 1999 by and between
Virage Logic Corporation ("Virage Logic"), a California corporation having its
principal place of business at 46824 Lakeview Blvd. Fremont, CA 94538, USA and
Chartered Semiconductor Manufacturing Ltd ("Chartered"), a Singapore company
having its principal place of business at 60 Woodlands Industrial Park D, Street
2, Singapore 738406, and is supplemental to a Joint Marketing and Technical
Support Agreement dated 4 November 1997 (the "Agreement") and an Addendum No. 2
to the Agreement dated 12 April 1999 (the "Addendum No. 2").

WHEREAS:-

In response to the market demand, Virage Logic and Chartered had entered into
Addendum No. 2 to modify and supplement the provisions of the Agreement. The
parties now desire to amend the term and termination provisions of Addendum No.
2 on the following terms and conditions.

IT IS AGREED AS FOLLOWS:-

1. Clause 3 of Addendum No. 2 is deleted in its entirety and replaced with the
following provision:

"3. Term and Termination

3.1 Unless otherwise terminated by the parties in accordance with Clause 3.2
hereof, this Addendum No. 2 shall remain in force for a period of three (3)
years from the Effective Date. However, notwithstanding the termination of this
Addendum No. 2, Chartered shall continue to pay royalties under the terms of
this Addendum in respect of wafers manufactured and sold to customers that have
licensed the Chartered/Virage Logic 0.18um memory compilers during the term of
this Addendum No. 2.

3.2 Notwithstanding the foregoing, this Addendum No. 2 shall terminate

        (a)    by the agreement of the Parties in writing;

        (b)    forthwith by either Party if the other commits any material
               breach of any term of this Addendum No. 2 or the Agreement and
               which in the case of a breach capable of being remedied shall not
               have been remedied within thirty (30) days of a written request
               to remedy the same.

        (c)    at the option of either Party, in any of the following events:

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               (i)    the inability of the other Party to pay its debts in the
                      normal course of business; or

               (ii)   the other Party ceasing or threatening to cease wholly or
                      substantially to carry on its business, otherwise than for
                      the purpose of a reconstruction or amalgamation without
                      insolvency; or

               (iii)  any encumbrancer taking possession of or a receiver,
                      trustee or judicial manager being appointed over the whole
                      or any substantial part of the undertaking, property or
                      assets of the other Party; or

               (iv)   the making of an order by a court of competent
                      jurisdiction or the passing of a resolution for the
                      winding-up of the other Party or any company controlling
                      the other Party, otherwise than for the purpose of a
                      reconstruction or amalgamation without insolvency.

3.3 The termination of this Addendum No. 2 pursuant to this Clause 3.2 shall
take effect immediately upon the issue of a written notice to that effect by the
Party terminating the Addendum to the other. The termination of this Addendum
No. 2 however caused shall be without prejudice to any obligations or rights of
either Party which have accrued prior to such termination and shall not affect
any provision of this Addendum No. 2 and/or any provision of the Agreement which
is expressly or by implication provided to come into effect on or to continue in
effect after such termination."

2. Term and Termination

This Addendum No. 3 shall terminate at the same time that Addendum No. 2 is
terminated or has expired and is not renewed.

3. Saving and Incorporation

(a)     Save as expressly varied by the terms of this Addendum No. 3, the
        provisions of Addendum No. 2 shall remain with full force and effect in
        all other respects.

(b)     The Agreement, Addendum No. 1 to the Agreement, Addendum No. 2 to the
        Agreement and this Addendum No. 3 shall be construed as one document and
        this Addendum No. 3 shall be deemed to be a part of the Agreement.

4.      Governing Law

The validity, enforceability and construction of this Addendum No. 3 shall be
governed by the Laws of the State of California.



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IN WITNESS WHEREOF the parties have entered into this Addendum No. 3 as of the
date first above written:

VIRAGE LOGIC                           CHARTERED SEMICONDUCTOR
                                       MANUFACTURING LTD.

/s/  ALEX SHUBAT                         /s/  ROB BAXTER
   ------------------------------        ---------------------------------
Name:    Alex Shubat                   Name: Rob Baxter

Title: VP Engineering, CTO             Title: Senior Vice President,
                                       Business Operations