agonal Bur9au of standard

Morary, N. W- B1(Jg

APR 1 91963

^&cknic&l vtote 768

TRANSISTORIZED BUILDING BLOCKS

FOR DATA INSTRUMENTATION

ROGER L. HILL

U. S. DEPARTMENT OF COMMERCE

NATIONAL BUREAU OF STANDARDS
lazfloi

THE NATIONAL BUREAU OF STANDARDS

Functions and Activities

The functions of the National Bureau of Standards arc set forth in the Act of Congress,

March 3, 1901, as amended by Congress in Public Law 619, 1950. These include the development and maintenance of the national standards of measurement and the provision of means

and methods for making measurements consistent with these standards; the determination of physical constants and properties of materials; the development of methods and instruments

for testing materials, devices, and structures; advisory services to government agencies on

scientific and technical problems; invention and development of devices to serve special needs

of the Government; and the development of standard practices, codes, and specifications. The

work includes basic and applied research, development, engineering, instrumentation, testing,

evaluation, calibration services, and various consultation and information services. Research

projects are also performed for other government agencies when the work relates to and supplements the basic program of the Bureau or when the Bureau's unique competence is required.

The scope of activities is suggested by the listing of divisions and sections on the inside of

the back cover.

Publications

The results of the Bureau's research arc published either in the Bureau's own scries of

publications or in the journals of professional and scientific societies. The Bureau publishes

three periodicals available from the Government Printing Office: The Journal of Research,

published in four separate sections, presents complete scientific and technical papers; the Technical News Bulletin presents summary and preliminary reports on work in progress; and the

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the best frequencies to use for radio communications throughout the world. There are also

five series of nonperiodical publications: Monographs, Applied Mathematics Series, Handbooks,

Miscellaneous Publications, and Technical Notes.

A complete listing of the Bureau's publications can be found in National Bureau of Standards Circular 460, Publications of the National Bureau of Standards, 1901 to June 1947 ($1 .25),

and the Supplement to National Bureau of Standards Circular 460, July 1947 to June 1957

($1.50), and Miscellaneous Publication 240, July 1957 to June 1960 (includes Titles of Papers

Published in Outside Journals 1950 to 1959) ($2.25); available from the Superintendent of Documents, Government Printing Office, Washington 25, D.C.
NATIONAL BUREAU OF STANDARDS

Technical ^otc 168

ISSUED APRIL 1, 1963

TRANSISTORIZED BUILDING BLOCKS

FOR DATA INSTRUMENTATION

Roger L. Hil

NBS Technical Notes are designed to supplement the Bureau's regular publications program. They provide a means for making available scientific data that are of transient or limited interest. Technical Notes may be

listed or referred to in the open literature.

For sale by the Superintendent of Documents, U.S. Government Printing Office Washington 25, D.C. - Price 55 cents

Contents

Page

I. Introduction 1

II. General System and Package Specifications 2

III. Series 2 Packages ....... 3

IV. Series 3 Packages 13

V. Logical Symbols . 16

VI. Examples of Design Problems ...... 21

VII. Yield and Reliability Data ........ 27

Appendix . 29

Figures ...... 31

Board Layouts • • • 77

111
ABSTRACT

The National Bureau of Standards has developed a number of modular transistorized digital circuits that

have been used in automatizing many data recording and

preliminary processing tasks encountered in its scientific

operations . These versatile building blocks can be connected together systematically to form digital circuits

that accept raw data from experimental equipment and

transpose these data into a form suitable for input to a high-speed electronic computer.

Each assembly of packages can be tailored to fit

the special requirements of the project and can be used

at the site of the experiment. The output from the system

can be: 1) fed directly to a computer, 2) recorded on a medium (paper tape, magnetic tape, etc.) suitable for

computer input at a later date, or 3) used to drive display

equipment that keeps the scientist informed of the progress

of his experiment.

As a result of experience in the application of these

units, some of the original packages have been modified

and additional types developed. In addition to describing

the modified and new package types, this report also

includes a description of a new series of packages consisting of identical circuitry, but utilizing a different

type of mating connector and a smaller circuit-board.

iv
TRANSISTORIZED BUILDING BLOCKS

FOR DATA INSTRUMENTATION

by Roger L. Hill

I INTRODUCTION

NBS Technical Note 68, published in May I960, described a

series of "Transistorized Building Blocks for Data Transmission",

also identified as Series 2 Packages. Since then, several additional

circuits have been added to this series. In addition, some of the

original circuits have been modified, and these modifications as well

as corrections of errors that occurred in the original descriptions are

noted. Many suggestions from various sources which have been incorporated into Series 2 have also generated another Series (Series 3).

The primary change between the two series is in the physical features

and not the electrical circuit configuration. Series 3 Packages are

physically smaller and stronger, with test points on the top edge of the

packages.

Well over 25, 000 packages have been produced and are incorporated into equipments ranging from simple instrumentation tasks to

complex computer systems. However, we have only had the opportunity to check and follow approximately 40% (10, 000) of these with

detailed production yield and operating reliability figures. This

experience and data are extremely valuable and give us a very good

indication of the performance of the packages from a long-term standpoint. These data are reported in Section VII of this report.

One of the most frustrating phases of interpreting logical designs

has been due to the lack of acceptance of a set of uniform symbols.

The primary purpose of the symbols should be to convey as much

logical information about the electrical circuit as possible, and yet be

simple and easy to draw. Since there has been no specific set of

symbols adopted by many of the organizations working on this task, we

have selected oui own after much deliberation. These are shown and

explained in detail in Section V of this report.

Again it should be emphasized that these series of packages are

designed for laboratory equipments primarily because of an upper

temperature limitation of 50°C. The construction techniques and environmental conditions become more important as the number of

packages or size of the system grows. We take this opportunity to

again state the general operating specifications and also to discuss

and explain several techniques (tricks of the trade) which have proved

invaluable from the standpoints of reliable system performance and

simplicity in trouble shooting or debugging procedures. The success

of any system is dependent not only on the performance of the

individual circuits, but also on the logical design and construction

technology adopted in the system.

1
II. GENERAL SYSTEM AND PACKAGE SPECIFICATIONS

The following specifications apply to all packages and to any

system constructed with them:

1) All major functions may be performed at an operating speed

of up to 50 kc.

2) Ambient temperature range may be from 0° to 50°C (32°

to 122°F).

3) The supply voltages are:

a) -12 volts (Care should be taken not only in ground

distribution but also in ensuring that this voltage

appears at the terminals of the package. This

supply is usually filtered with an electrolytic capacitor in parallel with a smaller mylar capacitor

which has a lower impedance to high frequency

transients. )

b) +12 volts.

c) Other special voltages required for references (analog

comparison) and for driving mechanical devices.

4) The digital pulses have:

a) A minimum range of to -6 volts,

b) A propagation delay averaging 0. 5 [xsec,

c) A rise of at least 6 volts in 1. usee.

Each package is constructed on a plug-in printed-board and uses

electronic components that are common stock items to avoid replacement problems. Most of the packages contain type 2N414 transistors,

and some contain types 2N363, 2N123, or 2N1302 transistors. In

some of the packages components or subassemblies are left unconnected and must be wired externally to the package. Connecting

these components externally allows greater flexibility in combining

them.
e<

III. SERIES 2 PACKAGES

The packages described in this Section were either developed

)r modified since NBS Technical Note 68 was issued. For all of NBS

applications a zero ±0. 5 volt signal is considered a logical "one" and a

aegative (-6 to -12 volts) signal as a logical "zero". In portions of

:his text, flip-flops will be referred to in terms of their input lines,

(such as R-S, J-K, or T. The logical characteristics _V of each type

~re outlined in the following paragraphs.

An R-S flip-flop has two inputs. Input S, the set line, puts the

flip-flop in the "one" state, and input R, the reset line, puts it into the

|"zero " state. These rules are true only if a "one" is applied to the

particular input line and a "zero" to the other input line. If both R and

p are "zero", the flip-flop will do nothing. However, if both R and S

are "one", the action of the flip-flop is indeterminate.

The J-K flip-flop has the properties of an R-S type, except that

if both J and K are "one" the circuit will change to the opposite state.

The T flip-flop has a single input line which causes the circuit to

change state when it is "one", but leaves it in its former state otherwise.

Gated "T" Input, Series 2

The gated "T" input package is used for furnishing a T input

connection to a flip-flop. This T input may be inhibited by a control

pulse to allow shifting of other information into a flip-flop without permitting the propagation of a new pulse condition to succeeding flipflops.

A schematic diagram of the gated T input circuit is shown in

Fig. 1. Four similar circuits are contained in each package. Each

circuit consists of a pair of our standard pulse gates (enclosed by

dashed lines) with the d-c level of each resistor determined by a onetransistor switch (Q ]_ or Q^). These switches are controlled by a combination of the turn-on command and the d-c levels of the flip-flop

collectors to which they are connected.

The presence of a negative turn-on command pulse enables the

switch (Qi or Q2)> with its emitter connected to the "one" (zero volts

level) collector of the flip-flop, to turn on. This places the d-c level

of its gate resistor (R^ or R2) at ground. Therefore, if a positive

pulse is applied to the counting pulse input the flip-flop to which the

diodes (CR^ and CR2) are connected will function as one stage of a

binary counter with a T-input. — Logical Design of Digital Computers by Montgomery Phister, Jr,

John Wiley & Sons, Inc. , 1958.

Figures appear in consecutive order in back of the Appendix.

3
A positive level (ground) at the turn-on command (enable) input

will inhibit the counting pulse and allow the transfer of new informatior

into the flip-flop without propagation of a false carry signal.

A typical example of an application of this package is shown in

the logical diagram of Fig. 2 which illustrates a series of flip-flops

being used as a counter and also a shift register. During the shift

register input the T inputs to the flip-flops are inhibited by maintaining a positive (ground) level on the enable line.

One -Shot, Series ZA

The pin configuration of this one -shot package is directly interchangeable with that of the Series 2 Model. To alleviate a problem of

having the flip-flop "hang-up" in the wrong state a threshold circuit

has been developed which provides a d-c reset to the flip-flop.

Positive monostable operation is assured with this circuit.

res

3:

( Initially, transistors Ql and Q6 are conducting and all others

are in the cut-off state. For normal operation, pin 4 is connected to

pin 10 and a positive going input pulse is applied to the input terminal

(pin 1). This triggers the flip-flop (Ql and Q2), and Q2 assumes the

conducting state, cutting off Qft. The timing circuit, composed of

resistor R 1 and one or more of capacitors C\, C^> and C3, begins to

charge toward a terminal voltage determined in part by the adjustment j of the IK potentiometer (R3) which is used for fine control of the output pulse width. Coarse control is obtained by grounding one of the

timing capacitors (pin 17, 19 or 21). Pulse widths ranging from below

10 jasecs to above 7 msecs may be obtained by using the capacitor

values shown in the schematic diagram. For wider pulses (from 7

msecs to beyond 1 sec) an external capacitor may be used from pin 12

to ground. Consistency of pulse widths above 10 msec is very

dependent upon the leakage and over -all quality of the capacitor.

When the timing circuit is charged to its selected voltage level

the threshold circuit, which consists of a complementary transistor

circuit (Q3 and Q4) is triggered. This turns on a transistor, Q5,

which clamps the collector of the normally on transistor, Q 1, of the

flip-flop to ground at the end of the timing cycle; thereby, returning

the flip-flop to its initial state.

Trigger diodes (CR^ and CR2) have been added from both the

timing circuit and the discharge transistor (Q6) to the threshold

circuit in order to achieve faster switching of the threshold circuit.

These diodes enable the circuit to switch rapidly even when a large

timing capacitor is being used. A two-input diode or-gate (CR3 and

CR4) has been inserted from the flip-flop and the restart input to the

input circuit of the discharge transistor.

A positive going trigger pulse output which occurs at the trailing edge of the one-shot output is available, at the collector of

4

I
ransistor Q7 (pin 9), for triggering an external circuit such as a

lip-flop.

The restart mode of operation permits the timing cycle to be

stopped and started without resetting the flip-flop. A negative pulse

ipplied to the restart input turns on the discharge transistor and halts

he timing cycle which may be started again when the restart input is

-estored to ground level. This package may be used for sensing a

rap in a series of pulses by applying negative pulses to both the

lormal input and the restart input as shown in Fig. 4. The trailing

idge of the first pulse sets the flip-flop which initiates the timing

vaveform. Each successive negative pulse restarts the timing waveform until a gap occurs in the pulse train and allows the timing wave-

"orm to reach the threshold, thus ending the timing cycle in the

lormal manner.

Alternatively, the timing cycle may be ended synchronously as

shown in Fig. 5 with an external pulse train which is applied to the

apacitor (pin 3) of the trigger gate. During the timing cycle the d-c

Level of this gate resistor will normally be negative until the cycle

ends and the level returns to ground. This allows the gate capacitor

:o charge and respond to the following pulse which turns off the flipTop. A jumper connection to pin 10 on the socket determines whether

;he package is to be used for the restart mode of operation or for the

synchronous turn-off mode. A block diagram for each mode with

external wiring and input-output waveforms is shown in Figs. 4 and 5.

Pulse Gate Driver Package, Series 2A

The pulse gate driver package, Series 2A, is intended to replace

the Series 2 version without requiring wiring changes in any previous

isystem applications. The circuit requires a single input that is

complementary to the output since inversion takes place. Two circuits are contained on one board with connections as shown in Fig. 6.

The former model had two stages of inversion, therefore, the output

followed the input on pin 7 (or 19). Since no connections are made

to these two pins on the new package, no wiring changes are necessary

when it is substituted for the old series 2 package.

The input impedance of the pulse gate driver presents 2 orinverter loads to any driving circuit. The circuit output will drive 20

flip-flops or 24 and/or inverter loads at a repetition rate of 50 kilocycles. Greater loads can be driven provided the frequency of

operation is decreased. For example, the circuit will drive 30 flipflop loads at a repetition rate of 20 kilocycles. The fall time increases with an increase in capacitive load thus extending the recovery

jtime of the circuit.

The pulse gate driver is basically a three -transistor circuit with

two grounded emitter amplifiers operating in parallel with one (Qx)

driving an emitter follower (Qz)» The grounded emitter amplifier (Q 3)
>;

acts as a low impedance discharge path for the capacitive portion of

the load when the transistor is turned on by a negative going input

signal. The emitter follower (Q2) is a low impedance discharge path

for the load capacitance when the input signal is positive going and

turning off Qi which drives Q;?. The circuit operates as an inverting

power amplifier for either pulses or levels with a minimum rise of 6 \ volts in one microsecond. When a positive going signal brings the

input terminal to ground Qi is turned off and the output voltage falls

toward -8 volts at a rate determined by R 1 and the impedance of the

saturated transistor 02 in series with the capacitive and resistive

load. When a negative going signal is applied to the input, Ql is

turned on which turns off Q2. The grounded emitter amplifier, Q3, i< turned on bringing the output to ground.

The p of all three transistors should be greater than 55 with

V__ = 6V and 1=1 ma.

Preamplifier Package, Series 2

The preamplifier package is intended for use where a standard

output pulse is desired for triggering digital logic packages in this

series, such as the flip-flop and one-shot. The input to this package

may be a push-pull or single -ended sinusoidal waveform with a

repetition rate which is variable from 50 kc down to 7 cps. The input

signal must have a peak-to-peak amplitude of at least 0. 5 volt. The

output pulse will swing from -12 volts (the collector supply voltage)

to ground potential with a rise time of less than one microsecond.

This package (Figure 7) contains a push-pull amplifier stage

which may be modified by means of an external jumper for single

ended input signals. When used in this fashion, it has a gain of

approximately 10. The input amplifier is followed by a Schmitt

trigger circuit which switches rapidly in response to slowly varying

input voltages, providing an output pulse having the desired rise time

and amplitude. Since the amplifier and trigger circuit are directcoupled, there is no shift in threshold with repetition rate.

A threshold control is provided for establishing a suitable

triggering level in order to avoid multiple triggering on irregular

waveforms and to provide discrimination against background noise.

In addition, a balance control is provided on the push-pull input stage.-

This is useful for obtaining balanced clipping on large push-pull input

signals, and is necessary to obtain correct operation with singleended connection. A feature of the input amplifier is that a substantial d-c level or common-mode component may be accommodated

in the triggering signal. When used with a push-pull signal, the

amplifier will tolerate a common-mode d-c shift of -3 to +10 volts.

When used as a push-pull amplifier, the input signal is applied

to terminals 5 and 7. With single -ended input signals, terminal 5 is

grounded and the input signal is applied to terminal 7. The input

6
ifK

erminals are connected through current limiting resistors R and R

o the bases of transistors Qj and Q which are connected as an

mitter -coupled amplifier stage. The emitters of Qx and Q are

onnected through a 100-ohm balance potentiometer, R , which

>rovide some degeneration. The potentiometer wiper is connected to

he collector of transistor Q3

, which serves as a constant-current

;ource, and appears as a very high impedance. This leads to the high

ommon-mode rejection obtained from the push-pull amplifier stage.

The operation of Q, as a constant-current source can be

:xplained as follows: The base of Q3 is connected to a low-impedance

'oltage divider consisting of R6 and IL, which places the base at about

-11 volts. The emitter is returned to +12 volts through a 120 -ohm

-esistor, R . The transistor attempts to maintain the emitter at a

potential close to that of the base, resulting in a drop of about one volt

icross R , and a steady current through it of about 8 ma. The current

hrough R8 flows mainly in the collector circuit; thus a constant

;ollector current of 8 ma is obtained over a wide range of collector

/oltages

.

n The emitter-coupled amplifier has good overload characteristics

that it recovers rapidly from overloads of either polarity. The

ibresent circuit is direct coupled throughout, so there are no capacitors

.vhich might charge during an overload.

The amplifier output is a single -ended signal for either push-pull

or single -ended inputs. This signal may be viewed with an oscilloscope at a test point brought out to terminal 3. The signal is applied

;o a potentiometer, R , which serves as a threshold control and drives

k trigger amplifier stage, Q4

. This is an NPN transistor connected as

'Jan emitter follower and furnishes positive trigger signals to the output

jstage which is a Schmitt trigger circuit consisting of transistors Q

and Q . These transistors are emitter -coupled with the emitters

jlbeing returned to +12 volts through a 1000-ohm resistor, R . This

furnishes a large amount of coupling between the two transistors.

Additional regeneration is afforded by the coupling network, R^ and

C , from the collector Q to the base of Q6

. The emitters of Q and

jb

6 rest approximately at ground potential, with Q5 normally conducting

[and Q cut off. Application of a positive trigger signal to the base of

|Q- results in Q„ turning off and T, turning on. It would also have been

l J

: [ *> 5 O "possible to use negative signals, turning the "off" side "on"; however,

it has been observed that there is less tendency for the output signal to

follow the input (which would deteriorate the rise time) if the "on" side

as triggered "off".

Both collectors of the Schmitt circuit are brought out, providing

complementary output signals; however, terminal 16 is the one which

goes positive when triggered, and hence is the one that would normally

be used for triggering other circuits, such as flip-flops and one -shots.

Generally speaking, it is the leading edge of this signal which will be

used; the width is subject to wide variation, depending on the triggering
hi

signal. The Schmitt circuit is bistable and will remain in its

triggered state as long as the input signal exceeds the threshold. A

typical connection diagram is shown in Figure 8.

The +12 volt supply is essential to the circuit operation and is

not merely a bias supply for use at elevated temperatures. Both the

-12 volt supply and the +12 volt supply must be connected as indicated

Pulse Stretcher Package, Series 2

The pulse stretcher package is intended for use where an analog]

amplitude value is to be retained for a brief interval. The value is

stored as a charge on a 1. (j,fd low leakage, capacitor and may be

retained for several milliseconds or longer, depending upon the

required accuracy. Circuits are provided for rapidly discharging and

charging the capacitor, and an output isolation stage is provided whicl:

_ permits the stored voltage value to be read out while presenting a high impedance to the capacitor.

The package was originally developed for use with an analog-to-*

digital converter. In this application the pulse stretcher is supplied 3 l with a series of negative pulses of different amplitudes obtained by

sampling a continuously varying waveform. The pulse stretcher then s maintains these amplitude values during the time required for the

conversion process. In the original application the amplitude values

were retained within 5% over a 5 millisecond interval. The width of

the input pulse was 200 microseconds to assure complete charging of

the storage capacitor.

The pulse stretcher package (Fig. 8) normally requires two

signals for its operation. The input signals should be negative pulses

of varying amplitude from to -10 volts, with a pulse width between

100 and 200 microseconds to fully charge the 1. ufd storage

capacitor, Cj . The capacitor is charged by an emitter follower,

which presents a reasonably high impedance greater than 50 kilohms

to the input source, while providing a low impedance for charging the

capacitor. Across C : is a transistor, Q , which is turned on to discharge the capacitor before a new value is read in. An emitter

follower stage containing Q is included to provide a means of reading

out the voltage stored on C.. This stage presents an impedance

greater than 50 kilohms to C, in order not to discharge the capacitor

at an excessive rate, and at the same time presents a reasonably low

output impedance of approximately 5 kilohms depending upon the

circuit being driven.

The discharge pulse which is applied to Q for discharging the

storage capacitor should be a negative pulse of 8 to 12 volts with a duration of 100 to 200 microseconds.

In order to provide for flexibility in the connection of the pulse

stretcher package a number of connections have been brought out to

terminals

8
The timing of the input and discharge signals is illustrated on

ie schematic diagram (Fig. 9). It can be seen that each input pulse

hould be preceded by a discharge pulse to assure that any residual

harge on C 1 is removed prior to recharging. Fig. 10 is a diagram

howing typical connections for an application of the pulse stretcher

ackage.

ampler Package, Series 2

The sampler package is intended for use where the contents of

large number of registers are to be transferred, one by one, to a

ingle buffer register. Normally, gating packages might be used for

nis purpose; however, it is not satisfactory to bring more than 7 or 8

ate diodes to the base input of a flip-flop. The sampling package was

eveloped when a need arose to accommodate a much larger number

f inputs. The limiting quantity has not been ascertained, but at least

5 registers may be sampled in this manner. The registers being

ampled may be connected in any way, such as counters, subtractors,

hift registers, display buffers, etc. , just so long as standard logic

5vels are maintained. The contents will not be disturbed during

ampling, but should be held stationary for the sampling interval,

/hich is 20 microseconds, in order that a true sample be obtained.

a other words, the leading edge of a sampling pulse must precede the

ransfer pulse by a minimum of 20 usee. A typical application of

ampler packages being used to sample three different registers is

jhown in Figure 11 with the sampling and transfer pulse waveforms.

There are 8 sampling circuits per package, and each circuit

onsists of a transistor and diode with appropriate resistors (Fig. 12).

One circuit is needed for each stage that is to be sampled. The

transistor is used as a two-input and-gate with the emitter attached to

he collector of a stage which is at ground potential for a "one", and

tie base connected to a turn-on signal which is negative during

j ampling. An example of the connection of a typical stage is shown

n Fig. 13.

The sampler package may also be used for making an absolute

omparison between registers as illustrated in Fig. 14. The

ollector is connected through a diode to the resistor of a diode gate

t the input of a flip-flop in the buffer register. Up to thirteen

ollectors may be in parallel to this gate resistor achieving in effect

multi-input or-gate. An external resistor must be connected

etween this point and -V so that this point will normally be held

egative. The gate, then, will only be able to charge when a stage

ontaining a "one" is being sampled. Under this circumstance, the

elected sampling transistor will have its emitter at ground potential.

Vhen turned on by the sampling pulse, its collector will move toward

round causing the diode gate to charge. After the sampling pulse

>as been on for 20 microseconds the capacitor of the diode gate may

ie pulsed, transferring the "one" to the buffer register. It is

•ossible, of course, to transfer "zeros" rather than "ones", if desired.
It has been noted that there is a diode in the collector lead of , each sampling transistor. These diodes are necessary to keep the

transistors off in case the collectors should become positive with

respect to their emitters. This would occur when an unselected

transistor is sampling a "zero" (emitter negative); while a selected

transistor on the same collector line is sampling a "one", bringing

the collector line up to ground potential. The remaining components

on the sampling packages are pull-down resistors from base to

emitter (620 ohms) and current-limiting resistors in series with eacl

base lead (8. 2K ohms).

!

!

The value of external resistors used with the collector lines

should be low enough to offset any leakage current which might result

when a large number of sampling circuits are connected in parallel.

However, it should not be so low that the sampling circuit imposes

an appreciable load on the stage being sampled, or that excessive

base current is required to turn the sampling circuit fully on. A

value of 5, 000 ohms has been found quite suitable. When long

registers are being sampled, up to 13 sampling circuits can be

connected to the same base turn-on line. Some 12 or 13 stages

should be about the limit when the turn-on signal is provided by a

single or -inverter or flip-flop, although the turn-on line could be

supplied by two or more drive circuits or a pulse gate driver. In

some applications it may be possible to save circuitry by terminating!

the sampling pulse simultaneously with the start of the read-in pulseJ

The storage associated with the diode gate allows this to be done.

Because of the fact that the sampling circuits are connected to

trigger gates via the resistor input, and are d-c connected throughou

it is not necessary that rise times be preserved in the cabling to and

from the sampling packages. Thus, the registers being sampled may

be widely separated from the buffer register.

Read Package, Series 2E it;

1

,

The Read Package, Series 2E, is intended for reading low leve

( 10 millivolt) signals from a magnetic drum or magnetic tape. It! is designed for use either with NR Z (non-return-to-zero) or returnto-bias recordings. When used with a magnetic drum the frequency

of operation was 50, 000 pps (pulses per second) although it is useful

to higher frequencies. It has also been used with tape at 3, 000 pps

The coupling capacitors in the amplifier portion may be varied to

optimize performance for various conditions such as overload

characteristics and pulse repetition rates greater than 50 kc. How- s ever, the rise time of the output pulse is not a function of frequency.

Since the amplifier portion of the circuit is a-c coupled there may be

a significant settling time after a disturbance such as the application

of a writing signal or a transient due to electronically selecting headiiai

(, The circuit (Fig. 15) consists of two stages of push-pull amplH

fication (QiQ;? and O3Q4) and is intended for use with balanced signalija

10
uch as those obtained across a full head winding. If the winding is

:enter-tapped the center tap would normally be grounded; however,

ae circuit works well even if the center tap is left floating. The

implification is controlled by introducting degeneration in the first

tage. The amplifier stages drive two independent trigger circuits,

jie outputs of which can be combined when used with NRZ signals.

he trigger circuits consist of an impedance -matching stage, Q5 and

!^; a trigger amplifier, Q7 and Q8; and a Schmitt trigger circuit,

!9QlO and QllQl2* The impedance -matching stage serves to

stablish a d-c level for the signal which then remains d-c coupled

irough the remainder of the circuit. This stage drives the trigger

mplifier which is normally biased off and conducts on negative -going

jwings. The trigger amplifier drives the Schmitt trigger circuit

fhich furnishes an output pulse with a rise of at least 9 volts in less

iian one microsecond. This is adequate for application to flip-flops,

ne-shots, or external trigger gates. A pair of trigger gates is

deluded on the package, in addition to the pulse outputs. The trigger

jate outputs (pins 15 and 21) may be directly combined for application

|d a flip-flop or one -shot. The positive rise of the output pulse does

iot quite reach ground potential but remains slightly negative; hence,

|; should not be used as the input to an or-inverter. The duration of

lie output pulse will be determined by the duration of the input waveprm, which is generally a function of the input pulse frequency,

iyith NRZ signals it is possible that the output pulse from one trigger

lircuit may overlap that of the other circuit. This poses no problem,

owever, since the trigger gates respond only to leading edges and

lese will be well separated. A balance adjustment (R^) is provided

'O that the two trigger circuits may be adjusted to respond to equal

Excursions of their respective waveforms. Each circuit responds to

gative -going excursions, but since they are driven by opposite outts of a push-pull amplifier these represent opposite swings of the

aput signal. A test point (pin 13 or 23) is brought out from the input

}d each trigger circuit at a low impedance point. The signals are

till in essentially analog form at these points although some wavehaping may have taken place. Fig. 16 illustrates these various out-

•|ut waveforms.

1 When return-to-bias recording is used with a pulse spacing

/hich is so close as to produce crowding of adjacent pulses a

articular form of envelope distortion occurs, making it difficult to

'stablish a suitable threshold. This can be corrected by adding a d-c restorer" diode (CR^ and CR^) at the point where the signal

asses from a-c to d-c coupling (the input to the impedance -matching

tage). "With return-to-bias recording a "one" is read as a positive

D negative excursion, with the trigger circuit responding to the

'egative excursion. The restorer diode clips off any excessive swing

in the positive direction and results in charging of the coupling

japacitor (C l or C^). The stored voltage then adds to the negative

oing excursion which results in a much more uniform envelope.

the coupling capacitor at this point must be small enough (approximately . 001 |j.fd) to permit significant charging during one half-cycle.

11

eu
pi

11!

A value this small may result in some loss of signal, necessitating

a somewhat higher gain setting. At a frequency of 50, 000 pps a valu<

of .001 [ifd for this capacitor gave satisfactory results.

As a result of the restorer diodes, the waveforms visible at th<

test points will appear to be half -wave rectified, having only negative

excursions

Typical applications of the Read Package are as shown in Fig,

17.

Indicator /Amplifier Package, Series 2

The circuitry for this package (Fig. 18) consists of that of our

original indicator package plus a resistor (usually 620 ohms) for eacltransistor from -V to its collector. This enables the ten circuits in

the package to be used either as a type 344 incandescent lamp driver

with -V (pin 1) open, or as a common-emitter amplifier by providing

-V (-12 volts).

| ii Dual Write Package, Series 2A

This package is used for recording on magnetic tape or drum.

It is intended for use with a center-tapped recording head and may be

used for a variety of recording schemes such as non-return-to-zero

(NRZ) or return-to-bias. There are two complete and independent

circuits per package. Each circuit can provide up to approximately

200 milliamperes of write current, the actual value being determinec

by the recording head resistance and the value of the fixed currentlimiting resistors on the package.

For normal operation, using the lower numbered half of the

package (Fig. 19), a complementary input signal is connected to pins

2 and 11. The outputs (pins 3 and 5) are connected to the read-write

busses (two lines common to the opposite sides of recording head

windings). Pins 1 and 7 are terminals on a voltage divider from the

read-write busses and may serve as inputs to a read package.

Pulse Generator with Flip-Flop, Series 2

A diagram (Fig. 20) of the circuit for this package is included

only to show the proper wiring and pin connections when using a

typical pulse transformer. The only other variation is in the value o; the resistor, R, (56 ohms), across the feedback winding of the trans

former. The function of this resistor is to prevent oscillations

between pulses, therefore, its value which is dependent upon the

inductance of the transformer may vary slightly.

12

i :oi

!

re:

?='

cit

in

:.

oi

cii
analog Voltage Comparator, Series 2

A diagram (Fig. 21) of the circuit for this package, as for the

previous one, is to show proper pin connections when using a typical

ulse transformer.

IV SERIES 3 PACKAGES

After modifying some of the original circuit layouts and designng additional types of circuits for the Series 2 Packages, increasing

osts (nearly doubled) of the mating connectors reached a level where

v^e could not justify one of our original design criteria - that of

xonomy. Since there was no directly replaceable connector avail-

.ble, it was decided that we change the connector type. This

Lecessitated the redesign of all printed circuit layouts. For these

reasons, plus the desire for a more compact unit, a complete set of

Series 3 Packages were designed. A photograph of some Series 3

packages plus two mating connectors is shown in Fig. 22. The

onversion from Series 2 was accomplished without sacrificing reLability of the units and in some cases versatility was increased,

'he cost for each unit was considerably reduced so that at present

he average cost per package, including mating connectors in quantiies of 500 (assorted types), is less than fourteen dollars.

Major physical differences between the two series are: The

Series 3 Units are constructed on smaller (3 l/8" x 4 3/4") fire

fetardant glass epoxy boards vs 4" x 5" XXXP phenolic for Series 2;

tt he Series 3 connector is a 23-terminal blade-type vs. a 25-terminal

(jin-type; voltages and ground, where necessary, are located on

:ommon pin numbers for each package type; and test point jacks in

fssorted colors, which also serve to identify the package type, are

tt the top edge of most boards.

Using the Series 3 Packages in one of our standard drawer-type

Chassis, the density is increased from 72 to 110 packages per

Irawer. Figures 23 and 24 show the package and the wiring sides,

espectively, of a typical drawer in one of our systems.

To conserve space and avoid repetition the only Series 3

packages described in this section are those with modified or entire

circuitry which is unique to the Series 3 unit. Otherwise, as noted

In Table 1, the descriptions of the circuits shown in Figures 25

through 38 may be found either in the Series 2 package descriptions

Df this report or in NBS Technical Note No. 68. In most cases the

circuitry for both series is identical and differs only in pin numbers.

13
SERIES 3

PACKAGE TYPE

LOCATION OF

DESCRIPTION

FIGURE NUMBER OF

SCHEMATIC DIAGRAM

(In this report

)

Analog Switch

Analog Voltage

Comparator

Decimal Decoder

Dual Flip-Flop

Gated-T Input

Indicator /Amplifier

NBS Tech Note 68

This Report, Series 2

Octal-Hexadecimal NBS Tech Note 68

Decoder

One Shot, Series 3

"

One Shot, Series 3A This Report, Series 2

Pulse Gate Driver "

Pulse Generator " with Flip -Flop

Read "

Sampler "

Dual Write "

25

26

27

28

29

30

31

32

33

34

35

36

37

38

TABLE 1

14
•ual Pulse Generator, Series 3

The circuitry for this package (Fig. 39) consists of a freeunning blocking oscillator with its output connected to an inverting

mplifier. Both circuits are identical to that included in the pulse

;enerator with flip-flop package. The amplifier output may be inibited by the application of a positive signal at pin 5 or 20. Two

•^dependent pulse generators are included on a board.

'ulse Gate, Series 3

The circuitry for this package (Fig. 40) is identical to that of

le original gate package, series 2 with the exception that two of the

iput capacitors (pins 19 & 21) are connected on this board. This was

ecessary in order to place eight gate circuits on the board.

.mplifier, Series 3

This package (Fig. 41) consists of nine independent two tranistor amplifiers which have an input impedance of approximately 40K

nd an output impedance of approximately IK. The output remains in

n off state (-12 volts) when the input level is between ground and -1

olt. An input signal of -2 to -12 volts amplitude will cause the ampliLer to turn on causing the output to swing very near to ground (<0. 5

olts).

Lnd/Or Inverter, Series 3

The basic circuit (Fig. 42) of the and/or Inverter has not been

jhanged but, in order to increase the versatility of this package the

hput diode configuration has been modified. There are four inde - >endent inverters, one with four fixed input diodes and three with one

ixed input diode. Also, included on the board are a group of three

iodes and a separate pair of diodes. Each of these two combinations

ave a common anode connection which may be tied into any of three

if the inverters with a connection brought out from its base circuit.

|n this manner multiple input inverters may be formed with a maximum of nine inputs to a single inverter on one board.

5CD Counter, Series 3

This package (Fig. 43) consists of four of our standard fliplops connected as a serial binary 1-2-4-8 counter with the necessary

eedback gating to enable it to function as a binary coded decimal

ounter. The counter may be reset electronically by applying a

>ositive going pulse with a minimum of six volts amplitude

eferenced to -V) and a rise of at least six volts in one microsecond.

f it is desired that the counter be reset manually the emitter bus

pin 15), which is common to one emitter of each flip-flop, is

connected through a normally closed switch to ground. Opening this

twitch would reset the counter. If a manual reset is not required the

i 15
emitter bus may be tied directly to ground (pin 22). Both collectors

of each flip-flop are brought out to individual pins. The input signal

characteristics are the same as for a standard flip-flop.

V. LOGICAL SYMBOLS

In the absence of the adoption of a standard set of logical

symbols by any of the national organizations responsible for this task

we have developed the following symbols which we feel convey an

adequate representation of the logical functions of the various

schematic diagrams. ,

Pulse Gate

(circuit and symbol)

-IF <)

Flip-Flop

T input

Relative voltage levels for

zero or reset state is indicated

(_+) inside symbol

— +

A

JK inputs

(Internal pulse gates)

4-

K

n

16
RS inputs

Requires external pulse gates

Note: external gate connections

to base are shown byplacing arrows at the

corners of the block.

R

+

C) O

SYMBOLS FOR INTERCONNECTED FLIP-FLOPS

SHIFT PULSE

+

* K

)

+

i f>

T

Shift Register -using internal gates

Each circle in the above diagram symbolizes

the common connection of a pair of capacitors

which are included in the two internal pulse

gate circuits contained in the flip-flop to its

left.

+

SHIFT PULSE

_TL

Shift Register -using external gates

Each circle in the above diagram symbolizes

the capacitor of a standard pulse gate as

previously noted.

17
2

INPUT

+ 4- 4 +

Serial Binary Counter -with indicators

In the above diagram, the symbol above each flip-flop

(circle and triangle) represents an indicator /amplifier driver.

AND /OR INVERTER

A

B

C

D

ABCD

A

B

C

D

A+B+C+D

AND OR

This symbol was adopted not only for its ease of drawing but

also because it readily indicates whether the circuit is used as a

logical AND or a logical OR. One may start at the beginning, middle,

or end of a logical diagram and know, at any point, what the signal

polarity is.

The above symbols are modified for the series 3 package to

indicate the internal connection, if it is used, for increasing the

number of available inputs. Its symbols are shown below with one

internal connection (6 to 17) and typical pin numbers.

2

3

4

5

15

16

:^A

7

A17 AND OR

18
J~L

ONE-SHOT

"i r

EXTERNAL

CAPACITOR

J L

This composite symbol, which represents a one -shot, is a flipflop with input and output lines of a one -shot package joined to a block

indicating the internal capacitor ground, or external capacitor used

and duration of the output pulse.

SAMPLER

A

B

SYMBOL

CIRCUIT

19
GATED-T INPUT

ENABLE

ENABLE

COUNT

INPUT

COUNT

INPUT

\r <r +

CIRCUT SYMBOL

The example above shows one bit of a counter/register with • feedback coming from the outputs of the flip-flop to which the Gated-T

input is connected. This is the normal feedback; however, for

special applications feedback connection may come from another flipflop.

OTHER CIRCUITS

Circuits such as the Pulse Gate Driver, Read, Write, and

special packages are denoted by a block so labeled with input-output

lines indicated as shown below:

OUT

TO

READ/

WRITE

BUSSES

TO READ PKG.

20
VI. EXAMPLES OF DESIGN PROBLEMS

The following examples were chosen to emphasize a few logical

design techniques. Also, this section demonstrates the use of our

adopted logic symbols.

The first example is the design and logic of a binary decimal

four bit counter. As one knows, there are several methods of constructing a counter but there are two basic techniques, serial and

parallel. In a serial counter each flip-flop change occurs after that of a preceding stage. The number and type of stages determine the total

time required for the counter to reach its quiescent state . In a

parallel counter each flip-flop assumes its final state simultaneously.

Therefore, this type counter is faster and allows one to examine or

remove contents of the counter in much less time than from a serial

counter. Using the techniques described in M. Phister's text,*

"Logical Design of Digital Computers", an example of the design of a

parallel binary coded decimal (BCD) counter is described below.

As stated in Phister*, the originally defined behavior of a flipflop is that it changes its state after the initial application of an input

pulse. This is necessary if one of the flip-flop outputs is connected to

an input and-gate. It insures that changing of the flip-flop state will

not affect the gate because the flip-flop change does not occur until the

input pulse is no longer present. Since our flip-flops change state

only when a positive rise is sent into the input, and we are using andinverter stages for gating structures on the inputs, the flip-flops will

not change state until the trailing edge of an input pulse. This type of

input connection has not only the logical value indicated, but also may

be used for another which is; there is now a specification on the input

pulse shape. It must be at least 10 microseconds in duration to satisfy

the input time constant required for charging the input capacitors of

the flip-flops. Therefore, no noise pulse of shorter duration may

trigger the flip-flops.

The simplest input equations for a parallel BCD counter are:

JA

= BCD, KA

= D

TB

= CD

T

c

= AD

T D =

1 A logical diagram illustrating the parallel BCD counter

described above is shown in Fig. 44.

Serial counters may be constructed as shown in Fig. 45. These

counters propagate the signal from flip-flop to flip-flop, resulting in a considerable time delay before the last flip-flop in the series

assumes its proper state.

* cit. , p. 3.

21
The second example of a design problem is the logical design of a parallel adder which is incorporated into ACCESS, a computer

being designed and constructed for the Office of Emergency Planning.

A parallel adder requires a few more packaged circuits in the

actual adder section than for a serial adder; however, it simplifies

the logic and decreases the number of packages required in the

control circuitry in addition to operating at a higher speed.

Consider the addition of bits An and Bn of the A and B registers,

as shown in Fig. 46. The present states of An and Bn must be

combined with the carry from the previous stage, if there is one, to

determine the state of An after the addition (A contains the sum) and

the state of the carry to the next stage.

Table A represents Cn + 1, the carry to the next stage (n + 1),

and Ann+1, the state of the adder stage under consideration (n) after

the addition, as functions of the three variables An, Bn, and Cn, the

present states of the n"1 stage of A and B and the carry from the

previous stage. From this table Cn + 1 and Ann+ 1 are represented

as Boolean functions and simplified as follows:

Cn + 1 = AnBnCn + AnBnCn + AnBnCn + AnBnCn

Simplified,

Cn + 1 = AnBn + AnCn + BnCn

and . , An = AnBnCn + AnBnCn + AnBnCn + AnBnCn

An Bn Cn C

n+ 1

a n+1 An

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1

1 1 1 1 1 TABLE A

22
Employing the input equation of a T input flip-flop,

T = Q

n Q

n +

' + Q

n Q

n + \

where Q is the present state and Q the desired state of the flipflop after the input, T. This is a function for the input to An as a T

input flip-flop so that it represents the function An11 +

. The sum in

the addition is

T = BnCn + BnCn

These functions for the sum and carry can be developed for each

stage of a multi-stage adder, and are implemented in the general

stage as in Fig. 47.

The actual addition of B to A, the input to An if the variables

are in the appropriate states, occurs at the trailing edge of the add

command. However, the conditions setting up Cn for each stage must

be stable before such an add command is given. Note that the

condition of each Cn depends upon that of the previous stage, and that

this dependence continues until the least significant stage of the adder

J is reached, at which rpoint the carry is merely a function of A , J } stage 1 and B ,. Thus, as soon as the least significant stages have been

j set up foP the add operation, the carry exists as a variable for the

next adder stage.

The time necessary for the carry to be set up at the most

significant end of the adder, after completing the setup of the least

significant stage, is known as the propagation or ripple time of the

adder. This time, the sum of the propagation times of the individual

stages, limits the speed of the parallel adder. In ACCESS the

propagation time through the one word length adder is on the order of

18 microseconds and for double word length, 3 6 microseconds.

The ACCESS parallel adder, as shown in Fig. 48 consists of two

sections, each section containing 12 stages controlled by common

micro-operation lines. These micro -ope rations to the adder are the

add command, either single or double word length; and the carry

command. The carry command is activated for all operations involving the adder except Modulus 2 Add.

The basic adder adds the absolute values of A and B. In the

complete addition operation it is necessary to consider the signs of A

and B, and to sequence through control operations according to

certain rules. Table B shows the procedure to be followed for each

of the four possible combinations of A and B.

23
Original ABASigns Comp Carry No Carry Final Sign

1. + + no set OF +

2. + - yes add 1 comp +

3. - + yes add 1 + comp

4. no set OF

TABLE B. Addition Procedure

24
Interpretation of the Table is as follows:

1. If both A and B are positive, S (sum) equals A + B, and if

a carry exists from the addition the overflow flip-flop is set. The

sign of the final sum is positive.

2. If A is positive and B is negative, A is complemented

before adding it to B. When a carry exists from this addition, a "one"

is added to the sum. In this case the final sign is negative. If there

is no carry, the sum is complemented and the final sign is positive.

3. If A is negative and B is positive, A is complemented, then

added to B. If there is a carry, "one" is added and the final sign is

positive. If there is no carry, the sum is complemented and the

final sign is negative.

4. If both A and B are negative, A is added to B, the final sum

being negative, and the overflow flip-flop is set if a carry occurs.

A block diagram of the micro -operations required to carry out

this procedure is shown in Fig. 49. The following steps, referenced

[by number to this figure form the add operation sequence.

1. Transfer the word to be added from the operand address to

ithe B register.

| 2. Compare the signs of A and B. If they are different,

I complement A and set the complement flip-flop.

3. Add B to A, leaving the sum in A.

4. If a carry exists from the most significant stage of the

adder, set the carry flip-flop.

5. If the complement flip-flop and the carry flip-flop are both

on, reset B to "one". Otherwise, reset B to all "zeros".

6. If the carry flip-flop is on and the complement flip-flop is

off, set the overflow flip-flop.

7. If the complement flip-flop is on and the carry flip-flop is

off, complement A.

8. If the complement flip-flop and the carry flip-flop are both

on, add the "one" in B to A.

The actual control logic utilized to set the various flip-flops is

shown in Fig. 50.

This sequence of operations is executed by developing a special

set of timing pulses for the addition operation. The time necessary

25
M for each part of the sequence includes the various add commands anc commands for setting flip-flops as well as the time necessary for

the carry propagation before the actual addition can occur. Since

most of the control is the same for single or double length addition,

the timing for the two modes is similar. The carry propagation is

twice as long for a double length as for a single length word, so pulses are divided by two for double length operation, providing mor

than sufficient time for the propagation.

Fig. 51 shows the add timing pulses: Sector Compare, (1),

(Z), and (3). All operations occur at either the leading or trailing

edge of these pulses. The pulses (1), (2), and (3) are generated by

feeding the bit pulses (or the bit pulses divided by two for double

length operation) into a three -stage counter. The separate lines for

pulses (1), (2), and (3) are activated as the counter reaches the

appropriate states.

The actual Control sequence for the addition operation is as

follows:

At Ta The beginning of the operation resets the overflow,

carry, and complement flip-flops.

At T During the sector compare time the word to be addec

is transferred from memory into the B register. If the operation is double length, the sector compare

pulse remains on for two word times.

At Tb If the signs of A and B are different, complement

A and set the complement flip-flop. The time

between Tb and Tc is occupied by the carry propagation which occurs after complementing A, if this

is done.

At Tc The actual add occurs and the carry flip-flop is set

if conditions are as specified in the procedure.

At Td B is reset to "zero" or "one", the overflow flip-flop

is set, and A is complemented if conditions are

correct.

At Te B is added to A if B has been set to "one" and the

end of operation signal is given.

All sections of the control are identical for single or double

length operation except the add command. The add command is

actually fed to both halves of the adder in the double length mode.

:

.

•

26
'I I

Other operations employing all or part of this addition control

circuitry are Subtract, Mod 2 Add, Multiply, and Divide. The

Subtract operation changes the sign of the word from the memory

mmediately after its transfer into the B register, then executes the

idd operation in its entirety. The Mod 2 Add operation merely adds

he operand to A without activating the carry command and causing no

;hange in the signs of the A register.

VII. YIELD AND RELIABILITY

A majority of the transistors used in our transistorized building

blocks are type 2N414 alloy junction units. In our original designs, a

:ew years ago, this type was specified because a transistor type of

he entertainment variety such as the 2N414 (an RF amplifier) was the

oest choice for obtaining low-cost, stable characteristics transistors.

\t that time this particular type was being produced by only one manuacturer, but now it is produced by many companies which has helped

o keep the cost down.

To maintain low manufacturing costs for our building blocks we

io not require our contractors to perform qualitative tests on the

ransistors used. It is only necessary that a unit exhibit transistor

action regardless of the other parameters. Therefore, our requirements are for a consistently uniform distribution of characteristics

Erom one transistor order to another.

Our circuits using 2N414 transistors are designed for a beta

range of 20 to 200. Normally, if one purchases a number of this

type transistor off-the-shelf from a wholesaler, the beta can be

expected to fall within this range virtually 99- 9% of the time. A

graph of the normal distribution of current gain for a 2N414 type

transistor is shown in Fig. 52. The data used for these plots was

obtained from d-c beta measurements of a random selection of units

produced by four manufacturers and purchased from a wholesaler.

These measurements were taken with I c

= 1 ma and Vc = 6 volts.

A distribution such as that exhibited by manufacturer B has proven

to be most satisfactory. Using transistors with this distribution in

bur building blocks the rejection rate for modules containing them has

consistently remained at less than 5% which is quite acceptable.

An effort was made to devise a simple measurement technique

for determining the acceptability of a group of transistors by making

a single measurement on each unit. After experimenting, it was

decided that measurements of f^ (frequency at which hfe

= 1) would

provide the most applicable data. The gain (hfe) of a type 2N414

transistor is linear at the lower frequencies (below 1 mc) and then

jrolls off at a slope of 6 db /octave. The gain-bandwidth product along

this slope is constant; therefore, a circuit was designed (Fig. 53) for

[measuring gain at a fixed frequency of 1 mc, to determine the gainjbandwidth product for the test unit. Since our frequency is fixed at

1 mc, gain is interpreted as ft.

27
In our test circuit the input generator is set at a frequency of

1. mc and an amplitude of 0. 1 volt peak-to-peak which provides an

i^ of 10 |j.a. The 500K pot is then adjusted until the I meter reading

is 6 ma which assures a d-c collector voltage (Vc ) of 6 volts. The

voltage drop across the 10 ohm resistor, which is observed on the

VTVM, is very nearly equal to the small signal a-c collector voltage

(v c ) because the drop across the 5 ui capacitor is negligible. The

small signal a-c collector current (i c ) may be determined from this

value. Then the gain (hfe ) is equal to i c divided by i^ which, because

of the circuit values used, may be read directly from the VTVM if it

is set on the proper (X 10,000) scale.

Fig. 54 shows the distribution of f^ for a group of 2N414

transistors which includes the same units used for the previous graph.

Units with a distribution such as that exhibited by manufacturer B

produced a very satisfactory yield when used in our modules.

Judging from both graphs it appears that the units produced by

manufacturer D should operate equally well with an acceptable yield.

However, at present the number of transistors from this source

which are used in our modules has been rather limited and not

sufficient for an acceptable appraisal of yield and reliability.

The author gratefully acknowledges contributions to this report

by all the members of the Computer Technology Section, since the

development and applications of these building blocks were a joint

endeavor. However, for original design work, special recognition is

given to Paul Meissner, Donald E. Humphries, J. Michael St. Clair,

and James A. Cunningham. A note of gratitude is also extended to

Robert L. French for his assistance in assembling the artwork

included in this report.

We are also grateful for the constructive feedback from many

divisions of NBS and other outside organizations and have endeavored

to incorporate, where feasible, their suggestions in this latest version!

of our transistorized building blocks.

28
APPENDIX

The diode designated as type DR435 is a gold-bonded germanium

mit with controlled forward voltage drop and the following

haracteristics:

peak inverse voltage - 20 volts

minimum forward current - 10 ma at 0„ 37 volts

maximum average rectified current - 100 ma

maximum reverse current at 25 C - 10 (j.a at 10 volts

'Although type DR435 is indicated on the drawings, any diode meeting

the above specifications would be satisfactory.

In all schematic and board layout drawings the following

(component notations shall apply:

1. All capacitors not specified as micromicrofarads (|j.|i.f)

shall be in microfarads.

2. All resistors shall be 1/2 watt units unless specified

otherwise.

3. All resistors are in ohms unless specified as kilohms (K)

or megohms (M).

4. The voltage rating of all capacitors shall be 15 volts or

greater unless specified otherwise.

5. The notation NC on a potentiometer terminal indicates no

connection.

The Board Layouts (Figs. 55 to 84) show enlarged views of

each printed-circuit board with components layout for any new series

2 packages designed since NBS Technical Note 68 as well as any

which have been modified. Also included is a complete set of series

3 layouts. In all cases the printed-circuit side of the board is shown.

29
'

I

:
ENABLE

COUNT INPUT C

TO COLLECTOR

OF FLIP-FLOP

t * TO BASES OF

FLIP-FLOP

TO COLLECTOR

OF FLIP-FLOP

GATED T INPUT SYMBOL

8.2K

620

> 8 0« TO BASES

OF FLIP-FLOP ^Qw

TO ONE COLLECTOR

OF FLIP-FLOP

TO OTHER COLLECTOR

OF FLIP-FLOP

FIGURE I. GATED "T" INPUT, SERIES 2
ENABLE

'

23

XL SI H w m. if I8L J22

_TL

COUNT

INPUT <

4

3

10

c b

ii

15

14

:d

20

C

19

5

21

4-

A 4

» »'

" t

-TT

4 I

-*—»J

H V

+ » H

n <>

w w

n n

RESET SET RESET SET RESET SET RESET SET

FIGURE 2. EXAMPLE OF GATED -T INPUT PACKAGE USED WITH

COUNTER/ SHIFT REGISTER (SERIES 2).
;z

>-CO

Q

Ld

a:

L_ . o

III

CJ

LU

LiQ_ Ll_ ^t CO O d

Ld z:

LJ Q_ CO CO ^ ^ o_ rr Ld

1.1J CO o X ^ hh-o

COCO

UJ

a:

LdXo

ECTED ATION. I z ac 2 CO 2 Ld ~

CO

O Q.

Ld

O 1

CM

CO 2

Z>m

ro XTERNALLY RESTART

QL tr

CO

Q

CO Ld'Q

CO LlJ ^ < *d n <

h- o d < 2 ^

_i _i -, LT _i _i ^ O < < Q_ ^ — cvi rd <

CM

COLd

trLdCO

I-oX

CO

Ld

ro

Ld

cro
INPUT

.--- +

m

RESTART INPUT

TIMING AND

TRIGGER CKT.

I TI EXTERNAL JUMPER

PIN 4 TO PIN 10

INPUT UUTJ LTLTLTU LTI

OUTPUT i_r U"

FIGURE 4. RESTART OPERATION FOR ONE- SHOT, SERIES 2A.

+

NPUT

PIN I

TIMING AND

TRIGGER CKT

$ TRIGGER GATE

"INPUT (PIN 3)

INPUT n_r\JTjnjTJiJTrLrLrL_

OUTPUT i_r i_r

FIGURE 5. SYNCHRONOUS TURN-OFF OPERATION FOR

ONE -SHOT, SERIES 2A.

,
I— o < 2 b

ISW CVI

co

—

O ^

h- cr co o < CO

cr lu < <

(M

CO

LU

or

LU

CO

orLU>

a:Q

LU

h-<O

LU

CO

_l

Z>

CD

LU

=>O

H

_

3. . CL O
T.R

INPUT v5/

S"\ 2K Rl

( 5Vvww—

47K

i—/vvw—4- R4

IK R6

47KR3

<>—wwv—#

2K

R2

INPUT

2 J-I2V

2N4I4

Q2 100 R5

BALANCE

2N4I4

Q3 120 R8 ww

100 R7

-a/vw

2N4I4

Ql

20K!

RI2

T.V65)

THRESHOLD

CONTROL

2N585

Q4

36K

RI6

CI 4=270

H-H* SI2K

RI5

I0K Rll IKRI7

IK vwv^

RI4

10 K

RIO

note:

H2v® +,2v© out© ©out

ALL RESISTORS ARE 1/2 W.

I

FIGURE 7 PREAMPLIFIER, SERIES 2
TEST POINT

o

PUSH-PULL

INPUT Vx/\/^

GND. CONNECTION^"

FOR SINGLE-ENDED

OPERATION -I2V — o

PACKAGE TO BE

DRIVEN

+ I2V

FIGURE 8. CONNECTION DIAGRAM FOR PREAMPLIFIER PACKAGE
-I2V

©

300

WAAAr

INPUT

2N4I4

Ql

CI

1.0

2N4I4

Q2

GND +I2V DISCHARGE

rULOL .

DISCHARGE PULSE

PIN 13

INPUT PULSE

PIN 3

U u u

i_r

1

n

2N4I4

Q3

^Mr%

© © ®

r;\in -n?\/

© ®x

DLSCHARGF

©

m

@

it

:5IK

23) (24)Q9;

DUT GND -I2V

STRETCHED PULSE

PIN 23

notes :

i. pins 10 and 21 connected for normal operation

2. r and c values are typical, but subject to

change depending on application.

3. all resistors are 1/2 watt.

FIGURE 9. PULSE STRETCHER PACKAGE, SERIES 2
CD

<

O

in

io

hLd

a:

h-

(/)

UJ

co

_l

Q_

q:O

<

CS> <

g

ho

LU

O

<

o

Q_

>-

LU

Z>

(3

Ll
X

REGISTERS BEING SAMPLED

/S

REGISTER

S|

"LTSAMPLING

CIRCUITS

SAMPLING

PULSES \

k*3

TRANSFER

PULSES

REGISTER

s 2 SAMPLING

CIRCUITS

X, X2

^

REGISTER

"LP

SAMPLING

CIRCUITS

X||

^(KKKK)

! if ir w 'r BUFFER

REGISTER

LT

Jl_JLJl_

|X| x2 x3

h- 20^ SEC.

NOTE

LEADING EDGE OF SAMPLING

PULSE MUST PRECEDE TRANSFER PULSE BY AT LEAST

20 fiSEC.

FIGURE EXAMPLE OF SAMPLER PACKAGE APPLICATION
C o- *~c

SYMBOL

2N4I4

620

#-wvw-f

HB-2

8.2K

6 6 6

PIN PIN PIN

NOS NOS. NOS

1 2 3

6 5 4

9 8 7

12 II 10

14 15 16

17 18 19

20 21 22

25 24 23

8 CIRCUITS PER PACKAGE

FIGURE 12. SAMPLER PACKAGE, SERIES 2
LU

h-

(/) o

LU

cro

LU

o

CO

LU

o

<

CO

p

(j)

v-o

LU

O

CD

roLU

cr
en lu

o

< CD

(T LU

CO

2

O

cr

LU

u_

u_Z)

CD

LU

H

ZD

_I

o

CO

CD

<

coo;

< LU

Q

LU

CO

Z)

Z>Oo

o S

< a: ^ LU

o CO

s<

cr z

LU LU

_|LU

3£< LU

CO CD

LU

cr

Z)

o

Ll
•d" m CO IsUJCM

COUJ

a:IUCO

UJ<

o

<

UJ

or

10

q:O
HEAD

READCT^

5K

TEST POINT "l TRIGGER GATE

PULSE

PULSE

TRIGGER GATE

TEST POINT

1

UPPER TRIGGER

CIRCUIT

LOWER TRIGGER

CIRCUIT

(NRZ SIGNALS)

JUMPER OR

EXTERNAL

AMPLIFICATION

CONTROL

FIGURE 16. READ PACKAGE, SERIES 2E CONNECTIONS AND

OUTPUT WAVEFORMS.

-Aj-Ar 5

RETURNTO- BIAS

NRZ

OS

RESET PULSE

(FROM SYNC. CIRCUIT)

_n_n_n_

M+

_IU1_F_

FIGURE 17. TYPICAL APPLICATIONS OF READ PACKAGE, SERIES 2E
H"

(TM\—'wa—

C\J

00

CO

CD

(SHr

H''

CVJ __ CO

(goY-AAA 1

C\J CD

Hi

UoY-AAA

00

00

CD

HiCO

c\J

>

>

tfT\C\J

CD

-01

00

CO

He

-(§)

00

CD 00

ad —^AA-(w)

T-VS

(M

CD

A A 0I~V V V */ —aaa-(5)

00

CD ooL-AA'VV -

He —/\AA--(5)

CO

4

CD

-5fe

00 CO

orn f

k°g

or wft

00 &

LU

Sior _)

°

LU ^<

or CO

co < ^

^ C5

P o

00 3

Id

Q^co

o

00

CD

-33

HOO*

c\j

CO

LU

orLU

co

orLU

o_

<

oro

h-

<

go

LU

or

z>CD

Li_
Q_

LJOX

UJ

C\J

CO

cro

h- o

LU

Q_

CO

LU

cr CO LJ

L±J >

cr <

CO

LU

crLJ

CO

LJ

CO<o<

Ql

LJ

cr<

IDQ

LJ

cro
CVJ co

LU

a:LU

CO

of

3

u_

I Q_

orI

crLU

LdO

LU

CO

O

CO

LU

or

Z)

Ll_
-V

/^INHIBIT

vl2/ INPUT

5.IK

JNKNOWN

i VOLTAGE

!220

K

--5.0

-VC c

DR435

(23)

+V

ANALOG

VOLTAGE

=t=.OOI

JUMPER

ALADDIN

23-178

• LCI

5

NOTES!

2N4I4

l.-Vcc

= -1-2 VOLTS.

2.+VAND-VARE TERMINALS OF A FLOATING POWER SUPPLY.

FIGURE 21. ANALOG VOLTAGE COMPARATOR, SERIES 2
co

UJ

CD<

o

<

0_

ro

CO

LjJ cr

LjJ CO

CO

C\J UJ

cr

CD

Ll
FIGURE 23. PACKAGE SIDE OF A TYPICAL DRAWER CHASSIS
WlHMMBHir'-'

FIGURE 24. WIRING SIDE OF A TYPICAL DRAWER CHASSIS
Q

§LiJ

Q_0

LUQ

h-_l <O<

Q_

ro5£

st- ereo

CO

cog

LU

OJLJLuh- OO

GOZ)

LULL

—'—' _J

<<t>o

ro

GO

LU

crLU

CO

LU<<

Q_Xu

Ico

coo

CO

LU

cr

Z)o
-V

® ©

5.IK

UNKNOWN

VOLTAGE

!220

©

+

5.0

25V

i

K

INHIBIT

INPUT

"Vcc

o

DR435

+V

ANALOG

VOLTAGE

=!=.ooi

©

JUMPER

ALADDIN

23-178

5

NOTES

2N4I4

I. -Vcc

= -12 VOLTS.

2. + V AND -V ARE TERMINALS OF A FLOATING POWER SUPPLY.

FIGURE 26. ANALOG VOLTAGE COMPARATOR, SERIES 3
rO

>ro —

TM<\i or 4- uj

c/)

(/) UJ Ll! I- q z o 3 o

O LJ o Q

o

UJQ

CVJ UJ cj ir3

<]A© <€£©

oo

_: oj to * tfi ID S 00
^2

CD

~e>

LO

00 oo

—-

-AAAAr

oois

-^AA^- : Hc\J I

00

UJ

-w- c

o. 2 a

ST

X 2 00

CvJ m<

roo

oo

u <

cr o>— 

I- Qx

00

_J -I < <LlIOo

Q_I Q

LU

LU

Q_

00

ro

if) LU

q:

LU

00

Q_3

u_I Q_<3Q

00

CO

LU

oro

LL
TURN ON COMMAND

2,23 COUNTING PULSE

NPUT

_TL

5,10 Ol5 > 20

8.2K

620

R2

.001 5.IK

DR435-

Jl(j 16 >

8.2K

CR2 620

,8 013,18 TO BASES

OF FLIP-FLOP

7 J2(j l7> 22

TO ONE COLLECTOR

OF FLIP-FLOP

TO OTHER COLLECTOR

OF FLIP-FLOP

ii _ ii FIGURE 29. GATED T INPUT, SERIES 3
roCO

LU

q:

LU

CO

crLU

_i

Q_

<

eno

o

o

ro

ljcr

Z>
>

§(S)~jwv

^g)c ^{g

>

<^©0

od s oo s °° <

<^©0

cwro\—/v\/v

c\n cjS w 5 cvi oo*< od < op < °° c\j5 cm S c\j s ^

<x>< co < oo < cd

orLUX

CO

C\J

CO

oro

H

CO

CO

CO

orO

}-

COCO

UJ < or or

-I o

_J CVJ < CO

rci ^

UJo

<

<

Q_

COor

UJo

<

o

<

0_

o

C_> UJ

CO

h- t- 3 =>

0_ Q.

=) 3

O O

D<l

— <M

roco

UJ

orUJ

co

orUJQ

o

o

UJQ

_i

<

o

UJo

<

X

UJX

I _)

f*

o

o

ro

UJ

or

Z>S2

u_
ro

CO

LJ

(r

LU

CO

LU

CD

<

o

2

o

X

CO

LJ

o

c\j roLU

a:

Z)

Li_
<

ro

COUJ

orUJCOO

X

CO

I UJ

ro

roUi

trIDO

— <\j ro
< Q3 . Q_ O

*H

X. IS ro ^C\J

<T V.

CO

—

eno co

\- 01 co o

^co 2 — < co

a: lu

cr < <

ro

co

LU

orLU

co

orLU>

a:Q

Ld<

LU

CO

_l

Z>

Q_

ro

LU

cr

Z>C2

Ll_
o

ro

m

CO

LU

or /"-\ CO

St-A \cvj\) v y

Q_

Q_- o H _J

Li_1 Q_

Q . £

Ldo;

£ll cr co«_ Q g< >- or X GQ

to

LU

-z. LU

£LU

O

_l

is

LU

CO

_J

OCO 3 12 Q_ co —

,~l- LO' C0 O ro liJz O LU

Qlu q:

Z> Q(£ o < Ll

Q_

—

=> 

PEED

INES(- CO_J
(0K

ro

if) LJq:

uj

(3

<

o

2

<

LJ

a:

rou

crO
2N4I4

620 NWWf

"or

HB-2

8.2K

6 6 6

PIN PIN PIN

NOS. NOS. NOS

1 2 3

4 5 6

7 8 9

10 II 12

14 15 16

17 18 19

20 21 22

7 CIRCUITS PER PACKAGE

FIGURE 37 SAMPLER PACKAGE, SERIES 3

DR435

-w—

33

'VNAAAr

N.C.

56

200K r'WVV

DR435

620

^/WNAr

INHIBIT

INPUT

=P220

PE-2672-V

4:iM

22

JL

-12 VOLTS GND OUT

FIGURE 39. DUAL PULSE GENERATOR, SERIES 3
ALL DIODES DR 435

ALL CAPACITORS .00 1 /if

ALL RESISTORS 5100 X2

FIGURE 40. PULSE GATE, SERIES 3
2N4I4

2N4I4

©- K -'ww

2N4I4

IK

6 ) vwv

2N4I4

d>-

K

2N4I4

(4>- K

2N4I4

®~ K

-/vwv

2N4I4

27 K 'WW

I.6K

I.6K

-^wwI.6K

/wwI.6K

-'VWV"

I.6K

-vwvI.6K

^vvw6-

2N4I4

2N4I4

2N4I4

2N4I4

2N4I4

2N4I4

IK

27K -'WW

IK ^vwv

27 K 'WW

IK

-#-^ww27K

-'wwIK f-WW"

is

27K

-wwIK f^WW

27 K 'WW

IK

-f-'ww27K 'WW

22JGND ©H-V

FIGURE 41. AMPLIFIER CIRCUIT, SERIES 3
?0-

5:

icm m eg ro \

co <$ ~

co¥1 co °

\-

W UJ CO 2 Q m

fro or < < <

ro

CO

UJ

q:

UJ

CO

(r

UJ

I-

<r

uj>o\Q

-z. <

CM

UJ

(T

Z>o
Tfl

cO

CD 00 |(g)&>€> cu

I-

?3i

ro

<fr CO QO

CO CO

LlJ Qo—1 I I —I I I < < <

l±j 5x

_i ^

_j

xC3

co o

C\J co<s

cro ui

hX

co f- co

UJ

H

cr Q-UJaX

UI

hh-I

CM

Xo

UJO

mcr I UJ oo

3DOOcr cr oo

CO

-i- UJ o cr

C03

o<

ro

CO

UJ

cruiCO

cruiOod

<J

CD

— ro

LU UJ

en cr3O

u.

©
A B — + —B CTB

+

Tr

C D + -D

T,D

C D A D

INPUT

FIGURE 44. LOGICAL DIAGRAM FOR A BCD COUNTER

— + — + — + — +

1 I ( I

1 1 1

I

FIGURE 45. LOGICAL DIAGRAM OF A SERIAL BINARY COUNTER
A n — +

'r Cn + 1, CARRY

ADDER

TO NEXT STAGE

ii — +

C n , CARRY FROM

PREVIOUS STAGE

Bn

FIGURE 46. ADDER STAGE n

Cn-h

An Bn An Cn Bn Cn

An B n

t 1 — 4- +

An

+

£^

ADD

COMMAND

Bn Cn Bn Cn

FIGURE 47 GENERAL ADDER STAGE
A2 Al

ADD

a

F

i ADD

DL

V i

1 ir 1

' r SL

ADDER 1 ADDER 2

J 1 CARRYa

B2 Bl

FIGURE 48. ADDER MICRO - OPERATION

COMPLEMENT COMMAND

' r

A

+ COMP

FF

CARRY

FF

27

i

'

i

1

, 2 4

ADDER

2

CARRY AND

SIGN SENSE

CONTROL

6 OVERFLOW

FF

ADD 3,8^ CARRY 4

COMMAND SENSE 2

i *•

i i

FROM 1 B

+ 5

MEMORY

i 1 RESET B T<3

"0' 'OR

" "

FIGURE 49. ADDITION CONTROL
TIMING COMFF OFFF

+

T

ADD OP ADD OP

TIMING

CARFF

COMFF = COMPLEMENT FLIP-FLOP

OFFF = OVERFLOW FLIP-FLOP

ADD OP = ADD OPERATION.

CAR FF = CARRY FLIP-FLOP

Al s

= A REGISTER SIGN.

Bl s

= B REGISTER SIGN.

SL = SINGLE LENGTH.

DL = DOUBLE LENGTH.

+

ADD OP JT

CI3

TIMING SL

C25 <)

DL

FIGURE 50. ADDITION CONTROL LOGIC

T,

sc

i Tb Tc Td

ADD OP f

SC

l_

(I)

(2)

(3) 1_

FIGURE 51. ADDITION TIMING
H|!1 ii i i 1 \ ' \ \ 4 \ k \ ^ c \ O \Ji k *\> Vv 9 \ >

1% i 1

t\ \ U#

IV

11, > 

X ) o<

LlI OO

<QQ OQ

odod odod - Lull. Ll Ll 22 22

035I ii I , v * oo oo

ro

O

cm

O

OO

O om o oro

O

CM

en

atm

en

a>a>

at

CO

01

CDro

o> LlI o> 0- "72

at > <£. a> LU

GO cr

en «- 3

o>

A

2N4I

NUFACT

O < at or 2 pLl. C£ Q

Z)

00 2-

O ±: Ll <

fc! °2 o<x> oin

_l<

h-O

rRRENT

R

(FRO

O1- Li_ O dgCO

ro .0 Ll CO

c> o 2< o<\] 2 Lt O h1- o ?§ m L

DISTR

JUNCTI

CM Is — o: _i O -1 2 < in

C\j CM m

IxJ or

in 3 O O

V138 3 a
O.I/if

'O.IV P TO P

IOa> (v^VTVM

'c t

FIGURE 53. CIRCUIT FOR MEASURING ft OF 2N4I4 TRANSISTOR
CO

oro

COCO<

\-

CD

Ld

Q_

co

eno

ICO o

CO2 LU < 0_

q: >

i- h- oo £

en

oro»-co 00

CO^ LJ < Q_ Oo

COo

i- o

CD I I I I Om o oo I I l l U

I- CD

if)

-- ro

-- <M

-- CD

A".

:::

<dro ~ "5

CD

in

COLd

_j9O<

CD

Ixl + «" 21

Ld

C£ + CO ^

CD - m

-- sl-

-- ro

CM 8 S

CO

cr

Ixl orZ>O£3

orZ)oLlO

en

Ll

CO

oro

I-co

CO<

en

C\J

oro

Ll<

enoo

h-coIo

»-

Z>

93en

\-coQm

LJ

(T

Z>^2

Ll

Q31S31 1V101 dO %
|7hANALOG VOLTAGE COMPARATOR

SERIES 2

FIGURE 55

*
-2N4I4

Wo 25

FIGURE 56
INDICATOR /AMPLIFIER

SERIES 2

FIGURE 57
ONE - SHOT

SERIES -2A

FIGURE 58
FIGURE 59
FIGURE 60
PPULSE GENERATOR WITH FLIP-FLOP H

SERIES 2

FIGURE 61
rPULSE STRETCHER SERIES 2 1

ALL mANSISTOXS 2N4I4

L°

©2*J 0006000000 °J

FIGURE 62
JUMPf/Z

IN2069

ALL TRANSISTORS /IRE 2H4/4

FIGURE 63
SAMPLER PACKAGE

SERIES 2

ALL TRANSISTORS ARC 2N4I4

ALL DIODES AR€ HB-2
470

2N/302

620

DUAL WRITE PACKAGE

SERIES 2

€20

2M302

2N4/4

470

2H/302

620

ojo O O O O

FIGURE 65
/^AMPLIFIER ' ^ IIS ^

FIGURE 66
ANALOG SWITCH

SERIES

3

FIGURE 67
ANALOG VOLTAGE COMPARATOR SERIES
o O

O

O o AND/OR INVERTER SERIES 3 w
BCD COUNTER

SERIES-3 on-. o o

.00/
DECIMAL DECODER SERIES 3

620

620

620

620

620

620

620

620

620

FIGURE 71
DUAL FLIP-FLOP SERIES 3

FIGURE 72
FIGURE 73
° INDICATOR/ SERIES -3 °

AMPLIFIER

62 K

'/4W

FIGURE 74
OCTAL- HEXADECIMAL

SERIES

DECODER

FIGURE 75
o o ONE-SHOT SERIES-3 °

FIGURE 76
1K, TRIMPOT

FIGURE 77
oo o o o o o o o o|

PULSE GATE SERIES -3

FIGURE 78
o o PULSE GATE DRIVER ° ©

FIGURE 79
o o

PULSE GENERATOR

WIT FF

10-IOOKc

SERIES 3

FIGURE 80
DUAL PULSE GENERATOR SERIES 3

DR435

o o o o o

O O O O Ol

o o o o o oooooooo

12 23

FIGURE 81
JUMPER

FIGURE 82
SERIES 3

ALL TRANSISTORS

ARE 2N4I4

DIODES

HB-2

FIGURE 83
r

DUAL WRITE SERIES 3 ~l

2N4/4-

FIGURE 84

6 U. S. GOVERNMENT PRINTING OFFICE : 1963 O - 680103
I. S. DEPARTMENT OF COMMERCE

Luther II. Hodges, Secretary

NATIONAL BUREAU OF STANDARDS

A. V. Astin, Director THE NATIONAL BUREAU OF STANDARDS

The scope of activities of the National Bureau of Standards at its major laboratories in Washington, DC, and

front cover.

ript the

WASHINGTON, D. C.

Electricity. Resistance and Reactance. Electrochemistry. Electrical Instruments. Magnetic Measurements

Dielectrics. High Voltage.

Metrology. Photometry and Colorimetry. Refractometry. Photographic Research. Length. Engineering Metrology.

Mass and Scale. Volumetry and Densimetry.

Heat. Temperature Physics. Heat Measurements. Cryogenic Physics. Equation of State. Statistical Physics.

Radiation Physics. X-ray. Radioactivity. Radiation Theory. High Energy Radiation. Radiological Equipment.

Nucleonic Instrumentation. Neutron Physics.

Analytical and Inorganic Chemistry. Pure Substances. Spectrochemistry. Solution Chemistry. Standard Refer- ence Materials. Applied Analytical Research. Crystal Chemistry.

Mechanics. Sound. Pressure and Vacuum. Fluid Mechanics. Engineering Mechanics. Rheology. Combustion

Controls. _, Polymers. Macromolecules: Synthesis and Structure Polymer Chemistry. Polymer Physics Polymer Characterisation. Polymer Evaluation and Testing. Applied Polymer Standards and Research. Dental Research.

Metallurgy. Engineering Metallurgy. Microscopy and Diffraction. Metal Reactions. Metal Physics. Electrolysis and Metal Deposition. . Inorganic Solids. Engineering Ceramics. Glass. Solid State Chemistry. Crystal Growth. Physical Properties.

Crystallography.

Building Research. Structural Engineering. Fire Research Mechanical Systems. Organic Building Materials. Codes and Safety Standards. Heat Transfer. Inorganic Building Materials. Metallic Building Materials. Applied Mathematics. Numerical Analysis. Computation. Statistical Engineering. Mathematical Physics. Operations Research. Data Processing Systems. Components and Techniques. Computer Technology. Measurements Automation.

Engineering Applications. Systems Analysis.

Atomic Physics. Spectroscopy. Infrared Spectroscopy. Far Ultraviolet Physics. Solid State Physics. Electron Physics. Atomic Physics. Plasma Spectroscopy.

Instrumentation. Engineering Electronics. Electron Devices. Electronic Instrumentation. Mechanical Instru- ments. Basic Instrumentation. Physical Chemistry. Thermochemistry. Surface Chemistry. Organic Chemistry. Molecular Spectroscopy. Ele- mentary Processes. Mass Spectrometry. Photochemistry and Radiation Chemistry.

Office of Weights and Measures. BOULDER, COLO.

Cryogenic Engineering Laboratory. Cryogenic Equipment. Cryogenic Processes. Properties of Materials. Cryogenic Technical Services. CENTRAL RADIO PROPAGATION LABORATORY

Ionosnhere Research and Propagation. Low Frequency and Very Low Frequency Research. Ionosphere Research PredicUoTservices. Sun-Earth Relationships/ Field Engineering, rtadio Warning Services. Vertical Soundings Research. . Radio Propagation Engineering. Data Reduction Instrumentation. Radio Noise. Tropospheric Measurements.

Tropospheric Analysis. Propagation-Terrain Effects. Radio-Meteorology. Lower Atmosphere Physics.

Radio Systems. Applied Electromagnetic Theory. High Frequency and Very High Frequency Research. Fre- quency Utilization. Modulation Research. Antenna Research. Radiodetermination.

Ipper Atmosphere and Space Physics. Upper Atmosphere and Plasma Physics. High Latitude Ionosphere

Ulhysics. Ionosphere and Exosphere Scatter. Airglow and Aurora. Ionospheric Radio Astronomy.

RADIO STANDARDS LABORATORY

Radio Physics. Radio Broadcast Service. Radio and Microwave Materials. Atomic Frequency and Time-Interval

Standards. Radio Plasma. Millimeter-Wave Research.

Circuit Standards High Frequency Electrical Standards. High Frequency Calibration Services. High Frequency

fmp^ltc^^ ServiceS- Microwave Circuit Standards- Low Frequency Calibrauon

Services. ervices.
NBS