A111D3

NBS

PUBLICATIONS

NBSIR 79-1595

CMOS/SOS Test Patterns for

Process Evaluation and Control:

Annual Report, March 1 to

November 1 , 1 978

Loren W. Linholm

Electron Devices Division

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, D.C. 20234

January 1979

Prepared for U.S. Air Force

-QC—^\ir Force Avionics Laboratory

100 A/right Patternson AFB, Ohio 45433

.U56

79-1595

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NBSIR 79-1595

• *

* CMOS/SOS TEST PATTERNS FOR

PROCESS EVALUATION AND CONTROL:

ANNUAL REPORT, MARCH 1 TO

NOVEMBER 1, 1978

Loren W. Linholm

Electron Devices Division

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, D C. 20234

January 1979

Prepared for U.S. Air Force

Air Force Avionics Laboratory

Wright Patternson AFB, Ohio 45433

/ \

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A {> / ' - i U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary

Jordan J. Baruch, Assistant Secretary for Science and Technology

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director
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TABLE OF CONTENTS

Executive Summary

Obj ective

Approach

NBS-16 Test Pattern Design

Pattern Generator Software Verification.

NBS-16 Description

NBS-16 Evaluation

Cross-Bridge Sheet-Resistor Array, NBS-21

Acknowledgment

Appendix A

Appendix B

Page

1

1

2

2

O

3

4

5

6

11

14

LIST OF FIGURES

Page

1. NBS-16 test pattern. 7

2. Computer plot of NBS-16 ................. 8

3. Computer-generated ploFol NBS-21 . 9

4. Intrachip linewidth variations 10
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CMOS/SOS Test Patterns for Process

Evaluation and Control

ANNUAL REPORT

March 1 to November 1, 1978

Loren W. Linholm

Executive Summary:

The National Bureau of Standards in collaboration with the Jet Propulsion Laboratory, Pasadena, CA and RCA, Somerville, NJ, has designed a CMOS/SOS test pattern, NBS-16, and the necessary measurement techniques.

RCA is required to process one test pattern wafer with each CMOS/SOS

wafer lot being fabricated for the radiation-hardened microprocessor

chip set. Each test pattern wafer is to be tested at NBS and JPL and

recommendations for improvements made to the Air Force Avionics

Laboratory (AFAL) , the Air Force Materials Laboratory (AFML) , and RCA.

A second-generation test pattern will be designed later based on information and experience obtained from the first. To date, the NBS-16

test pattern has been designed, a pattern generator tape has been

delivered to RCA, and the testing hardware and software has been

developed. A simple test pattern, NBS-21, has been designed and

fabricated to verify the compatibility of NBS layout programs with

the RCA pattern generator and also to electrically determine linewidth

variations across a pattern. NBS-16 test wafers are being fabricated

at RCA. A program schedule (AFSC form 103) can be found in Appendix A.

Objective

The objective of this program is to develop process assessment methods

which can be used by an independent source to evaluate the electrical

performance, radiation tolerance, and yield potential of LSI circuits

fabricated with a radiation-hardened silicon gate CMOS/SOS process.

1
Approach

In collaboration with JPL and RCA, NBS has designed a CMOS/SOS test

pattern, NBS-16, and developed the required measurement techniques.

Under AFAL contract, RCA is processing one wafer on NBS-16 with each

Q40S/S0S wafer lot. Each wafer will be tested by NBS and JPL. Recommendations for improvements will be made to AFAL, AFML, and RCA based

on the analysis of test results. By July 1979, a second-generation

test pattern will be designed incorporating the information and

experience gained from the first.

NBS-16 Test Pattern Design:

Prior to the design of NBS-16, a meeting was held with RCA personnel to

carefully review the RCA radiation hardened silicon gate CMOS/SOS process and topological design rules. RCA uses a seven-level mask set

for their radiation-hardened process. This process has nine photolithography steps (see table 1). Two of the masks are used twice.

In the standard RCA process the N-I mask is used for the N- and P+

implants and P-I mask is used for the P- and N+ implants. A list of

the topological design rules and tolerances can be found elsewhere.^

For optimum flexibility, the test pattern mask set is nine levels.

This allows for N+ into N- and P+ into P- implants. It does not require

any additional processing and is fully compatible with RCA production

process. The function of each mask level is described in table 1. The

working photomasks were fabricated by a computer-controlled pattern

generator at RCA.

Pattern Generator Software Verification:

Prior to fabrication of the NBS-16 photomasking, a simple one-level test

pattern, NBS-21, was designed at NBS to check the compatibility of the

^Design Rules, Silicon-Gate CMOS/SOS RCA Solid State Technology

Center, April 15, 1978.

2
Table 1

Photomask Level Functions

Process

Sequence

« Function Mask

Designator

RCA

level

No.

1. Island Definition ISD 8

2. N- Implant N-I (9)

3. P- Implant P-I (4)

4. Poly Definition PLY 3

5. •

f N+ Implant N+ 4

6. P+ Implant P+ 9

7. Contact CNT 5

8. Metal Definition MET 6

9. Passivation PRO 7

I'lBS layout programs with the RCA pattern generator. An HBS-21 tape

which could be read by the pattern generator was sent to RCA and a satisfactory reticle was produced.

NBS-16 Description:

dBS-16 is a square test pattern 250 mils (6.35 mm) on a side. It was designed in English units in order to be compatible with RCA photomask

fabrication. It is divided into seven basic areas as shown in figure 1 Each area can be physically separated, if desired. The functions of

each area are listed in table 2. A computer-generated plot of the actual layout is shown in figure 2.

NBS-16 is being fabricated on 3-in, (76. 2-nun) diameter sapphire wafers.

Approximately 94 sites are available. An RCA TCS-121 test pattern is

being placed in two of the available sites. This pattern is an internal RCA test pattern and contains structures such as a ring oscillator

circuit not found on NBS-16. A detailed description of each structure

in the NBS areas of NBS-16 is provided in Appendix B.

3
Table 2

Device Types on NBS-16

Area Types of Devices

I. Process Parametric

Device Pattern

(NBS)

MOSFETS, cross-bridge

sheet resistors, contact resistors,

capacitors, RCA Gate

Universal Array Cells.

II. Physical Analysis

Pattern (NBS)

Level designators,

alignment marks, ion

beam areas, surface

prof ilometer , etch

structure.

III. Random Fault

Structure I (NBS)

MOSFET arrays.

IV. Random Fault

Structure II (NBS)

Capacitor arrays.

V. Process Parametric

Device (JPL)

MOSFETS, capacitors,

resistors.

VI. Oxide Breakdown

Pattern (JPL)

Capacitor array,

P- substrate.

VII. Oxide Breakdown

Pattern (JPL)

Capacitor array,

N- substrate.

NBS-16 Evaluation:

The NBS portions of NBS-16 are to be evaluated at NBS. Baseline

electrical parameters from the Process Parametric Device Pattern will

be measured. Whore appropriate, statistical averages and wafer maps

will be produced. Random Fault Structure I will be analyzed to determine the suitability of using a logic type MOSFET array as a test

structure for detection of random faults and to determine the fault

density of minimum geometry MOSFET structures. Random Fault Structure

II will be used to determine the density of faults in the gate oxide.

4
The degree of overetch and surface topography will be determined from

the Physical Analysis Pattern at specific chip sites. Information

obtained from these measurements will be sent to AFAL, AFML, and RCA

on a monthly basis. When a wafer has been completely tested at NBS,

it will be sent to JPL for further evaluation.

Cross-Bridge Sheet-Resistor Array, NBS-21:

NBS-21 is a one-level pattern consisting of an 8 by 15 array of identical metal cross-bridge sheet resistors. A computer-generated plot

of the actual chip layout is seen in figure 3. A working photomask

was made from a reticle of this pattern produced by Harry Diamond

Laboratories, Adelphi, MD. Wafers were made at NBS.

Initial evaluation of the NBS-21 array indicates that periodic intrachip variations in linewidth occur and can be measured. Figure 4

illustrates a map of the intrachip linewidth variations.

The linewidth of each of the cross-bridge sheet resistors on a wafer

was measured. There are 120 resistors per chip and 53 chips on a wafer. A map of linewidth variations was obtained for each of the 53

chips. Figure 4 is a point-by-point average of the 53 chip maps. The

standard deviation of each point of the map was about + 1 percent.

It is believed that the intrachip variation in linewidth is a function

of the resolution of the lens in the step and repeat camera used in

fabricating the IX photomasks. After the periodic intrachip variation

in linewidth is known, chip-to-chip and wafer-to-wafer variations in

linewidth can be determined. These are believed to be caused by variables in the photolithographic processing. If specific variables in

the photolithography can be identified by this type of structure, it

will be included on the second-generation test pattern. Further work

is being performed to increase our data base and to measure periodic

or random chip-to-chip and wafer- to-wafer variations.

5
Acknowledgment

The author would like to acknowledge the technical contributions made

by Martin G. Buehler, the computer-aided layout and design efforts of

Dwight A. Maxwell, the assistance in software development from Richard

L. Mattis, and the wafer testing performed by Melvin R. Doggett.

6
II.

Physical

Analysis

Pattern

(NBS)

VI. Oxide Breakdown Pattern,

P- Substrate (JPL)

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Random Fault

Structure I (NBS)

III.

Random Fault

Structure I (NBS)

IV.

Process Parametric Device

Pattern (NBS)

IV.

Process Parametric Device

Pattern (JPL)

Figure 1. NBS-16 test pattern.

7
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Figure 2. Computer plot of NBS-16.

8
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9
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Appendix A

Program Schedule

(AFSC Form 103)

11
PROGRAM

SCHEDULE

SUBSYSTEM

NBS

type

Milestone

AS

OF

Nov

9,

1978

12

AFSC

103

PREVIOUS

EDITIONS

ARE

OBSOLETE
AS

OF

Nov

9,

1978 |

COMPL DATE

>-

QTR

>

U. CN-

>"Cb 0>

OJ

TYPE

Milestone

-

FY 1980

fO

CNFISCAL

YEAR

1979

(A<

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i

s

SUBSYSTEM

NBS

<

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u.

Q

z

0

FISCAL

YEAR

1978

CA<

z

<

SYSTEM

NO,

(PROJ)

z

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Q

z

0

PRIOR SCUED

K

><0z

PROGRAM

MILESTONES

Monthly

Status

Letters

Technical

Report

fDraftl

Technical

Report

(Final!

PROGRAM

SCHEDULE

J - 2 U - <N (*) xn vO 00 O' o CO vn vO X ON

13

AFSC

103

PREVIOUS

EDITIONS

ARE

OBSOLETE.
Appendix B

CMOS/SOS Test Pattern for Process Evaluation

and Control: NBS-16

14
CMOS/SOS Test Pattern For Process Evaluation

and Control: NBS-16

Introduction: This report describes the structures designed by NBS

and included on the NBS-16 test pattern. NBS-16 is illustrated in

Figure B-1.

This report contains a number of figures produced on a computercontrolled plotter. Figure B-2 is a key for identifying the individual

levels. Many structures require a change in only the level position

of the implant mask to form a new device (e.g., P-channel MOSFET vs. N-channel MOSFET). Only one figure has been included in this report

for each basic structure. Similar structures, varying only in the

level of the Implant mask, are grouped in this listing. The figures

show, in each case, the levels associated with the first structure of

the group.

A description of the method used to measure the MOSFET electrical

parameters is found elsewhere [B-1].

15
I. Process Parametric Pattern

Purpose: The process parametric portion of NBS-16 contains structures necessary to evaluate baseline electrical parameters.

Description: The process parametric pattern is laid out in 2 by

N columns of probe pads. The pattern is a square approximately

100 mil (2.54 mm) on a side. Six columns containing 28 structures

are present. The pattern can be probed automatically by a 2 by

10 probe card and computer tester.

Drawing: Figure B-3. (The structure number appears in the upper

left probe pad of each structure.)

List of Structures

1. ' P-channel four-terminal MOSFET

2. N-channel four-terminal MOSFET

a. Description: This device is a conventional MOSFET with

electrical contacts to gate, source, drain, and body. The

gate dimensions are 2.5 by 0.3 mil (0.064 by 0.0076 mm).

b. Parameters determined: Threshold voltage at 1.0 pA, source- to-drain breakdown voltage at 1.0 pA, source-todrain leakage current at 10.0 V, calculated conduction

factor K* , calculated threshold voltage, and the standard

error of estimate of the two calculated parameters.

c. Drawing: Figure B-4.

3. N-channel MOSFET

4. P-channel MOSFET

a. Description: This device is a five-terminal MOSFET with

electrical contacts to gate, source, and drain, and two

contacts to the body. The device is much larger than

Devices 1 and 2 but has approximately the same length- towidth ratio. The gate dimensions are 9.0 by 1.0 mil

(2.3 by 0. 025 mm)

.

b. Parameters determined: Threshold voltage at 1.0 pA,

source-to-drain breakdown voltage at 1.0 pA, source-todrain leakage current at 10.0 V, calculated conduction

16
5.

6 .

7.

8 .

9.

10 . 11 . 12 . 13.

factor K' , calculated threshold voltage, and the standard

error of estimate of the two calculated parameters,

c. Drawing: Figure B-5.

The fifth electrical contact to the body region is made

via an implanted region of opposite dopant concentration

to the body. This may be useful in evaluating the back

channel leakage characteristics of the device.

N-channel closed geometry MOSFET

P-channel closed geometry MOSFET

a. Description: This device is a four- terminal MOSFET with

electrical connection to gate, source, drain, and body.

It is a circular device with the source completely sur- rounded by the gate channel and the gate channel sur- rounded by the drain. The gate channel is "edgeless";

it has a length of 0.3 mil (0.0076 mm).

b. Parameters determined; Threshold voltage at 1.0 pA,

source-to-drain breakdown voltage at 1.0 yA, source-todrain leakage current at 10.0 V, calculated conduction

factor K* , calculated threshold voltage, and the standard

error of estimate of the two calculated parameters.

c. Drawing: Figure B-6.

P- cross-bridge sheet resistor

N- cross-bridge sheet resistor

P+ cross-bridge sheet resistor

N+ cross-bridge sheet resistor

P+ doped poly cross-bridge sheet resistor

N+ doped poly cross-bridge sheet resistor

Metal cross-bridge sheet resistor

a. Description: The cross-bridge sheet resistor is a combination of a van der Pauw sheet resistor and a bridge resistor

[B-2]. The design linewidth is 0.6 mil (0.015 mm).

b. Parameters measured: Sheet resistance and linewidth of

the conducting layer.

c . Drawing : Figure B-7

.

17
14. P- gated cross-bridge sheet resistor

15. N- gated cross-bridge sheet resistor

a. Description: The gated cross-bridge sheet resistor is

similar in geometry to device 7 except that the resistor

is junction isolated in an epi island. The resistor is

defined by a poly silicon gate which is a mask for a further heavy channel stop implant. Electrical contact

is made to the resistor (or channel region), the poly

gate, and the channel stop.

b. Parameters measured: Sheet resistance and linewidth of

the channel region with the gate grounded.

c. Drawing: Figure B-8.

16. Metal to P- contact resistor

17. Metal to N- contact resistor

18. Metal to P+ contact resistor

19. Metal to N+ contact resistor

20. Metal to P+ doped poly contact resistor

21. Metal to N+ doped poly contact resistor

a. Description: The contact resistor is used to measure the

electrical resistance between the metal level and a resistive layer [B-3]. The size of the contact opening is a square 0.4 mil (0.010 mm) on a side. This is the same

size contact opening used on the cross-bridge sheet

resistor.

b. Parameters measured: Contact resistance.

c. Drawing: Figure B-9.

22. P-type MOS capacitor

23. N-type MOS capacitor

a. Description: This structure is a poly-oxide-epi capacitor

with an area of 10.24 mil^ (6.61 x 10”^ mm^) and with an electrical guard ring.

b. Parameters measured: Capacitance per unit area and possibly capacitance vs. voltage characteristics.

c. Drawing: Figure B-10.

18
24. Closed geometry gated diode

a. Description: This device is similar to the closed geometry

MOSFET (device No. 5) except that the gate is extended

beyond the drain region and off the epi island. The

electrical connection to the drain has been removed leaving

electrical connection to the source, body, and gate.

b. Parameters measured: Leakage current caused by bulk and

surface carrier generation.

c. Drawing: Figure B-11.

25. N-channel two-terminal MOSFET

26. P-channel two- terminal MOSFET

a. Description: This structure is a two-terminal MOSFET

with the gate permanently connected to the drain. It is

used as the Internal cell in the Random Fault Structure I MOSFET arrays. It is included here to permit electrical

access to a single cell.

b. Parameters measured: Threshold voltage at 1.0 pA, sourceto-drain breakdown voltage at 1.0 yA, and source-to-drain

leakage current at 10.0 V.

c. Drawing: Figure B-12.

27. Internal cell from RCA Gate Universal Array (GUA)

a. Description: This is an internal cell from the RCA GUA

family and has been included to provide electrical access

to an individual structure used frequently in the RCA GUAs

.

The cell consists of two P-channel MOSFETs and two N-channel

MOSFETs [B-4].

b. Parameters determined: Threshold voltage at 1.0 yA,

source-to-drain breakdown voltage at 1.0 yA, source-todrain leakage current at 10.0 V, calculated conduction

factor K’ , calculated threshold voltage, and the standard error of estimate of the two calculated parameters.

c. Drawing: Figure B-13.

28. Input /Output cell with input protection from RCA GUA

a. Description: This is an input/output cell consisting of

a P-channel and N-channel MOSFET, two diodes, and a 19
resistor [4], The diodes and resistor are arranged so they can be included in input structures or omitted in output

structures. The device on NBS-16 has no components internally connected. Each device is connected to a probe pad

for electrical access.

b. Parameters determined: Threshold voltage at 1.0 pA,

source-to-drain breakdown voltage at 1.0 pA, source-todrain leakage current at 10.0 V, calculated conduction

factor K’ , calculated threshold voltage, and the standard

error of estimate of the two calculated parameters. PN

junction characteristics.

c. Drawing: Figure B-14.

II. Physical Analysis Pattern

Purpose: The physical analysis portion of NBS-16 contains structures which are intended for physical, visual, or beam analysis.

No electrical testing is performed with these structures.

Description: The physical analysis pattern is a square approximately 50 mil (1.27 mm) on a side located in the upper left corner of NBS-16. Mask alignment marks and level designators are also included in this pattern.

Drawing: Figure B-15. (The structure number appears to the left

of each structure.)

List of structures

29. Light-Field RCA alignment marks (Figure B-16)

30. Dark-Field RCA alignment marks (Figure B-17)

31. Mask level designators and critical dimension structures

a. Description: This structure contains mask level designators and critical dimension structures on each level.

The critical dimension structure consists of a pair of

minimum width 2.0-mil (0.051-mm) long parallel lines separated by the width of one line.

20
32.

33.

34.

35.

36.

37.

b. Parameters measured: Linewidth of critical dimensions on the working photomasks.

c. Drawing: Figure B-18.

Overetch structure

a. Description: This structure contains checker board

elements which can be inspected visually to determine

over-etching or underetching for epi definition; polyover-epi definition, metal-over-epi definition, contact

window over epi definition, and contact-window-over-poly

definition.

b. Parameters measured: The degree of over-etching or underetching of critical levels.

c. Drawing: Figure B-19.

P- SIMS area

N- SIMS area

a. Description: This structure is a square 10.0 mil

(0.0254 mm) on a side which can be analyzed by secondary

ion mass spectroscopy.

b. Parameters measured: Impurity atom concentration.

c. Drawing: Figure B-20.

Surface profllometer

a. Description: This structure is a series of parallel

4.0 mil (0.10 mm) long stripes of metal, oxide, epi,

and poly and is intended for use with a surface-profiletype Instrument.

b. Parameters measured: The step height of epi, poly,

metal, and contact window on sapphire and the step

height of poly, contact window, and metal on epi.

c. Drawing: Figure B-21.

NBS Designator "NBS-16'* (Figures B-22 and B-23)

NBS Designator "NBS-16" (Figure 24)

21
III. Random Fault Structure I Purpose: The purpose of this structure is to test the feasibility of using a logic type array to determine the random fault

density of a MOSFET array and determine the location and nature

of any faults detected. The spatial integrity of important

parameters will also be determined.

Description: This structure consists of two 10 by 10 arrays of

P-channel MOSFETs and two 10 by 10 arrays of N-channel MOSFETs.

The arrays are within a 100-mil (2.54-mm) square. The devices

are interconnected such that the drains and gates are common. They are arranged in rows and columns similar to a diode matrix

with source connections to columns and the gate and drain

connections to rows. Each device is electrically isolated from

its neighbor and can be individually tested by addressing the

appropriate row and column probe pads.

Parameters measured: For each MOSFET in the array, threshold

voltage at 1.0 pA, source-to-drain breakdown voltage at 1.0 pA,

source-to-drain leakage current at 10.0 V, and fault location

(e.g., the location of a MOSFET not having reasonable electrical

parameters). Based on the nature of detected faults (shorts

or opens) and location, information regarding the quality of the

metal step coverage, metal bridging and other shorts or opens

in the metal level can be determined.

Drawing: Figure B-25.

IV. Random Fault Structure II

Purpose: The purpose of this structure is to determine the fault

density of gate oxide dielectric breakdown primarily at the

epi island edge.

Description: This structure contains an array of capacitors and

is used to detect metal- to-poly, poly-to-epi, and metal-to-epi

leakage caused by photolithography-induced defects or dielectric

22
breakdown of the gate or field oxide. The array consists of

6,021 capacitors connected in electrically parallel groups of

225, 375, 750, 1500, and 3000. The array is in a 100~

mil (2.54-mm) square and can be probed by a 2 by 10 probe card.

Parameters measured: Metal-to-poly , poly-to-epi, and metal- toepi leakage current as a function of array size.

Drawing: Figure B-26.

References

B-1. Penny, W. M. and Lau, L. , Editors, MOS Integrated Circuits,

pp. 126-129, (van Nostrand Co, New York, 1972).

B-2. Buehler, M. G., Grant, S. D. , and Thurber, W. R. , Bridge and van

der Pauw Sheet Resistors for Characterizing the Line Width of

Conducting Layers, J. Etectrochem. Soc. 125 , 650-654 (1978).

B-3. Buehler, M. G. , Semiconductor Measurement Technology: Microelectronic Test Pattern NBS-3 for Evaluating the ResistivityDopant Density Relationship of Silicon, NBS Special Publication

400-22 (June 1976).

B-4 . Skorup, Gordon E. , SOS COS/MOS Universal Array User's Manual,

Solid State Technology Center, Somerville, NJ, (May 1977).

23
I I I I J !

arr m

\u%-m

vr.%-vm

|Lki

-1 r

[ j L ii -

I !

--

] n

1

Figure B-1. NBS-16 test pattern.
Process

Sequence Function

1 . Island Definition

I 1 T ^ 2 . N- Implant

3. P- Implant

4. Poly Definition

' i\ ^ I

I \

'< 5. N+ Implant

6 . P+ Implant

sssss

? 7. Contact

rrijr’i

\\ {\ 1 Liuu

8 . Metal Definition

9. Passivation

Figure B-2. Level identification key.

25
Figure B-3. NBS-16 process parametric pattern.

26
MIL

0.00

3.00

6.00

9.00

12.00

15.00

"^do‘ ' ' 'a'.do'

TT 6.00 9.00

MIL

Figure B-4. Four-terminal MOSFET.

27
MIL

Vdo' ' ' 'a'.do' s‘.00 9.00

MIL

Figure B-5. MOSFET.

28
MIL

0.00

3.00

6.00

9.00

12.00

15.00

' '

' aWTT 6.00

MIL

9.00

Figure B-6. Closed geometry MOSFET.

29
MIL

MIL

Figure B-7. Cross-bridge sheet resistor.

30
31

Figure

B-8.

Gated

cross-bridge

sheet

resistor.
MIL

O

MIL

Figure B-9. Contact resistor.

32
00*91

00*31

00*6

00*9

00*6

00*0

1IW

Jdo' ' ' '3'.'(ro'"f"^

MIL

Figure B-10. MOS capacitor.

33

*
MIL

0.00

3.00

6.00

9.00

12.00

15.00

o.do'

' ' 'a'.do'

' ' 6.00

hlL

9.00

Figure B-11. Closed geometry gated diode.

34
MIL

3.00

6.00

9.00

12.00

15.00

Figure B-12. Two-terminal MOSFET.

35
MIL

0.00

3.00

6.00

9.00

12.00

15.00

IS

^ !

i

Lhi

-i—

r~ ^ —

IeT

.^:.J ! n

iHri

r-|

r

t

I

»

Wl

L

t

^=1 I

-4

I I —

I

I

Ii

I 1

.do'

' ' 'a'.do'

MIL

TT

Figure B-13. Internal cell from RCA Gate Universal Array.

36
OO'ZI 00*8

lU

00 'T 00*0 {j^

37

igure

B-14.

Input/output

cell

with

Input

protection

from

RCA

GUA.
IS® s

JVl'-I s

F°S

PLY S

31 w s

nsTS

Fiaa s

36

37TE§°11

ccm

c c:d

D era cm

32

Figure B-15. NBS-16 physical analysis pattern.

38
MIL

0.00

3.00

6.00

9.00

12.00

15.00

ll

1 r‘ _ r ll

1

1

i

1

“

I r — ll

! “

11

l,J ui

o'.do'

' ' 's'.dii' e'.oo

MIL

Figure B-16. Light-field RCA alignment marks.

39
MIL

O

U3_

O

• (NJ_

OO• O)'

o

o• (o‘

o

o• m

o

o

r 1

1

$

• 1^ ;I

o.do' ITU

2i

r3F TT 6.00

MIL

Figure B-17. Dark-field RCA alignment marks.

40
MIL

Figure B-18. Mask level designators and critical dimension

structures.

41
MIL

0.00

3.00

6.00

9.00

12.00

15.00

O' ' ' 'a'.do'

TT TIoo

MIL

Figure B-19. Over etch structure.

42
OO'St

OO'Zt

00*6

00*9

OO’E

00*0

IIU

"^do' ' ‘ 'a'.do'

' ' e'.oo

MIL

9.00

Figure B-20. SIMS area.

43
o

o«

c ]

00* e

niu

o

o«

_CSI

o

o

O)

o

o

‘co

o

1^• w

oo« ‘o

00*0

44

Figure

B-21.

Surface

prof

ilotneter

.
MIL

0.00

3.00

6.00

9.00

12.00

15.00

"U 1

I : 4;

M-f-i

l-L-i

o.do*

TT

Figure B-22. Designator NBS45
Figure B-23. Designator 16.

46
o

o

00-t 00*2 00*0

1IW

47

Figure

B-24.

Designator

TCS-139.
N channel N channel

Figure B-25. NBS-16 random fault structure I.

48
Figure B-26. NBS-16 random fault structure II.

49
NBS<114A IR£V. 9-78)

U.S. DEPT. OF COMM.

BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBSIR 79-1595

4. TITLE AND SUBTITLE

CMOS/SOS Test Patterns for Process Evaluation and Control:

Annual Report, March 1 to November 1, 1978

5. Publicaiion Date January 1, 1979

7. AUTHOR(S)

Loren W. Linholm

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, DC 20234

11. Contract/Grant No. MIPR No. FY11758N2026

12. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS csfreer, city, st^te, ziP)

U. S. Air Force

Air Force Avionics Laboratory

Wright Patterson AFB

Ohio, OH 45433

13. Type of Report & Period Covered Annual

15. SUPPLEMENTARY NOTES

[~ 1 Document describes a computer program; SF-185, FIPS Software Summary, is attached.

I 16. ABSTRACT (A 200-word or less factual summary ot moat significant inlormation. If document includes a aignificent bibliography or

literature survey, mention it here.)

The National Bureau of Standards in collaboration with the Jet Propulsion

Laboratory, Pasadena, CA and RCA, Somerville, NJ, has designed a CMOS/SOS test

pattern, NBS-16, and the necessary measurement techniques. RCA is required to

process one test pattern wafer with each CMOS/SOS wafer lot being fabricated for

the radiation hardened microprocessor chip set. Each test pattern is to be

tested at NBS and JPL and recommendations for improvements made to the Air Force

Avionics Laboratory (AFAL) , the Air Force Materials Laboratory (AFML) , and RCA.

A second generation test pattern will be designed later based on information

and experience obtained from the first. To date, the NBS-16 test pattern has

been designed, a pattern generator tape has been delivered to RCA, and the testing hardware and software has been developed. A program schedule and a description and illustration of each test structure are found in the appendices.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name;

aeperated by aemicolons)

CMOS/SOS; process control; process metrology; silicon gate; test patterns; test

structures.

18. AVAILABILITY r^rt Unlimited

For Official Distribution. Do Not Release to NTIS

[~ ] Order From Sup. of Doc., U.S. Government Printing Office, Washington, DC

20402, SD Stock No. SN003-003- L

[Xj Order From National Technical Information Service (NTIS), Springfield, VA, 22161

19. SECURITY CLASS 21. NO. OF

(THIS REPORT) PRINTED PAGES

53

UNCLASSIFIED

20. SECURITY CLASS 22. Price (THIS PAGE)

$ 4.50

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