# Patent

## Title
Oscillator configured to complete an output pulse after inactivation

## Abstract

An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal operates so that the control signal is maintained to complete a last cycle period after an inactivation timing of the oscillator enable signal.

## Background
The present patent application is a Continuation of application Ser. No. 11/030,748, filed Dec. 22, 2004, which has issued as U.S. Pat. No. 7,123,079 on Oct. 17, 2006.


FIELD OF INVENTION
The present invention relates to a voltage generator for boosting a supply voltage; and, more particularly, to a high voltage generator included in a semiconductor memory device for raising a supply voltage to a predetermined level.
DESCRIPTION OF PRIOR ART
Recently, a supply voltage used in a semiconductor memory device becomes lower, but an operating speed of the semiconductor memory device becomes much faster. Thus, the semiconductor memory device boosts a supply voltage to a predetermined level for guaranteeing a stable operation and improves a speed for sensing a data in a unit cell.
For example, in case of a dynamic random access memory (DRAM) of which unit cell is constituted with one capacitor and a transistor, the transistor in the unit cell is usually a NMOS transistor instead of a PMOS transistor because a size of the PMOS transistor is higher than that of the NMOS transistor. However, the NMOS transistor can fast transmit a logic low level data, i.e., ‘0’; but, in case of a logic high level data, i.e., ‘1’, an operating speed of the NMOS transistor is relatively slow because of a threshold voltage Vth. Therefore, for improving the operating speed of the NMOS transistor and reading/writing the logic high level data of which level is generally similar to a supply voltage (VDD) level into a unit cell without a loss as much as a threshold voltage (Vth) level, a high voltage VPP of which level is more the threshold voltage level than the supply voltage level is requested.
The semiconductor memory device usually raises the supply voltage VDD to a predetermined level because a level of the high voltage VPP should be kept more than the supply voltage level.
FIG. 1 is a block diagram showing a conventional high voltage generator used in a conventional semiconductor memory device.
As shown, the conventional high voltage generator includes a high voltage level detector 110, a ring oscillator 120 and a charge pump 130.
In detail, the voltage level detector 110 compares a high voltage VPP, which is outputted and fedback from the charge pump 130, with a reference voltage Vref; and, then, outputs an oscillator enable signal OSCEN having a logic high level “H” to the ring oscillator 120 if a level of the high voltage VPP does not reach on a predetermined voltage level. The ring oscillator 120 receives the oscillator enable signal OSCEN and generates a pumping clock signal OSC in response to the oscillator enable signal OSCEN. If the pumping clock signal OSC is a logic low level “L”, the charge pump 130 precharges a first capacitor C1. Then, if the pumping clock signal OSC is a logic high level “H”, the charge pump 130 generates the high voltage VPP by using the first capacitor C1.
Herein, the ring oscillator 120 includes a delay block constituted with a plurality of inverters. For example, the delay block can have six inverters.
FIG. 2 is a timing diagram describing an operation of the conventional high voltage generator shown in FIG. 1. Further, an operation of the conventional high voltage generator shown in FIG. 1 is described.
If the oscillator enable signal OSCEN is inputted to the ring oscillator 120, the ring oscillator 120 generates the pumping clock signal OSC. Herein, a period of the pumping clock signal OSC is determined by the delay block. If the pumping clock signal OSC becomes a logic high level “H”, a voltage level of a first node node1 which is initially precharged as a supply voltage (VDD) level is boosted up by a precharged first capacitor C1. Then, a boost-up voltage of the first node node1 is transmitted through a first NMOS transistor N1 turned on by a control signal OSC_H. After a predetermined time, if the pumping clock signal OSC becomes a logic low level, first and second PMOS transistors P1 and P2 are turned on and, then, the first capacitor C1 and a second capacitor C2 are precharged.
In the conventional high voltage generator, the ring oscillator 120 normally outputs the pumping clock signal OSC toggled according to a predetermined period. However, referring to FIG. 2, if the oscillator enable signal OSCEN is inactivated, i.e., becomes a logic low level, the last period of the pumping clock signal OSC is not guaranteed. That is, before the ring oscillator 120 is disabled, the charge pump 130 cannot boost up the high voltage VPP to a desired voltage level. Particularly, if there is not guaranteed the last logic high level period of the pumping clock signal OSC, the boost-up voltage of the first node node1 is not fully transmitted through the first NMOS transistor N1 but discharged. As a result, efficiency and duty of the charge pump 130 are decreased.
SUMMARY OF INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device having a high voltage generator for increasing efficiency and duty of a charge pump by guaranteeing an activation period of the charge pump.
In accordance with an aspect of the present invention, there is provided a high voltage generator including a high voltage level detector for comparing a high voltage with a reference voltage and generating an oscillator control signal being a first logic level in response to a comparison result; a clock feedback block for receiving the oscillator control signal and an inverse pumping control signal and keeping an oscillator enable signal in the first logic level for a predetermined period; an oscillator for generating a pumping control signal in response to the oscillator enable signal and outputting the inverse pumping control signal to the clock feedback block, wherein the pumping control signal is periodically toggled; and a charge pumping block for boosting up the high voltage in response to the pumping control signal.
In accordance with another aspect of the present invention, there is provided a method for generating a high voltage including the steps of A) comparing the high voltage with a reference voltage and generating an oscillator control signal being a first logic level in response to a comparison result; B) generating an inverse pumping control signal and keeping an oscillator enable signal in the first logic level for a predetermined period; C) generating a pumping control signal in response to the oscillator enable signal and outputting the inverse pumping control signal to the clock feedback block, wherein the pumping control signal is periodically toggled; and D) boosting up the high voltage in response to the pumping control signal.



BRIEF DESCRIPTION OF DRAWINGS
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram showing a conventional high voltage generator used in a conventional semiconductor memory device;
FIG. 2 is a timing diagram describing an operation of the conventional high voltage generator shown in FIG. 1;
FIG. 3 is a block diagram showing a high voltage generator in a semiconductor memory device in accordance with the present invention; and
FIG. 4 is a timing diagram describing an operation of the high voltage generator shown in FIG. 3.



DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a high voltage generator included in a semiconductor memory device for increasing efficiency and duty of a charge pump according to the present invention will be described in detail referring to the accompanying drawings.
FIG. 3 is a block diagram showing a high voltage generator in a semiconductor memory device in accordance with the present invention.
As shown, the high voltage generator includes a high voltage level detector 310, an oscillator 320, a clock feedback block 340 and a charge pumping block 330.
The high voltage level detector 310 compares a high voltage VPP with a reference voltage Vref and generates an oscillator control signal OSCEN in response to a comparison result. Herein, the oscillator control signal OSCEN becomes a logic high level “H” if the high voltage VPP is under a predetermined level. That is, the oscillator control signal OSCEN outputted from the high voltage level detector 310 becomes a logic low level if the high voltage VPP is higher than a predetermined level of the reference voltage Vref.
The clock feedback block 340 receives the oscillator control signal OSCEN to thereby output an oscillator enable signal ENR to the oscillator 320. In response to the oscillator enable signal ENR, the oscillator 320 generates a pumping control signal OSC. Also, the oscillator 320 outputs an inverse pumping control signal to the clock feedback block 340. Herein, the pumping control signal OSC is periodically toggled. The charge pumping block 330 is for boosting up the high voltage in response to the pumping control signal. If the pumping control signal OSC is a logic low level “L”, the charge pumping block 330 precharges a first capacitor C1. Then, if the pumping control signal OSC is a logic high level “H”, the charge pumping block 330 generates the high voltage VPP by using the first capacitor C1. Further, the oscillator 320 includes a delay block constituted with a plurality of inverters. For example, the delay block can have six inverters. Also, the delay block determines a period of the pumping control signal OSC.
The charge pumping block 330 is the same as a charge pump 130 included in a conventional high voltage generator in their structures. Thus, a detailed description about an internal structure of the charge pumping block 330 is omitted herein.
Further, the clock feedback block 340 includes two NOR gates, each cross-coupled to each other. A first NOR gate receives the oscillator control signal OSCEN and an output signal ‘a’ from a second NOR gate. The second NOR gate receives an output signal ‘b’ from the first NOR gate, an inverse power-up signal pwrup and the inverse pumping control signal OSCB. The clock feedback block 340 further includes a first inverter for inverting the power-up signal pwrup to the second NOR gate.
The oscillator 320 includes a first NOR gate, a delay block, a second inverter and a third inverter. The first NOR gate is for receiving the oscillator enable signal to thereby generate a pulse. The delay block receives an output signal of the first NOR gate in order to feedback the output signal to the first NOR gate. The first inverter receives the pulse outputted from the first NOR gate to thereby generate the inverse pumping control signal to the clock feedback block 340. The second inverter is for receiving the inverse pumping control signal and outputting the pumping control signal to the charge pumping block.
FIG. 4 is a timing diagram describing an operation of the high voltage generator shown in FIG. 3. Furthermore, an operation of the high voltage generator shown in FIG. 3 is described.
If the oscillator enable signal ENR is inputted to the oscillator 320, the oscillator 320 generates the pumping control signal OSC. If the pumping control signal OSC becomes a logic high level “H”, a voltage level of a first node node1 which is initially precharged as a supply voltage (VDD) level is boosted up by a precharged first capacitor C1. Then, a boost-up voltage of the first node node1 is transmitted through a first NMOS transistor N1 turned on by a control signal OSC_H. At this time, a level of the boost-up high voltage VPP is higher than that of a supply voltage VDD. After a predetermined time, if the pumping control signal OSC becomes a logic low level, first and second PMOS transistors P1 and P2 are turned on and, then, the first capacitor C1 and a second capacitor C2 is precharged.
In the high voltage generator in accordance with the present invention, the oscillator 320 normally outputs the pumping control signal OSC having a predetermined period after the oscillator control signal OSCEN is inactivated. Referring to FIG. 4, if the oscillator control signal OSCEN becomes a logic low level, the last period of the pumping control signal OSC is guaranteed because the oscillator enable signal ENR, i.e., the output signal ‘b’ of the first NOR gate included in the clock feedback block 340, is kept in a logic low level during a predetermined time.
In conclusion, the charge pumping block 330 is not directly disabled by the clock feedback block 340 though the high voltage level detector 310 outputs the oscillator control signal OSCEN being a logic level low. That is, the last enable period of the pumping control signal OSC is guaranteed during a half of one period of the pumping control signal OSC. Therefore, before the oscillator 320 is disabled, the charge pumping block 330 can sufficiently boost up the high voltage VPP to a desired voltage level.
According to the present invention, power unnecessarily consumed for generating a high voltage can be suppressed fully. In addition, in a semiconductor memory device receiving a low level supply voltage, an internal high voltage of which level is higher than that of the low level supply voltage can be stably generated. Particularly, the present invention is very useful in a semiconductor device used for a system requiring a low power consumption such as a mobile system.
The present application contains subject matter related to Korean patent application No. 2004-19438, filed in the Korean Patent Office on Mar. 22, 2004, the entire contents of which being incorporated herein by reference.
While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modification may be made without departing from the spirit and scope of the invention as defined in the following claims.

## Claims

1. An oscillator, comprising:
an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled; and
a feedback block for receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal maintains the control signal so as to complete a last cycle period of the control signal after an inactivation timing of the oscillator enable signal.

2. The oscillator as recited in claim 1, wherein the feedback block includes:
a first NOR gate for receiving the oscillator enable signal and outputting the enable signal; and
a second NOR gate, cross-coupled with the first NOR gate, for outputting a pulse to the first NOR gate in response to the enable signal, a power-up signal and the control signal.

3. The oscillator as recited in claim 2, wherein the feedback block further includes a first inverter for inverting the power-up signal.

4. The oscillator as recited in claim 1, wherein the oscillating block includes:
a first NOR gate for receiving the enable signal;
a delay block for receiving an output signal of the first NOR gate in order to feedback the output signal to the first NOR gate; and
a first inverter for receiving the output signal from the first NOR gate to thereby generate the control signal.

5. The oscillator as recited in claim 4, wherein the delay block is constituted with a plurality of inverters.

6. The oscillator as recited in claim 4, wherein the oscillating block further includes a second inverter for inverting the control signal to output an output of the oscillating block.

7. A method for generating an oscillated signal, comprising:
generating a control signal in response to an enable signal, wherein the control signal is periodically toggled; and
receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal maintains the control signal so as to complete a last cycle period of the control signal after an inactivation timing of the oscillator enable signal.

8. An apparatus for generating an oscillated signal in response to an inputted signal, comprising:
an oscillating block for generating the oscillated signal in response to an enable signal, wherein the oscillated signal is maintained to complete a last cycle period of a control signal after the inputted signal is inactivated; and
a feedback block for generating the enable signal using the oscillated signal outputted from the oscillating block in response to the inputted signal and feeding back the enable signal into the oscillating block.

9. The apparatus as recited in claim 8, wherein the enable signal maintains the oscillated signal so the control signal completes the last cycle period after the inactivation of the inputted signal.

10. The apparatus as recited in claim 9, wherein the feedback block includes:
a first NOR gate for receiving the inputted signal to output the enable signal; and
a second NOR gate, cross-coupled with the first NOR gate, for outputting a pulse to the first NOR gate in response to the oscillated signal, a power-up signal and the enable signal.

11. The apparatus as recited in claim 10, wherein the feedback block further includes a first inverter for inverting the power-up signal.

12. The apparatus as recited in claim 8, wherein the oscillating block includes:
a first NOR gate for receiving the enable signal;
a delay block for receiving an output signal of the first NOR gate in order to feedback the output signal to the first NOR gate; and
a first inverter for receiving the output signal from the first NOR gate to thereby generate the oscillated signal.

13. The apparatus as recited in claim 12, wherein the delay block is constituted with a plurality of inverters.

14. The apparatus as recited in claim 12, wherein the oscillating block further includes a second inverter for inverting the oscillated signal to output an output of the oscillating block.