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NASA CASE NO. LAR 13950-1

PRINT FIG. 1 ,_

NOTICE

The invention disclosed in this document resulted from research in aeronautical and

space activities performed under programs of the National Aeronautics and Space

Administration. The invention is owned by NASA and is, therefore, available for licensing

in accordance with the NASA Patent Licensing Regulation (14 Code of Federal

Regulations 1245.2).

To encourage commercial utilization of NASA-owned inventions, it is NASA policy to grant

licenses to commercial concerns. Although NASA encourages nonexclusive licensing to

promote competition and achieve the widest possible utilization, NASA will provide the

necessary incentive to the licensee to achieve early practical application of the invention.

Address inquiries and all applications for license for this invention to NASA Patent

Counsel, Langley Research Center, Code 143, Hampton, Virginia 23665-5225.

Serial No." 07/891,604

06-01-92 LaRC

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NASA Case No. LAR 13950 

AWARDS ABSTRACT 

PRINTER PORT INTERFACE 

A number of methods are available for interfacing to personal 

computers (PC). One method is to interface directly to the PC's internal 

bus. This method requires a special card to be placed inside the PC. 

Another method is to interface through the RS232 serial port. The data 

transfer rate using this method is very slow and the data must be converted 

from serial to parallel. Various other methods exist which require internal 

cards andlor special circuitry within the PC. 

A novel interface device has been designed which converts a 

standard printer port into a general purpose bus so that a number of external 

devices or microprocessor peripheral integrated circuits may be connected to 

a personal computer via the printer port on the personal computer. The 

interface device connects the external device to the personal computer and 

in write mode, receives data from the personal computer, signals the 

external device to accept the information, and sends the data to the external 

device and in read mode signals the external device to provide data, 

receives data from the external device and sends the data in amounts which 

do not exceed the input limits of the printer port to the personal computer. 

Inventors: Jerry H. Tucker Ann B. Yadlowsky 

Address: 15 Cortez Court 1350 20th Street, Apt. B-31 

Hampton, VA 23666 Boulder, CO 80302 

SS: D ss: m 

Employer: NASA - LaRC National Research Council 

Evaluator: Marice K. Morin 

Serial No.: 071891,604 

Filed: June 1, 1992 
SERIAL NO. 07/891,604

FILED: 06-01-92

LAR 13950-1 -1- PATENT APPLICATION

PRINTER PORT INTERFACE

Ori.qin of the Invention

The invention described herein was made by employees of the United

States Government and may be used by and for the Government for

governmental purposes without the payment of any royalties thereon or

therefor.

10 Technical Field of the Invention

15

The present invention relates generally to interface devices, and more

particularly to an interface device which is connected to a printer port on a

personal computer.

Back.qround of the Invention

A number of methods are available for interfacing to personal

computers (PC). One method is to interface directly to the PC's internal

20 bus. This method requires a special card to be placed inside the PC.

Another method is to interface through the RS232 serial port. The data

transfer rate using this method is very slow and the data must be converted

from serial to parallel. Various other methods exist which require internal

cards and/or special circuitry within the PC.

25 It is accordingly an object of the present invention to provide an

interface which converts the printer port on a personal computer to a general

purpose bus.

It is another object of the present invention to provide an interface

which is capable of causing the printer port on a personal computer to

30 emulate a simple 8 bit microprocessor.
5

10

LAR 13950-1 -2- PATENT APPLICATION

It is another object of the present invention to provide an interface

which is capable of connecting many different devices, including

microprocessor peripheral integrated circuits, to a personal computer.

It is another object of the present invention to provide an interface

which does not require additional cards to be installed inside the personal

computer.

It is another object of the present invention to provide bidirectional

data transfer.

It is yet another object of the present invention to accomplish the

foregoing objects in a simple manner.

Additional objects and advantages of the present invention are

apparent from the drawings and specification which follow.

15

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30

Summary of the Invention

According to the present invention, the foregoing and additional

objects are obtained by providing a device which converts a standard printer

port into a general purpose bus so that a number of external devices or

microprocessor peripheral integrated circuits may be connected to a

personal computer via the printer port on the personal computer. The

interface device connects the external device to the personal computer and

in write mode, receives data from the personal computer, signals the

external device to accept the information, and sends the data to the external

device and in read mode signals the external device to provide data,

receives data from the external device and sends the data in amounts which

do not exceed the input limits of the printer port to the personal computer.

The write mode may be accomplished by having the interface device receive

address, data and control information from the personal computer, latch the

address and data on proper output lines, and signal the external device to

accept the information. The read mode may be accomplished by having the
5

LAR 13950-1 -3- PATENT APPLICATION

interface device receive address and control information from the personal

computer, signal the external device to provide data, receive data from the

external device and send the data to the personal computer in amounts

which do not exceed the input limits of the printer port.

Brief Description of the Drawin.qs

10

Fig. 1 is a block diagram showing an embodiment of the present

invention.

Detailed Description of the Invention

15

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30

Fig. 1 shows one embodiment of the invention. In this embodiment

the PC's printer port provides PC DATA consisting of the eight output

terminals 11-18, PC CONTROL OUT consisting of the four output terminals

21-24, and PC CONTROL IN consisting of the five input terminals 31-35.

These signals are sent and received by the printer port under control of

software running on the PC.

The selected embodiment of the invention consists of six components

the CONTROL LATCH, the DECODER, the SELECTOR, the HIGH ADDR

LATCH, the LOW ADDR LATCH, and the DATA LATCH. A device suitable

for use as the CONTROL LATCH, HIGH ADDR LATCH, LOW ADDR

LATCH, and DATA LATCH is a 74LS374. A device suitable for the

DECODER is a 74LS138, and a device suitable for the SELECTOR is a

74LS244. These devices are available from various semiconductor

manufacturers. The CONTROL LATCH 4 has eight data input terminals

connected to PC DATA terminals 11-18, and eight data output terminals 51-

58. The data output terminals are tri-stated unless the OE terminal 6 is "0".

The CLK terminal 7 is connected to PC CONTROL OUT terminal 23. A "0"

to "1" transition on the CLK terminal 7 causes the value of 11-18to be
LAR 13950-1 -4- PATENT APPLICATION

transferred to the output terminals 51-58. The DECODER 8 has eight output

terminals 91-98. When the EN input terminal 10 is a "0" then one of the

outputs 91-98goes to "0". The particular output is determined by the value

applied to input terminals 111-113.The SELECTOR 12 has eight input

5 terminals 131-138. If input terminal 141is a "0" then the value on input

terminals 131-134is gated to the four output terminals 151-154. If input

terminal 142is a "0" then the value on input terminals 135-138is gated to the

four output terminals 151-154.The DATA LATCH 16, the HIGH ADDR

LATCH 17, and the LOW ADDR LATCH 18 are identical to the CONTROL

10 LATCH 4. The eight data input terminals of latches 16, 17, and 18 are

connected to PC DATA 11-18. When the OE input 19 of DATA LATCH 16 is

"0", a "0" to "1" transition on CLK input 20 will cause the value of 11-18to be

transferred to the output terminals 211-218.When the OE input 22 of HIGH

ADDR 17 is "0", a "0" to "1" transition on CLK input 23 will cause the value

15 of 11-18to be transferred to the output terminals 241-248. When the OE input

25 of LOW ADDR LATCH 18 is "0", a "0" to "1" transition on CLK input 26

will cause the value of 11-18to be transferred to the output terminals 271-278.

PC DATA TERMINAL 11is connected directly to PC CONTROL IN terminal

3s. This connection is used to determine if the selected embodiment is

20 present and to identify the printer port to which it is connected.

An external device is connected to the selected embodiment using the

bi-directional data terminals Do-DT,the address terminals Ao-Als,read control

terminal/RD, write control terminal/WR, and various SPARE terminals with

uses that are dependent upon the particular external device. The bi25 directional data terminals Do-D7are connected to lines 131-138of

SELECTOR 12 and lines 211-218of DATA LATCH 16. The address

terminals As-Alsare connected to lines 241-248HIGH ADDR LATCH 17 and

address terminals Ao-A_,are connected to lines 271-278of LOW ADDR

LATCH 18. The read control terminal/RD is connected to line 57of

30 CONTROL LATCH 4, and the write control terminal/WR is connected to line
5

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LAR 13950-1 -5- PATENT APPLICATION

58 of CONTROL LATCH 4. In this embodiment the PC CONTROL OUT

terminal 21, line 58 of CONTROL LATCH 4, and lines 96-9e of DECODER 8

are all SPARE terminals with uses that can be defined to accommodate a

particular application.

The two modes of operation for the invention are read and write. The

function of the embodiment of the invention during the write operation is to

transform information received from the PC's printer port to sixteen bits of

address, eight bits of data, and a write pulse which will be accepted by an

external device. The write operation consists of 23 steps. Steps 1-6

describe the output of the low eight bits of a sixteen bit address. Steps 7-12

describe the output of the high 8 bits of the address, and steps 13-23

describes the output of the eight bits of data.

Step 1: The PC outputs a value of "1" to 11, and a value of "0" to 12 and 13.

This will be used to force 92 to "0" prior to clocking LOW ADDR LATCH 18.

Step 2: The PC outputs a value of "1" to 22. This disables the DECODER 8

and causes its outputs 91-9e to assume a value of "1". At the same time the

PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".

Step 3: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value of "001"

that was output to 13, 12, and 11 in Step 1 above to be transferred to the

CONTROL LATCH outputs 51-53, which are connected to DECODER 8

inputs 111-113.

Step 4: The PC outputs the low byte of a 16 bit address to 11-18.

Step 5: The PC outputs a "0" to 22. This enables the DECODER 8. The

value "001" that was transferred to the DECODER inputs 111-113 in Step 3

above causes the DECODER output 92 and thus the LOW ADDR LATCH

clock input 26 to assume a value of "0".

Step 6: The PC outputs a value of "1" to DECODER enable pin 22. This

disables the DECODER so that the DECODER output 92 changes from "0"
LAR 13950-1 -6- PATENT APPLICATION

to "1". Since 92 is connected to LOW ADDR LATCH clock input 26, the low

byte of address that was placed on 11-1e in Step 4 is latched to LOW

ADDRESS LATCH outputs 271-278 .

Step 7: The PC outputs a value of "0" to PC DATA terminals 11-13. This will

5 be used force 91 to "0" prior to clocking HIGH ADDR LATCH 17.

Step 8: The PC outputs a value of "1" to 22. This disables the DECODER 8

and causes its outputs 91-98 to assume a value of "1". At the same time the

PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".

10 Step 9: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value of "000"

that was output to 13, 12, and 11 in Step 7 above to be transferred to the

CONTROL LATCH outputs 51-53 which are connected to DECODER inputs

111-113.

15 Step 10: The PC outputs the high byte of a 16 bit address to 11-18.

Step 11: The PC outputs a "0" to 22. This enables the DECODER 8. The

value "000" that was transferred to the DECODER inputs 111-113 in Step 9

above causes the DECODER output 91 and thus the HIGH ADDR LATCH

clock input 23 to assume a value of "0".

20 Step 12: The PC outputs a value of "1" to DECODER enable pin 22. This

disables the DECODER 8 so that the DECODER output 91 changes from "0"

to "1". Since the DECODER output 91 is connected to HIGH ADDR LATCH

clock input 23, the high byte of address that was placed on 11-1e in Step 10

is latched to HIGH ADDRESS LATCH outputs 241-24 e.

25 Step 13: The PC outputs a value of "0" to 13-15, a value of "1" to 12, and a

value of "0" to 11.

Step 14: The PC outputs a value of "1" to 22. This disables the DECODER

8 and causes its outputs 91-98 to assume a value of "1". At the same time

the PC also outputs a value of "0" to 2_. This insures that the CONTROL

30 LATCH 4 clock input 7 is a "0".
5

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25

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LAR 13950-1 -7- PATENT APPLICATION

Step 15: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value of

"00010" that was output to 15- 11 in Step 13 above to be transferred to the

CONTROL LATCH outputs 5_-51.

Step 16: The PC outputs the data to terminals 11-18.

Step 17: The PC outputs a "0" to 22. The value of "010" that was

transferred to the DECODER inputs 111-113 in Step 15 above causes the

DECODER output 93 and thus the DATA LATCH clock input 20 to assume a

value of "0".

Step 18: The PC outputs a value of "1" to DECODER enable pin 22. This

disables the DECODER so that the DECODER output 93 changes from "0"

to "1". Since 93 is connected to DATA LATCH clock input 20 the data byte

that was placed on 11-1e in Step 16 is latched to DATA LATCH outputs 211-

218.

Step 19: The PC outputs a value of "0" to 1e. This will be used to activate

the/WR terminal by forcing it to "0".

Step 20: The PC outputs a value of "1" to 22. This disables the DECODER

8 and causes its outputs 91-98 to assume a value of "1". At the same time

the PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".

Step 21 : The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value of "0"

that was output to 18 in Step 19 above to be transferred to the CONTROL

LATCH output 5e which is connected to the/WR terminal.

Step 22: The PC outputs a value of "1" to 18, 1s, and 14. This will be used

to raise/WR to a "1" and to disable the output of latches 16, 17, and 18.

Step 21: The PC outputs a value of "1" to 22. This disables the DECODER

8 and causes its outputs 91-98 to assume a value of "1". At the same time

the PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".
LAR 13950-1 -8- PATENT APPLICATION

Step 23: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value of "1"

that was output to 14, ls, and 18 in Step 22 above to be transferred to the

CONTROL LATCH outputs 54, 55, and 58. The "1" on 54 disables the LOW

5 ADDR LATCH 18 and HIGH ADDR LATCH 17. The "1" on 55 disables the

DATA LATCH 16. The "1" on 58 causes the/WR terminal to return to a

value of "1"

The read process consists of fourteen steps. The output of the low

eight bits and high eight bit of the address is described in step 1. The

10 procedure for reading eight bits of data four bits at a time is described in

steps 2-14.

Step 1: The PC outputs a 16 bit address using the same procedure outlined

in Steps 1-12 of the write process described above.

Step 2: The PC outputs a value of "1" on terminals 1s and 13, and outputs a

15 value of "0" on terminals 11, 12, 14, and 17. The value of "100" on 13-11 will

be used to select D4-D7, which are connected to SELECTOR inputs 13s-138.

The "0" on 14 will be used to enable the HIGH ADDRESS LATCH outputs

241-248 and LOW ADDRESS LATCH outputs 271-278. The "1" on 1s will be

used to disable DATA LATCH outputs 211-218. The "0" on 17 will be used to

20 activate the/RD terminal.

Step 3: The PC outputs a value of "1" to 22. This disables the DECODER 8

and causes its outputs 9t-98 to assume a value of "1". At the same time the

PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".

25 Step 4: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value that was

output in Step 2 above to be transferred to the corresponding outputs of

CONTROL LATCH 4.

Step 5: The PC outputs a value of "0" to 22 which enables the DECODER 8.

30 The value of "100" that was transferred to DECODER inputs 113-111 in Step
5

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LAR 13950-1 -9- PATENT APPLICATION

4 above causes the DECODER output 9s and thus SELECTOR input 142 to

assume a value of "0". This causes the D4-D7 values on SELECTOR inputs

135-138 to be gated to SELECTOR outputs 151-154 and thus PC CONTROL

IN terminals 31-34.

Step 6: The PC reads the data values D4-D7 on PC CONTROL IN terminals

31-34.

Step 7: The PC outputs a value of "0" on terminal 13, and outputs a value of

"1" on terminals 11, and 12. The value of "011" on 13-11 will be used to

select D0-D3, which are connected to SELECTOR inputs 131-134.

Step 8: The PC outputs a value of "1" to 22. This disables the DECODER 8

and causes its outputs 91-9e to assume a value of "1". At the same time the

PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".

Step 9: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the value that was

output in Step 7 above to be transferred to the corresponding outputs of

CONTROL LATCH 4.

Step 10: The PC outputs a value of "0" to 22 which enables the DECODER

8. The value of "01 1" that was transferred to DECODER inputs 113-111 in

Step 9 above causes the DECODER output 94 and thus SELECTOR input

141 to assume a value of "0". This causes the D0-D3 values on SELECTOR

inputs 131-134 to be gated to SELECTOR outputs 151-154 and thus PC

CONTROL IN terminals 31-34.

Step 11" The PC reads the data D0-D3 values on PC CONTROL IN

terminals 31-34.

Step 12: The PC outputs a "1" on terminals 14and 17. The "1" on 17 will be

used to raise the/RD line to a "1". The "1" on 14 will be used to disable the

HIGH ADDR LATCH 17 and the LOW ADDR LATCH 18.

Step 13: The PC outputs a value of "1" to 22. This disables the DECODER

8 and causes its outputs 91-9e to assume a value of "1". At the same time
LAR 13950-1 -10- PATENT APPLICATION

the PC also outputs a value of "0" to 23. This insures that the CONTROL

LATCH 4 clock input 7 is a "0".

Step 14: The PC outputs a value of "1" to 23 and a value of "0" to 24. This

clocks and enables the CONTROL LATCH 4 and causes the "1" that was

5 output to 14 and 17in Step 12 above to be transferred to outputs 54 and 57 of

CONTROL LATCH 4. The "1" on 54 is connected to enable inputs 22 and

25 and thus disables HIGH ADDR LATCH 17 and LOW ADDR LATCH 18.

Since 5_,is connected to the/RD terminal the/RD terminal goes to "1".

What is claimed is:
LAR 13950-1

//

PRINTER PORT INTERFACE

PATENT APPLICATION

Abstract of the Disclosure

5

10

15

A printer port interface is provided which converts the printer port on a

personal computer to a general purpose bus so that a number of external

devices or microprocessor peripheral integrated circuits may be connected to

a personal computer via the printer port on the personal computer. This

interface enables the printer port to emulate a simple 8 bit microprocessor.

The interface device connects the external device to the personal computer

and in write mode, receives data from the personal computer, signals the

external device to accept the information, and sends the data to the external

device and in read mode signals the external device to provide data,

receives data from the external device and sends the data in amounts which

do not exceed the input limits of the printer port to the personal computer.
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