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                                                                  EXHIBIT 10.16

*CERTAIN INFORMATION WITHIN THIS EXHIBIT HAS BEEN OMITTED AND THE NON-PUBLIC
INFORMATION HAS BEEN FILED SEPARATELY WITH THE SEC. CONFIDENTIAL TREATMENT HAS
BEEN REQUESTED WITH RESPECT TO THE OMITTED PORTIONS.


                                                                    CONFIDENTIAL



                               MOSYS-VIRAGE LOGIC
                           MEMORANDUM OF UNDERSTANDING
                              FOR JOINTLY DEVELOPED
                     1T-SRAM(TM) TECHNOLOGY MEMORY COMPILERS



PURPOSE

        To establish a relationship between MoSys Incorporated (MoSys) and
Virage Logic Corporation (Virage) to jointly develop and market 1T-SRAM
technology memory compilers in order to speed proliferation of the MoSys 1T-SRAM
technology and Virage memory compiler technology.

        Following the signature of this MOU both MoSys and Virage will use best
efforts to conclude a definitive agreement within 60 days of the signature of
this MOU.

TERM

        Agreement to have a 3 year duration unless terminated by either party
giving the other 90 days written notice.

PRODUCT

        MoSys and Virage shall jointly develop a multi-megabit 1T-SRAM compiler
for an initial foundry and process. The specification of the compiler shall be
as per the attached specification to be updated by mutual agreement.

        MoSys and Virage shall engineer the 1T-SRAM compiler such that instances
generated include BIST, redundancy and fuse programming to ensure high yield and
density. MoSys and Virage shall provide the plans for all DFT planned; including
but not limited to, BIST, diagnostics, etc. MoSys and Virage to determine before
project start on which parameter to optimize the compilers: low power, speed,
area or any combination of the above factors into one or more compilers.

        The schedule for the joint compiler development project shall be
developed jointly by MoSys and Virage. The current date for the start of the
development is slated to be July 1, 1999. Front-end views would then be
available 6 weeks after project start. The GDS availability date is to be
determined during the schedule development.

        Following this initial joint compiler development MoSys and Virage may
agree to develop additional compilers for further foundries and/or processes.


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BUSINESS

        Potential compiler customers of MoSys and Virage can be characterized in
one of three ways: Foundry Users, ASIC Vendors, or semiconductor Integrated
Device Manufacturers (IDMs). The Foundry User is the fabless IC or Systems
Company that goes direct to a licensed Foundry with GDS2 to have the silicon
fabricated. Although a relationship with Foundries will be important in order to
initially develop compilers for their processes and market the results to their
customers, the compilers would not normally be sold to the Foundries themselves.

        The business models, and therefore pricing, for each of these customers
is potentially different. However it is expected to set the same pricing for
ASIC vendors and IDMs, resulting in a simpler compiler pricing structure. All
Foundries, ASIC vendors and IDMs must have a valid 1T-SRAM base technology
license direct from MoSys, who will retain all royalties from that license.

        Any potential 1T-SRAM compiler customer shall be engaged by either
company to determine the need of the customer and determine what course of
action is to be taken to meet and exceed the customers' needs. To that end,
there are four potential engagement scenarios with customers:

        1) Licensing of the 1T-SRAM base technology,

        2) Custom instance development or stand alone chip development,

        3) Instance production using the jointly developed compilers,

        4) Licensing of the Jointly developed compilers themselves.

        In the case of scenarios 1 &2, MoSys shall determine the customers needs
and execute the business with that customer and retain all revenues derived from
such business. MoSys has the sole discretion of directly licensing its 1T-SRAM
technology to its direct customers (Scenarios #1&2).

        In the case of scenarios 3&4, either MoSys or Virage will take the lead
position in determining the customers needs and driving the business with that
customer. In these cases the revenue derived from this business with the
customer will be split between MoSys and Virage as specified in the pricing
section of this agreement. This agreement shall establish the licensing of the
jointly developed compilers incorporating Virage's Compiler Technology and MoSys
1T-SRAM Technology to both companies solely for the purposes of selling the
jointly developed compilers and instances generated from the jointly developed
compilers to customers. Neither MoSys nor Virage may use each other's technology
for any other purpose. The Partner Company takes a secondary role in providing
the product and/or service to the customer in both of the aforementioned



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scenarios 3&4. The ability for the Partner Company to move from a secondary to
primary role in any scenario is only allowed by joint agreement.

        MoSys and Virage will cooperate in Joint selling activities in order to
locate an initial source of NRE fees to help fund development of the compiler
through direct funding of the compiler development or the purchase of a number
of instances. If possible, the first compiler will be developed with common
design rules to allow foundry reuse. MoSys and Virage shall also cooperate on
development of the test chip and silicon validation report with the first
customer. MoSys and Virage shall migrate the developed compiler to additional
foundries based on customer demand.

PRICING

        Although initial pricing is given below, it is expected that pricing
will have to be updated regularly based on the response from the market. MoSys
and Virage will jointly review and, if necessary, amend this pricing by mutual
agreement on a quarterly basis.

        All compiler or compiled instance revenues gained from the jointly
developed compiler products covered by this agreement will be split 50% to MoSys
and 50% to Virage. The pricing below is for the compiler only and does not
include the 1T-SRAM technology license from MoSys, which will require an
additional royalty, together with a license fee from the foundry.

ASIC VENDORS AND IDMS

        Unlimited Compiler License Fee ***.

        Can be converted at customer request to an initial license fee plus
non-capped royalty to at least reach the *** mark. However, both MoSys and
Virage to agree all ASIC Vendor and IDM business proposals prior to customer
commitment.

COMPILERS FOR FOUNDRY USERS

        Unlimited Compiler Site License Fee ***.

        Additional Compiler BIST option Fee ***.

        Compiler royalty (additional to MoSys technology license royalty): MoSys
will assist Virage's negotiations with the foundry to participate in the normal
library EP pool business model royalty. The discount schedule presented in Table
I shall be used in setting discounted pricing for MoSys/Virage products to
prospective customers and applies to MoSys/Virage products only.



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        Any MoSys or Virage specific products included in a deal with a customer
shall not be included in the volume calculation for the purposes of utilizing
Table 1. Any discount in excess of the published discount schedule in Table I to
be extended to any prospective customer is to be agreed by both MoSys and Virage
before being offered.

COMPILED INSTANCES FOR FOUNDRY USERS

        Unlimited worldwide Instance License Fee ***.

        Compiler royalty (additional to MoSys technology license royalty): MoSys
will assist Virage's negotiations with the foundry to participate in the normal
library IP pool business model royalty. The discount schedule presented in Table
I shall be used in setting discounted pricing for MoSys/Virage products to
prospective customers and applies to MoSys/Virage products only.

        Any MoSys or Virage specific products included in a deal with a customer
shall not be included in the volume calculation for the purposes of utilizing
Table 1. Any discount in excess of the published discount schedule in Table I to
be extended to any prospective customer is to be agreed by both MoSys and Virage
before being offered.

TABLE I - VOLUME DISCOUNT TABLE (APPLIES TO COT PRODUCT ONLY)



<TABLE>
<CAPTION>
               VOLUME (LIST PRICE)                        DISCOUNT
               -------------------                        --------
<S>                                                        <C>
                    ***                                     ***

                    ***                                     ***

                    ***                                     ***

                    ***                                     ***

                    ***                                     ***

                    ***                                     ***
</TABLE>


MAINTENANCE AND SUPPORT

        The customer maintenance revenues shall be split 50% MoSys - 50% Virage
as per the agreement that MoSys will answer the physical layout issues resulting
from design rule changes and Virage will answer recharacterization issues,
specific compiler technology issues, EDA models and updates, and will act as the
first line of support to all customers of products borne from this agreement. If
either party finds that this split is not equitable and does not at least cover
the cost of the support provided, the split shall be renegotiated.



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        The maintenance to be charged to the customers shall be 20% of the
compiler list price per year for ASIC and IDM customers and 15% of the list
price per year for Foundry User customers.

MARKETING

        MoSys and Virage agree to perform joint marketing activities to promote
the relationship established by this agreement. The activities shall include,
but not be limited to, the following;

        a) A Joint press release that announces the established partnership,
published after signature of this MOU by both parties,

        b) Joint sales activities to establish the first customer, that will
find the NRE of the first compiler, and also subsequent customers to proliferate
the 1T-SRAM compiler products,

        c) A jointly authored white paper discussing the 1T-SRAM compiler
technology and the Virage compiler technology, and the advantages of both in one
product,

        d) Quarterly technology reviews to inform each party of subsequent
technology developments that could lead to the modification of the product
established under this agreement, or to additional products jointly developed by
the parties,

        e) Advertisement of the compiler in the list of off-the-shelf components
by both MoSys and Virage, including published datasheets to be used by both
companies in the selling of the compiler



<TABLE>
<S>                                     <C>
MOSYS INCORPORATED  /s/ FU-CHIEH HSU    VIRAGE LOGIC CORPORATION  /s/ ADAM KABLANIAN
                   -----------------                             -------------------


Date:  7/1/99                           Date:  6/29/99
     ---------------------------            ---------------------------



Fu-Chieh Hsu                           Adam Kablanian
Chairman, President & CEO              President & CEO
</TABLE>



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                     1T-SRAM COMPILER OUTLINE SPECIFICATION


DELIVERABLES

        -   Data sheet

        -   Verilog model (back-annotatable o/p delays)

        -   VHDL (VITAL95) model (back-annotatable o/p delays)

        -   Synopsys synthesis model

        -   Synopsys static timing (Motive) model

        -   Synopsys timing model

        -   Synopsys power model

        -   Cadence place-and-route abstract (LEF)

        -   Avant! place-and-route Frame view abstract

        -   GDSII

        -   Spice netlist for LVS

PARAMETERS & LIMITS

        -   Word widths: 16, 32, 64 or 128 bits with 8-bit byte enables

        -   Size: 4K, 8K, 16K, 32K, 64K, 128K, 256K, 512K, IM or 2M words
            provided total memory size is between 512K and 32M bits

        -   Pipeline or Flow-Through

        -   Late-write options (To be defined)

        -   Some aspect-ratio control (To be defined)

        -   BIST option (To be defined)

OTHER ITEMS

        -   Include Redundancy

        -   Include Scan support





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        -   Define timing characterization process

        -   Define test silicon process








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