I

'"CAU Of * NBS SPECIAL PUBLICATION 400-

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

emiconductor Measurement lecnnology:

i

Metrology for Submicrometer

Devices and Circuits

ai^TiiiiiW"""
NATIONAL BUREAU OF STANDARDS

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the Institute for Computer Sciences and Technology.

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HATIONAL BUREAU OF STANDARDS

tlBRARY

Semiconductor Measurement Technology:

JUN ^ 5 1980

Metrology for Submicrometer

Devices and Circuits

(oo

.U57

Ko, 4oo- (q I

1980

W. Murray Bullis

Electron Devices Division

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, D.C. 20234

U.S. DEPARTMENT OF COMMERCE, Philip M. Klutznick, Secretary

Luther H. Hodges, Jr., Deputy Secretary

Jordan J. Baruch, Assistant Secretary for Productivity , Technology and Innovation

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director

Issued June 1980
Library of Congress Catalog Card Number: 80-600054

National Bureau of Standards Special Publication 400—61

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-61,41 pages (June 1980) CODEN; XNBSAV

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1980

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402

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(Add 25 percent additional for other than U.S. mailing)
Table of Contents

Page

List of Figures iv

List of Tables vi

Abstract 1

1 . Introduction 1

2. Dimensional Metrology 3

3. Materials Characterization «. 17

4. Other Metrology 25

5. Summary > 27

6. Acknowledgments 30

7. References 30

iii
LIST OF FIGURES

Page •

1. Schematic representation of the cross-sectional material profile

of a transparent line in an opaque background and the corresponding

optical image profile of a line scan from one side to the other . . 2 )

2. Line-edge image profiles for limiting conditions of microscope \ operation 2

3. Optical image profiles of two adjacent ideal clear lines in an * opaque field 2

4. Scanning photometric microscope for measurements in transmitted ' light 4

'

5. Comparison of experimental and calculated edge profiles for anti- ^' reflecting chromium on glass 5

6. Patterns for linewidth and associated measurements on an artifact \ designed for use in evaluating and calibrating linewidth measurement systems 6

7. Scanning electron micrograph of three nominally 3-ym wide antireflecting chromium lines on a glass substrate 6

8. Outline drawing of a three-level cross-bridge sheet-resistor test

structure 8

9. One cell of test pattern NBS-21, an 8 by 15 array of single-level

cross-bridge sheet-resistor test structures 10

10. Linewidth variation determined with test pattern NBS-21 11

11. Outline drawing of three-level production-compatible electrical

alignment test structure 12

*

12. Vector maps of contact-window-to-channel alignment at 62 sites on

a 2-in. diameter silicon wafer 14

13. Photomicrograph of a portion of a 2-ym wide single-level, crossbridge sheet-resistor test structure fabricated in aluminum on an oxidized silicon substrate showing asymmetries in the voltage-tap ; geometry 14:

14. A TO- 100 header with attached test chip on the left and temperaturesensing diode on the right 16

15. Photograph of a 2-in. diameter silicon wafer mounted in variable

temperature prober 181

iv
Page

16. Wafer maps of gold acceptor density and diode junction leakage

current showing correlation between these quantities 20

17. Effect of diameter of analyzed area on detection limit of various

analytical methods 20

18. Model of the Si-Si02 interface on thermally oxidized silicon

wafers as derived from sputter Auger studies 21

19. Planar four-probe test structure for measurement of bulk resistivity 21

20. Circuit for obtaining the dopant profile in the gate region of a p-channel enhancement-mode MOSFET 22

21. Dopant profiles of boron diffusion, phosphorus implant, boron implant, boron-doped bulk, and phosphorus-doped bulk 22

22. Idealized curve of leakage current of a p'^n gated diode at a fixed value of reverse bias Vj^ as a function of gate voltage Vq . . 24

23. Outline drawing of integrated gated-diode test structure with output MOSFET electrometer and MOSFET reset switch 24

24. Wafer map of generation lifetime as determined from measurements

on integrated gated-diode test structures fabricated with a pchannel, self-aligned polysilicon gate technology 26

25. Dose deposited in a 100-nm thick oxide under l-jjm thick aluminum

and 50 0-nm thick resist as a function of the dose in the resist

for 15- and 25-keV electrons 26

26. Experimental set-up for 370-MHz scanning acoustic microscope ... 28

27. Scanning acoustic micrograph of a section of a silicon-on-sapphire

integrated circuit which illustrates structural detail under the

metallization stripes 28

28. Capacitance-voltage profiles of a phosphorus-implanted silicon

wafer characteristic of thermally annealed and laser-annealed areas

of the wafer, illustrating highly doped surface region produced by

laser annealing 28

29. Charge collection scanning electron micrographs of as-implanted,

thermally annealed, and laser-annealed regions of a silicon wafer

implanted with a boron to a dose of about 10^^ cm"^ 29

30. Outline drawings of random fault testers included on test pattern

NBS-16 29

v
LIST OF TABLES

Page

1 . Results of Linewidth Measurements Made with a Variety of Optical

Microscope Measurement Systems 4

2. Selected Properties of Single-Crystal Silicon 16

vi
Semiaonduotov Measurement Teehnology:

METROLOGY FOR SUBMICROMETER DEVICES AND CIRCUITS*

W. Murray Bui lis

National Bureau of Standards

Washington, DC 20234

The raetrological requirements of semiconductor microelectronics,

j always challenging, are made even more stringent by the trend

[ toward submicrometer devices and structures. This comes about not

1 only because of the obvious demands associated with the smaller

I feature sizes of circuit elements but also because of the attendant

j requirements for more efficient design verification aids, computer

ij simulations, and process validation and control techniques and

j because of the concurrent trend toward larger die and package

I sizes. This paper examines the types of metro logical requirements

I associated with submicrometer devices and structures, summarizes

|j the present state of the art in selected critical areas of metroljj ogy, and reviews current research and development efforts on ad-

\ vanced measurement technology, especially those at the National

I Bureau of Standards.

! Key Words — Dimensional metrology; electronics; integrated circuits; materials characterization; measurement methods; microelec-

^1 tronics; micros tructures; semiconductors.

I

1 . INTRODUCTION

I

' The semiconductor device field has long provided many challenges for the

metrologist. The purity, perfection, and cleanness required of the materi-

^ als, the tiny dimensions of the devices, and the multidisciplinary nature of

' the field have all contributed to the metrological difficulties. Although a great deal of progress has been made over the years, the speed with which the

semiconductor field develops continually provides new challenges. The trend

toward submicrometer devices is the latest in a long series of such developments. The more stringent metrological requirements associated with microstructure geometries arise not only because of the obvious demands associated

!l with the smaller feature sizes of circuit elements but also because of the

l' attendant requirements for more efficient design verification aids, computer

simulations, and process validation and control techniques, and because of

the concurrent trends toward larger die and package sizes.

Two major types of metrology — dimensional metrology and materials characterization — are required to provide the basic understanding of submicrometer structures and to interpret device and circuit characteristics. In addition, ancillary techniques associated with analysis of process chemicals,

control of process steps, and characterization of packages are also needed.

[( In this paper, we examine these three types of metrological requirements.

* This report is an edited and expanded version of an invited paper presented

at the Conference, Microcircuit Engineering '79 — Microstructure Fabrication, Aachen, West Germany, September 27, 1979.

1
b. Limit of coherent illumination.

Figure 1. Schematic representation of Figure 2. Line-edge image profiles

the cross-sectional material profile for limiting conditions of microscope

of a transparent line in an opaque operation. (After Nyyssonen [1])

background and the corresponding optical image profile of a line scan from one side to the other. (After Nyyssonen [ 1 ] )

DISTANCE

Figure 3. Optical image profiles (solid curves) of two adjacent ideal clear

lines in an opaque field (dashed lines). The line spacing is X3 - (or X4

- X2) and the width of the lines is X2 - x-j (or X4 - X3 ) . The true threshhold is located a distance A (in a direction toward zero intensity) from the

threshold assumed in making the measurement. (After Nyyssonen and Jerke [4]

)

2
stumnarize the present state of the art in selected metrology areas which bear

on these requirements, and review current research and development efforts

on advanced measurement technology for the semiconductor industry, with em- phasis on efforts at the National Bureau of Standards. Techniques for a wide

variety of dimensional measurements are considered in section 2. Materials

characterization methods are reviewed in section 3. Several other types of

measurements are mentioned briefly in section 4.

2. DIMENSIONAL METROLOGY

Dimensional measurements are, of course, critical for submicrome ter technology. Both line-spacing and linewidth measurements are necessary to characterize circuit geometries and to quantify pattern registration, surface distortion, and surface stability. Dimensional measurements are also necessary

to determine layer thicknesses, flatness and finish of surfaces, and characteristics of particulates on surfaces or in fluids. At the present time,

techniques for these measurements on the micrometer and submicrometer scales

are in an embryonic state.

Dimensional measurements on semiconductor device and integrated circuit patterns are generally carried out with the use of a measurement system based on

an optical microscope. Measurements of this type require interpretation of an optical image of the line or space as shown schematically in figure 1 [1] . The threshold on the optical image profile is the value of transmittance or reflectance which corresponds to the actual material edge. This value depends on the nature of the particular optical system employed for the measurement. For example, the thresholds for abrupt edges viewed by incoherent

and coherent illumination, shown in figure 2, are significantly different.

In the limit of incoherent illumination, the threshold T^, is:

T = 0.5 (I + I ) , c 0 M

where the transmittance or reflectance is denoted as Iq on one side of the

edge and as Ij^^ on the other as shown in figure 2 [1] . In the limit of co- herent illumination, the threshold is:

T = 0.2 5 (I^ + I. + 2 yil cos (J)) , c O M O M

^

where 4) is the optical phase difference between light rays passing through

the materials on the two sides of the line edge. The degree of coherence of

the illumination in an optical microscope can be varied by changing the ratio

of the numerical apertures of the objective and condenser lenses [3].

For pitch, or line-spacing, measurements errors due to improper selection of

threshold cancel so that accurate measurements between edges of the same type

on features can be made without accurate knowledge of the actual threshold,

but for width measurements such errors add rather than cancel. This is illustrated in figure 3 [4] . If the image profiles of the two lines are as- sumed identical, the measured distance between the thresholds assumed for the

left-hand edges of the lines is given by:

P = (x^ + A) - (x^ + A) = x^ - x^ ,

3
Table 1 — Results of Linewidth Measurements Made with a Variety of Optical Microscope Measurement Systems. (After Nyyssonen and Jerke

[4] )

Type of System

Linewidth (Micrometers)

Spaces Lines

Photometric

Filar Eyepiece

Filar Eyepiece

TV Filar

Filar Eyepiece

Shearing Eyepiece

Filar Eyepiece

Filar Eyepiece

Shearing Eyepiece

TV-Image Scanning

Shearing Eyepiece

Photometric

0 .98

1.05

1 .44

0.85

1.12

0.81

1 .55

1.16

0.73

0.85

0 .93

1.00

3.13

3.17

3.71

3.05

3.36

2.96

3.68

3.57

2 .82

2.93

2 .93

3.10

0 .87

0.73

0.66

1.14

0.71

0.98

0.94

0.66

1 .04

1 .06

0.99

0.75

2.87

2.68

2.78

3.00

2 .71

2.98

2.88

2.66

3 .05

2.83

2 .95

2.80

Figure 4. Scanning photometric microscope for measurements in transmitted

light. (Photo by W. R. Smallwood)

4
where A is the distance between the assumed and actual thresholds as shown in

the figure. The measured distance P is seen to be the true distance between

similar points on the two lines. On the other hand, the measured width of

the left hand line is given by:

M 2 1 2 1 The measured width differs from the true width by twice the distance between

the assumed and actual thresholds. Therefore, for accurate measurements of

feature widths, it is necessary to establish the correct threshold. Various

microscope measurement systems, such as those equipped with filar, image shearing, or video eyepieces, have different edge detection thresholds [5,4] . It is

well known that apparent differences of a quarter of a micrometer or more are observed when measuring widths, lines, or spaces with different systems [6]

Typical results of linewidth measurements made by a variety of optical systems

on the same nominal 1- and 3-ym wide lines and spaces on antiref lectivechromium photomask-like artifacts are listed in table 1 [4] . Each system was adjusted for pitch or line scale only.

Concern with such errors increased substantially about five years ago when it

became apparent that feature sizes for integrated circuits would soon reach

the submicrometer range [7] . Since that time, the problem of optical mea- surement of linewidths has been under investigation at NBS. Procedures have

been established to permit measurements with an accuracy of about 50 nm on

lines or spaces as narrow as 50 0 nm in thin layers (that is, layers less than

400 nm thick for measurements in transmitted light and layers less than 200 nm thick for measurements in reflected light) [3] . To do this the theory of

the optical microscope was extended to take into account the spatial co- herence of the illumination [3] and optical phase changes at material interfaces [8] . Experimental measurements were made on an automated scanning photometric microscope, pictured in figure 4. The numerical aperture of the objective lens is 0.9 and that of the condenser lens is 0.6 to provide effectively

coherent illumination and to minimize flare light. For measurements in transmitted light, illumination is provided by a tungsten-halogen source, filtered

to provide radiation sharply peaked at 530 nm."^ In operation, the test object

is moved so that the optical system is always used axially. The signal is detected with a photomultiplier through a narrow line slit with an effective

width of 0.13 }jm at the object plane. The microscope incorporates a novel piezoflex stage, developed at NBS, to provide smooth motion in the horizontal

plane [9] and automatic piezo-controlled focusing to avoid dimensional changes

in the image due to changes in lens-to-specimen distance. Comparisons between

experimental measurements of the image edge profiles and the calculated profiles show extremely good agreement as can be seen by the example in figure 5

[8] . To make such comparisons, the experimental profile (solid line) and calculated profile (open circles) are simply superimposed by matching at the

threshold. In this example, Iq is taken as 0.0 1 and (}) is taken as 90 deg.

Procedures have been worked out for measurement of linewidths in these ranges

with the use of many of the types of linewidth measuring systems available in

the field. To facilitate calibration of these instruments, NBS plans to issue

+ A 0.5-W krypton laser source and a somewhat more sensitive photomultiplierdetector system are required for measurements in reflected light [8]

5
1.0

0.5

-1 0 +1

DISTANCE \^m\

Figure 5. Comparison of experimental (solid curve) and calculated

(open circles) edge profiles for

antiref lecting chromium on glass.

(After Nyyssonen [8] )

Dia3H 56109

l-l- -l-l-H-l-l-l-l-l

1

1 D133H SBIBg

c -I I I- -l-c-l-l-l-l-lD

Dia3H SBTBg

E H"HiihHiiH«l-E-|iiHHH"Hiih

F

G

D 1 3 3 H

r-l hH||K1

Figure 6. Patterns for linewidth

and associated measurements on an artifact designed for use in evaluating and calibrating linewidth

measurement systems.

Figure 7. Scanning electron micrograph of three nominally 3-ym wide

antiref lecting chromium lines on a glass substrate. (Micrograph by W. J.

Keery)

6
I as standard reference materials a series of artifacts which contain a variety

! of patterns as shown in figure 6. Four sets of lines and spaces in the 0.5-

to 10-ym range (rows A-D) comprise the basic patterns [10]. Other patterns

are included to permit line-spacing calibrations (row E), setting of edge detection thresholds and line-to-space ratios on automatic measuring instruments (row F), and testing for lead screw errors (row G) . Each artifact contains 8 such patterns, one of which is calibrated and certified by NBS. The

first of these artifacts, which is fabricated in an antiref lecting chromium

film on a glass substrate, is designed for use in measuring opaque photomasks

in transmitted illumination. Together with the associated measurement procedures [11], this artifact provides the user with the capability of evaluating

I his own measurement procedures and calibrating his measuring instrument.

At the present time, the principal limitation on the accuracy of linewidth

measurements is the shape and uniformity of the material edge being measured;

the measurement technique must be extended to account for both the slope and

waviness of the edge which are evident in the scanning electron micrograph in

figure 7. In addition, the theory must be extended to permit accurate measurements of lines and spaces in thicker layers. Both these extensions are essential for measurements on very large scale integrated circuit wafers or

,, chips.

i;

j Optical techniques are not suitable for measurement of the widths of lines or spaces less than about 500 nm wide. For such features an electron probe must

be employed. In making the electron-probe measurements, it is also necessary

to consider the characteristics of the material edge profile. Preliminary

, comparisons between electron probe and optical measurements of widths of

lines in the 1- to 10-ym range have yielded generally satisfactory results

for opaque lines in a clear field, but not for clear lines in an opaque field

[12]. These preliminary electron probe measurements were made with a conveni tional scanning electron microscope adapted for the purpose; a first-order

model of the edge profile was used to interpret the results. Additional work

to address the difficulties encountered with the clear lines is now being

carried out at NBS. A specially designed electron microscope designated the

microlength calibrating electron probe (MCEP), with integral polarization in-

|i terferometer [13], is being used for the electron-probe measurements, and

more sophisticated edge profile models are being developed.

I Line-spacing determinations, as noted earlier, are somewhat less demanding;

, calibrations down to about a micrometer can presently be performed by NBS on suitable artifacts supplied by the user [14] . Nevertheless, calibrations of

line spacings in the submicrometer range will probably require the use of an electron probe such as the MCEP.

} Line-spacing measurements can be used to establish registration of patterns

and distortion characteristics of substrate surfaces. It is projected that

'i pattern registration will be required to an accuracy of less than 10 nm.

j Measurements to such an accuracy over distances of 1 cm or more are presently

[! not practical. Among the critical factors are the maintenance of smooth

translation of the test specimen and retention of focus of the measuring

probe. This latter factor requires control of the lens-to-specimen spacing

in the submicrometer range. An advanced class of high quality x-y stages

which will achieve these characteristics over translational motions of 1 cm

7
Figure 8. Outline drawing of a three-level cross-bridge sheet-resistor test

structure. The three levels shown are channel (heavy outline), contact

window (solid), and metal (light outline). A single-level cross-bridge can also be fabricated in metal; in this form the channel and metal levels are combined and the contact window level is omitted. (After Carver et dl.

[15] )

8
and more is currently under development at NBS in connection with studies of

surface topography. Such stages will be very important in the extension of

optical techniques for measurement of line spacings to determine pattern registration and surface distortion.

Microelectronic test structures, suitably replicated across the surface of a wafer, permit the measurement of geometrical quantities electrically. Microelectronic test structures are device-like structures fabricated in the same

way as integrated circuits. Two major types of microelectronic test structures are of interest for dimensional measurements. The cross-bridge test

structure is used to determine the width and sheet resistance of conducting

regions [15] . One form of this structure is depicted in figure 8.* Analysis

has shown that the cross-type sheet resistor is a symmetrical van der Pauw

structure which yields a value of sheet resistance Rg(VDP) which is independent of the structure size [15]:

R (VDP) =-^^ , s In R I where I is the current passed from contact I-| to contact I2 and AV is the

potential difference between contacts V-j and Ideally, the effective

width of the bridge region, W, is given by the product of the design distance

between potential contacts on the bridge portion of the structure, L, and the

ratio of the sheet resistance as measured by the cross portion of the structure to the sheet resistance as measured by the bridge portion [17]

* W = R (VDP)L T , s

* AV

where I is the current passed from contact I-, to contact I9 and AV is the

* * potential difference between contacts V^ and Measurements of W can be made

with a resolution of about 10 nm.

If cross-bridge structures are replicated across the entire wafer, it is possible to make a map of the linewidth variations. For example, test pattern

NBS-21 is a single-level pattern formed in the metal over an oxide by repeating the 5- by 5-mm cell shown in figure 9 [18] . The upper map in figure 10

shows the width of the lower-left structure in each cell. Denser symbols represent wider values of linewidth. It can be seen that the width variation is

somewhat random in nature. The program which generated this wafer map was designed to interpolate between actual data points which appear at every fourth

symbol [19] . Consequently, the fine structure within the cell cannot be observed on the map. When data from all the structures in a given row are plotted as in the lower chart of the figure, it can be seen that there is a variation in linewidth that is periodic with the cell dimension in addition to random variations. The periodic variation can be attributed to the system used

to fabricate the photomask; variations from cell to cell in the linewidth at a given point in the cell matrix can be attributed to the photolithography asso-

* Other forms of this structure have been reported in the literature; see,

for example, Wahl, F. E., and Perloff, D. S., Techniques for the Evaluation

and Display of VLSI Process Uniformity, Proc. Microelectronics Measurement

Technology Seminar, San Jose, California, February 6-7, 1979, pp. 17-26.

9
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0.00 10.30 20.60 30.90 41.20 51-50 61.80 72.10 B2.40 92.70 103.00 113.30 123.50 133.90 144.20 1S4.S0 MIL

175-10 IBS. 40 195.70

Figure 9. One cell of test pattern NBS-2 1 , an 8 by 15 array of single-level

cross-bridge sheet-resistor test structures. (After Linholm [18])

I

10
a. Wafer map of the linewidth of the lower left structure in each cell. The

number of structures in each width interval is shown in the table at the

left.

DISTANCE ACROSS WAFER (MIL)

b. Linewidth of the structures along one line (denoted by arrows in a) of

test pattern NBS-2 1 as a function of position on the wafer.

Figure 10. Linewidth variation determined with test pattern NBS-2 1 . (After

Linholm and Buehler [20])

11
Figure 11. Outline drawing of three-level production-compatible electrical

alignment test structure. The form shown in the main drawing is for use in

determining alignment between the diffusion (channel) and contact window

levels; the modifications shown in the insets are made to allow determination

of the alignment between the diffusion and metal levels. (After Russell et

at. [21]) i

I 12
elated with printing the pattern, to variations in etching the pattern, or to

both [ 18,20]

The production-compatible electrical alignment test structure* shown in

figure 11 provides a means for direct electrical determination of the alignment between the channel (diffusion) and contact-window mask levels (main

drawing) or between the channel and metal levels (insets) [21,22]. When

there is perfect alignment between the two mask levels, resistance R-] is

equal to resistance R2 and resistance R3 is equal to resistance R4. Misplacements of the upper level with respect to the lower in the x- and ydirections are given by

and

al = -

L R^ - R^

y 2 R

'

where resistance R and the length L are defined in figure 11. When fabricated into a test pattern with 6-iJm minimum-linewidth design rules, this

structure can resolve misregistration of the order of 100 nm. If the structure is replicated across the wafer, it is possible to make complete wafer

maps of the misalignment as illustrated in figure 12. In these maps, the

length of the vector indicates the displacement; the distance scale is given

at the bottom. Under ideal conditions, these maps can be analyzed to extract

the trans lational, rotational, and radial components [23] , leaving a residual

which may result from process-induced wafer distortion, from variations in

the test structure, or from both.

Both the cross-bridge and electrical alignment test structures are potentiometric in nature. In order to provide accurate results, these structures must

be fabricated in layers with uniform resistivity, and the active regions must

have uniform cross sections. Deviation from these conditions, asymmetries in

the voltage-tap geometry (as shown in the photomicrograph of figure 13), and

This style of production-compatible electrical alignment test structure is

patterned after that reported by Thomas, D. R. , and Pearson, R. D., [An

Electrical Photolithographic Alignment Monitor, Digest of Papers, Govt. Microcircuit Applications Conf . , Orlando, Florida, November 1974, pp. 196-

197.] Another style of production-compatible electrical alignment test

structure has been reported by Stemp, I. J., Nicholas, K. H. , and Brockman,

H. E. [Automatic Measurement and Analysis of Misalignments in Integrated

Circuit Processing, Proc. Conf. Microcircuit Engineering '78, Cambridge

(1978)] and by Wahl, F. E., and Perloff, D. S. [loc. cit.] Perloff has described a single-mask electrical alignment tester intended primarily for

evaluation of mask aligners and projection printers [A van der Pauw Resistor

Structure for Determining Mask Superposition Errors in Semiconductor Wafers,

Solid-state Electronics 2^_, 1013-1018 ( 1978)]. In utilizing a productioncompatible electrical alignment test structure similar to the one pictured

in figure 11, Perloff adds a second sheet resistor perpendicular to the

first to account for the possibility that the width of the potentiometer

bars may depend on direction [Wahl, F. E., and Perloff, D. S. , loc, cit.].

13
I 1 I 1 5 Mm 5 MTi

a. Original data (Device 15.1, Wafer b. Residual displacements after re17). moval of translational and rotational components.

Figure 12. Vector maps of contact-window-to-channel alignment at 52 sites on

a 2-in. diameter silicon wafer. The position of the dot represents the

location of the test structure on the wafer, and the length and direction of

the line correspond to the length (as given by the dimensional scale below

the map) and direction of the displacement. (After Carver et at. [15])

Figure 13. Photomicrograph of a portion of a 2-)jm wide single- level,

cross-bridge sheet-resistor test structure fabricated in aluminum on an oxidized silicon substrate showing asymmetries in the voltage-tap geometry

(arrows). (Photomicrograph by T. J. Russell and W. J. Keery)

.

i

14
any source of distortion in the current lines (which may be caused, for example, by shunting at the voltage taps or crowding at the current contacts) are

i all potential sources of error in these measurements. While these error

I sources do not appear to be very serious for structures fabricated in geomej tries of 6-um or larger, they are expected to become quite significant for

j structures fabricated with micrometer and submicrometer geometries.

j Another dimension which must be controlled carefully is the thickness of

various films and layers which comprise a microstructure. Control of the

j thickness of oxide or other insulator films is particularly critical for sub-

' micrometer devices. For example, for MOS integrated circuits, it is expected

that gate oxides will be the order of 50 nm thick with a uniformity and accu- racy requirement of about 1%. At the present time, there are no standards

I for film thickness or step height when either quantity is required to have a

1 value in the range between 10 and 1000 nm. NBS does offer a limited stepjt height calibration service based on stylus profilometry [24] ; present mea- surement uncertainty is as high as 2 0% for thicknesses of about 50 nm. During 1980, NBS is planning to issue a standard reference material for oxi deli film thickness measurements by ellipsometry. This standard will consist of a

j thermally oxidized silicon wafer; the oxide thickness will be between 50 and

^ 100 nm. Although a reproducibility of 1 to 2% is expected for ellipsometry

I measurements on these standards, there is no assurance that the ellipsometric

I values will agree with values obtained by stylus profilometry. In fact, one

of the major reasons for the large uncertainty in thickness calibrations is

the disagreement between values deduced from the three commonly used measurement techniques: stylus profilometry, ellipsometry, and interf erometry . Be-

, cause these differences exceed the resolution capabilities of each of the

f techniques, they are usually attributed to test specimen characteristics

'I (such as design, uniformity, and stability), to inadequate models of the mea- surement techniques, and to differences in the material parameters to which

I the individual measurement techniques respond. Intercomparison of these

three thickness measurement techniques on the scale appropriate for microstructures would be a major research project.

j. Stylus techniques and interferometry are also utilized in measurements of

, surface finish and flatness. In addition, light scattering techniques are

I I also employed. A principal problem in connection with stylus measurements

of surface topography is the smoothness and planarity of the stage which

' moves either the specimen or the stylus. The previously mentioned high-

[ quality x-y stages are essential if stylus techniques are to be utilized to

determine surface topography in regimes appropriate for microstructures.

i The final dimensional measurement area to be considered relates to particulates which may appear in fluids or on surfaces. Both light scattering and

, microscopical techniques are utilized in sizing and counting such particles.

Standard procedures do not exist for sizing particles smaller than 5 ym.

Sizing and counting particles smaller than 10 to 25 ym remains more an art

j than a science. Comparisons between various techniques are being made by

I Subcommittee 10 (Process Chemicals) of ASTM Commmittee F-1 on Electronics

with increasing success. Work on particulates was also undertaken in the

fall of 1979 by a subcommittee (Testing of Process Chemicals for Semiconductor Technology) of DIN Committee NMP 221 on Testing of Materials for Semiconductor Technology. Extension of these various techniques to the submicrome15
Table 2 — Selected Properties of Single-Crystal Silicon, (After ref . [32]

)

Current Capabilities Requirements

Property Czochralski Float Zoned for VLSI

Resistivity n-type (P), Q,'cm 1-40 1-300 100-400

Resistivity w-type (Sb), Q-cm 0.005-10 0.0002-0.02

Resistivity p-type (B), Q,'cm 0 .005-50 1-300 100-400

Resistivity gradient (four-probe) % 5-10 20 <1

Resistivity microsegregation, % 10-15 20-50 <1

Minority carrier lifetime, ys 30-300 50-500 300-1000

Oxygen, ppma 5-15 Not Uniform and

detected controlled

Carbon, ppma 1-5 0.1-1 0.1

Heavy-metal impurities, ppba 1 0.01 0.001

Figure 14. A TO- 100 header with attached test chip (quadrant 1 of test pattern NBS-3) on the left [A] and temperature-sensing diode on the right [B]

The devices are mounted to gold-plated regions on a thin sapphire slab to

provide thermal contact but electrical isolation.

16
ter regime, essential for controlling particulate contamination in the fabrication of microstructures, is a major undertaking which has not yet been adequately addressed. The NBS Center for Mechanical Engineering and Process

Technology has undertaken a basic research effort in wave optics which re- sponds to a portion of the problem. Among the results expected from this

long range project is extension of the theoretical basis for scattering of

light by particles and fibers to the regime where the size of the scatterer

is near the wavelength of light.

3. MATERIALS CHARACTERIZATION

A wide range of techniques is available for characterizing the physical,

electrical, and optical properties of semiconducting and other electronic

materials. The available techniques have been summarized briefly in a number

of recent reviews [25-30] . Standard test procedures for many techniques are under development both in Germany (by DIN Committee NMP 221) and in the

United States (by ASTM Committee F-1) [31].

Semiconductor characterization for microstructures is made more difficult by

the greater demands for control and uniformity of the chemical and defect

properties of the materials, by the necessity for analyzing for distributions

of dopant and trace impurities in ever smaller volumes, and by the necessity

for characterizing interfacial and surface regions. The present state of the

art of characterization techniques with respect to their application to characterization of microstructures has been recently considered in some detail

by the Panel on Thin Film Microstructure Science and Technology <jf the Solid

State Sciences Conunittee of the National Academy of Sciences [32]. As an example of the problems encountered, consider some of the projected requirements for single crystal silicon substrates to be used in very large scale

integrated circuits listed in table 2, extracted from the Panel's report.

The demonstrated reproducibility of the four-probe method for measuring re- sistivity in the 100 to 400 Q'cm range is +5% [33], much larger than the 1%

uniformity required on both macro and micro scales. The situation is not as bleak as it might appear at first glance however, because the large scatter

obtained in the inter laboratory comparative experiments is attributable partly to nonuniformities in the test specimens; reproducibility of +2% was obtained on homogeneous specimens of lower resisitivity.

The control of both oxygen and carbon impurities in the silicon crystal appears to be essential. Fully satisfactory methods to test for these impurities are not yet available; much greater understanding of the nature of these

impurities in the silicon lattice will be required before satisfactory methods can be developed.

Reduction of heavy metal contamination is necessary to achieve the high lifetimes required. Deep level transient spectroscopy and other deep level measurement techniques are widely used in detecting heavy metal impurities [34]

Use of these techniques requires formation of a junction diode or MOS capacitor such as those in the first quadrant of test pattern NBS-3 [35] shown

mounted on the header in figure 14. Generally the measurements are made on devices individually packaged together with a temperature sensor, such as the

small silicon diode shown mounted on the header to the right of the test

17
18
chip, which adds time and complexity to the specimen preparation. NBS has

developed a variable temperature wafer prober pictured in figure 15 for use in making deep level measurements on unscribed wafers [36] . With this instrument, it is possible to make wafer maps of the density of the deep level

impurities and to compare the density distribution with maps of other parameI ters such as leakage current or carrier lifetime [37]. Typical maps [19] are reproduced in figure 16. NBS has also undertaken to conduct an informal inter laboratory comparison of various deep level measurement techniques. In

j this comparative study, two well-characterized gold-doped silicon gated diodes are being circulated among interested participating laboratories.

Although electrical measurements, such as Hall effect or transient capacitance measurements, can in special cases provide information about the identity of certain impurities in semiconductors, physical analysis techniques

jl are generally recognized as being required for adequate identification of

! impurities. Generally speaking, the sensitivity of the various beam tech-

:i niques is reduced as the sampling area is decreased as shown in figure 17,

f also taken from the report of the Micros tructures Panel [38] . No techniques

are available which have part-per-million atomic sensitivities in sampling

areas of the order of 1 ym or less in diameter. Development of standards and

inter laboratory comparisons to provide estimates of the reproducibility of

these techniques in their conventional ranges are only just getting underway

in ASTM Committee E-42 on Surface Analysis. An indication of the current

state of the art is provided by the results of a preliminary study of the ion

microprobe mass analysis (IMMA) technique recently carried out for NBS.

These results suggest that the repeatability of this technique when measuring

phosphorus implants in silicon over a period of about a week is the order of

10% [39] . This variation may also be due principally to microinhomogeneities

in the material as noted earlier in regard to resistivity measurements.

Although these techniques, with the exception of IMMA (or secondary ion mass spectrometry, SIMS), are not well suited to profiling impurities in semiconductors, they have proved extremely valuable in compositional studies of interfaces. For example, through very careful analysis of Auger electron spectroscopy (AES), taking into account electron escape depth, ion beam mixing,

and electron stimulated desorption considerations, the Electron Spectroscopy

Group at Stanford has developed the model for the silicon/silicon dioxide interface shown in figure 18 [40] . These experiments also took advantage of

the fact that AES can provide information on the chemical state of certain

species. Additional information on the chemical state is available from

, x-ray photoelectron spectroscopy. Results of such measurements demonstrate

that the transition region between silicon and silicon dioxide which contains

partial oxides of silicon is very narrow [41].

Microelectronic test structures can also be used to determine material characteristics. Some years ago Krausse used a matrix array of aluminum contacts

to determine the resistivity uniformity of a wafer by spreading resistance

measurements [42] . Bulk resistivity can be measured with the use of the planar four-probe square array shown in figure 19 [43] . The use of junction diodes and MOS capacitors for making deep level measurements has already been

mentioned; these structures can also be used to determine dopant profiles

from incremental capacitance-voltage (C-V) measurements, usually at 1 MHz

[44] . Dopant-profile measurements can be made by dc techniques if a four19
(a) (b)

Figure 16. Wafer maps of gold acceptor density (a) and diode junction leakage current (b) showing correlation between these quantities. The maps show

five equal ranges; the darkest symbol denotes the highest range. The gold

acceptor density varies from 1.9 to 7.6 x 10^-^ cm"-^, and the leakage current

varies from 0.26 to 1.05 nA. (After Koyama [37])

EFFECT OF DIAMETER OF ANALYZED AREA

ON DETECTION LIMIT

100 _,

10 100 1000 1 10 100 1000 1

I 1 1 I Angstroms microns cm

DIAMETER

Figure 17. Effect of diameter of analyzed area on detection limit of various

analytical methods. (After Larrabee [38], courtesy of Texas Instruments Incorporated)

20
Figure 18. Model of the Si-Si02 interface on thermally oxidized silicon

wafers as derived from sputter Auger studies. (After Helms et at. [40])

a.

4.75 mil 121 /im

Photomicrograph of overall structure including probe pads.

b. Detail of one of the four contact

region.

] COLLECTOR

EMITTER

BASE

I 1 OXIDE

ALUMINUM

GOLD -H25/imh^

c. Schematic cross section of the planar square array four-probe resistor

test structure (scaled in horizontal direction only).

Figure 19. Planar four-probe test structure for measurement of bulk resistivity. (After Buehler and Thurber [43])

21
Figure 20. Circuit for obtaining the dopant profile in the gate region of

p-channel enhancement-mode MOSFET. (After Buehler [45]

)

DISTANCE \Nm (Mm)

Figure 21. Dopant profiles of boron diffusion (a), phosphorus implant (b),

boron implant (c), boron-doped bulk (d) and (f), and phosphorus-doped bulk

(e). The dips in the profiles to the left of the 3 A line are artifacts of

the measurement; dopant density values measured in this region do not repre

sent the true profile. (After Buehler [46]

)

22
terminal enhancement-mode MOSFET is employed [45,46]. This structure and its

i associated test circuit are shown in figure 20. The device is operated in

the linear current region. Ideally, both the depletion width and the dopant

density can be obtained from high-speed dc measurements made on a conventional wafer prober. As the gate-source voltage Ygg is changed, the source- drain current is held constant by adjusting the source-body voltage Vgg.

i The depletion width is given by:

i e X dV^„

' W = ^ ° SB

I o GS

and the dopant density at this position is given by:

i N (W ) = o / SB

mm 2 1,2

q e X \dV^^

s o \ GS

where Eg and are the dielectric constants of silicon and silicon dioxide, respectively, Xq is the oxide thickness, and q is the electronic

charge. Figure 21 shows a selection of profile measurements made with the

MOSFET profiler. Like the rf (CV) method, this method cannot provide information at depths beyond the depletion depth associated with voltage breakdown

in the silicon or for distances between the surface (or the junction) and the

zero-bias depletion depth. The latter limitation may limit application of

these techniques for measurement of dopant profiles in very thin layers as might be found in many submicrometer devices.

The gated diode is a powerful tool for determining the magnitude and origin

of leakage currents [47] . As shown in figure 22, the device is sensitive to

currents in various portions of microelectronic device structures, depending

on the gate voltage. Because of the difficulty of measuring the very small

currents in the very high impedance reverse-biased diode, this device has not

been widely utilized. However, by adding integral circuitry, including a MOSFET source-follower output amplifier as shown in figure 23, the measurements can be made rapidly with ordinary dc wafer-probing equipment [48,49]

An example of such measurements is the wafer map of generation lifetime shown

in figure 24; here the denser symbols relate to shorter lifetimes. It must

be emphasized that careful design and accurate modeling are required to in- sure that the integrated test structure is measuring the desired quantities

and is not dominated by parasitics [50] . Also, it should be observed that

reducing critical dimensions of either integrated or discrete test structures

to submicrometer dimensions requires design and modeling efforts very similar

( to those employed in making submicrometer integrated circuits.

The reduction in lateral dimensions is generally accompanied by some reduc-

\ tion of the vertical dimension which adds to metrological difficulties. For

example, semiconducting layers become fully depleted at very small voltages,

which complicates the interpretation of electrical measurements as alluded to

previously. Hot-carrier effects, which are encountered because of the very

j large electric fields which appear across thin insulating and depleted semiI conducting layers, must also be taken into account in interpreting electrical

' measurements. The interpretation of beam analysis methods is also complicated when measurements are made in very thin layers. For example, ion beam

23
• INVERSION »-

J

DEPLETION

Ig Igg

ACCUMULATION

Vtx

GATE VOLTAGE Ve

Figure 22. Idealized curve of leakage current of a p'^n gated diode at

a fixed value of reverse bias Vj^ as a function of gate voltage Vq. The

dashed curves in the insets at the top schematically illustrate the spatial

extent of the depletion region. The current components are Ig, the generation current in the depletion region under the metallurgical junction; Ig,

the surface current generated by interface states under the gate; and Igg/ the

generation current in the depletion region under the gate. The voltage Vrpj^ | is the extrapolated threshold voltage. (After Carver and Buehler [49])

Vs

GATED

DIODE

^

SOURCE/DRAIN

H] POLY SILICON

^

SUBSTRATE

CONTACT

METAL

Vg - DIODE GATE BUS

(Dr - RESET TRANSISTOR GATE BUS

Vr - RESET TRANSISTOR DRAIN BUS

Vb - ELECTROMETER DRAIN BUS

Vq - ELECTROMETER OUTPUT PAD

Vs - COMMON GROUND STRIPE

Figure 23. Outline drawing of integrated gated-diode test structure with

output MOSFET electrometer and MOSFET reset switch.

24
mixing effects are observed as deep as 3 nm below the surface when sputter

profile measurements are made with a 1-keV ion beam [51] . The mixing depth

for the higher energy ion beam used for ion microprobe mass analysis is substantially larger.

Many of the techniques used to fabricate microstructures involve substantial

amounts of ionizing radiation. Calculations have been made of the dose deposited in oxide layers by several processing steps [52,53]. For example,

figure 25 shows the dose deposited during typical exposure during directwrite electron-beam lithography. This radiation can introduce neutral traps

into the oxide [54] . Temperatures higher than 550°C are required to anneal

out these traps; those which remain may later cause device failure. Because

the commonly employed threshold-voltage-shift tests do not detect neutral

traps, it is necessary to develop new test procedures to assure that the an- nealing steps have been effective.

High-resolution scanning acoustic microscopy [55] is a new technique for direct imaging of the crystal or device chip. The instrumentation, shown in

figure 26, is relatively simple to use because it responds to the elastic

properties of the specimen. Acoustic microscopy provides the possibility of

observing defects, such as the voids under metallization crossovers shown in

figure 27, which are not detectable by the more traditional imaging methods

such as visible-light, infrared, or electron microscopy.

4. OTHER METROLOGY

Microstructure fabrication imposes additional demands on the purity of process chemicals and gases. Chemical purity to the degree required for microelectronic fabrication is not a trivial matter. Only recently have specifications for chemicals used in microelectronics been prepared and methods to

test for impurities in these chemicals been assembled [56] . It remains to be

demonstrated whether these specifications and test procedures will be adequate for chemicals to be used in fabrication of submicrometer devices and

structures.

A variety of new processing technologies is required to fabricate microstructures. A new set of measurements, replacements for the traditional times and

temperatures, is essential for controlling the new processes if reproducible

devices with predictable characteristics are to be manufactured.

For example, accurate control of shallow, low-dose ion implantations is critical to modern device performance. Careful studies have been made of secondary particle collection procedures to improve the accuracy of dose measurements [57] . A systematic investigation of the dependence of implant profiles

on the beam alignment angle led to the conclusion that in a variety of circumstances significant channeling tails can exist for alignment angles com- monly thought to yield random-equivalent implants [58] . NBS has had some inquiries which suggest there might be a need for standards to relate the sheet

resistance of an implanted layer to the implanter machine parameters. Although it would appear that the already developed dose measurement procedures

would be adequate to predict the sheet resistance, additional standards may

be required for use in manufacturing environments.

25
40 20 0 LIFETIME (MS)

Figure 24. Wafer map of generation lifetime as determined from measurements

on integrated gated-diode test structures fabricated with a p-channel, selfaligned polys il icon gate technology. The values given on the map are averages

of measurements made on six diodes in each cell; darker symbols represent

lower lifetime. The graph on the right shows the results of individual measurements in the line of cells identified by the arrows on the wafer map.

10*

10'

</> - - 106

10="

10*

10^

I I I iiiiii—I

I I mill I I I I mil TTTTn "T I IIIIII

I POOP

PIGMA-co-EA]

PMMA

iiiiil I 1 I mill I I 1 I Hill I I lllllll 10* 10-' 10* 10*

RESIST DOSE |C/cm^ 1

Figure 25, Dose deposited in a 100-nm thick oxide under 1-ym thick aluminum

and 500-nm thick resist as a function of the dose in the resist for 15- and

25-keV electrons. The doses required to expose typical e-beam resists are indicated by the vertical arrows. (After Galloway et al. [53])

26
Sensitive measuring techniques are also needed to evaluate the annealing step

required to activate implants [59] . For shallow, low-dose implants, only ca- pacitance voltage profiling appears to have adequate sensitivity for measurI ing dopant profiles. Figure 28 shows the highly doped surface region produced by annealing of a low-dose implant with a l-ys pulse from a dye laser.

The scanning electron microscope operated in the charge-collection mode appears to be the most appropriate technique for studying electrically active

defects in implanted regions; these defects may or may not be removed by the

annealing step. The three scanning electron micrographs in figure 29 show —

from left to right — unannealed, thermally annealed, and 1-ys pulse-laser

annealed regions. Defects appear as the dark areas of the micrograph. Annealing with pulsed or scanned steady-state lasers is currently a very active

research field. Different laser conditions have yielded significant differences in impurity redistribution and defect removal properties; new metrology

is required for characterization and control of the laser sources.

i Plasma etching is an important process for patterning microstructures. At

the present time, the physics of the plasma etching mechanism is not well un- derstood and a good in-line monitoring system for this process is not yet

available. Neither mass spectrometry nor optical spectroscopy provides data

on either etch rate or uniformity of etching, although both techniques prof vide end point information. Interferometric monitoring provides both etch

rate and end point information but does not provide data on the etching uniformity.

Process-induced structural faults, ,such as pin holes in insulating films,

shorts between layers in the structure, or open circuits in the metal interconnection runs, represent yield-limiting factors in microstructure fabrication. These faults may occur randomly or they may be clustered in various

localized positions. Test structures for these faults may be series or parallel strings (designed to be tested with a continuity tester) or memory-like

addressable arrays as shown in figure 30 [ 18] . Both types of structures must

occupy substantial areas on the wafer if they are to be effective. At the

present time, the models for analyzing the, results obtained on such structures are extremely crude; nevertheless, qualitative and semiquantitative information can frequently be obtained.

The large die and package configurations associated with very large scale integrated circuits impose additional requirements on the measurement of me- chanical integrity of the package, interior moisture levels in the package,

and heat transfer characteristics of the die package configuration. Accurate

measurements of these quantities are, at the present time, virtually impossible. All these areas are currently under investigation, but the work is in

such an early stage that definitive results have not yet been achieved.

5 . SUMMARY

In summary, selected types of metrology associated with subraicrometer devices

and structures have been examined with emphasis on problems associated with

dimensional metrology and characterization of semiconducting materials. Generally speaking, metrology on the scale required for microstructures is still

in an embryonic state. Resolution and sensitivity of conventional methods

for both dimensional measurements and materials characterization must be ex27
Figure 26. Experimental setup for

370-MHz scanning acoustic microscope.

(Photo by Hughes Research Laboratories)

Figure 27. Scanning acoustic micrograph of a section of a silicon-onsapphire integrated circuit which illustrates structural detail under the

metallization stripes. (Micrograph

by C. F, Quate, Stanford University)

10

10

10

1 5x10 CI 375 keV

(111) Si

LASER

ANNEAL

0.2 0.4 0.6 0.8 DEPTH (^;m)

1.0

Figure 28 (left). Capacitance-voltage

profiles of a phosphorus-implanted

silicon wafer characteristic of thermally annealed and laser-annealed

areas of the wafer, illustrating highly doped surface region produced by

laser annealing. (After Myers et at.

[59] )

28
:1

(a) (b) (c)

Figure 29. Charge collection scanning electron micrographs of as-implanted

(a), thermally annealed (b), and laser-annealed (c) regions of a silicon

' wafer implanted with boron to a dose of about 10^^ cm"^ , (After Myers et

J al, [59] )

a. Parallel-string tester for leakage b. A 10 by 10 array of individually

in gate and field oxides. addressable MOSFETs.

Figure 30. Outline drawings of random fault testers included on test pattern

NBS-16. (After Linholm [18])

29
tended if these are to be useful in the submicrometer range. In some cases adequate methods do not yet exist, and new methods and standards must be developed. This need is widely recognized, and considerable activity for this

field is now underway at many laboratories throughout the world to provide

the advanced measurement technology needed for the reproducible manufacture

of microstructures with predictable characteristics.

6. ACKNOWLEDGMENTS

The author wishes to thank the many members of the staff of the NBS Electron

Devices Division and its contractors who have conducted the research reported

herein for detailed discussions of their work and for their assistance in the

preparation of this manuscript. In addition, he wishes to thank Graydon

Larrabee of Texas Instruments for permission to reproduce figure 17 and for

providing an original drawing of this figure. Finally, he wishes to thank

the organizers of the Microstructure Fabrication Conference for the valuable

opportunity to participate in the conference.

7. REFERENCES

1. Nyyssonen, D., Optical Linewidth Measurements on Wafers, Pvoe » Soe

Photo-Optical Instrumentation Engineers 135 , Developments in Semiaondustor Microtithography III, 115-119 (1978).

2. Considine, P. S. , Effects of Coherence on Imaging Systems, J. Opt. SoQ.

Am. 56, 1001-1009 (1966).

3. Nyyssonen, D., Linewidth Measurement with an Optical Microscope: The

Effect of Operating Conditions on the Image Profile, Appt. Optics 16 , 2223-2230 (1977).

4. Nyyssonen, D., and Jerke, J. M. , Optical Linewidth Measurement — A Basic

Understanding, Proa. Miaroeteatvonias Measurement Teohnotogy Seminar,

San Jose, California, February 6-7, 1979, pp. 251-266.

5. Swyt, D. A., NBS Program in Photomask Linewidth Measurements, SotidState Technology (4), 51-57 (April 1976).

6. Swyt, D. A., and Rosberry, F. W., A Comparison of Some Optical Microscope Measurements of Photomask Linewidths, Solid State Technology 2£

(8), 70-75 (August 1977).

7. Jerke, J. M. , Semiconductor Measurement Technology: Optical and

Dimensional-Measurement Problems with Photomasking in Microelectronics,

NBS Spec. Publ. 400-20 (October 1975).

8. Nyyssonen, D., Spatial Coherence: The Key to Accurate Optical Micrometrology, Proc. Soc. Photo-Optical Instrumentation Engineers 194 , Applications of Optical Coherence, 34-44 (1979).

9. Scire, F. E., and Teague, E. C. , Piezodriven 50-ym Range Stage with Subnanometer Resolution, Rev. Sci. lustrum. 49, 1735-1740 (1978).

30
10. Swyt, D. A., An NBS Physical Standard for the Calibration of Photomask

Linewidth Measuring Systems, Proe. Soo. Photo-Optical Instrumentation

Engineers 129 , Effective Utilisation of Optics in Quality Assuranae,

98-105 (1977); see also Swyt, D. A., Design of a Pattern on a Photomask-Like Physical Standard for Evaluation and Calibration of

Linewidth-Measuring Systems, Solid State Technology 2_1_ (1), 35-42

(January 1978).

11. Recommended Procedures for Photomask Linewidth Measurement (ARChromium) , to be published.

12. Jerke, J. M. , Hartman, A. W. , Nyyssonen, D., Swing, R. E. , Young, R.

D., and Keery, W. E., Comparison of Linewidth Measurements on an SEM/Interferometer System and an Optical Linewidth-Measuring Microscope,

Proc. Soc. Photo-Optical Instrumentation Engineers 100 , Developments in

Semiconductor Microlithography II, 37-45 (1977).

13. Young, R. D., Length Calibrations in the Micrometer and Siib-Micrometer

Range, Ann. CIRP 25, 245-250 (1977).

14. Belanger, B. C. , Ed., Calibration and Related Measurement Services of

the National Bureau of Standards, NBS Special Publication 250, p. 15

(April 19 78); see also Anon., Line-Standard Interferometer, WS Tech.

'News Bulletin, pp. 43-45 (March 1967).

15. Carver, G. P., Linholm, L. W. , and Russell, T. J., The Use of Microelectronic Test Structures to Characterize IC Materials, Processes, and

Processing Equipment, Solid State Technology (in press).

16. David, J. M. , and Buehler, M. G., A Numerical Analysis of Various Cross

Sheet Resistor Test Structures, Solid-State Electronics 20, 539-543

( 1977)

17. Buehler, M. G., Grant, S. D., and Thurber, W. R. , Bridge and van der

Pauw Sheet Resistors for Characterizing the Line Width of Conducting

Layers, J. Electrochem. Soc. 125 , 650-654 (1978).

18. Linholm, L. W., CMOS/SOS Test Patterns for Process Evaluation and Control: Annual Report, March 1 to November 1, 1978, NBSIR 79-1595 (January 1979).

19. Chandler, J. P., and David, J. M. , Mapping of Geometrically Dependent

Data in Two Dimensions, in Semiconductor Measurement Technology, Progress Report, July 1 to December 31, 1975, W. M. Bullis, Ed., NBS Special

Publication 400-25, pp. 43-44 (October 1976).

20. Linholm, L. W., and Buehler, M. G., A Cross-Bridge Structure Array for

Characterizing Intrachip Linewidth Variations, Electrochemical Society

Ejctended Abstracts (79-1), pp. 502-504 (May 6-11, 1979).

21. Russell, T. J., Leedy, T. F., and Mattis, R. L., A Comparison of Electrical and Visual Alignment Test Structures for Evaluating Photomask

Alignment in Integrated Circuit Manufacturing, Technical Digest, Inter31
national Electron Devices Meeting, Washington, DC, December 5-7, 1977,

pp. 7A-7F.

22. Russell, T. J., and Maxwell, D. A., Semiconductor Measurement Technology: A Production-Compatible Microelectronic Test Pattern for Evaluating Photomask Misalignment, NBS Special Publication 400-51 (April

1979)

23. Perloff, D. S., A Four-Point Electrical Measurement Technique for Characterizing Mask Superposition Errors on Semiconductor Wafers, IEEE J*

Solid-state Circuits sc-13 , 436-444 (1978).

24. Belanger, B. C, op. cit*, p. 21; see also Teague, E. C, Evaluation,

Revision, and Application of the NBS Stylus/Computer System for the Measurement of Surface Roughness, NBS Tech. Note 902 (April 1976).

25. Blood, P., and Orton, J. W. , The Electrical Characterization of Semiconductors, Rep. Prog. Phys, 4j[, 157-259 (1978).

26. wieder, H. H., Laboratory Notes on Electrical and Galvanomagnetic Measurements (Elsevier Scientific Publishing Company, Amsterdam, 1979).

27. Evans, C. A., Jr., Surface and Thin Film Compositional Analysis, Anal.

Chem. 47, 818A-829A (1975), and Surface and Thin Film Analysis, Anal.

Chem. 47, 855A-866A (1975).

28. Wittry, D. B., Microanalysis, Past, Present, and Future, Proc. Adv.

Tech. Failure Analysis Symp. 1976^ Newport Beach, California, February

20-21, 1976, pp. 1-8.

29. Larrabee, G. B., The Characterization of Solid Surfaces, Scanning Electron Microscopy/197 7, Vol. 1., pp. 639-650 (IIT Research Institute,

Chicago, Illinois, 1977).

30. Schroen, W. H., Materials Quality and Process Control in Integrated Circuits Manufacture, Festkorperprohleme XVII (1977), pp. 351-380.

31. Annual Book of ASTM Standards, Part 43, published each year in November

by the American Society for Testing and Materials, Philadelphia, Pennsylvania.

32. Panel on Thin Film Microstructure Science and Technology, Micros true ture

Science, Engineering, and Technology (National Academy of Sciences,

Washington, DC, 1979).

33. Method F 84, Measuring Resistivity of Silicon Slices with a Collinear

Four-Probe Array, Annual Book of ASTM Standards, Part 43 (ASTM, Philadelphia, 19 79).

34. Miller, G. L., Lang, D. V., and Kimerling, L. C. , Capacitance Transient

Spectroscopy, Ann. Rev. Mater. Sci. 7, 377-448 (1977).

32
35. Buehler, M. G., Semiconduatov Measurement Technology: Microelectronic

Test Pattern NBS-3 for Evaluating the Resistivity-Dopant Density Relationship of Silicon, NBS Special Publication 400-22 (June 1976).

36. Koyama, R. Y., and Buehler, M. G. , Novel Variable-Temperature Chuck for

Use in the Detection of Deep Levels in Processed Semiconductor Wafers,

Rev. Soi, Instvum. 50, 983-987 (1979); see also Koyama, R. Y., and

Buehler, M. G., Semieonduotov Measuvement Teahnology: A Wafer Chuck for

Use Between -196 and 350''C, NBS Special Publication 400-55 (January

1979) .

37. Koyama, R. Y., Detection of Deep Levels in High Power Semiconductor

Materials and Devices, NBS J . Res. 83, 273-281 (1978).

38. Larrabee, G. B., Characterization of Materials at Small Dimensions,

Paper No. 8 in the Appendix of Reference 32.

39. Larrabee, G. B., and Dobrott, R. , Techniques for the Preparation and

Analysis of Standard Silicon Semiconductor Specimens for the Ion Microprobe Mass Analyzer, NBS GCR 79-159 (January 1979).

40. Helms, C. R. , Johnson, N. M. , Schwarz, S. A., and Spicer, W. E., Auger

Sputter Profiling Studies of the Si-Si02 Interface, The Physics of

Si02 cmd Its IntevfaceSy S. T. Pantelides, Ed., pp. 366-372 (Pergamon

Press, New York, 1978).

41. Grunthaner, F. J., and Maserjian, J., Chemical Structure of the Transition Region of the Si02/Si Interface, The Physics of Si02 cmd Its

InterfaaeSy S. T. Pantelides, Ed., pp. 389-395 (Pergamon Press, New

York, 1978).

42. Krausse, J., Spreading Resistance Measurements on Silicon with Nonblocking Aluminum-Silicon Contacts, Semiconduotov Measuvement Technology: Spreading Resistance Symposium, NBS Special Publication 400-10, J.

R. Ehrstein, Ed., pp. 109-122 (December 1974).

43. Buehler, M. G., and Thurber, W. R. , A Planar Four-Probe Test Structure

for Measuring Bulk Resistivity, IEEE Trans. Electron Devices ED-23 , 968-974 ( 1976)

44. Buehler, M. G., Peripheral and Diffused Layer Effects on Doping Profiles, IEEE Trans. Electron Devices ED-19, 1171-1178 (1972).

45. Buehler, M. G., Dopant Profiles Determined from Enhancement Mode MOSFET

D-C Measurements, Appl. Rhys. Letters 3J_, 848-850 ( 1977).

46. Buehler, M. G., The D-C MOSFET Dopant Profile Method, J. Electrochem.

SOC. 127, 701-704 (1980).

47. Grove, A. s.. Physics and Technology of Semiconductor Devices^ pp.

296-305 (Wiley, New York, 1967).

33
48. McCarthy, D., Buehler, M. G., Acevedo, J., Stamps, B., and Lonky, M. , An

Advanced Integrated Test Structure for High Speed Measurement of Generation Lifetime, Eleatvoahemioal Society, Extended Abstracts (78-2), pp.

488-490 (October 15-20, 1978); for additional details, see McCarthy, D.,

Acevedo, J., and Herman, D., Advanced Planar Silicon Test Structures,

NBS-GCR (to be published).

49. Carver, G. P., and Buehler, M. G., The Development of Test Structures

for Characterization of the Fabrication and Performance of RadiationHardened CCD Imagers, NBSIR 79-1744 (May 1979).

50. Carver, G. P., and Buehler, M. G., Analytical Expression for the Evaluation of Leakage Currents in the Integrated Gated-Diode Electrometer (to

be published).

51. Schwarz, S. A., and Helms, C. R. , An Ion Knock-On Mixing Model with Application to Si-Si02 Interface Studies, J. Vac. Sci, Tech. ^6^, 781-783

( 1979)

52. Galloway, K. F. , VLSI Processing, Radiation, and Hardening, IEEE Trans,

Nusl. Sci. NS-25 , 1169-1472 (1978).

53. Galloway, K. F. , Mayo, S., and Roitman, P., Radiation Levels Associated

with Advanced Lithographic Techniques, J. Electrochem, Soc. 126 , 2245-2248 (1979).

54. Aitken, J. M., 1 ym MOSFET VLSI Technology: Part VIII - Radiation Effects, IEEE Trans. Electron Devices ed-26 , 372-379 (1979).

55. Quate, C. G., Atalar, A., and Wickramasinghe, H. K. , Acoustic Microscopy

with Mechanical Scanning - A Review, Proc. IEEE 67, 1092-1114 (1979).

56. Book of SEMI Standards (Semiconductor Equipment and Materials Institute,

Mountain View, Calif., 1978).

57. Jamba, D. M., Semiconductor Measurement Technology: Some Aspects of

Dose Measurement for Accurate Ion Implantation, NBS Special Publication

400-39 (July 1977); see also Jamba, D. M. , Secondary Particle Collection

in Ion Implantation Dose Measurement, Rev. Sci. Instrum. 49, 634-638

( 1978) .

58. Wilson, R. G., Dunlap, H. L., Jamba, D. M., and Myers, D. R. , Semiconductor Measurement Technology: Angular Sensitivity of Controlled Implanted Doping Profiles, NBS Special Publication 400-49 (November

1978) .

59. Myers, D. R. , Roitman, P., and Mayo, S. , Electrical Characterization of

Low-Dose Ion-Implanted Silicon Annealed with Microsecond Laser Pulses,

Laser-Solid Interactions and Laser Processing—19 78y s. D. Ferris, H. J.

Leamy, and J. M. Poate, Eds., pp. 563-568 (Am. Inst. Phys., New York,

1979) .

34
lBS-r14A REV. &-76I

i U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBS Spec. Publ. 400-61

2.Gov't. Accession No. 3. R«£ip(ent's Accession No,

4. TITLE AND SUBTITLE Ssniconduator Measurement Technology: Metrology for Sub-

^5 /"vrM7iot-(=>r' rv^ \7 "i r" <=; r5nc3 Circuits

5. Publication Date June 1980

6. Performing Organization Code

I?. AUTHORiS

W. Murray Bullis

8. Performing Organ. Report No.

19. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, DC 20234

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Same as abDve

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' Document describes a computer program; SF-185, FIPS Software Summary, is attached.

16. ABSTRACT (A 200~word or less factual summary oi most significant information. If document includes a signi ficant bibliography or

literature survey, mention it here,)

The raetrological requirements of semiconductor raicroelectronics , always challenging, are made even more stringent by the trend toward submicrometer devices and

structures. This comes about not only because of the obvious demands associated

with the smaller feature sizes of circuit elements but also because of the attendant requirements for more efficient design verification aids, computer simulations, and process validation and control techniques and because of the concurrent

trend toward larger die and package sizes. This paper examines t±ie types of metrological requirements associated with submicrometer devices and structures, sum- marizes the present state of the art in selected critical areas of metrology, and

reviews current research and development efforts on advanced measurement technology, especially those at the National Bureau of Standards.

17. KEY WORDS fslx to (we;ve entries: alphabetical order; capitalize only the first letter of the first key word unless a proper name;

separated by semicolons) Dimensional metrology; electronics; integrated circuits; materials characterization;

measurement methods; microelectronics; microstructures; semiconductors.

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