NATL INST. OF STAND & TECH

AlllOb EbOSSM

NBSIR 84-2894

TERRY-2: A Test Chip for

Characterization of the

Performance of Buried-Channel

Charge-Coupled Device (CCD)

Imagers

G. P. Carver and R. A. Wachnik

U.S. DEPARTMENT OF COMMERCE

National Bureau of Standards

National Engineering Laboratory

Center for Electronics and Electrical Engineering

Semiconductor Materials and Processes Division

Gaithersburg, MD 20899

December 1984

QCPrepared for harles Stark Draper Laboratory, Inc.

ridge. MA 02139

100

,1156

34-2894

1984

IL j i

NATIONAL BUREAU

OF STANDARDS

library

NBSIR 84-2894

TERRY-2: A TEST CHIP FOR

CHARACTERIZATION OF THE

PERFORMANCE OF BURIED-CHANNEL

CHARGE-COUPLED DEVICE (CCD)

IMAGERS

G. P. Carver and R. A. Wachnik

U S. DEPARTMENT OF COMMERCE

National Bureau of Standards

National Engineering Laboratory

Center for Electronics and Electrical Engineering

Semiconductor Materials and Processes Division

Gaithersburg, MD 20899

December 1984

Prepared for The Charles Stark Draper Laboratory, Inc. Cambridge, MA 02139

U S. DEPARTMENT OF COMMERCE, Malcolm Baldrige, Secretary

NATIONAL BUREAU OF STANDARDS, Ernest Ambler. Director

Table of Contents

Page

Abstract ••«*»•••• '

Introduction •

CCD Fabrication Process and Design Rules ..... 3

Test Structure Descriptions 4

Layout 6

Test Structure Measurement Procedures .... ...... r 7

Measurement Program and Test Result Evaluation .... 18

References . . . t . . 20

Appendix: Charge Pumping . 121

Lise of Tables

1. Layer and Mask Labels 23

2. Minimum Geometry Design Rules ........... 24

3. Cross-Bridge Sheet Resistors 25

4. Contact Resistors .... c. ........ 26

5. Transistors 27

6. Large Capacitors and Transistors .... 29

7. X- and Y-Coordinates of Cell Origins 30

8. X- and Y-Coordinates of Bonding Pij d Origins 31

9. Bonding Pad Connections „ 32

10. Devices Listed by Cell 34

11. List of Symbols for Transistor Models 38

A1 . Lis^- of Symbols for Charge Pumping 126

iii
List of Figures

Page

1. Cross-bridge sheet resistor CB-1 39

2. Cross-bridge sheet resistor CB-2 40

3. Cross-bridge sheet resistor CB-3 41

4. Cross-bridge sheet resistor CB-4 42

5. Cross-bridge sheet resistor CB-6 43

6. Cross-bridge sheet resistor CB-7 44

7. Cross-bridge sheet resistor CB-8 45

8. Cross-bridge sheet resistor CB-9 46

9. Cross-bridge sheet resistor CB-10 47

10. Cross-bridge sheet resistor CB-1 1 48

1

1 . Contact resistor CR-1 49

12. Contact resistor CR-2 50

13. Contact resistor CR-3 51

14. Contact resistor CR-4 52

15. Contact resistor CR-5 53

16. Contact resistor CR-6 54

1

7. Contact resistor CR-7 55

1 8. Contact resistor CR-8 56

19. Contact resistor CR-9 57

20. MOSFET T— 1 58

21. MOSFET T-2 59

2 2. MOSFET T-3 60

2 3. MOSFET T-4 61

24. MOSFET T- 5 62

25. MOSFET T-6 63

26. MOSFET T-7 64

27. MOSFET T-8 „ 65

28. MOSFET T-9 66

29. MOSFET T-1 0 . . . 67

30. MOSFET T-1 1 . 68

31. MOSFET T-1 2 69

3 2. MOSFET T- 1 3 70

3 3. MOSFET T-1 4 , . . . e 71

34. MOSFET T-1 5 . . 72

35. MOSFET T-1 6 73

36. MOSFET T-1 7 . 74

37. MOSFET T-1 8 75

38. MOSFET T-1 9 76

39. MOSFET T-20 77

40. MOSFET T-21 78

41. MOSFET TN-1 79

4 2. MOSFET TN-2 80

4

3. MOSFET TN-3 81

44. MOSFET TN-4 82

45. MOSFET TN-5 83

46. MOSFET TN-6 84

4 7. MOSFET TN-7 85

48. MOSFET TN-8 86

49. MOSFET TN-9 87

IV
List of Figures (cont'd)

Page

50. MOSFET TN-10 88

51. Triple-Gate MOSFET TN-1 1 89

5 2. Triple-Gate MOSFET TN-1 2 90

53. Triple-Gate MOSFET TN-1 3 91

54. Triple-Gate MOSFET TN-1 4 92

55. Triple-Gate MOSFET TN-1 5 93

56. Triple-Gate MOSFET TN-1 6 94

57. Capacitor/Transistor T-101 95

58. Capacitor/Transistor T-102 96

59. Capacitor/Transistor T-103 97

60. Capacitor/Transistor T-104 98

61. Capacitor/Transistor T-105 99

62. Capacitor/Transistor T-106 100

6 3. Capacitor C-1 101

64. Capacitor C-2 102

65. Capacitor C-3 103

66. Capacitor C-4 104

67. Capacitor C-5 105

68. Gated-diode Electrometer GDA-1 ..... 106

69. Gated-diode Electrometer GDA-2 107

7 0. Gated-diode Electrometer GD-1 108

71. Gated Diode GD-2 109

72. Gated Diode GD-3 ........ 110

73. Gated Diode GD-4 Ill

74. Probe-Fault Error Structure P 112

7 5. Ground G 112

76. Cell probe pad array used for TERRY-2 113

77. Schematic of TERRY-2 showing the locations or each probe pad

cell 114

78. Schematic of TERRY-2 showing the locations and identifications of

bonding pads . 115

79. Schematic of TERRY-2 showing interconnections between test

structures, probe pads, and bonding pads 116

80a. TERRY-2 test chip layout schematic Produced by the CAD system

used to digitize the chip 117

80b. Photograph of a TERRY-2 test ch'p 118

81. Schematic of a six-terminal metai-to-dif fusion contact resistor . 119

82. Schematic cross sections of trxple-gate transistors showing the

effect of a misalignment -j”, in the sourue-to-drain current

direction, between the r-SI mask and the DIFF mask 120

A1 . Comparison between .rapezoidai pulse and three-level pulse ... 127

A2. Capture and emis'-ion processes during charge pumping cn a p-type

sub«t ’'a i_e 128

v
PREFACE

This work was conducted as a part of the Semiconductor Technology Program at

the National Bureau of Standards (NBS). This program serves to focus NBS

research to enhance the performance, interchangeability, and reliability of

discrete semiconductor devices and integrated circuits through improvements

in measurement technology for use in specifying materials and devices in

national and international commerce and for use by industry in controlling

device fabrication processes. This research leads to carefully evaluated and

well-documented test procedures and associated technology. Special emphasis

is placed on the dissemination of the results of the research to the electronics community. Application of these results by industry will contribute

to higher yields, lower cost, and higher reliability of semiconductor devices. Improved measurement technology also leads to greater economy in

government procurement by providing a common basis for the purchase specifications of government agencies and, in addition, provides a basis for con- trolled improvements in fabrication processes and in essential device characteristics .

The segment of the Semiconductor Technology Program described in this report

was supported by The Charles Stark Draper Laboratory, Inc. (CSDL) under CSDL

Prime Contract N00030-81 -C-01 33 issued by the Department of the Navy, Strategic Systems Project Office. CSDL's purchase Order Number DL-H-2081 37 covered

work at NBS for the period December 1, 1982 through November 30, 1983. Work

was monitored by Mr. Robert E. Var of CSDL. The NBS contacts for technical

information on this project are Gary P. Carver and Richard A. Wachnik of the

Semiconductor Materials and Processes Division at the National Bureau of

Standards, (301) 921-3786.

The authors would like to acknowledge the technical guidance and support of

Loren W. Linholm, Jeffrey A. Mazer, and Dwight Yen and the editorial assistance of Jane Walters, Brenda L. Kefauver, and Pamela M. Baker.

vi
TERRY-2: A Test Chip for Characterization of the Performance

of Buried-Channel Charge-Coupled Device (CCD) Imagers

G. P. Carver and R. A. Wachnik

Semiconductor Materials and Processes Division

National Bureau of Standards

Gaithersburg, MD 20899

ABSTRACT

Test chip TERRY-2 is intended to be used for characterization of

process and performance parameters associated with buried-channel

charge-coupled device (CCD) imagers fabricated with a doublepolysilicon-gate process which includes several implants. Test

structures in TERRY-2 permit evaluation of material properties

which are useful for predicting CCD performance and processing

quality. TERRY-2 is a modular chip designed for automatic testing;

selected devices can be wire bonded for testing various environmental effects; a region containing test structures can be thinned in

the same manner as a back-side-i llvminated CCD would be; and large

devices can be beveled for spreading resistance or physical analysis. This report describes TERRY-2, the test structure designs,

and the measurement procedures. The technique of charge puinping

for measuring interface state density is discussed ir an appendix.

Key Words: CCD; charge-coupled device; charge pumping; contact re- sistor; microelectronic test chip; sheet resistor; test chip; test

pattern; test structure

1
INTRODUCTION

This report documents the charge-coupled device (CCD) test chip TERRY-2. It

contains information for understanding the layout, test structures, and test

methods associated with the test chip and for implementing the test chip and

test methods.

The CCD test chip TERRY-2 is intended to be used for characterization of the

processing steps and the performance of buried-channel CCD imagers fabricated

with a double-polysilicon-gate process which includes several implants.

With adaptive changes, it could be useful to monitor other fabrication processes.

Some of the special features incorporated in TERRY-2 are as follows:

1 . Modularity . All the probe pad arrays are located on a constant grid

spacing.

2. Testability . All test structures are accessible electrically for automated testing using the 2 by 1 0 probe pad array cells.

3. Bondability . Test structures useful for evaluation of environmental

effects are accessible both from the probe pad arrays and from bonding

pads.

4. Thinnabili ty . Selected test structures for evaluating the effects of

thinning are located in a region which can be thinned in the same manner

as back-side-illuminated CCD imagers are thinned. After thinning, these

test structures remain accessible by probe pads, and in some cases by

bonding pads also, located on unthinned regions.

5. Availability for Beveling . Structures large enough to bevel for spreading resistance measurements are located at the top edge of the chip.

The implementation of a test chip measurement program depends on a variety of

factors which may change with time as the process evolves and as test results

are accumulated and evaluated. In the beginning, it is necessary to identify

those parameters associated with the materials and device characteristics

which are sensitive to process control, to establish their variability, to

characterize excursions from expected results, and to identify sources of

process variations.

When a test chip is first introduced into a process, all test devices should

be measured. These initial test results can be used to correct or improve

the process and also to identify specific tests which provide the information

most needed to monitor the process performance, to characterize the materials, and to evaluate critical performance parameters. When the process is

determined to be under reasonable control, the initial complete test program

may be reduced to a less complete set of test chip measurements which still

provides the most useful data.

2
Test data must be interpreted in association with a mathematical model. When

choosing a model for the interpretation of test data, the accuracy with which

the model represents the test device becomes an issue, A complex model re- quiring a large number of measurements may in principle yield very accurate

values of material or device parameters. Alternatively, a simple model may

describe device behavior over a specified range using less accurate or more general parameters. The simpler model may avoid the need for large amounts

of test data and measurement time, while retaining sufficient sensitivity to

variations in material parameters. Yet, too simple a model or measurement

can provide incorrect results or can fail to detect unacceptable device behavior. A complex model and large amounts of data taking may mean in actuality that no data will be acquired because the investment is too great. There

are no simple guidelines to choose the optimal degree of complexity or the

optimal amount of data. Practical considerations particular to each case determine both.

Ideally, well-designed test structures provide accurate, sensitive methods of

easily measuring selected parameters with simple models and automated instrumentation. In the following sections, models are described which should be

sufficiently sensitive and simple to be useful with test chip TEPRY-2. In

general, the notation in each section is consistent with the primary reference for the section.

CCD FABRICATION PROCESS AND DESIGN RULES

A fabrication process used to fabricate n-buried-channel CCD arrays for which

test chip TERRY-2 is intended is outlined in table 1 . The process includes

two levels of polysilicon gates. There are ten mask levels, plus one mask

for an optically active back-side-thinned region beneach the CCD.

Table 2 specifies the process geometrical design rules used for the test

structures in TERRY-2. There are a few instances ^here the design rules were

violated. These violations were necessary to solve specific geometrical

problems which arose in sequences of structures where one dimension differs

from structure to structure but all other dimensions are constant. The design rules stated in table 2 were violated in structures CB10, T13, T14, T16,

T17, and T19.

TEST STRUCTURE DESCRIPTIONS

The test structures in TERRY-2 include ones for use in measuring process and

material properties, active device parameters, and device and material properties related to CCD performance. In addition, several structures are designed to be used in exper: .^ntal studies on interface states and other mea- surements and phenomena jf probable nigh value in evaluating the performance

of CCD imagers.

Cross-Bridge Sheet Resistors . The cross-bridge sheet resistor is a combined

four—terminal van der Pauw sheet resisLux. and a. bridge tesistoi. rh>; i -irumeters which can be measured are the conducting layer she * : resistance and

linewidth. Cross bridges made in source/drain polysilicon 1, polysilicon 2, n~

,

n°, and aluminum are designed at or near the minimum process linewi ith.

In addition, there are gated structures in n~ and n° to evaluate the effects

3
of fixed oxide charge on the surface of these implants. The gates are also

accessible so that effects of fixed oxide charge and possible unwanted depletion can be overcome. Finally, there are cross bridges in field channel

stop, column channel stop, and epi. The epi structures are defined by

source/drain regions. Cross-bridge sheet resistors are designated CB-1

through CB-1 1 and are listed in table 3.

Contact Resistors . Six-terminal contact resistors are used to determine the

interfacial contact resistance and the front and end contact resistance of

ohmic contacts between the aluminum layer and the source/drain polysilicon 1

,

and polysilicon 2 layers. Each of the three contact types is addressed by

three contact resistors having square contact windows with sides of 5 (mini- mum geometry), 10, and 20 ym. This combination allows evaluation of the area dependence of the contact. Contact resistors are designated CR-1 through CR9, as described in table 4.

Practical-Style Transistors . The "practical-style" four- terminal MOSFETs

include four sets of devices with either polysilicon 1 or polysilicon 2 gates

and either with an n-type implant (depletion mode) or without an implant

(enhancement mode). The widths and lengths in ym (W/L) in each set are 60/10, 120/10, and 60/20. In addition, there are several transistors with

various gate layers over field oxide and with field channel stop or column

channel stop in the channel.

The enhancement- and depletion-mode sets are used to determine device parameters such as the threshold voltage, source-to-drain leakage current, source- to-drain breakdown voltage, and other transistor operating properties.

Availability of three different gate length/width ratios gives the advantage

of being able to verify the expected behavior of the devices in relation to

their geometical dimensions and to evaluate deviations from the design dimensions. The enhancement-mode devices can also be used for interface state

density measurements using charge-pumping techniques.

The nonconventional transistors (field oxide, channel stop-doped channels)

can be used to evaluate the unwanted threshold and breakdown voltages present

in unavoidable parasitic transistor structures in the circuit.

The design of the input-output circuit transistors incorporates the scheme of

extending the gate and gate oxide cut beyond the ends of the source and drain

(at the ends of the channel) to overlap the field channel stop. This strategy gives the capability to turn the transistor off even when the surface

beneath the oxide surrounding the source and drain, where there is no channel

stop, may have become inverted. In the test chip, some practical-style transistors include this design feature and some do not. The reason for not

including this inversion protection on all practical-style transistors is

that the effective active gate area is better known when the active area is

defined by the gate oxide cut. For measurements of the effects of thinning,

interface state density, lateral diffusion, etc., a well-known gate area is

important.

The practical-style transistors are designated T1 through T21 and are described in table 5.

4
Wide-Gate Transistors . The four-terminal MOSFETs with wider gates than the

practical-style series are all enhancement-mode devices. They provide larger

dimensions and a larger range of gate lengths primarily for verification of

the smaller practical transistor results and for studies requiring a more accurately known gate area, sucn as the development of measurement procedures

for quantifying the interface state density value obtained from charge pumping. The wide-gate transistor series listed in table 5 includes devices

designated TNI through TN10.

Triple-Gate Transistors . The triple-gate MOSFETs have a center gate formed

from one polysilicon layer and two outer gates, between the center gate and

the source or drain, formed from the other polysilicon layer. These

enhancement-mode transistors are six- terminal devices. They are intended for

further verification of charge -pumping results and for studies relating leakage current measurements to charge-pumping measurements. The critical feature is that the center gate can be operated like an MOS capacitor when the

outer gates are "OFF" or like a conventional transistor gate when the outer

gates are "ON." Therefore, gated-diode-like reverse-bias leakage current

measurements, MOS capacitance-voltage measurements, and charge pumping mea- surements can be performed on the same interface.

The triple-gate transistors are wide-gate structures (and their gates do not

overlap the field channel stop) so that their gate area is .large enough to be

known accurately. They are in a series where the center gate has lengths of

10, 20, and 30 pm. The outer gate lengci s are 10 pm. The series is repeated

with the polysilicon 1 and polysilicon 2 layers reversed. Triple-gate transistors have designations TN1 1 through TN16. They are listed in table 5.

Large Area Capacitors/Transistors . There are eight different structures with

areas large enough for accurate capaci tance-voltage and capaci tance- time

measurements, for electrical dopant profiling, and tor spreading resistance

measurements. Two devices are MOS capacitor strr.c cures formed of polysilicon

1 or polysilicon 2 and gate oxide over die p - type epilayer. These devices

are designated Cl and C2 . Two devices are enhe.icemant-mode MOSFETs with n

+ sources and drains, designated T101 and T102, Two pairs of additional devices are depletion-mode transistors with rT' or n 3 implanted layers in their

channel region, designated T103 through T'.j 6. They are identified in table

6. All eight devices have equal gate active-region areas.

The unique value of these structures is their large area and the associated

large gate capacitance. These devices will be necessary for precise diagnostics, although they may not be tested on a regular basis. When measurements

on other transistors require comparison with a structure having a much larger

gate area, these devices wi .j_ be valuable for verification purposes. Also,

the depletion-mode tra^°_stors car, be used to perform bulk deep-level transient spectroscopy (DLTS).

Gated Diodes . There are six gated diodes for measuring reverse-: : is leakage

current and surface recombination velocity. The reverse-bias leakage current

value can be used to determine the bulk generation rate and the bulk lit e— time; these parameters can be determined as a function of dept.. Over i ne

5
thinned area, it may be possible to measure the back-side-thinned surface

recombination velocity.

Two devices, designated GDA1 and GDA2 , are the previously developed gated

diode test structures with built-in electrometers for easy automated measurement [Carver and Buehler, 1980; Carver, 1981

]

c These devices have gates of

polysilicon 1 or polysilicon 2. Four other gated diodes, GDI through GD4, are dual-gate devices and are either surface channel or buried channel.

Buried-channel devices have the n~ implant beneath their gates. The dualgate gated diodes are intended to be used for a variety of measurements, some

of which duplicate the measurements that can be performed on single-gate or triple-gate transistors. However, the geometry of the gated diodes is optimized for reverse-bias leakage current measurements and the results are more straightforward to interpret. The disadvantage is that, without the built-in

electrometer, gated-diode measurements are more difficult to perform and are not suitable, generally, for automated measurement. Results of comparisons

between measurements made on these gated diodes and on the various transistor

configurations will indicate the most appropriate strategy for actual use of

the devices. It is likely that the gated diodes will provide additional

information not available otherwise, and some information more accurately

than otherwise available but at a greater expense of time and effort.

Probe-Fault Error Structure . The probe-fault error structure is simply a metal connection between two adjacent probe pads. The absence of an electrical short between the two pads would indicate the likelihood of a probe position error. This device is placed wherever two probe pads occur in a column

in a location where they cannot be used for anything else. This structure is

labeled P.

Computer-generated drawings of the test structures contained in CCD test chip

TERRY-2 are presented in figures 1 through 75. The drawings are all to the

approximate scale of one inch equals 50 pm. The smallest interval used is

2.5 pm. This distance corresponds to one-half the grid spacing on the mylar

sheets used for the original master drawings. No overlapping lines were allowed except where absolutely necessary to preserve some dimensional re- quirement in one device of a sequence.

Interconnects between devices and probe or bonding pads are 12.5 pm in

width.

LAYOUT

CCD test chip TERRY-2 is a square chip and fits within an area 5200 pm on a side. It has alignment targets designed for use with positive photoresist.

TERRY-2 is modular for convenient access by automated probing systems. All

test structures can be probed electrically via uniformly arrayed probe pads.

In addition, certain test structures are connected also to bonding pads.

These devices can be conveniently wire bonded for measurement when the chip

is packaged for environmental testing.

6
Some devices are located over a region which can be back-side-etched to evaluate effects of thinning processes used for back-side-illuminated CCDs.

These structures are connected to probe pads, and in some cases, bonding pads

located outside the thinned area.

Large area test structures containing the n~ and n° layers are situated near

the upper edge of the chip for con/enience when beveling to perform spreading

resistance profiling measurements.

The selection of test structures for the thinning area and for connection to

the wire bonding pads involved an assessment of the process and material

parameters which would be important to evaluate the performance of CCDs. The

choices were based on some knowledge of the performance of the existing process and anticipated process and materials characterization needs. Just as

in the selection of measurements to be made, choices of test structures involve tradeoffs that can be best evaluated only with knowledge of the process

status and with a guiding test philosophy. These considerations are discussed in the "Test Structure Measurement Procedures" section.

The TERRY-2 test chip employs modular test structures and a 2 by 1 J probe pad

array [Buehler, 1979]. Except for the large area capaci tor/tra lf.is tors , all

test structures have probe pads contained in their design.

The probe pad array within one cell is shown in figure 76. One probe pad

array is a cell of 20 pads, two pads wide and ten pads high. Prcbe pad spacing is 160-pm center- to-center. This spacing is preserved, between cells so that each probe pad is positioned at a distance which is f. multiple of 160 pm

from any other probe pad in the chip. All probe pads ave square, 80 pm on a side.

Table 7 gives the x- and y-coordinates of the origins (lower left corner) of

the cells. The lower left corner of the chip boundary is the reference origin (0,0) for the chip. The locations of the cells are shown in figure 77.

The square bonding pads are 120 pm on a side. Locations and designations of

the bonding pads are shown in figure 78 and rhe location of the origins (lower left corner) of all bonding pads is tabulated in table 8. A list of the

device connections to each bonding pad is prc /ided in table 9. Figure 79

shows a schematic of the connections between the bonding pads and the probe

pads. The overall layout of the test chip is shown in the composite drawing

in figure 80a and the photograph of an actual chip in figure 80b.

All test structures are listed cell in table 10. The numbers at the right

are the pad numbers associated with each test structure. Pads within each

cell are numbered according to the scheme shown in figure 76; the pads a^e

counted down from number one at the top left and then uo numoer 20 at the

top right

TEST STRUCTURE MEASUREMENT PROCEDURES

The particular strategy chosen to implement the TERRY-2 test chi p as j-art of

a comprehensive testing program depends on a variety of factors assoc i a t.o,

i

7
with the performance of the fabrication process [Carver, 1980; Buehler,

1983], Some of these factors and their implications regarding test strategy

are discussed in the next section. In this section, emphasis is on the specific measurements which can be performed using the individual test structures in the test chip.

Detailed measurement procedures for certain of the test structures are described in many widely available publications; those procedures are not re- peated in this report. However, to provide a useful and reasonably complete

report, many of the required measurement procedures and mathematical relationships are briefly described.

Cross-bridge Sheet Resistors . Cross-bridge sheet resistors are designed to

allow measurement of the conducting layer sheet resistance at the cross and

the effective average electrical linewidth in the bridge portion of the

structure [Buehler et al . , 1978 and Buehler and Thurber, 1978]. The measurements are performed by sensing a voltage between two probe pads while a cur- rent flows between two separate probe pads. The measurements are potentiometric and avoid interfering current-induced voltage drops in the voltagesensing connections. The appropriate current levels are chosen to maximize

the resolution of the voltage measurement while avoiding thermal effects.

Carrying out the suggested permutations of the sheet resistance measurement

allows calculation of an asymmetry factor. When the asymmetry factor is

small enough, a high degree of assurance is obtained that the measured sheet

resistance value is reliable [Buehler and Thurber, 1978].

Measurement of the sheet resistance and linewidth of the n

+ source/drain

layer (cross-bridge CB1 ) , the two polysilicon layers (CB2 and CB3 ) , and the

aluminum layer ( CB4 ) is straightforward and is unlikely to be affected by

other process or material characteristics. Measurement of the n~ image area implant and the n° depletion transistor implant could be affected by charges

in the oxide and overglass covering the cross bridges made of these layers

(CB5 and CB8). Therefore, additional n~ and nO cross-bridge structures are provided which are gated. In principle, the gate voltage is adjusted to

obtain the flatband condition at the oxide interface of these structures when

the sheet resistance and linewidth measurements are performed. The required

gate voltage can be determined from high-frequency capacitance-voltage

measurements on the large capacitor/transistors (T103, T104, T105, and T106).

Cross-bridge sheet resistors CB6 and CB7 are n~ layer devices with gates

formed of polysilicon 1 and polysilicon 2 layers, respectively. Cross-bridge

sheet resistor CB9 is an depletion transistor layer device with a poly - silicon 2 gate.

Using a cross-bridge structure, measurement of the sheet resistance and linewidth of the image area column channel stop layer CS2 presents special problems because the substrate is p-type. In this case, the n

+ source/drain

layer is used to define the lateral shape of the column channel stop conducting channel (because there is no n-type tub in the CCD fabrication process)

to create cross-bridge CB10. However, since there is no isolation beneath

the column channel stop layer, an additional cross-bridge structure, CB1 1 , is

provided which is identical with CB1 0 except that the column channel stop

8
layer is absent. It is likely that the comparison of results from these two

structures will provide a measure of the column channel stop sheet resistance. Since the linewidth in these structures is determined by the n

+ layer

lateral diffusion, the bridge portion of the devices may be used to provide

an additional estimate of the column channel stop sheet resistance. The

effective linewidth would be assumed from information about the amount of n

+ layer lateral diffusion

It is possible, using a detailed model of the current distribution in CB1 1

,

that the resistivity of the p- type epilayer could be estimated using this

structure.

Contact Resistors . The "contact resistance" at a test contact is not adequately described by a single resistance value; unless a complete set of

parameters associated with a particular contact is known, measurements on

that contact cannot be used to predict the behavior of other contacts.

Six- terminal contact resistors can be used to determine electrically four

parameters which can be used to describe the contact performance and to predict the behavior of other contacts. These parameters are the iiiterfacial

contact resistance, the end contact resistance, the front contact resistance,

and the specific contact resistance r Proctor et al., 1983], Tne first two

parameters are directly measured using the contact resistor test structure;

the latter parameters are calculated using expressions based upon a twodimensional resistor network model.

The interfacial contact resistance Rc

, in ohms, is the total resistance of

the interfacial layer in a metal-semiconductor contact; it does not include

any interconnect resistance. The end contact resistance Re

, in ohms, is

the resistance given by the voltage drop across the interfacial layer at the

edge of the contact where the current density is least divided by the total

current through the contact. The front contact resistance Rf, in ohms, is

similarly defined except that the edge of interest is the contact edge where

the current density is greatest. These two resistances are different, even

in a uniform contact, because at a contact the current tends to flov in the

layer with the lower sheet resistance, usually the metal layer. Therefore,

if the current flows in a straight path through a contact between a diffusion

layer and an aluminum layer, the edge of cne contact where the current density is greatest (the "front" edge) is the edge toward the diffusion since near

that contact edge much of the curreni will cross the interfacial layer and

flow through the aluminum. The specific contact resistance, in ohm^cm'-, is

the resistance of a unit area of the interfacia] layer in a metal semiconductor contact. It is the voltaae drop across the interfacial layer divided by

the current density through the interfacial layer and is constant across a uniform interfacial layei.

A series devices with different contact window areas can be used to determine the uniformity of the interfacial layer and the uni formi t-y of he i nterfacial contact resistance, relying on the assumption that the interfacial

contact resistance is inversely proportional to the contact window ar*-a.

This assumption is required for all the parameter determinations using hottest structures. If the data indicate that the expected inverse propr

I

ality is not realized, then the specific contact resistance cannot be defined

9
and the interfacial contact resistance from a particular structure cannot be

used to predict reliably the interfacial contact resistance of any other

contact [Proctor et al., 1983].

Contact resistors in TERRY-2 address the aluminum to the source-drain layer,

tne aluminum to the polysilicon 1 level, and the aluminum to the polysilicon

2 level. The devices are replicated with square contact windows of three

edge lengths: 5, 10, and 20 pm.

The measurements are made by forcing a current through two probe pads and

measuring the voltage between two separate pads on the structure as described

in the reference [Proctor et al . , 1983]. Similar to cross-bridge sheet re- sistor measurements, this is a potentiometric measurement. Using the probe

pad notations in figure 81 , the interfacial contact resistance Rc is determined by measuring the voltage between probe pads 2 and 4, while a known

current is flowing between probe pads 1 and 3. A second voltage measurement

is made between pads 6 and 4. Then, with the current flowing between pads 5 and 3, the voltage is measured between pads 2 and 4 and between pads 6 and 4.

All four voltage measurements are averaged to calculate Rc

. The end con- tact resistance Re is determined by measuring the voltage between probe

pads 4 and 5 with a known current flowing between probe pads 1 and 3.

Results with the current flowing in the opposite (negative) direction should

also be included to average out thermoelectric voltages.

The set of expressions required for complete analysis of the four parameters

is as follows:

R =

c

V

nm

I nm

R

e

V

nm

I nm

R

e csch

R 1/2

[(-) a]

(1 )

( 2 )

(3)

R^ = R cosh

f e

R 1/2

[(/)

c

(4)

p = AR . (5) c c V nm and I nm are the voltage in volts and current in amps, respectively,

measured between pads n and m, Rs is the sheet resistance of the nonmetal

layer in ohms (per square), d is the contact window length (i.e., the distance between the front and back edges in cm) , w is the contact window width

in cm, and A is the contact window area in cm2

. The calculation of Rc

/ R

g

, and p c is straightforward using the first, second, and fifth expressions. Using the determined values of Re and p c

, the third equation is

10
evaluated to calculate Rs

. This value of Rs is then used in the fourth

expression to determine Rf.

If a series of contact resistors having different areas is found to have the same value of p c , then the uniformity of the interfacial layer is verified

and the above expressions can be used to predict reliably the values of Rc , Re , and R^. These values completely characterize the low-frequency behavior of a given contact.

Transistors . As test devices, transistors can be used for a variety of purposes, including device and process parameter extraction and random fault and

reliability analysis. The transistors in TERRY-2 are designed primarily for

measuring device and process parameters.

Methods used to determine test transistor behavior and models to define transistor parameters are discussed extensively in many common references and are therefore not treated in detail here. Only a brief overview is presented to

provide a guide to typical forms of the models and to illustrate tne types of

parameters that can be determined. In addition, some measurement approaches

are suggested. There is, however, no definitive set of transistor parameters

which can be prescribed as a critical set. The importance of each parameter

depends on too many factors specific to ci e quality of the process and the

demands of the product circuit.

"Normally-off

" Enhancement-Mode Transistors . For "normally-off , or enhancement-mode, MOSFETs , an idealized model [Sze, 1981, •_>. 438] gives the

linear region drain current for small VD as

*D = l “s

C ox ( V

G

- V

t) v

r,

; (linear) (6)

and, when the transistor is operated in the saturated region with VD >

( VG

" VT

} ' as

I Dsat

Z2L P s Cox (saturated) (7)

where all symbols are defined in table 1 1 - In the linear region, the channel conductance is described by

31. q = D 3V„

D

V constant

G

Z , . = t y c [v - v ) L s ox ^ G T J

and the transconductance j ? given as

am constant

A conduction factor may be defined as

(linear) (8)

(linear) (9)

11
K =

31

1 D

2 V 3V

D G V constant

D

which, for this model, is then given by

K = ~ u C

2L s ox

In the saturated regime, the transconductance is

gmsat LM s C ox

(VG

“ V

T

J '

and the conduction factor becomes

( linear ) (10)

(linear) (11)

(saturated) (12)

or

Ksat

2

3 vgJ V constant

D

(saturated) (13)

K

sat

(saturated) (14)

In a method described by Buehler [1983], following a procedure proposed by

Ham [1980], eight drain current measurements are made to determine seven device parameters which characterize the linear and saturation portions of

the MOSFET current- voltage operating characteristics. The determined device

parameters are the threshold voltage, conduction factor, and transconductance, each measured in the linear and in the saturated regions, and also the

output conductance in the saturation region. The procedure involves twopoint estimations of the parameters, based on the partial derivative definitions given above.

There are different ways to define MOSFET operating parameters, and in most

cases more detailed information may be obtained at the expense of additional

time and effort. On the other hand, less complex measurements may provide

misleading or erroneous results.

A good example of the tradeoffs is the threshold voltage measurement. The

threshold voltage reflects the various oxide charges and surface doping [Sze,

1981]. The value of the threshold voltage in the linear operating region may

be ambiguous since there is no clear turn-on; instead there is initially a gradual exponential increase of drain current with gate voltage due to the

diffusion current.

The simplest definition of threshold voltage is the gate voltage required to

pass a prescribed drain current for a specified value of drain voltage.

Because of the diffusion current, this single operating point definition may

give an erroneous result. Also, use of this definition requires additional

knowledge to assure the particular transistor is operating properly; for

example, it must be known that there is no significant gate-leakage current

or that the drain-substrate junction breakdown voltage is not exceeded. A

definition based on a two-point procedure involving linear extrapolation to

12
zero current [Buehler, 1983] requires additional measurement time, but provides greater assurance that the determined value is reliable. Alternatively, ASTM Standard Method F 617-79, "Measuring MOSFET Linear Threshold Voltage," requires measurement of several values of drain current for different

gate voltages, at a fixed drain voltage, to determine the maximim slope of

the drain current-gate voltage curve. The more complex procedures may be

worthwhile because they involve examination of the behavior of the device

current-voltage relationship. In a sense, they provide screening or qualification criteria that may save time because there is a higher probability of

identifying and eliminating defective devices. Characteristic parameters

other than the traditional ones may be defined and measured and sometimes

additional useful information may be gained.

According to Takacs [1980], another useful parameter is the peak transconductance, gm peak' which is the maximum slope in the measured I D versus VG curve

and occurs near VT

. The peak transconductance may be useful since it does

not require a measurement of threshold voltage, is not a function of oxide

charge variation, and is easy to measure experimentally using a lojk.-in

amplifier. It can be used to monitor gate length using data from a series of

transistors of different gate lengths. This may be done by plotting the

mask-defined mask

1 versus

q

m, peak

using the equation

^m, peak

k liJlnask f L , - AL ] v mask > (15)

The proportionality constant k is determined by the slope jf the line or from a single data point on a transistor where Lmas^

is much larger than AL.

Gate dielectric breakdown strengths, source- to-drain breakdown strengths, and

source-to-drain leakage currents are also important parameters which may be

measured on transistors to characterize the materials and the process. The

values of voltage or current used in these tests ave chosen to reflect the

range of operating points expected for th€j device.

A sequence of several transistors having different dimensions allows more precise determination of the material parameters and the dimensional parameters than can be obtained using only one device. As an example the surface

mobility calculated for one transistor should be that calculated for a second

transistor with different dimensions (assuming that short-channel effects are unimportant). Such a comparison verifies that a suitable model is being

obeyed. Therefore, data on a series of transistors can be used to plot I n as a function of Z/L for the same VG and VD

; the slope of the resulting

linear fit can be used to obtain a value for (eq (6)]. Cox is determined

from an appropriate MOS capacxtor nearby and Z and L are the design dimensions. If the surface mobility varies in a systematic fashion with design

gate length, it could b^ evidence for lateral diffusion of the oource/drain

dopant. A simpler analysis has been demons t rated co determine systematic

deviations in gate length and gate width from design values while accounting

for parasitic resistance in series with the channel resistance [(.hern ' . ,

1 980]

.

There are two groups of transistors in TERRY-2. One group contains sr.u i

1 , practical-style devices labeled T1 through T21 ; the other group contains

13
wider gate devices labeled TNI through TNI 0 (and triple-gate devices labeled

TN1 1 through TNI 6, discussed in a following section).

Among the practical-style transistors, T1 through T6 are enhancement-mode

devices having polysilicon 1 or 2 gates. Within each gate type, there is a minimum design-rule gate length device (T1 and T4 ) , a device having twice the

gate width (T2 and T5), and a device having twice the gate length (T3 and

T6 ) . Among the TN series, TNI has a polysilicon 1 gate and the minimum gate

length; TN2, TN3, and TN4 have successively longer gate lengths. The se- quence TN5 through TN8 repeats the series except that the gates are formed of

polysilicon 2. Transistors TN9 and TN10 are polysilicon 1 -gated and polysilicon 2-gated devices whose channel length is much longer than their width.

Among the practical-style enhancement-mode transistors are some devices that

only serve to provide specialized information about the process or materials,

rather than information about a realistic device characteristic. Transistors

T1 3 and T1 4 have a stripe of column channel stop in their channel regions and

gates of polysilicon 1 and polysilicon 2, respectively. These transistors

are meant to be used to investigate the breakdown properties of the column

channel stops used in the CCD array.

Transistors T1 5 and T1 6 have field oxide rather than gate oxide under their

gates. Both have gates formed of polysilicon 2, but T1 6 also has a stripe of

field channel stop in the conducting channel. Transistor T1 7 is similar,

except that it has gate oxide and a stripe of the field channel stop. Transistor T1 8 is similar to T1 5 (field oxide, no channel stop), except that the

gate is aluminum. These four devices are intended for use in examining the

effectiveness of the field channel stop and the degree of protection against

parasitic transistor action. The threshold voltage of these devices may also

be monitored before and after environmental exposure.

"Normally-On" Transistors . The properties of "normally-on" or depletion-mode

transistors are determined by the properties of the implant which forms the

conducting channel and are controlled by the gate-to-channel voltage and the

channel- to-substrate voltage. There are three contributions to the drain-tosource current, depending upon the condition of the semiconductor surface:

the carrier concentration in the undepleted portion of the channel, the current reduction due to the depletion of carriers in the channel-substrate

depletion region, and when the surface is accumulated, the excess accumulated

carriers. Several models have been developed to describe these effects

[Huang, 1973; Huang and Taylor, 1975; and Edwards and Marr, 1973],

In the model of Huang and Taylor [1975], the drain current of a depletionmode transistor is related to the gate, drain, and substrate potentials

through an average capacitance C which relates the gate voltage to the

amount of mobile charge in the channel. The model assumes that the conducting channel may be approximated by a step profile. For a conducting channel

formed by an n-type implant into a p- type substrate, when the gate voltage is

adjusted so that the surface is depleted, the drain current is given by:

I =— mJq.V + C f f V -V ]V - — v2 1 D L

M Bl y i DS GS FBJ DS 2 DS -I -4f2K eqN ,) 1/2 [fv +v . + v j 3 / 2 _ r v + v .] 3 / 2 l| . 3 s 0H A' > L ( RS Hi DS > y RS Ri / J J

(16)

14
While the equation for the depletion-mode transistor drain current is more complicated than the enhancement-mode equation, the characteristics are very

similar. If the drain- to-source voltage is small, then the device is pinched

off uniformly along the channel at some voltage V>p which may be called the

threshold voltage. The threshold voltage is given by

A plot of VT versus (VBS + V

B

^)l/2 will have an intercept on the VT axis

of -y^/C + VFB . C is determined by the slope of the curve near VBS +

VB ^ = 0. The flatband voltage VFB is determined by a 1 -MHz C-V curve on

the ga te-to-buried-channel capacitors (T102 to T106). The total activated

implant may be then determined from the intercept.

This method of measuring the total implant, proposed by Huang and Taylor

[1975], underestimates the actual total activated implant by 20 percent ac- cording to their data for a 6 x 10*1 cm“2 implant which is ~0.5 pm deep. It

is probably less accurate for deeper implants. Still, this threshold technique might serve as a precise but inaccurate method of process monitoring.

Techniques similar to those described for the surface channel enhancementmode transistors can be applied to the depletion-mode transistors.

The bulk trap concentration and emission krretics may be measured using a depletion-mode transistor using a technique due to Collet [1975]. The transistor is biased very close to pinch-off so that only a email current flows.

The gate bias is pulsed to increase the current; during this time, the con- ducting portion of the channel increases in thickness. Bulk traps now included in the conducting channel which were above the Fermi level are moved

below the Fermi level and the traps are filled. When the gate pulse ends,

the conducting channel is again nearly pinched oft. As the filled traps in

the surface depletion region emit charge, che depletion region thickness is

reduced, further increasing the channel thickness. A steady-state current is

reached only some time, determined by the emission rate of the traps, after

the original gate bias is restored. The current transient may be modeled, as

in deep-level transient spectroscopy, to find the bulk trap concentration and

the trap emission kinetics. Possibly, the trap concentration can be profiled

as a function of depth. This measurement should be sensitive to those traps

in the implanted layer which affect the performance of buried-channel CCDs.

Triple-Gate Transistors . The tripie-gate transistors are surface channel

(enhancement-mode) devices wich three separately connected, overlapping

gates. Their gate widths are the same as most of the wider gate TN series.

Triple-gate transistors are labeled TNI 1 through TN16. Three transistors

have center gates of layer polysilicon 1 (TNI 3, 14, and 1 6) and three of

layer polysilicon 2 (TNI

i

e 12, and 15). The center gate channel lengths aro

10, 20, or 30 pm, and the outer gate channel length is 10 pm.

Triple-gate transistors are intended to be used for a variety of nonroit in*-,

but potentially very valuable, measurements relevant to the ch i rac t>> r i /. i * i• <n of interface and oxide traps. The unique capability provided by trip! '-<!

>

f -•

(17)

15
transistors is that MOS capacitor and reverse-bias junction leakage measurements can be performed on a single gate, a gate that can also be used to measure transistor properties. With the outer gate biased to the flatband

voltage, the center gate is isolated and can be used for MOS capacitor measurements, for example, using transient capacitance or admittance methods to

determine the interface state density. With the outer gates biased to strong

inversion, the center gate can be used, as in a gated-diode measurement, to measure the surface recombination velocity. Since the surface recombination

velocity is the product of the interface state density and capture cross

section, a determination of the capture cross section near midgap can be

made. This quantity is otherwise very difficult to measure accurately [Nicollian and Brews, 1982, p. 221].

In addition, the interface state density on the center gate can be measured

using charge pumping techniques (see Appendix). The measurement of interface

state density using charge pumping has not been quantitatively evaluated by

comparison with another more completely understood method using the same interface. If these devices can be used to interpret charge pumping results,

or even to calibrate the charge pumping current against a more reliable interface state density method, it is possible that the easy-to-perform charge

pumping technique could be used reliably on the smaller transistors and could

become a new "routine" measurement.

Furthermore, the opportunity is available to compare interface state measurements with transistor transport measurements, and to address such issues as the effect of interface state density on transconductance.

The triple-gate transistors can also be used to measure relative misalignment

in the direction of the channel current flow between the polysilicon layers

and the source-drain layer. The procedure is similar to the peak transconductance method of Takacs [1980]. In this application, the transconductance

is measured separately in each outer gate of a device, while the other outer

gate and the center gate are held in strong inversion. The misalignment AX

between the polysilicon-1 level and the source-drain level is given by [Takacs, 1980]

2 *^g (outer gate left) g (outer gate right) ' ' m m where L' and gm

' are the effective channel length and transconductance

from a single-gate transistor having the same polysilicon layer gate type as the outer gates on the test device and the same gate width, and gm (outer

gate left) and gm (outer gate right) are the transconductances of the left

and right outer gates, respectively. The single-gate transistor length and

transconductance provide an empirical relationship between gate length and

transconductance for the polysilicon layer being measured. However, it does

not matter which layer is being measured; the result always gives the relative misalignment between the polysilicon-1 layer and the source-drain layer.

This is shown in figure 82.

Large Area Capacitor/Transistors . There are a great number of ac measurement

techniques involving capacitance and conductance as a function of time, frequency, and dc bias voltage, applicable to MOS structures. (See e.g., the

16
Simmons and DeClerck articles in Zemel, 1S79; Nicollian and Brews, 1982; and

Sze, 1981.) These techniques can be used to obtain information on the electrical characteristics of the MOS structure, including the oxide layer, the

oxide-silicon interface, and the bulk silicon substrate. Examples of characteristics amenable to measurement include:

for the oxide: trapped charge density, neutral trap density, dielectric breakdown strength, and thickness;

for the interface: trap density, trap energy distribution, trap

capture/emission rates, and fixed charge density;

and

for bulk silicon: deep-level trap density, trap energy, trap

capture/emission rates, shallow-level (dopant) profiles, and minority carrier lifetime.

The most common MOS measurement is probably the high-frequency capacitance

versus bias voltage measurement. From this measurement it is possible to

obtain or estimate the oxide thickness, threshold voltage, flatbanc. voltage,

silicon dopant density, interface state density (for relatively large values

of interface states by today's integrated circuit standards), and minority

carrier lifetime. Special considerations must be applied to the polysilicon

gate capacitors because of depletion effects in the polysilicon [Yaren and

Frohman-Bentchkowsky , 1980].

In TERRY-2, there are six MOS structures of interest. They are the two polysilicon layers and their respective gate oxides over the substrate ( p- type

epilayer), the n~ implant, and the n° implant. To address each of these

structures and to provide optimal structures for a variecy of measurements,

eight large capacitor/transistor test structures are available. For each

polysilicon-gate oxide pair, there is a capacitor (Cl cr C2), enhancementmode transistor (T101 or T102), and two depletion-mode transistors (T103 or

T1 04 for the n~ implant and T1 05 or T1 06 for the nO implant). The depletionmode transistors can be thought of, and treated as junction-isolated MOS

capacitors where the "substrate" is the implant layer* the source-and-drain

connections provide contacts to the "substrate. " The arrangement of two

separate substrate contacts on opposite sides jf the gate conveniently forms

a transistor and allows the performance of additional types of measurements,

such as pinch-off voltage and deep- level transient spectroscope ( DLTS ) using

a deep depletion MOS transistor [Collet, 1975J. The depletion-mode transistor measurements on these large devices can be compared with results obtained

on the smaller, practical-size transistors. Similarly, the large

enhancement-mode transistors (T101 and T102) can be used to provide data for

comparison with the smaller transistors.

The large depletion-mode transistors provide a convenient junction (either

n“-substrate or n °-substrate) for dopant profiling through the epilayer : , the substrate using high-frequency capacitance-voltage techniqc -a. The lar je

enhancement-mco^ us vices (T101 and T102) ran be to profile using the dc

MOSFET copant profiling technique [Buehler, 1980, and Carver, 1983..

The large depletion-mode transistors are uxso intended for use a-- spreading

resistance samples for profiling the implanted layers. They ar> located at

the top edge of the chip for ease in beveling. These devices are large

enough to allow several measurements to be made on each device for assessing

17
the reproducibility of the measurement. Also, the devices are large enough

to permit a suitably shallow bevel angle for high resolution in the profile

depth scale.

In addition, the large capacitors and transistors can be used to perform

deep-level transient spectroscopy (DLTS ) measurements for bulk and surface

trap parameters [Tredwell and Viswanathan, 1980],

Gated Diodes and Gated-Diode Electrometers . The gate-controlled diode structure is a useful device for studying the effects of the interface, and spacecharge regions at the interface, on the behavior of p-n junctions [Grove,

1967], These effects primarily involve generation/recombination processes

and they cause excess reverse-bias leakage current in the diode and a reduction in the junction reverse-bias breakdown voltage. In CCDs, these effects

lead to higher levels of dark current. (Even in buried-channel CCDs, higher

dark current levels are experienced due to intersection of depletion regions

at the periphery of the gates with the interface.) Also, bulk leakage sources can be monitored, including depth profiling of bulk leakage sources.

(Leakage sources in the bulk are deep-level traps where generation and recom- bination can take place.

)

The gated-diode electrometer is a test structure that combines a MOSFET electrometer amplifier with a gated diode [Carver and Buehler, 1980]. Instead of

measuring the small leakage currents, typically picoamperes, directly in

series with the high impedance of the reverse-biased junction, a voltage

transient at the output of a source-follower amplifier is measured. The

junction is initially reverse-biased and disconnected from the voltage

source. The leakage currents discharge the depletion capacitance and the

voltage across the junction is dissipated. The voltage decrease is monitored

by the electrometer amplifier. With this arrangement, leakage current mea- surements are more accessible to automated measurement systems.

Grounds and Probe Placement Detectors . In various places, as space dictated,

pairs of probe pads are connected together. Some of these pairs are grounded

(device G) and some are ungrounded (P). These devices can provide assurance

of proper placement of probes and continuity between probe pads.

Devices GG are grounded bonding pads.

MEASUREMENT PROGRAM AND TEST RESULT EVALUATION

The implementation of a test chip measurement program depends on a variety of

factors which may change with time as the process evolves and as test results

are accumulated and evaluated. Initially, it is necessary to [Linholm, 1981,

p. Ill:

1. Identify and measure process parameters, both fundamental materials

parameters and device characteristics, which can be used to characterize the degree of process control to and accurately predict process performance; and

2. Establish the ranges and uniformities of these materials parameters

and device characteristics and determine the correlations between

18
their variations over a wafer, from wafer-to-wafer within a lot, and

from lot-to-lot.

Only after the completion of these two steps can a minimum set of measurements be established and procedures set up to monitor excursions from ex- pected results and to collect data to identify the source of unexpected process performance variations. It is important that these principles are un- derstood by those implementing a test chip metrological program.

The first version of a test chip should contain test structures suitable for

measuring accessible and appropriate material properties, even though their

ranges and acceptable variations may not be known beforehand. Therefore, the

initial design of a test chip should contain a broad spectrum of test structures and representative devices to characterize the process and the intended

product performance. In order to characterize a new process, or one previously untried for a given product or performance level, new unproven test

structure designs and test methods may have to be used in addition to the set

of fully characterized devices and test methods already known to be dependable and proven in use. Every process is different; the critical, yield- or performance-limiting parameters are different. These critical parameters

will likely change with time as process control improves and the process

evolves to maturity. In addition, certain critical parameters relating to

product performance may require more sophisticated (non-automated) test methods.

Buehler [1983] identifies six use categories of test structures. TERRY-2 was designed to address only two of these areas judged to be key ones for CCD

performance and process control: device parameters and process parameters,

including processed materials properties. In the case of TERRY-2, prior

knowledge of the maturity of the process and of the CCD performance, both

before and after environmental exposure, facilitated some decisions related

to the design and selection of test structures. A broad variety of process

and device parameters are addressed and there are many devices aimed at characterizing interface and bulk trap distributions spatially and energetically.

Most of these latter devices are capacitor/transistors, gated diodes, and

multigate transistors. Some test methods suggested for measuring interface

and bulk traps are promising, but they may not be practical in a production

environment and they are unproven and untried on the CCD process. Most of

these methods are mentioned in the previous section; some of them are likely

to provide important and critical information not available from any other

source.

When TERRY-2 is included in the CCD process (as a drop-in), all test devices

should be measured. The initial test results must be obtained and interpreted quickly so they can be used to correct or improve the process [T\nholm, 1981] and to:

1. Provide averages and standard deviations of all process parameters

to determine statistically significant variations.

2. Provide average and standard deviations of parameters across a wafer, between wafers in a given lot, and between lots.

19
3. Determine which of the promising, but not yet evaluated on this CCD

process, devices and techniques can be used to provide information

on critical parameters, including environmental effects.

4. Develop a realistic test program which will provide information

useful to monitor the process performance, to characterize the materials, and to evaluate critical parameters related to the desired

performance of the CCD.

When the process is determined to be under acceptable control, the initial

test program may be reduced to a less complete set of test chip measurements.

In this sense, a test chip and the associated test methodology are like an insurance program. The criteria which determine which properties should be

routinely measured and how often they should be measured include whether the

parameters lie within target design windows, the size of the parameter variations, and the amount of effort required to obtain the information. Only the

data can provide the input needed by process engineers to make meaningful

judgments and decisions.

The key attribute of a successful test program is the efficient handling and

evaluation of test data so that important conclusions about the acceptability

of the results can be reached quickly.

REFERENCES

Bach, H. G. , and Fahrner, W. R. , Properties of MOS Structures with Buried

Layers as Deduced from Nonequilibrium C(V) Measurements, j. Appl . Phys.

53 , 3848, (1982).

Brugler, J. S., and Jespers, P. G. A., Charge Pumping in MOS Devices, IEEE

Trans. Electron Devices ED- 16 , 193 (1969).

Buehler, M. G. , Grant, S. D. , and Thurber, W. R. , Bridge and van der Pauw

Sheet Resistors for Characterizing the Line Width of Conducting Layers, j.

Electrochem. Soc . 125 , 650-654 (1978).

Buehler, M. G. , and Thurber, W. R. , An Experimental Study of Various Cross

Sheet Resistor Test Structures, J. Electrochem. Soc. 1 25 , 645-650 (1978).

Buehler, M. G. , Comprehensive Test Patterns with Modular Test Structures:

The 2 by N Probe-Pad Array Approach, Solid State Technology 22 (10), 89-94

(October 1979).

Buehler, M. G. , The D-C MOS FET Dopant Profile Method, J. Electrochem Soc.

127, 701-704 (1980).

Buehler, M. G. , Microelectronic Test Chips for VLSI Electronics, N. G. Einspruch and G. B. Larrabee, Eds., VLSI Electronics: Microstructure Science,

Vol. 6 (Academic Press, New York, 1983).

Carver, G. P. , Influence of Short-Channel Effects on Dopant Profiles Obtained

from the DC MOSFET Profile Method, IEEE Trans. Electron Devices ED-30, 948-

954 (1983).

20
Carver, G. P. , and Buehler, M. G. , An Analytical Expression for the Evaluation of Leakage Current in the Integrated Gated-Diode Electrometer, IEEE

Trans. Electron Devices ED-27 , 2245-2252 (1980),

Carver, G. P. , Linholm, L. W., and Russell, T, J. , Use of Microelectronic

Test Structures to Characterize IC Materials, Processes, and Processing

Equipment, Solid State Technology 23 (9), 85-92 (September 1980),

Carver, G. P. , Development of Test Structures for Characterization of the

Fabrication and Performance of Radiation-Hardened Charge-Coupled Device (CCD)

Imagers: Annual Report, May 15, 1980 to May 14, 1981, NBSIR 81-2319 (August

1981 ) .

Chern, J. G. , Chang, J, P. , Motta, R, F., and Godhinho, N. , A New Method to

Determine MOSFET Channel Length, IEEE Electron Device Letters EDL-1 , 170

(1980).

Collet, M. G. , An Experimental Method to Analyze Trapping Centers in Silicon

of Very Low Concentrations, Solid-State Electronics 18, 1077 (1975),

Edwards, J. R. , and Marr, G. , Depletion Mode IGFET Made by Deep Ion Implantation, IEEE Trans. Electron Devices ED-20 , 283-289 (1973).

Feigl, F. J. , Characterization of Dielectric Films, N. G. Einspruch and G.

B. Larrabee, Eds., VLSI Electronics: Microstructure Science, Vol . 6 (Academic Press, New York, 1983).

Groseneken, G. , Maes, H. E. , Beltran, N. , and de Keer smaeker , R. F., The

Energy Distribution of Si/Si02 Interface States Measured in Small Size

MOSFETS using the Charge Pumping Technique, to be published in Proceedings of

the INFOS Conference, Eindhoven, April 11, 1983 (North Holland Publishing

Co. )

.

Groseneken, G. , Maes, H. E. , Beltran, N. , and de Koersmaeker, R. F., A Reliable Approach to Charge-Pumping Measurements in LOS Transistors, IEEE Trans.

Electron Devices ED-31, 42-53 (1984).

Grove, A. S., Physics and Technology of Semiconductor Devices (John Wiley,

New York, 1 967 )

.

Ham, W. E., Semiconductor Measurement Technology: Comprehensive Test Pattern

and Approach for Characterizing SOS Technology, NBS Spec. Publ. 400-56 (January 1980).

Huang, J. S. T. , and Taylor, G-. W., Modeling of an Ion Implanted Silicon Gate

Depletion Mode IGFET, IEEE Trans. Electron Devices ED-22_. 995- i 001 (1975).

Linholm, L. W., Semiconductor Measurement Technology: The Design, Test and

Analysis of a Comprehensive Test Pattern for Measuring CMOS/SOS Process in

Performance and Control, NBS Spec. Publ. 400-66 (August 1981).

21
Ma, Y.-R., and Wang, K. L. , A New Method to Electrically Determine Effective

MOSFET Channel Width, IEEE Trans. Electron Devices ED-29 , 1825 (1982).

Markel, G. , Ion Implantation of MOS Transistors Depletion Mode Devices, F. Van de Weile, W. L. Engle, and P. G. Jespers, Eds., Process and Device

Modeling for Integrated Circuit Design (Noordhoff, Leyden, 1977).

Nicollian, E. H. , and Brews, J. R., MOS (Metal Oxide Semiconductor) Physics and Technology (John Wiley, New York, 1982).

Proctor, S. J. , Linholm, L. W., and Mazer, J. A., Direct Measurements of

Interfacial Contact Resistance, End Contact Resistance, and Interfacial Contact Layer Uniformity, IEEE Trans. Electron Devices ED-30 , 1535-1542 (1983).

Russell, T. J. , Wilson, C. L. , and Gaitan, M. , Determination of the Spatial

Variation of Interface Trapped Charge Using Short-Channel MOSFETs , IEEE

Trans. Electron Devices ED-30 , 1662-1671 (1983).

Simmons, J. G. , and Wei, L. S., Theory of Dynamic Charge Current and Capacitance Characteristics in MIS Systems Containing Distributed Surface Traps,

Solid-State Electronics 16, 53 (1973).

Sze, S. M. , Physics of Semiconductor Devices, 2nd edition (John Wiley, New

York, 1981).

Takacs, D. , Muller, W., and Schwabe, U. , Electrical Measurement of Feature

Sizes in MOS Si 2 -Gate VLSI Technology, IEEE Trans. Electron Devices ED-27 , 1368 (1980).

Tredwell, T. J. , and Viswanathan, C. R., Determination of Interface-State

Parameters in a MOS Capacitor by DLTS , Solid State Electronics 23, 1171—

1178 (1980).

Yaron, G., and Frohman-Bentchkowsky , D. , Capacitance Voltage Characterization

of Poly Si-Si02 -Si Structures, Solid State Electronics 23, 433-439 (1980).

Zemel, J. N., Ed., Nondestructive Evaluation of Semiconductor Materials

and Devices (NATO Advanced Study Series, Plenum Press, New York, 1979).

22
Table 1

.

Layer and Mask Labels.

Defining Conductivity

Process Layer or Feature Note Mask Type

Field channel stop (a) CS1 P

Source/drain (b) DIFF n Gate oxide (c) TO - n~ implant (d) NW n

/•jO implant (d) NW2 n Image area column channel stop (e) CS2 P

Polysilicon 1 (f) PS1 n Polysilicon 2 (f) PS2 n Contact window (g) CT - Aluminum (h) AL - Passiva tion (i) PAD -

(a) Allows the inactive field region to be doped to increase the field

threshold.

(b) Allows the diffusing or implanting of sources or drains cf

transistors, CCD input and output diodes, and undercrossi igs

.

(c) Removes all oxide over CCD gate area, transistor gate area, ecc.

(d) NW and NW2 are two masks for doping the silicon surface for (1) the

CCD buried channel and (2) optional depletion-mode transistors in the

input and output circuitry.

(e) Defines the well areas in the CCD.

(f) PS1 and PS2 define the gates of the CCD or transistors and other

structures.

(g-i) These mask levels have the usual functions in an MOS process.

23
Table 2. Minimum Geometry Design Rules.*

Level/Mask Layer Rule Definition

Minimum Nominal

Distance

( pm)

Source/Drain (DIFF) width 7.5

source-to-drain spacing 1 0.0

spacing- to-channel stop 12.5

overlap of thin oxide cut 2.5

overlap of contact window 5.0

Field Channel Stop (CS1

)

width 5.0

Column Channel Stop (CS2) width 2.5

Thin Oxide (TO) width 5.0

overlap of contact window 2.5

n~ Implant (NW) width 5.0

overlap of thin oxide 2.5

First Polysilicon (PS1)/ width 7.5

Second Polysilicon (PS2) same-level poly silicon- topolysilicon spacing 2.5

overlap of channel stop 2.5

overlap of contact window 2.5

overlap of source/drain

overlap between polysilicon

2.5

levels 2.5

Contact Window (CT) width 5.0

Aluminum (AL) width 10.0

aluminum- to-aluminum spacing 12.5

overlap of contact window 5.0

* Note that these design rules apply specifically to test chip TERRY-2

are related to the design rules for the CCD but do not correspond to

They

them.

24
Table 3. Cross-Bridge Sheet Resistors

Parameters determined: Sheet resistance and linewidth of various conducting

layers.

Device

Designation Cell*

Conducting

Layer

CB1 1 n

+ source/drain

CB2 7 polysilicon 1

CB3 2 polysilicon 2

CB4 3 aluminum

CB5 4 n~ implant

CB6 8 n~ implant

CB7 9 n“ implant

CBS 10 n° implant

CB9 11 nO implant

CB1 0 18 column channel

stop

CB1

1

23 p~ epi layer

*Cell designations are identified in the

Specifications and Notes

(dimensions in ym)

nominal linewidth: 10.0

nominal linewidth: 10.0,

polysilicon 1 over gate oxide

nominal linewidth: 10.0,

polysilicon 2 over gate oxide

nominal linewidth: 10.0

nominal linewidth: 10,0 same as CB5, except gated

using polysilicon 1 same as CB5, except gated

using polysilicon 2 nominal linewidth: 10.0

same as CB8, except wi th

polysilicon-2 gate

linewidth determined by n

+ boundaries, nominally 10.0 same as CB10, except no column channel stop implant

section entitled “Layout."

25
Table 4. Contact Resistors

Parameters determined: Interfacial contact resistance, end contact resistance, front contact resistance, and specific contact resistance.

Device Conducting Contact Window

Designation Cell Layers Edge Length (ym)

CR1 1 3 Metal-source/drain 5.0

CR2 16 Me tal-source/drain 10.0

CR3 11 Me tal-source/drain 20.0

CR4 2 Metal-polysilicon 1 5.0

CR5 3 Metal-polysilicon 1 10.0

CR6 4 Metal-polysilicon 1 20.0

CR7 8 Metal-polysilicon 2 5.0

CRB 9 Metal-polysilicon 2 10.0

CR9 10 Metal-polysilicon 2 20.0

26
Table 5. Transistors.*

Parameters determined: Threshold voltage (enhancement devices), pinch-off

voltage (depletion devices), interface state density (enhancement devices), and

transistor properties.

Practical-Style Transistors

Enhancement (E)

Device or Channel Gate Oxide

Designation Cell Depletion (D) Layer Layer Type W/L ( u m)

T1 5,23 E epi(p) PS1 gate 60/1 0

T2 1 E epi( p

)

PS1 gate 120/10

T3 2 E . epi( p) PS1 gate 60/20

T4 6,23 E epi

(

p) PS2 gate 60/10

T5 3 E epi( p) PS2 gate 120/10

T6 4 E epi( p) PS2 gate 60/20

T7 7,17 D n~ PS1 gate 60/10

T8 15 D n PS1 gate 120/10

T9 16 D n PS1 gate 60/20

T10 6,17 D n~ PS2 gate 60/10

T1

1

8 D n PS2 gate 120/10

T1 2 9 D n~ PS2 gate 60/20

T1 3 21 E CS2 PS1 gate 60/1 5 T1 4 10 E CS2 PS2 gate 60/1 5

T1 5 22 E epi (p) PS2 field 60/10

T16 22 E CS1 PS2 field 60/15

T17 16 E CS1 PS2 gate 60/1 5 T1 8 1

1

E CS1 AL field 60/1 5 T19 11 ,14 D nO PS2 gate 60/10

T20 2,15 D n° PS2 gate 120/10

T21 3 D n° PS2 gate 60/20

Wide-Gate Transistors

TNI 19 E epi( p) PS1 gate 230/1

0

TN2 1,20 E epi ( p) PS1 ga te 230/1

5

TN3 12 E epi( p) PS1 gate 230/20

TN4 13 E epi(p) PS1 gate 230/30

TN5 4 E epi(p) PS2 gate 230/1

0

TN6 5 E epi(p) PS2 gate 230/1

5

TN7 6 E epi( p) PS2 gate 230/20

TN8 7 E epi (p) PS2 gate 230/30

TN9 13 E epi(p) PS1 gate 55/160

TNI 0 14 E epi(p) PS2 gate 55/160

27
Table 5. Transistors (cont'd).

Triple-Gate Transistors**

Device Center Gate Center Gate Outer Gate Outer Gate

Designation Cell Layer Length ( pm) Layer Length ( pm)

TNI 1 1 ,6,22 PS2 10 PS1 10

TNI 2 13 PS2 20 PS1 10

TNI 3 16,19 PS1 10 PS2 10

TNI 4 19 PS1 20 PS2 10

TNI 5 5 PS2 30 PS1 10

TNI 6 7 PS1 30 PS2 10

*Among the practical-style transistors, all are of the radiation-hard

extended-gate design except T1 in cell 5, T4 in cell 6, T7 in cell 7, T1 0 in

cell 6, T19 in cell 14 , and T20 in cell 15. Of the wide-gate transistors,

only TN2 in cell 1 is the radiation-hard design. Only TNI 1 in cell 22 and

TNI 3 in cell 19 are the radiation-hard design among the triple-gate

transistors. T1 5 and T1 6 in cell 22 and T18 in cell 1 1 are not radiationhard because they have field oxide under the gate. The p-type regions in

the channels of T13, T14, and T1 6-T1 8 are confined to 5-pm wide stripes in

the center of the channel.

**All triple-gate transistors are enhancement-mode, in the p-type epi layer.

Gate widths are 230 pm.

28
Table 6. Large Capacitors and Transistors *

Parameters determined: Dopant profile (spreading resistance, capacitancevoltage where possible), capacitance-voltage properties, transistor

properties (including threshold and pinchoff voltages, where applicable),

interface properties, bulk traps in n~ buried layer (where applicable).

Comparisons can be made between thick and thin regions (except for T105

and T1 06)

.

Device

Lgnation Cell Channel Gate Notes

Cl 20 epi (p

)

polysilicon 1 surface capacitor

C2 21 epi(p ) polysilicon 2 surface capacitor

T101 20 epi (p

)

polysilicon 1 enhancement-mode

transistor

T1 02 21 epi(p ) polysilicon 2 enhancement-mode

transistor

T103 14,19 n~ polysilicon 1 depletion-mode transistor

T104 15,22 n

~ polysilicon 2 depletion-mode transistor

T105 20 n° polysilicon 1 depletion-mode transistor

T1 06 21 n° polysilicon 2 depletion-mode transistor

*A11 large transistors have a channel length of 255 pm and a channel width

of 425 pm. The active area of the large capacitors is also 255 ym by 425

pm.

29
Table 7. X- and Y-Coordinates of Cell Origins

The coordinates of the cell origins are given relative to the chip origin.

The chip origin is at the lower left corner of the chip. All cell origins

are at the lower left corner of the cell when the cell is "upright." A cell

is upright when the origins of each of the test structures within the cell

are at the left margin of the cell. The master drawings of the test

structures were oriented so that when the test structure designs were digitized and the cells were created by stacking the test structures, the

cells would automatically be stored digitally in an upright orientation.

Certain test structures that lie outside the cells are not in an upright

position on the chip.

cell number coordinates (x,y) in ym

1 (200, 0)

2 (520, 0)

3 (840, 0)

4 (1160, 0)

5 (1800, 0)

6 (2440, 0)

7 (3080, 0)

8 (3720, 0)

9 (4040, 0)

1 0 (4360, 0)

1 1 (4680, 0)

1 2 (200, 1600)

1 3 (520, 1600)

1 4 (840, 1600)

15 (4040, 1600)

1 6 (4360, 1 600)

1 7 (4680, 1600)

1 8 (200, 3200)

19 (520, 3200)

20 (840, 3200)

21 (4040, 3200)

22 (4360, 3200)

23 (4680, 3200)

30
Table 8. X- and Y-Coordinates of Bonding Pad Origins

Designation

Coordinates

(x,y) in Mm

1

L

(40, 4600)

2L (40, 4360)

3L (40, 4120)

4L (40, 3880)

5L (40, 3640)

6L (40, 3400)

7L (40, 3160)

8L (40, 2920)

9L (40, 2680)

1 OL (40, 2440)

1 1

L

(40, 2200)

1 2L (40, 1960)

1 3L (40, 1720)

1 4L (40, 1480)

1 5L (40, 1240)

1 6L (40, 1000)

1 7L (40, 760)

1 8L (40, 520)

1 9L (40, 280)

20L (40, 40)

21

L

(1200, 3920)

22L (1 200, 3680)

23L (1200, 3440)

24L (1 200, 3200)

25L (1200, 2960)

26L (1 200, 2720)

27L (1200, 2480)

28L (1 200, 2240)

29L (1200, 2000)

30L (1 200, 1760)

3 1

L

(1400, 1680)

3 2L (1520, 1880)

3 3L (600, 5040)

34L (560, 4800)

35L (1200, 4640)

36L (1440, 4640)

37L (1680, 4640)

38L (1880, 4800)

39L (1880, 5040)

40L (2440, 5000)

41L (2480, 4800)

4 2L (2160, 4480)

43L (1560, 1440)

Coordinates

Pad Designation ( x, y) in Mm

1R (5040, 4600)

2R (5040, 4360)

3R (5040, 41 20)

4R (5040, 3880)

5R (5040, 3640)

6R (5040, 3400)

7R (5040, 3160)

8R (5040, 29 20)

9R (5040, 2680)

1 OR (5040, 2440)

1 1

R

(5040, 2200)

1 2R (5040, 1 960)

1 3R (5040, 1720)

14R (5040, 1 480)

1 5R (5040, 1 240)

1 6R (5040, 1000)

1 7R (5040, 760)

1 8R (5040, 520)

1 9R (5040, 280)

2QR (5040, 40)

21R (3880, 3920)

22R (3880, 3680)

23R (3880, 3440)

24R (3880, 3200)

25R (3880, 2960)

26R (3880, 2720)

27R (3880, 2480)

28R (3880, 2240)

2 9R (3880, 2000)

3 OR (3880, 1 760)

31R (3680, 1680)

32R (3560, 1880)

33R (4480, 5040)

34R (4520, 4800)

3 5R (3880, 4640)

36R (3640, 4640)

3 7R (3400, 4640)

38R (3200, 4800)

3 9R (3200, 5040)

40R (2640, 5000)

41R (2560, 4600)

42R (2 800, 4480)

4 3R (3520, 1440)

31
Table 9. Bonding Pad Connections.

Pad Designation Device Designation Function

1

L

T103 source-drain

2L G ground

3L GDI outer gate

4L GDI inner gate

5L GD2 outer gate

6L • GD2 inner gate

7L G ground

8L GD3 outer gate

9L GD3 inner gate

1 OL GD4 outer gate

1 1L GD4 inner gate

12L G ground

13L TNI 1 source-drain

14L TNI 1 center gate

1 5L TNI 1 source-drain

1 6L TNI 1 left outer gate

1 7L TNI 1 right outer gate

1 8L TN2 gate

1 9L TN2 source-drai

n

20L TN2 source-drain

21

L

Cl gate

22L T101 source-drain

23L T101 gate

24L T1 01 source-drain

25L T103 gate

26L T103 source-drain

27L T103 source-drain

28L GDA1 reset

29L GDA1 reverse bias voltage

30L GDA1 amplifier supply voltage

3 1 L GDA1 output

3 2L GDA1 inner gate

33L T1 03 source-drain

34L T103 gate

35L Cl gate

36L T1 05 source-drain

37L T105 gate

38L T1 05 source-drain

39L T101 source-drain

40L T1 01 gate

41

L

T101 source-drai

n

4 2L GG ground

43L GDA1 outer gate

43 GDI junction

44 GD2 junction

45 GD3 junction

46 GD4 junction

32
Table 9 Bonding Pad Connections (cont'd)

Pad Designation Device Designation Function

1

R

T104 source-drain

2R T1 gate

3R T1 source-drain

4R T1 source-drain

5R T4 gate

6R T4 source-drain

7R T4 source-drain

8R G ground

9R T7 gate

1 OR T7 source-drain

1 1

R

T7 source-drain

1 2R T1 0 gate

1 3R T1 0 source-drai

n

14R T1 0 source-drain

1 5R T1 9 gate

1 6R T1 9 source-drain

1 7R T1 9 source-drain

1 8R T1 8 gate

1 9R T1 8 source-drain

2 OR T1 8 source-drain

21R C2 gate

22R T1 02 source-drain

23R T102 gate

24R T1 02 source-drain

25R T104 gate

26R T104 source-drain

27R T104 source-drain

28R GDA2 outer gate

29R GDA2 inner gate

3 OR GDA2 output

31R GDA2 amplifier supply voltage

32R GDA2 reverse bias voltage

33R T104 source-drain

34R T1 04 gate

35R C2 gate

36R T106 source-drain

37R T106 gate

38R T106 source-drain

39R T102 source-drain

4 OR T1 02 source-drain

41

R

T102 gate

42R GG ground

43R GDA2 reset

33
Table 10. Devices Listed by Cell

Cell 1

TNI 1 1,2,3,18,19,20

T2 4, 5, 16, 1 7 CB1 6,7,8,13,14,15

TN2 9, 1 0, 1 1, 1

2

Cell 2

CR4 1,2,3,18,19,20

T3 4,5,16,17

CB3 6, 7, 8,1 3,1 4,15

T20 9, 10, 1 1, 1 2

Cell 3

CR5 1,2,3,18,19,20

T5 4, 5, 1 6, 1

7

CB4 6,7,8,13,14,15

T21 9, 1 0, 1 1, 1 2

Cell 4

CR6 1,2,3,18,19,20

T6 4, 5, 16, 1 7 CB5 6,7,8,13,14,15

TN5 9, 10, 1 1, 1 2

Cell 5

GDI 1,2,3,18,19,20

T1 4, 5, 1 6, 1 7 TNI 5 6,7,8,13,14,15

TN6 9, 1 0, 1 1, 1 2

Cell 6

TNI 1 1 , 2, 3, 1 8, 1 9,20

T4 4, 5, 1 6, 1

7

T1 0 6,7,14,15

G 8, 1 3 TN7 9, 1 0, 1 1 , 1 2

34
Table 10. Devices Listed by Cell (cont'd)

CB2

T7

TNI 6

TN8

CR7

T1 1 CB6

P

CR8

T12

CB7

P

CR9

T14

CB9

P

CR3

T19

CB8

T18

G

GD3

GD4

P

TN3

Cell 7

1,2,3,18,19,20

4,5,16,17

6,7,8,13,14,15

9,10,11,12

Cell 8

1,2,3,18,19,20

4.5.16.1 7

6. 7. 8. 9.1 2,1 3,1 4,1 5

10.

1

1

Cell 9

1,2,3,18,19,20

4,5,16,17

6. 7. 8. 9.1 2,1 3,1 4,1 5

10.

1

1

Cell 10

1 ,2,3,1 8,1 9,20

4,5,16,17

6. 7. 8. 9.1 2,1 3,14,1 5

10.

1

1

Cell 11

1 ,2,3,18,19,20

4.5.16. 1 7 6. 7. 8.1 3,14,15

9.10.1 1,12

Cell 12

1,20

2, 3,4, 1 7,18, 19

5, 6, 7,1 4,1 5,1

6

8, 1 3

9/10,1 1,12

35
Table 10. Devices Listed by Cell (cont'd)

Cell 13

CR1

TN9

TNI 2 TN4

1 ,2,3,1 8,1 9,20

4,5,16,17

6. 7. 8.1 3,1 4,1

5

9. 1 0, 1 1, 1 2 Cell 14

G

T103

TNI 0

T1 9

GDA1

1,20

2, 3, 1 8, 1

9

4,5,16,17

6, 7, 1 4, 1

5

8,9,10,1 1,12,13

G

T104

T8

T20

GDA2

Cell 15

1,20

2, 3, 1 8, 1 9

4,5,16,17

6, 7, 1 4, 1

5

8,9,10,1 1,12,13

CR2

T9

TNI 3 T1 7

Cell 16

1,2,3,18,19,20

4, 5, 1 6, 1 7 6,7,8,13,14,15

9, 10, 1 1, 1 2

C3

T7

C4

T10

Cell 17

1.2.3. 1 8,1 9,20

4, 5, 1 6, 1 7 6. 7. 8.1 3,14,15

9. 1 0, 1 1 , 1 2

CB1 0

GDI

GD2

P

Cell 18

1 , 2, 3,1 8,1 9,20

4, 5, 6, 1 5, 1 6, 1 7 7,8,9,12,1 3,14

10 ,1 1

36
Table 10. Devices Listed by Cell (cont'd)

T103

TNI 3

TNI 4

TNI

Cl

T105

T101

Cl

T101

TN2

C2

T106

T102

C2

T102

T13

T104

P

T15

TNI 1 T16

CB1 1 T1

C5

T4

Cell 19

1,2,19,20

3,4,5,16,17,18

6, 7, 8,1 3,14,15

9,10, 1 1,12

Cell 20

1,20

2, 3, 18, 1 9

4,5,16,17

6. 1 5 7.8.1 3,14

9.10.1 1,12

Cell 21

1,20

2, 3, 18,19

4,5,16,17

6, 1 5

7.8.1 3,1 4

9. 1 0, 1 1, 1 2

Cell 22

1 .2.1 9,20

3, 1 8

4,5,16,17

6,7,8,13,14, 15

9.10.1 1,12

Cell 23

1,2,3,18,19,20

4,5, 16, 1 7 6, 7, 8,1 3,1 4,1 5

9, 1 0, 1 1, 1 2

37
Table 11. List of Symbols for Transistor Models

a. Enhancement-Mode MOSFETs

Cox oxide capacitance

Al gate-drain overlap

ID drain current

L channel length

P s surface mobility

VD drain voltage

VG gate voltage

Vs source voltage

VT threshold voltage

Z gate width

b. Depletion -Mode MOSFETs

cox

2s

c

d

o *S

L

^o

V

na

nd

q

Qi

t v

VBS

VDS

VFB

vT

W

gate oxide capacitance

average seimiconductor capacitance

cox cs/^ cox + average capacitance

channel junction depth

silicon dielectric constant

vacuum dielectric constant

relative dielectric constant of silicon

channel length

bulk mobility

N

A

N

D

, composite doping concentration

'a + N

D

substrate doping concentration

average implant doping concentration

electron charge

total active implant

oxide thickness

built-in junction voltage

source-body voltage

drain-source voltage

flatband voltage

threshold voltage

gate width

38
( 0 • 480 )

( 320 , 480 )

( 0

( 0

( 0 . 0 ) ( 320

Figure 1. Cross-bridge sheet resistor CB-1.

320 )

100 )
( 0 , 4 8 0 ) ( 320 , 480 )

( 0 , 0 ) C B 2

Figure 2. Crossr-bridge sheet resistor CB-2,

3 2 0 )

\ 60 )

, 0 )

40
( 0 . 480 )

( 320 , 480 )

irr

( 0 , 320 )

( 320

J

y

/

j

-f—\

i 1 y

\ )

( 0 , 160 ( 3 2 0 ,

( 0 , 0 ) C B 3

( 320

3 2 0 )

160 )

Figure 3. Cross-bridge sheet resistor CB-3.
( 0 , 480 > ( 320 , 480 )

C B 4

Figure 4. Cross-bridge sheet resistor CB-4.

320

3 2 0 )

180 )

• 0 )
320 , 480 )
320 , 480 )

44 B 7
( 0 f 480 > ( 320 , 460 )

3 2 0 )

I 00 )

. 0 )

< 0 . 480 ) ( 320 , 480 )

( 0 ,

( 0 ,

( 0 , Figure 9. Cross-bridge sheet

resistor CB-10. B
( 0 • 480 > ( 320 . 480 )

3 2 0 )

180 )

, 0 ) 48
( 0 . 480 )

( 320 » 480 )

( 0 , 0 ) ( 3 ? 0 . 0 )

Figure 11. Contact resistor CR-1.
( 0 . 480 > ( 320 , 480 )

( 0 . 0 ) C R 2

( 320 t 0 )

50

Figure 12. Contact resistor CR-2
4 8 0 )

( 320 , 480 )

( 0 , 0 ) ( 320 0 ) I Figure 13. Contact resistor CR-3.
( 0 , 480 ) ( 320 , 460 )

C R

z -

Figure 14. Contact resistor CR-4.

320 , 0 )

52
( 0 . 4B0 ) 320 , 480 )

C R 5

Figure 15. Contact resistor CR-5.

( 0 , 0 ) 320
( 0 ' 480 ) ( 320 , 480 )

CR&

Figure 16. Contact resistor CR-6.

320 * 0 )

54
( 0 , 480 ) ( 320 , 480 )

( 0 , 0 ) ( 3 ? 0 . 0

Figure 17. Contact resistor CR-7.
( 0 . 480 ) ( 320 , 480 )

( 0 ,

< 0 ,

( 0 , 0 ) C R 8( 320 . 0 )

Figure 18. Contact resistor CR-8,

56
( 0 , 460 ) ( 320 , 460 )

Figure 19. Contact resistor CR-9.

3 2 0 . 0

( 0 , 0 )
( 0 , 480 ) ( 320 , 460 )

( 0 . 320 )

{ 3 2 0 ,

( 0 ,

/

/ r

c]

Z=1

100 ) i 320

( 0 , 0 ) ( 320

3 2 0 )

100 )

. 0 )

58 Figure 20. MOSFET T-l.
( 0 . 480 ) ( 320 , 480 )

( 0 , 320 ) ( 3 2 0 ,

( 0 ,

( 0 , 0 ) ( 320

3 2 0 )

U0 )

Figure 21. MOSFET T-2.
( 0 . 480 ) ( 320 , 480 >

( 0 , 320 ( 3 2 0 ,

( 0 ,

( 0 , 0 ) T 3

Figure 22. MOSFET T-3.

( 320

3 2 0 )

U0 )

, 0 )

60
( 0 . 480 )

( 320 , 480 )

( 0 , 320 )

( 3 2 0 .

( 0 , 0 ) ( 320

3 2 0 )

I 00 )

. 0 )

Figure 23. MOSFET T-4

.

61
< 0 , 480 > ( 320 , 480 )

( 0 , 320 )

( 3 2 0 ,

( 0 ,

( 0 , 0 ) T 5

Figure 24. MOSFET T-5.

( 320

3 2 0 )

10 0 )

, 0 )

62
( 0 . 480 )

( 3 3 0 , 4 8 0 )

( 0 , 330 ( 3 3 0 ,

( 0

( 0 , 0 )

Figure 25. MOSFET T-6.

( 3 3 0

330 )

100 )

. 0 )
< 0 , 480 ) < 320 . 480 ) U

( 0 , 320 >

( 320 .

( 0 . 0 ) ( 320

3 2 0 )

180 )

. 0 )

64 Figure 26. MOSFET T-7

.
( 0 * 480 )

( 320 , 460 )

( 0 , 320 )

( 320

60 ) < 320

( 0 , 0 )

Figure 27. MOSFET T-8 ,

( 320

3 2 0 )

160 )

. 0 )

6
< 0 . 480 > ( 320 , 480 )

< 0 . 320 )

( 3 2 0 ,

( 0 ,

( 0 . 0 ) T9 ( 320

66

Figure 28. MOSFET T-9.

3 2 0 }

! GO )

. 0 )
( 0 , 320 )

( 320 . 3 2 G )

100 )

( 320 . 0 )

67

Figure 29. MOSFET T-10
< Q . 320 )

( 320 . 320 )

(0,0) (320

Figure 30. MOSFET Trll,

T 1 1

100 )

, 0 )

68
( 0 t 320 )

( 320 , 320 ;

( 0 , 0 ) 320

100 )

. 0 )

Figure 31. MOSFET T-12.
( 0 . 320 )

( 320 , 320 )

T 1 3

Figure 32. MOSFET T-13.

160 )

, 0 )

70
( 0 , 320 )

( 320 , 320 )

( 0 , 0 ) ( 320

9

I &0 )

, 0 )

Figure 33 MOSFET TV14
< 0 . 320 >

( 320 , 320 )

T 1 5

Figure 34. MOSFET T-15,

320

160 )

• 0 )

72
( o , 480 ) ( 320 , 480 )

( 0 , 320 ) ( 320 , 320 )

( 0 , 1 BO )

( 0 , 0 ) T 1 &

( 320 , 0 )

Figure 35. MOSFET T-16.
< 0 . 480 ) ( 3 2 0 *

74

( 0 , 320 )

( 320 ,

T I 7

Figure 36. MOSFET T-17.

4 8 0 )

3 2 0 )

! & 0 )

, 0 )
( 0 . 480 )

( 320 . 480 )

( 0 . 320 )

( 0 .

( 320 , 320 )

T 1 8

Figure 37. MOSFET T-18.

( 0 . 0 ) ( 320 . 0
( 0 • 480 ) ( 320 ,

( 0 . 320 )

( 3 2 0 ,

( 0 . 0 ) T 1 9

4fl0 )

3 2 0 )

16 0 )

. 0 )

76

Figure 38. MOSFET T-19.
( o , 480 ) ( 320 . 480 )

( o . 320 ) ( 320 . 320 )

Figure 39. MOSFET T-20. 320 . 0 )

t ? n
( 0 , 480 ) ( 320 , 480 )

( 0 . 320 )

( 320 . 320 )

T 2 1 Figure 40. MOSFET T-21.

78

( 0 , 0 ) ( 320 , 0 )
( 0 , 480 ) ( 320 . 480 )

< 0 . 320 ) ( 3 2 0 , Q

N

\

(0*160) T| 3 2 0 .

( 0 * 0 ) TN ( 320

3 2 0 )

160 )

Figure 41. MOSFET TN-1.
( 0 t 480 ) ( 320 , 480 )

( 0 . 320 )

( 320 .

( 0 ,

( 0 . 0 ) T N 2

( 320

80

Figure 42. MOSFET TN-2.

3 2 0 )

160 )

, 0 )
( 0 . 480 > ( 320 , 480 )

( 0 .

( 0 ,

( 0 ,

320 )

( 320 ’

0 ) T N 3

3 2 0 )

I 00 )

. 0 )

Figure 43. MOSFET TN-3.
( 0 . 480 ) ( 320 . 480 )

( 0 • 320 )

( 3 2 0 , 320 )

( 0 ,

( 0 . 0 ) T N 4

( 320 . 0 ) Figure 44. MOSFET TN-4

,

82
( 0 . 480 ) < 320 » 480 )

( o * 3 2 0 ) ( 3 20 . 3 ? 0 )

T N 5

Figure 45. MOSFET TN-5.

( 0 , 0 )
( 0 » 480 > ( 320 * 480 )

< 320 , 0 >
( 0 . 480 >

( 320 . 480

Figure 47. MOSFET TN-7.
( 0 , 480 ) ( 320 , 480 )

( 0 . 320 )

( 320 , 320 )

( 0 ,

( 0 , 0 )

320 , 160 )

8

( 320 , 0 ) Figure 48. MOSFET TN-8, 86
( 0 , 480 )

( 380 , 480 ) —

( 0 . 0 ) ( 3 ? 0 . 0 ) Figure 49. MOSFET TN-9.
( 0 , 480 ) ( 320 , 480 )

( 0 . 320 )

( 320 , 320 )

Figure 50. MOSFET TN-10.

320 , 0 )

88
400 ( 320 480 )

3 2 0 )

1 GO )

. 0 )
( 0 , 480 ) ( 320 , 480 )

90

320 )

180 )

, 0 )
( 0 , 480 > < 320 . 4 8 0 )

3 2 0 )

180 )

» 0 )
( 0 , 480 ) ( 320 , 480 )

—( 0 , 0 ) ( 320 , 0 ) T N 1 4 —

92 Figure 54. Triple-Gate MOSFET TN-14.
( 0 , 480 > ( 3 2 0 » 4 8 0 )

3 2 0 )

ISO )

. 0 )
( 0 . 480 ) ( 320 » 4 8 0 )

320 )

160 )

. 0 )
C 480 -&—n * -£-0

( :(

( III

20 )

50 )

/ \

\ /

( 320 , 32

A

( 3 2 0 , I & )

T"O'

; 0""T ^ 0 ~T

95

Figure 57. CapacitorAransistor T-101.
-( 0 , 4 8 0 32=0= 4 a .)-

20 )

( 3 2 0 * 3 2 ]

A / \

\ /

r~\

00 )

i

( 320 . 161

i o i o r no?

i

:T? {F'~U~T

Figure 58. Capacitor/Transistor T-102.

96
j * iSJL £23= -AS- II . i

n

( 20 )

A / \

\ /

( 320 , 32)

r

<

\

0 ) ( 320 , 18)

T U * 0 ) T I 0 3

^- 320 *. [FT

Figure 59. Capacitor/Transistor T-103.


100
( 0 • 480 >

( 0 , 0 ) ( 320

Figure 63. Capacitor C-l.
i!

( 0 , 0 ) ( 320 * 0 ) 102 Figure 64. Capacitor C-2.
0 , 480 ) ( 320 f 4 8 C

C 3

Figure 65. Capacitor C-3

( 320 , 320 )

( 3 2 0 , 180 .)

, 0 )

( 0 , 0 ) ( 320
( 0 , 4B0 ) ( 320 , 480 )

( 0 , 0 ) ( 320 , 0 )
( 0 * 480 ) ( 320 , 480 >

C 5

Figure 67. Capacitor C-5.

( 0 , 0 ) 3 2 0 . 0
( 0 , 4 8 0 ) ( 320 , 480 )

106
( 0 , 480 > ( 320 , 400 >
( 0 * 480 > ( 320 , 480 )

( 3 2 0 ,

( 3 2 0 t

108

G D 1 Figure 70. Gated Diode GD-1.

320

3 2 0 )

i’oo )

, 0 )
( 0 • 480 ) ( 320 * 480 )

( 0 , 0 ) ( 3 2 0

320 )

I 80 )

Figure 71. Gated Diode GD-2

.
( 0 » 480 ) < 320 * 480 )

( 0 * 0 ) G D 3

3 2 0 )

I 8 0 )

, 0 )

no

Figure 72. Gated Diode GD-3.
( 0 . 4B0 ) ( 320 , 480 >

( 0 ,-0 ) ( 320

3 2 0 )

HO )

. 0 )

Figure 73. Gated Diode GD-4

.
( 0 , 4 8 0 ) ( 3 2 0 , 4 B 0 )

( 0 , JBO ) Figure 74.

t §?§

Probe-Fault Error Structure P.

)

D ( B202Q l&O )

Figure 75. Ground G.

( 0 , 0 ) ( 320 , 0 )

112 u
Figure 76. Cell probe pad array used for TERRY-2. Dimensions shown nr»‘ in

micrometers. Probe pads are numbered as shown at th*3 1ow«t • in each pad.
H

c

c

c

CB10

GDI

GD2

q

c

c

1 8

p

GD3

GD4

Q

TN3

12

TN1

T2

CB1

TN2

1

n . (C1_)

“(T 105)

T 103)--- —

TNI 3

TN14

(T101)

(Cl)

(T101)

TNI

19

CR1

G

(T 103)

TN9

TN12

TN4

13

CR4

T3

CB3

T20

2

TN2

20

TN10

T19

(GDA

1) 14

CR5

T5

CB4

T21

3

CR6

T6

CB5

TN5

4

(GDI)

(T1)

TN15

TN6

5

(TN

11 )

(T4)

(T 10) ;:<r; TN7

6

(C2)

[T 104]

(T 106)

P

CT102]

(C2)

(T 102)

G

(T104:

(CB2)

(T7)

TN16

TN8

7

CR7

Til

CB6

8 P

T13

21

T8

T20

(GDA

2) 15

CR8

T12

CB7

9 P

T15

TN1

T16

22

CR2

T9

TN13

T17

16

CR9

T14

CB9

10P

CB1

T

C5

T4

23

C3

T7

C4

T10

17

CR3

T19

CB8

T18

11

Figure 77. Schematic of TERRY-2 showing the locations of each probe pad

cell. The bold numbers are the cell numbers. The test structure

designations are also shown within the cells. Device designations in parentheses indicate that although they are addressed by

probe pads in those locations, the devices are actually located

outside the cells.

114
1

33I_D 39LD 40LD D40R 039R D33R

34L 36L 41l_n 38RQ 36R 34RQ

38L 41R

t _ 1 35L 37L (GS) E23 37R 35R

n. i 42L 42R

3*“ '43

21LD 21R

] 22LD 22R

'44

23LD 23R

7L 24LQ 24R

3L 25LQ 25R

9L 45 26LQ 26R

10L 27LQ 27R

1 1

46 28LQ 28R

^2L

13L

29LD

30LD n

D32L 32RD

29R

30R

14L

31L 31R

15L 43L 43R

16L

17L

18L

19L

20L

2R

3R

4R

5R

6R

7R

8R

9R

10R

1 1

12R

13R

14R

15R

16R

17R

18R

19R

20R

Figure 78. Schematic of TERRY-2 showing the locations and identi

ica f 1

- : bonding pads.
Figure 79. Schematic of TERRY-2 showing interconnections between test

structures, probe pads, and bonding pads.
Figure 80a. TERRY-2 test chip layout schematic produced by the CAD system

used to digitize the chip.
118
H Diffusion Level

[ j Metal Level

^

Contact Level

Figure 81 Schematic of a six-terminal metal-to-dif fusion contact resist

(from Proctor et al»t 1983).
Pc

03 0 g X

to •H 03 fH e

<c

CO Pn •H fa e HQ

03

0)

4-1

x 0 p P 00 O c

0) 03

4-1 4-1 rV

0) CO

03

0) e XP

C7> Oi c

•H 0) 5 X 0 p X

CO c

CD

CO a? p s 0 p p a)

CO XI •H

CO * c c

03 0 P •H P po

0) <u p p

03 •H i<D P

rH

G

a, 0) •H P p P p 3O

4-10 C

•H

(0 03 G P 0 TO H 1 P 0 0 p V 1 CO 03O

CO P

CO 3 0 O p CO o

0) o X

•rHp P

03

G 8 •H

<D x

— 0 X

c/5 < uX

'Oc

(0QX • CM

00

03po

ij' •H

120

Misalignments

involving

the

PS2

mask

do

not

affect

the

channel

lengths

unless

they

are

large

enough

to

leave

an

ungated

gap

in

the

channel.
APPENDIX

Charge Pumping

narge pumping is a method for determining the interface state density at the

^iO -Si interface of a transistor or gated diode [Brugler and Jespers, 1969],

vith the source and drain connected and reverse biased with respect to the

ubstrate, the gate is pulsed so that the semiconductor surface is alternatey accumulated and inverted. An electrometer connected from the source and

rain to the substrate measures the pulsed dc current generated by alternate-

_y filling interface traps with free carriers from the inversion layer and

hen recombination of the trapped carriers with majority carriers in the

bulk. The observance of charge pumping current requires that the emission

time of the traps be longer than the time required for several other processes: the formation or disappearance of the inversion layer, the response of

the majority carriers, and the filling of the traps. Also because of the

finite emission time, some of the trapped carriers initially provided by the source and drain return to the inversion layer instead of capturing an opposite sign (majority) carrier from the substrate during accumulation. Capture

of an opposite sign carrier is needed to complete the recombination process

which causes the measured dc current. A complementary process involves trapping majority carriers from the substrate which recombine with inversion

layer carriers during a later portion of the pulse, also causing a charge

pumping current.

In an n-channel device, the charge pumping current flows from the substrate

to the surface and then to the source and drain. The magnitude of the current is proportional to the frequency f at which the gate is pulsed, the area

Ag of the gate, and the number of traps per unit area N^ t which participate

[Brugler, 1 969]

:

I cp

fqA N . J g it ( A— 1 )

Table A1 lists and defines the symbols used in this appendix. The above

description is oversimplified since during the gate voltage cycle several

processes occur, and each affects the magnitude of the measured charge pumping current.

The pulses which bias the gate have finite transition times; these times are also important in determining the magnitude of the charge pumping current.

So, from the beginning, trapezoidal pulses with rise time t and fall time

t , pulse top VpQS and pulse bottom Vneg are considered. As an alternative,

a three-level pulse can be used to pulse the gate (see fig. A1 ) . The gate can be held at some voltage, vbaseline' for a t;*- me x

^ during the rise of

the pulse and for a time t

2 during the fall of the pulse as shown in the

figure. The advantages and disadvantages of this method are discussed

later.

During one pulse cycle, the capture and emission processes which occur -if

illustrated in figure A2 and described below.

* See Table A1 for definitions of symbols used in this appendix.

121
For p-type material (n-channel enhancement-mode MOSFET), during the bottom of

the pulse, at Vneg, the surface is in strong accumulation with a large concentration of holes forming an accumulation layer. The dominant mechanism for

the filling of interface traps is hole capture. Empty traps remain empty and

traps filled with an electron capture a hole which neutralizes the electron

and results in recombination. The time constant for these reactions x c is given by P

cPV., °rJ? th p

( A-2

)

where vt^ and Op are functions of the material and the surface, respectively,

and p, the hole concentration depends on the gate voltage. This time con- stant depends only on the hole concentration and not on the energy of the

trap in the band gap.

If during the transition of the pulse from Vneg

to VpOS the inversion

layer formed instantaneously, then there would not be time for other mechanisms to alter the state of the interface traps. In fact, the transition

time is finite and the emission of holes from the interface states is large

enough to make a measurable difference in the final current. The time con- stant for emission of holes from traps is governed by the difference in

energy of the trap and the valence band:

v. , o N e th p v

- ( E-E ) T v kT (A-3)

Independent of electron concentration, emission of holes is rapid from

traps close to the valence band and is slow for those near midgap or the

conduction band. The emitted holes return to the bulk and thus do not con- tribute to the charge pumping current.

The inversion layer forms very rapidly once the gate voltage is beyond the

threshold voltage because the source and drain provide the carriers. It is

assumed that the inversion layer responds instantaneously to changes in gate

voltage although the traps do not. During the top of the pulse at voltage

Vp0g/ the traps change their state by electron capture, and the time con- stant for electron capture is— = c = v . a n . ( A-4)

t n th n

cn

Again, note that the time required for electron capture depends on electron

concentration and not on trap energy. Traps which have not emitted a hole

capture an electron and thus contribute to the charge pumping current.

It is assumed that during the transition from inversion to accumulation, the

inversion layer responds instantaneously to the gate voltage although the

traps do not. The electron traps emit electrons with a time constant of

emission x- which is

122
T

1 (A-5)

e n

.e that electron traps close to the conduction band emit electrons rapidwhile those near midgap emit slowly. Many of the emitted electrons rei to the source and drain from which they came and thus do not contribute

the charge pumping current.

n the surface enters accumulation and the time constant for hole capture

short, the electrons are neutralized by holes from the bulk as discussed

viously and these electrons contribute to the charge pumping current.

roeseneken et al

.

have assumed that capture and emission processes occur

ring different time segments and do not overlap. They have assumed that

surface potentials outside the range from flatband to threshold, the

rface states are in equilibrium with the bulk Fermi level. During the

ansition period (either rising or falling), they assume that some of the

rface states are out of equilibrium if their time constant of emission is

nger than the switching time.

Lirunons and Wei have obtained a closed form expression for the nonsteadytate emission from a continuous distribution of traps of constant capture

coss section. For electrons trapped at the interface and out of equilibrim, after a time t all traps above energy E^t) will have emitted and any

.rap below Em

(t) will still have the trapped carrier where

Here, E^ is the intrinsic energy level and E

g

is the gap energy. E

rn (0) is

ihe energy at which nonsteady state emission begins.

Further, Groeseneken et al

.

have assumed that every carrier emitted returns

;o its origin and does not contribute to the charge pumping current. That

s, carriers captured from the inversion layer return to the source and drain

when emitted, while majority carriers captured from the bulk return to the

bulk when emitted. Furthermore, they assume that the capture by a filled

trap of the opposite sign carrier which completes the recombination process

does not occur during the nonequilibrium emission part of the transition from

flatbands to threshold. This conclusion is quite natural when the depletion

approximation is used because in the depletion approximation, n = p = 0 in

the depletion region.

With the above assumptions, Groeseneken et al

.

[1984] find:

Ie (t)

L m

E.

l - kT£n [ 1 - [1 -e

V. V

I = 2qD . f A • kT in

cp it g

FB T

V V

( A-7

)

. pos neg

123
In this equation, the term in brackets describes the range of potential in

which carriers trapped in the interface state remain trapped until they re- combine with the opposite sign carrier. If the fall or rise times are longer

or the majority-carrier capture cross sections larger, the charge pumping

current decreases in magnitude (note that the quantity in brackets must be

less than or equal to unity).

Also, Groeseneken et al

.

[1984] show that the distribution of traps in energy

can be measured, if the majority-carrier capture cross sections of the traps are constant, by varying either the rise or fall time. The density of traps

per unit area per unit energy is

D.it <V

D

it

( V

dl

'cp

qA f kT dJlnt

9 r dl

cp

qA f kT dJlnt,.

' g f

( A-8

)

where and are the upper and lower bounds of the energy range of traps

which contribute to charge pumping.

The energy at which D^ t (E) is measured is found from

|v - V I E

2 = E. - kUn [a^v y —?

t ]

, <A-9)

pos neg

or

| V “ V

I E

1 ‘ E. mn [a n.v

th ,

( A— 1 0

)

pos neg

depending on whether the leading edge tr or falling edge tf is used. To calculate the value of E, it is necessary to estimate Op or a n which is a drawback; the geometric mean of a n and Op can be found by fitting eq (A-7), but

Op and o n cannot be separately determined easily.

A clear-cut test of the validity of these assumptions may be made by measuring the increase in charge pumping current as an inverted surface is pulsed

closer and closer to flatbands. Alternatively, the surface may be held near

flatbands and pulsed further into depletion and then inversion. These methods have been proposed by others, but never examined in detail [Brugler,

1969, and Elliot, 1975]. A comparison of the charge pumping current measured

using the former technique to a surface potential versus gate bias curve

shows that a significant I Cp

is measured before the pulse bottom is sufficiently negative to bias the surface to flatbands. In the case of an n- channel device, this nonzero current is produced by either capture of holes

by traps containing electrons or failure of emitted carriers to return to the

124
ce or drain. These two phenomena would lead to errors in determination

:he density of interface traps from the charge pumping current using eqs

A-7) and (A-8).

he effect on the charge pumping current of capture during the nonsteadystate regime and of inefficient collection of emitted carriers can be shown

sing the three-level pulse technique described earlier. An advantage of the

hree-level pulse technique over the variable falltime technique is that the

urface potential is held at some constant value during the times x and x

2 :or responding to the choice of Vbaseline . The relation between surface

potential and gate voltage can be obtained experimentally by measuring the

iUasi-static capacitance on an adjacent capacitor. The effect of capture or failure to collect emitted carriers in the nonsteady-state emission regime is

a function of the surface potential. The emission of carriers from surface

traps depends only on the trap properties and whether the trap is in or out

of equilibrium, not on the exact value of the carrier concentration at the

surface. It is assumed that the response of carriers in the bulk is instantaneous on the time scale of the experiment and that the nonsteady-state

emission occurs somewhere in the range from accumulation to strong inversion.

Since there are systematic errors in determining the density of states using

the charge pumping current, a comparison of the D^ t

(E) measured using another

technique should be made. The high frequency-low frequency capacitancevoltage comparison (Nicollian, 1982) allows a measured D^ t

(E) to be obtained on a capacitor provided that the capture cross sections for surface

states are similar to those commonly observed. The comparison can be performed on a gated diode or a transistor with a gate large enough to obtain

accurate capaci tance-voltage data. Preliminary measurements show that the

charge pumping current value can be used to calculate interface trap densities within 20% of the value obtained from capaci tance-voltage data. The

large capacitor/transistors on TERRY-2 will allow a more precise comparison

of the results from these techniques.

125
Table A1 . List of Symbols for Charge Pumping

L cp

eP

v th

'P'

; p'

V,pos

^neg

T

l' t2

Dit (E)

Nit

kT

*c'

charge pumping current

time constant for capture of holes and electrons, respectively

time constant for emission of holes and electrons, respectively

7 thermal velocity of electrons or holes ~10

capture cross section for holes

capture cross section for electrons

hole concentration

electron concentration

capture rates of hole and electrons, respectively

emission rates of hole and electrons, respectively

pulse top voltage

pulse bottom voltage

transition time for leading edge, see figure A1

transition time for trailing edge, see figure A1

time during which gate is held at voltage Vkase ^ne , see figure A1

number of traps per unit area per unit energy

number of traps per unit area mean thermal energy, k, Boltzmann's constant,

T, absolute temperature

density of states of conduction band, valence band

gate area

126
©©©©©©©©

©

©

©

©

©

© Accumulation with

hole capture

Depletion with

hole emission

Depletion with

electron emission

Inversion with

electron capture

Figure A1 . Comparison between trapezoidal pulse ( ) and three-level

( ). Hie time spent in nonsteady state emission is -

>

pulse

and

127
128

Figure

A2.

Capture

and

emission

processes

during

charge

pumping

on

a

p-type

substrate.
NBS-H4A (rev. 2-80

U.S. DEPT. OF COMM.

BIBLIOGRAPHIC DATA

SHEET (See instructions)

1. PUBLICATION OR

REPORT NO.

NBSIR 84-2894

2. Performing Organ. Report No.| 3. Publication Date December 1984

4. TITLE AND SUBTITLE

TERRY-2: A Test Chip for Characterization of the Performance of Buried-Channel

Charge-Coupled Device (CCD) Imagers

5. AUTHOR(S)

G. P. Carver and R. A. Wachnik

6. PERFORMING ORGANIZATION (If joint or other than NBS, see instructions)

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

7. Contract/Grant No. DL-H-208137

8 . Type of Report & Period Covered

12/1/82-11/30/83

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street. City. State, ZIP)

The Charles Stark Draper Laboratory, Inc.

Cambridge, MA 02139

10. SUPPLEMENTARY NOTES

J Document describes a computer program; SF-185, FIPS Software Summary, is attached.

11. ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant

bi bl iography or literature survey, mention it here)

Test chip TERRY-2 is intended to be used for characterization of the performance of

buried-channel charge coupled device (CCD) imagers fabricated with a doublepolysilicon-gate process which includes several implants. Test structures in TERRY2 address two areas judged to be key ones for CCD performance, device parameters

and process parameters, including material properties. TERRY-2 is a modular chip

designed for automated testability; wire bonding of selected devices for radiation

effects testing; thinning of a region containing test structures, in the same manner

a back-side-illuminated CCD would be thinned; and beveling of large devices for

spreading resistance or analytical analysis. This report describes the features of

TERRY-2, the test structure designs, and the measurement procedures. The technigue

of charge pumping for measuring interface state density is discussed in an appendix.

12. KEY WORDS (Six to twelve entries; alphabetical order; capitalize only proper names; and separate key word-, by -.m - CCD; charge- coupled device; charge pumping; contact resistor; microel' -ct r< .n i * s* chip; sheet resistor; test chip; test pattern; test structure

13. AVAILABILITY

[X/] Unlimited

| | For Official Distribution. Do Not Release to NTIS

/] Order From Superintendent of Documents, U.S. Government Printing Office, Washington, D.C.

20402.

QZ] Order From National Technical Information Service (NTIS), Springfield, VA. 22161

14. NO. OF

PRINTED PAGES

135

15. Pn

tCOuu- r;