NATL INST OF STAND & TECH NBS

PUBLICATIONS

A11107 310056

NBSIR 83-2683

Description of a CMOS Test Chip,

NBS-39

U.S. DEPARTMENT OF COMMERCE

National Bureau of Standards

National Engineering Laboratory

Center for Electronics and Electrical Engineering

Semiconductor Devices and Circuits Division

Washington, DC 20234

April 1983

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NBSIR 83-2683

DESCRIPTION OF A CMOS TEST CHIP,

NBS-39

T. J. Russell

U S. DEPARTMENT OF COMMERCE

National Bureau of Standards

National Engineering Laboratory

Center for Electronics and Electrical Engineering

Semiconductor Devices and Circuits Division

Washington, DC 20234

April 1983

U.S. DEPARTMENT OF COMMERCE, Malcolm Baldrige, Secretary

NATIONAL BUREAU OF STANDARDS, Ernest Ambler. Director
i I . .. ‘ - •
Table of Contents

Abstract 1

Description 2

Acknowledgments 6

References 6

List of Figures and Table

1. The CMOS Test Chip NBS-39 8

2. The key to the shading in figures for the JI-CMOS process 9

3. Subsection N-l 10

4. Subsection N-2 11

5. Subsection P-1 12

6. Subsection P-2 13

7. An n-channel MOSFET 14

8. A p-channel MOSFET 15

9. An n

+ doped polysilicon cross-bridge sheet resistor test structure 16

10. A p

+ doped polysilicon cross-bridge sheet resistor test structure 17

11. The subsection PP-1 18

12. The subsection PP-2 19

13. A contact resistor test structure 20

14. An MOS capacitor test structure 21

in
15. An electrical alignment resistor test structure 22

16. A metal gate field oxide n-channel MOSFET 23

17. A metal gate intermediate oxide n-channcl MOSFET 24

18. An n

+ secondary ion mass spectroscopy profiling target 25

Table 1. Test Structure List for CMOS Test Chip NBS-39 26

1Y
Description of a CMOS Test Chip, NBS-39

T. J. Russell

Semiconductor Devices and Circuits Division

National Bureau of Standards

Washington, DC 20234

Abstract

Test chip NBS-39 was designed to analyze the scaling properties of short-channel

metal-oxide-semiconductor field effect transistors(MOSFETs). This report is a guide

for identifying and locating each test structure included on the test chip. There is

a table with each test structure identified by name, number, parameter measured,

and a reference of how to perform the measurement when appropriate. The test

chip can be fabricated by a junction-isolated(JI) silicon complementary metal-oxide

semiconductor(CMOS) p-well process and by a local oxidation of silicon(LOCOS)

CMOS p-well process. The modifications required to go from a JI-CMOS fabrication

process to a LOCOS-CMOS are discussed.

Key words: CMOS; MOSFETs; p-well junction-isolated (JI) CMOS process; p-well

local oxidation of silicon (LOCOS) CMOS process; scaling; short-channel; test chip;

test structure.

1
Description

CMOS test chip NBS-39 was designed to analyze the scaling properties of shortchannel MOSFETs. The test chip is shown in figure 1. The chip is divided into six

subsections. Subsections labeled N-l, N-2, P-1, and P-2 contain arrrays of n— and

p —channel MOSFETS with different gate lengths and the same gate width. In addition, there are n

+ and p+ doped polysilicon cross-bridge sheet resistor test structures with design bridge width equal to the adjacent transistor design gate length.

Each structure contains probe pads in 2 x N array for electrical testing utilizing a

manual probe station or a computer-controlled wafer prober. Selected transistors in

each subsection are connected to the bonding pads around the periphery of the test

chip. The chips can be packaged and the transistors bonded out for experiments

which require that the transistor be under bias during test. Subsections labeled

PP-1 and PP-2 contain process parameter test structures which can be used to

characterize the process used to fabricate the transistors.

The design rules used for the layout of the test structures on the test chip had a minimum feature size of 5 /mi. In selected cases, the gate length of some transistors

and the bridge width of some of the cross-bridge sheet resistor test structures were

smaller than the minimum feature.

The test chip can be fabricated by a junction-isolated(JI) p-well CMOS fabrication

process or by a p-well LOCOS-CMOS fabrication process. Both processes use a

p-well for the n-channel transistors, self-aligned polysilicon gates, and single-level

metallization. The changes, although minor, apply to a particular JI process and

2
a particular LOCOS process and may not be applicable to other JI and LOCOS

processes. The level-by-level design file for a JI-CMOS process is as follows:

1. p-well

2. p

+ guard band

3. Thick oxide opening

4. Polysilicon

5. n

+ source-drain

6. p

+ source-drain

7. Contact opening

8. Metal

9. Protective oxide overcoat.

The design file used for the JI process was converted into a CalTech Intermediate

Form(CIF) file[l] with design rules compatible with a p-well LOCOS silicon foundry[2].

A list of the levels including changes to the corresponding JI levels listed in parentheses follows:

1. Active area(level 5 and 6, n

+ and p+ source and drain implants)

2. p-well(level 1 and 2, p-well and p

+ guard band)

3. No equivalent level

3
l:

4. Polysilicon

5. p

+ source-drain(level 6, p

+ source-drain)

6. The logical NOT of level 5 is used to define the n

+ source-drain

regions

7. Contact opening(no change)

8. Metal(no change)

9. Passivation(no change).

Table 1 is a list of each test structure included on the test chip NBS-39. Each structure is identified by name, number, critical dimension, and the parameter measured.

Test structures are identified by N followed by a number and P followed by a number according to their use to measure n-type or p-type parametrics, respectively.

References to appropriate measurement techniques are provided for selected structures. For example, there is reference to the measurement of the misalignment between two conducting layers using an electrical alignment test structure [3], but there

is no reference to the measurement of transistor characteristics.

Figure 2 is the key to the shading for the JI-CMOS process structures shown in

the figures. Subsections N-l,N-2, P-1, and P-2 are shown in figures 3, 4, 5, and

6, respectively. An n — and a p —channel transistor are shown in figures 7 and 8,

respectively. The transistors are representative of the other transistors in the Nand P- subsections. The differences are only in the polysilicon gate length noted in

Table 1. From left to right in subsection N-l, transistors with gate lengths of 8, 4,

4
and 1.25 pm and in subsection N-2 transistors with gate lengths of 3.5, 3.0, and 1.0

pm are connected to the bonding pads around the periphery of the test chip. From

right to left in the P-1 and P-2 subsections, transistors with gate lengths of 8, 4,

and 1.25 pm and 3.5, 3.0, and 1.0 pm, respectively, are connected to the bonding

pads around the periphery.

In subsections N-l and N-2, the polysilicon cross-bridge sheet resistor test structures are doped with the n+ source-drain implant n

+ doped and in P-1 and P-2

subsections they are doped with the p

+ source drain implant. Representative n

+

and p

+ doped polysilicon cross-bridge sheet resistor test structures are shown in

figures 9 and 10. The width of the bridge of the sheet resistor is designed to be

equal to the gate length of the adjacent MOSFET. The gate dimensions are found

in Table 1.

Process parameter test structures which address properties of n —channel devices

are labeled N59-N69 and those that address properties of p —channel devices are

labeled P57-P68. These structures are grouped into subsections PP-1 and PP-2

and are shown in figures 11 and 12. In subsections PP-1 and PP-2, there are test

structures to be used to measure contact resistance[4] (fig. 13); MOS capacitors (fig.

14) to be used to measure gate oxide properties and interface trapped charge(ITC);

cross-bridge sheet resistors [5] (fig. 9) to be used to measure the sheet resistance of

the various conducting layers used to fabricate devices and circuits; and electrical

alignment resistors [8] to be used to measure the misalignment between a contact

window and a conducting layer (fig. 15). There are metal gate n — and p —channel

transistors to be used for characterizing the field oxide (fig. 16) and the intermediate

field oxide (fig. 17). The large area structures N61 (fig. 18), and P61 are for secondary

5
ion mass spectroscopy(SIMS) profiling of the sources and drains in the p— and n —

channel transistors. A NAND, a NOR, and four experimental structures, dual-gated

diodes and split cross-bridge sheet resistors are included, but are not illustrated or

discussed.

Acknowledgments

The author would like to acknowledge all of the members of the staff of the Semiconductor Devices and Circuits Division for their contributions to the design of the

CMOS Test Chip NBS-39. In particular, the author would like to thank C. L.

Wilson, K. F. Galloway and L. W. Linholm for their reading of the manuscript and

their useful suggestions and E. J. Walters for preparing the manuscript.

References

1. Mead, C. A., and Conway, L. A., Introduction to VLSI Design, (Addison Wesley,

Reading 1980).

2. Griswold, T. W., Portable Design Rules for Bulk CMOS, VLSI Design m, No.

5, 62-67(1982).

3. Russell, T. J., Leedy, T. F., and Mattis, R. L., A Comparison of Electrical

and Visual Alignment Test Structures for Evaluating Photomask Alignment in

Integrated Circuit Manufacturing, Technical Digest, International Electron Devices

Meeting, Washington, D.C., December 5-7, 1977, pp.7A-7F and Russell, T. J. and

6
Maxwell, D. A., Semiconductor Measurement Technology: A Production-Compatible

Microelectronic Test Pattern for Evaluating Photomask Misalignment, NBS Spec.

Publ . 400- 5 1(April 1979).

4. Proctor, S. J., and Linholm, L. W., A Direct Measurement of Interfacial Contact

Resistance, IEEE Electron Device Lett. EDL-3, 294-296(1982).

5. Buehler, M. G., Grant, S. D., and Thurber, W. R., Bridge and van der Pauw Sheet

Resistors for Characterizing the Line Width of Conducting Layers, J. Electrochemical

Soc. 125, 650-654(1978).

6. Takacs, D., Muller, W., and Schwabe, U., Electrical Measurement of Feature Size

in MOS Si2 -Gate VLSI Technology, IEEE Trans. Electron Devices ED-27, 1368-

1373(1980).

7. Brugler, J. S., and Jespers, P. G. A., Charge Pumping in MOS Devices, IEEE

Trans. Electron Devices ED-16, 297-302(1969).

8. Russell, T. J., Wilson, C. L., and Gaitan, M., Determination of the Spatial

Variation of Interface Trapped Charge Using Short-Channel MOSFETs (submitted

to IEEE Trans. Electron Devices for publication).

7
* 5080jUm

Figure 1. The CMOS Test Chip NBS-39 is shown with its six subsections labeled N-l,

N-2, P-1, P-2, PP-1, and PP-2.

8
Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Level 8

Level 9

Figure 2. The key to the shading in figures for the JI-CMOS process.

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14
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Figure 8. A p—channel MOSFET, P36, from subsection P-1.

15
Figure 9. An n

+ doped polysilicon cross-bridge sheet resistor test structure, N15,

from subsection N-l.

16
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Table

1.
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contains

process

parameter

test

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The

test

structures

are

numbered

and

described

in

Table

1.
80/j.m N63

Figure 13. A contact resistor test structure, N63, from subsection PP-1.

20
^////////^/////////////////////^

80jUm N59

Figure 14. An MOS capacitor test structure, N59, from subsection PP-1.

21

^777y7/77/y////////y///////////////////////////////////////////////

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—

80/um|— N68

Figure 15. An electrical alignment resistor test structure, N68, from subsection PP1.

22
Figure 16. A metal gate field oxide n—channel MOSFET, N57, from subsection PP2 .

23
Figure 17. A metal gate intermediate oxide n—channel MOSFET, N58, from subsection PP-2.

24
N61

Figure 18. An n

+ secondary ion mass spectroscopy(SIMS) profiling target, N61,

from subsection PP-2.

25
Table

1.

Test

Structure

List

for

CMOS

Test

Chip

NBS-39

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32
NBS-114A (REV. 2 -80

U.S. DEPT. OF COMM.

BIBLIOGRAPHIC DATA

SHEET (See instructions)

1. PUBLICATION OR

REPORT NO.

NBSIR 83-2683

2. Performing Organ. Report No. 3. Publication Date

April 1983

4. TITLE AND SUBTITLE

Description of a CMOS Test Chip, NBS-39

5. AUTHOR(S)

T. J. Russell

6. PERFORMING ORGANIZATION (If joint or other than NBS, see instructions) -

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

7. Contract/Grant No.

8 . Type of Report & Period Covered

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street. City. State. ZIP)

10.

SUPPLEMENTARY NOTES

I J Document describes a computer program; SF-185, FIPS Software Summary, is attached.

11.

ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant

bibliography or literature survey, mention it here)

Test chip NBS-39 was designed to analyze the scaling properties of short-channel

metal-oxide-semiconductor field effect transistors (MOSFETs). This report is a guide for identifying and locating each test structure included on the test chip.

There is a table with each test structure identified by name, number, parameter

measured, and a reference of how to perform the measurement when appropriate. The

test chip can be fabricated by a junction-isolated (JI) silicon complementary metaloxide semiconductor (CMOS) p-well process and by a local oxidation of silicon

(LOCOS) CMOS p-well process. The modifications required to go from a JI-CMOS

fabrication process to a LOCOS-CMOS are discussed.

12.

KEY WORDS (S/x to twelve entries; alphabetical order; capitalize only proper names; and separate key words by semicolon s) CMOS; MOSFETs; p-well junction-isolated (JI) CMOS process; p-well local oxidation of

silicon (LOCOS) CMOS process; scaling; short-channel; test chip; test structure.

13. AVAILABILITY

| y | Unlimited

| | For Official Distribution. Do Not Release to NTIS

| | Order From Superintendent of Documents, U.S. Government Printing Office, Washington, D.C.

20402.

[X] Order From National Technical Information Service (NTIS), Springfield, VA. 22161

14. NO. OF

PRINTED PAGES

36

15. Price

$8.50

USCOMM-OC 8043-P80
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