NBSIR 73-302

RF NULL DETECTOR NBS/SND

Robert E. Stoltenberg

Electromagnetics Division

Institute for Basic Standards

National Bureau of Standards

Boulder, Colorado 80302

June 1973

Prepared for

Army/Navy/Air Force

Calibration Coordination Group
i

I

I
NBSIR 73-302

RF Null Detector NBS/SND

Robert E. Stoltenberg

Electromagnetics Division

Institute for Basic Standards

National Bureau of Standards

Boulder, Colorado 80302

June 1973

Prepared for

Army/Navy/Air Force

Calibration Coordination Group

U.S. DEPARTMENT OF COMMERCE, Frederick B. Dent, Secretary

NATIONAL BUREAU OF STANDARDS, Richard W. Roberts, Director

Abstract

This report describes an ultrasensitive receiver for

detecting low-level rf signals in the nanovolt region. The

primary purpose of the instrument is to detect the balance

condition in rf bridges; however, it is useful in any

comparison measurement in which two or more signals can be adjusted in phase and magnitude such that their summation

results in a null.

The receiver frequency is determined by individual plugin units. Units have been built for selected frequencies

from 100 kHz through 30 MHz. Detection is accomplished by

double conversion. The first converts the signal of interest

to a common intermediate frequency; the second performs a dual synchronous (homodyne) conversion. The dual detectors

are sensitive to signals in quadrature with each other. A

reference voltage synchronous with the null signal is required.

Thus, the dual detection provides an indication of both the

phase and the magnitude of the null unbalance.

The output of each detector is displayed on a zero-center

meter, thus indicating the direction of unbalance as well as the magnitude. This information is also available at a rear panel jack for use in servo control of the external

system.

Gain adjustment over a 90 dB range is provided by a single front panel control. Phase adjustment to compensate

for differential phase delay between the reference and

null signals is accomplished with a front panel 360° continuous

phase control.

Key Words

Detector; phase sensitive; RF null detector.
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TABLE OF CONTENTS

Page

1.0 General Information 1

1.1 Introduction 1

1.2 Description 1

1.3 Specifications 2

2.0 Operating Instructions 4

2.1 Introduction 4

2.2 Description of Controls, Connectors, and Indicators 4

2.3 Operating Procedures 8

3.0 Theory of Operation 13

3.1 Reference Channel 13

3.2 Signal Channel 19

4.0 Maintenance and Circuit Description 22

4.1 Main Frame Assembly 2 2

4.2 Power Supply 2 4

4.3 Reference Amplifier 26

4.4 Phase Shifter 30

4.5 Discriminator 33

4.6 Signal Amplifier 37

4.7 Synchronous Detector 41

4.8 Meter Amplifier 46
TABLE OF CONTENTS (continued)

Page

5.0 Frequency Plug- In 49

5.1 Plug-In SND/PI-30A 49

6.0 Parts List 55

6.1 Introduction 55

7.0 Schematics, Wiring Diagrams, and Component Location 69

7.1 Introduction 69

LIST OF FIGURES

Figure 2.1A. Front panel control and indicator location 5

Figure 2. IB. Rear panel connector location 6

Figure 3.1. Functional block diagram 14

Figure 3.2. Main frame RF wiring diagram 15

Figure 3.3. Frequency plug-in wiring diagram 16

Figure 4.1 Test diagrams 31

Figure 4.2. Test diagrams 40

Figure 7.1 NBS/SND master wiring diagram 70

Figure 7.2 Reference amplifier schematic 71

Figure 7.3. Reference amplifier parts pictorial 72

Figure 7.4. Discriminator schematic 73

Figure 7.5. Discriminator parts pictorial 74

Figure 7.6. Signal amplifier schematic 75

Figure 7.7. Signal amplifier parts pictorial 76

Figure 7.8. Synchronous detector schematic 77

Figure 7.9. Synchronous detector parts pictorial 78

Figure 7.10. Meter amplifier schematic 79

Figure 7.11. Meter amplifier parts pictorial 80

Figure 7.12. SND/PI-30A schematic 81

Figure 7.13. 30 MHz Pre Amp schematic 82

Figure 7.14. 30 MHz Pre Amp parts pictorial 83

LIST OF TABLES

Table 6.1. Parts list RF null detector NBS/SND 56

Table 6.2. Parts list plug-in SND/PI-30A 66
NBS RF NULL DETECTOR

(Synchronous Detector)

I. General Information

1.1 Introduction.

This document contains a description, specifications, operating instructions, theory of operation, parts list, schematics,

and wiring diagrams for the National Bureau of Standards RF

Null Detector, Model NBS/SND. This unit is a general purpose

calibration instrument which provides both magnitude and phase

information at sensitivities not previously available.

1.2 Description

This unit consists of a main frame detector assembly which

accepts individual specific frequency plug in units. The frequency coverage of the Null Detector is thus limited to only those

plug in units available. This instrument has been designed for

extremely high sensitivity consistent with simplicity of operation.

The detector is frequency locked to the signal to be examined and

thus requires a synchronous reference voltage. A single gain control adjusts sensitivity. The null signal is indicated by two

front panel center- indicating meters. A continuously variable

phase control enables in-phase and quadrature components of the

null signal to be displayed individually on separate meters.
An additional unfiltered rear panel output is provided

directly from the detector which can be used for servo control

of external systems.

1.3 Specifications

1.3.1 Frequency Range:

Frequency is determined by plug in units.

100 kHz, 1 MHz, 10 MHz, and 30 MHz units are

presently available.

1.3.2 Maximum sensitivity:

Nominally 1 nanovolt.

1.3.3 Dynamic Sensitivity Range:

90 dB.

1.3.4 Phase control:

360° continuously variable.

1.3.5 Total maximum gain to Synchonous detector output:

(for servo control) 150 dB.

1.3.6 Reference Voltage Requirement:

50-500 yv, synchronous with input signal.

1.3.7 VCLO Tracking Range:

Dependent upon plug in, nominally ± 20 kHz.

1.3.8 Noise figure:

2 dB.

1.3.9 Input Impedance:

Nominally 50 Q, Reference and Signal Inputs.

2
1,3.10 Dimensions:

13.3 cm X 48.2 cm W x 43 cm Deep 10.1 Kg

(5%"H X 19"W X 17" Deep) .

3
2.0. Operating Instructions

This section contains information and instructions for

preparation and use of this instrument in a step-by-step procedure.

2 . 1 Introduct ion

The RF Null Detector provides synchronous detection of low

level RF signals. The instrument uses double conversion. The

first mixer converts the incoming RF signal to the main frame

20 kHz IF frequency. This is accomplished by the frequency plugin unit which contains a VCLO (Voltage Controlled Local Oscillator)

and a preamplifier appropriate for the frequency desired. The

second conversion is a homodyne or synchronous converter (Synchronous Detector). The second conversion obtains its reference L.O.

(Local Oscillator) from an internally generated 20 kHz signal. All

RF cables are semi-rigid with SMA connectors, with one exception,

which is a BNC coupler.

2.2 Description of Controls, Connectors, and Indicators

See figures 2.1A and 2. IB for location and description of

controls, connectors and indicators.

2.2.1 AC Power.

A^ AC Power Jack

Ao AC Power Switch
5

Fuse (% A.

)

AC Indicator Lamp

2.2.2 VCLO

^1

^2

2.2.3 Null

J28-J29 VCLO outputs

Provide RF power to J24-J25 for first mixers.

J26 Reference Voltage Input

Connects reference voltage to Reference Amplifier

Mixer.

VCLO Trim

Provides small frequency adjustments to VCLO for

tuning precisely 20 kHz above incoming reference

signal frequency.

Frequency Error Meter

Indicates frequency difference between VCLO and

external reference voltage.

Lock Switch

Frequency locks the VCLO 20 kHz displaced from the

reference signal.

Reference Level Indicator

Indicates adequate reference signal.

J31-J39 RF Signal Input. J31 on Model SND/PI-30A

Plug - in

.

7
J27-J30 connects plug-in preamplifier to main

frame

.

Gain Control

Provides up to 90 dB attenuation for initial null

adjustments.

Phase Control

Provides 360° continuously variable phase adjustment for the internal synchronous detectors.

C5 M2-M3

Indicate input voltages. (Nominally ± 5.0 Nanovolts

f.s. @ maximum gain setting.) Right-hand meter

indicates quadrature voltage (90° phase displaced)

with respect to left hand meter.

Cg S2-S3 (Time Constant)

Control meter response time constant; Fast in left

position, Slow in right position (approximately

7:1 ratio).

Cy J8 Synchronous Detector output (unfiltered)

Pin F proportional to M2 (50 mV/10 y amps)

Pin K proportional to M3 (50 mV/10 y amps)

Pin J Ground.

2.3 Operating Procedures

The following steps must be performed to insure accurate and

consistent null measurements.

8
2.3.1 These preliminary connections and checks should

be performed prior to applying power.

a. Insure AC power switch is off.

b. Connect AC line cord to J6

.

c. Insert appropriate frequency plug-in.

d. Connect the following semi-rigid RF cables

(supplied with unit) : MAIN FRAME PLUG IN

Ref to VCLO out. (J24 to J28)

Sig to VCLO out. (J25 to J29)

Sig in to Sig out. (J27 to J30)

WARNING : DO NOT APPLY AC POWER WITH THESE CABLES

REMOVED . PRE AMP MAY BE DAMAGED .

e. Lock switch off.

f. Time Constant switches to fast.

g. Gain Control to min (full CCW)

.

Connect Synchronous Reference Voltage to Ref in,

(J26) (Do not exceed 500 yv) . Connect null signals to Sig In (J31)

.

SND/P1-30A contains two inputs (J31-J39)

NOTE: Do not exceed -20 dBm (22 mv)

.

The following steps are required to insure frequency lock.

a. Turn power on.

b. Adjust frequency trim control until frequency error meter indicates null. Meter should

9

2.3.2

2.3.3

2.3.4
indicate to the right with CW rotation of VCLO

trim control. Ref Lamp should be on (indicating

sufficient reference signal).

c. Lock switch to Lock.

d. In order to insure VCLO is locked, rotate

VCLO Trim Control a small amount. The Frequency

Error Meter should indicate right with CW rotation and left with CCW rotation. Re-zero the

meter with the trim control.

The VCLO is now locked to the Ref. Voltage and should require

no further attention unless the unit has AC power interupted or the

Reference signal is lost. The frequency error meter indicates IF

frequency deviation from 20 kHz. Meter sensitivity in the locked

position is nominally 1 Hz/2 yamp. In the event of large reference frequency drifts resulting in frequency error indication of

more than 20 yamps (10 Hz) , either the external signal source

should be readjusted to the nominal frequency of the plug-in, or

the VCLO trim control should be adjusted to re-zero the meter.

Note : The Automatic Frequency Lock response is limited to

approximately 100 Hz. A rapid change in the reference

frequency can exceed the tracking response of the

VCLO, resulting in the loss of frequency lock. This

normally results in off-scale frequency error meter

fluctuations coupled with blinking of the Ref Level

lamp. If this occurs, repeat steps b through d of 2.3.4.
2.3.5 Null Measurement . The primary function of this

instrument is to serve as the detector in an RF

bridge or dual channel calibration system where

the null balance signal is to be reduced to the

minimum possible value. In this application a null unbalance in the system can occur as a result of either a differential magnitude or phase

change in either of the two signal paths. This

instrument provides the capability of distinguishing between the two types of unbalance (magnitude

and phase) and, additionally, of indicating the

direction of the unbalance by the direction of

the meter deflection. The following steps are to

be performed to reduce the null signal to a minimum value.

Note: In order to assure there are no external rf leakage

paths from the external system, a 50 ohm termination

should be connected to the signal input, and the gain

turned fully CW. No meter deflection should be observed other than random noise.

2.3.5.1 Rotate the gain control CW until either one or both

meters indicate half scale.

2.3.5.2 Alternately adjust the external phase and magnitude

controls for zero meter indications.

11
2.3.5.3 Repeat steps 2.3.5.1 and 2.3.5.2 until the gain

control is approximately 3/4 CW.

2.3.5.4 Unbalance the external system a small amount

by using its magnitude control. Rotate the null

detector phase control until the left hand null

indicating meter indicates zero. Adjustment of

the external system magnitude control should now

be indicated on the right hand meter only. Re-zero

the right hand meter with the magnitude control

and unbalance the external system by adjusting

its phase control. Only the left hand null meter

should deflect. Re-zero the left hand meter.

! ' 2.3.5.5 Rotate the gain control CW for increased meter

I

: deflections (increased sensitivity) . Reduce the

off-null condition by adjusting the external

I system as indicated in 2.3.5.4. Repeat quadrature

separation (2.3.5.4) adjustment if necessary.

2.3.5.6 Repeat step 2.3.5.5 until maximum desired sensitivity

is reached or until an adequate null is achieved.

Note : In order to take advantage of the full sensitivity

'

. (lnv/10 ya) , it is normally advantageous to switch

the meter time constants to "S" when maximum gain

is approached to reduce the effects of random noise

fluctuations. This also severely restricts the

meter response to system changes, thus requiring

very slow adjustments in the external system.

12

j
3.0. Theory o£ Operation

The following section contains a functional description of

the Null Detector operation. A Circuit description is contained

in Section 4.0. See fig. 3.1 for the Block Diagram of the Null

Detector. See fig. 3.2 and 3.3 for RF wiring diagrams. The main

frame contains six modules plus the power supply board (MPS-1).

The plug-in contains two modules and a circuit board containing

the VCLO trim and filter components. Some frequency plug- ins

additionally contain a third module, an isolation amplifier

(Iso-Amp)

.

3.1 Reference Channel

The RF Null Detector is a double conversion frequency locked

receiver. The first conversion provides a common main frame 20

kHz IF frequency. The second conversion is a homodyne synchronous detection.

The homodyne detection requires a reference signal source

synchronous at the 20 kHz IF. Due to the critical differential

phase stability required and the narrow band IF amplifiers

incorporated, it is necessary to provide a local oscillator (L.O.)

which is frequency locked to the incoming signal. Hereafter the

L.O. is referred to as the VCLO (Voltage Controlled Local

Oscillator)

.

3.1.1 VCLO

The 20 kHz IF is generated by using a common

13

'1 II I'

i/2

DISC

JI7

JM

^ II -

J/3

(i

J5 Jll J/2 J3 Sid

JIO

1 L

JZ2 J23

JG

Figure 3.2, Main frame RP wiring diagram

15

- PHASE SHIFT. ASS'Y

TOP SIDE HEmnveV TO IHOijJ K£SOLVee 1ND COmPOHENlS
5 K

Figure 3.3. Frequency plug-in wiring diagram

16
VCLO (located in the frequency plug-in) as a mixer local oscillator for both the null signal

and the reference signal provided from the external

system. The VCLO output is coupled to the mixers

through external cables (supplied with the unit)

RF leakage from the Reference signal is prevented

from entering the Null channel by either a separate

optional Iso Amp or by providing isolation within

the VCLO itself. The method used varies with each

VCLO and is covered in the plug-in options.

3.1.2 Reference Amplifier

The external reference frequency signal is connected directly to the reference mixer located

within the reference amplifier (Ref Amp) . The

reference amplifier is a three stage, 20 kHz, 80 dB

gain Amplifier. Up to 20 dB AGC is provided to insure

a constant amplitude reference voltage to the detectors, independent of amplitude changes in the external reference voltage. The Ref Amp contains an

additional circuit, which lights the Ref Level Lamp

when the 20 kHz Ref Signal is adequate for detector

operation. Two outputs from the Ref Amp are available.

The first connects the 20 kHz signal directly to a

20 kHz discriminator. The second passes through the

17
phase shifter assembly and is applied to the Syn Det

(Synchronous Detector) to provide the detector reference voltage.

3.1.3 Phase Shifter

The phase shifter assembly contains a resolver with

appropriate circuitry to provide 360° of Electrical

phase shift for 360° of mechanical rotation of the

front panel phase control knob.

3.1.4. Discriminator

The first output from the Ref Amp is applied to

the discriminator (Disc) . The discriminator is an

unconventional inductorless 20 kHz discriminator,

producing a bi-directional voltage proportional

to the frequency deviation from 20 kHz. This deviation is indicated by the frequency error meter on

the front panel. The output from the Discriminator

is amplified and connected through the frequency

lock switch to the VCLO Control Board in the locked

position. In the unlocked position the VCLO Control

is grounded and the output amplifier gain is reduced

by 15 dB to provide easier frequency trimming.

3.1.5 VCLO Control

The control board contains the servo loop filter and

a provision for independent tuning of the VCLO with

the frequency trim control. This control allows

precise tuning of the VCLO to 20 kHz above the in18
coming reference frequency prior to locking the VCLO.

3.2.0 Signal Channel

As noted in 3.1 the instrument is a double conversion receiver. Initial preamplif icat ion is provided by the preamplifier located within the frequency plug-in. Its output is mixed with the common VCLO, thus providing a 20 kHz IF (first conversion) which is synchronous with the reference

channel IF.

The signal channel IF and the Reference Channel

IF are then synchronously detected (second conversion). This output is amplified, filtered, and

displayed on the front panel Null Meters

.

Pre Amplifier

The null signal is first amplified in a low noise

3 stage 66 dB preamplifier (Pre Amp) of appropriate frequency for the individual plug-in. The

output from the Pre Amp is connected to the main

frame through an external cable (supplied with the

unit) from J27 to J30.

Gain Control

The Pre Amp output is connected to a main frame,

front panel controlled, 90 dB attenuator. This

attenuator functions as a gain control. The out3.2.1

3.2.2

19
put from the attenuator is connected to the mixer

of the signal amplifier (Sig Amp)

.

Signal Amplifier

The Sig Amp is a 90 dB gain (including the mixer)

20 kHz Amplifier. It contains three stages, two of

which are tuned, resulting in a narrow band amplifier. Two outputs are provided, one as a test

jack, and the second, which is connected to the

synchronous detector (Syn Det) input.

Synchronous Detector

The Syn Det is in fact a dual detector, each channel

of which is a full wave synchronous detector. These

detectors provide a wide dynamic range in order

to detect a signal of interest in the presence of up

to +40 dB of noise. A fixed 90° phase shift is

inserted in one reference path thus making one

detector sensitive to voltages in quadrature with

respect to the other.

Each detector has two outputs. One output from

each detector is connected to rear panel connector

J8 for use in an external servo control circuit if

desired. The other output from each detector is

connected to the meter amplifier (Met Amp)

.

20
NOTE : Synchronous detectors are characterized by their

phase sensitivity. The output voltage is Ecos0

where 9 is the phase angle between the reference

and the signal of interest. Thus, at 0° and 180°,

the detector will have maximum sensitivity and

the output is bi-directional. At 90° and 270° the

output will be zero in a perfect detector. By

inserting the 90° phase separation in the Reference

voltages for the detectors, one can be sensitive to

the resistive component of the signal while the

other is sensitive to the reactive component of the

signal.

If there is capacitive coupling between windings

within the detector transformer, this phase separation will be compromised, so the transformers used

are specially NBS-designed toroidal units to approach

the theoretical goal.

3.2.5 Meter Amplifier

This unit contains two identical DC Amplifiers with

limited frequency response. The detector outputs

are amplified and displayed on their respective

front panel Null Meters. An additional time constant

switch is available for each circuit to reduce

the effect of indicated noise when operating in

the maximum gain position.

21
4.0 Maintenance and Circuit Description

The following section contains a detailed circuit analysis

of each individual module and assembly. Test and adjustment procedures for each separate unit are included in each subsection.

Refer to Schematics and Parts pictorials, section 6, for parts

ident if icat ion

.

4.1.0 Main Frame Assembly (fig. 7.1 - 3.2)

4.1.1 The main frame assembly contains the wiring, connectors, meters, and various switches which interconnect the replaceable modules.

4.1.2 A complete functional description of the entire

unit is contained in section 3.0. No additional

circuitry is contained independent of these replaceable modules, which are treated individually

within this section.

i ^ 4.1.3 Test Procedures (Plug In should be tested first.

! See Section 5 . 0)

.

I a. Connect the RF Null Detector per instructions

I 2.3.1, 2.3.2, and 2.3.4. (Delete cable J27-J30 (C-2)

I and install a. SO Q, termination on J27 and J30.)

Gain control fully CW.

i

j Null meters should indicate 0 ± 1.0 ya.

' b. Remove termination from J2 7 and connect a 3 yv

i signal synchronous with the input to J2 6. Adjust

phase control for 0 indication on left null meter and

22
positive indication on right null meter.

Right null meter should indicate +30 ± 10 ya.

c. Rotate Phase Control 180°.

Right null meter should indicate negative with

the magnitude equal to b ± 3 yamp.

d. Rotate Phase Control 90° CW from c. position

for zero indication on Right null meter.

Left null meter should show indicated value of

b . C± 3 ya) .

e. Rotate Phase Control 180° from d position.

Left null meter should indicate negative with the

magnitude equal to d (± 3 yamps)

.

f. Power off.

Reconnect the cable from J27-J30.

Repeat steps 2.3.1, 2.3.2 and 2.3.4.

Connect 50 Q termination to Sig In on the Plug-in

Gain Max CW.

Null meters should indicate a zero average with

a maximum excursion of ± 15 yamps.

T.C. Switch to Slow, (S)

.

Null meters should indicate a zero average with

a maximuin excursion of ± 5 ya.

23
g. Connect the 3 yv signal from step b through a

60 dB attenuator to Sig In on Plug-in. (If two

inputs are available attach a 50 termination

to one input.)

Repeat steps b through e on both fast and slow

time constants.

Outputs should indicate the previous readings.

Tolerance -0 + 6 dB.

•

' NOTE Meter fluxuations in the fast position will require visual averaging of the meter indication.

Meter response time in the slow position will

require several seconds to reach the final value.

4.2.0 Power Supply (fig. 7.1)

4.2.1 All DC power for circuit operation is provided

from the master power supply board (MPS-1). This

board is supplied with AC power from rear panel

connector J6 via the front panel fuse (fl) and AC

power switch (S2).

4.2.2 The board contains five commercial dual output

regulated power supplies. Three units, (PS1,2,3)

are adjusted to provide ± 15 VDC while PS4 is

adjusted for ± 14 VDC and PS5 is adjusted to ± 10

VDC.

24
PSl provides power via a shielded cable to the

Signal Amplifier Module through P5 . No common

power ground exists on MPS-1. This prevents ground

loops.

PS2 supplies DC power to the Discriminator via

plug P2 , Reference Amplifier via plug PI, and the

Meter Amplifier via plug P3.

PS3 supplies power to the Synchronous Detector

through P4 . In addition, + 15 VDC is connected

to J7 (pin 6) for use in some models of the Frequency Plug- In.

PS4 is connected such that the negative terminal

is grounded, thus providing + 14 VDC and + 28 VDC.

Each of these voltage sources is connected to

J7 (Pin 5,8) for a preamplifier voltage selection.

The + 28 VDC is additionally connected to DS2

(reference level indicator lamp)

.

The positive terminal of PS5 is grounded providing

-20 VDC to J7 (Pin 4) for the VCLO within the

Frequency Plug-In.

Resistor Rl on MPS-1 is the current limiting resistor for DSl (power "on" indication) located on

the front panel.

25
4.2.3 Test Procedures

The power supplies are preadjusted at assembly.

The proper voltages are listed below.

Measurement Point Voltaj7 I\ X ]J J. c P-2 Pin A to H +15VDC + 2 0 0mV 5mV

Pin B to H -15VDC + 2 0 0mV 5mV

P-4 Pin A to H +15VDC + 2 0 0mV 5mV

Pin B to H -15VDC + 2 0 0mV 5mV

P-5 Pin A to H +15VDC + 2 0 0mV lOmV

Pin B to H -15VDC + 2 0 0mV lOmV

J-7 Pin 5 to 7 +28VDC + 4 00mV lOmV

Pin 8 to 7 +14VDC + 4 00mV lOmV

Pin 4 to 3 -2 0VDC + 4 00mV lOmV

4.3.0 Reference Amplifier (fig. 7.2 - 7.3)

. 4.3.1 The Reference Amplifier supplies the 20 kHz reference

IF within the main frame . It is generated by mixing

the VCLO signal (located within the Frequency PlugIn) and the externally supplied reference signal.

4.3.2 The Reference Amplifier requires two inputs, +5

DBM local oscillator input at J14 and 50 to 500

microvolts at J13. The frequency range is 100

kHz to 100 MHz with the local oscillator 20 kHz

above the frequency of the input signal.

The two inputs are heterodyned in a commercial mixer

(Ml). The output is filtered by LPl (50 kHz

Low Pass) reducing harmonics and L.O. feedthrough

at low frequencies. Resistor R4 provides a matched

load for LPl, and CI is a coupling capacitor.

26
The mixer output is amplified by Ql . Bias is provided by Rl , R2 , R3 , and C2 . R5 is the emitter

resistor and C4 the RF bypass. L3 in conjunction

with C5 and C21 (when required) are tuned to 20 kHz

providing in excess o£ 50 db gain at 20 kHz.

Transistors Q2 , Q3 , and Q7 function as a voltage

variable gain amplifier which automatically provides a constant output voltage independently of

input changes. Q2 is an emitter follower which

provides an impedance match between the high output

impedance of Ql , and the low input impedance of Q3

,

R6 and R7 furnish bias for Q2 while R9 and RIO provide bias for Q3 . C6, C7, and C8 are coupling

capacitors. R8 is an emitter resistor for Q2

.

The gain of Q3 is determined by the ratio of Rll

,

the emitter resistor, and the collector load. The

collector load is composed of R12 and Q7 a dual

gate MOS field effect transistor (f.e.t.) whose

effective resistance is controlled by the gate volta

This voltage is supplied from U2 . The output voltag

of U2 thus controls the gain of this stage.

Additional gain (XlOO) for the module is provided

by Ul and its associated components R13-R14. The

27
output from Ul is coupled by C5 to two emitter

followers Q4 and Q5 . Common bias is supplied by

R15-R16 while R17-R18 are the respective emitter

resistors. Q4 output is connected to J16 (Discriminator input) via C12, while the output of Q5

is coupled to J15 (Phase Shifter input) through

CI 3.

Automatic gain control is accomplished by sampling

the output of Q5 and converting it to a negative DC

voltage. This voltage is generated by C14 , R19, D19,

and CIS. This voltage is connected to one side of

a dual resistor divider composed of R20, R21 , R22,

and R23. The other side is supplied with a variable

positive voltage from R25 and R26.

The output of the divider R20-R21 is connected to

the input of U2 , a XlOO gain DC Amplifier. R27

is the feedback resistor. The output of U2 controls the effective resistance of Q7 through the

low pass filter composed of R28-R29 and C18.

The circuit provides automatic leveling by the

following analysis: Assuming an initial stable

condition, an increase in output voltage results in

a larger negative voltage at the voltage divider.

This in turn results in a negat ive -going input to

28
U2 . U2 is an inverting amplifier which provides a positive voltage on Q7 gate. The f.e.t. decreases

its effective resistance thus decreasing the gain

of Q6.

The output magnitude can thus be controlled by adjustment of R25, changing the level at which

stability exists.

The second divider controls U3 , which is connected

as an inverting switch for Q6 . When the input for

the divider is insufficient for leveling to occur

(less than 50 yv input) , the output from the divider

composed of R22-R23 will be positive. The output

from U3 will be -15VDC under this condition, which

will prevent conduction of Q6 . When the amplifier

output rises to a leveled condition, the negative voltage will be sufficient for the input to U3 to be

negative, which provides a positive output. This

positive output turns Q6 on, which supplies current

to DS2 (Reference Level Indicator). R25 is a base current limiting resistor.

Frequency compensation for operational amplifiers

Ul, U2, and U3 is provided by C9, C16, and C17.

RF decoupling is provided by filters composed of

L1C3, L2C11, L4C19, and L5C20.

29
4.3.3 Test Procedures

Connect the Reference Amplifier as indicated

in fig. 4-lA.

^. a. Set RF Sig. Source #1 to 100 kHz.

Adjust output to 100 yv.

b. Set RF Sig. Source #2 to 20 kHz ± 100 Hz above

the frequency of #1.

Adjust for +5 dBM.

. ' c. Connect Scope to J15.

Output should be 0.8VPP (-0 + 0.5), 20 kHz.

If not, adjust R25 for 0.8VPP.

d. Reduce RF Sig. Source #1 to 50 yv.

Output should remain at 0.8VPP.

e. Increase RF source #1 output to 500 yv.

Output should remain at 0.8VPP.

f. Connect scope to J16.

Output should be 0.8VPP.

g. Repeat a, b, d, and e for RF source #1 frequency settings of 10 MHz, 30 MHz, and 60 MHz.

Do not readjust R25.

4.4.0 Phase Shifter (fig. 3.2)

4.4.1 The phase shifter provides continuous electrical

phase shift of the 20 kHz reference signal with

mechanical rotation of the assembly shaft (360° of

mechanical rotation equals 360° electrical).

30
A

RF SIGNAL

SOURCE k;> -«-5DBM

#2

« JI4

RF SIGNAL

SOURCE

#1

50-500

« JI3

REF B

AMP H

JI6 JI5 7-

+ 15 VDC

-15 VDC

28

• 27 BULB

FREQUENCY

COUNTER

B

20 KHz

oevpp « J-22

« J-23

PHASE

SHIFTER

DUAL TRACE

OSCILLOSCOPE

(OR CHOPPED

MODE) I

C

20000 * I Hz OBVpp

FREQ

COUNTER

Figure 4.1

A

6

'^'"^ DISC H

C

D

E

OSCILLOSCOPE

DUAL TRACE

OR CHOPPED

*^ MODE

«l

Test diagrams

31

+ 15 VDC

-15 VDC
4.4.2 The phase shift assembly consists of a commercial

resolver with a resistor-capacitor divider connected

across the rotor outputs. The 20 kHz signal from

J15 of the reference amplifier is connected to

J22 of the phase shift assembly. This input is

connected in parallel to the two stators of the

resolver. When the impedance of the capacitor is

approximately equal to the resistor value, the output from the RlCl junction is a cons t ant - ampl itude

signal whose phase with respect to the stator input is variable with mechanical rotation of the

input shaft. This output is connected to J23 of

the assembly.

4.4.3 Test Procedures

Connect the phase shifter as indicated in fig. 4. IB.

a. Adjust the oscillator to 20 kHz ± 25 Hz and

0.8VPP.

b. Rotate resolver for in phase signal.

Output should be 1.3VPP ± O.IVPP.

c. Rotate resolver shaft slowly through 360

mechanical degrees. Electrical phase shift

should rotate through 360°. Output amplitude

should not vary more than O.IVPP.

32
4.5.0 Discriminator (fig. 7.4 - 7.5)

4.5.1 The discriminator controls the frequency of the Voltage Controlled Local Oscillator within the frequency

plug-in. It maintains the local oscillator precisely

20 kHz above the external reference signals by providing a bi-directional DC voltage proportional to

differential frequency deviation from 20 kHz.

4.5.2 The Discriminator input (J17) accepts a 0.8VPP

20 kHz signal from the reference amplifier. The

signal has two paths, one to a tuned amplifier, the

other to a 90° fixed phase shift network.

The 90° phase shift is generated by U3 and U4

with their associated components. U3 provides a low output impedance to drive one input of the phase

shift network (R23, R24 , C18). C15 is a coupling

capacitor while R19 provides a dc ground return

for the amplifier input. The output of U3 is

phase inverted by U4 producing a 180° shifted

signal. R20, R21, and R22 provide unity gain. The

output of U4 is connected to the second input of

the phase shift network. Adjustment of R24 provides precisely 90° phase lag from the input.

33
The output from the divider is amplified by U5

.

R26 is a dc ground return while R25 and R27 produce

a voltage gain of 10. This 90° phase lagging signal is coupled to the discriminator circuitry via

C9.

The tuned circuit for the discriminator is an active

filter composed of Ul and its associated components,

(Rl, R2 , R3, R4, CI and C2). This narrow band filter is tuned to precisely 20 kHz by adjustment of

R3 . U2 and its associated components, R5 , R6

,

and R7 invert the tuned signal at unity gain. The

in-phase and 180° out-of-phase signals are coupled

to the discriminator circuitry by C8 and CIO.

These three signals generate a bi-directional dc

voltage proportional to frequency deviation. This

voltage is produced by subtracting the voltages of

two rectifiers. Each of these rectifies the output

of a separate voltage divider. One is composed of

R8-R9 and the other by R11-R12. These dividers

have a common terminal coupled to the 90° phaseshifted signal. R12 is coupled to the 180° signal

while R8 is coupled to the in-phase signal.

The divider output voltages will be of equal

magnitude at 20 kHz, and thus the dc voltage developed

across R13C11 will be equal to that across R14C12.

34
Their subtraction results in 0 dc potential from

R28 to pin 3 of U6 . C6 provides an ac ground for

the divider while RIO serves as a dc return for the

rectified current. Dl and D2 serve to rectify the

ac signal.

When the input signal rises in frequency the action

of the tuned circuit provides a phase delay with

respect to the input. In this condition the output

of divider R11-R12 increases since the two signals

are more nearly in phase. The inverse is true for

the divider composed of R8-R9, since they will become farther out of phase.

Since the AC input to Dl is decreasing while the

signal input to D2 is increasing, the rectified voltage will also undergo similar changes. The net

result will be a negative potential applied to the

input of U6 . The inverse will be true when the

frequency decreases.

This bi-directional voltage proportional to frequency is amplified by U6 . The gain is determined

by the ratio of R15, R16, and R17. The frequency

lock switch (SI on the front panel) is connected

such that R16 is in parallel with R17 in the un35
locked position, reducing the gain of U6 by 5.5. The

output o£ U6 is connected to the VCLO through J7

(pins 1,2) in the locked position and controls the

VCLO frequency. The output of U6 is also connected

to the Frequency Deviation Meter (Ml) through R18

,

producing a front panel display of the frequency

deviation from 20 kHz.

Capacitors C3 , C4 , C5, C7 , C14 , C17, and C19 provide frequency compensation for the respective

operational amplifiers.

L1C20, L2C21 provide dc filters for the input power.

Pins f and k of J2 are shorted to make this unit compatible with a prototype model.

Test Procedures

Connect the Discriminator as indicated in fig. 4.I.C.

a. Connect #2 scope input to Ul Pin 6 (TPl)

.

(See Parts Pictorial)

Adjust R3 for precisely 180° shift (output 6-8VPP).

(Phase meter can be used if available.)

b. Connect #2 scope input to U2 Pin 6 (TP2).

Output should be in phase and of equal magnitude to TPl output.

c. Adjust R24 for zero indication on the 50-0-50

ya meter.

36
d. Adjust audio oscillator frequency for -50 ya

indication on frequency deviation meter (Ml)

.

Counter should indicate 20035 ± 5 Hz

.

e. Record frequency.

Adjust audio oscillator frequency for +50 ya

indication on frequency deviation meter (Ml)

.

Counter should indicate 20 kHz minus deviation

in previous reading ± 3 Hz

.

f. Connect Pin D and E of J2

.

g. Adjust audio oscillator frequency for -50 ya

indication on meter Ml.

Counter should read 20250 ± 50 Hz.

h. Adjust audio oscillator frequency for +50 ya

indication on meter Ml.

Counter should read 19750 ± 50 Hz.

4.6.0 Signal Amplifier (fig. 7.6 - 7.7)

4.6.1 The signal amplifier provides a 20 kHz IF signal

generated from the VCLO input and the output of

the manual gain (front panel) control. This Amplifier has 90 dB gain.

4.6.2 The signal amplifier requires two inputs, a +5 DBM

to the LO input J9 and a signal of no more than

100 yv to JIO. The frequency range is 100 kHz to

100 MHz with the LO input 20 kHz above the signal.

37
The two inputs are heterodyned in a commercial mixer

(Ml). The output is filtered by LP-1, (a 50 kHz

Low Pass) reducing harmonics and LO feedthrough

at low input frequencies. Rl provides a matched

load for LPl , and C2 is the coupling capacitor.

The mixer output is amplified in a tuned circuit

composed of Ql and associated parts. R3 , R4 , R5

,

and CI provide bias while R2 is the emitter resistor.

C3 is the RF bypass. Tuning is accomplished by

LI and C4 . R23 may be added at assembly to provide precise tuning.

Impedance matching to Ul is accomplished by Q2

,

an emitter follower. Bias for Q2 is provided by

R6 and R7 . R8 is the emitter resistor while

C6 and C7 are coupling capacitors.

R9 and feedback resistor Rll produce a gain of 10

by U2 . RIO is a dc return for Ul

.

The output of U2 is coupled directly to an active

filter composed of U2 and associated components

R12, R13, R14 , R21, Cll , and C12. This amplifier

furnishes a gain of 100 with a 1 kHz bandwidth.

Tuning adjustment is provided by R21.

Two emitter followers, Q3 and Q4 , furnish identical

38
outputs from the module. Common bias from R15-R16

controls both Q3 and Q4 while C16 is the coupling

capacitor. R17-R19 and C17-C19 provide individual

decoupling from the dc power. R18 and R20 are the

emitter resistors while C18 and C20 couple the signals to Jll and J12.

Capacitors C8, C9, CIO, C13, C14 , and CIS provide

frequency compensation for their respective amplifiers.

Power line filtering is provided by filters composed of L2C5, L3C21, and L4C22.

Test Procedures

Connect the Signal Amplifier as indicated in fig. 4.2A.

a. Set RF signal source #1 to 100 kHz.

Reduce output to less than 1 yv.

b. Set RF signal source #2 to 20 kHz ± 100 Hz

above the frequency of signal source #1. Adjust

for +5 DBM.

c. Connect oscilloscope to Jll.

Noise output should be less than lOOMVPP

on scope.

d. Increase the output of RF signal source #1 to

30 yv. Adjust R21 for maximum indication on

oscilloscope. Output should be 2VPP minimum at

2 0 kHz.

39
RF SIG SOURCE

#1

RFSIG

SOURCE

#2

«J-10 SIG

AMP

J9

J-ll

FREQ

COUNTER

J-12 -V-

-+I5VDC

-I5VDC

OSCILLOSCOPE

B

20 KHz ±20Hz

0.8 Vpp

20 kHz

PHASE

SHIFTER

J-19 SYN

DET

« J-18

-+I5VDC

--I5VDC

Hi'

PHASE *l

METER

±01° *2

ACCURACY

#1

#2

OSCILLOSCOPE

DUAL TRACE

OR CHOPPED

MODE

DVM

1 mv ACCURACY

Figure 4.2. Test diagrams

40
e. Connect oscilloscope to J12. Output should be

identical to that at Jll

f. Repeat above steps for RF signal source #1 frequencies of 10 MHz, 30 MHz and 60 MHz as desired.

DO NOT READJUST R2

.

4.7.0 Synchronous Detector (fig. 7.8 - 7.9)

4.7.1 The Synchronous Detector contains two identical

homodyne or synchronous detectors whose output voltage is Ecos9, where E is the signal input, and 0

is the phase angle between the signal and Reference

voltages. A 90° phase shift is inserted in one

Reference path, making that detector sensitive to

signals in quadrature with respect to the first

s ignal

4.7.2 The 1.3VPP 20 kHz reference signal from the phase

shift assembly is injected at J18 . CI is the coupling capacitor and Rl a ground return for Ul

Ul is a unity gain voltage follower. Its output

is phase inverted at unity gain by U2 and associated resistors R2 , R3 , and R4 . The output of U2

is the input for the Reference Driver (113) for the

#1 detector. The output of the voltage divider . composed of C4, R5 , and R6 is adjusted for a 90° lead41
ing signal by R5 and furnishes the input for the

second detector driver U6 . The two detectors are

identical and only the number one detector will be

discussed. U3 with R7 , R8 , and R9 amplify the

input signal with a gain of 5, which in turn is

connected to Tl through RIO, a damping resistor.

The detector is an 8-diode full wave, wide dynamic

range, synchronous detector. The circuit is designed

to detect synchronous signals in the presence of

up to 40 db noise.

This requires a reference voltage of sufficient

magnitude to control diode switching in the presence of the maximum noise peak.

Tl is a 10:1 step up transformer which, when connected

to the dual diode paths, alternately switches each

set of diodes into conduction for half of each cycle

of signal. The large voltage step-up insures the

diode conduction is controlled by the reference

voltage instead of the noise voltage from T3. C6

tunes the transformer to approximately 2 0 kHz to

present a non-reactive load to the driver, U3

.

The signal to be detected from J19 is coupled in

common to both detectors by C8 and CIO. Only that

path to #1 detector will be discussed. U4 in con42
junction with Rll , R12 , and R13 is a unity gain

amplifier which drives T3 (a 1:3 step up) through

R14 a damping resistor. C7 tunes the transformer

just as C6 does.

When no signal is present the current in R27 alternately changes direction for each half cycle.

When a signal is in phase with the reference signal, current in the load resistor R27 due to the

signal voltage will flow only in one direction due

to the alternate switching of the diodes. Noise

voltages which are of random phase with respect to

the reference can flow in both directions creating

an average of zero.

When a signal is 90° or 270° with respect to the

reference voltage, the current in the load resistor will

reverse direction for half of the cycle thus giving

a net voltage of zero. The detector is therefore

insensitive to quadrature (90°, 270°) voltages. R23-

R26 are current limiting resistors for the diodes.

Detector output is taken from J4 (pin C and D)

.

Capacitors C2 , C3 , C5, C9 , Cll , and C12 provide frequency compensation for their respective operational

amplifiers.

DC power is filtered by L1C15 and L2C16.

43
Test Procedures

Connect the Synchronous Detector as indicated

in fig. 4.2B. See Parts pictorial and schematics

for parts identification.

a. Observe voltage at J18 with scope input #2.

Adjust Phase Shifter for in-phase condition.

Voltage should be 1.2VPP (± 0.1).

b. Observe voltage at R23--R24 (TPl)

.

Voltage should be 30VPP (± 2.5), 180° out

of Phase.

c. Observe voltage at R25-R26 (TP2).

Voltage should be 30VPP (± 2.5) in phase.

d. Observe voltage at R28-R29 (TPS).

Voltage should be 30VPP (± 2.5), 90° leading

the input signal.

e. Observe voltage at R30-R31 (TP4).

Voltage should be 30VPP C± 2.5), 90° lagging

the input signal.

f. Connect Phase Meter input #1 to junction of

R21-R22 (TPS). Connect Phase Meter input #2 to

junction of R9-R10 (TP6)

.

Phase angle should be 90° ± 0.1°. If not,

adjust R5

.

g. Connect DVM to J4 Pin F. Disconnect OSC from

J19. Short J19.

44
Voltage indicated should be less than 4 mv.

Connect DVM to J4 Pin E. Voltage indicated

should be less than 4 mv.

Remove short from J19. Connect audio oscillator

to J19.

Connect #1 Phase meter input to J19.

Connect #2 Phase meter input to J18.

Connect DVM to pin E, J4

Monitor audio oscillator output for 0.8VPP during

the following steps.

Adjust phase shifter for 0.000 VDC (± 1 mv) on

Pin E with nominal 7° indication on Phase meter.

Record Phase angle.

Adjust phase shifter for 0.000 VDC (± 1 mv) on

Pin E with nominal 187° indication on Phase meter.

Record Phase angle.

Difference in reading should be 180° (± 1°).

Connect DVM to pin F , J4

DVM should read 0.85 VDC (± 0.05).

Adjust phase shifter for 0.000 VDC (± 1 mv) on

Pin F, J4 , with approximately 97° indicated on

Phase meter.

Record Phase angle.

45
Adjust phase shifter for 0.000 VDC (± 1 mv) on

Pin F with approximately 277° indicated on

Phase meter.

Record Phase angle.

Difference in phase angle should be 180° (± 1.0)

Connect DVM to Pin E of J4

.

DVM should read 0.85 VDC (± 0.05)

Average Phase angle readings 1 and 2.

Average Phase angle readings 3 and 4.

, '

' Differences between averages should be 90° ± 1°.

4.8.0 Meter Amplifier (fig. 7.10 - 7.11)

4.8.1 The meter amplifier contains two low pass DC amplifiers, each of which amplifies one detector output

for display on the front panel null meters. An additional filter capacitor is provided to increase the

indicated meter response time constant. These

capacitors are activated by the front panel time

constant switches.

4.8.2 The two amplifiers are identical so only one will

be discussed. The frequency response of the synchronous detector signal at Pin C is reduced by the lowpass filter composed of RlCl . The front panel Time

Constant switch provides a ground for C2 when

46
activated, thus decreasing the frequency response

of the filter by approximately a 7:1 ratio. Ul with

R2-R3 provide an amplification of 4 . R6 is a current limit resistor for the Null meter, which provides a meter sensitivity of 200 mV/10 ya. R4-R5

provides a DC output balance for the amplifier. C3

provides frequency compensation for the amplifier.

4.8.3 The following steps should be performed to insure

proper operation of this assembly.

a. Connect ± 15 VDC to the appropriate pins of J3

.

(Allow 10 min. warm up.)

b. Connect ± 50 ya meter to pin F(+) and ground

(-) of J3.

c. Short Pin c (J3) to ground.

Meter should indicate zero. If not, adjust

R5 for zero indication.

d. Connect + 200 mV to Pin c. Meter should indicate + 40 yamps.

e. Connect -200 mV to Pin c. Meter should indicate -40 yamps.

Remove -200 mV to Pin c.

f. Connect low frequency oscillator to Pin c. Connect oscilloscope to TPl

.

Set oscillator for 1 Hz @ 200 mV PP.

47
Output on oscilloscope should indicate 175-

225 mVPP.

g. Short Pin e to ground.

Output should indicate 30-40 mVPP.

h. Repeat all steps above for second amplifier.

Check output on TP2

.

48
5.0 Frequency Plug- In

The following section contains a detailed description of

the various units and parts contained in each of the plug- in

available for use in the main frame assembly. Where modules

which were designed at NBS are included, circuit description is

provided. Schematics and wiring diagrams are included within

Section 7. Parts lists are included in Section 6.

5.1.0 Plug-in SND/PI-30A (fig. 3.3 - 7.12)

5.1.1 This 30 MHz unit provides the local oscillator voltages for the reference and signal channel first

mixers, the signal summation junction for use in

dual channel null calibrations, and the preamplifier for the signal channel.

5.1.2 The reference and signal channel first mixers require a L.O. which is 20 kHz above the Plug-in

frequency. This is provided by a commercially

purchased VCLO which is tuned to 30020 kHz with

the control voltage grounded. (Sensitivity-6kHz/V)

.

Frequency control is provided by a control circuit

mounted on a printed circuit board located on the

left side of the plug-in.

This control functions as follows: In the unlocked position of the NBS/SND frequency lock

49
switch Pin 2 of P7 is grounded. The resistor

divider composed of Rl , R3 , R4 , and R5 will produce zero voltage at the junction of R3-R5 by

adjustment of R4 , which is the front panel frequency

trim control. This junction is connected through

a low pass filter composed of R2 -CI to the control

terminal of the VCLO. The low pass filter determines the tracking response of the VCLO. When

the NBS/SND lock switch is in the locked position,

the output of the Disc is connected to Rl through

Pin 2 of P7. The output voltage of the Disc

thus controls the voltage at the VCLO control terminal. This control voltage is of the proper

polarity and magnitude to precisely maintain the

VCLO 20 kHz above the reference voltage. This

insures IF frequency stability independent of drift

in either the Reference or VCLO.

The VCLO has two outputs whose magnitude are independently adjustable by a screwdriver adjustment. These adjusting screws are located under

nylon cap screws on top of the VCLO. The two

outputs have a minimum of 60 dB isolation at

30,000 kHz to insure isolation of Reference and

the signal channel.

50
This plug-in is a special purpose unit designed to

be used in a dual channel attenuator calibrator

in which the channels are adjusted for equal output voltages. The plug-in contains the summation

hybrid, which produces a null when the input voltages are of equal magnitude and are precisely

in phase. If a single input is to be measured,

this unit can be used with a 3 dB loss of sensitivity by installing a 50 Q termination on the

second input jack.

The output from the hybrid is connected to a 66 dB

Pre Amp located at the right side of the plug-in.

The Pre Amp output is connected to the Sig Out

jack at the front panel.

5.1.2 Pre Amplifier (fig. 7.13 - 7.14)

5.1.2.1 The Pre Amp provides 66 dB gain at 30 MHz.

This unit is specially designed to insure

precisely 50 Q, input impedance consistent

with a low noise figure.

5.1.2.2 This amplifier is a three-stage tuned amplifier

operating from 28 VDC. The input signal is

coupled through C2 . Bias for Ql is provided

through R2 by > adjustment of Rl . CI and C3 are

RF bypass capacitors. LI and C4 furnish input

51
tuning, while R3 , R4 , and C4 enable the input

impedance to be precisely adjusted to 50 Q.

These adjustments are made during construction

and test and should not be adjusted without

special instructions from NBS.

The first stage is tuned to 30 MHz by C6-C7

in conjunction with L2 , R5 is a damping resistor to lower the Q.

The second stage of amplification is provided

by Q2 . C8 is a coupling capacitor and Tl in

conjunction with C13 is tuned to 30 MHz. Bias

is furnished by R8 , and the output signal is

coupled to the final stage of amplification,

Q3 , from the center tap of Tl through C14.

Bias current for Q3 is furnished by RIO. Output tuning is provided by T2 and C17. The output is coupled from T2 to J33 through C8 from

a tap selected to offer a. SO Q, output impedance,

RF decoupling is accomplished by filters composed of R6C1, R7C10C11, R9C15C16, and RF

filter C9C12. Additional filtering is provided

by ferrite beads on the resistor leads. Dl .

is a zener diode to reduce the supply voltage.

52
5.1.2.3 Test Procedures

Insert the SND/PI-30A into a NBS/SND. Do not

connect the interconnecting cables.

a. Connect a 30 MHz generator to the Sig In.

Connect a 50 load to the second input.

Connect a 50 RF power meter to Sig Out.

b. Set 30 MHz generator to -70 dBm (70 yv)

.

Energize the AC power.

Output power should be -9 min -3 max dBm.

c. Repeat b with Sig In connections reversed.

Output power should be within 0.1 dB. Shut

off all power.

d. Attach the RF cable from Sig Out of the

SND/PI-30A to Sig of NBS/SND. Connect

power meter to either VCLO output.

Energize AC power.

RF power should be 4.5 ± 0.5 dBm.

If not, adjust Osc output control under cap

screw on VCLO.

e. Repeat d for second VCLO output.

f. Connect the RF cable from left VCLO output

to Ref. L.O. input. Connect a frequency

counter to the right VCLO output. Set freq

trim control full CCW.

Frequency should be 30025 kHz min.

53
Set freq trim control full Cw.

Frequency should be 30015 kHz max.

g. Connect 100 yV 30000 ± 1 kHz signal to the

Re£ input. Lock Switch to unlock.

Adjust VCLO trim control for 0 indication

of the freq error meter with Ref Indicator

lamp on. Note frequency counter indication.

Adjust VCLO trim for -50 ya indication.

Frequency should be +300 ± 100 Hz from

reading at 0 ya.

Adjust VCLO trim for +50 ya indication.

Frequency should be -300 ± 100 Hz from

reading at 0 ya.

h. Rezero freq error meter with VCLO trim

control and switch freq lock to lock position. Note frequency reading. Adjust

VCLO trim control for -50 ya, switch lock

to unlock and note frequency reading.

Frequency should be 3 kHz minimum from

first reading.

i. Repeat step h except adjust VCLO for

+50 ya.

Frequency should be -3 kHz min from first

reading.

54
6.0 Parts List

6.1 Introduction

This section contains information necessary in ordering replacement parts. Table 6.1 lists parts in alpha -numerical order

by reference designations. The list is arranged so that the

components on each printed circuit board are listed together.

Where possible, the manufacturer and manufacturer's part number

are included.

A few parts listed will not be identical to those found in

some instruments. The list contains the preferred component;

and if it is necessary to replace it, the one listed should be

used rather than one identical to the defective part.

Certain commercial equipment, components, or materials are

identified in this paper in order to adequately specify the equipment. In no case does such identification imply recommendation or

endorsement by the National Bureau of Standards, nor does it imply

that the material or equipment identified is necessarily the best

available for the purpose.

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S <u m 03 •H e o O f—1 i-H U OJ U (-1 J- !h ^1 !h )-i (h U U o ^ i- l- a. ft X) u o O O O O O O O O o O rJ o o o

o\o 2 T3 <-> 4-) 4J 4J 4-) 4J 4-> (-) (-> rH i-> a: >H +J 4-) LO OJ 0) •H •H •H 'H T-t •H •H M o u u

HJ 0) (/) t/l ft +-> u o o u o o o o u o (U D X 0) <u <u H 3 3 a OJ C 03 03 03 03 03 03 03 a: ^ c c c

CO CO •(—^•(—

ft •H ft ft ft ft ft £1. ft ft ft ft o o dec OJ S-H 03 03 03 cfl rt 03 03 03 o o o o

s: < <: 00 ft ft U U u u u u u U U U C_) LO u u c_)

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(

1—

(

1—1 1—1 1—

I

1—

1

rH 1—1 rH rH to rH

rH 00 '-3 CJ rH 'J- U C_) rj o

o rH LO o rH * rH rH u <NI -7

CJ U U U ft

r- ai 1-1 rH l-O LO

rH 00 rH LO rH rH rH rH (Nl rH LO hO £1, rH rH rH U U U u C_) CJI C_) u u C_) CJ U -J ft ft ft -^

Table 6.1. Parts list RF null detector NBS/SND

56
HJu

3J

u

rt Mh3

C

to

c3

co

C rt

^ -Ha

04

e o H ^1

tl O

tH 4J l-H <U O ' 3: 3: E- <

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o

I—( i-H <N1 f<1 vD 1^ s cro'O'O'O'

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rH(Vll^'*unvJ3r-(CTl,-(r-(l-H^^rsl(V)(Virsl<virsl

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3

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• H

•H c d C <

z c o o o rH a to c d c c c o c c XXX O • H o o c o o o d c X c o o Ih ^1 1- to p Xi XI o C C XXX o o Ih O X X cO CO (0 Z

u o ll in XI o O Ih Ih Ih X X (9 X Ih U U u ^

\0 00 '3- U « X XI rt Ih U u Ih CO (0

ll> vO to O M-l u u u u u rt (fl U u 0\0 <*0 <*v« Ih Q 00 CTl O 0> (fl u u u LO LO LO <U lO O to fO w •to u u *• LO *» •H Z Z 2 2 LO 1/1 LO LO LO «*• «>• «• LO LO a a a Uh

(VI N (SI TS LO d# LO LO c; lo •H a c; LO c: G cs C5 a QO M CiC rH 2 2 O. (U ^ ;^ a i< C3 c; u C3 rH V il> (1> a.

&< &. 2 2 'H c; u< S S 2 e 2 2 CL, O. U. to Ln o ^ LO o ai •r-» <

rH o to o o (VI O O (VI

l-H l-H rH rH (VI tv. ^ rH rH to rH to <£ rH rH (VI rH

1^ ^. )h )h CO O O O O O d

4-1 4J 4-> 4-> «-> (m u Ih Ih Ih Ih Ih Ih Ih V- Ih Ih Ih Ih o

l/l (/I (/) l/l </l o o O o o o o o o o o O O o O O O O •H

•H -H T-l 4-> *J «-> J J *> l-l 4J 4-> 4-> «-> <-> «-><-)<-> <->

>-i <n ifl (/) (fl in (/I in in in in in in in in I/) in in in in I/l in in in CO V e e c e c • H •i-t •H •H •H H •H •H -H •H •fH •H •H •H •H U

K ?3 Co CQ (Q cO in in in in in in in in in in in in in in in in in <D M u u u u u 1) a> 1> <u 1) i) H) (U 0) (U il> <U m 0) 0) O. S H H H H H OS ai a: 0£ S DS OS a: oia OS OS OS a: OS OS OS o

+J rH iH rH to i-H rH (VI rH rH rH (VI rH rH (V) l-H rH rH rH rH rH (VI rH to

CO

PQ2

A'*X

(VI toX

Xo

09CX ID 6 ^- < u

t/5 1)U 13 d CO

0) <u

(h X

0)

1) CO OS a,

u

COs U T3

in ^- H CO

57
Q

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CO

CO

pa

<D z

3

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•H Q

+-> O

c 5. o

u PCo

H

1-H u

w

vD H

w w Q

ca< -JZ

u.

ct:

tno

LO 00 (Nl l-O 1-3 1-2 ^ "-^ o

<N1 O 1—1 1-1 o X

o 1 CT> LD r-- r- 1—

1

o LD z

i-H 1 1—1 Tl- (Nl LTl

1 1 1 1 o

1—1

r O1—1

+-* Z o O O O O 1—

<

O

(- rH iH ,H 1-1 1—1 1-1 1—1 B. 1-1 <N1 rt 1—1 fNJ 1 1—

1

1 o

a. 1—1 2 i 2 i U s: u

.-H 0£ Q (VI Q Q Q Q H o LO

=<t l« vD 00

03 =*: : \ (-. S 1-, A"^ to

(1) (D X 1-1 0) x; MM rsi I/) <D i/l 3 3

to oi dj 1/1 03 J J

X 2: -P 0! S

O CO 3

3t C 1—1 4) 4) O +-< ri'! <U T3 T3

+-> 1—( o! o <D 1—I 1-1 3 O -P O O Z 2 ti- -J CO CO CO

nj O o o o o aj O 0) u o u u o U 3 u 3

•H c c c c C M c M

1- a> (D D 0) (U 03 <u 03

dJ E CO CO E E E E !- E

E 1—1 CO pa pa pa 1—1 1—1 1—1 r-l &, 1—1 < PJ o z z z PJ w w PJ CO w CO

<-:> Z

Z J!M

<fl 3

6 O

0) i-i *^ x:

(/I +j >-> E t3

CO i-( (D O O '^H CH > -O 1-1 1—1

!-i 03 -a

dj 03 -i-J 03 o

CO o OJ OJ •1-1 \-H E X HECO o\° 1—1 < U-i 1-1 3 1—1 E a

O O < !- CT. X

M-l K) 00

A-'

T3 -

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1 W O !-i rt O

x: -H +-> O U l/l

J-1 03 -H 3 Cl, t/1 C- 03 0) U Di

CO XO (/I -oa M

*- 3

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4-1 (D o >

(U 1—I 0) COT)

C 1/1 rH O 0) o

ej d; CO

M p. 3 3

1-1 o

o

1-

(D 4-1

1-H 03 o x:

CO CO

T3

03o

pa

O

03 E

U 03 rt 03 H rt o u

E u -H .H (U •H E E u m E

u-( &, a, 3. O CX, C C C i-H uo r~- i-H rH ^ (vj LO O

t-, ^ ^- o o o o o

u CJ u o u

rt rt rt rt rt CX CL, D. O.

rt rt rt rt rt CJ c_J U U U

c

rt

rt U

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ch

3.

U

rtft

rt U

3 -1 CO 'S- O lO r-l i-H 1—1 rg 1—1 r>j oo t—

i

l—t rH 1-H ro -ac (VI •H 1-H c

o +J u —

a; -fh T3 c U

U 4-1 !- o C rt rt u rH

<u c X (VI 1-H

1-1 M U u

0) -H o 0) Mh t/) 1-H o » ro

0) CD rt (u 1-H i-H rsi u .—1 ro (VI 00 rH Q S 3 u o; i-:! Q u u U U U u U U

58
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T)D z

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dH Q

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1-1 U

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a o rH 3 Cl.

u

1-1 rH e r-H 1—1 o (u o I-I o o H H •H •H U 3 o rt d d )h ^1 4S x; C 00 d !h a> 1) +J '!-> U o

(U R) 0) 0) j3 s: •H r-4 !-i e iH E c a. cu iH l-t •H •H II 0) <D nj OS w w w u a: (J-. IX.

r-tto d

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•H CO

4-> ,V •!-> D. (/) H •H u

!-i ^3 a

U > (/I nS O

Hi CO in Q •H e

d

CO *-> 3 -H

e CO

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&, 3- O rHO O O

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»H (-. !h Ih O O O O

4J 4J 4J 4J H 'H 'H -H u u u o

CO CO CO cO !x cu

CO CO CO CO u u u u

ou

Clfi 3

o

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xi

4-> TS

<u

13

CO

iH x;

CO M

3

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z

Oi PQ

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*-> 4-> o u

0) 0) d d

d d o o u u

e 6 rH

rH rH -H

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MH MH

<U rH iH rH rH CO

CO CO XI 4-> •tJ 4-> CO 0)

0) 4) 4-> 6

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o\« o\o »rH

r-t XS< G

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rH rH m rs)

CO d

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o

CTi 00

fH Ih )h >^ )h O O O O O O

4J 4J 4J 4J ^ 4J

l/l (/) (/) (/I V) I/l H 'H .H 'H .H 'H

(/) C/1 VI </) t/1 I/l lU <U <U H) V 4) oi a: ce: a:

e •H

iH IJH rH •H d d LO O

Uh d d o O rH C rH O O XI 43 CO O

rH C X X tH in VJ 0) X

CO O !h i-i CO CO (1) rH

4-> X CO CO U U e X CO 0) u u o CO U 0) S CO c.\» •H •H U c»\o o\«> LO LO rH t/1 c\« t+H UH

LD LO 3 LO •H H

rH o\= G G G -r-i rH rH LOGGiatiNiS^'O W) oUS < (U s o o (NJ 2 < <

O O O o . (VI rH (Nl (NI r-t r-{ r-{ rH rH

CO CO d d u u u u u U U U U o o

o o o o o O O O O H •H

4-> 4-> 4-> 4-> 4-J 4J <J 4J +J +J

</) (/) to t/i to t/l t/) (/I t/l CO CO •H •H 'H 'H 'H •H 'H -H -H t- U

(/) C/l (/) to 10 to I/) (/I to (U (D

0) (U 4) <U O) 1) U 0) 0) a Qa: ce: 02 oe; a£ a: o:: a: o O

rH (VJ to rH rH rH rH rH LO

<0 -H

rH c to (NI

(L> d u (Nl OO -J

1) 'H

<4H to LO |-~- O

tU (1> r-t r-t T-t r<\ rH rH rH

0=: Q U U U U rJ

(NI oo

(NI » rH (Nl Oi rH oi Oi

rH

pt: - a: rH o LO

« CNI •> rH rH (Nl o OS a> Di Cd 3 3

"O «(Niot')Lor— CT>tOTtt^ rH(NI^O«a-LO(Nl(»rHr^rHMfHrH(NJCVl(NI rHCNJLO

a: a: ci. Oi. a: ai ei ot en ai ac cc cc 333

59
0)3

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w

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PJH

PJQ

PL.

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I PJ a Q

<=> '-i O O f-H .H 1-t X i-H t-~- \0 ^o i-H ^ c o c c S

CJ f-H i-H r-t ,-( O I I I I fNl LO s 2 s: s: <~si ^ o Q a Q

i-H 'S- <

(Nl I-H

1 <V1 O <N1 vD o

CTi r-- I-H

(L> 0)

o (D O o o o

3 u 3 U u o u

+J M •!-> c M C c c c !-> 0) « D (U <u CO 6 ^- e e f- e E e E E

CQ 0) ex <u I-H 1—1 I-H <u 2 PJ CO PJ PJ PJ w

o

c

<ucxE<

toc

e x: 3 E E OO e I-H 3 3 3

3 CO .-H .-H o

1—

(

+-> CO CO (h

CO o C P 4-1 j:: o U) CO d 4-1 •H •H +J CO CO 13

•M CO -T3 •M M <t) CI. U (b

• H u p U u Mh Q CO u Q E CO g CO > U -a

l/l > CO LTl u CO O CO • H CO X r-j •H C CO u -H u e <u (U Q rg vO LO <U E (VI O "H E 'H •H l-O 1-H ^0 =«= CO U •HE E E I-H CO X o M-H CO E

X pa D. mh a.<4-i d 3

O =»= 3. 3. o C

PQ PJ 4-' ch C 3. Cu O 3. H

;g 00 •H 3- LO O c c c O 4-) D.

D. (D rt at \ u. 3 o • (Nl l-O LD T-H E !- u >0 "3- K1 r-l LO o o CO < U -J

(/) B. H E E

(U 3 U i-i j-i )_ (-1 !-, !-. i-. S-i u -d CO t/l 1—

1

< O o o o o o o o o O O o o CNl o o

C n; X S -1-1 CO •l-l •M 4-1 +-I 4-) +J 4J 4-> •!-> 4-> +-> r-i 4-1 4-1 <U (U -o LO S -J (U • H 'H H -H .H -H -rH •H T-l o u c < M U u u u u u u u u u o o (D 0) CU <u O -M ^ 13 2 c CO CO CO CO CO CO CO CO CO CO CO CO c c

c M T-H CO u r-H •H P. Cl.Cl,D.i:i,P.CI,P.CuP.P.P. O O c

OJ CO 3 >..-l o O I-. CO to CO CO cO CO CO cO CO CO CO CO o o 2 2 P- J &. u u u U u u u u u u u u u u u u

3 rH rH^t30^'3-^i-H I-H VO rH rH rH rsj iH rH rH rH c 4-1 O

C71 rH C i-H U rH o U 1^

(U c_> u 4-" (U 00 (vi CN) c CO H - iH ^o o iH o

QJ C CO rH O U 1—4 iH U U ro u • IS U U U u •-^ OJ •H

I-H (/I (/) i-c t-H vCl I-H LO rH I-O » (VI D QJ H CO < rH rg i-H t~0 LO 00 cn rH rH rH rg (VI LO 0\ rH Q u u U u U U U U U -J _) -5

60
Q2

pa

<u 2

3

C

• H Q

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C s: o

u o

i-H Uw

f-w

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•H CO o <u pa a: n. 2

to

CT> to

B r-(

d d d •H lh C LO

t-t C d o o o d LH rH oca rH

i-i C d o o X XI X o rH CO X o t^ o o O X2 X ^ !- U X rH CO 4-) in X O

t/l 00 XI XI Sh S-i CO CO CO s- CO 4-1 (D CO r-j X

0) vD r-- to ii CO CO U O U CO 4-) <U e U CO cvi vO Q CO o CO CO a u u a> 6 U 0) D X to u B <a\= rH o X 2 2 2 o\o o\o in LO LO 0\» rH LO oV^ X LH PQ vO in

^^^ (VI LO

o\0 LO LO

LO GO,

LO

C5 rH

rH

CS LO CO G 4-> rH t- o

t-

(U 2 2 a. cs cs ^ :^ be; c; CS S<i t«S CS in a 0) in X

D. 2 G M ^ 3 H 3 in 2 2

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LO O

o

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S-c CO

i- LO i-H i-H ^ rH LO LO (VJ rH rH OO < rH rH O OJ t- in (D

^- ^- CO CU 10 X rH OJ o o O d e (VJ in <U X 3 in

•!-> *-> (-) u u u u ^ u )-< 1- o < to CO 0) in -J (0

(/•, IT, IT. O o o o o o o o O o o O O O to X 2 *-> CO

*-> 4-) <-) 4-1 4-1 4-> 4-> 4-" 4-> 4-> 4-1 4-> 4-> 4-> 4-1 rH 1) CO u

1-. t/l in 1/1 (A {/) t/) tn (/) i/i (/) in in in cn in in in CO CO X d D rH D c C c •H -H -tH -H -H H .rH H •H •H •iH -r-t -r-* u d o 4-) ^ a

X CS CO CO If) l/l l/l t/l 1/1 t/l in in in in in in in in 0) CIO c 4-> rH CO o rH 0)

^- i- ^- 0) 0) 0) (D 0) CL) (D D 0) 0) OJ 0) CO 3 >>rH o O 4-1 H E- H Qi oc: o; oi d; o: Oi d; o; ct: OS o CO Cl. 2 2 u. _J CO C/5

3 -H rH rH rH rg rH rs] to rH (NJ rH rH rH rH rH CNl t-H (Nl rH O

3 OS U 4-> vD cyi u

d CO OO o rH r-l CO D d rH rH OS OS X

to oc: OS OS rD

OS o

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0) (U rH rH (Vj to rH rsi ^ LO ^ C» (31 rH rH rH rH rH rH <V) rH CO q; q cyo'O' OS OS OS OS OS OS OS OS OS OS OS OS OS

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61
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(-> i-H O O O LT) >^ (NJ Ih O. i-H rH 1—I i-H Q (NI

CT3 t 1 1 1 1 o O 1-1 UL. 2 S S S L/l (vj 1—

t

o

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C C C C OO a; m 4-» 03 (D (U (U (U nS r—i • H

to ^ e e e e as rH iH m r—1 t—1 .—1 D. e 00 H <u 2 CO UJ lil UJ w to < o a:

6

3 a

rH o

03 u E

d P x: (S rH o O C p O -H

•H t/l oi t3 ^ Mh

• H t-i (U !h (U 03 rH d d

•H U <+-! d d u 0! o o o Q o o p ^ d X) d

u H OS > Id X) -Q oso <u fH O 1h o

l/l e U 03 ce fH f-i LO E 03 0) ^

<u ^3 03 'H o3 L) LO o (U 03 03 U tn u ^ Q Pd U O E tJ -H (NJ O <J (D 03 0) O 03 <u •H .H e (NJ rH rH oS= L) o\» O H O U 2 rH o\o o\o X LO LO U Pr 3 LO LO 03 G o\= W t+H (-H M-l P.(+-l C Z3 P « C; Ln G LO H +-1 CLrO p, ;i E •H a cs fi t«i W o o 3 P<^ 1^ fc^ 3 LO G CI Q 3 o o (NJ t-^ r-~ H •r-»r- o O

u (NJ rH (30 (Nl ^ (Ti to rH O "0 • O O O .H

to i-i 03 LO rH <^ (NJ ,H iH LO •H E E O !_) fH t-H ^ ^ f-> fH ^H 2 O O O O O O <D O O (NJ in fH fH 1h fH 1h i- iH O tj M 4-1 +J +J +J 4-1 P P (NJ o o o o o o o o

ct: H •rH -H .H 'H u u 4-1 P P P +J P p p

3: M tJ o u u o o <u <u 0) (/I t/l t/l t/l t/l 1/1 t/l t/l u c 03 03 03 03 ct3 03 T3 c c • H 'H -H -H 'H -H •H -H 2 P. Dh P. P. P- o d C o (/I t/l t/l t/l t/l t/l t/l t/l >- u 03 ct3 03 03 c(3 oj •H o o X. tD (D (D CU (D QJ (P tu to tJ C_) tJ U t_l U Q u u u Di Oi Oi Oi cd cc: oi oi

c

053 •H iH VO rH (NJ (Nl (Nl \0 rH (NJ (NJ rH rH rH (Nl (NJ \D (Nl cy *-> rH

Kl O m

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(30 (O rH rH rH tJ ^H (Nl r-~ Oi Oi ci (n (NJ Qi cd Oi

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<4-l t/1 rH * •• Ln (30 <3i 00 rH O rH LO r-

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c/l I-" cw to o o z e Ul LO Ch

tA •H X m Z '+H G CO LO H

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(Uin d CO o o 3

CU -rH u *-> C CO to 03 o CNl CU d c; i- •a- LO VO CNJ 1-H 1—

1

(NJ Ih oo u u u o; a: rD

CU rH CJ

IH^ c/l c/l rH

CU o 1—

(

CO rH < 1—t (Nl to to oo to LO o

o; Q H u u u -1 IX a: 3

63
X)

HIc

<

o

tH D (->

(-> 03 o >- 1/) 03 O

Pu O o M

C O L) u 0)

03 u (U

c; • • 3 t—1 1—1 ^

c c o d O O "-M o o o

03 o c o U U 0) c c c

u u r-H flj 0) <U

t/1 rH r-( ^-1 J= X ^

X 03 It (-> d Cu CX m (D LD CO CO CO CO pj .H E E E

7^ H O c o o c c < c o o o Q Q U -J < < <

d >,

03 -t-" 3

cy -1-1 01

i- co

<L> i- (J o; c 03 0) d u

Cm (/I in o (LI rH Q

(VJ O

CO

(vj fvj <a^ <^ <^ <^

4J o ^

1 O O (-H i-H rH r-t p—

(

(VJ r—t (—1 O O O O O

(Nl (VI (V] (VJ (V] ^ Cn] (VJ (VJ (VI (^ o . o 1 i Q Q (~) \^ f~i \J {~i <f^-1, f~i u M -M 4-1 +-J ^ _ oo

00 (VI (O o d '—

'

^ 1

^

1 r—<

1—1 1—1 <C <!•<< 1 fvj o d ' 1 1 1 I ^ 1 X

O .-H f—1 ^ ^ 1 I-H t-H 1—1 1—

1

(VJ < (VI (V) (VI (VI CD O o c o 3 O (VI (VJ u (VI (VI (VI (VJ (VJ (VJ 3 (VJ (VJ rvj (VJ U 05 (O to 1 (VJ

3

o

X M e o

rj \£> 03 03 M

X t^. at 4) U CJ O X S-i H A"' 0) K so x> o d

3t <U OS d d

u « o

1/1 ^- O (VJ ^0 oo cri u QJ u

•r-l <U 03 03 LO (VJ (VI (VI (VJ (VJ (VI D. 3

Cm - - CO > (VJ -) •-^ C- G, B. CI. &. t3 E (—1 Cu C

•r-l L> (D d 03 o

r-H CO J= (L) CO C t—

1

Kl •rf Ul (» LO x: 3

a. Wl <u x: CO o ^ 1—1 iH ivj (VI fvi (U O M

03 (// < (-' a. Ci, D- a. U 3 >- < oi 03 05 (U d d Ml ^ O

<u u 3 QJ OS QJ 2 u ~ d d QJ QJ (U 0) 1) (L> <u OJ d) OJ o a o

o +-> <u I-H .—t I—

(

r—1 rH (H .H 1—

1

.H a, (D .n QJ ^ d M 03 O I-" X) X) X: X X X X X X X (+- rH t/1 d QJ

cu 03 >v o < M 03 03 0) 03 03 o 0) 03 03 u QJ 3 3 >, >- u

0- J < U U U U cj u u u U U < d; oa u, CO tl- <

Tf oo 'd- ^

1—

1

(^0 K1

rH (VJ tn LO o oo (ji rH fH

-J -J _j _J -J x: rJ iH (VI H oa pa CQ CQ oa CO CQ pa CQ CQ CQ CO CO < (_) CJ U U U u u U U (^ ca Q ^ o r-- OO

64
Q

Z

c/^

13 CQ

<D3

C Q

M c

co

u d;cH

>—

U

tu

PJ

a: Q

cc _J <

s

o Z Q Q

z L,T 1/5 LO

CQ CO O C O

+J H ^- rg rg ^ 1—

rsi rg H H

Ci, (—4 rg CO m

I—

i-DM

U

03

C

03

D

(U o

C C

O O

(/I VI P- O- E e

• rH -H

oc

n

a. o o o

u u o ^ ^ ^

< < <

LO CO CO

oa ca ca z z z

•H 1-1 +J O X

P.

rH t-> oo oo

!- C oo \ 00 u o : to to \

1/) U LO X X to rH

CU X X o rg : X Q 0) o rg at at K5 4-1 O 3 u !/) 'S- X X

4-> 13 (-> 03 X X yi ^ t/5 \ to z

nj O c at ai 1/5 1 00 O B J3 3 (15 3 '—

•H O c/: C/l .c 3 t/l OJ X to >

t-J u T3 3 3 c/1 at 3 1/5 at (D 4-J : a o O +-> +j (I) 0 03 Si m u _~ X 4-> HH 4_i 3 • H c c 03 at S 1/1 »-l s 1/5 at O D.

03 CO 03 o U U o !- 1/5 e 4H rt

S- U t/l 4-1 QJ >- C 1/5 ;/5 U5 r—1 flj 1/1 rH 0) O rH U

O -rH (- <r, X 4h H l-J <U ^ 4) 3 13 ^- 0! o; 13 o (J i-^ C CO 03 13 <U i/i 13 (U 1/5 ^ 03 U 4-> J3 rH

i- c p o D O ;/) M 03 03 z +J 03 n) fl- 4-J 03 <D (D CO c w >— u -J QJ (U (U CO 3 <u at CO Sh j3 B >- O (D -rH 1/5 J3 d J3 05 QJ 4-1 o; +-) a".-i c O I/) o 4-) ^ c/5 4-> ^ 13 4-J X2 (U (U rH rt c CU B C C O C C M 1—

03 U 4-) U ,_i 03 ^ OJ X5 rH o

o u •rH 0) D 03 C 03 03 D Xi-I o 03 D rH o O rH 3 -rH o rH u- z u < f- U O id CL Z Z tu _J a. Z P-, -J CO U. CO B- a,

>,

(-> rg rg rg c oo oo oo oo 00 rg rg rg rg 1—1 o ^ ^ rH rH rH

0)

(-1 nS3

13

>-i nS

rH r^J to

CO CO CO

65
<

(SI z

ea z

3

oz

t-c <u

)-< D

•Pu

03

<+-! D

(S

rt

oaz

c

o

•H

p-

'tH

!-i U

(/) 0) T3 Q !-<

Cfl O

CQ

+J

• H3

u

u

•Hu

dJ < *-> fS •H

&. a,

C >N

CO I—

(

C -i-i

c

o

(U 'H U +-) C

<u c

(-. DO

<U -H

t—

1

0) <u <

G.

00Z a:

Oh

a)3

nj o

o

oJ

o 4>

CO C

•H P a> c d d o d

13 C

M-< CO >-H00(U0j3C|0

x> XI r-t Si o Si U (O^I-i^V- 03Xi>-'

CO CO CO Pc0o3o3o3l)>hO3

e LD (J U U Ln 1/1 U O P U 03 U

CS (VI .H 'H -H 3 i/l U

t-. 1 E e 6 I-I •r- o^o 3 cf^*' l-O 6°

(D <^ 00 3 tJ^ LT) • >—I LO o\o LO U >-H M-l e o vO < -a C? LO

r~ 00 ^ txi < G i^t: 1—

t

•r-, ^ Z •ri- ^^ C T3 00 Z o o i»i o r- :^

<; o to •«r >—

1

(vj •rH (VJ o (VI oo r--

(-1 • x; Ln(V]^r-1(V]^t-H^

(U E 1-1

(-. ^ i_ ^. ^1 c •1—

t

i-i o

o o o o o o o p

-> +J 4-1 +J +J !-> M CO (VI p (A OOOOOOOO H •H -f-t L) H pp+jppppp

u u u u u o 1) 0)

03 CO (0 CO CO CO c

D. CI. O. (1, Ok o o o c: 03 l/)t/)(/lt/)t/lC/l(/lC/l

03 cO CO CO CO CO • t-( ^ j= o t- U u u u u u Q u u u H

I—I I—I rH l~0 i-(

cn 1/5

to

.—I

T-H u

(VI

(VI U (_) O GO r-- rH rHi-H.—l'*rHl-n>000.-H

o-

.-H(vjrO'!rLn%oc^oo

Table 6.2. Parts list plug-in SND/PI-30A

66
033

C

CD2

CO

2:

a)3

PVi

o

o

vO

C/) o

w

ou

o

0)

oi

(NJ (SI fsl (N) (Nl

I I I f I -H O O O O O

O i-H I—I I—I t—I t-H

(Nl <N) (Nl CNl CNl (Nl (NJ CO I I I I I I ^

I <<<<<< 1-H I—I r-( I—I 1—I t—

VO O O O O O O

(Nl (Nl (Nl (NJ (Nl fSJ CSJ

o

c

03 E z <

(-1 o

!-> u

c

o

c

o ^1 H o

+J Ih •p P. d rt d d d OS H d o o d O (D O f—

o ^ o O ^ rH rH T3 u Sh ^ M X3 in • H H

(/) U 03 03 o3 03 03 u V- 13 P

(1) OS U d O 03 O t-J O I/l 43 03 3 Q u o o in o >^ O P.

03 oXO o\o 3 rH d

6= LO Q o LO LO •r~~iU-i 13

LO LO X) 0) DO a

CI < G <- C3 rH d C +-> I—

•H o OJ CQ H <r a O X) LO oo a-, rH c c X 3 c (Nl iri rH !- e o (Nl (Nl (O

(NJ C (Nl -J u LO LO 4-1 o a. "-^ (NJ (—

O I-H C» LO LO d u d X cc •H o o (Nl to \o OO

•~D H u u +-> H u K1 to hO K3 to

*= 2 O ti i-i !h (h (h M o Cl. D. Ch Cl. C- o. o o O +-> O o O O O (D o 03 p

•(-> 4-' i/l u (U •H l-J 4-> 4-> -P -P DO d o

l/l (/) •M u (/) (/) 1/) (/) (/) 03 •H CD OJ <D <u (U 01 OJ

0) o d 03 •M (h e d rH rH rH rH rH rH

(/) (/) X -J P. (/) l/l (/) t/1 (/) rH 3 u d 43 -Q 4D ^ 4D -O

(U (U o u u 03 QJ <D (U <U (U O O <D o 03 03 03 03 03 OS pa c/5 > a. U o; > Ll- u U u U U U

C X

0) •!-> 3 'H 1—1 1—

f—

•St- r—

r—t I-H rH rH rH rH rH rH (—rH rH rH rH C •->

co

dJ -H U !-» 0) d 03 in

(U d OS r-l -a

t-. 00 (Nl LO xO

(D .-1 o O

(/) o -J 43 r-l _J _J -J -J rj

QJ OJ G~i T-H 03 r—t (Nl ro LO rH pa pa P3 CQ pa pa

Oi Q > U > u u u u

67
u

u

3o

3

Q

o

(Nl OI (M O 1 l/l O

i-H vO

o o u u

c/2 CO CO w w to

PQ oa pQ w to oa Z Z Z 3 3 Z

3 -H

c

o 5

lU 'H U +J « C

CJ c

(U -H u

1/) <u a> l-t Oi Q

00\

A" A' X X X vD : X o f-^ *: rj

ro X

X X X in X

T—t ^ \D vD >H 3E 00 o at at at 4) *:

4) l/l O X 3 00 T3 e DC 3 in 4) 3 *:

• H O c cn c 4) CO 4)

t/l *J o C -H t-l (l Ifl 1/1 3 O ^ in P +-> t—H u H u u ^- ^ O l/l u f- 3 O ^1 3 1/1 lA 0) HJ in 1-H 1/1 4) O OQ c E 3 U 4) X 03 H U D 00 13 1/1 1/1 TJ 4) 03 T) in

ij) in Oh (U i/l rj CO oJ cC 03 03 vO (-> 4) 03 00 03 •H in X 4) 1) 3 3 <D *: in x: 4J *=

1/1 <n <-> x x: x; X I/l 1/) C X3 XI in +-I •!-> in M

03 03 o o O 03 •M C C U U c 03 CO C o

x: X c C ^ 3 03 CO O O 03 3 1 r-H OS 3 o u u i»J to Z &. D- -3 —

1

Cl. 2 U, ti. &, Z -J

1—

1

<N1 O ^ ^ oo 00 vD ^ -a- •cr

68
7.0 Schematics, V/iring Diagrams, and Ccmponent Location

7.1 Introduction.

This section contains schematics, parts pictorials, and

wiring information for all non -purchas ed assembly. This section also contains complete information on the various Plug-in

units available

.

69
MASTER WIRING DIAGRAM

AMP)

A -<- BH

NOTES:

I.S-I IN LOCK POS.

2.S-3, S-4 IN FAST TIME

CONSTANT,

8 7 6 5 4 3 2 1

Figure 7.1 NBS/SND master wiring diagram

70
Figure 7.2 Reference amplifier schematic

71
Figure 7.3. Reference amplifier parts pictorial

72

Figure 7.5. Discriminator parts pictorial

74


77


Figure 7.11. Meter amplifier parts pictorial

80
LiJ

too

ffil k5^^

CVJ

o

ro

-3

Figure 7.12. SND/PI-30A schematic

81
ro

ro-3

g

a:

I

I

a. m

(OCVI

?4H

K

S5 . St l^zS

5f

Figure 7.13. 30 MHz Pre Amp schematic

82

O

UJ5

UJCO

X

o

< o

— cvj ro
S

Figure 7.14. 30 MHz Pre Amp parts pictorial

83

FORM NBS-114A (1-71) U.S. DEPT. OF COK':»1. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBSIR 73-302

2. Gov't Accession

No.

3. Recipient's Accession No.

4. TITLE AND SUBTITLE

RF NULL DETECTOR NBS/SND

5. Publication Date June 1973

6. Performing Organization Code

7. AUTHOR(S)

Robert E. Stoltenberg

8. Performing Organization

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS, Boulder Labs.

DEPARTMENT OF COMMERCE

Boulder, Colorado 80302

10. Project/Task/ Work Unit No. 2724457

11. Contract/Grant No. CCG No. 71-44A

12, Sponsoring Organization Name and Address ARMY /NAVY /AIR FORCE

Calibration Coordination Group

13. Type of Report & Period Covered

14. Sponsoring Agency Code

I 15. SUPPLEMENTARY NOTES

16. ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant

I bibliography or literature survey, mention it here.) This report describes an ultrasensitive receiver for detecting low-level rf

signals in the nanovolt region. The primary purpose of the instrument is to detect

; the balance condition in rf bridges; however, it is useful in any comparison

I measurement in which two or more signals can be adjusted in phase and magnitude such

that their summation results in a null.

I The receiver frequency is determined by individual plug- in units. Units have

1 been built for selected frequencies from 100 kHz through 30 MHz, Detection is

i accomplished by double conversion. The first converts the signal of interest to a

I common intermediate frequency; the second performs a dual synchronous (homodyne)

ij conversion. The dual detectors are sensitive to signals in quadrature with each

! other, A reference voltage synchronous with the null signal is required. Thus, the

j dual detection provides an indication of both the phase and the magnitude of the null

I unbalance,

1 The output of each detector is displayed on a zero-center meter, thus indicating

the direction of unbalance as well as the magnitude. This information is also

j available at a rear panel jack for use in servo control of the external system.

Gain adjustment over a 90 dB range is provided by a single front panel control,

j Phase adjustment to compensate for differential phase delay between the reference and

null signals is accomplished with a front panel 360° continuous phase control.

7. KEY WORDS (Alphabetical order, separated by semicolons)

I Detector; phase sensitive; RF null detector.

18. AVAILABILITY STATEMENT 19. SECURITY CLASS

(THIS REPORT)

21. NO. OF PAGES

m UNLIMITED.

UNCL ASSIFIED

1 1 FOR OFFICIAL DISTRIBUTION. DO NOT RELEASE

TO NTIS.

20. SECURITY CLASS

(THIS PAGE)

UNCLASSIFIED

22. Price

USCOMM-DC 66244.P71

USCOMM ERl.