NATL INST- OF STAND & NBS

PUBLICATIONS

NBS SPECIAL PUBLICATION 400-66

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

Semiconductor Measurement Technology:

The Design, Testing, and Analysis

of a Comprehensive Test Pattern

for l\/leasuring CMOS/SOS Process

Performance and Control

*
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or 8TANDASDC

LIBBABT

Semiconductor Measurement Technology: ^

The Design, Testing, and Analysis of a

Comprehensive Test Pattern for Measuring

CMOS/SOS Process Performance and Control

Loren W. Linholm

Electron Devices Division

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, DC 20234

Sponsored by: U.S. Air Force

Air Force Wright Aeronautical Laboratories Wright Patterson AFB, OH 45433 and

Defense Nuclear Agency

Washington. DC 20305

*/ vxjaiL, I" \ WJ

U.S. DEPARTMENT OF COMMERCE, Malcolm Baldrige, Secretary

NATIONAL BUREAU OF STANDARDS, Ernest Annbler, Director

Issued August 1 981
Library of Congress Catalog Card Number: 81-600078

National Bureau of Standards Special Publication 400-66

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-66, 148pages{Aug. 1981) CODEN; XNBSAV

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1981

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402

Price $5.50

(Add 25 percent for other than U.S. mailing)
Table of Contents

Page

Abstract 1

1 . Introduction 1

2. Approach 2

3. Test Pattern Description 2 3.1 Test Pattern NBS-16 2 3.2 Test Pattern NBS-26 7

4. Electrical Measurements and Analysis Techniques 7

4.1 Measurement System Description 7

4.2 Statistical Analysis Techniques 10

5. Evaluation 11 5.1 Process Parameter Pattern 11 5.1.1 Lot-to-Lot Contact Resistance Variation 13

5.1.2 Intrawafer Contact Resistance Variation 13

5.1.3 Lot-to-Lot p -Channel Threshold Voltage Variation 16

5.1.4 Intralot Parameter Variation 21

5.2 Random Fault Test Structure Evaluation 23

5.2.1 Random Access Fault Structure (RFI) 24

5.2.2 Gate Dielectric Integrity Array (RFII) 34

6. Conclusions 38

6.1 Process Parameter Pattern 38

6.2 Random Fault Test Structures 40

Acknowledgment 41

References 41

Appendix A - NBS-16 and NBS-26 Topological Design Rules 42

Appendix B - NBS-16 and NBS-26 Test Structure Description 58

Appendix C - Variation in p-Channel Threshold Voltage for Eighteen

NBS-16 Process Validation Wafers 93

Appendix D - Critical Electrical Parameters from One NBS-16 Process

Validation Wafer 112

iii
List of Figures

Page

1. Test pattern NBS-16 functional layout 3

2. Computer-generated plot of test pattern NBS-16 5

3. Computer-generated plot of test pattern NBS-26 8

4. Block diagram of computer-controlled electrical test system ... 9

5. Typical computer-generated gray-scale wafer map showing test site

location and intrawafer parameter variation 12

5. Average metal-to-rz^ contact resistance, Q,, versus lot number and

average metal-to-p"*" contact resistance, ^, versus lot number . . 15

7. Wafer maps of metal-to-n^ contact resistance at 87 test sites and

n"*" sheet resistance at 90 test sites for NBS-16 PVW AlO 17

8. Wafer maps of metal-to-n"^ contact resistance at 91 test sites and

n"*" sheet resistance at 95 test sites for NBS-16 PVW A9 18

9. Wafer maps of p-channel threshold voltage at 83 test sites for

PVW A16 and PVW A11 20

10. Wafer maps showing location of nonfunctional n-channel MOSFETs

and n"*" sheet resistor test structures for NBS-26 PVW B4 22

11. Random access fault structure, RFI, contained on one NBS-16/26

test pattern 25

12. One random access fault structure RFI, showing a micrograph of a two-by-two section of MOSFETs and a schematic of the electrical

interconnect 26

13. Test results for one RFI array from NBS-16 PVW A1 28

14. Test results for 268 RFI structures from NBS-16 PVW A6 29

15. Test results for 268 RFI structures from NBS-16 PVW A1 30

16. Histogram of breakdown voltage, Vg, volts, with devices with

a source-to-drain leakage current greater than 50 nA/mil gate

length for NBS-16 PVW A1 32

17. Failure map showing approximate location of RFI structures

containing MOSFETs with high source-to-drain current leakage . . 33

iv
List of Figures (continued)

Page

18. Gate dielectric integrity array, RFII 35

19. Yield versus number of elements tested from NBS-16 PVW A6 with a leakage current greater than I.OviAatlOV 37

20. Yield versus number of elements tested from NBS-16 PVW A6 with a leakage current greater than LOxlO'^^yAatlOV 39

List of Tables

1. Device Types on NBS-16 4

2. Photomask Levels 6

3. List of Structures Evaluated on Process Parameter Patterns ... 14

V

Semioonduetov Measurement Teohnology

The Design, Testing, and Analysis of a Comprehensive Test Pattern

for Measuring CMOS/SOS Process Performance and Control

by

Loren W. Linholm

Electron Devices Division

National Bureau of Standards

Washington, DC 20234

A Process Validation Wafer (PW) is a wafer containing only test

patterns. One PVW accompanies a product lot during the fabrication

process. Test patterns NBS-15 and NBS-26 are designed to be used

on PVWs. They contain both process parameter test structures and

random fault test structures. Eighteen NBS-16 PVWs were fabricated

in a radiation-hardened silicon-gate CMOS/SOS process. These PVWs were tested on a high-speed computer-controlled dc test system.

Test results from the process parameter test structures were used

to establish the baseline electrical parameters for each product

lot and to produce an eight-level gray-scale wafer map for these

parameters. Based on correlations of selected wafer maps, it was possible to identify specific yield-related process problems

otherwise unknown to the manufacturer or user.

Test results from two random fault test structures were used to

establish a statistically significant data base for identifying and

evaluating major yield-limiting fault mechanisms in the process.

Test results from a developmental random access fault structure and

a gate dielectric integrity array are presented. The results are analyzed for selected PVWs and a major yield-limiting fault

mechanism detected. A description of the test pattern and test

results, including a drawing of each test structure, recommended

test procedure, and design rules, are found in the appendices.

Key words: integrated circuits; microelectronics; process validation wafer; random faults; silicon-on-sapphire; test pattern; test

structure; yield.

1 . INTRODUCTION

With the increasing complexity of integrated circuits, it is becoming more

difficult for both the manufacturer and user to fully characterize circuit

performance. Functional testing alone is an impractical approach for evaluating complex circuits. As a result, greater emphasis is being placed on re- sults from microelectronic test structures which provide clear and unambiguous test results [1].

The objective of the work covered in this report was to develop process as- sessment methods which use microelectronic test structures and which can be

used by an independent organization to evaluate the electrical characteristics and yield potential of the integrated circuits being manufactured.

1
2. APPROACH

The approach used in meeting the objective of this program was to design,

test, and evaluate a test pattern consisting of many well-defined and wellcharacterized test structures together with several developmental test structures. Test pattern NBS-16 was implemented as a process validation wafer

(PVW) [2,3], a wafer consisting only of identical test patterns. One PVW was processed as part of each production run at RCA in a developmental program

being conducted under Air Force Wright Aeronautical Laboratories (AFWAL) contract. The PVW was subsequently tested and evaluated at NBS. Midway through

the program, a modified test pattern, NBS-26, was designed based on the information and experience gained from testing NBS-16.

The test pattern was designed in a collaborative effort by NBS and the Jet

Propulsion Laboratory (JPL). Three areas on the test pattern contain structures designed by JPL. These structures were merged with four areas containing NBS-designed structures. Final pattern layout was performed by NBS.

Testing and analysis of the structures was to be performed by the respective

laboratories. Only the test results and analysis of the NBS structures are included in this report.

An automatic computer-controlled integrated circuit tester and wafer prober

were used to determine the dc electrical parameters of selected test structures. Each test pattern on a wafer was probed and electrical results re- corded on a line printer and floppy disc. Statistical analysis and wafer

mapping of selected electrical parameters which formed a statistically significant data base were used to evaluate the process.

3. TEST PATTERN DESCRIPTION

3.1 Test Pattern NBS-16

NBS-16 is a square test pattern 250 mil (6.35 mm) on a side. It is divided

into seven basic areas as shown in figure 1. Each area can be physically

separated, if desired. The functions of each individual area are listed in

table 1. A computer-generated plot of NBS-16 is shown in figure 2.

NBS-16 was fabricated in a radiation-hardened, silicon gate CMOS/SOS process.

RCA uses a seven-level mask set for their radiation-hardened process. The

process [4] has nine photolithography steps* (two masks are used twice). In

the standard RCA process, the N-I mask is used for the n~ and p"*" implants

and the P-I mask used for the p~ and n"*" implants. A list of the topological design rules and tolerances employed in designing the test pattern can be

found in Appendix A. In this appendix as in this report, the terms polysilicon and poly are used interchangeably as are episilicon, epi, epi island, and

island.

For optimiam flexibility, the test pattern mask set contains nine levels as listed in table 2. This allows for into n~ and p"*" into p~ implants.

It does not require any additional lithography processing and is fully

*During the program, the n~ photolithography step and accompanying n' implant were dropped, reducing the number of steps to eight.

2
II.

Physical

Analysis

Pattern

(NBS)

VI.

Oxide Breakdown Pattern, p~ Substrate

(JPL)

VII

.

Oxide

Breakdown

Pattern,

n~

Substrate

(JPL)

III.

Random Access

Fault Structure,

RFI

(NBS)

I.

Process Parameter

Pattern

(NBS)

IV.

Gate Dielectric

Integrity Array,

RFII

(NBS)

V.

Process Parameter

Pattern

(JPL)

Figure 1. Test pattern NBS-16 functional layout.

3
Table 1. Device Types on NBS-16.

Area Types of Devices

I. Process Parameter

Pattern (NBS)

II. Physical Analysis

Pattern (NBS)

III. Random Access Fault

Structure, RFI (NBS)

IV. Gate Dielectric

Integrity Array, RFII

(NBS)

V. Process Parameter

Pattern (JPL)

VI. Oxide Breakdown

Pattern (JPL)

VII. Oxide Breakdown

Pattern (JPL)

MOSFETs, cross-bridge sheet

resistors, contact resistors, capacitors, RCA Gate

Universal Array Cells

Level designators, alignment

marks , ion beam areas , sur- face profilometer, etch

structure

p- and n-channel MOSFETs

Capacitors

MOSFETs, capacitors, resistors

Capacitor array, p~ substrate

Capacitor array, n~ substrate

4
Figure 2. Computer-generated plot of test pattern NBS-16.
Table 2. Photomask Levels.

Process Function Mask

Step Designator

1. Island Definition ISD

2. n~ implant N-I

3. p~ Implant P-I

4. Poly Definition PLY

5. Implant N+

6. p"*" Implant P+

7. Contact CNT

8. Metal Definition MET

9. Passivation PRO

6
compatible with most commercial CMOS/SOS processes. The working photomasks

were fabricated by a computer-controlled optical pattern generator at RCA.

The PVW was fabricated on 3-in. (76.2-mm) diameter silicon-on-sapphire wafers. Ninety-five of the 97 sites available on the PVW are used for NBS-16

test patterns. A detailed description of the test structures included on NBS-16, as well as the function, location, test method, and layout, is provided in Appendix B. A pattern designed by the manufacturer is located in

the two remaining sites. This pattern includes a ring oscillator circuit and

MOSFETs with varying gate lengths.

One PVW accompanied each product lot during fabrication. Upon completion,

the wafer was tested in order to determine the value of critical electrical

process parameters. These parameters were then statistically analyzed to

identify correlations between selected parameters and the performance of the

process lot. A total of 18 NBS-16 PVWs have been manufactured from 17 different process lots. In one instance, two PVW wafers accompanied the same product lot.

3.2 Test Pattern NBS-26

NBS-26 is identical to test pattern NBS-16 except for modifications to the

process parameter pattern. A computer-generated plot of NBS-26 is shown in

figure 3. Two test structures (no. 27, internal cell from RCA Gate Universal

Array (GUA) , and no. 28, input/output cell with input protection from RCA

GUA) found on NBS-16 were omitted. In their location test structures con- sisting of p- and n-channel MOSFETs with 0.20-mil (5.08-ym) and 0.15-mil

(3.81-ym) gate lengths, metal step coverage structures, and developmental

MOSFET/cross-bridge sheet resistor test structures were added. These structures are also described in Appendix B. Eleven wafers containing NBS-26 test

patterns were fabricated and tested. All 1 1 wafers were fabricated in the same lot and were used as a check of the functionality of the photomask set.

At the time of this report, no NBS-26 test patterns had been fabricated as PVWs accompanying product wafer lots.

4. ELECTRICAL MEASUREMENTS AND ANALYSIS TECHNIQUES

4.1 Measurement System Description

The measurement system used to test the PVWs consists of a minicomputer and

associated electrical test equipment. A block diagram of the measurement

system is shown in figure 4. The minicomputer is configured with 352 kilobytes of memory, two 10 -megabyte disc drives, two floppy disc drives, a 9-track dual density magnetic tape drive, a system console, several CRT and

hard-copy terminals, a line printer, a digital plotter, and a multiuser operating system. The test equipment consists of an automatic wafer prober which

can be programmed in English or metric units; a current supply with l-yA

resolution and compliance voltage programmable up to 100 V; two voltage supplies with 1-mV resolution and 550-mA current capability; a digital voltmeter

with 1-yV resolution and operating modes which provide either high precision

or high speed readings; a digital picoammeter with 1-pA resolution; 16

single-pole, single-throw dry reed relays; and eight 20-channel scanners, all

digitally programmable and operating under computer control.

7
8
EIGHT

20-CHANNEL

SCANNERS

20

Control

8

PATCH

PANEL

I WAFER

CHUCK

WAFER PROBER

12

2

32

10

-1^

3

TWO

VOLTAGE

SUPPLIES

TWO

D/A

CONVERTERS

CURRENT

SUPPLY

SIXTEEN

SPST

RELAYS

TWO

OP AMPS

SIX CHANNEL

A/D CONVERTER

PICOAMMETER

DIGITAL

THERMOMETER

Figure 4. Block diagram of computer-controlled electrical test system.

9
The software to control these instruments consists of a set of assembly language subprograms/ one to control each instrument; several assembly language

subroutines for mathematical operations such as conversion from binary coded

decimal to floating point format, status checking, and error handling; and a driver within the operating system. To activate an instrument, the user

calls the appropriate subprogram from a FORTRAN program using a CALL statement. The instruments can also be controlled from programs written in BASIC.

An interactive mode is available wherein the operator can command all instruments from a terminal. This is useful in developing and debugging software

and in determining appropriate applied voltage or current levels for automated testing.

In a typical measurement, data are acquired from selected structures at each

test site on a wafer, and the test results are logged to the line printer and

recorded on a floppy disc. Testing time is determined by the data acquisition rate and the total number of sites tested. The data acquisition rate is

generally limited by the response time of the test instrument which is usually run in a high precision or filtered mode. Typical measurement times for

the digital voltmeter operating in the filtered mode are about one-half sec- ond per measurement; for the digital picoammeter, about eight seconds. When

measurement precision and accuracy are not critical, the measurement time can

be greatly reduced by operating instruments in an unfiltered mode.

4.2 Statistical Analysis Techniques

Once data are obtained, it is important to transfer this information into a form which can be readily interpreted by the user or manufacturer. Data

analysis programs were developed to allow for the rapid determination of statistically significant parameters and to characterize their spatial variation

over the wafer for further process analysis.

The program developed, called STAT2 , allows one to determine the maximum,

minimum, mean, and median values, the sample standard deviation (a), and the

percent standard deviation of each parameter. A 50-character histograph can be produced to permit the user to see how the data are distributed between

the minimum and maximum values. A value N can be selected such that all

points farther than N times the sample standard deviation from the mean can

be identified.

For this work, all parameters measured except for leakage current were as- sumed to have a Gaussian distribution. In order to separate and identify devices which had failed and remove them from the data set from which meaningful statistical analysis could be performed, it was necessary to specify an exclusion criterion. For this work a device parameter was considered not to

be representative of the baseline process if the parameter was outside a +3o

limit about the mean value for that parameter. On the average, for a population of 95 independent samples, the expected number of points that would fall

outside this limit is between 0 and 1. This limit was considered a reasonable basis for identifying and separating data from the original population.

When such data were present, the data were excluded from the population and

the mean recomputed. This process was repeated until no points outside a +3a

bound were found.

10
This data base was then used to produce an eight-level gray- scale wafer map

as shown in figure 5. For this figure, each "x" represents the location of a measured structure. Averaging techniques were used to determine the shading

for sites excluded from the data population or locations not measured. The

magnitude of each of eight levels is determined initially by simple division

of the parameter range between maximum and minimxjm values. In order to produce wafer maps which represent parameter variations over a predetermined

range of interest, the upper bound of the highest level and the lower bound

of the lowest level can be varied by the operator. When the bounds are varied, a "+" is used to denote the location of a structure with a parameter

magnitude greater than the highest level of the upper bound, and a

"-" is

used to denote the location of a structure with a parameter magnitude below

the lower bound of the lowest level.

5. EVALUATION

5.1 Process Parameter Pattern

In order to control a developmental integrated circuit process, a process

engineer must:

(a) identify which parameters accurately predict or determine the degree

of process control;

(b) establish the value and range, etc. , of these parameters for a given

process lot; and

(c) determine how these values vary across an integrated circuit die, across a wafer, from wafer to wafer, and from lot to lot.

Test results must be obtained and interpreted in a timely fashion in order to

be used for correcting or improving the process. A PVW containing appropriate process parameter test structures can be used to obtain test results

which provide:

(a) a statistically significant estimate of the value and range of critical process parameters;

(b) the variation in these parameters as a function of wafer location;

and

(c) the lot-to-lot variation in critical parameters.

As will be shown later, the spatial variation of critical parameters can be

used to establish correlations between different parameters and allow identification and evaluation of wafer processing problems. In some instances the

spatial variation of certain parameters can be used to infer the variability

of parameters which cannot otherwise be determined by test structures or test

methods that are available.

For this work, the process parameter patterns on 18 NBS-16 PVWs (wafers A1

through A18) from 17 different lots were evaluated. Wafers A16 and A18 were processed in the same product lot. The process parameter patterns from one entire lot of 11 NBS-26 test patterns (wafers Bl through B11) were also

evaluated.

11
1

Threshold voltage,

l/ft It c nu.

-1.65

3

-1.60

2 -1.56

6

-1.51

'

10

-1.47

6

-1.42

13

-1.38

27

-1.33

23

-1.29

Sites included 90

Mean: -1 .40 V Median: -1 .37 V

Standard deviation 0.086 V

Figure 5. Typical computer-generated (eight-level) gray-scale wafer map

showing test site location and intrawafer parameter variation.

12
The process parameter pattern included on NBS-16 in Area I is a square approximately 100 mil (2.54 mm) on a side and contains 28 test structures laid

out in 2 by N probe-pad arrays [5] . The 2 by N probe pad array allows for

the use of one common probe card for wafer probing. It also allows great

ease and flexibility in test pattern design. For the process parameter pattern on NBS-16, N varies between 10 and 14 depending on the column. Testing

was performed using a 2 by 10 probe card. The pattern on NBS-26 is of similar size and probe-pad arrangement and contains 35 test structures. The process parameter pattern for NBS-16 is shown in Appendix B, figure B-3, and for

NBS-26 in Appendix B, figure B-4. A description of each test structure and

corresponding test method employed in this study can also be found in this

Appendix.

The test structures that were selected for inclusion in the process parameter pattern were those that were judged to provide the maximum number of useful process parameters within the available space on the test die and to minimize the testing constraints imposed by the automatic testing system. The

test structures listed in table 3 were those which were evaluated to determine the baseline electrical characteristics of the process. Additional developmental structures were also included on the patterns. Test results from

the process parameter pattern were obtained using the automatic wafer prober

and data analysis techniques previously described. The parameters measured,

described in Appendix B, were selected to provide information of sufficient

accuracy while minimizing the testing time and test equipment utilization.

5.1.1 Lot-to-Lot Contact Resistance Variation

The lot-to-lot variation in critical parameters can be used to monitor the

degree of process control. Plots of the lot-to-lot variation in the average

metal-to-n"^ contact resistance (Device no. 19) and the average metal-top"*" contact resistance (Device no. 18) are shown in figure 6. Data presented are from PVWs A1 through A18. Each point plotted represents the average resistance of approximately 95 test structure measurements on each PVW.

Since the contact resistor test structure [6] is a four-terminal Kelvin-type

structure with current taps separated from voltage taps, the effects of

probe-to-probe-pad contact resistance or the series resistance of the epi

layer or metal layers connecting the probe pads to the voltage taps do not

affect the measurement.

The test results indicate a wide range in the metal-to-n"*" contact resistance from lot to lot. Since little variation is observed in metal-to-p"*"

contact resistance and because both contact resistors are adjacent devices,

and the contact window is defined in the same photolithographic process for

both structures, variations or problems with contact window photolithography,

etching, and subsequent thermal processing are not suspected. The magnitude

of the variations in metal-to-n"*" contact resistance indicates problems as- sociated with other aspects of process control.

5.1.2 Intrawafer Contact Resistance Variation

Further information relating to the lot-to-lot contact resistance variation

can be obtained by looking at the intrawafer variation in these parameters

and establishing correlations with other process parameters. Wafer maps of

13
Table 3. List of Structures Evaluated on Process Parameter

Patterns.

Structure

No. Description

1. p-channel four five-terminal MOSFET

2. n-channel four five-terminal MOSFET

3. n-channel five-terminal MOSFET

4. p-channel five-terminal MOSFET

9. p"*" cross-bridge sheet resistor

10. n"^ cross-bridge sheet resistor

11. p"*" doped poly cross-bridge sheet resistor

12. w"*" doped poly cross-bridge sheet resistor

13. Metal cross-bridge sheet resistor

18. Metal to p"*" contact resistor

19. Metal to n"*" contact resistor

20. Metal to p"*" doped poly contact resistor

2 1. Metal to n"*" doped poly contact resistor

22. p-type MOS capacitor

23. n-type MOS capacitor

14
1

\—

1

\—ri—I—

600

250

200

^ 150

NBS-16

Average

Metal-to-n+

Contact Resistance

" 100

50

I I I

I I

J \ LJ L J_J L

</) E

C/3

6 8 10 12

RUN NUMBER

14 16

NBS-16

Average

Metal-to-p+

Contact Resistance

Figure 6. Average metal-to-n'*' contact resistance, Q, versus lot number and

average metal- to-p"^ contact resistance, Q, versus lot number. Data presented

show the variation in the electrical parameters over a time interval of approximately two years

.

15
metal-to-n''" contact resistance and n"*" sheet resistance for the PVWs ac- companying lots AlO and A9 are shown in figures 7 and 8, respectively. For

lot A10, both the mean and median values of metal-to-n"*" contact resistance

and of n"*" sheet resistance are approximately equal. The approximate corre- lation of the map pair in figure 7 suggests that the high metal-to-n"*" contact resistance is a function of sheet resistance or phosphorus concentration.

For lot A9, as shown in figure 8, there is a large difference between the

mean and median values for metal-to-n"^ contact resistance. Approximately

two-thirds of the metal-to-n"*" contact resistance structures measured had a resistance below 40.7 fi. The remaining structures with a resistance higher

than this value are grouped in the lower right portion of the PVW. The shading scale used both in this illustration and in figure 7 was determined by

dividing the range between the lowest and highest parameters obtained into

eight segments of equal magnitude.

The accompanying n'^ sheet resistance data have approximately equal mean and

median values suggesting a more symmetrical distribution of measured parameters. Here, the wafer map was produced by adjusting the minimum bound of the

parameter shading range so that approximately the same number of points would

be included for the first seven levels as for the first seven levels of the

metal-to-n"^ contact resistance map. Values of n"*" sheet resistance falling

below this bound are represented by the lightest gray tone. As can be seen

in figure 8, the highest metal-to-n"*" contact resistance occurs in the re- gions of highest sheet resistance.

The sheet resistance of the measured structures was controlled by a two-stage

phosphorus implant. The first implant was intended to dope the majority of

the epi island region. The second was intended to increase the dopant con- centration at the island surface in order to decrease contact resistance in source and drain regions. Both implants were made through a gate oxide which

covered the epi island.

Subsequent capacitance measurements on the p-type MOS capacitor (Device no. 21) on the PVW from lot A9 indicated that the gate oxide thickness was greatest in the areas of lowest phosphorus concentration.

Based on this wafer map correlation, it was concluded that due to variations

in the gate oxide thickness which were unaccounted for in the process design,

the peak of the phosphorus implant varied between the silicon and silicon dioxide depending upon the oxide thickness. This caused significant variations

in the amount of phosphorus reaching the silicon surface during the implant

and caused the observed variation in metal-to-n"*" contact resistance.

5.1.3 Lot-to-Lot p-Channel Threshold Voltage Variation

Wafer maps for one-parameter, p-channel threshold voltage of Device no. 1, for

all 18 PVWs produced, are reproduced in Appendix C. These results are illustrative of how a single parameter can vary across a wafer and from lot to

lot. The data presented are the p-channel threshold voltage of Device no. 1.

16
Resistance. Mean: 151.0 ohms

ohms No. Median: 147.0 ohms

314.4 Standard Deviation: 56.2 ohms

S ites included 87 'i ^ ? \

Resistance , ^ean: 93.6 ohms/sq.

ohms/sq. No. Median:95.2 ohms/sq.

1145 Standard deviation: 8.5 ohms/sq.

Figure 7. Wafer maps of metal-to-n"'" contact resistance (top) at 87 test sites

and n'^ sheet resistance (bottom) at 90 test sites for NBS-16 PVW AlO. In both

maps, the scale or gray- tone boundaries were selected such that the upper bound

of the darkest gray tone was the largest resistance value, and the lower bound

of the lightest gray tone was the smallest resistance value. The "x" symbols

on the maps represent the locations of nondefective test sites. Test results

from these sites were used to calculate mean, median, and standard deviation

and also to produce the wafer map.

17
Resistance,

ohms

290.7

112.1

.i-'^-,'^:--V'.'c.'o.-iC',-x-^c'»>^.'^

:;•;•?.^Vv:0£?>:o:<.:•>^:•:^^/^^^^^ ^r-^/:v\vc^/:/s>.^J.^>^^w^ 76,4

'" ^' 40^7'7'

Sites included

No.

5

3

2

2

6

7

7

59

91

Mean: 63.4 ohms

Median: 19.9 ohms

Standard deviation: 76.9 ohms

Resistance,

ohms/sq.

95.3

89.9

84.5

718

68.4

Sites included

No.

5

8

8

7

6

16

20

25

~95^

Mean: 83.7 ohms/sq.

Median: 79.6 ohms/sq.

Standard deviation: 12.2 ohms/sq.

Figure 8. Wafer maps of metal-to-n+ contact resistance (top) at 91 test sites

and n"*" sheet resistance (bottom) at 95 test sites for NBS-16 PVW A9

.

18
Two of these wafer maps of p-channel threshold voltage are shown in figure 9.

As can be seen, a general similarity in the two maps exists with higher valued parameters located in the upper right of the map and lower valued parameters located in the lower left. A majority of the 18 wafer maps in Appendix

C contain this general pattern. This suggests that usually the p-channel

threshold voltage is affected by processes in which the wafers are all similarly oriented with respect to the wafer flat.

There are two areas in the fabrication in which wafers are processed with the

wafer flat location remaining the same: photolithography and epitaxial

growth. In general, threshold voltage variation correlating with a lithography variation is not expected for MOSFETs of the size (0.3 mil, 8 ym) being

tested. Variations in linewidth of poly, epi, and metal can be found in the

appropriate wafer maps in Appendix D which contains a complete set of wafer

maps and statistical data. No correlation with threshold voltage was observed.

A simple expression for the threshold voltage of a p-channel silicon gate

MOSFET is [7,8] :*

Q Q

V = 4 + (f, - — - — . (1)

T ^ss C C ox ox where = effective work function of the silicon-oxide-silicon system,

(t)g = total band bending at the onset of strong inversion,

Qqj^ = total surface state charge located at the silicon-silicon

dioxide interface,

Qg = charge contribution of the substrate depletion region, and

Cqjj = the gate oxide capacitance.

In general, (})gg is a function of the gate electrode material, polysilicon.

The sum of both (Jjgg and is approximately constant for a given gate electrode technology. C^^^ for the most part varies with changes in the gate oxide thickness.

The main factors affecting the variation in Q^^ are substrate crystal

orientation, oxidation conditions, and subsequent thermal processing. Qg

is given by

Qg = (2c^ q [-*g])'^' ' (2)

where Eg = the permittivity of silicon,

Nq = the substrate dopant concentration, and

q = the electronic charge.

Thus, Qg varies mainly with changes in the substrate dopant concentration.

Dopant concentration for the n~ islands is determined in the epitaxial

growth process. No other epi island doping is intentionally performed. For

this process, the wafer flat location relative to the gas injector within the

* The cited references provide a more detailed description of the parameters

affecting the threshold voltage.

19
Threshold voltage, volts No. - 0.891

-0 867

-0.844

-0.820

Tit^S» 8 -0.773

WW^^^^^ 14 '"-0.750"

mmmmm 20

-0.726

27

-0.703

Sites included 83

Mean: -0.757 V Median: -0.7^7 V Standard deviation: 0.045 V

Threshold voltage, volts No.

-1.65

3 -1.60

2 -1.56

6 -1.51 10 ^-1.47 _ 6

-1.42

13 -1.38

27

-1.33

23

-1.29

Sites included 90

Mean : -1 .40 V

Median : -1 .37 V

Standard deviation: 0.086 V

Figure 9. Wafer maps of p-channel threshold voltage at 83 test sites for PVW

A16 (top) and PVW All (bottom)

.

20
epitaxial reactor is both the same for each wafer and the same from lot to

lot. A pancake type of vertical reactor was used with a rotating susceptor.

During the epitaxial growth process, if depletion of the dopant species were

to occur across the susceptor, a systematic variation in the epi island

dopant concentration across each wafer would occur.

Other factors which influence threshold voltage, such as Qqjj and Cqj^, are governed by gate oxide growth, anneal, sinter, and poly deposition, processes

which are performed with uncontrolled wafer flat orientation. If these processes were the major factors governing the variation in p-channel threshold

voltage, similar variations in the n-channel threshold voltage would also be

observed. Lot-to-lot variation in p-channel threshold voltage as a function

of variation in Qq^ or is not anticipated because of the uncontrolled wafer orientation during the processes which affect these parameters. This observation is further supported by the lack of any correlation between

p-channel and n-channel wafer maps for the same PVW. These test results suggest that the dominant source of variation in p-channel threshold voltage is

the variation in epi island dopant concentration. The observed variation is

consistent with the expected dopant variation introduced during epitaxial

growth

.

There are no test structures or test methods available from which the

n-island concentration can be directly determined. By determining the variation of threshold voltage across the wafer and from wafer to wafer, it was possible to identify processing techniques which affected the control and

variability of this critical quantity.

5.1.4 Intralot Parameter Variation

One 11-wafer lot of NBS-25 test patterns was produced in order to qualify the

functionality of the mask set for NBS-26. Test results from the process

parameter pattern indicated the presence of functional MOSFETs on three of

the 1 1 wafers produced. Analysis of electrical tests on the remaining wafers

indicated the absence of electrical contact between the device being tested

and the wafer prober. Further analysis indicated that the metal cross-bridge

sheet resistors (Device no. 13) on all 11 wafers were functioning properly

and providing expected test results. These results indicate that adequate

probe-to-probe-pad contact is being made and that the electrical problems

being encountered are associated with the contact windows between metal and

all other conductive layers. From visual inspection, it was determined that

the contact window lithography step had been performed. The presence of a contact window problem was confirmed by test results from one of the PWs

containing functional devices.

Figure 10 contains wafer maps of n-channel threshold voltage and ri^ sheet

resistance for PVW B4. The threshold voltage wafer map indicates that non- functional MOSFETs are clustered in the upper right portion of the map.

Voltages exceeding 12 V for this measurement indicate that the voltage limit

for the programmable current supply was reached due to an open circuit in the

structure under test. Similarly, the r& sheet resistance shows the location of nonfunctioning cross-bridge resistors. Test results from the cross- bridge sheet resistors in the upper right portion of the PVW show that a voltage limit had again been reached. (For the van der Pauw sheet resistance

21
Threshold voltage, volts No.

31

0

0

0

0

0

0

64

Sites included 95

X • W • X

X • M X.

Resistance,

ohms/sq.

26.0

20.2

14.4 wmmmmm

8.5

2.7

Voltage limit

Sites included

No.

43

9

0

0

0

0

0

41

93

Figure 10. Wafer maps showing location of nonfunctional n-channel MOSFETs

(top) and n'^ sheet resistor test structures (bottom) for NBS-25 PVW B4

.

22
measurement, a current is forced through two adjacent taps of the structure,

and voltage is measured at the two remaining taps. Sheet resistance is then

calculated from the voltage measured for a fixed current in the structure.

IThen electrical contact is not made to the structure, no voltage is measured

between the voltage taps, and the calculated sheet resistance is approximately zero.

)

Based on these data, it was possible for the manufacturer to isolate the source of the processing problem to that portion of the process between contact window lithography and metallization deposition. Further evaluation by

the manufacturer revealed that a change in a premetallization chemical cleaning procedure had occurred and that contamination was being introduced during

one of the wafer drying steps.

5.2 Random Fault Test Structure Evaluation

A random fault test structure is a microelectronic structure which can be

electrically tested in order to determine the density of certain types of

faults associated with the fabrication process [9] . These structures usually

consist of arrays of identical elements connected electrically in a series,

parallel, or addressable configuration. Two types of developmental random

fault test structures were included on NBS-16 and NBS-26.

The purpose of using a random fault test structure on a test pattern is to

provide the user and manufacturer with a tool which can be used to assess the

yield potential and identify the principal yield detractors associated with

the process being used. For the manufacturer, test results can be used to

identify, quantify, and correct yield-limiting processes in the fabrication

process. For the user, test results can be used to monitor the manufacturer's performance with time, rate the performance of multiple manufacturers,

or accept or reject products.

Several factors must be considered before selecting and using a random fault

test structure. Briefly, they are:

(a) What type of structure should be used? If the structure selected

does not provide information about principal fault mechanisms in the

process, test results and analysis will be of little use in improving yield.

(b) What size should the structure be? If a series or parallel type of

array is used and the array size is too large, all arrays will probably contain at least one fault. On the other hand, if the array

size is too small, a single array has a high probability of containing no faults. If a large number of small arrays is employed, testing time and probing difficulties increase. The array size for a single structure must be selected such that enough faults will be

detected that some form of statistical analysis can be performed.

(c) Is the fault detected the intended fault? If a structure were used

to detect dielectric faults in capacitor arrays and serious metallization bridging between interconnect lines from probe pads to the

23
capacitors occurred, a fault would be detected, but the identity of

the fault would be incorrect.

(d) Is the fault detected a singular fault or a clustered fault? If,

for instance, a continuity test is performed for a metallization interconnect and test results indicate a break, is the break at one location? Two? Ten?...

(e) What degree of testing complexity and time is required to obtain

meaningful information? If the time required to test and evaluate

the structure is too great to provide timely information to the fabricator, the structure will be of little value.

One of the two random fault structures included on NBS-16 and NBS-26 is a new type of developmental fault structure which can both provide information on a variety of faults common to MOSFET devices and in general determine the location of the faults. The other structure, an MOS capacitor array, is a more

conventional parallel array intended to determine the occurrence of gate dielectric failure at the epi island edge.

5.2.1 Random Access Fault Structure (RFI)

The purpose of including this type of structure on NBS-15 and NBS-26 was to

develop a general purpose random fault structure which can be used to detect,

identify, and evaluate faults common to MOSFET structures without foreknowledge of dominant fault type or fault density. The structure is a random ac- cess structure which allows one to identify different fault types and determine the exact location of the fault for further analysis. One can determine

if the fault is singular or clustered and also obtain parametric electrical

data which can be used in further analysis. In Area III, each NBS-16 test

pattern contains four of the random access fault structures, shown in figure

11. The top two are p-channel; the bottom two are n-channel. Each structure contains a 10 by 10 array of minimum geometry MOSFETs. There are 400

MOSFETs per pattern and thus a total of 38,000 MOSFETs on the 95 sites of

each PVW. Within each array, each MOSFET has the gate electrically tied to

drain. The devices are arranged in rows and columns similar to a diode matrix. Each MOSFET is isolated from its neighbor and can be individually addressed by selecting the appropriate row and column probe pads as shown in

figure 12. The vertical columns are made of metal, the rows of polysilicon.

Each MOSFET has a gate size of 0.2 by 0.6 mil (5.1 by 15.2 ym). Testing is

accomplished in two phases with the automatic computer-controlled test system. The first phase, a row-to-row and column-to-column integrity test, is

to establish whether there is electrical conductivity between adjacent rows

or columns. If the structure passes this test, each MOSFET is individually

tested to determine the threshold voltage measured at 1-yA source-to-drain

current, the source-to-drain breakdown voltage measured at 10-uA source-todrain current, and the source-to-drain leakage current measured with the gate

and drain grounded and source held at 10 V. These data and site location are recorded.

To evaluate the data, failure criteria must first be established. For this

work, two criteria were recommended by the manufacturer as limits which, if

exceeded, would result in circuit failure. They are:

24

I

I

Electrical Interconnect

Figure 12. One random access fault structure RFI, showing a micrograph of a two-by-two section of MOSFETs and a schematic of the electrical interconnect.

26

J.
(a) a source-to-drain leakage current greater than 50 nA/mil (2 nA/ym)

gate width and

(b) a source-to-drain breakdown voltage less than 17 V or greater than

30 V. (This upper limit was an arbitrary bound to enable one to

determine when the voltage compliance limit of the current supply

was reached.

A third criterion was also used. A MOSFET was considered to have failed if

the threshold voltage was above or below a preselected bound. This bound can

be determined from circuit simulation programs or past experience. Since no data were available from these sources on which more precise bounds could be

established, the following criterion was used:

(c) A MOSFET was considered to have failed if the threshold voltage was outside the four-sigma limit where sigma is the sample standard deviation of the data from test results of discrete MOSFETs tested in

the process parameter pattern. The threshold voltage data sample

was assumed to follow a Gaussian distribution, and data falling outside this distribution were considered to be failures. For a population of approximately 25,000 independent samples, only a single

valid datum was expected to fall outside this limit.

Figure 13 is a graphical presentation of the outcome of the test results of

one array. By analyzing the test results and comparing the outcome of individual sites to the nearest neighbors, the exact fault location and the category of fault type can be determined. Examples of this are shown in figure

13. Visual inspection was used to confirm the indicated break in metallization and the dielectric gate short. By testing a large number of these

arrays, a variety of different electrical fault types can be identified.

These fault types can be separated into two basic groups: physical faults

and parametric faults.

Physical faults are those which produce a definite physical failure which

directly results in circuit failure. Examples are: poly, metal, or epi

voids or breaks; poly, metal, or epi bridges; contact window opens; gate

dielectric shorts; and poly or metal step coverage breaks. A parametric

fault or parametric variation outside a predetermined bound may or may not

produce a circuit failure. Examples of parametric failures are a high

source-to-drain leakage current or low source-to-drain breakdown voltage.

Failures caused by either physical or parametric faults may or not be visible.

Test results from the random access fault structure on PVWs accompanying

product lots A6 and A1 are shown in figures 14 and 15, respectively. For

these two lots, the product being manufactured consisted of a circuit con- taining about 5,000 transistors. PVW A5 accompanied a product lot which had

a wafer probe yield nine times greater than the product lot accompanying PVW

A1. Test results from test patterns on the interior 67 sites within the PVW

are presented.

The detection of fault location is important because it provides information

about how the faults are distributed over the area being tested. For a given

number of faults, a nonuniform fault distribution generally results in a

27
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30
higher potential product yield as all of the faults tend to be located in a relatively few product sites. A more uniform fault distribution generally

results in more product sites containing a fault and therefore a lower product yield. A more detailed description of the effects of fault distribution

on product yield can be found elsewhere [10].

A fault is clustered when two or more adjacent transistor failures of the

same or similar type are detected within an array. When this occurs, the en- tire cluster is counted as one clustered fault. As may be seen in figure 14,

information on both clustered and nonclustered faults for PVW A6 is presented; however, few failures of either category were detected. Data for

both p- and n -channel MOSFETs are plotted together. Based on these test results, it was possible to eliminate certain failure mechanisms as the principal cause of yield degradation. For example, no gate-to-source shorts were

detected. Also, metallization coverage can be considered good. To test

26,800 MOSFETs required that 107,200 metallization steps be covered. Further

testing at higher current levels confirmed the electrical quality of the step

coverage.

Test results from PVW A1 indicate the presence of a major yield-limiting

fault type. The dominant fault detected is a nonclustered, parametric type

fault. Eighty-seven out of 26,700 MOSFETs evaluated had a source-to-drain

breakdown voltage or both a source-to-drain leakage current and breakdown

voltage which fell outside one or more of the previously described failure

criteria. Since the number of faults detected was approximately the same for

both p- and n-channel MOSFETs, test results for both types are plotted together.

A histogram of breakdown voltage for all devices with a source-to-drain leakage current greater than the failure criterion is shown in figure 16. The

distribution is peaked at about 14 to 15 V. In most cases, leakage current

was much greater than the 50 nA/mil (2 nA/ym) of gate width failure criterion.

Because the location of each fault was known, selected MOSFETs were inspected; however, no visible defects were observed. When individually . tested, the MOSFETs exhibited noisy soft breakdown characteristics. Figure

17 is a wafer map showing the approximate location of the faults that were detected by this technique.

This type of failure seems to be run-dependent, since test results from PVW

A6 do not indicate a large number of these faults. At this time, further

physical analysis is required to determine the exact nature and physical

cause of this defect.

To summarize, by using a random access fault structure, it was possible to

identify a yield-limiting fault which was unknown to the manufacturer and

user at the time of test structure design and selection. The location of

each fault could easily be determined from the test results. The dominant

fault encountered had electrical characteristics with lower-than-normal

source-to-drain breakdown voltage, with a mean of approximately 14 V, a source-to-drain leakage current greater than 50 nA/mil (2 nAAini) of gate

31
20

0 10 20 30

BREAKDOWN VOLTAGE, Vb , volts

Figure 16. Histogram of breakdown voltage, Vg, volts,

with devices with a source-to-drain leakage current

greater than 50 nA/mil (2 nA/ym) gate length for NBS-15

PVW Al.

32
ARRAY CONTAINING ONE

MOSFET WITH PARAMETERS

h > 50.0 nA/mil • Vb < 13.0 V

• 13.0V < Vb < 17.0V

Drop in site

Figure 17. Failure map showing approximate location of RFI structures con- taining MOSFETs with high source-to-drain current leakage.

33
width, and was not clustered. Also, no visible defects were observed at each

fault location.

The random access fault structure is important for two reasons. First, it

has been demonstrated that test results can be used to identify the exact

location of each fault. Further electrical or physical analysis can then be

undertaken. Second, the random access fault structure is able to identify

different fault types. In one example, a major fault was detected that had

not been previously anticipated; this fault would not have been detected from

the other test structures included on the pattern. The random access fault

structure was able to provide test results that allowed the determination of

the relative fault density and relative ranking of different fault types.

The user and manufacturer can use this structure as a tool to identify the

major yield-limiting process problems affecting their process.

5.2.2 Gate Dielectric Integrity Array (RFII)

The purpose of including this type of random fault test structure on NBS-15

and NBS-26 was to develop and evaluate a structure which could be used to

analyze one particular type of physical and electrical defect common to MOSFETs made in an SOS technology, namely, gate dielectric leakage from poly-toepi island occurring through the gate oxide at the epi-island edge. The

structure was designed such that metal-to-poly and metal-to-epi leakage could

also be detected.

The approach taken was to design a parallel array type of random fault test

structure consisting of subarrays of identical capacitor elements. Each subarray was then electrically tested and the results compared to a failure criterion. From these results, the yield (the ratio of the number of good subarrays to the total number of sdbarrays tested) could be determined for each

subarray size. Similar types of structures have been described by others

[9].

The gate dielectric integrity array, RFII, is shown in figure 18. The structure occupies Area IV of the test pattern. It contains capacitor arrays

which can be used to detect poly-to-epi leakage caused by dielectric defects

in the gate oxide. It can also be used to measure photolithography- induced

defects or dielectric defects in the field oxide by detecting leakage between

metal-to-poly and metal-to-epi levels. The structure is comprised of five

layers on a sapphire substrate: n~ epitaxial silicon; gate oxide; p"*" polysilicon; field oxide; and aluminum metallization. The poly lines are grouped

to form seven subarrays with 57, 114, 225, 375, 750, 1500, and 3000 crossovers. The polysilicon and metallization in each subarray are each connected

to a single probe pad; all of the epi lines in all of the subarrays are electrically common and connected to a single probe pad.

The size of the entire structure and the sizes of the subarrays were selected

as an arbitrary compromise between maximizing the niomber of elements (capacitors) from which a statistically significant data base can be obtained and

minimizing the overall size of the structure to one that could be reasonably

included within the test pattern. There are 95 RFII structures on each PW.

Each structure is in a 100-mil (2.54-mm) square and can be probed by means of

a 2 by 10 probe card.

34
Figure 18. Gate dielectric integrity array, RFII. The number of

elements for each subarray is listed at the right.

35
For each structure, a probe-to-probe-pad continuity is first made on the two common probe pads shown in figure 18. The use of only one set of common probe pads for determining electrical continuity places a limitation on the

overall usefulness of the test structure as designed. Double probe pads for

each subarray would ensure that electrical continuity is established and that

a test result indicating no current leakage is the result of the oxide integrity of the subarray being tested and not probe- to- probe- pad misalignment.

Use of double probe pads does increase the area required for the test structure and the time required for automatic testing.

For the present structure, however, if continuity is established at the two common probe pads, it is necessary to assume that probe-to-probe-pad continuity exists for the entire 2 by 10 probe-pad array. Each subarray is then individually tested by applying 10 V between the poly and epi contacts and mea- suring any detectable leakage current. Similar testing procedures are also

followed to determine leakage between metal-to-poly and metal-to-epi subarrays. Also, a series of tests is performed to determine the leakage between

the electrical nodes of the different subarrays. Data are recorded on a floppy disc for later evaluation.

The primary advantage of using this type of structure is that the time re- quired to test a large number of elements is very small since large parallel

arrays can be tested by one or two measurements. The structure is also useful in that it addresses primarily one type of fault.

The primary disadvantage of using this type of structure is in evaluating the

test results obtained and in determining meaningful statistical results. One reason for this is that the structure cannot identify the occurrence of more than one fault in a particular subarray. However, the two major sources of

difficulty are: (1) defining the magnitude of leakage current necessary to

consider the subarray to have failed and (2) separating electrical interferences between adjacent subarrays occurring from the presence of unintended

faults.

Test results from RFII structures on the PVW accompanying lot A6 are shown in

figure 19. The yield of the structure is plotted as a function of the number

of elements tested. Any array with a leakage greater than 1.0 yA was considered to have failed.

The bands accompanying the curve are the uncertainty of the measurement introduced by interferences caused by the test structure. An example of a typical interference is the occurrence of an unintended fault causing electrical communication between two adjacent subarrays. A typical example of

this type of unintended fault is a poly bridge or a metallization bridge

electrically linking two subarrays. When an unintended fault is detected for

a subarray pair and an intended fault is detected for that combination, an uncertainty arises as to which subarray contained the fault or if both subarrays contained a fault. The upper and lower bounds of the curves in figure

18 represent the highest yield and lowest yield, respectively, that can be

determined from test results where unintended faults are present.

Lowering the leakage current failure threshold criterion greatly increases

the uncertainty associated with evaluating the test results. As can be seen

36
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in figure 20, if the failure threshold is lowered to 10"'* yA, the uncertainty bands increase.

Test results from RFII do allow for some basis of yield evaluation. If the

yield versus number of elements, N, were extrapolated to an N of 5000 in

figure 19, the resultant yield predicted would be considerably greater than

the product yield measured. Given the accuracy of the test structure

measurements and accompanying uncertainty, this suggests that the principal

source of yield degradation is not breakdown of the dielectric layers which

separate the episilicon, polysilicon, and metallization.

In order to improve the accuracy of these results, the structure should be

redesigned with greater separation between subarrays. This would reduce the

possibility of metal or poly bridging between subarrays. Also, the structure

should be designed such that only one fault type can be detected. For instance, a structure intended to detect poly-to-epi faults should consist of

poly-over-gate-oxide-over-epi layers only. The absence of metal will remove

the possibility of electrical interferences by combined metal-to-epi and

metal-to-poly shorts. These steps will increase the area required for a structure and eliminate the possibility of detecting metal-to-poly and metalto-epi faults. Also, the use of double probe pads for the entire structure

will ensure that probe-to-probe-pad continuity is established for each subarray. To establish a more meaningful correlation between the test results

from RFII and product yield, a precise estimate of the poly-to-epi leakage

current required to cause circuit failure must be available. This estimate

must come from circuit modeling work.

Use of random fault test structures consisting of parallel or series arrays

of identical elements can be a valuable method of acquiring test results from

a statistically significant data base from which yield estimates can be made.

Testing time and equipment are minimal. Care must be taken in structure design and selection to ensure that:

(a) the occurrence of unintended faults is minimized or that they can readily be identified,

(b) well-defined failure criteria exist, and

(c) the fault being detected represents a dominant fault mechanism oc- curring in the process.

6. CONCLUSIONS

6.1 Process Parameter Pattern

In order to be able to characterize the performance of integrated circuits,

it is necessary to determine first the baseline electrical parameters of the

process. The data presented show that significant variations in these parameters can occur across a wafer and from wafer lot to wafer lot. In order to

obtain reasonable estimates of these parameters, it is insufficient merely to measure two or three test structures per wafer, as is often done, and expect

an accurate result. A large sample of test sites must be available in order

to make a statistically significant estimate of the desired parameter.

3,8
O) oo CO lO 9 CO

ro

-p•H

ft

iH

( m

om

'd

0) +j

CO

(U

4->

-p >

c

0) o

0) M -4-1

4-1 <; o ^

M JX! o

(%) ai3iA

c

!^

-P

fC

(D

tn

-pC

0)M

tn !-) H 13 Pm U

T3

39
As can be seen from the wafer maps presented, the mean, median, and standard

deviation are not necessarily sufficient information on which to fully evaluate electrical characteristics. For instance, the linewidth variation for

the p"*" cross-bridge sheet resistor for PVW A9 as seen in figure D-19 of Appendix D appears very uniform over the wafer and can be adequately characterized by statistical parameters. Conversely, examples previously given in

this report illustrate examples where intrawafer variations do occur and can be used for parameter correlation. In either case, sufficient data must be

taken and wafer maps produced in order to determine if the parameters are uniformly distributed over the wafer or a pattern exists. Graphical parameter mapping techniques provide an important tool for making correlations of

critical parameter variations and identifying process problems which cannot

be detected by other means. Much of the data and analyses presented identified process irregularities which were unknown to the manufacturer.

How many test sites are enough? This question cannot be directly answered,

but must involve the judgment of the user and manufacturer and the maturity

of the process being used. For a new developmental process, the identity,

spatial variation across a wafer, and the reproducibility of critical process

parameters must first be determined. A reasonable approach for determining

this is to run process lots of wafers containing only test patterns. As the

process matures and sufficient confidence exists, a PVW can be used in con- junction with test pattern "drop-ins," test patterns substituted for the

product at selected sites on a product wafer, to monitor critical parameters.

Finally, for a mature process in which all parameters are well controlled and

the product completely testable, the use of test patterns can be minimized as the product yield itself becomes the measure of process control. As chip

complexity increases and the possibility of complete functional testing of

VLSI circuits diminishes, test patterns may provide the only means of assess- ing process performance.

5.2 Random Fault Test Structures

Two types of random fault test structures were included on NBS-16 and NBS-26:

a random access fault structure (RFI) and a gate dielectric integrity array

(RFII).

Test results from RFI show that the identity and location of failure mechanisms can be detected by an addressable array and that a relative fault density of different failure mechanisms introduced during the fabrication process can be determined with this structure. This type of structure is important because it does not require the user or manufacturer to have foreknowledge of the major faults that may be encountered in a process. Further work

is necessary to increase the size of random access fault structures and to

minimize the testing time per element. The gate dielectric integrity array

is a random fault test structure which can be tested quickly; it provides information about one specific type of fault. The effects of interferences

caused by unintended faults can be reduced through improvements in the design

of the structure.

40
Acknowle dgment

The author would like to acknowledge the technical contributions made by

Michael A. Mitchell, Martin G. Buehler, and W. Murray Bullis; the assistance

in software development and computer-aided layout and wafer mapping techniques from Richard L. Mattis, Dwight A. Maxwell, and Ronald C. Frisch; the

wafer testing conducted by Melvin R. Doggett; the statistical analysis and

wafer mapping performed by Maha M. Osman; wafer processing by Joseph J.

Fabula, RCA; and manuscript preparation by E. Jane Walters.

References

1. Carver, G. P., Linholm, L. W. , and Russell, T. J., The Use of Microelectronic Test Structures to Characterize IC Materials, Processes, and Processing Equipment, Solid State Teahnology _23 (9), 85-92 (September

1980) .

2. Reynolds, F. N. , Lawson, R. W. , and Mellor, P. J. T. , Specifications for

Integrated Circuits in Telecommunications Equipment, Ppoc. IEEE 62 , 223-230 (February 1974).

3. Buehler, M. G. , and Sawyer, D. E. , Microelectronic Test Patterns Aid

Production of Custom iCs, Circuits Manufacturing V7_ (2), 46-56 (February

1977) .

4. Fabula, J. J., Kane, M. G. , and Woo, D. S., Manufacturing Technology for

Radiation-Hardened Microprocessor, Interim Technical Report No. 4

(12-1-78 to 3-1-79), Contract F 336 15-78-C-5135 , Air Force Materials

Laboratory.

5. Buehler, M. G. , Comprehensive Test Patterns with Modular Test Structures: The 2 by N Probe-Pad Array Approach, Solid State Technology _22

(10), 89-94 (October 1979).

6. Thurber, W. R. , and Buehler, M. G. , Semiconductor Measurement Technology: Microelectronic Test Pattern NBS-4, NBS Spec. Publ. 400-32 (April

1978) .

7. MOS Integrated Circuits^ W. M. Penney and L. Lau, Eds., pp. 55-59 (van

Nostrand Co., New York, 1972).

8. Physics and Technology of Semiconductor Devices, a. S. Grove, Ed., pp.

263-274 (John Wiley and Sons, Inc., New York, 1967).

9. Ipri, A. C. , and Sarace, J. C. , Integrated Circuit Process and Design

Rule Evaluation Techniques, RCA ReV. 38, 323-330 (1977).

10. Paz, 0., and Lawson, T. R. , Jr., Modification of Poisson Statistics:

Modeling Defects Induced by Diffusion, IEEE J. Solid-State Circuits

SC- 1 2 , 540-546 (1977).

41
Appendix A

NBS-16 AND NBS-26 TOPOLOGICAL DESIGN RULES

The following design rules were used for test structure layout. They are taken from Manufacturing Technology for Radiation-Hardened Microprocessor,

Interim Technical Report No. 4, by J. J. Fabula, M. G. Kane, and D. S. Woo,

and are reproduced with the permission of the Air Force Wright Aeronautical

Laboratory.

42
RADIATION HARDENED CMOS/SOS DESIGN RULES (F»+ POLYSILICON)

Mask Level

Mask

Designation

Street Symbol

Level 8: Epi Islands

NMOS Island

PMOS Island

Level 3: Polysilicon

Level 4: n"^ Diffusion

Level 4: a- Diffusion

(Reverse Tone of

Level 4)

Level 9: Diffusion

Level 5: Contact

Level 6: Metal

Level 7: Bond Pad

ILD

PLY

CNT

MET

PAD

No

No

No

No

Yes

No

Yes

V

L.,

r" 1

r

43
1. Minimum Values

a. Level 8: Epi Islands

Minimum

Value

Aim (mil)

Illustration

Value (Mm)

7 (0.28)

7 (0.28)

5 (0.2)

A ^ ^ ^

7 (0.28)

i(—

Rule

8.1

8.2

8.3

Item

Width of NMOS Island

Width of PMOS Island

Spacing,

>fMOS Island to NMOS Island or PMOS Island to PMOS Island

Spacing

NMOS Island to PMOS Island

44
b. Level 3: Polysilicon

Rule # Item

Minimum

Value

jum (mil)

Illustration

Value (pim)

3.1

3.2

3.3

3.4

3.5

Width of Polysilicon Gate

Width of Polysilicon Tunnel

for Interconnection

Spacing,

Polysilicon to Polysilicon

Spacing,

Polysilicon to NMOS Island

Spacing,

Polysilicon to PMOS Island

6 (0.24)

5 (0.20)

7 (0.28)

7 (0.28)

5 (0.2)

5 (0.2)

GATE

TUNNEL

0

H I45
Rule # Item

Minimum

Value

(im (mil)

Illustration

Value (jLtm)

3.6

3.7

Polysilicon Extension

Beyond NMOS Island

Polysilicon Extension

Beyond PMOS Island

5 (0.2)

5 (0.2)

ym

46
c. Level 4: n"*" Diffusion

Rule Item

Minimum

Value

Mm (mil)

Illustration

Value (Min)

4.1

4.2

Overlap,

n"*" Diffusion to NMOS Island

Spacing, n Diffusion to PMOS Island

4 (0.16)

4 (0.16)

r

I -J U1

T

I 1

47
Rule # Item

Minimum

Value

Mm (mil)

Illustration

Value (/im)

4.3

NOTE

Overlap of n"^ Diffusion

and Polysilicon is allowed

This does NOT exempt

the designer from following niles 3.6 and 3.7.

Minimum polysilicon

extension is 5iim(0.2 mil)

0

4 |. 1

1

/////,

1

1

• 1 OVERLAP

OVERLAP

48
d. Level 9: p"*" Diffiision

Rule Item

Minimum

Value

Aim (mil)

Illustration

Value (/im)

9.1

9.2

9.3

Overlap,

p"^ Diffusion to PMOS Island

Exception: To achieve

substrate strapping, a portion of the PMOS

island may be outside

the p* diffusion.

Spacing,

p"*" Diffusion to NMOS Island

Zener Diodes NOT

Allowed

4 (0.16)

4 (0.16)

r

-A

49
Rule #

9.4

NOTE

9.5

Item

Overlap of p"*" Diffusion

and Polysilicon is allowed

This does NOT exempt

the designer from following rules 3.6 and 3.7. Minimum polysilicon

extension is 5^01(0.2 mil)

Spacing of p"*" to n"*" Diffusion

(coincidence is allowed)

Minimum

Value

/um (mil)

Illustration

Value (Mm)

(a)

OVERLAP

1

J

(bl

OVERLAP

W///////////^

OVERl

(c

L

L.

50
e. Level 5: Contact

Rule #

5.1

5.2

5.3

5.4

5.5

Item

Active Contact Area

Contact Area in Level 5

Mask

Spacing,

Contact to Polysilicon Gate

All Contacts to Polysilicon shall be Outside of

n"*" Diffusion Mask.

Contact of Polysilicon over Active Transistor

is not allowed.

Minimum

Value

Mm (mil)

5x7

(0.2 X 0.28) or 6x6

(0.24 X 0.24)

5 X 10

(0.2 X 0.4) or 6x6

(0.24 X 0.24)

5 (0.2)

Illustration

Value (Mm)

10

I

I

r^-CHANNEi.

1

7PCHANNEL

1 ^

1 K 1

1

/////]

1

1

1

51
Rule # Item

Minimum

Value

nm (mil)

Illustration

Value (jum)

5.6 Spacing, Contact to Epi on Epi2 (0.08)

On All Sides

5.7 Spacing, Contact to

Poly on Poly

2 (0.08)

On All Sides

5.8 Overlap of Contact'

Over Epi Edge or Over Poly Edge onto

Sapphire

Not Allowed

52
t Level 6: Metal

Rule # Item

Minimum

Value

jum (mil)

Illustration

Value inm)

6.1

6.2

6.3.1

6.3.2.

NOTE

Width of Metal

Spacing,

Metal to Metal

Spacing,

Metal to NMOS Island

Spacing,

Metal to PMOS Island

Metal should not be

coincident with

any edge.

8 (0.32)

6 (0.24)

2 (0.08)

2 (0.08)

53
Rule # Item

Minimum

Value

Mm (mil)

Illustration

Value (^im)

6.4

6.4.1

6.5

6.6.1

6.6.2

Spacing, Metal to

n"*" Diffusion

Spacing, Metal to p+ Diffusion

Metal and Polysilicon

Edge Should not be

Coincident

Spacing,

Metal to Polysilicon

Gate (n-channel)

Spacing,

Metal to Polysilicon

Gate (p-channel)

0

Coincidence

Is Allowed

Coincidence

Is Allowed

2 (0.08)

2 (0.08)

L9

1

\

m

54
Rule # Item

Minimum

Value

Mm (mil)

nixutratioa

Value O^m)

6.7

NOTE

6.7.1

6.7.2

6.7.3

NOTE

Spacing,

Metal to Contact on

Poly Tunnel

Metal encompasses

contact completely.

Spacing,

Metal to Contact on PMOS Island

Spacing,

Metal to Contact on NMOS Island

p-channei Transistor

when 7.5 tim < W < 15

Metal encompasses

contact completely.

2 (0.08)

2 (0.08)

2 (0.08)

I

SOURCE

_L

wT

GATE

1

DRAIN

i

55
Rule # Item. Minimum

Value

Mm (mil)

Olusttation

Value (Mm)

6.7.4

NOTE

6.8

6.9

6.10

n-channei Device vrh&i

7.5 Mm < W < 15 Mm

0.3 mil < W < 0.6 mil

Metal encompasses

contact completely.

soonci I

Spacing,

Metal to Pad Metal

(Except Arc Gap)

Arc Gap between

Groimd Metal to Pad Metal is 12.5 Mm (0.5 mil)

Overlap,

Pad Metal to PMOS Island is 2 Mm (0.08 mil)

'—-mzMM

40 (1.6)

NOT TO SCALE

INDENT PAD MET. TO CLEARLY GROUND METAL oelinEATE

BONDING AREA

MASK LEVEL 7 (BOND PAD)

See Illustration on

Rule # 7.1

56
Rule ^ Item

Minimum

Value

Aim (mil)

Illustration

Value inm)

6.11 Pad Size 100 X 100

X 4.1/)

O.ll.l opaCing, raa to rau lUU (4.U)

fill 1 o.ll.l Spacing, Pad to Metal Line 4U (l.b)

6.12 Width of Scribe Line 120 (4.8)

6.12 Spacing, Scribe Line to Pad 40 (1.6)

Metal Pad and Scribe Line

SCR>af LINC 120 Amn (4.8 mil)

40 , (1.6)

*

IOOx-100

(4 X 4)

^ 100

(4)

40^(1.6)

V

1/

g. Level 7: Bond Pad

Rule ^ Item Illustration Value (nm)

7.1 Epi Overlap to Via Hole is 2.0 Mm (0.08 mil)

57
Appendix B

NBS-16 AND NBS-26 TEST STRUCTURE DESCRIPTION

Introduction

This appendix describes the structures designed by NBS and included on the

test patterns NBS-16 and NBS-26. NBS-16 is illustrated in figure B-1.

This appendix contains a number of figures produced on a computer-controlled

plotter. Figure B-2 is a key for identifying the individual levels. Many

structures require a change in only the level position of the implant mask to

form a new device (e.g., p-channel versus rz-channel MOSFET). Only one figure

has been included in this report for each basic structure. Similar structures, varying only in the level of the implant mask, are grouped in this

listing. The figures show, in each case, the levels associated with the

first structure of the group.

A description of the method used to measure the iVIOSFET electrical parameters

is found elsewhere [B-1].

I . Process Parameter Pattern

Purpose: The process parameter portion contains structures necessary to

evaluate baseline electrical parameters.

Description: The process parameter patterns on test patterns NBS-16 and

NBS-26 are laid out in 2 by N columns of probe pads. The pattern is a

^ square approximately 100 mil (2.54 mm) on a side. Six columns containing 28 structures are present. The pattern can be probed automatically

by a 2 by 10 probe card and computer tester. Structures 1 through 28

' appear on NBS-16. The process parameter pattern on test pattern NBS-26

is laid out similarly to NBS-16 and contains 35 structures. Test structures 1 through 26 and 38 through 46 appear on NBS-26.

Drawings: NBS-16, figure B-3; NBS-26, figure B-4. (The structure numbers appear in the upper left probe pad of each structure.

)

List of Structures

1. p-channel four-terminal MOSFET

2. n-channel four-terminal MOSFET

a. Description: This device is a conventional MOSFET with electrical contacts to gate, source, drain, and body. The gate dimensions are 2.5 by 0.3 mil (0.064 by 0.0076 mm).

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage current at 10.0 V, calculated conduction factor k', calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters.

c. Drawing: Figure B-5.

3. p-channel five-terminal MOSFET

58
59
Process

Sequence Function

Island Definition

N- Implant

P- Implant

Poly Definition

N+ Implant

P+ Implant

Contact

Metal Definition

Passivation

Figure B-2. Level identification key,

60
61
Figure B-4. Process parameter pattern, test pattern NBS-26.

62
Figure B-5. Four-terminal MOSFET.

63
4. n-channel five-terminal MOSFET

a. Description: This device is a five-terminal MOSFET with electrical contacts to gate, source, and drain, and two contacts to

the body. The device is much larger than Devices 1 and 2, but

it has approximately the same length-to-width ratio. The gate

dimensions are 9.0 by 1.0 mil (2.3 by 0.025 mm).

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage cur- rent at 10.0 V, calculated conduction factor k' , calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters.

c. Drawing: Figure B-6.

5. n-channel closed geometry MOSFET

6. p-channel closed geometry MOSFET

a. Description: This device is a four-terminal MOSFET with electrical connection to gate, source, drain, and body. It is a circular device with the source completely surrounded by the gate

channel and the gate channel surrounded by the drain. The gate

channel is "edgeless" ; it has a length of 0.3 mil (0.0076 mm).

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage cur- rent at 10.0 V, calculated conduction factor k' , calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters.

c. Drawing: Figure B-7.

7. p~ cross-bridge sheet resistor

8. n~ cross-bridge sheet resistor

9. p"*" cross-bridge sheet resistor

10. n"*" cross-bridge sheet resistor

11. p"^ doped poly cross-bridge sheet resistor

12. n"*" doped poly cross-bridge sheet resistor

13. Metal cross-bridge sheet resistor

a. Description: The cross-bridge sheet resistor is a combination

of a van der Pauw sheet resistor and a bridge resistor [B-2]

.

The design linewidth is 0.5 mil (0.015 mm).

b. Parameters measured: Sheet resistance and linewidth of the con- ducting layer.

c. Drawing: Figure B-8.

14. p~ gated cross-bridge sheet resistor

15. n~ gated cross-bridge sheet resistor

a. Description: The gated cross-bridge sheet resistor is similar

in geometry to Device no. 7 except that the resistor is junction

isolated in an epi island. The resistor is defined by a polysilicon gate which is a mask for a further heavy channel stop

implant. Electrical contact is made to the resistor (or channel

region) , the poly gate, and the channel stop.

b. Parameters measured: Sheet resistance and linewidth of the

channel region with the gate grounded.

c. Drawing: Figure B-9.

16. Metal to p~ contact resistor

17. Metal to n~ contact resistor

18. Metal to p"*" contact resistor

19. Metal to M"*" contact resistor

64
0^ I I I

1 O' ' ' 6.00

MIL

9.00

Figure B-6. Five-terminal MOSFET.

65
o

o• to.

MIL

Figure B-7. Closed geometry MOSFET.

66
Figure B-8. Cross-bridge sheet resistor.

67
68
20. Metal to p"*" doped poly contact resistor

21. Metal to n"*" doped poly contact resistor

a. Description: The contact resistor is used to measure the electrical resistance between the metal level and a resistive layer

[B-3] . The size of the contact opening is a square 0.4 mil

(0.010 mm) on a side. This is the same size contact opening

used on the cross-bridge sheet resistor.

b. Parameters measured: Contact resistance.

c. Drawing: Figure B-10.

23. n-type MOS capacitor

a. Description: This structure is a poly-oxide-epi capacitor with

an area of 10.24 mil^ (6.61 x 10"^ mm^) and with an electrical

guard ring.

b. Parameters measured: Capacitance per unit area and possibly

capacitance versus voltage characteristics.

c. Drawing: Figure B-11.

24. Closed geometry gated diode

a. Description: This device is similar to the closed geometry

MOSFET (Device no. 5) except that the gate is extended beyond

the drain region and off the epi island. The electrical connec- tion to the drain has been removed, leaving electrical connec- tion to the source, body, and gate.

b. Parameters measured: Leakage current caused by bulk and surface

carrier generation.

c. Drawing: Figure B-12.

25. n-channel two-terminal MOSFET

26. p-channel two-terminal MOSFET

a. Description: This structure is a two-terminal MOSFET with the

gate permanently connected to the drain. It is used as the internal cell in the Random Fault Structure I MOSFET arrays. It

is included here to permit electrical access to a single cell.

b» Parameters measured: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, and source-to-drain leakage

current at 10.0 V.

c. Drawing: Figure B-13.

27. Internal cell from RCA Gate Universal Array (QUA)

a. Description: This is an internal cell from the RCA GUA family

and has been included to provide electrical access to an individual structure used frequently in the RCA GUAs. The cell consists of two p-channel and two n-channel MOSFETs [B-4]

.

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage current at 10.0 V, calculated conduction factor k', calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters.

c. Drawing: Figure B-14.

28. Input/Output cell with input protection from RCA GUA

a. Description: This is an input/output cell consisting of a p-channel and n-channel MOSFET, two diodes, and a resistor

[B-4] . The diodes and resistor are arranged so they can be

included in input structures or omitted in output structures.

The device on NBS-16 has no components internally connected.

Each device is connected to a probe pad for electrical access.

69
o

o

O

• (SIMIL

Figure B-10. Contact resistor.

70
71

to.

o

o

csi_

o

1°

o

o

O

o

o

on

101

o.do' ' ' 'a'.do'

MIL

Figure B-13. Two-terminal MOSFET.

73
o

o

o

o

CMO

o

o• co'

o

o

CO

o

o

—1-| r-y

< !

LI

2

I

I

IAMIL

Figure B-14. Internal cell from RCA Gate Universal Array

74
b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage cur- rent at 10.0 V, calculated conduction factor k', calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters, pn junction characteristics.

c. Drawing: Figure B-15.

38. p-channel four-terminal MOSFET

39. n-channel four-terminal MOSFET

a. Description: This device is a conventional MOSFET with electrical contacts to gate, source, drain, and body. The gate dimensions are 2.5 by 0.2 mil (0.064 by 0.0051 mm).

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage cur- rent at 10.0 V, calculated conduction factor k', calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters.

c. Drawing: Figure B-5.

40. p-channel four-terminal MOSFET

41. n-channel four-terminal MOSFET

a. Description: This device is a conventional MOSFET with electrical contacts to gate, source, drain, and body. The gate dimensions are 2.5 by 0.15 mil (0.064 by 0.0038 mm).

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage cur- rent at 10.0 V, calculated conduction factor k' , calculated

threshold voltage, and the standard error of estimate of the two

calculated parameters.

c. Drawing: Figure B-5.

42. Metal-over-island step coverage structure

a. Description: This structure is a two-terminal resistor designed

to evaluate metal-over-island electrical continuity. The structur-e consists of a 0.3-mil (0.0076-mm) serpentine metallization

line crossing a parallel array of 0.3-mil (0.0076-mm) epi islands at 488 steps.

b. Parameters determined: Electrical continuity and resistance.

c. Drawing: Figure B-15.

43. Metal-over-poly step coverage structure

a. Description: This structure is a two-terminal resistor design

to evaluate metal-over-poly electrical continuity. The structure consists of a 0.3-mil (0.0076-min) serpentine metallization

line crossing a parallel array of 0.3-mil (0.0076-mm) poly lines

at 488 steps.

b. Parameters determined: Electrical continuity and resistance.

c. Drawing: Figure B-17.

44. Metal-over-poly on island step coverage structure

a. Description: This structure is a two-terminal resistor designed

to evaluate the electrical continuity of metal-over-poly when

the poly is over an epi island. The structure consists of a 0.3-mil (0.0076-mm) serpentine metallization line crossing a parallel array of 0.3-mil (0.0076-mm) poly lines at 488 steps.

b. Parameters determined: Electrical continuity and resistance.

c. Drawing: Figure B-18.

45. p -channel MOSFET cross-bridge sheet resistor

75
76
o

o

,} r-1

— —-'i I —1 I 1 K.

IZl I I I—

.-J !

'1 1 ~T

•T I—

I

t I J—»-

I I

-I-4-

-»—•- -I—I- l-l4-f

4 .0( 6.00

MIL

8.00 10.00 12.00

Figure B-16. Metal-over-island step coverage structure.

77
o

o

T r—-T

'ifjy/MfAY^AjYj

\y^AfJYjYjyjfJ^jyjYjV^jyjyAfA^AjK^^^

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I > I I I

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III

111

!

I I

i t

I I

I t

j I 1 I

I I

I I

6.00 10 T2.OO

MIL

8.00 00

Figure B-17 . Metal-over-poly step coverage structure.

78
Q

O

I

!

I I -I rI

! I ! I

I I

t « !

I I I T I •

I I ! I I

Tl i

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j

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j I \

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{

I I

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! • I

! I

! • I

I i

I

! < I

—1 k.

t I I

r——

! I

f

I

III

II

iI

Ic

I

II

. . . •

I ' ! i I

I

I

i i • i L

I

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I

I

I I

t I j

i j

J } j

{ j

• IT' I

t I I j

;

\ » Y \ \\\\ !

I ! L L I I j j j

V -i L J L

! I I * ! ! i

i ; J

\ \ \

I i I

1 i

I

t

I

! I

I I

1 I

I I

! I

L J I

0 .0(

7 2 .0( Voi 6 .00

MIL

8,00 10 ,00

T i

! i if

V

t

T2 .00

Figure B-18. Metal-over-poly on island step coverage structure.

79
46. n-channel MOSFET cross-bridge sheet resistor

a. Description: This is a developmental test structure which consists of a three-terminal MOSFET with a polysilicon cross-bridge

sheet resistor as the gate electrode. The structure may be useful in determining correlations between MOSFET electrical parameter variations and changes in the linewidth and sheet resistance of the gate.

b. Parameters determined: Threshold voltage at 1.0 yA, source-todrain breakdown voltage at 10.0 yA, source-to-drain leakage cur- rent at 10.0 V, calculated conduction factor k', calculated

threshold voltage, the standard error of estimate of the two

calculated parameters, and sheet resistance and linewidth of the

gate electrode.

c. Drawing: Figure B-19.

II. Physical Analysis Pattern

Purpose: The physical analysis portion of NBS-16 contains structures

which are intended for physical, visual, or beam analysis. No electrical testing is performed with these structures.

Description: The physical analysis pattern is a square approximately 50

mil (1.27 mm) on a side located in the upper left corner of NBS-16.

Mask alignment marks and level designators are also included in this

pattern.

Drawing: Figure B-20. (The structure number appears to the left of

each structure.

)

List of Test Structures

29. Light-field RCA alignment marks (fig. B-21)

30. Dark-field RCA alignment marks (fig. B-22)

31. Mark level designators and critical dimension structures

a. Description: This structure contains mask level designators and

critical dimension structures on each level. The critical

dimension structure consists of a pair of minimum width 2.0-mil

(0.051-mm) long parallel lines separated by the width of one

line.

b. Parameters measured: Linewidth of critical dimensions on the

working photomasks.

c. Drawing: Figure B-23.

32. Overetch structure

a. Description: This structure contains checkerboard elements

which can be inspected visually to determine overetching or underetching for epi definition, poly-over-epi definition,

metal-over-epi definition, contact- window- over- epi definition,

and contact-window-over-poly definition.

b. Parameters measured: The degree of overetching or underetching

of critical levels.

c. Drawing: Figure B-24.

33. p~ SIMS area

34. n~ SIMS area

80
o

o

MIL

Figure B-19. MOSFET cross-bridge sheet resistor.

81
31 o«* 1 EMT 1 mmr\

36 MBE-^

37TE§°a: era

nrc

32

Si

35

Figure B-20. NBS-16 physical analysis pattern.

82
o

o• in.

o

o

CSl.

o

1°

o

o

o

o

co'

o

o

1

6.00

MIL

Figure B-21. Light-field RCA alignment marks

83
o

o

U3.

O

O

(NJ_

O

o

o

o

o

o

o

r

ILJl 1^ 'J

%

O.Jo ' ' 'a'.do' ' ' 6.00

MIL

Figure B-22. Dark-field RCA alignment marks.

84
o

o

lO.

o

o

CM.

o

o

o

to"

o

o

en'

o

o

I 1'- I I

I

I I'-l 1

I 1 1

LY ZZ222Z

EZZZZZ

L] \

I lIJ I ,J"_ :r--^'-Lr'

T

Li u Li L_~ 1 Li

TT 1

' ' 6.00

MIL

Figure B-23. Mask level designators and critical dimension structures.

85
86
a. Description: This structure is a square 10.0 mil (0.0254 mm) on

a side which can be analyzed by secondary ion mass spectroscopy.

b. Parameters measured: Impurity atom concentration.

c. Drawing: Figure B-25.

35. Surface profilometer

a. Description: This structure is a series of parallel 4.0-mil

(0.10-mm) long stripes of metal, oxide, epi, and poly and is

intended for use with a surface-profile-type instrument.

b. Parameters measured: The step height of epi, poly, metal, and

contact window on sapphire and the step height of poly, contact

window, and metal on epi.

c. Drawing: Figure B-25.

III. Random Access Fault Structure (RFI) - NHS- 16 and NBS-26

Purpose: The purpose of this structure is to test the feasibility of

using a logic type array to determine the random fault density of a MOSFET array and determine the location and nature of any faults detected. The spatial integrity of important parameters will also be determined.

Description: This structure consists of two 10 by 10 arrays of

p-channel MOSFETs and two 10 by 10 arrays of n-channel MOSFETs. The

arrays are within a 100-mil (2.54-mm) square. The devices are interconnected such that the drains and gates are common. They are ar- ranged in rows and columns similar to a diode matrix with source connections to columns and the gate and drain connections to rows. Each device is electrically isolated from its neighbor and can be individually

tested by addressing the appropriate row and column probe pads.

Parameters Measured: For each MOSFET in the array, threshold voltage at

1.0 pA, source-to-drain breakdown voltage at 10.0 yA, source-to-drain

leakage current at 10.0 V, and fault location (e.g., the location of a MOSFET not having reasonable electrical parameters). Based on the na- ture of detected faults (shorts or opens) and location, information re- garding the quality of the metal step coverage, metal bridging, and

other shorts or opens in the metal level can be determined.

Drawing: Figure B-27.

IV. Gate Dielectric Integrity Array ( RFII ) - NBS-16 and NBS-26

Purpose: The purpose of this structure is to determine the fault density of gate oxide dielectric breakdown primarily at the epi island

edge.

Description: This structure contains an array of capacitors and is used

to detect metal-to-poly, poly-to-epi, and metal-to-epi leakage caused by

photolithography-induced defects or dielectric breakdown of the gate or field oxide. The structure is comprised of five layers on a sapphire

substrate: n~ epitaxial silicon lines 0.4 mil (6 ym) wide; oxide p"*" polysilicon lines 0.4 mil (6 ym) wide running perpendicular to the epi

87
88
C J

00-8

1IW

00-0

89

91
lines; field oxide; and aluminum metallization. The poly lines are grouped to form seven subarrays with 57, 114, 225, 375, 750, 1500, and

3000 crossovers. The polysilicon and metallization in each subarray are each connected to a single probe pad; all of the epi lines in all of the

subarrays are electrically common and connected to a single probe pad.

The array is in a 100-mil (2.54-min) square and can be probed by a 2 by

10 probe card.

Parameters measured: Metal-to-poly, poly-to-epi, and metal-to-epi leakage

current as a function of array size.

Drawing: Figure B-28.

References

B-1. MOS Integrated Civauits, W. M. Penney and L. Lau, Eds., pp. 126-129

(van Nostrand Co., New York, 1972).

B-2. Buehler, M. G. , Grant, S. D. , and Thurber, W. R. , Bridge and van der

Pauw Sheet Resistors for Characterizing the Line Width of Conducting

Layers, J, Eleotvoohem. Soe. 125 , 650-654 (1978).

R-3. Buehler, M. G. , Semiaonduotov Measurement Technology: Microelectronic

Test Pattern NBS-3 for Evaluating the Resistivity-Dopant Density Relationship of Silicon, NBS Spec. Publ. 400-22 (June 1976).

B-4. Skorup, G. E. , SOS COS/MOS Universal Array User's Manual, Solid State

Technology Center, Somerville, New Jersey (May 1977).

92
Appendix C

VARIATION IN p-CHANNEL THRESHOLD VOLTAGE FOR EIGHTEEN NBS-16

PROCESS VALIDATION WAFERS

Wafer maps of p-channel threshold voltage for Device no. 1 from PVWs accom- panying wafer lots A1 through A18 follow. The data are presented in order

show how one intrawafer parameter variation changes from lot to lot. The

time interval for processing the 18 lots was about two years.

For each figure, an "x" represents the location of a measured structure hav

ing a parameter value within the eight-level gray scale used. A "+" represents the location of measured sites with parameters higher than the scale,

and a "-" represents locations of measured sites lower than the scale.

f

93
Threshold voltage

Figure C-1. Wafer map of p-channel threshold voltage Device no. 1,

NBS-16 PW Al.

94
Threshold voltage

Figure C-2. Wafer map of p-channel threshold voltage. Device no. 1, NBS-16 PVW A2.

95
Threshold voltage

(V) No.

-1 210

-1 . 163

-1.116

~] .068

-1 021

MMm

.97^

mm

m

m

-0 .927

-0 .880

-0.833

Sites included

25

25

10

Mean: -0.998 V Median: -0.979 V Standard deviation 0.082

93

Figure C-3. Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PVW A3.

96
Threshold voltage

(V)

-1 . 109

-1 .076

No.

-1 .042

21

,009

-0.975

-0.9^2

mm

-0.908

,** J/ J/ i _.y _.v _.y _.y _.y y, -0.875

15

-0.842

Sites included 85

Mean: -0.967 V Median: -0.966 V Standard deviation; 0.048 V

Figure C-4. Wafer map of p-channel threshold voltage, Device no. 1,

NBS-16 PW A4 .

97
Threshold voLtage

No^ Mean: -1.136 V Median: -1.330 V Standard deviation: 0.152 V

Sites included 93

Figure C-5. Wafer map of p-channel threshold voltage, Device no. 1,

NBS-16 PW A5.

98
Threshold voltage

(V) No- Mean: -0.983 V Median: -0.969 V Standard deviation: 0.069 V

Sites included 90

Figure C-6 . Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PVW A6,

99
Threshold voLtage

Figure C-7. Wafer map of p-channel threshold voltage, Device no. 1, NBS-16 PW A7.

100
ThreshoLd voltage

(V) No.

-1 .014

1 -0 . 968

nsBBHBBBB8B 3

-0 . 922

7

-0 875

13

-0 829

12

783

20

-0 737

17

-6 690

18

-0 ekk

Mean: -0.770 V Median: -0.762 V Standard deviation: 0.081 V

7s7/..v.-.5a7.v5

Sites included 91

Figure C-8. Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PVW A8.

101
Threshold voltage

Figure C-9. Wafer map of p-channel threshold voltage, Device no. 1,

NBS-16 PW A9.

102
Threshold voltage

Figure C-10. Wafer map of p-channel threshold voltage, Device no. 1,

NBS-16 PVW AlO

.

103
Threshold voltage

<V> Mean: -1.400 V Median: -1.365 V Standard deviation: 0.086 V

Sites included 90

Figure C-11, Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PW All.

104
Threshold voltage

Figure C-12, Wafer map of p-channel threshold voltage, Device no. 1,

NBS-16 PW A12 ,

105
Threshold voltage

Sites included 93

Figure C-13. Wafer map of p-channel threshold voltage, Device no. 1, NBS-16 PW A13.

106
Threshold voltage

(V)

-1 . 176

'1.077

:^^.K:v^v:•^i^c>^>:>:•/•^«••^J

-1 .027

-0.977

-0.928

No.

21

22

25

Mean: -1 .047 V Median: -1.031 V Standard deviation; 0.095 V

: r ^ yT..:;<.'

• : ;:.-;:vKfe;::$<is^#

Sites included 94

Figure C-14. Wafer map of p-channel threshold voltage. Device no. NBS-16 PVW A14.
Threshold voltage

(V)

-1.139

-1 .085

No.

-1 .032

-0.978

-0.925

wmm

-0.872

-0.8!

8

V '/ ••/ '/ '/ ••.'.'/ •

• ' . •: .•

• 0.764

-0.71

Sites included

11

20

17

10

Mean: -0.932 V Median: -0.957 V Standard deviation: 0.100 V

94

Figure C-15. Wafer map of p-channel threshold voltage. Device no. '. NBX-16 PVW A15.

108
Threshold voltage

Sites included 82

Figure C-16. Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PVW A16.

109
Threshold voltage

Figure C-17 . Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PVW A17.

110
Threshold voltage

(V)

-1 .21 1

-1 . 145

-1 .079

- 0.685

Sites included

No.

10

18

16

20

87

Mean: -0.872 V Median: -0.838 V Standard deviation: 0.140 V

11

Figure C-18. Wafer map of p-channel threshold voltage. Device no. 1,

NBS-16 PVW A18.

Ill
Appendix D

CRITICAL ELECTRICAL PARAMETERS FROM ONE NBS-16 PROCESS VALIDATION WAFER

Wafer maps of critical electrical process parameters from the PVW accompanying wafer lot A9 follow. The data presented are from test structures found

in the process parameter pattern and are typical of data found on other PVWs.

The data are presented in order to show the type of information that can be

obtained from one PVW.

For each figure, an "x " represents the location of a measured structure having a parameter value within the eight-level gray scale used. A "+" represents the location of measured sites with parameters higher than the scale,

and a "-" represents locations of measured sites lower than the scale.

112
Threshold voltage

Median: -0.639 V Standard deviation: 0.118 V

Sites included 91

Figure D-1. Wafer map of p-channel threshold voltage. Device no. 1.

113
Breakdown voltage

Mean: 22.685 V Median: 22.705 V Standard deviation: 0.596 V

Sites included 85

Figure D-2. Wafer map of p-channel breakdown voltage. Device no. 1.

114 I
CaLcuLated Conduction

Factor

Sites included 91

Figure D-3. Wafer map of p-channel calculated conduction factor.

Device no . 1

.

115
CaLcuLated ThreshoLd

Voltage

(V)

0.679

0.624

0.569

0.514

0.459

0.404

0.349

0.294

0.239

Sites included

No.

11

16

11

14

17

Mean: 0.472 V Median: 0.468 V Standard deviation: 0.111 V

91

Figure D-4. Wafer map of p-channel calculated threshold voltage. Device no. 1.

116
Threshold Voltage

(V) No.

2.913

2.450

4

2.384

Sites included 89

Figure D--5. VJafer map

Mean: 2.610 V Median: 2.592 V Standard deviation: 0.117 V

of n-channel threshold voltage. Device no. 2.

117
Breakdown Voltage

(V) No- Mean: 19.957 V Median: 20.037 V Standard deviation: 0.437 V

Sites included

Figure D--6. VJafer map of ?7-channel breakdown voltage, Device no. 2.

118
CaLcuLated Conduction

Factor

Figure D-7. Wafer map of n-channel calculated conduction factor,

Device no. 2.

119
CaLcuLated Threshold

Voltage

Figure D-8. Wafer map of n-channel calculated threshold voltage, Device no, 2.

120
Threshold Voltage

(V) No. Mean: 2.685 V Median: 2.691 V

T, Standard deviation: 0.059 V

Figure D-9. Wafer map of n-channel threshold voltage. Device no. 3.

121
Breakdown Voltage

Mean: 16.685 V iXl No^ Median: 18.179 V Standard deviation: 3.379 V

21 .563

Sites included 94

Figure D-10. Wafer map of n-channel breakdov/n voltage. Device no. 3,

122
CaLcuLated Conduction

Factor

Sites included 91

Figure D-11. Wafer map of n-channel calculated conduction factor, Device no . 3 .

123
CaLcuLated Threshold

Voltage

Figure D-12, Wafer map of n-channel calculated threshold voltage, Device no. 3.

124
Threshold Voltage

(V) No. Mean: -0.735 V Median: -0.716 V

,-, Standard deviation: 0.137 V

Sites included 91

Figure D-13. VJafer map of p-channel threshold voltage. Device no. 4.

125
Breakdown Voltage

(V) No. Mean: 22.768 V

Sites included 79

Figure D~14. Wafer map of p-channel breakdov/n voltage. Device no. 4.

126
CaLcuLated Conduction

Factor

(k') No. Mean: 2.885 yA/V^

Median: 2.749 pA/V^

.945 Standard deviation: 0.408 pA/V^

Sites included 92

Figure D-15. Wafer map of p-channel calculated conduction factor, Device no, 4.

127
CaLcuLated Threshold

Voltage

(V) No. Mean: 0.561 V Median: 0.548 V 0.825 Standard deviation: 0.129 V

Sites included 91

Figure D-16 . Wafer map of p-channel calculated threshold voltage. Device no. 4.

128
Resistance

Sites included 95

Figure D-17. Wafer map of n"*" sheet resistance, Device no. 9.

129
Linewidth

Figure D-18. Wafer map of n+ cross-bridge sheet resistor linewidth,

Device no. 9.

130
Resi stance

(^/) No. Mean: 92.949 Q/D

Median: 90.896 Q/D

, , Standard deviation: 5.405

Sites included 92

Figure D-19. Wafer map of p"*" sheet resistance. Device no. 10.

131
Linewidth

^P""^ NOj^ Mean: 14.932 ym Median: 14.932 ym

15.931 Standard deviation: 0.381 \jn

Sites included 90

Figure D-20. Wafer map of p+ cross-bridge sheet resistor linewidth.

Device no. 10.

132
Resi stance

(^/) No. Mean: 109.50 ^/O

Median: 109.80

T t-n Standard deviation: 9.793 fi/O

Sites included 91

Figure D-21. Wafer map of p+ doped poly sheet resistance. Device no.

11.

133
Linewidth

Figure D-22. Wafer map of p doped poly cross-bridge sheet resistor

linewidth. Device no. 11.

134
Resistance

Sites included 93

Figure D-23. Wafer map of n+ doped poly sheet resistance. Device no.

12 .

135
Linewidth

(pm)

13.536

13.390

13.244

13.099

12.953

12.807

12.662

mmmmm

12.516

12.370

Sites included

No.

12

13

14

14

16

10

Mean: 13.028 um Median: 13.048 ym

Standard deviation: 0.293 ym

90

Figure D-24. Wafer map of n+ doped poly cross-bridge sheet resistor

linewidth, Device no. 12.

136
Resi stance

Median: 4936.7 Q. Standard deviation: 1458.9 S2

Sites included 95

Figure D-25. Wafer map of metal-to-p contact resistance, Device no.

16 .

137
Resi stance

80282.0

71197.0

No.

62113.0

53028.0

43943.0

34858.0

25774.0

16689.0

76044.0

Sites included

13

12

26

27

90

Mean: 28033.0 ^ Median: 21918.0 Q, Standard deviation: 17369.0 Q.

M

Figure D-26

17,

Wafer map of metal-to-n contact resistance, Device no

138
Resi stance

Median: 4.350 Q

Standard deviation: 1 .077 Q.

Sites included 91

Figure D-27. Wafer map of metal-to-p+ contact resistance, Device no.

18.

139
Resi stance

Figure D-28. Wafer map of metal-to-n"'" contact resistance. Device no.

19.

140
Resi stance

(n) No.

5.976

5.661

5.347

5.033

4.719

4.405

4.090

3.776

3.462

Sites included

10

18

12

16

18

13

91

Mean: 4.415 Q

Median: 4.388

Standard deviation: 0.570

• .V .V .V .V ..• .V /.v.vwV'-V-v>-'?'-S-'-*>-V-'"-'o

Figure D-29. Wafer map of metal-to-p+ doped poly contact resistance,

Device no . 20 .

141
Resi stance

No.

4.878

2 4.607

888S 4

4.335

7

4.064

3.793

13

17

3.522

3.250

15

2.979

'.'•^-'.j-'.jV 22

11 2.708

Sites incLuded 91

Figure D-30. Wafer

Device no. 21.

Mean: 3.524 9. Median: 3.498 Q

Standard deviation: 0.493 Q

map of metal-to-n+ doped poly contact resistance.

142
NBS-n4A REV. 2-8C) U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET (See instructions)

PUBLICATION OR

REPORT NO. NBS SP 400-66

2. Performing Organ. Report No, 3. Publication Date

August 1981

4. TITLE AND SUBTITLE

Sem-iconductor Measurement Teohnology : The Design, Testing, and Analysis of a Comprehensive Test Pattern for Measuring CMOS/SOS Process Performance and Control

5. AUTHOR(S)

Loren W. Linholm

6. PERFORMING ORGANIZATION (/f joint or other than NBS. see instructions)

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

7. Contract/Grant No, MIPR No. FY117580N3105

8. Type of Report & Period Covered Final

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS {Street, City, State, ZIP)

and

U.S. Air Force

Air Force Wright Aeronautical Laboratories

Wright Patterson AFB, OH 45433

Defense Nuclear Agency

Washington, DC 20305

10. SUPPLEMENTARY NOTES

Library of Congress Catalog Card Number: 81-600078

[ Document describes a computer program; SF-185, FIPS Software Summary, is attached.

11. ABSTRACT (A 200-word or less (actual summary of most significant information. If document includes a significant

bi bl iography or literature survey, mention it here) A Process Validation Wafer (PVW) is a wafer containing only test patterns. One PVW

accompanies a product let during the fabrication process. Test patterns NBS-16 and

NBS-26 are designed to be used on PVWs. They contain both process parameter test

structures and random fault test structures. Eighteen NBS-16 PVWs were fabricated in

a radiation-hardened silicon-gate CMOS/SOS process. These PVWs were tested on a high-speed computer-controlled dc test system. Test results from the process parameter

test structures were used to establish the baseline electrical parameters for each

product lot and to produce an eight-level gray scale wafer map for these parameters.

Based on correlations of selected wafer maps, it was possible to identify specific

yield-related process problems otherwise unknown to the manufacturer or user. Test results from two random fault test structures were used to establish a statistically significant data base for identifying and evaluating major yield-limiting

fault mechanisms in the process. Test results from a developmental random access fault

structure and a gate dielectric integrity array are presented. The results are analyzed for selected PVWs and a major yield-limiting fault mechanism detected. A description of the test pattern and test results, including a drawing of each test

structure, recommended test procedure, and design rules, are found in the appendices.

12. KEY WORDS (Six to twelve entries; alphabetical order; capitalize only proper names; and separate key words by semicolons)

integrated circuits; microelectronics; process validation wafer; random faults;

silicon-on-sapphire; test pattern; test structure; yield.

13. AVAILABILITY

Unlimited

[ [ For Official Distribution. Do Not Release to NTIS

fX3j Order From Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402.

I

^1 Order From National Technical Information Service (NTIS), Springfield, VA. 22161

14. NO. OF

PRINTED PAGES

148

15. Price

$5.50

USCOMM-DC 6043-P80 GOVERNMENT PRINTING OFFICE : 1981 0 - 350-781



NBS TECHNICAL PUBLICATIONS

PERIODICALS

JOURNAL OF RESEARCH—The Journal of Research of the National Bureau of Standards reports NBS research and develop- ment in those disciplines of the physical and engineering sciences in which the Bureau is active. These include physics, chemistry,

engineering, mathematics, and computer sciences. Papers cover a broad range of subjects, with major emphasis on measurement

methodology and the basic technology underlying standardization. Also included from time to time are survey articles on topics

closely related to the Bureau's technical and scientific programs. As a special service to subscribers each issue contains complete

citations to all recent Bureau publications in both NBS and non- NBS media. Issued six times a year. Annual subscription: domestic

SI 3; foreign SI 6.25. Single copy. S3 domestic; S3. 75 foreign. NOTE: The Journal was formerly published in two sections: Section A "Physics and Chemistry" and Section B "Mathematical

Sciences." DIMENSIONS/NBS—This monthly magazine is published to in- form scientists, engineers, business and industry leaders, teachers, students, and consumers of the latest advances in science and

technology, with primary emphasis on work at NBS. The magazine

highlights and reviews such issues as energy research, fire protection, building technology, metric conversion, pollution abatement,

health and safety, and consumer product performance. In addition, it reports the results of Bureau programs in measurement

standards and techniques, properties of matter and materials, engineering standards and services, instrumentation, and

automatic data processing. Annual subscription: domestic $11;

foreign $13.75. NONPERIODICALS

Monographs—Major contributions to the technical literature on

various subjects related to the Bureau's scientific and technical activities. Handbooks—Recommended codes of engineering and industrial practice (including safety codes) developed in cooperation with in- terested industries, professional organizations, and regulatory

bodies. Special Publications—Include proceedings of conferences sponsored by NBS, NBS annual reports, and other special publications

appropriate to this grouping such as wall charts, pocket cards, and

bibliographies. Applied Mathematics Series—Mathematical tables, manuals, and

studies of special interest to physicists, engineers, chemists,

biologists, mathematicians, computer programmers, and others engaged in scientific and technical work.

National Standard Reference Data Series—Provides quantitative data on the physical and chemical properties of materials, compiled from the world's literature and critically evaluated. Developed under a worldwide program coordinated by NBS under

the authority of the National Standard Data Act (Public Law

90-396).

NOTE: The principal publication outlet for the foregoing data is the Journal of Physical and Chemical Reference Data (JPCRD)

published quarterly for NBS by the American Chemical Society

(ACS) and the American Institute of Physics (AIP). Subscriptions,

reprints, and supplements available from ACS, 1 155 Sixteenth St., NW, Washington, DC 20056.

Building Science Series— Disseminates technical information developed at the Bureau on building materials, components,

systems, and whole structures. The series presents research results,

test methods, and performance criteria related to the structural and

environmental functions and the durability and safety characteristics of building elements and systems.

Technical Notes—Studies or reports which are complete in themselves but restrictive in their treatment of a subject. Analogous to monographs but not so comprehensive in scope or definitive in treatment of the subject area. Often serve as a vehicle for final reports of work performed at NBS under the sponsorship of other government agencies.

Voluntary Product Standards—Developed under procedures

published by the Department of Commerce in Part 10, Title 15, of

the Code of Federal Regulations. The standards establish nationally recognized requirements for products, and provide all concerned interests with a basis for common understanding of the

characteristics of the products. NBS administers this program as a supplement to the activities of the private sector standardizing

organizations. Consumer Information Series—Practical information, based on NBS research and experience, covering areas of interest to the con- sumer. Easily understandable language and illustrations provide

useful background knowledge for shopping in today's tech- nological marketplace. Order the above NBS publications from: Superintendent of Documents. Government Printing Office, Washington. DC 20402. Order the following NBS publications—FIPS and NBSIP's—from

the National Technical Information Services, Springfield, VA 22161.

Federal Information Processing Standards Publications (FIPS

PUB)—Publications in this series collectively constitute the Federal Information Processing Standards Register. The Register

serves as the official source of information in the Federal Govern- ment regarding standards issued by NBS pursuant to the Federal Properly and Administrative Services Act of 1949 as amended.

Public Law 89-306 (79 Stat. 1127), and as implemented by Executive Order 11717(38 FR 12315, dated May II, 1973) and Part 6 of Title 15 CFR (Code of Federal Regulations).

NBS Interagency Reports (NBSIR)—A special series of interim or

final reports on work performed by NBS for outside sponsors

(both government and non-government). In general, initial dis- tribution is handled by the sponsor; public distribution is by the National Technical Information Services, Springfield, VA 22161,

in paper copy or microfiche form.
U.S. DEPARTMENT OF COMMERCE

National Bureau of Standards

Washington. DC 20234

OFFICIAL BUSINESS

Penalty for Private Use, $300

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