# Patent

## Title
Pre-matched module for an ultra-high frequency diode with high heat

## Abstract

The Government has rights in this invention pursuant to Contract No. F33615-81-C-1527 awarded by the Department of the Air Force.

## Background
Common metalization schemes for silicon based integrated circuits comprise multilayer contact structures. Such structures typically include aluminum or aluminum/copper metalization layers serving as electrical conductors. The semiconductor devices in such circuits require protection against aluminum or aluminum/copper interdiffusion or spiking into the silicon substrate. Further, silicon based devices require protection against mobile ion contamination.

The present invention relates to providing protection against both the aluminum or aluminum/copper spiking and against mobile ion contamination. The present invention provides this protection while allowing normal processing to be done on multilayer metal structures.

Specifically the present invention comprises a bimetal layer located between two portions of an integrated circuit, the bimetal layer comprising a layer of TiWN and a layer of TiN.

Prior art disclosures separately address the nitriding of TiW or Ti as a barrier metal against spiking, and also separately address the possibility of using Ti as a barrier against mobile ion contamination. However, the reaction of Ti with Si has prohibited the use of Ti alone. The present invention uses TiN instead of Ti and adds TiWN to satisfy both requirements.

The FIGURE illustrates an integrated circuit comprising the present invention.

The FIGURE illustrates an integrated circuit comprising three metalization layers 12, 14, and 16. (For the purpose of the present application, metalization layers may comprise more than one layer of metal; thus, for example, each metalization layer 12, 14, and 16 may comprise a layer of aluminum or aluminum/copper as typically found in the prior art and may also comprise the bimetal layer of the present invention.)

Metalization layers such as 12, 14, and 16 may comprise contact pads or may comprise interconnects used to connect various portions of an integrated circuit including devices such as 18 located within a device substrate. A device substrate may comprise a layer of semiconductor material 21 such as silicon and a dielectric layer 22 such as silicon dioxide formed on a major surface 23 of the substrate. Devices such as 18 are typically formed in dielectric layer 22. A first layer of metalization such as 12 is typically formed over major surface 23.

In the case of devices comprising a layer 22 of SiO.sub.2, a thin layer 24 of Pd.sub.2 Si is typically formed between first metal layer 12 and device 18. This layer of Pd.sub.2 Si typically serves the purpose of enhancing the ohmic contact between the metalization layer and the device.

In accordance with the present invention, the aluminum or aluminum/copper portion 32, 34 and 36 of each metalization layer 12, 14 and 16 respectively is separated from the integrated circuit portion below it by the bimetal layer of the present invention, i.e. by a layer comprising a layer 29 of TiWN and a layer 28 of TiN. In the preferred embodiment of the present invention, layer 28 of TiN is relatively thin, e.g., in the range of 200 angstroms through approximately 500 angstroms, although any thickness desired may be used. The thickness of the TiWN layer 28 is typically on the order of 1,000 angstroms although any desired thickness may also be used for this layer. Further, in the preferred embodiment of the present invention, layer 28 of TiN is underneath layer 29 of TiWN.

As previously indicated, the bimetal layer of the present invention is located between two portions of an integrated circuit. For example, the present invention may be located between an aluminum or aluminum/copper layer such as 32 and a semiconductor device such as 18. As also previously indicated, the purpose of the present invention in such a location is to prevent spiking of the aluminum or aluminum/copper composition of portion 32 of metalization 12 from contaminating device 18 which typically comprises silicon. Note that as indicated in the FIGURE it is not unusual to place a layer 24 of Pd.sub.2 Si between device 18 and metalization 12; as previously indicated, this Pd.sub.2 Si layer 24 enhances ohmic contact to the device.

The bimetal layer of the present invention may also be located between an aluminum or aluminum/copper layer such as 32, 34, or 36 and a dielectric layer such as 22 or 30. At such a location, the present invention serves as an etch stop during the plasma etching of the aluminum or aluminum/copper since TiN does not etch in plasmas such as chlorine commonly used for delineating the pattern of metalizations such as 12, 14, and 16. This aspect of the present invention has an advantage over similar approaches in the prior art. One approach in the prior art was to use TiW as a barrier metal. However, when TiW is nitrided to form TiWN, it deprives the material from functioning as an etch stop. However, inasmuch as TiN is an effective etch stop in a plasma environment, the TiN not only serves as a barrier against mobile ion contamination but also as an etch stop. This etch stop feature of the present invention allows normal processing to be done on multilayer metalization structures while also achieving the protection against aluminum or aluminum/copper spiking and against mobile ion contamination.

The bimetal layer of the present invention may also be located between layers of aluminum or aluminum/copper, e.g., between layer 32 and 34 in the region of oversized via 38. At such a location, the TiN layer 28 comprising the present invention serves as an etch stop in forming the second layer of metal 14 at this location.

This etch stop feature is also important during the etch of a region which might comprise a thickness of metal two or three times the thickness of the normal metalization coverage (see, for example, the thickness labelled 3X in the FIGURE). If the present invention did not comprise an etch stop, the etching of third metal layer 36 in the region of nominal thickness would not be stopped by TiN layer 28. For example, if the present invention did not comprise TiN layer 28, a chlorine etching process used in removing the 3X region in the FIGURE would not only attack metalization layer 36 but also those portions of dielectric layer 30, and, perhaps, second metalization layer 34 located below those portions of layer 36 that are of nominal thickness.

In fabricating devices comprising the present invention, layer 28 of TiN may be formed by reactively sputtering a Ti target in Ar with a 10% partial pressure of nitrogen at a total pressure of 10 mTorr and an RF power of 6.5 w/cm.sup.2. Without breaking the vacuum, wafers may then be transferred to a TiW target. There the TiW may be reactively sputtered with a 50% partial pressure of nitrogen in Ar at a total pressure of 10 mTorr. For this portion of the process, a DC power on the order of 6.5 w/cm.sup.2 may be used.

The resulting multilayer barrier metal 28, 29 is etchable in a plasma of BCl.sub.3 followed by CF.sub.4 plus oxygen plasma (TiWN etches in a chlorine containing plasma; TiN etches in a fluorine plasma).

The reason that it is preferred to make layer 28 of TiN relatively thin (in the 200-500 angstrom range as previously indicated) is that a gas such as CF.sub.4 used to plasma etch the TiN layer will also typically etch any SiO.sub.2 layer below layer 28; accordingly by making layer 28 thin, it can be quickly etched away without injury to the dielectric layer below it.

All other portions of integrated circuits comprising the present invention may be fabricated using standard processes, dimensions and materials or other processes, dimensions and materials as desired. Further, those skilled in the art will recognize that many other processes to fabricate layers 28 and 29 of the present invention are also possible.

The present invention is to be limited only in accordance with the scope of the appended claims, since others skilled in the art may devise other embodiments still within the limits of the claims. For example, locations of the present invention other than those illustrated in the FIGURE are possible. Further, those skilled in the art will also recognize that many other variations, both in processing and structure, are also possible in addition to those disclosed.

## Claims

claimed are defined as follows:

1. A bimetal layer located between a metalization layer and a semiconductor device in an integrated circuit, the bimetal layer comprising a layer of TiWN and a layer of TiN, wherein one of the TiWN and TiN layers is deposited above the other.

2. The apparatus of claim 1 wherein the layer of TiN is located between the layer of TiWN and the semiconductor device.

3. The apparatus of claim 2 where a layer of Pd.sub.2 Si is located between the layer of TiN and the semiconductor device.

4. The apparatus of claim 3 wherein the metalization layer comprises aluminum and wherein the semiconductor device comprises silicon.

5. The apparatus of claim 4 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

6. The apparatus of claim 1 where a layer of Pd.sub.2 Si is located between the bimetal layer and the semiconductor device.

7. The apparatus of claim 6 wherein the metalization layer comprises aluminum and wherein the semiconductor device comprises silicon.

8. The apparatus of claim 7 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

9. The apparatus of claim 1 wherein the metalization layer comprises aluminum and wherein the semiconductor device comprises silicon.

10. The apparatus of claim 9 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

11. The apparatus of claim 1 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

12. A bimetal layer located between a metalization layer and a dielectric layer in an integrated circuit, the bimetal layer comprising a layer of TiWN and a layer of TiN, wherein one of the TiWN and TiN layers is deposited above the other.

13. The apparatus of claim 12 wherein the layer of TiN is located between the layer of TiWN and the dielectric layer.

14. The apparatus of claim 13 wherein the metalization layer comprises aluminum and wherein the dielectric layer comprises an oxide of silicon.

15. The apparatus of claim 14 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

16. The apparatus of claim 12 wherein the metalization layer comprises aluminum and wherein the dielectric layer comprises an oxide of silicon.

17. The apparatus of claim 16 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

18. The apparatus of claim 12 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

19. A bimetal layer located between two metalization layers in an integrated circuit, the bimetal layer comprising a layer of TiWN and a layer of TiN, wherein one of the TiWN and TiN layers is deposited above the other.

20. The apparatus of claim 19 wherein the layer of TiN is located under the layer of TiWN.

21. The apparatus of claim 20 wherein each of the metalization layers comprise aluminum.

22. The apparatus of claim 21 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

23. The apparatus of claim 21 wherein each of the metalization layers comprise aluminum.

24. The apparatus of claim 23 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.

25. The apparatus of claim 19 wherein the TiN layer has a thickness in the range of approximately 200 angstroms through approximately 500 angstroms.