# Patent

## Title
Electronically variable active analog delay line

## Abstract

A transistor (14) having a plurality of sub-transistors (29a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24). The limiting of current through the output sub-transistors (29a-f) for a predetermined time interval reduces the generation of output noise by controlling the rate at which current is changing in that output.

## Background
This invention pertains in general to integrated circuits, and more particularly relates to apparatus and methods for reducing output noise of digital integrated circuits.

"Integrated Circuit Distributed Geometry To Reduce Circuit Noise," by Steven Edward Marum, James Craig Spurlin, Dale Philip Stein, and Sam Max Weaver.

"Integrated Circuit to Reduce Noise," by George John Ehni, Ser. No. 901918, filed 8/29/86 concurrently herewith.

Advancement in integrated circuit technology has lead to vast improvements in the speed of integrated circuits, i.e. the time in which the output of a circuit reacts in response to a new input. Increasing integrated circuit speed has resulted in faster rise and fall times of the output voltages. Similarly, the fast rise and fall times of the output voltages have resulted in abrupt transitions of output current.

While faster speeds are very desirable, the abrupt transition of output currents has created serious problems. The package which holds an integrated circuit device has metallic leads which allow interconnection of the device on a circuit board. Each lead has a small inductance associated with it. The leads are connected to the integrated circuit using bonding wire, which also has an inductance associated with it. Voltage is related to inductance and the time rate of change of current by the equation E=L.multidot.dI/dT, where L is the measure of inductance, and dI/dT is the change in current with respect to time. The abrupt transition of output currents creates a large change of current at the ground and power supply leads and in the bonding wire, resulting in ground and power supply voltage spikes. These voltage spikes affect the output voltages of the device, and cause output ringing, ground bounce, and false signals.

Techniques have been heretofore developed which attempt to alleviate this problem by reducing the amount of inductance (L) present at the leads. One method provides multiple power supply and ground leads in order to reduce the inductance (L) that generates the voltage spikes. However, the reduction in inductance is often insufficient to eliminate voltage spikes at the output of many devices, and many necessitate using a larger package to carry the same integrated circuit.

Another method has attempted to reduce the effect of the voltage spikes by bifurcating the surge of current through the lead inductances of the package. The large pull-down transistor in the standard CMOS buffer is split into two devices separated by a resistor. The resistor delays the turn-on of the second device so that the circuit produces two smaller current spikes rather than one large current spike. While somewhat slowing the edge of the output current transition, this circuit is often insufficient to bring the dI/dT term to a value which will eliminate voltage spikes at the power and ground leads.

From the foregoing, it may be seen that a need has arisen for a technique which produces a smooth change of output current with respect to time in response to switching output voltage states, in order to reduce or eliminate voltage spikes. Furthermore, a need has arisen for circuitry capable of protecting against false outputs without substantially increasing the number of devices needed to implement the circuitry.

In accordance with the present invention, an integrated circuit is provided which substantially eliminates or reduces disadvantages and problems associated with switching noise in prior high speed integrated circuits.

In accordance with an aspect of the invention, a transistor is provided for reducing output switching noise. The transistor includes a substrate having semiconductor areas forming a plurality of transistor regions, and an elongated gate having a predetermined resistance. A signal applied to a first end region of the gate propagates along the length of the gate during a predetermined time interval. Upon application of a signal to the first end of the elongated gate, a conducting device conneted to a second end of the gatee allows a current between the first and second ends, creating a voltage drop along the gate. The voltage drop across the elongated gate decreases the amount of current which the transistor regions exposed to reduced gate voltage can conduct. Over a predetermined time interval, the amount of current through the conducting device is reduced, thereby increasing the amount of current which the transistor regions can conduct. The predetermined time interval over which the conducting device induces a current through the elongated gate can be adjusted by positioning the gate of a transistor along the elongated gate. The gradual increase in conductivity of the transistor regions reduces the generation of output noise by limiting the rate of change of output current with respect to time.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description in conjunction with the accompanying Drawings in which:

FIG. 1 illustrates a layout of a circuit implemented in accordance with the present invention in a CMOS chip to reduce abrupt output current transitions with respect to time;

FIG. 2 illustrates a cut-away view of the P-channel transistor illustrated in FIG. 1;

FIG. 3 illustrates a detailed circuit diagram of the invention using an equivalent circuit representation of an output transistor;

FIG. 4 illustrates output characteristic curves for a representative transistor.

The preferred embodiment of the present invention is best understood by referring to FIGS. 1-4 of the Drawings, like numerals being used for like and corresponding parts of the various Drawings. FIG. 1 illustrates a circuit used to reduce the sharp current transitions in a CMOS device. An output CMOS transistor pair, generally referred to by the reference number 10, includes a P-channel transistor 12 and an N-channel transistor 14.

The P-channel transistor 12 includes a polysilicon serpertine gate 16 disposed between a plurality of elongated P-channel sources 18a-f and elongated P-channel drains 20a-e, forming sub-transistors identified by brackets 21a-j. As may be seen, gate 16 is formed of elongated portions which extend parallel to the sources and drains, with the elongated portions joined at alternating upper and lower regions thereof by short portions perpendicular to the sources and drains to form a single continuous serially-connected gate for the entire transistor 12. A plurality of metal contacts 22 are formed on each P-channel source 18a-f and P-channel drain 20a-e. The P-channel sources 18a-f are connected to V.sub.cc (the power supply lead), generally held at five volts.

The N-channel transistor 14 also employs a polysilicon serpentine gate 24 separating a plurality of elongated N-channel sources 26a-d and N-channel drains 28a-c, forming sub-transistors identified by brackets 29a-f. Gate 24 is constructed similarly to gate 16 to form a single serially-connected gate for the entire transistor 14. Each of the N-channel sources 26a-d and N-channel drains 28a-c have a plurality of metal contacts 30. The N-channel sources 26a-d are connected to ground.

The output 34 of the output pair 10 is connected to the P-channel drains 20a-e and the N-channel drains 28a-c. A capacitor 35 is shown in phantom to represent the capacitance of the circuitry connected to the output.

A plurality of P-channel pull-up transistors 36 is connected at their gates to the input terminal 37 of the output pair 10. The drains of transistors 36 are connected at successive positions on the P-channel serpentine gates 16 and the sources of transistors 36 are connected to V.sub.cc. The input 37 in connected to the gate of a N-channel inverting transistor 38 having its source connected to ground and its drain connected to the input of the P-channel serpentine gate 16 and to the drain of the first pull-up transistor 36. Similarly, a plurality of N-channel pull-down transistors 40 is connected with their drains connected to successive points on the N-channel serpentine gate 24, the sources of transistors 40 being tied to ground and their gates connected to the input terminal 37. A P-channel inverting transistor 44 is connected at its gate to the input terminal 37, the source of transistor 44 connected to V.sub.cc and its drain connected to the drain of the first pull-down transistor 40 and to the input of the N-channel serpentine gate 24.

A voltage controlling circuit 45 embodies the present invention and is connected at one terminal to input 37, another terminal to the output end of gate 24 and a third terminal to a point on the serpentine gate 24. The specific circuitry and operation of circuit 45 will be subsequently described in connection with FIG. 3.

It should be noted that while FIG. 1 illustrates a representative output pair 10 of a CMOS device, the relative sizes of the P-channel transistor 12 and the N-channel transistor 14 may vary according to the desired application. Both the size and the number of the sources and drains of the transistors may vary accordingly, without effect on the present invention. Similarly, the number of pull-up transistors 36 and pull-down transistors 40 may also vary depending upon the application. CMOS pair 10 is constructed similarly to known CMOS circuits, except that the serpentine gates 16 and 24 are uniquely formed in order to slow down the conduction of the pair in order to reduce or eliminate spikes or noise at the circuit output.

As is known, a P-channel transistor conducts between source and drain when the gate voltage is negative with respect to the source voltage. Therefore, if the source is tied to V.sub.cc, a P-channel transistor will conduct when a "low" signal is present at its gate and will not conduct when a "high" signal is present at its gate. Conversely, a N-channel transistor will conduct between source and drain when the gate voltage is positive with respect to the source voltage. Thus, if the source of a N-channel transistor is tied to ground, it will conduct when a "high" signal is present at its gate and not conduct when a "low" signal is present at the gate. A transistor is "turned-on" if it is in a conducting (low impedance) state, and is "turned-off" if it is in a non-conducting (high impedance) state.

The P-channel transistor 12 is comprised of many sub-transistors 21a-j connected in parallel. In the illustrated embodiment, the P-channel transistor 12 comprises ten such sub-transistors. For example, the first sub-transistor 21a includes the source 18a, the drain 20a and a leg of the serpentine gate 16 therebetween. The second sub-transistor 21b comprises the drain 20a, the source 18b, and a leg of the serpentine gate 16 therebetween. The last sub-transistor 21j includes the drain 20e, the source 18f and the last leg of the serpentine polysilicon gate therebetween. The sources of each P-channel sub-transistor 21a-j are connected in parallel to V.sub.cc, while the drains of each sub-transistor 21a-j are connected to the output 34. Similarly, the N-channel transistor 14 includes a plurality of N-channel sub-transistors 29a-f, each characterized by a source and a drain (or a drain and a source) with a leg of the serpentine polysilicon N-channel gate between. The sources of the N-channel sub-transistors 29a-f are connected in parallel to ground 32 and the drains are connected in parallel to the output 34.

In operation of the circuit of FIG. 1, assume that the input 37 to the output pair 10 is initially in a "high" state. The two complimentary pairs comprising transistors 36-38 and 40-44 act as inverters between the input 37 and the beginning of the serpentine gates 16 and 24. Thus, a "low" signal would be present at the gate 16 of the P-channel transistor 12 and at the gate 24 of the N-channel transistor 14. The low signal present at serpentine gates 16 and 24 would result in the P-channel transistor 12 being turned on and the N-channel transistor 16 being turned off. Therefore, in the initial state with a "high" input signal, the output 34 would be high, and the output circuitry capacitance 35 would be fully charged. After the output circuitry capacitor 35 is charged, only a negligible amount of current would exist from V.sub.cc to the output 34. With the N-channel transistor 14 turned off, there would be negligible leakage current to ground.

However, as the input 37 switches from a high signal to a low signal, the P-channel transistor 12 will turn off and the N-channel transistor 14 will turn on; thus, the output 34 will switch from a high signal to a low signal. Previously developed CMOS transistors have been designed to charge the entire gate substantially instantaneously, thus turning all the N-channel sub-transistors on simultaneously. This results in a surge of current from the output circuitry to the ground, which would in turn create a large voltage at the ground node due to inductance. The change of voltage at ground, which is a reference for all the other voltages in the circuit, would adversely affect the output voltages. Naturally, this problem is compounded when multiple outputs are switching simultaneously.

The circuit of FIG. 1, however, prevents the rush of current through the ground 32 by more gradually draining the outside circuitry capacitor 35 as follows. The serpentine polysilicon gates 16 and 24 are essentially distributed RC networks, as will be discussed in more detail below in conjunction with FIG. 2. Thus, the input current will propagate along the N-channel serpentine gate 24 according to a predetermined time interval. As the signal propagates along the serpentine gate path, the voltage will increase along the leg of the serpentine gate 24 between the source 26a and the drain 28a, increasing the voltage across the leg. When a threshold voltage is reached, the first N-channel sub-transistor 29a will turn on, allowing charge to flow from the output circuitry capacitor 35 to ground therethrough. However, the amount of current which a single sub-transistor can sink is only a fraction of what the N-channel transistor 14 could sink if all its sub-transistors 29a-f were turned on. Consequently, the dI/dT term attributable to the change in current caused by turning on the first sub-transistor 29a is relatively small in comparison to the change in current attributable to turning on an entire transistor. As the current reaches a steady state, the dI/dT term will return to zero.

As the input current continues to propagate through the N-channel serpentine gate 24, the leg between the frist drain 28a and the second source 26b will also reach the threshold volatge, turning on the second sub-transistor 29b. After the second sub-transistor 29b turns on, twice as much charge will be flowing from the output circuit capacitor 35 to ground 32, but the incremental change in current will only be the current attributable to the turn-on of the second sub-transistor 29b. Thus, the dI/dT term will again be relatively small. The input signal will continue to propagate along the N-channel serpentine gate 24, successively turning on each of the six sub-transistors 29a-f contained in the N-channel transistor 14. The successive turn-on of the sub-transistors may be referred to as "graded" or "graduated" turn-on. The "graded turn-on" of the present invention provides the technical advantage of reducing noise in the output voltage.

After each sub-transistor 29a-f turns on, there will be a small increase in the current; the dI/dT term will increase from zero, but will be smaller in value than if the sub-transistors 29a-f had turned on simultaneously. By the time the input signal has propagated through the entire polysilicon gate 24, all six sub-transistors 29a-f will be conducting to the extent permitted by their varying gate voltages. The rate of change of the current with respect to time, however, will have been reduced as each of the six sub-transistors turned on. Thus, the dI/dT factor will be much less than if the entire N-channel transistor 14 turned on at once. This has been found to significantly reduce noise and spikes in the output signal.

The voltage controlling circuit 45 further reduces the dI/dT factor by temporarily decreasing the voltage present at the gates of the sub-transistors 29a-f, thereby decreasing the amount of the current conducted by the sub-transistors 29a-f. The operation of voltage controlling circuit 45 will be described in detail in connection with FIG. 3.

After the charge from the output circuitry capacitor 35 has been drained through ground, the current through the ground 32 will once again be practically zero. Likewise, since the P-channel transistor 12 remains turned off, no current will exist from V.sub.cc to output 34.

Assuming the input 37 is now changed from low to high, in previously developed P-channel transistors, the entire P-channel transistor would turn on, allowing current from V.sub.cc to the output 34, charging the output circuitry capacitor 35. Since the entire P-channel transistor would be turned on at once, there would be an abrupt increase in current from V.sub.cc to output 34, causing a large voltage drop to occur at the V.sub.cc node, and causing undesirable noise in the output voltage.

However, in the present invention, the low signal present at the input of the P-channel polysilicon gate 16 will propagate along the serpentine gate 16, successively turning on the ten sub-transistors 21a-j comprising the P-channel transistor 12. As each sub-transistor 21a-j is turned on, charge from V.sub.cc will flow to the output circuit, thus creating a current from V.sub.cc to the output 34. However, as described above, the increase in the rate of flow will occur as each P-channel sub-transistor 21a-j is turned on, limiting the dI/dT term to a relatively small value. Consequently, the noise spike at the V.sub.cc node will be greatly reduced, thus providing substantial technical advantages.

The purpose of the pull-up transistors 36 and pull-down transistors 40 is to turn off the sub-transistors 21a-j or 29a-f simultaneously, thereby preventing a short circuit from V.sub.cc to ground 32. For example, with the input 37 initially in a high state, all the sub-transistors 21a-j of the P-channel transistor 12 will be turned on. As the input signal changes from high to low, the sub-transistors 29a-f of the N-channel transistor 14 will turn on incrementally and without the pull-up transistors 36, sub-transistors 21a-j of the P-channel transistor would turn off incrementally. At some point, sub-transistors of both the P-channel transistor and the N-channel transistor would be conducting simultaneously, resulting in a short from V.sub.cc to ground. Naturally, this would cause high currents at both the V.sub.cc and ground, resulting in high power dissipation in the device.

The P-channel pull-up transistors 36 serve to turn off all of the sub-transistors 21a-j of the P-channel transistor 12 at once by applying V.sub.cc at various points along the P-channel serpentine gate 16. In operation, the pull-up transistors will turn on in response to a low signal at their gates, and apply V.sub.cc along the P-channel serpentine gate 16. Thus, in the illustrated embodiment, all the legs of the polysilicon gate 16 will be charged at essentially the same time, resulting in a fast turn off of the P-channel sub-transistors 21a-j.

Likewise, the N-channel pull-down transistors 40 will operate to simultaneously turn off the sub-transistors 29a-f of the N-channel transistor 14 whenever a high signal is present at the input 37, preventing a possible short through the latter sub-transistors of the N-channel transistor 14 and the initial sub-transistors of the P-channel transistor 12.

Referring now to FIG. 2, a cross-section of the P-channel transistor 12 is shown to illustrate the source of the resistive-capacitive effect, which resists propagation of a signal along the P-channel serpentine gate 16. The polysilicon gate 16 is known to have predetermined resistance. The sources 18 and drains 20 of the P-channel transistor 12 are shown formed by conventional techniques into a N-well 46. A silicon dioxide layer 48 covers the sources 18, drains 20 and N-well 46. The silicon dioxide layer over th N-well 46 is very thin and is known as the "gate oxide". The metal contacts 22 extend through the silicon dioxide layer 48 and contact the sources 18 and drains 20. Fabrication of transistors 12 and 14 is by conventional techniques and will not thus be described in detail. Conducting channels 50 between the sources and drains are illustrated with dotted lines to show the channels are present only when there is a negative voltage on the gate 16 with respect to the source 18. In the present case, the negative voltage will be present when a source 18 is connected to V.sub.cc and its respective leg of the serpentine gate 16 is brought to ground.

While parasitic capacitance exists between the gates 16 and sources 18 and between the gate 16 and the drain 20, the main source of capacitors will be created by the conducting channels 50 and the polysilicon gates 16 acting as conductors, and the thin silicon dioxide layer acting as a dielectric therebetween. Similar structure creates resistance and capacitance in the case of the N-channel transistor 14. The capacitance and resistance of the present circuit thus cause a predetermined time delay in the propagation of the input signal through the serpentine gate.

FIG. 3 illustrates the voltage controlling circuit 45 in conjunction with an equivalent circuit representing the N-channel transistor 14. Sub-transistors 29a-f are illustrated in schematic form with their gates separated by series resistive elements 52a-f to illustrate the resistance of the N-channel serpentine gate 24. The sources of the sub-transistors 29a-f are connected to ground 32 and the drains are connected to the output 34. A first inverter 54 is shown in schematic form to represent the inverter formed by the inverting transistor 44 and the first pull-down transistor 40 of FIG. 1. The input 37 is connected to the first inverter 54 and a second inverter 56. The second inverter 56 is connected to a first terminal 57 of capacitor 58, and a second terminal 59 is connected to the gate of the N-channel shunting transistor 60 and to the drain of a N-channel discharging transistor 62. The drain of the shunting transistor 60 is connected to the end of resistive element 52f which represents the end of the N-channel serpentine gate 24. The source of the shunting transistor 60 is connected to ground 32. The gate of the discharging transistor 62 is connected to a node on the serpentine gate 24 and its source is connected to ground 32.

Because a N-channel transistor has much higher current sinking capability than a P-channel transistor of the same size, an output pair, such as the output pair 10 illustrated in FIG. 1, can have a N-channel transistor 14 which is one-third as big as the P-channel transistor 12. Consequently, the N-channel serpentine gate 24 may have approximately on-third the resistance of the P-channel serpentine gate 16, and produce about one-third of the capacitance. This results in an R-C time constant product which is roughly one-ninth of the R-C time constant product of the P-channel transistor 12. The effectiveness of the graded turn-on in the N-channel devices may thus be only about one-ninth as effective as in P-channel devices. The voltage controlling circuit 45 serves to reduce the surge of current through the N-channel transistor 14 by temporarily reducing the capability of the N-channel sub-transistors 29a-f to conduct.

In operation, the voltage controlling circuit 45 limits the current sinking capability of the sub-transistors 29a-f by producing a temporary I-R drop across the serpentine gate 24. The I-R drop provides successively lower gate voltages at each of the sub-transistors 29a-f. As will be described more fully in connection with FIG. 4, the amount of current which a transistor can conduct varies with its gate voltage.

A high to low transition of the signal at the input 37 causes a low to high transition of the signal present at the beginning of the serpentine gate 24 and at the first terminal 57 of the capacitor 58. As previously described, the high signal present at the serpentine gate 24 propagates along the gate 24 and sequentially turns the sub-transistors 29a-f on. The capacitor 58 resists changes in the voltage differential between its terminals 57 and 59; therefore, it will raise the voltage at the second terminal 59 to a voltage level approximately the high signal. The high signal present on the second terminal 59 is also present at the gate of the shunting transistor 60, putting it in a conducting state. Hence, the shunting transistor 60 conducts between the end of the serpentine gate 24 and ground 32 causing a current through the serpentine gate 24.

A current through the serpentine gate 24 creates a voltage drop over each of the resistive elements 52a-f. Therefore, each sub-transistor has a gate voltage which is less than the sub-transistor preceding it. Since the first sub-transistor 29a would be fully turned-on, it would be able to sink more current than the last sub-transistor 29f, which would conduct relatively little current. By limiting the current through the sub-transistors 29a-f, the rate at which current is changing at the ground node 32 is reduced.

While it is desirable to limit the current sinking capability of the sub-transistors 29a-f at the beinging of the output voltage transition, it is also necessary that the N-channel transistor 14 eventually be able to sink current at its maximum capability in order to maintain rated output switching rates. Therefore, it is beneficial to inhibit current though the serpentine gate 24 after a predetermined time interval. The purpose of the discharging transistor 62 is to discharge the capacitor 58 buy providing a path to ground 32. Discharging transistor 62 has its gate connected to a node on the serpentine gate 24, and is therefore in a conducting state only when the proper signal is present at the node on the gate 24. Thus, by positioning the gate of the discharging capacitor 62 at different nodes along the serpentine gate 24, the time at which discharge transistor 62 turns on, and the strength with which it turns on may be varied. After the discharging transistor 62 turns on, it bleeds the charge off of capacitor 58, thereby reducing the voltage present at the gate of the shunting transistor 60; consequently, the amount of current which the shunting transistor 60 can conduct is reduced, and the amount of current flowing through the serpentine gate 24 is also reduced. The reduction in current flowing through the serpentine gate 24 causes a proportional reduction in the voltage drop across the resistor elements 52a-f. The reduction in the voltage drop across the resistive elements 52a-f increases the gate voltage at each of the sub-transistors 29a-f allowing the sub-transistors 29a-f to conduct more current.

The discharging transistor 62 continues to bleed the charge off the capacitor 58 until a near zero voltage is present at the gate of the shunting transistor 60. As the voltage at the gate of the shunting transistor 60 declines, the voltage at the gates of the sub-transistors 29a-f increases; at the point where the shunting transistor 60 is no longer conducting, the voltages at the gates of sub-transistors 29a-f will be equal to the voltage present at the beginning of the serpentine gate 24.

In the current invention, the gate of the discharging transistor 62 is connected to a node on the elongated gate 24; thus, the time of discharge may be adjusted by moving the connection of the gate of the discharging transistor 62 along the length of the serpentine gate 24. By placing the gate of discharging capacitor 62 towards the input end of the serpentine gate 24, the discharging transistor 62 will turn on earlier and more strongly than if the gate of the discharging transistor 62 is placed further along the serpentine gate 24. By placing the gate towards the output end of the polysilicon gate 24, the duration of the I-R drop can be increased while decreasing the size of capacitor 58 thereby providing a smoother current transition while using less space on the integrated circuit.

The present invention has the further advantage that the duration of the I-R drop can be easily modified by repositioning the gate of the discharging transistor 62 along the serpentine gate 24. For a given capacitor 58 and discharge transistor 62, the duration of the I-R drop as a function of the position of the gate of the discharge transistor 62 along the serpentine gate 24 depends upon two factors. The first factor is the time taken by the signal to propagate along the serpentine gate 24 to the point of connection between the serpentine gate 24 and the gate of the discharging transistor 62. The second factor is the voltage present at the gate at the point of connection, since the gate voltage of the discharging transistor 62 will determine how fast the transistor conducts charge from the capacitor 58 to ground 32. As previously described, the voltage along the serpentine gate 24 depends upon the voltage drop caused by shunting transistor 60.

In the preferred embodiment, the capacitor 58 is formed by connecting the source and drain of a N-channel transistor to form one terminal, with the polysilicon gate used as the other terminal. However, other methods of forming a capacitive element on a integrated circuit are known to those skilled in the art.

The illustrated embodiment depicts the invention in connection with a serpentine gate. However, the invention will also work using other shared gate configurations, in which a single gate is used in conjunction with multiple sub-transistors.

FIG. 4 illustrates output characteristic curves for a typical transistor. As can be seen from the curves, the drain current I.sub.d (amount of current which the transistor will conduct) for a given drain voltage V.sub.d increases substantially proportionally with the voltage present at the gate V.sub.g. It is this characteristic of a transistor which allows the present invention to provide a smooth current transition in response to a changing output by proportionately decreasing the gate voltage of successive sub-transistors 29a-f in the N-channel transistor 14. This characteristic also accounts for a decrease in current through the resistive elements 52a-f  in response to decreasing the signal present on the gate of the shunting transistor 60.

It should also be noted that while the invention has been illustrated in FIG. 3 with a N-channel transistor, it could be easily modified to reduce the sharp transition of current in a P-channel, bipolar, NMOS, or other transistor, by methods known to those skilled in the art.

Thus, the present invention provides advantages as discussed above, as well as numerous other advantages. As will be apparent to those skilled in the art, the present invention can be widely modified and varied. The scope of the invention is not limited, except as set forth in the accompanying claims.

It is an important technical advantage that the invention may be used to reduce inductive voltages at the power supply and ground nodes of an integrated circuit by reducing the change in current through the nodes with respect to time in response to switching output voltages. It is a further technical advantage that the invention reduces the change in current with respect to time by producing a voltage drop over the gate of a transistor, thus reducing the voltage at the gate of the sub-transistors. It is yet a further technical advantage that the voltages at the gates of the sub-transistors are increased over a predetermined time interval to allow maximum current sinking by all the sub-transistors. It is yet another technical advantage that the duration of the predetermined time interval can be easily varied by moving a single connection.

Another important technical advantage is that the invention may be used with N-channel, P-channel, bipolar, and other transistors to reduce inductive voltages at the pins of an integrated circuit.

## Claims

1. A transistor circuit comprising: sub-transistors including a shared gate; said semiconductor surface areas such that a gate signal applied to a first end region of said gate propagates along the length of said gate in a predetermined time interval, the propagation of said gate signal along said shared gate causing graduated turn-on of said sub-transistors; a transient current to pass from said first end region of said shared gate through said conducting device to cause a voltage drop across said shared gate, said voltage drop reducing the amount of current conducted by said sub-transistors; and gate, said switching device operable to inhibit current through said shared gate a predetermined time after sensing a signal on said shared gate.

2. The transistor circuit of claim 1 wherein said conducting device comprises a transistor which includes a first terminal, a second terminal, and a third terminal, said first terminal being connected to said second end region of said shared gate, said second terminal being connected to said switching device, and said third terminal being connected to a predetermined voltage.

3. The transistor circuit of claim 1 wherein said switching device comprises a capacitor including a first and second capacitor plate and a transistor, said first capacitor plate being connected to said conducting device, said transistor having its gate connected to said shared gate, its drain connected to said second capacitor plate, and its source connected to a predetermined voltage.

4. The transistor circuit of claim 1 wherein said switching device comprises: connected to said conducting device such that said conducting device will conduct in response to a change in said signal on said first terminal; and conducting device is gradually rendered non-conductive a predetermined time after said inhibiting device senses a voltage change on said shared gate.

5. The transistor circuit of claim 4 wherein said inhibiting device comprises a transistor having its source connected to a predetermined voltage, its gate connected to said shared gate, and its drain connected to said capacitor.

6. A method of reducing noise in the output signal of a semiconductor transistor which includes sub-transistors formed on semiconductor surface areas, wherein said method comprises: distributed resistance and being disposed in the semiconductor surface areas such that a signal, applied to a first end region of said gate, propagates along the gate in a predetermined time interval causing conduction of said sub-transistors; gate thereby reducing the current conduction capability of said sub-transistors; signal at said second node.

7. The method of claim 6, wherein said gate is an elongated gate, such that propagation of said input signal along said gate causes sequential conduction of said sub-transistors.

8. The transistor circuit as recited in claim 1 wherein said shared gate is elongated.

9. The transistor circuit as recited in claim 1 wherein said switching device is connected selectively to positions along said shared gate.

10. The transistor circuit as recited in claim 8 wherein said switching device is connected selectively to positions along said shared gate.