# Patent

## Title
CMOS logarithmic current generator and method for generating a logarithmic current

## Abstract

A CMOS logarithmic current generator includes current mode circuitry having a design principle based on a Taylor's series expansion that approximates an exponential function. A MOSFET circuit provides a function generator core cell having a biasing current Ib. The FETs of the circuit are matched and are biased in the weak inversion region. Additional transistors are used to convert a pair of input currents to a pair of voltages to provide an output current based upon a current mode logarithmic function. The biasing current Ib can be varied to provide a variable gain in the circuit.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to current mode electronic circuitry, and particularly to a complimentary metal-oxide semiconductor (CMOS) logarithmic current generator.
2. Description of the Related Art
A logarithmic function is a non-linear function in which the output is proportional to the logarithm of the input. The circuits performing such a function are typically widely used in many applications, these include but are not limited to medical equipment, instrumentation, telecommunication, active filters, disk drives and neural networks, for example.
Many approaches to the design of a logarithmic circuit have been reported in the literature. An existing type of CMOS current-mode logarithmic circuit produces the logarithmic of an input greater than unity and generally has a limited dynamic range. In addition, typically an existing type of CMOS current-mode logarithmic circuit has relatively no gain controllability and uses some passive elements. Other realizations of an existing type of CMOS current-mode logarithmic circuit typically have at least one of the following drawbacks. These drawbacks include, for example, absence of low voltage operation capability, a limited dynamic range, employment of bipolar junction transistor (BJT) transistors, does not enjoy a current-mode, cannot realize a true logarithmic function circuit where the ratio is larger or smaller than unity, temperature dependent, relatively high power consumption, generally no controllability, and, to some extent, linearity error is high, use passive elements, i.e. resistors, and general complexity of the circuit.
Thus, a CMOS logarithmic current generator addressing the aforementioned problems is desired.
SUMMARY OF THE INVENTION
The CMOS logarithmic current generator includes current mode circuitry having a design principle based on Taylor's series expansion that approximates an exponential function. A metal-oxide semiconductor field-effect transistor (MOSFET) circuit provides a function generator core cell having a current Ib. The field effect transistors (FETs) of the circuit are matched and are biased in the weak inversion region. Additional transistors are used to convert a pair of input currents to a pair of voltages in logarithmic form to provide a current mode logarithmic function. The current Ib can be varied to provide variable gain in the circuit.
These and other features of the present invention will become readily apparent upon further review of the following specification and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plot of the error between ex−e−x and 2x.
FIG. 2 is a circuit diagram and block equivalent of a basic exponential function circuit used in embodiments of a CMOS logarithmic current generator according to the present invention.
FIG. 3 is a circuit diagram of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 4 is the layout of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 5 is a plot of simulated and calculated results of an input current versus an output current in an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 6 is a plot showing gain variability using a bias current in an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 7 is a plot showing the effect of temperature change on an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 8 is a plot showing the transient response of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 9 is a plot showing the frequency response of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 10 is a plot showing simulation results for log(1/x) of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 11 is a plot showing input noise as a function of frequency of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.
FIG. 12 is a plot showing output noise as a function of frequency of an embodiment of a CMOS logarithmic current generator circuit according to the present invention.



Unless otherwise indicated, similar reference characters denote corresponding features consistently throughout the attached drawings.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of a CMOS logarithmic current generator include current mode circuitry having a design principle based on a Taylor's series expansion that approximates an exponential function, the approximation being characterized by the relation:




  
    
      
        
          
            e
            x
          
          =
          
            1
            +
            x
            +
            
              
                x
                2
              
              
                2
                !
              
            
            +
            
              
                x
                3
              
              
                3
                !
              
            
            +
            ...
            ⁢
            
              
            
            +
            
              
                x
                n
              
              
                n
                !
              
            
            +
            ...
          
        
        ⁢
        
          
        
        ,
      
    
    
      
        (
        1
        )
      
    
  




where x is the independent variable and if x is much smaller than one (x<<1), then the higher order terms in the Taylor's series approximation become negligible and relation (1) can be written as:





  
    
      
        
          e
          x
        
        ≈
        
          1
          +
          x
          +
          
            
              
                x
                2
              
              
                2
                !
              
            
            ⁢
            
              
            
            ⁢
            for
            ⁢
            
              
            
            ⁢
            x
          
        
        ⪡
        1.
      
    
    
      
        (
        2
        )
      
    
  




According to relation (2), e−x can be written as:




  
    
      
        
          e
          
            -
            x
          
        
        ≈
        
          1
          -
          x
          +
          
            
              
                x
                2
              
              
                2
                !
              
            
            .
          
        
      
    
    
      
        (
        3
        )
      
    
  




From relations (2) and (3) it can be shown that:

ex−e−x≈2x.  (4)

The error between ex−e−x and 2x is plotted in FIG. 1. The error can be less than 0.1% while the input |x|<0.2. As shown in FIG. 2, the exemplary basic exponential function circuit 200 has a MOSFET circuit 210a providing function generator core cell 210b with a current Ib. Assuming that the FETs, such as FETS M1 and M2 of 210a are relatively perfectly matched and both are biased in the weak inversion region, the I-V characteristics of the MOSFET in weak inversion is given by:





  
    
      
        
          I
          b
        
        =
        
          
            
              I
              
                D
                ⁢
                
                  
                
                ⁢
                0
              
            
            ·
            
              exp
              ⁡
              
                [
                
                  
                    
                      (
                      
                        
                          V
                          DD
                        
                        -
                        
                          V
                          A
                        
                      
                      )
                    
                    +
                    
                      
                        (
                        
                          n
                          -
                          1
                        
                        )
                      
                      ⁢
                      
                        V
                        BS
                      
                    
                  
                  
                    nU
                    T
                  
                
                ]
              
            
          
          ⁢
          
            
          
          ⁢
          and
        
      
    
    
      
        (
        5
        )
      
    
  
  
    
      
        
          
            I
            2
          
          =
          
            
              I
              
                D
                ⁢
                
                  
                
                ⁢
                0
              
            
            ·
            
              exp
              ⁡
              
                [
                
                  
                    
                      (
                      
                        
                          V
                          DD
                        
                        -
                        
                          V
                          B
                        
                      
                      )
                    
                    +
                    
                      
                        (
                        
                          n
                          -
                          1
                        
                        )
                      
                      ⁢
                      
                        V
                        BS
                      
                    
                  
                  
                    nU
                    T
                  
                
                ]
              
            
          
        
        ,
      
    
    
      
        (
        6
        )
      
    
  




where





  
    I
    
      D
      ⁢
      
        
      
      ⁢
      0
    
  
  =
  
    2
    ⁢
    
      
    
    ⁢
    n
    ⁢
    
      
    
    ⁢
    
      μ
      n
    
    ⁢
    
      C
      ox
    
    ⁢
    
      U
      T
      2
    
    ⁢
    
      W
      L
    
  




is the leakage current, n is the weak inversion slope factor, μn is the mobility of charge carriers





  
    
      cm
      2
    
    
      V
      .
      s
    
  
  ,




Cox is the normalized oxide capacitance, capacitor per unit gate area





  
    F
    
      m
      2
    
  
  ,




VBS is the body-source voltage of M1 and M2, and UT=KbT/q is the thermal voltage, Kb is Boltzmann's constant (1.38*10−23 J/K), T is temperature in degrees Kelvin (K), and q is charge of an electron (1.6*10−19 coulombs(C)). Combining relations (5) and (6) provides:





  
    
      
        
          I
          2
        
        =
        
          
            I
            b
          
          ·
          
            
              exp
              ⁡
              
                [
                
                  
                    (
                    
                      
                        V
                        A
                      
                      -
                      
                        V
                        B
                      
                    
                    )
                  
                  
                    nU
                    T
                  
                
                ]
              
            
            .
          
        
      
    
    
      
        (
        7
        )
      
    
  




Referring now to FIG. 3, there is illustrated a circuit diagram of an embodiment of a CMOS logarithmic current generator circuit 300. The CMOS logarithmic current generator 300 illustrates a plurality of transistors, such as MOSFETS, namely MOSFETS M1 through M8, for example. In the CMOS logarithmic current generator circuit 300, a first metal-oxide semiconductor field-effect transistor (MOSFET) M1 and a second MOSFET M2 are matched with each other and configured in the (CMOS) logarithmic current generator circuit 300 as a first MOSFET pair biased in a weak inversion region to provide a first function generator core cell 310.
Also, in the CMOS logarithmic current generator circuit 300, a third MOSFET M5 and a fourth MOSFET M6 are matched with each other and configured in the CMOS logarithmic current generator circuit 300 as a second MOSFET pair biased in a weak inversion region to provide a second function generator core cell 320. A fifth MOSFET M7 is connected to a source voltage VSS and the first function generator core cell 310, the fifth MOSFET M7 contributing to an output current Iout of the CMOS logarithmic current generator circuit 300. A sixth MOSFET M8 connected to the source voltage VSS and the second function generator core cell 320, the sixth MOSFET M8 contributing to the output current Iout of the CMOS logarithmic current generator circuit 300.
Also, in the CMOS logarithmic current generator 300, a seventh MOSFET M4 is in operable communication with the first function generator core cell 310, the seventh MOSFET M4 providing an input current IX to the CMOS logarithmic current generator circuit 300 to convert an input current IX to a first voltage VA. An eighth MOSFET M3 in operable is communication with the second function generator core cell 320, the eighth MOSFET M3 providing an input current IY to the CMOS logarithmic current generator circuit 300 to convert the input current IY to a second voltage VB.
Further, the first function generator core cell 310 and the second function generator core cell 320 have a biasing current Ib that varies based upon the first voltage VA and the second voltage VB applied to the first function generator core cell 310 and the second function generator core cell 320, the first voltage VA being determined by the input current IX and the second voltage VB being determined by the input current IY, and the CMOS logarithmic current generator circuit 300 provides the output current Iout based upon a current mode logarithmic function defined by the relation:




  
    
      
        
          I
          out
        
        =
        
          2
          ⁢
          
            
          
          ⁢
          
            
              I
              b
            
            ·
            
              
                ln
                ⁡
                
                  (
                  
                    
                      I
                      Y
                    
                    
                      I
                      X
                    
                  
                  )
                
              
              .
            
          
        
      
    
    
      
        (
        
          7
          ⁢
          
            
          
          ⁢
          A
        
        )
      
    
  




The drain current of transistors M2 and M6 are given by relations (8) and (9), respectively:




  
    
      
        
          
            I
            2
          
          =
          
            
              I
              b
            
            ·
            
              exp
              ⁡
              
                [
                
                  
                    (
                    
                      
                        V
                        A
                      
                      -
                      
                        V
                        B
                      
                    
                    )
                  
                  
                    nU
                    T
                  
                
                ]
              
            
          
        
        ,
        
          
        
        ⁢
        and
      
    
    
      
        (
        8
        )
      
    
  
  
    
      
        
          I
          6
        
        =
        
          
            I
            b
          
          ·
          
            
              exp
              ⁡
              
                [
                
                  
                    (
                    
                      
                        V
                        B
                      
                      -
                      
                        V
                        A
                      
                    
                    )
                  
                  
                    nU
                    T
                  
                
                ]
              
            
            .
          
        
      
    
    
      
        (
        9
        )
      
    
  




Equation relation (9) can be rewritten as:





  
    
      
        
          I
          6
        
        =
        
          
            I
            b
          
          ·
          
            
              exp
              ⁡
              
                [
                
                  
                    -
                    
                      (
                      
                        
                          V
                          A
                        
                        -
                        
                          V
                          B
                        
                      
                      )
                    
                  
                  
                    nU
                    T
                  
                
                ]
              
            
            .
          
        
      
    
    
      
        (
        10
        )
      
    
  




The drain current for transistor M8 is the same as the drain current of M6 and, therefore:

Iout=I2−I8=I2−I6.  (11)

Combining relations (8), (10) and (11), the output current is given by:





  
    
      
        
          I
          out
        
        =
        
          
            
              I
              b
            
            [
            
              
                exp
                ⁡
                
                  [
                  
                    
                      (
                      
                        
                          V
                          A
                        
                        -
                        
                          V
                          B
                        
                      
                      )
                    
                    
                      nU
                      T
                    
                  
                  ]
                
              
              -
              
                exp
                ⁡
                
                  [
                  
                    
                      -
                      
                        (
                        
                          
                            V
                            A
                          
                          -
                          
                            V
                            B
                          
                        
                        )
                      
                    
                    
                      nU
                      T
                    
                  
                  ]
                
              
            
            ]
          
          .
        
      
    
    
      
        (
        12
        )
      
    
  




Using relation (4) and with the quantity





  
    
      [
      
        
          (
          
            
              V
              A
            
            -
            
              V
              B
            
          
          )
        
        
          nU
          T
        
      
      ]
    
    ⪡
    1
  
  ,




then relation (12) can be written as:





  
    
      
        
          I
          out
        
        =
        
          2
          ⁢
          
            
          
          ⁢
          
            
              I
              b
            
            ·
            
              
                [
                
                  
                    (
                    
                      
                        V
                        A
                      
                      -
                      
                        V
                        B
                      
                    
                    )
                  
                  
                    nU
                    T
                  
                
                ]
              
              .
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




Transistors M3 and M4 are used to convert the input currents Iy and Ix to voltages VB and VA, respectively, in logarithmic form as shown in relations (14) and (15):





  
    
      
        
          
            V
            A
          
          =
          
            
              
                V
                DD
              
              -
              
                V
                
                  sg
                  ⁢
                  4
                
              
            
            =
            
              
                V
                DD
              
              -
              
                
                  nU
                  T
                
                ⁢
                
                  
                
                ⁢
                
                  ln
                  ⁡
                  
                    (
                    
                      
                        I
                        X
                      
                      
                        I
                        Do
                      
                    
                    )
                  
                
              
            
          
        
        ,
        
          

        
        ⁢
        and
      
    
    
      
        (
        14
        )
      
    
  
  
    
      
        
          V
          B
        
        =
        
          
            
              V
              DD
            
            -
            
              V
              
                sg
                ⁢
                3
              
            
          
          =
          
            
              V
              DD
            
            -
            
              
                nU
                T
              
              ⁢
              
                
              
              ⁢
              
                
                  ln
                  ⁡
                  
                    (
                    
                      
                        I
                        Y
                      
                      
                        I
                        Do
                      
                    
                    )
                  
                
                .
              
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




Combining relations (15) and (14) provides:





  
    
      
        
          [
          
            
              (
              
                
                  V
                  A
                
                -
                
                  V
                  B
                
              
              )
            
            
              nU
              T
            
          
          ]
        
        =
        
          
            ln
            ⁡
            
              (
              
                
                  I
                  Y
                
                
                  I
                  X
                
              
              )
            
          
          .
        
      
    
    
      
        (
        16
        )
      
    
  




Combining relations (16) and (13), the output current Iout is given by:





  
    
      
        
          I
          out
        
        =
        
          2
          ⁢
          
            
          
          ⁢
          
            
              I
              b
            
            ·
            
              
                ln
                ⁡
                
                  (
                  
                    
                      I
                      Y
                    
                    
                      I
                      X
                    
                  
                  )
                
              
              .
            
          
        
      
    
    
      
        (
        17
        )
      
    
  




Relation (17) is a current-mode logarithmic function. Keeping the current IX constant or substantially constant provides a means for controlling a gain of the output current Iout by the bias current Ib and a means for implementing the output current Iout as being proportional to the logarithm of IY. Also, keeping the current IY constant or substantially constant provides a means for implementing the function




  
    Log
    (
    
      1
      X
    
    )
  
  .




Further, to assure the metal-oxide semiconductor (MOS) operates in a weak inversion forward saturation, the conditions ID≦ID0, and VDS≧4UT must be satisfied, for example.
FIG. 4 is a layout 400 of an embodiment of the CMOS logarithmic current generator circuit 300. The layout and post layout simulation for an embodiment of a CMOS logarithmic current generator circuit was carried out using a Tanner tool in 0.35 μm 2p4m Taiwan Semiconductor Manufacturing Company (TSMC) process. The layout 400 of the embodiment of the CMOS logarithmic current generator circuit 300 is shown in FIG. 4. The simulation results were obtained for Ib=30 nA, Ix=125 nA and VDD=−VSS=0.5V. The transistors' aspect ratios in the embodiment of the CMOS logarithmic current generator circuit 300 in the layout 400 are listed in Table 1.







TABLE 1







Aspect Ratios of Transistors










Transistor
Aspect Ratios width/length (W/L)







M1-M2
1.4 μm/0.35 μm



M3-M4
6.3 μm/0.35 μm



M5-M6
1.4 μm/0.35 μm



M7-M8
1 μm/1 μm 










The output current was measured by forcing it through a grounded load RL=1 kΩ. The current Ix=125 nA, and the input current Iy was varied from 20 nA to 400 nA. The measured output dynamic range is around 150 nA. The simulated and calculated results are shown in plot 500 of FIG. 5 which uses a log scale. The plot 500 shows that the simulated result is in substantial agreement with the theory and confirms the functionality of the CMOS logarithmic current generator circuit design. Moreover, the plot 500 shows the output current is zero for Iy=Ix=125 nA. It was found that the maximum linearity error is 4% and the maximum power consumption is 0.3 μW.
The CMOS logarithmic current generator circuit was simulated for different values of the bias current Ib and the corresponding output current is shown in plot 600 of FIG. 6. It is evident from the plot 600 that the circuit gain is controllable.
The temperature insensitivity of the CMOS logarithmic current generator circuit design has been confirmed by simulation. The temperature was varied from −25° C. to +75° C. The output current of the CMOS logarithmic current generator circuit was normalized to its current at T=+25° C. Plot 700 shows simulation results in FIG. 7. It is clear from the plot 700 that the output current is substantially insensitive to temperature.
The circuit transient response of the CMOS logarithmic current generator circuit was also found for a triangular signal shifted by a 40 nA direct current (DC) component. The simulation result shown in plot 800 of FIG. 8 confirms the functionality of the CMOS logarithmic current generator circuit. The CMOS logarithmic current generator circuit was also simulated for frequency response. The −3 dB bandwidth is found to be 5.7 MHz as shown in plot 900 of FIG. 9. The CMOS logarithmic current generator circuit can be used to implement for




  Log
  (
  
    1
    X
  
  )




at a constant or substantially constant current IY. Simulation result for this function is shown in plot 1000 of FIG. 10.

Simulation for noise analysis on the CMOS logarithmic current generator circuit was carried out. The equivalent noise at the input terminal is shown in plot 1100 of FIG. 11. The equivalent noise at the output terminal is shown in plot 1200 of FIG. 12. The simulation was carried out with the input DC and small signals equal to 100 nA and 50 nA, respectively, and also a 1 kΩ resistor was attached to the output as a load, for example. It is evident from the plots 1100 and 1200 that noise suppression can be achieved by around 50%.
The performance of the CMOS logarithmic current generator design is summarized in Table 2. It is apparent from the Table 2 that the CMOS logarithmic current generator circuit design has parameters and parametric features that can address the various problems previously outlined as can be present in existing types of CMOS current-mode logarithmic circuits.







TABLE 2







Performance of the CMOS Logarithmic Current Generator










Parameter
CMOS Logarithmic Current Generator















Technology
0.35
μm










(Process)
CMOS



Operation
Sub threshold











Region





Voltage
±0.5
V



Supply










Input\output
Current-current











Power
0.3
μW



dissipation










Gain
Yes











controllability












True for
Satisfied











x ≧ 1 or





x < 1










Temperature
Not sensitive










Embodiments of CMOS logarithmic current generator circuits can produce a relatively highly accurate logarithmic function for any value of Iy larger or smaller than Ix. The performance of the CMOS logarithmic current generator circuit has been verified using Tanner Tools with a 0.35 μm CMOS process. The CMOS logarithmic current generator circuit typically consumes around 0.3 μW and has a maximum linearity error of at or about 4% and −3 dB of 3.4 MHz, for example. The CMOS logarithmic current generator circuit can therefore be a useful building block in many analog signal processing applications, for example.
It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.

## Claims

1. A complimentary metal-oxide semiconductor (CMOS) logarithmic current generator circuit, comprising:
a first metal-oxide semiconductor field-effect transistor (MOSFET) and a second MOSFET matched with each other and configured in the (CMOS) logarithmic current generator circuit as a first MOSFET pair biased in a weak inversion region to provide a first function generator core cell;
a third MOSFET and a fourth MOSFET matched with each other and configured in the (CMOS) logarithmic current generator circuit as a second MOSFET pair biased in the weak inversion region to provide a second function generator core cell;
a fifth MOSFET connected to a source voltage and the first function generator core cell, the fifth MOSFET contributing to an output current Iout of the CMOS logarithmic current generator circuit;
a sixth MOSFET connected to the source voltage and the second function generator core cell, the sixth MOSFET contributing to the output current Iout of the CMOS logarithmic current generator circuit;
a seventh MOSFET in operable communication with the first function generator core cell, the seventh MOSFET providing an input current IX to the CMOS logarithmic current generator circuit to produce a corresponding first voltage VA; and
an eighth MOSFET in operable communication with the second function generator core cell, the eighth MOSFET providing an input current IY to the CMOS logarithmic current generator circuit to produce a corresponding second voltage VB,
wherein the first function generator core cell and the second function generator core cell are each biased by a biasing current Ib that varies based upon the first voltage VA and the second voltage VB applied to the first function generator core cell and the second function generator core cell, the first voltage VA being determined by the input current IX and the second voltage VB being determined by the input current IY, wherein the weak inversion region is defined by a current, I2, where





  
    
      I
      2
    
    =
    
      
        I
        b
      
      ·
      
        exp
        ⁡
        
          [
          
            
              (
              
                
                  V
                  A
                
                -
                
                  V
                  B
                
              
              )
            
            
              nU
              T
            
          
          ]
        
      
    
  
  ,



 where n is a weak inversion slope factor and UT=KbT/q, where Kb is Boltzmann's constant, q is electron charge, and T represents temperature, and
wherein the CMOS logarithmic current generator circuit provides the output current Iout based upon a current mode logarithmic function defined by the relation:





  
    I
    out
  
  =
  
    2
    ⁢
    
      
    
    ⁢
    
      
        I
        b
      
      ·
      
        
          ln
          (
          
            
              I
              Y
            
            
              I
              X
            
          
          )
        
        .

2. The CMOS logarithmic current generator circuit according to claim 1, wherein the output current Iout is proportional to a logarithm of the input current IY when the input current IX is maintained substantially constant.

3. The CMOS logarithmic current generator circuit according to claim 1, wherein a gain of the output current Iout is controlled by the biasing current Ib.

4. The CMOS logarithmic current generator circuit according to claim 1, wherein the first MOSFET pair has an aspect ratio of a width/length (WL) of 1.4 μm/0.35 μm, the second MOSFET pair has an aspect ratio (WL) of 1.4 μm/0.35 μm, the seventh Ix, MOSFET and the eighth Iy MOSFET have an aspect ratio (WL) of 6.3 μm/0.35 μm, and the fifth and sixth source voltage MOSFETS have an aspect ratio (WL) of 1 μm/1 μm.

5. A complimentary metal-oxide semiconductor (CMOS) logarithmic current generator circuit, comprising:
a first transistor pair biased in a weak inversion region, the first transistor pair comprising a first function generator core cell;
a second transistor pair biased in the weak inversion region, the second transistor pair comprising a second function generator core cell;
a first input current transistor in operable communication with the first function generator core cell, the first input current transistor providing a first input current IX to the CMOS logarithmic current generator circuit to produce a corresponding first voltage VA; and
a second input current transistor in operable communication with the second function generator core cell, the second input current transistor providing a second input current IY to the CMOS logarithmic current generator circuit to produce a corresponding second voltage VB,
wherein the first function generator core cell and the second function generator core cell are each biased by a biasing current Ib that varies based upon the first voltage VA and the second voltage VB applied to the first function generator core cell and the second function generator core cell, the first voltage VA being determined by the first input current IX and the second voltage VB being determined by the second input current IY, wherein the weak inversion region is defined by a current, I2, where





  
    
      I
      2
    
    =
    
      
        I
        b
      
      ·
      
        exp
        ⁡
        
          [
          
            
              (
              
                
                  V
                  A
                
                -
                
                  V
                  B
                
              
              )
            
            
              nU
              T
            
          
          ]
        
      
    
  
  ,



 where n is a weak inversion slope factor and UT=KbT/q, where Kb is Boltzmann's constant, q is electron charge, and T represents temperature, and
wherein the CMOS logarithmic current generator circuit provides an output current Iout based upon a current mode logarithmic function defined by the relation:





  
    I
    out
  
  =
  
    2
    ⁢
    
      
    
    ⁢
    
      
        I
        b
      
      ·
      
        
          ln
          (
          
            
              I
              Y
            
            
              I
              X
            
          
          )
        
        .

6. The CMOS logarithmic current generator circuit according to claim 5, wherein the output current Iout is proportional to a logarithm of the second input current IY when the first input current X is maintained substantially constant.

7. The CMOS logarithmic current generator circuit according to claim 5, wherein the first and second transistor pairs and the first and second input current transistors comprise metal-oxide semiconductor field-effect transistor (MOSFET) transistors.

8. The CMOS logarithmic current generator circuit according to claim 5, further comprising:
a first source voltage transistor connected to a source voltage and the first function generator core cell, the first source voltage transistor contributing to the output current Iout of the CMOS logarithmic current generator circuit; and
a second source voltage transistor connected to the source voltage and the second function generator core cell, the second source voltage transistor contributing to the output current Iout of the CMOS logarithmic current generator circuit.

9. The CMOS logarithmic current generator circuit according to claim 8, wherein the first and second transistor pairs, the first and second input current transistors and the first and second source voltage transistors comprise metal-oxide semiconductor field-effect transistor (MOSFET) transistors.

10. The CMOS logarithmic current generator circuit according to claim 5, wherein a gain of the output current Iout is controlled by the biasing current Ib.

11. A method for generating a logarithmic current, comprising the steps of:
biasing a first transistor pair comprising a first function generator core cell in a weak inversion region;
biasing a second transistor pair comprising a second function generator core cell in the weak inversion region;
receiving a first input current IX by a complimentary metal-oxide semiconductor (CMOS) logarithmic current generator circuit, the CMOS logarithmic current generator circuit comprising the first and second function generator core cells, and producing a corresponding a first voltage VA;
receiving a second input current IY by the CMOS logarithmic current generator circuit and producing a corresponding second voltage VB;
generating a biasing current Ib, that varies based upon the first voltage VA and the second voltage VB applied to the first function generator core cell and the second function generator core cell, the first voltage VA being determined by the first input current IX and the second voltage VB being determined by the second input current IY, wherein the weak inversion region is defined by a current, I2, where





  
    
      I
      2
    
    =
    
      
        I
        b
      
      ·
      
        exp
        ⁡
        
          [
          
            
              (
              
                
                  V
                  A
                
                -
                
                  V
                  B
                
              
              )
            
            
              nU
              T
            
          
          ]
        
      
    
  
  ,



 where n is a weak inversion slope factor and UT=KbT q, where Kb is Boltzmann's constant, q is electron charge, and T represents temperature; and
providing by the CMOS logarithmic current generator circuit an output current Iout based upon a current mode logarithmic function defined by the relation:





  
    I
    out
  
  =
  
    2
    ⁢
    
      
    
    ⁢
    
      
        I
        b
      
      ·
      
        
          ln
          (
          
            
              I
              Y
            
            
              I
              X
            
          
          )
        
        .

12. The method for generating a logarithmic current according to claim 11, further comprising the step of:
maintaining the first input current X to the CMOS logarithmic current generator circuit substantially constant,
wherein the output current Iout is proportional to a logarithm of the second input current IY when the first input current IX is maintained substantially constant.

13. The method for generating a logarithmic current according to claim 11, further comprising the step of:
controlling a gain of the output current Iout by the biasing current Ib.

14. The method for generating a logarithmic current according to claim 11, wherein the CMOS logarithmic current generator circuit comprises metal-oxide semiconductor field-effect transistor (MOSFET) transistors.