# Patent

## Title
Digitally tuned capacitors with tapered and reconfigurable quality factors

## Abstract

The present disclosure describes tuning capacitors with tapered and reconfigurable quality factors. Digitally tuned capacitors (DTCs) that provide a variable quality factor (Q) while maintaining a constant or near constant capacitance as well as DTCs that provide one or more Q values in a tapered distribution while maintaining a constant or near constant capacitance are described. The present disclosure also describes DTCs that provide one or more capacitances in a tapered distribution and one or more Q values in a tapered distribution.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
The present application is a continuation-in-part of U.S. patent application Ser. No. 12/735,954 filed on Aug. 27, 2010, incorporated herein by reference in its entirety, which application is a 371 National Stage Entry of PCT Patent International Application No. PCT/US09/01358 filed on Mar. 2, 2009, entitled “Method and Apparatus for use in Digitally Tuning a Capacitor in an Integrated Circuit Device”, which PCT Application No. PCT/US09/01358 claims the benefit under 35 U.S.C. section 119(e) of provisional Application No. 61/067,634 filed Feb. 28, 2008.


FIELD
The present disclosure relates to tuning of capacitors. More particularly, the disclosure relates to digitally tuned capacitors with tapered and reconfigurable quality factors.
SUMMARY
According to a first aspect of the present disclosure, a digitally tuned capacitor (DTC) adapted for use in a circuit device is provided, the DTC comprising: a first terminal; a second terminal; and a plurality of bit stages in parallel between the first terminal and the second terminal, each bit stage comprising at least one switch connected with at least one capacitor, wherein: the plurality of bit stages is configured to be controlled by a numeric control word in binary representation, each bit of the numeric control word representing a switching state of one bit stage in the plurality of bit stages, wherein the switching state is either an ON state or an OFF state, and states of the DTC with same number of ON states is configured to provide a variable quality factor while maintaining a constant or near constant capacitance around a fixed level.
According to a second aspect of the present disclosure, a method of digitally tuning a tunable capacitor in a circuit device is provided, the method comprising: providing a first terminal; providing a second terminal; providing a plurality of bit stages connected in parallel between the first terminal and the second terminal, each bit stage comprising at least one switch connected with at least one capacitor; applying a numeric control word in binary representation to the plurality of bit stages, each bit of the numeric control word representing a switching state of one bit stage in the plurality of bit stages, wherein the switching state is either an ON state or an OFF state; selectively controlling capacitance between the first terminal and the second terminal based on switching states of each bit stage in the plurality of bit stages; and configuring states of the tunable capacitor with same number of ON states to provide a variable quality factor while maintaining a constant or near constant capacitance around a fixed level.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.



BRIEF DESCRIPTION OF DRAWINGS
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
FIG. 1 shows a simplified schematic representation of an implementation of a digitally tuned capacitor (DTC).
FIG. 2 shows an equivalent circuit of the DTC shown in FIG. 1.
FIG. 3A shows a circuital arrangement of a stack of transistors connected with a capacitor. FIG. 3B shows an equivalent circuit of the circuital arrangement of FIG. 3A when the transistors in the stack of transistors are in an ON state.
FIG. 4 shows an implementation of a DTC using the circuital arrangement of FIG. 3A.
FIG. 5 shows a system that comprises a DTC coupled with a controller.
FIG. 6 depicts an implementation of a DTC with constant quality factor Q. Exemplary values for coefficients An and Bn for the DTC are provided, where the coefficients scale values of capacitances and resistances, respectively.
FIGS. 7A and 7B show exemplary monotonic quality factors as a function of state of a DTC. Specifically, FIG. 7A shows a max-to-min tapered-Q whereas FIG. 7B shows a min-to-max tapered-Q.
FIG. 8 depicts exemplary values for coefficients An and Bn for a DTC.
FIGS. 9A and 9B show a parallel-to-series conversion. FIG. 9A shows a parallel circuit. FIG. 9B shows a series circuit equivalent of the parallel circuit of FIG. 9A.
FIGS. 10 and 11 show DTCs that provide a variable Q while maintaining the same capacitance, in accordance with an embodiment of the present disclosure.
FIGS. 12A-12E show plots of capacitances and Q values as a function of state of a DTC. Specifically, FIGS. 12A-12D show the capacitances and Q values for a DTC with five transistor stacks, where one, two, three, and four transistor stacks are in an ON state, respectively. FIG. 12E shows the capacitances and Q values for a DTC with five transistor stacks for a zero-bit case (all transistors are in an OFF state) and a penta-bit case (all transistor stacks are in an ON state).
FIG. 13 shows capacitances and Q values for a thermometer coded DTC with tapered Q values.
FIG. 14 shows a plot of number of different configurations of Q value at each possible capacitance value for a five-bit DTC, in accordance with an embodiment of the present disclosure.
FIG. 15 shows a plot of number of different configurations of Q value at each possible capacitance value for an eight-bit DTC, in accordance to with embodiment of the present disclosure.
FIG. 16 shows a plot of number of different configurations of Q value at each possible capacitance value for DTCs with two-bit, three-bit, four-bit, five-bit, six-bit, seven-bit, and eight-bit configurations, in accordance with several embodiments of the present disclosure.
FIG. 17 shows an embodiment of a DTC that comprises capacitors connected with switching devices. Any one, plurality, or all of the capacitors and connected switching device pairs, which form a bit stage, shown in FIG. 17 can be implemented using a voltage or current dependent variable capacitor.
FIGS. 18 and 19 show additional embodiments of DTCs that comprise fixed and variable capacitors.
FIG. 20 is a simplified schematic of an SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, where an accumulated charge sink (ACS) terminal is coupled to a gate terminal via a diode.



DETAILED DESCRIPTION
As used in the present disclosure, the terms “tunable”, “tuned”, and “tuning” can be used interchangeably with the terms “adjustable”, “variable”, “programmable”, and “configurable”. The term “digitally tuned” used in “digitally tuned capacitor” (DTC) refers to tuning (varying) of capacitor values in discrete increments. For example, a digitally tuned capacitor can be implemented such that its possible capacitance values are C through nC in steps of C (i.e., the digitally tuned capacitor can have capacitance values of C, 2C, 3C, . . . , (n−1)C, and nC). As another example, a digitally tuned capacitor can be implemented with no set pattern in its possible capacitance values (e.g., 0.5C, C, 6C, 100C, and 125C). Possible capacitance values of the digitally tuned capacitor can be adjusted as necessary for a desired application.
As used in the present disclosure, a “state” associated with a DTC provides a manner for identifying which combination of switching devices in the DTC are ON or OFF.
According to several embodiments of the present disclosure, a tunable capacitor can be implemented through connections between capacitors and switching devices. Depending on state (i.e., ON or OFF) of each switching device in the tunable capacitor, capacitance and/or quality factor (Q) of the tunable capacitor can be tuned. The on or off nature of such control of the capacitance can lead to better control of performance, such as, for instance, in terms of Q value and signal linearity. As will be shown later in the present disclosure, some states of the tunable capacitor can be associated with a common capacitance value but be configured for different Q, or vice versa, where each state involves a particular combination of ON or OFF switching devices in the tunable capacitor. In some embodiments, the tunable capacitor can be implemented using devices that are inherently variable capacitors, such as voltage-controlled varactors, metal-oxide-semiconductor (MOS) capacitors, and barium strontium titanate (BST) films. An inherently variable capacitor can be (but need not be) connected to one or more switching devices.
Control of the states of the switching devices can be performed via signals applied to the switching devices by a controller. The controller is generally a digital device, such as a microprocessor or a digital signal processor. For purposes of discussion, the switching devices will be assumed to be field effect transistors (FETs). However, the present disclosure can also utilize other switching devices such as accumulated charge control field effect transistors, microelectromechanical system (MEMS) switches, diodes, diode connected bipolar junction transistors (BJTs), and other switching devices identifiable by a person skilled in the art.
According to several embodiments of the present disclosure, a tunable capacitor can comprise capacitors, where each capacitor is connected with a stack of switches. By way of example and not of limitation, consider a stack of transistors. Reliability considerations of transistors affect maximum amount of voltage, also referred to as a breakdown voltage or withstand voltage, that can be placed from drain to source of any particular transistor. Specifically, above the withstand voltage, the transistors used in implementing a system can break down, leaving the system unable to accomplish an intended purpose. A transistor stack, where two or more transistors are serially connected, can be utilized to allow the serially connected transistors to share a voltage applied to the transistor stack. For example, if each transistor has a withstand voltage of around 3 V, then a stack of five transistors would ideally be expected to have a withstand voltage of around 15 V. Consequently, a higher number of stacked transistors can be used in systems that involve higher voltages in order to withstand these higher voltages. Losses in the transistors due to various parasitics, such as parasitic capacitances that conduct current in various (e.g., including undesirable) directions, would generally lead to a withstand voltage lower than the expected 15 V. In a field effect transistor, for instance, the withstand voltage of an individual FET can be increased by increasing gate length, although this leads to occupation of more area on a chip for the individual FET and also to a generally slower switching FET.
In general, device reliability is a concern when switches are OFF. When the switches are OFF, the switches need to withstand voltage applied to the switches. Consequently, with a stack of switches, peak voltage of an applied signal, such as a radio frequency (RF) signal, can be higher than in the case with only one switch since voltage of the applied signal can be shared across each switch in the stack.
It should be noted that although lumped elements (e.g., discrete resistors, capacitors, and inductors) are depicted throughout the present disclosure, the embodiments of the present disclosure to be described below can also utilize distributed elements. Specifically, resistances, capacitances, and inductances can be distributed throughout a circuital arrangement and thus can be generally measured per unit length (e.g., Ω/length, F/length, and H/length, respectively). For example, transmission line elements such as half-wavelength, quarter-wavelength, series and parallel stubs (open circuit or short circuit stubs), and resonant stubs can also be utilized to provide resistances and reactances to the circuital arrangement. It should be noted that the various elements (either lumped or distributed) can be on-chip or off-chip.
FIG. 1 shows a simplified schematic representation of an implementation of a digitally tuned capacitor (DTC). FIG. 2 is an equivalent circuit showing ON resistances RON and OFF capacitances COFF associated with switching transistors of the DTC shown in FIG. 1. Additional examples of DTCs are shown in U.S. patent application Ser. No. 12/735,954, incorporated herein by reference in its entirety. Both RON and COFF are functions of size (e.g., width) of the switching transistors.
More specifically, FIGS. 1 and 2 show a representation of a five-bit DTC (100) along with an exemplary equivalent circuit model (200) of the representation, respectively. The five-bit DTC (100) can be designed to exhibit a constant Q value for each bit stage using binary coding. This constant Q value is achieved by first designing an initial bit stage b0 (102, 202) that provides a set quality factor. For reasons that will be apparent later in the disclosure, the initial bit stage b0 (102, 202) can also be referred to as a unit cell.
Then, for the case of binary coding, in order to achieve the same Q in a next bit stage b1 (104, 204), value of CMIM (208) and device periphery of the unit cell (102, 202) are both doubled. Doubling device periphery (specifically, doubling periphery of a transistor) effectively halves RON (210). Hence, constant RONCMIM can be maintained between bit stages b0 (102, 202) and b1 (104, 204). Components in bit stage b1 (104, 204) can be similarly scaled (value of CMIM and device periphery are doubled) to achieve bit stage b2 (106, 206). Similar CMIM and device periphery doubling occurs for bit stages b3 and b4.
As previously mentioned, the initial bit stage b0 (102, 202) can also be referred to as a unit cell. For example, bit stage b1 (104, 204) can be implemented using two initial bit stages b0 (102, 202) in parallel and similarly bit stage b2 (106, 206) can be implemented using four initial bit stages b0 (102, 202) in parallel.
Type of capacitor utilized in implementing the DTC (100, 200) is generally chosen such that the capacitor or capacitors used to implement CMIM (208 in FIG. 2) in bit stage b0 (202 in FIG. 2), 2CMIM in bit stage b1 (204 in FIG. 2), and so forth can withstand possible voltages to be applied at terminals RF− and RF+ across the DTC (100, 200). Although a metal-insulator-metal (MIM) capacitor, denoted as CMIM, is utilized in this disclosure for discussion purposes, other types of capacitors identifiable by a person skilled in the art can be utilized in place of or in combination with the MIM capacitor.
It should be noted that implementation of the DTC is dependent on application. For example, in applications where a maximized Q is desirable, the maximized Q can be associated with a minimization of ON resistance RON of a transistor, which can be obtained through maximization of transistor periphery as described above. Examples of constraints on minimizing RON include chip area and minimum required capacitance of the DTC.
With respect to chip area, a smaller RON can be associated with a larger transistor, and thus minimization of RON through maximization of transistor periphery is dependent on amount of chip area available. With respect to minimum required capacitance of the DTC, larger devices are generally associated with larger parasitic capacitances. Consequently, larger devices are also generally associated with a larger minimum capacitance state of the DTC, denoted as Cmin. For example, if a Cmin state of 0.5 pF is required of the DTC based on system specifications, using devices (such as transistors) that are too large may cause the Cmin state to be higher than 0.5 pF (e.g., 1 pF). Consequently, in the example of maximizing Q, a tradeoff exists between maximum Q possible with consideration to chip area and minimum capacitance possible.
The DTC shown in FIGS. 1 and 2 can function as a variable reactance in an impedance matching network. Since quality factor Q of capacitors is given by Q=1/(ωRC), where ω is (angular) frequency of a signal applied to the capacitor, a constant RONCMIM for each bit stage can be specified to achieve a constant quality factor Q for each bit stage.
In practice, voltage seen across the digitally tuned capacitor is proportional to Q. Consequently, in an impedance matching network, a DTC with a higher Q generally has higher voltages across the DTC than a DTC with a lower Q. In order to accommodate the higher voltages due to higher Q values, the DTC can comprise higher transistor stacking, which leads to occupation of more chip area.
As used in this disclosure, a “state” associated with a DTC provides a manner for identifying which combination of transistors are ON or OFF. The bit stages b0 (102, 202) through b4 form a numeric control word in binary representation that determines the state of the DTC. Each control word is associated with a plurality of control signals that turns transistors in the DTC on or off.
For instance, Table 1 below shows possible states b4b3b2b1b0 of the five-bit DTC shown in FIGS. 1 and 2. A b0 of ‘0’ can refer to a situation where a zeroth transistor (102 in FIG. 1) is turned OFF while in this case a b0 of ‘1’ would refer to a situation where the zeroth transistor (102 in FIG. 1) is turned ON, or vice versa (i.e., a ‘0’ can be associated with a transistor being turned ON while a ‘1’ can be associated with a transistor being turned OFF). As an example, a state is given by b4b3b2b1b0, so a state or numeric control word of 01001 signifies that a fourth, second (106 in FIG. 1), and first transistor (104 in FIG. 1) are in a first state while a third and zeroth transistor (102 in FIG. 1) are in a second state. It should be noted that a bit b0 can be referred to as a least significant bit (LSB) and a bit b4 can be referred to as a most significant bit (MSB), or vice versa. Such a designation is for convenience in discussion and is not necessarily associated with capacitance value, transistor size, and/or quality factor associated with a particular bit stage.







TABLE 1







Possible states of a five-bit configuration of a DTC














State
b4
b3
b2
b1
b0


















0
0
0
0
0
0



1
0
0
0
0
1



2
0
0
0
1
0



3
0
0
0
1
1



4
0
0
1
0
0



5
0
0
1
0
1



6
0
0
1
1
0



7
0
0
1
1
1



8
0
1
0
0
0



9
0
1
0
0
1



10
0
1
0
1
0



11
0
1
0
1
1



12
0
1
1
0
0



13
0
1
1
0
1



14
0
1
1
1
0



15
0
1
1
1
1



16
1
0
0
0
0



17
1
0
0
0
1



18
1
0
0
1
0



19
1
0
0
1
1



20
1
0
1
0
0



21
1
0
1
0
1



22
1
0
1
1
0



23
1
0
1
1
1



24
1
1
0
0
0



25
1
1
0
0
1



26
1
1
0
1
0



27
1
1
0
1
1



28
1
1
1
0
0



29
1
1
1
0
1



30
1
1
1
1
0



31
1
1
1
1
1










As used in the present disclosure, a “lower” state can refer to a state whose corresponding decimal value is lower than that of a “higher” state. For example, in the five-bit DTC, a state 00000 (corresponding to decimal value 0) can be referred to as the lowest state while a state 11111 (corresponding to decimal value 31) can be referred to as the highest state.
As mentioned above, a unit cell of a DTC can comprise one transistor connected with a capacitor, where state of the transistor determines whether the capacitor contributes to capacitance of the DTC (i.e., switching of the capacitance in or out of the DTC). The unit cell can also comprise a stack of transistors connected with the capacitor, where state of each transistor in the stack of transistors determines whether the capacitor contributes to capacitance of the DTC.
FIG. 3A shows a circuital arrangement of a stack of n transistors (306, 308, 310, 312, 314, 316) connected with a capacitor (320). Components in the schematic of FIG. 3A can be utilized as a unit cell (102 in FIG. 1, 202 in FIG. 2) of a DTC. The unit cell can comprise a stack of transistors (306, 308, 310, 312, 314, 316) coupled with a first terminal RF (350) on one end and coupled with a capacitor CMIM (320) on another end. A resistance RMIM (322) represents an equivalent series resistance (ESR) of the capacitor CMIM (320). The capacitor CMIM (320) is coupled with a second terminal RF+ (352). Designation of positive sign and negative sign to the terminals (350, 352) is arbitrary and does not necessarily indicate relative polarity of the terminals (350, 352). Furthermore, either of the terminals (350, 352) may be coupled to ground.
For discussion purposes, consider the case where the stack of transistors (306, 308, 310, 312, 314, 316) is a stack of field effect transistors (FETs). The unit cell can also comprise gate resistors RG coupled to a gate of each of the FETs (306, 308, 310, 312, 314, 316). A control bit b0 (326) applied to the FETs (306, 308, 310, 312, 314, 316) through the gate resistors can control ON or OFF state of the FETs (306, 308, 310, 312, 314, 316) in the stack. Voltage at a node (328) is based on value of the control bit b0 (326). The unit cell can further comprise drain-to-source resistors RDS. The gate and drain-to-source resistors can aid in biasing their associated and corresponding FETs.
FIG. 3B shows an equivalent circuit of the circuital arrangement of FIG. 3A when the transistors are in an ON state. As with FIG. 3A, the equivalent circuit shown in FIG. 3B shows a stack of transistors (in an ON state) coupled to a first terminal RF (350) on one end and a capacitor CMIM (320) on another end. The capacitor CMIM (320) is depicted as a capacitor and its equivalent series resistance RMIM (322) and is coupled with a second terminal RF+ (352). In FIG. 3B, each of the transistors (306, 308, 310, 312, 314, 316 in FIG. 3A) in the stack can be represented by a resistor. Equivalent resistance of the stack can be collectively denoted as RON and referred to as ON resistance. In contrast, when the transistors in the stack are turned OFF (not shown in FIG. 3B), equivalent capacitance of the stack can be collectively denoted as COFF and referred to as OFF capacitance.
FIG. 4 shows an implementation of a DTC using the circuital arrangement of FIG. 3A, where the DTC is coupled to a first terminal RF (450) and a second terminal RF+ (452). As mentioned in FIG. 3A, the circuital arrangement of FIG. 3A can be utilized as a unit cell for building of the DTC. A first bit stage (402) can comprise the unit cell shown in FIG. 3A while subsequent bit stages can comprise a plurality of unit cells tied to a common control bit (e.g., b1 . . . bb-1). In the implementation shown in FIG. 4, along with scaling number of unit cells and capacitance (420) in each unit cell, gate resistances and drain-to-source resistances can also be scaled.
FIG. 5 shows a system that comprises a DTC (500) coupled with a controller (502). A digital control word CAPword (528) can be applied to the controller (502) in order to generate control bits configured to control ON or OFF state of transistors in the DTC (500). The DTC (500) can be tied to a first terminal RF (550) and a second terminal RF+ (552). Designation of positive sign and negative sign to the terminals (550, 552) is arbitrary and does not necessarily indicate relative polarity of the terminals (550, 552). Either of the terminals (550, 552) may be coupled to ground. As previously mentioned, the controller (502) is generally a digital device, such as a microprocessor or a digital signal processor.
Each of the DTCs shown in FIGS. 1, 2, 3A, 3B, and 4 can be utilized as the DTC (500) shown in FIG. 5. The DTCs shown in U.S. patent application Ser. No. 12/735,954, incorporated herein by reference in its entirety, can also be utilized in the system of FIG. 5. Furthermore, as used herein, the term “stack” includes both the case where a stack comprises only one device (e.g., a stack of one switch or transistor) as well as the case where the stack comprises a plurality of devices (e.g., a stack of multiple serially connected switches or transistors).
FIG. 6 illustrates a DTC (600) whose RONCMIM product stays constant, or more specifically (RON/Bn)(AnCMIM) stays constant, for each bit stage. In FIG. 6, a constant RONCMIM is achieved by setting coefficients An and Bn to 2n for all n. The DTC (600) has a constant Q for each bit stage, and the state of each bit stage determines the capacitance of the DTC (600). Such a combination of coefficients is known as binary coding and has been previously shown in FIGS. 1 and 2. A constant Q design can aid in minimizing signal loss while maximizing Q.
It should be noted that (RON/Bn)(AnCMIM) being constant can be achieved through other means aside from binary coding. For example, a case where An=Bn=constant for all possible n also keeps (RON/Bn)(AnCMIM) constant. However, the binary case generally involves less on-chip routing, which decreases parasitic capacitances and leads to less signal loss. Furthermore, the binary case can involve fewer drivers to drive RF states, so chip area may be conserved.
Maintaining constant RONCMIM, however, might not allow a designer to choose an optimal Q, for a fixed capacitance, for a particular application. In addition, use of a DTC (100, 200) that maintains constant RONCMIM throughout the bit stages (e.g., b0 (102, 202), b1 (104, 204), etc. shown in FIGS. 1 and 2) can also consume more chip area. For a bounded design space or area, Q may not be maximized in the case of constant RONCMIM.
Specifically, in a constant Q design where RONCMIM is constant, each bit stage scales linearly as previously discussed. For instance, as previously mentioned in the case of binary coding, to keep Q constant by doubling CMIM for successive bit stages, ON resistance in one bit stage is half the value of ON resistance of a next bit stage. In order to reduce ON resistance by half, device (transistor) area or periphery can be doubled. Consequently, the b1 bit stage (104, 204) shown in FIGS. 1 and 2 comprises an area around twice that of the area for the b0 bit stage (102, 202), the b2 bit stage (106, 206) comprises an area around four times that of the area of the b0 stage (102, 202), and so forth.
The constant Q design can lead to consumption of more area by the DTC than a tapered-Q approach, as will be discussed later in the present disclosure. For example, a constant RONCMIM may use a constant bit-to-bit stack height at each bit stage such that each bit stage can withstand voltage applied at terminals RF− and RF+, which can involve more chip area than the tapered-Q approach. Furthermore, higher Q is generally associated with higher voltages, which may require an increased stack height (and thus use of more chip area) to withstand these higher voltages.
Embodiments of the present disclosure are directed to a DTC that utilizes a variable RONCMIM to achieve a “tapered” quality factor for each bit stage. By way of example and not of limitation, binary and thermometer codes can be utilized to implement the DTC with tapered quality factor.
According to an embodiment of the present disclosure, a DTC with a variable RONCMIM between states can provide a reconfigurable Q while maintaining constant (or near constant) DTC capacitance C. As used herein, a “constant capacitance” between states also includes the case where capacitance between states is near constant (or close to equal), but not exactly equal. A person skilled in the art recognizes that due to issues such as, but not limited to, tolerances of components (e.g., capacitors), operating conditions (e.g., temperature and pressure), and parasitics associated with any component, actual value (e.g., actual capacitance value) can fluctuate about a nominal value. As previously noted, voltage seen across the DTC is proportional to the quality factor. Consequently, the DTC can be configured for a high Q, hence low loss, when peak voltages are not a concern. On the other hand, the DTC can be configured for a low Q when peak voltages are a concern. Such a DTC has numerous applications.
For example, DTCs at a constant DTC capacitance value C and with variable Q values can be used to adjust system bandwidths. A tuning bandwidth, which refers to a frequency range that a system passes through relatively unattenuated, can be adjusted based on quality factor of the DTC.
Consider a system with two receivers that utilizes a bandpass matching network, where capacitance in the bandpass matching network is provided by a DTC. Further, consider that both of the receivers have a center frequency of 1850 MHz, but one operates within a frequency range of 1800 MHz to 1900 MHz and the other operates within a frequency range of 1750 MHz to 1950 MHz. Then, the same bandpass matching network (i.e., the same LC element values), which comprises the DTC, can be used to tune both receivers.
For a DTC at a set capacitance value, difference between the bandpass network in each receiver will be in the Q value, which is reconfigurable. The bandpass network in the 1800-1900 MHz receiver will have a DTC with a capacitance value C but can be configured with a higher Q value while the bandpass network in the 1750-1950 MHz receiver will have the same capacitance value C but can be configured with a lower Q value. Specifically, when used to transform impedances, a high Q DTC (i.e., a DTC operating in a state of higher Q) can be used to tighten the tuning bandwidth while a low Q DTC (i.e., a DTC operating in a state of lower Q) can be used to widen the tuning bandwidth. Tradeoff between high versus low Q is that a DTC operating in a state with higher Q provides a narrower (tighter) bandwidth and generally adds less loss whereas a DTC operating in a state with lower Q provides more bandwidth and generally adds more loss.
FIGS. 7A and 7B show quality factor of a DTC as a function of state of the DTC. Graphs in FIGS. 7A and 7B show monotonic quality factors. However, the person skilled in the art will understand that other Q-varying mechanisms can be used that will result in a configurable quality factor. Additionally, different coding schemes (e.g., binary, thermometer, etc.) can be applied. For the sake of simplicity and by way of example only, a thermometer coding scheme will be referenced in several parts of the present disclosure.
As shown in FIGS. 7A and 7B, the tapered-Q approach has a maximum Q at one end of the capacitance tuning range, where this maximum Q can be higher than quality factor achieved in a constant Q design (e.g., RONCMIM remains a constant between states), and a minimum Q at the other end of the capacitance tuning range, where this minimum Q can be lower than that achieved in a constant Q design. According to several embodiments of the present disclosure, depending on application to which the DTC is to be applied, area utilized by each bit stage can be designed such that a particular set of Q values can be associated with different states of the DTC. As a result, a tapered-Q DTC may be designed to occupy less chip area than a constant-Q DTC since a tapered-Q DTC may use fewer transistors in one or more stacks than a constant-Q DTC.
Max-to-min tapered-Q, shown in FIG. 7A, can be utilized in high frequency applications where low capacitance values are generally utilized. MM-to-max tapered-Q, shown in FIG. 7B, can be utilized in low frequency applications where high capacitance values are generally utilized. One exemplary application is that of utilizing DTCs in an impedance matching network. It is well known that impedance of a capacitor is given by Z=1/(jωC), Consequently, for components to be matched by an impedance matching network of impedance Z, a higher operating frequency ωHI would utilize a lower DTC capacitance value CLO while a lower operating frequency ωLO would utilize a higher DTC capacitance value CHI, where ωHICLO=ωLOCHI since the impedance Z of the impedance matching network is the same in both cases.
As shown in FIGS. 7A and 7B, lower states can be designed to be associated with lower capacitance while higher states can be designed to be associated with higher capacitance. In a five-bit case, 00000 would generally be considered the lowest state while 11111 would generally be considered the highest state. In another embodiment, the lower states can be designed to be associated with higher capacitance while higher states can be designed to be associated with lower capacitance.
According to several embodiments of the present disclosure, a tapered quality factor allows configuration of the quality factor in designs bounded by the area of the devices. For example, the quality factor of a particular state can be maximized with consideration to area requirements. The tapered quality factor enables a tailoring of the quality factor response such that the quality factor can be maximized where it is needed most and minimized where it is needed least in the tuning application. Implementation of the tapered quality factor lends itself to less transistor stacking for bit stages where the quality factor is maximized. Specifically, the transistor stacks associated with an OFF state need to be of sufficient stacking in order to withstand the higher voltages generally associated with a higher quality factor. Less transistor stacking results in higher COFF since an effective COFF of an η transistor stack is given by COFF=(1/COFF1+1/COFF2+ . . . +1/COFFη)−1.
Consequently, by using a DTC with tapered quality factor (when compared with a DTC with constant quality factor), less stack height can be utilized to achieve the same voltage handling as in the case of a DTC with constant quality factor, as shown in the following expression




  
    
      
        
          η
          eff
        
        =
        
          η
          *
          
            (
            
              1
              +
              
                
                  C
                  OFF
                
                
                  C
                  MIM
                
              
            
            )
          
        
      
    
    
      
        (
        1
        )
      
    
  




where η is the transistor stack height and ηeff is the effective stack height.

For a given stack height η, effective stack height ηeff increases as COFF increases. In some bit stages, stack height can be reduced, which would lead to a reduction in the effective stack height ηeff if CMIM were to remain constant or increase. However, in the tapered-Q DTC, CMIM can be reduced as well. Consequently, even though stack height is reduced, the effective stack height and thus the voltage withstand of the switch can remain the same. As a result, tapered-Q DTC can reduce area consumption of the devices (such as relative to the constant-Q DTC) without necessarily reducing the voltage withstand.
When appropriately designed, less transistor stacking for the bit stage with the highest quality factor opens up more area for successive (or preceding) bit stages. For instance, if a bit stage associated with highest Q is the least significant bit (LSB), more area is opened for successive bit stages (i.e., bit stages after the LSB). Similarly, if a bit stage associated with highest Q is the most significant bit (MSB), more area is opened up for preceding bit stages (i.e., bit stages before the MSB).
As the quality factor decreases about its maximum, ON resistance RON can increase across the remaining bit stages, and therefore transistor peripheries can be reduced (since transistor periphery is inversely proportional to RON as previously mentioned). If the transistor peripheries were to become too small such that COFF in equation (1) above for the FET stack becomes too small to provide an adequate effective stack height ηeff to reliably sustain voltages seen by the DTC, then an additional device (such as an additional transistor) can be added to the stack to boost voltage handling capability. The area savings by maximizing quality factor for the first (last) bit generally outweigh any increases in stack height for successive (or preceding) stages, and thus there is a net area reduction due to utilization of a tapered quality factor for the DTC.
According to several embodiments of the present disclosure, a DTC can provide a fixed capacitance and a reconfigurable quality factor. Such an embodiment adds value at the application level in that a system that comprises such a DTC can be set to a particular state depending on whether higher Q should be used to achieve less loss or lower Q should be used to achieve lower voltage peaks (but associated with more loss). The DTC can also be configured for lower (higher) Q to achieve more (less) system bandwidth. In practice, end-use application would tune the DTC to find an optimal solution that maximizes voltage peaks (lowers loss) without exceeding reliability limits and achieves system bandwidth requirements.
According to several embodiments of the present disclosure, design of tapered-Q DTCs comprises obtaining CMIM and RON and their corresponding scaling coefficients An and Bn, as depicted for instance in FIG. 8. An exemplary method to acquire each of these values is provided as follows.
In a first step, independent variables are selected by a designer based on one or more applications under consideration. Table 2 below provides these independent variables.







TABLE 2







Independent variables








Independent Variables





fo
operating frequency


b
number of bits (number of bit stages)


n
incremental bit order (i.e., n = 0, 1, 2, . . . , b)


N
number of states


ηeff
effective stack height


C0
capacitance at state 0


CN
capacitance at state N


Q0
quality factor at state 0



(Qmin occurs at state 0 for min-to-max taper;



Qmax occurs at state 0 for max-to-min taper)


QN
quality factor at state N



(Qmin occurs at state N for max-to-min taper;



Qmax occurs at state N for min-to-max taper)


QMIM
MIM capacitor quality factor


QCoff
device off-capacitance quality factor


ron
unit device channel resistance


coff
unit device off-capacitance









Values for capacitances Cn where 0≦n≦b, with |CN−C0| being the capacitance tuning range of the DTC and n being a particular bit stage, are generally user or application specified. Values for unit device channel resistance ron and unit device channel off-capacitance coff are technology parameters fixed for a given process. Effective stack height ηeff of a bit stage of the DTC is determined (set) based on knowledge of maximum operating voltages to be applied to and/or withstood by each transistor device. For instance, for a DTC that must be capable of handling (withstanding) 30 V with each transistor device capable of operating up to a maximum of 3 V, the effective stack height ηeff can be selected to be at least 10.
It should be noted that ron and coff are ON resistance and OFF capacitance associated with a given technology. For instance, if ron=1 Ω-mm, then a 1 mm device has 1Ω of ON resistance. Similarly, if coff=1 pF-mm, then a 1 mm device has 1 pF of OFF capacitance. Control of values for ron and coff occurs through scaling size of the device. These parameters differ from RON and COFF described previously, which represent ON resistance and OFF capacitance of a particular bit stage (where the bit stage generally comprises stacked transistors).
Consider a DTC with b bit stages. For each bit stage n, a target capacitance Cn and target reactance Xn are given respectively by:




  
    
      
        
          
            
              
                C
                n
              
              =
              
                n
                *
                
                  (
                  
                    
                      
                        C
                        N
                      
                      -
                      
                        C
                        0
                      
                    
                    b
                  
                  )
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              <
              b
            
          
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        
          
            
              
                X
                n
              
              =
              
                1
                
                  j
                  ⁢
                  
                    
                  
                  ⁢
                  ω
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    n
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              <
              b
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




Angular frequency ω is given by ω=2πfo, where fo is the operation frequency of the DTC. It should be noted that Cn is evaluated for 0<n<b, e.g., not inclusive of state 0 and N, because C0 and CN are values set by the user or application.

Similarly, for a bit stage n, a target quality factor is given by the following recursive equation:




  
    
      
        
          
            
              
                Q
                n
              
              =
              
                
                  Q
                  
                    n
                    -
                    1
                  
                
                -
                
                  (
                  
                    
                      
                        Q
                        N
                      
                      -
                      
                        Q
                        0
                      
                    
                    b
                  
                  )
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              <
              
                b
                .
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




The following provides additional equations to be solved in obtaining CMIM, ron, An, and Bn:




  
    
      
        
          
            
              
                R
                Pn
              
              =
              
                
                
                  
                    Q
                    n
                  
                  *
                  
                    X
                    n
                  
                
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        5
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  C
                  n
                
              
              =
              
                
                  C
                  n
                
                -
                
                  C
                  
                    n
                    -
                    1
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        6
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  R
                  Pn
                
              
              =
              
                
                  (
                  
                    
                      1
                      
                        R
                        Pn
                      
                    
                    -
                    
                      1
                      
                        R
                        
                          Pn
                          -
                          1
                        
                      
                    
                  
                  )
                
                
                  -
                  1
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        7
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  Q
                  n
                
              
              =
              
                
                  ω
                  ·
                  
                    d
                    
                      R
                      Pn
                    
                  
                
                ⁢
                
                  d
                  
                    C
                    n
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        8
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  R
                  Sn
                
              
              =
              
                
                  d
                  
                    R
                    Pn
                  
                
                
                  (
                  
                    1
                    +
                    
                      d
                      
                        Q
                        n
                        2
                      
                    
                  
                  )
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        9
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  R
                  MIMn
                
              
              =
              
                ω
                ⁢
                
                  
                
                ⁢
                
                  
                    Q
                    MIM
                  
                  ·
                  
                    d
                    
                      C
                      n
                    
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        10
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  R
                  ONn
                
              
              =
              
                
                  d
                  
                    R
                    Sn
                  
                
                -
                
                  d
                  
                    R
                    MIMn
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        11
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  C
                  OFFn
                
              
              =
              
                
                  
                    r
                    on
                  
                  ⁢
                  
                    c
                    off
                  
                
                
                  d
                  
                    R
                    ONn
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        12
        )
      
    
  
  
    
      
        
          
            
              
                d
                
                  R
                  OFFn
                
              
              =
              
                
                  ω
                  ·
                  
                    d
                    
                      C
                      OFFn
                    
                  
                
                ⁢
                
                  Q
                  
                    C
                    OFF
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




where equations (5)-(13) can be solved to obtain (5) equivalent parallel resistance RPn, (6) incremental capacitance dCn, (7) incremental parallel resistance dRPn, (8) incremental quality factor dQn, (9) equivalent incremental series resistance dRSn, (10) MIM resistance dRMIMn, (11) incremental on-resistance dRONn, (12) incremental off-capacitance dCOFFn, and (13) incremental series off-resistance dROFFn, respectively.

FIG. 9A shows a parallel equivalent circuit obtained through solving equations (6) and (7) for the incremental capacitance dCn and parallel resistance dRPn, respectively. FIG. 9B shows a series equivalent circuit of the parallel equivalent circuit of FIG. 9A, which is obtained by solving equation (9) to obtain incremental series resistance dRSn.
After solving equations (5)-(13), each of effective bit stage MIM capacitance dCMIMn, bit stage stack height ηn, and bit stage device periphery Wn can be obtained through the following equations:




  
    
      
        
          
            
              
                d
                
                  C
                  MIMn
                
              
              =
              
                
                  d
                  
                    C
                    n
                  
                
                +
                
                  d
                  
                    C
                    OFFn
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        14
        )
      
    
  
  
    
      
        
          
            
              
                η
                n
              
              =
              
                ceil
                (
                
                  
                    
                      η
                      eff
                    
                    ·
                    
                      d
                      
                        C
                        MIMn
                      
                    
                  
                  
                    
                      d
                      
                        C
                        MIMn
                      
                    
                    +
                    
                      d
                      
                        C
                        OFFn
                      
                    
                  
                
                )
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        15
        )
      
    
  
  
    
      
        
          
            
              
                W
                n
              
              =
              
                
                  η
                  n
                
                ·
                
                  
                    r
                    on
                  
                  
                    d
                    
                      R
                      ON
                    
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              <
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        16
        )
      
    
  




where ceil(x) is the ceiling function that outputs a smallest integer not less than x. The bit stage stack height ηn and bit stage device periphery Wn provide, for an nth bit stage, number of transistors and total periphery of the ηn transistors in the stack, respectively.

Additionally, MIM and off-capacitance scaling coefficient An and on-resistance scaling coefficient Bn are given by:




  
    
      
        
          
            
              
                A
                n
              
              =
              
                
                  C
                  0
                
                
                  C
                  n
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              ≤
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        17
        )
      
    
  
  
    
      
        
          
            
              
                B
                n
              
              =
              
                
                  d
                  
                    C
                    
                      OFF
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                  
                
                
                  d
                  
                    C
                    OGGn
                  
                
              
            
          
          
            
              
                for
                ⁢
                
                  
                
                ⁢
                0
              
              ≤
              n
              ≤
              b
            
          
        
      
    
    
      
        (
        18
        )
      
    
  




An error function for evaluating accuracy of a designed capacitance is given by:




  
    
      
        
          
            erf
            ⁡
            
              (
              C
              )
            
          
          =
          
            1
            -
            
              
                C
                min
              
              
                
                  
                    ∑
                    
                      n
                      =
                      1
                    
                    N
                  
                  ⁢
                  
                    d
                    
                      C
                      n
                    
                  
                
                ||
                
                  d
                  
                    C
                    OFFn
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        where
        ⁢
        
          

        
        ⁢
        
          
            
              d
              
                C
                n
              
            
            ||
            
              d
              
                C
                OFFn
              
            
          
          =
          
            
              
                
                  
                    
                      d
                      
                        C
                        n
                      
                    
                    ⁢
                    
                      d
                      
                        C
                        OFFn
                      
                    
                  
                  
                    
                      d
                      
                        C
                        n
                      
                    
                    +
                    
                      d
                      
                        C
                        OFFn
                      
                    
                  
                
                ⁢
                
                  
                
                ⁢
                and
              
              ⁢
              
                
              
              -
              1
            
            ≤
            
              erf
              ⁡
              
                (
                C
                )
              
            
            ≤
            
              +
              1.
            
          
        
      
    
    
      
        (
        19
        )
      
    
  




Consider a DTC whose desired capacitance tuning range is 1.0 pF to 5.0 pF. In the case of erf(C)=0 (error function is zero), actual capacitance tuning range acquired is 1.0 pF to 5.0 pF. If the error function were non-zero, the actual capacitance tuning range can be shifted and/or wider/narrower than the desired capacitance range of 1.0 pF to 5.0 pF. For example, the actual capacitance tuning range could be 1.1 pF to 5.4 pF.
For any given application, value of unit device channel resistance ron is based on technology used in a given process while values for CMIM and each coefficient An and Bn can be obtained by solving equations (2)-(19). Specifically, for a particular bit stage n, CMIM is given by dCMIMn in equation (14) whereas An and Bn are given by equations (17) and (18) above.
Bounds for capacitance C and quality factor Q that can be implemented on a particular DTC can broaden or shrink depending on process technology. For instance, if OFF state capacitance COFF of a device were to increase, possible range of values for the capacitance and quality factor shrinks, and vice versa for the case where COFF decreases. This is shown in equation (14) above, where effective bit stage MIM capacitance dCMIMn is given by dCMIMn=dCn+dCOFFn. The incremental off-capacitance dCOFFn is a device capacitance. As previously mentioned, whereas a larger device leads to smaller ON state resistance RON and thus increases Q, the larger device also increases dCOFF and thus increases dCMIMn. Consequently, ranges of capacitance and quality factor of the DTC are not independent of each other.
According to several embodiments of the present disclosure, DTCs can comprise multiple states that are associated with a common capacitance value but variable Q. FIGS. 10 and 11 show examples of DTCs that provide different Q values while maintaining the same capacitance in accordance with several embodiments of the present disclosure. Specifically, the DTCs of FIGS. 10 and 11 can be designed such that although capacitance of the DTC remains the same when number of ON switches is the same, the quality factor can vary between these states.
The DTCs (1000, 1100) in FIGS. 10 and 11 both have three ON switches and two OFF switches. For the DTC (1000) in FIG. 10, the switches associated with control bits b0 (1002), b1 (1004), and b2 (1006) are ON, while the switches associated with control bits b3 (1008) and b4 (1010) are OFF. For the DTC (1100) in FIG. 11, the switches associated with control bits b2 (1106), b3 (1108), and b4 (1110) are ON, while the switches associated with control bits b0 (1102) and b1 (1104) are OFF. Because both DTCs (1000, 1100) have only three ON switches, the two DTCs (1000, 1100) have the same total capacitance, 2.6 pF. However, their Q values differ (50 for the DCT (1000) shown in FIG. 10 and 32 for the DTC (1100) shown in FIG. 11) because of the different switch ON-OFF configurations.
If OFF transistors are designated as ‘0’ and ON transistors are designated as ‘1’, a configuration of the five transistors in FIGS. 6, 10, and 11 may be expressed by a numeric control word b4b3b2b1b0 and/or equivalently as a decimal number, y, defined by

y=b4*24+b3*23+b2*22+b1*21+b0*20  (20).

For example, consider a case where zeroth, first, and fourth control bits are set such that transistors associated with these control bits are ON (e.g., b0=b1=b4=1) and second and third control bits are set such that transistors associated with these control bits are OFF (e.g., b2=b3=0). The numeric control word (b4b3b2b1b0) can be written as 1001 while y=19 since 1*24+0*23+0*22+1*21+1*20=19. In accordance with this example, Table 1 shows the other 31 states possible in the five-bit case.

As previously mentioned, FIG. 8 shows a DTC (800) with exemplary values for coefficients An and Bn, which are used to scale RON and CMIM of each bit stage. By using coefficients An and Bn to scale RONCMIM (and thus RONCMIM are allowed to vary across states), a tapered quality factor across the capacitive tuning range can be achieved, such as previously shown in FIGS. 7A and 7B. Characteristics of the DTC shown in FIG. 8 are shown in each of the graphs that follow in FIGS. 12A through 12E. From the graphs to be shown in FIGS. 12A through 12E, it is noted that each bit stage of the DTC (800) of FIG. 8 contributes a capacitance of 0.5 pF.
When only one transistor stack is ON, there are five states (also known as configurations): 00001, 00010, 00100, 01000, and 10000. FIG. 12A shows the capacitances and Q values for DTCs in each of these five states in accordance with an embodiment of the present disclosure. These five states have the same capacitance, around 1 pF, but different Q values. The Q values have a tapered distribution with respect to the states.
When two of the five transistor stacks are in an ON state (e.g., two of the five control bits are 1's), there are ten states. FIG. 12B shows the capacitances and Q values for DTCs in each of these ten states in accordance with an embodiment of the present disclosure. Likewise, these ten states have the same capacitance, around 1.5 pF, and a tapered distribution of Q values.
When three of the five transistor stacks are in an ON state (e.g., three of the five control bits are 1's), there are ten states. FIG. 12C shows the capacitances and Q values for DTCs in each of these ten states in accordance with an embodiment of the present disclosure. Similarly, the ten states have the same capacitance, around 2.0 pF, and a tapered distribution of Q values.
When four of the five transistor stacks are in an ON state (e.g., four of the five control bits are 1's), there are five different states. FIG. 12D shows the capacitances and Q values for DTCs in each of these five states in accordance with an embodiment of the present disclosure. Similarly, the five states have the same capacitance, around 2.5 pF, and a tapered distribution of Q values.
FIG. 12E shows the capacitances and Q values for a zero-bit case (00000) and a penta-bit case (11111), which may signify states of the DTC when all transistors are in an OFF state or ON state, respectively. In the zero-bit case, capacitance of the DTC is due to COFF of each of the stacks of transistors in series with a corresponding MIM capacitor or capacitors. Due to the serial connections between the capacitances (COFF and CMIM), capacitance of the DTC is lower relative to the case when one or more transistors or stacks of transistors are ON. In FIG. 12E, capacitance for the zero-bit case and the penta-bit case are around 0.5 and 3.0 pF, respectively.
FIG. 13 shows the capacitances and Q values for a thermometer coded DTC with tapered Q values for the DTC (800) shown in FIG. 8. Because capacitances of a DTC are determined by the number of transistor stacks in an ON state (or equivalently determined by the number of transistor stacks in an OFF state), transistor configurations represented in thermometer coding may be utilized to provide tapered capacitances and Q values. It should be noted that in thermometer coding, a state of 0, 1, 2, 3, 4, and 5 can be represented as numeric control words 00000, 00001, 00011, 00111, 01111, and 11111, respectively. Specifically, FIG. 13 shows the capacitances and Q values for DTCs with these six states.
Additionally, FIG. 13 shows an exemplary tuning range for the DTC's capacitance of around 0.3 pF to 3.0 pF and an exemplary tuning range for the quality factor of around 35 to 70. However, it is noted that these tuning ranges (for both the DTC's capacitance and the quality factor) are highly dependent on the application in which the DTC is to be utilized.
FIG. 14 shows a plot of number of different configurations of Q value at each possible capacitance value for a five-bit DTC, in accordance to an embodiment of the present disclosure. Table 3 shows exemplary capacitance and Q configurations for a five-bit DTC that are in accordance with the plot shown in FIG. 14. For example, FIG. 14 shows that there are five states for which capacitance of the five-bit DTC is 1.8 pF, where each state can have a different Q value/configuration. Similarly, Table 3 shows that a capacitance of 1.8 pF is associated with arbitrary Q values Q1(C=1.8) through Q5(C=1.8), where such Q values can be set (e.g., DTC can be configured to realize such Q values) depending on application. Consequently, as previously mentioned, multiple states can have the same capacitance but be configured with different Q values. It is noted that each bit stage of the five-bit DTC (not shown) associated with FIG. 14 contributes a capacitance of 0.8 pF. Additionally, it should also be noted that, for all states with a common capacitance value, one or more states among these states can have the same Q value.







TABLE 3







Exemplary capacitance and Q configurations for a five-bit DTC














State
b4
b3
b2
b1
b0
C (pF)
Q

















0
0
0
0
0
0
1.0
Q1(C = 1.0)


1
0
0
0
0
1
1.8
Q1(C = 1.8)


2
0
0
0
1
0
1.8
Q2(C = 1.8)


3
0
0
0
1
1
2.6
Q1(C = 2.6)


4
0
0
1
0
0
1.8
Q3(C = 1.8)


5
0
0
1
0
1
2.6
Q2(C = 2.6)


6
0
0
1
1
0
2.6
Q3(C = 2.6)


7
0
0
1
1
1
3.4
Q1(C = 3.4)


8
0
1
0
0
0
1.8
Q4(C = 1.8)


9
0
1
0
0
1
2.6
Q4(C = 2.6)


10
0
1
0
1
0
2.6
Q5(C = 2.6)


11
0
1
0
1
1
3.4
Q2(C = 3.4)


12
0
1
1
0
0
2.6
Q6(C = 2.6)


13
0
1
1
0
1
3.4
Q3(C = 3.4)


14
0
1
1
1
0
3.4
Q4(C = 3.4)


15
0
1
1
1
1
4.2
Q1(C = 4.2)


16
1
0
0
0
0
1.8
Q5(C = 1.8)


17
1
0
0
0
1
2.6
Q7(C = 2.6)


18
1
0
0
1
0
2.6
Q8(C = 2.6)


19
1
0
0
1
1
3.4
Q5(C = 3.4)


20
1
0
1
0
0
2.6
Q9(C = 2.6)


21
1
0
1
0
1
3.4
Q6(C = 3.4)


22
1
0
1
1
0
3.4
Q7(C = 3.4)


23
1
0
1
1
1
4.2
Q2(C = 4.2)


24
1
1
0
0
0
2.6
Q10(C = 2.6) 


25
1
1
0
0
1
3.4
Q8(C = 3.4)


26
1
1
0
1
0
3.4
Q9(C = 3.4)


27
1
1
0
1
1
4.2
Q3(C = 4.2)


28
1
1
1
0
0
3.4
Q10(C = 3.4) 


29
1
1
1
0
1
4.2
Q4(C = 4.2)


30
1
1
1
1
0
4.2
Q5(C = 4.2)


31
1
1
1
1
1
5.0
Q1(C = 5.0)









FIG. 15 shows a plot of number of different configurations of Q value at each possible capacitance value for an eight-bit DTC, in accordance with an embodiment of the present disclosure. For example, FIG. 15 shows that there are eight states for which capacitance of the eight-bit DTC is 1.5 pF and twenty-eight states for which capacitance of the eight-bit DTC is 2.0 pF, where each state has a different Q value/configuration. It is noted that each bit stage of the eight-bit DTC (not shown) associated with FIG. 15 contributes a capacitance of 0.5 pF.
It is further noted that the number of states associated with a constant capacitance, as shown in both FIGS. 14 and 15, can be obtained by calculating binomial coefficients. Binomial coefficients are given by




  
    
      
        
          
            (
            
              
                
                  n
                
              
              
                
                  k
                
              
            
            )
          
          =
          
            
              (
              
                
                  
                    n
                  
                
                
                  
                    
                      n
                      -
                      k
                    
                  
                
              
              )
            
            =
            
              
                
                  
                    2
                    !
                  
                  
                    
                      k
                      !
                    
                    ⁢
                    
                      
                        (
                        
                          n
                          -
                          k
                        
                        )
                      
                      !
                    
                  
                
                ⁢
                
                  
                
                ⁢
                for
                ⁢
                
                  
                
                ⁢
                0
              
              ≤
              k
              ≤
              n
            
          
        
        ,
      
    
    
      
        (
        21
        )
      
    
  




which is generally read as “n choose k”. With reference to FIGS. 14 and 15 as well as equation (21), n can represent number of bit stages in a DTC and k can represent number of bit stages in the DTC that are ON. In the case that k is designated to represent the number of bit stages that are ON (and thus n−k represents the number of bit stages that are OFF), then





   
  
    (
    
      
        
          n
        
      
      
        
          k
        
      
    
    )
  




provides number of states where there can be k bit stages of the DTC in an ON state among the total n bit stages present in the DTC.

Since FIGS. 14 and 15 pertain to an embodiment of the present disclosure where states with the same number of bit stages that are ON have the same capacitance value but can be configured with different Q values,




   
  
    (
    
      
        
          n
        
      
      
        
          k
        
      
    
    )
  




also provides number of Q configurations at a given capacitance value. For example, consider the eight-bit DTC (not shown) associated with FIG. 15. Consider states where k=3 bit stages are ON. This is the case where only k=3 bit stages among the n=8 bit stages of the eight-bit DTC are turned ON (e.g., k=3 transistor stacks in the DTC are turned ON or n−k=5 transistor stacks in the DTC are turned OFF) and is associated with a capacitance of 2.5 pF. Number of states with k=3 is given by





   
  
    
      
        (
        
          
            
              n
            
          
          
            
              k
            
          
        
        )
      
      =
      
        
          (
          
            
              
                8
              
            
            
              
                3
              
            
          
          )
        
        =
        56
      
    
    ,
  




as also shown in FIG. 15. Therefore, in this example, for a capacitance value of 2.5 pF, the eight-bit DTC has 56 Q configurations. Results for FIG. 14 can also be derived similarly based on equation (21) with n=5.

FIG. 16 shows the number of different states with respect to capacitances for DTCs with two-bit, three-bit, four-bit, five-bit, six-bit, seven-bit, and eight-bit configurations, in accordance with several embodiments of the present disclosure. As with number of states shown in FIGS. 14 and 15, the number of states under a constant capacitance shown in FIG. 16 can be obtained by calculating binomial coefficients.
With reference to FIG. 16, the higher the number of bits, the more number of different Q configurations can generally be obtained for a fixed C value. According to several embodiments of the present disclosure, a tunable filter can be thus designed, because the bandwidth of the DTC is dependent on Q. If a sharper/tighter bandwidth is desired, a configuration with a higher Q can be utilized. On the other hand, if a large bandwidth is desired, a configuration with a lower Q can be utilized.
Whereas each bit stage of DTCs described above comprises a capacitance AnCMIM that is fixed in value and a switching device connected to the capacitance, according to many embodiments of the present disclosure, capacitance and switching device in one or more bit stages can also be implemented with an inherently variable capacitance. Specifically, any particular bit stage can comprise an inherently variable capacitance without a connected switching device or can comprise an inherently variable capacitance connected with a switching device. An inherently variable capacitance of a bit stage can be realized through use of, for example, a varactor diode, a metal-oxide-semiconductor (MOS) capacitor, and a varactor dielectric such as barium strontium titanate (BST) film, among other variable capacitors known to a person skilled in the art.
Varactors are generally utilized as voltage-controlled capacitors, where a varactor diode and a varactor dielectric are examples of varactors or are examples of components of varactors. The varactor diode is generally a pn junction diode whose capacitance and series resistance change with voltage applied to the varactor diode. It is noted that the varactor diode is generally operated in reverse-bias so that negligible (ideally no) current flows. In such a case, capacitance of the varactor diode can be modeled similar to junction capacitance Cj of a pn junction diode, which can be given by:




  
    
      
        
          
            C
            j
          
          =
          
            
              C
              
                j
                ⁢
                
                  
                
                ⁢
                0
              
            
            
              
                (
                
                  1
                  +
                  
                    
                      V
                      R
                    
                    
                      V
                      0
                    
                  
                
                )
              
              m
            
          
        
        ,
      
    
    
      
        (
        22
        )
      
    
  




where V0 is a junction built-in voltage, VR is a reverse-bias voltage applied to the pn junction diode, Cj0 is junction capacitance value at zero applied voltage (i.e., VR=0), and m is a grading coefficient. Value of the grading coefficient m is a function of manner in which doping density changes between the p side of the pn junction and the n side of the pn junction, as is well known by a person skilled in the art. The varactor diode can thus be designed such that capacitance of the varactor diode can be made to be a stronger function of voltage applied to the pn junction diode by increasing the grading coefficient (e.g., designing a varactor diode to have an m of 3 or 4). Consequently, a varactor diode can be utilized as a voltage-controlled capacitor and can be employed in a bit stage of a DTC.

A MOS capacitor is another example of a varactor. The MOS capacitor can be modeled as a capacitor formed of a metal layer, a semiconductor layer, and an insulator layer that acts as a dielectric material between the metal and semiconductor layers. In a CMOS process, for example, the metal layer can be formed by poly-silicon and referred to as a gate, the semiconductor layer can be formed by silicon and referred to as a body or substrate, and the insulating layer can be formed by silicon dioxide and referred to as an oxide layer. Capacitance of the MOS capacitor can be tuned based on voltage applied to the gate of the MOS capacitor. The MOS capacitor can be implemented, for instance, by a gate capacitance of a MOS transistor.
Another example of a varactor is a capacitor that utilizes a varactor dielectric, where dielectric constant of the varactor dielectric is a function of voltage applied to the varactor dielectric (and thus is a function of voltage applied to the capacitor). By way of example and not of limitation, a BST film can be utilized as a varactor dielectric. The BST film is a ferroelectric material, where a ferroelectric material has a dielectric constant that is a function of an electric field applied (and thus is a function of a voltage applied) to the ferroelectric material. Consequently, as an example, a parallel-plate capacitor with a BST film between the plates can present a capacitance that is a function of a voltage applied to the parallel-plate capacitor due to use of the BST film as the dielectric material. Aside from ferroelectric materials such as a BST film, non-ferroelectric materials such as a bismuth zinc niobate (BZN) film can also be utilized as a varactor dielectric.
As previously mentioned, other examples of varactors or otherwise other examples of variable capacitors are identifiable by a person skilled in the art. Such variable capacitors can be employed in one or more bit stages of a DTC, in accordance with many embodiments of the present disclosure, and can be (but need not be) connected with one or more switching devices. For example, in a case where (RON/Bn)(AnCMIM) remains constant across bit stages of a DTC, capacitance values of the fixed and variable capacitors can be configured accordingly to achieve a constant (RON/Bn)(AnCMIM) across the bit stages. However, the same DTC can also be configured to realize a case where (RON/Bn)(AnCMIM) is not a constant by tuning capacitance of the variable capacitors.
FIG. 17 shows an embodiment of a DTC (1700) that comprises capacitors connected with switching devices. Any one, plurality, or all of the capacitors and connected switching device pairs, which form a bit stage, can be implemented using a voltage or current dependent variable capacitor. As previously mentioned, a varactor diode, a MOS capacitor, and/or a capacitor employing a varactor dielectric such as a BST film, among other variable capacitors known to a person skilled in the art can be used instead of a fixed capacitance or can be used instead of a fixed capacitance connected with a switching device.
Capacitance exhibited by varactors (e.g., varactor diodes, MOS capacitors, BST films) is generally a function of size of the varactors, and as such a broad range of nominal capacitance values is possible depending on size that can be allocated to the varactors. Voltage that is applied to varactors is generally specific to a technology. For example, a varactor diode can be dependent on voltages applied at one or both terminals RF1 and RF2 shown in FIG. 18 whereas BST films can depend on voltage applied at a third terminal (not shown). A person skilled in the art can identify manners by which to apply control voltages/currents and control capacitances exhibited by voltage and/or current dependent capacitors. Furthermore, different metallization patterns or schema for the variable capacitors, identifiable by a person skilled in the art, can influence Q value for a given capacitance value.
FIG. 18 shows a DTC (1800) where capacitances C0, C3, and C4 of a zeroth, third, and fourth bit stage, respectively, are variable and capacitances C1 and C2 of a first and second bit stage, respectively, are fixed. Use of a variable capacitance in a DTC may be for tunability in addition to tunability provided by discrete capacitance values provided by the DTC. For example, with reference to FIG. 18, the fixed capacitances C1 and C2 can be 10 pF and 20 pF, respectively. The variable capacitances C0, C3, and C4 can be utilized for finer tuning around capacitance values of these fixed capacitances. It is noted that the combination of fixed and variable capacitances shown in FIG. 18 is an example. More or fewer of the capacitances C0 through C4 can be fixed capacitances or variable capacitances than the combination shown in FIG. 18. In some cases, all capacitors connected with switching arrangements can be variable capacitances.
FIG. 19 shows a DTC (1900) where a zeroth and second bit stage comprise a fixed capacitor connected with a switching device (bit stages with C0 and C2), a first bit stage comprises a variable capacitor connected with a switching device (bit stage with C1), a third bit stage comprises a fixed capacitor, and a fourth bit stage comprises a variable capacitor. As mentioned previously with reference to several embodiments of the present disclosure, additional bit stages, switching devices, fixed capacitors, and/or variable capacitors can be employed in the DTC (1900) as needed based on application.
As previously mentioned, field effect transistors (FETs) are utilized as switching devices for discussion purposes. However, the present disclosure can also utilize other switching devices such as accumulated charge control field effect transistors, microelectromechanical system (MEMS) switches, diodes, diode connected bipolar junction transistors (BJTs), and other switching devices identifiable by a person skilled in the art.
A switch such as an MEMS switch may be utilized. For MEMS switches, Ron and Coff are generally low over the range of typical operating frequencies. MEMS switches are generally packaged in hermetic packages and involve higher voltages such as 30-50 V to activate. MEMS switches generally have high performance and may be utilized, for instance, in medical or instrumentation equipment.
As another example, in some embodiments, FETs can be implemented in accordance with improved process and integrated circuit design advancements. One such advancement comprises the so-called “HaRPTM” technology enhancements developed by the assignee of the present application. The HaRP enhancements provide for new RF architectures and improved linearity in RF front end solutions. FETs made in accordance with the HaRP enhancements are described in pending applications and patents owned by the assignee of the present application. For example, FETs made in accordance with the HaRP enhancements are described in U.S. Pat. No. 7,910,993, issued Mar. 22, 2011, and U.S. Pat. No. 8,129,787, issued on Mar. 6, 2012, both of which are entitled “Method and Apparatus for use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink”; and in pending U.S. patent application Ser. No. 13/277,108, filed on Oct. 19, 2011, and Ser. No. 13/412,529, filed on Mar. 5, 2012. Disclosures in each of U.S. Pat. Nos. 7,910,993 and 8,129,787 as well as pending U.S. patent application Ser. Nos. 13/277,108 and 13/412,529 is incorporated herein by reference in its entirety.
More specifically, and as described in the aforementioned patents and pending patent applications, FETs made in accordance with HaRP technology enhancements comprise Accumulated Charge Control (ACC) SOI MOSFETs, where each ACC SOI MOSFET includes an Accumulated Charge Sink (ACS) coupled thereto which is used to remove accumulated charge from the ACC FET body when the FET operates in an accumulated charge regime. The ACS facilitates removal or otherwise controls the accumulated charge when the ACC SOI MOSFET operates in the accumulated charge regime. Thus, the HaRP technology enhancements provide a method and apparatus for use in improving linearity characteristics of MOSFET devices using the accumulated charge sink (ACS).
Via the ACS terminal, the HaRP FETs are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary implementation, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. The ACS is operatively coupled to the body of the SOI MOSFET, and eliminates, removes, or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion can be reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
In some implementations as described in the aforementioned patents and pending patent applications, the ACC MOSFET comprises as a four terminal device, where an accumulated charge sink (ACS) terminal is coupled to a gate terminal via a diode. One such four terminal ACC MOSFET (2000) is shown in FIG. 20. FIG. 20 is a simplified schematic of an SOI NMOSFET (2000) adapted to control accumulated charge, embodied as a four terminal device, where the ACC MOSFET (2000) includes a gate terminal (2002), source terminal (2004), drain terminal (2006), and accumulated charge sink (ACS) terminal (2008).
As shown in the implementation of FIG. 20, the ACS terminal (2008) is coupled to the gate terminal (2002) via a diode (2010). This implementation may be used to prevent a positive current flow into the body of the MOSFET (2000) caused by a positive Vg-to-Vs (or, equivalently, Vgs, where Vgs=Vg−Vs) bias voltage, as may occur, for example, when the ACC MOSFET (2000) is biased into an on-state condition. When biased off, the ACS terminal voltage VACS comprises the gate voltage plus a voltage drop across the diode (2010). At very low ACS terminal current levels, the voltage drop across the diode (2010) typically also is very low (e.g., <<500 mV, for example, for a typical threshold diode). The voltage drop across the diode (2010) may be reduced to approximately zero by using other diodes, such as a 0 Vf diode, for example. In one implementation, reducing the voltage drop across the diode is achieved by increasing the diode (2010) width. Additionally, maintaining the ACS-to-source or ACS-to-drain voltage (whichever bias voltage of the two bias voltages is lower) increasingly negative can also improve the linearity of the ACC MOSFET device (2000).
More details and examples of Accumulated Charge Control (ACC) SOI MOSFETs as well as circuits employing such ACC SOI MOSFETs are provided in the disclosures of U.S. Pat. Nos. 7,910,993 and 8,129,787 as well as pending U.S. patent application Ser. Nos. 13/277,108 and 13/412,529, each of which is incorporated herein by reference in its entirety. In many implementations, each ACC SOI MOSFET includes an Accumulated Charge Sink (ACS) coupled thereto which is used to remove accumulated charge from the ACC FET body when the FET operates in an accumulated charge regime. The ACS facilitates removal or otherwise controls the accumulated charge when the ACC SOI MOSFET operates in the accumulated charge regime. Thus, a method and apparatus for use in improving linearity characteristics of MOSFET devices using the accumulated charge sink (ACS) is provided. Via the ACS terminal, the ACC SOI MOSFETs are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary implementation, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. The ACS is operatively coupled to the body of the SOI MOSFET, and eliminates, removes, or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion can be reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
As previously mentioned, it is again noted that although lumped elements (e.g., discrete resistors, capacitors, and inductors) are depicted throughout the present disclosure, the embodiments of the present disclosure can also utilize distributed elements. Specifically, resistances, capacitances, and inductances can be distributed throughout a circuital arrangement and thus can be generally measured per unit length (e.g., Ω/length, F/length, and H/length, respectively). For example, transmission line elements such as half-wavelength, quarter-wavelength, series and parallel stubs (open circuit or short circuit stubs), and resonant stubs can also be utilized to provide resistances and reactances to the circuital arrangement. It should be noted that the various elements (either lumped or distributed) can be on-chip or off-chip.
The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use the embodiments of the digitally tuned capacitors with tapered and reconfigurable quality factors of the disclosure, and are not intended to limit the scope of what the inventors regard as their disclosure. Modifications of the above-described modes for carrying out the disclosure may be used by persons of skill in the art, and are intended to be within the scope of the following claims. All patents and publications mentioned in the specification may be indicative of the levels of skill of those skilled in the art to which the disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference had been incorporated by reference in its entirety individually.
It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. The term “plurality” includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.
A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims.

## Claims

1. A digitally tuned capacitor (DTC) adapted for use in a circuit device, comprising:
a first terminal;
a second terminal; and
a plurality of bit stages in parallel between the first terminal and the second terminal, each bit stage comprising at least one switch connected with at least one capacitor,
wherein:
the plurality of bit stages is configured to be controlled by a numeric control word in binary representation, each bit of the numeric control word representing a switching state of one bit stage in the plurality of bit stages, wherein the switching state is either an ON state or an OFF state, and
states of the DTC with same number of ON states is configured to provide a variable quality factor while maintaining a constant or near constant capacitance around a fixed level.

2. The DTC according to claim 1, wherein the DTC is configured to provide one or more quality factors in a tapered distribution and a constant capacitance in response to one or more switching states of the numeric control word, the one or more switching states having the same number of bits that represent ON states.

3. The DTC according to claim 1, wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution in response to one or more switching states of the numeric control word, the one or more switching states being binary coded.

4. The DTC according to claim 1, wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution in response to one or more switching states of the numeric control word, the one or more switching states being thermometer-coded.

5. The DTC according to claim 1, wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution, wherein higher capacitance values in the one or more capacitances are associated with lower quality factors in the one or more quality factors.

6. The DTC according to claim 1, wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution, wherein lower capacitance values in the one or more capacitances are associated with lower quality factors in the one or more quality factors.

7. The DTC according to claim 1, wherein each bit stage is associated with a quality factor and number of switches in the at least one switch of each bit stage is a function of the quality factor.

8. The DTC according to claim 7, wherein number of switches is lower in a bit stage that, when in an ON state, is associated with a higher quality factor than in a bit stage that, when in an ON state, is associated with a lower quality factor.

9. The DTC according to claim 1, wherein:
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
capacitance value of the at least one capacitor in the particular bit stage is a function of the ON resistance.

10. The DTC according to claim 1, wherein:
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
the ON resistance of the particular bit stage is a function of capacitance value of the at least one capacitor in the particular bit stage.

11. The DTC according to claim 1, wherein:
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
the ON resistance of the particular bit stage is a function of capacitance value of the at least one capacitor in one or more other bit stages among the plurality of bit stages.

12. The DTC according to claim 1, wherein
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
the ON resistance of the particular bit stage is a function of a difference between capacitance value of the at least one capacitor in the particular bit stage and the at least one capacitor in one or more other bit stages among the plurality of bit stages.

13. The DTC according to claim 1, wherein equivalent capacitance of the at least one capacitor in one bit stage is equal to equivalent capacitance of the at least one capacitor in each remaining bit stage.

14. The DTC according to claim 1, wherein each switch among the at least one switch in each bit stage is a microelectromechanical system switch, a diode, a diode connected bipolar junction transistor, a field effect transistor, or an accumulated charge control field effect transistor.

15. The DTC according to claim 1, wherein each capacitor among the at least one capacitor in each bit stage is a fixed capacitor or a variable capacitor.

16. The DTC according to claim 15, wherein a capacitor among the at least one capacitor in a particular bit stage is a variable capacitor, the variable capacitor comprising a varactor diode or a varactor dielectric.

17. A method of digitally tuning a tunable capacitor in a circuit device, comprising:
providing a first terminal;
providing a second terminal;
providing a plurality of bit stages connected in parallel between the first terminal and the second terminal, each bit stage comprising at least one switch connected with at least one capacitor;
applying a numeric control word in binary representation to the plurality of bit stages, each bit of the numeric control word representing a switching state of one bit stage in the plurality of bit stages, wherein the switching state is either an ON state or an OFF state;
selectively controlling capacitance between the first terminal and the second terminal based on switching states of each bit stage in the plurality of bit stages; and
configuring states of the tunable capacitor with same number of ON states to provide a variable quality factor while maintaining a constant or near constant capacitance around a fixed level.

18. The method according to claim 17, wherein the numeric control word to be applied to the plurality of bit stages is based on quality factor to be provided by the tunable capacitor.

19. The method according to claim 17, wherein the numeric control word to be applied to the plurality of bit stages is based on voltages to be applied to the first and/or second terminals.

20. The method according to claim 17, wherein each switch among the at least one switch in each bit stage is a microelectromechanical system switch, a diode, a diode connected bipolar junction transistor, a field effect transistor, or an accumulated charge control field effect transistor.

21. The method according to claim 17, wherein each capacitor among the at least one capacitor in each bit stage is a fixed capacitor or a variable capacitor.

22. The method according to claim 21, wherein a capacitor among the at least one capacitor in a particular bit stage is a variable capacitor, the variable capacitor comprising a varactor diode or a varactor dielectric.