# Patent

## Title
Lamp containing phase-control power controller with analog RMS load voltage regulation

## Abstract

A lamp includes a phase-control power controller within the lamp. The phase-control power controller includes an analog load voltage sensor that provides an optical output related to an RMS load voltage and a phase-controlled dimming circuit that has a comparison circuit that varies a resistance in the phase-controlled dimming circuit responsive to the optical output from the load voltage sensor.

## Background
BACKGROUND OF THE INVENTION 
The present invention is directed to a phase-control power controller that supplies a specified power to a load, and more particularly to a voltage converter for a lamp that converts line voltage to a voltage suitable for lamp operation.
Some loads, such as lamps, operate at a voltage lower than a line (or mains) voltage of, for example, 120V or 220V, and for such loads a voltage converter that converts line voltage to a lower operating voltage must be provided. The power supplied to the load may be controlled with a phase-control power circuit that typically includes an RC circuit. Moreover, some loads operate most efficiently when the power is constant (or substantially so). However, line voltage variations are magnified by these phase-control circuits due to their inherent properties (as will be explained below) and the phase-control circuit is desirably modified to provide a (nearly) constant RMS load voltage.
When the phase-control power controller is used in a voltage converter of a lamp, the voltage converter may be provided in a fixture to which the lamp is connected or within the lamp itself. U.S. Pat. No. 3,869,631 is an example of the latter, in which a diode is provided in the lamp base for clipping the line voltage to reduce RMS load voltage at the light emitting element. U.S. Pat. No. 6,445,133 is another example of the latter, in which transformer circuits are provided in the lamp base for reducing the load voltage at the light emitting element.
Factors to be considered when designing a voltage converter that is to be located within a lamp include the sizes of the lamp and voltage converter, costs of materials and production, production of a potentially harmful DC load on a source of power for installations of multiple lamps, and the operating temperature of the lamp and an effect of the operating temperature on a structure and operation of the voltage converter.
SUMMARY OF THE INVENTION 
An object of the present invention is to provide a novel phase-control power controller that converts a line voltage to an RMS load voltage and incorporates analog load regulation.
A further object is to provide power controller with a phase-control circuit having an analog load voltage sensor that includes a light emitter that provides an optical output related to an RMS load voltage, and a phase-control circuit that has a comparison circuit with a thermally dependent resistor, whose resistance varies in response to the optical output, to vary a resistance in the phase-control circuit.
A yet further object is to provide a lamp with this analog power controller in a voltage conversion circuit that converts a line voltage at a lamp terminal to the RMS load voltage usable by a light emitting element of the lamp.



BRIEF DESCRIPTION OF THE DRAWINGS 
FIG. 1 is a partial cross section of an embodiment of a lamp of the present invention.
FIG. 2 is a schematic circuit diagram of a phase-controlled dimming circuit of the prior art.
FIG. 3 is a schematic circuit diagram of the phase-controlled dimming circuit of FIG. 2 showing an effective state in which the triac is not yet triggered.
FIG. 4 is a schematic circuit diagram of the phase-controlled dimming circuit of FIG. 2 showing an effective state in which the triac has been triggered.
FIG. 5 is a graph illustrating current clipping in the phase-controlled dimming circuit of FIG. 2.
FIG. 6 is a graph illustrating voltage clipping in the phase-controlled dimming circuit of FIG. 2.
FIG. 7 is a graph showing the conduction angle convention adopted herein.
FIG. 8 is a graph showing the relationship of load voltage to conduction angle for several RMS line voltages.
FIG. 9 is a graph showing the relationship of line voltage to conduction angle for fixed RMS load voltages.
FIG. 10 is a schematic circuit diagram of a phase-controlled dimming circuit illustrating the concept of the present invention.
FIG. 11 is a schematic circuit diagram of an embodiment of the present invention.
FIG. 12 is a more detailed schematic circuit diagram of the embodiment of FIG. 11.
FIG. 13 is a schematic circuit diagram of a further embodiment of the present invention.



DESCRIPTION OF PREFERRED EMBODIMENTS 
With reference to FIG. 1, a lamp 10 includes a base 12 with a lamp terminal 14 that is adapted to be connected to line (mains) voltage, a light-transmitting envelope 16 attached to the base 12 and housing a light emitting element 18 (an incandescent filament in the embodiment of FIG. 1), and a voltage conversion circuit 20 for converting a line voltage at the lamp terminal 14 to a lower operating voltage. The voltage conversion circuit 20 is within the base 12 and connected between the lamp terminal 14 and the light emitting element 18. The voltage conversion circuit 20 may be an integrated circuit in a suitable package as shown schematically in FIG. 1.
While FIG. 1 shows the voltage conversion circuit 20 in a parabolic aluminized reflector (PAR) halogen lamp, the voltage conversion circuit 20 may be used in any incandescent lamp when placed in series between the light emitting element (e.g., filament) and a connection (e.g., lamp terminal) to a line voltage. Further, the voltage conversion circuit described and claimed herein finds application other than in lamps and is not limited to lamps.
The voltage conversion circuit 20 includes a phase-controlled dimming circuit, derived from a conventional phase-controlled dimming circuit such as shown in FIG. 2 that has a capacitor 22, a diac 24, a triac 26 that is triggered by the diac 24, and resistor 28. In a conventional dimming circuit, the resistor 28 may be a potentiometer that sets a resistance in the circuit to control a phase at which the triac 26 fires. A dimming circuit is a two terminal device intended to reside in series with a relatively small resistive load.
In operation, a dimming circuit such as shown in FIG. 2 has two states. In the first state the diac 24 and triac 26 operate in the cutoff region where virtually no current flows. Since the diac and triac function as open circuits in this state, the result is an RC series network such as illustrated in FIG. 3. Due to the nature of such an RC series network, the voltage across the capacitor 22 leads the line voltage by a phase angle that is determined by the resistance and capacitance in the RC series network. The magnitude of the capacitor voltage is also dependent on these values.
The voltage across the diac 24 is analogous to the voltage drop across the capacitor 22 and thus the diac will fire once breakover voltage is achieved across the capacitor. The triac 26 fires when the diac 24 fires. Once the diac has triggered the triac, the triac will continue to operate in saturation until the diac voltage approaches zero. That is, the triac will continue to conduct until the line voltage nears zero crossing. The virtual short circuit provided by the triac becomes the second state of the dimming circuit as illustrated in FIG. 4.
Triggering of the triac 26 in the dimming circuit is phase-controlled by the RC series network and the leading portion of the mains voltage waveform is clipped until triggering occurs as illustrated in FIGS. 5–6. A load attached to the dimming circuit experiences this clipping in both voltage and current due to the relatively large resistance in the dimming circuit.
Accordingly, the RMS load voltage and current are determined by the resistance and capacitance values in the dimming circuit since the phase at which the clipping occurs is determined by the RC series network and since the RMS voltage and current depend on how much energy is removed by the clipping.
Line voltage may vary from location to location up to about 10% and this variation can cause a variation in RMS load voltage in the load (e.g., a lamp) by an amount that can vary light levels, shorten lamp life, or even cause immediate failure. For example, if line voltage were above the standard for which the voltage conversion circuit was designed, the triac 26 may trigger early thereby increasing RMS load voltage. In a halogen incandescent lamp, it is particularly desirable to have a constant RMS load voltage.
By way of background and with reference to FIG. 7, clipping is characterized by a conduction angle a and a delay angle θ. The conduction angle is the phase between the point on the load voltage/current waveforms where the triac begins conducting and the point on the load voltage/current waveform where the triac stops conducting. Conversely, the delay angle is the phase delay between the leading line voltage zero crossing and the point where the triac begins conducting.
Define Virrms as RMS line voltage, Vip as peak line voltage, Vorms as RMS load voltage, Vop as peak load voltage, T as period, and ω as angular frequency (rad) with ω=2πf. The RMS voltage is determined from the general formula:




  
    V
    orms
  
  =
  
    
      
        1
        T
      
      ⁢
      
        
          ∫
          0
          T
        
        ⁢
        
          
            
              v
              2
            
            ⁡
            
              (
              t
              )
            
          
          ⁢
          
            d
            t
          
        
      
    
  




Applying the conduction angle defined above yields:




  
    
      
        
          
            
              
                
                  
                    
                      V
                      orms
                    
                    =
                    
                      
                        
                          1
                          
                            2
                            ⁢
                            π
                          
                        
                        ⁡
                        
                          [
                          
                            
                              
                                ∫
                                
                                  π
                                  -
                                  α
                                
                                π
                              
                              ⁢
                              
                                
                                  V
                                  ip
                                  2
                                
                                ⁢
                                
                                  
                                    sin
                                    2
                                  
                                  ⁡
                                  
                                    (
                                    ω
                                    )
                                  
                                
                                ⁢
                                
                                  d
                                  ω
                                
                              
                            
                            +
                            
                              
                                ∫
                                
                                  
                                    2
                                    ⁢
                                    π
                                  
                                  -
                                  α
                                
                                
                                  2
                                  ⁢
                                  π
                                
                              
                              ⁢
                              
                                
                                  V
                                  ip
                                  2
                                
                                ⁢
                                
                                  
                                    sin
                                    2
                                  
                                  ⁡
                                  
                                    (
                                    ω
                                    )
                                  
                                
                                ⁢
                                
                                  d
                                  ω
                                
                              
                            
                          
                          ]
                        
                      
                    
                  
                
              
              
                
                  
                    
                      V
                      orms
                    
                    =
                    
                      
                        
                          1
                          
                            2
                            ⁢
                            π
                          
                        
                        ⁢
                        
                          
                            (
                            2
                            )
                          
                          ⁡
                          
                            [
                            
                              
                                ∫
                                
                                  π
                                  -
                                  α
                                
                                π
                              
                              ⁢
                              
                                
                                  V
                                  ip
                                  2
                                
                                ⁢
                                
                                  
                                    sin
                                    2
                                  
                                  ⁡
                                  
                                    (
                                    ω
                                    )
                                  
                                
                                ⁢
                                
                                  d
                                  ω
                                
                              
                            
                            ]
                          
                        
                      
                    
                  
                
              
            
          
        
        
          
            
              
                V
                orms
              
              =
              
                
                  
                    
                      V
                      ip
                      2
                    
                    π
                  
                  ⁢
                  
                    (
                    
                      
                        α
                        -
                        
                          sin
                          ⁢
                          
                            
                          
                          ⁢
                          α
                          ⁢
                          
                            
                          
                          ⁢
                          cos
                          ⁢
                          
                            
                          
                          ⁢
                          α
                        
                      
                      2
                    
                    )
                  
                
              
            
          
        
      
    
  
  
    
      
        
          V
          orms
        
        =
        
          
            V
            ip
          
          ⁢
          
            
              
                α
                -
                
                  sin
                  ⁢
                  
                    
                  
                  ⁢
                  α
                  ⁢
                  
                    
                  
                  ⁢
                  cos
                  ⁢
                  
                    
                  
                  ⁢
                  α
                
              
              
                2
                ⁢
                π
              
            
          
        
      
    
  




This relationship can also be used to define Vip in terms of Vorms and α:




  
    V
    ip
  
  =
  
    
      V
      orms
    
    ⁢
    
      
        
          2
          ⁢
          π
        
        
          α
          -
          
            sin
            ⁢
            
              
            
            ⁢
            α
            ⁢
            
              
            
            ⁢
            cos
            ⁢
            
              
            
            ⁢
            α
          
        
      
    
  




Using these equations, the relationship between peak line voltage, RMS line voltage, RMS load voltage, and conduction angle α may be displayed graphically. FIG. 8 shows Vorms as a function of conduction angle a for line voltages 220V, 230V and 240V. Note that small changes in line voltage result in larger changes in RMS load voltage. FIG. 9 shows the relationship of line voltage to conduction angle for fixed RMS load voltages. A lamp light emitting element (e.g., filament) is designed to operate at a particular load voltage, such as 120Vrms. As seen these graphs, the conduction angle required to achieve this load voltage depends on the RMS line voltage and the relationship is not linear. Changes in the line voltage are exaggerated at the load.
With reference to FIG. 10 that illustrates the concept of the present invention, one option for solving the problem of varying line voltages is to provide the voltage conversion circuit 20 that includes an RC series network with a resistance element 30 and a capacitor 32 whose resistance and capacitance cause a conduction angle that provides the RMS load voltage appropriate for the lamp.
Recall that the conduction angle of triac triggering is dependent on the RC series portion of the dimming circuit. When selecting the resistance and capacitance for the voltage conversion circuit, it is preferable to pick an appropriate capacitance and vary the resistance. Consider how varying resistance affects triggering. In a simple RC series circuit (e.g., FIG. 3), the circuit resistance RT will be load resistance plus the resistance of the resistor. In application, the load resistance is very small compared to the resistance of the resistor and may be ignored. Using Kirchoff's voltage law the line source voltage Vs can be written in terms of loop current I and element impedances:




  
    V
    S
  
  =
  
    I
    ⁡
    
      [
      
        
          R
          T
        
        +
        
          1
          
            j
            ⁢
            
              
            
            ⁢
            ω
            ⁢
            
              
            
            ⁢
            C
          
        
      
      ]
    
  




which may be rewritten:




  I
  =
  
    
      j
      ⁢
      
        
      
      ⁢
      ω
      ⁢
      
        
      
      ⁢
      
        CV
        S
      
    
    
      
        j
        ⁢
        
          
        
        ⁢
        ω
        ⁢
        
          
        
        ⁢
        
          R
          T
        
      
      +
      1
    
  




This equation may be used to write an expression for the voltage across the capacitor:




  
    V
    C
  
  =
  
    
      I
      ⁢
      
        1
        
          j
          ⁢
          
            
          
          ⁢
          ω
          ⁢
          
            
          
          ⁢
          C
        
      
    
    =
    
      
        
          
            j
            ⁢
            
              
            
            ⁢
            ω
            ⁢
            
              
            
            ⁢
            
              CV
              S
            
          
          
            
              j
              ⁢
              
                
              
              ⁢
              ω
              ⁢
              
                
              
              ⁢
              
                R
                T
              
              ⁢
              C
            
            +
            1
          
        
        ⁡
        
          [
          
            1
            
              j
              ⁢
              
                
              
              ⁢
              ω
              ⁢
              
                
              
              ⁢
              C
            
          
          ]
        
      
      =
      
        
          
            V
            S
          
          ⁡
          
            (
            
              1
              -
              
                j
                ⁢
                
                  
                
                ⁢
                ω
                ⁢
                
                  
                
                ⁢
                
                  R
                  T
                
                ⁢
                C
              
            
            )
          
        
        
          
            
              ω
              2
            
            ⁢
            
              R
              T
              2
            
            ⁢
            
              C
              2
            
          
          +
          1
        
      
    
  




The magnitude and phase relation of capacitor voltage with respect to reference line voltage can be calculated:




  
    
      
        
          
            
              
                
                  
                    
                      Im
                      ⁢
                      
                        {
                        
                          V
                          c
                        
                        }
                      
                    
                    =
                    
                      
                        
                          -
                          
                            V
                            s
                          
                        
                        ⁢
                        ω
                        ⁢
                        
                          
                        
                        ⁢
                        
                          R
                          t
                        
                        ⁢
                        C
                      
                      
                        
                          
                            ω
                            2
                          
                          ⁢
                          
                            R
                            T
                            2
                          
                          ⁢
                          
                            C
                            2
                          
                        
                        +
                        1
                      
                    
                  
                
              
              
                
                  
                    
                      Re
                      ⁢
                      
                        {
                        
                          V
                          c
                        
                        }
                      
                    
                    =
                    
                      
                        V
                        S
                      
                      
                        
                          
                            ω
                            2
                          
                          ⁢
                          
                            R
                            T
                            2
                          
                          ⁢
                          
                            C
                            2
                          
                        
                        +
                        1
                      
                    
                  
                
              
            
          
        
        
          
            
              
                
                
                  V
                  C
                
                
              
              =
              
                
                  
                    
                      
                        Im
                        2
                      
                      ⁢
                      
                        {
                        
                          V
                          C
                        
                        }
                      
                    
                    +
                    
                      
                        Re
                        2
                      
                      ⁢
                      
                        {
                        
                          V
                          C
                        
                        }
                      
                    
                  
                
                =
                
                  
                    V
                    S
                  
                  
                    
                      
                        
                          ω
                          2
                        
                        ⁢
                        
                          R
                          T
                          2
                        
                        ⁢
                        
                          C
                          2
                        
                      
                      +
                      1
                    
                  
                
              
            
          
        
      
    
  
  
    
      
        
          ∠Θ
          C
        
        =
        
          
            
              tan
              
                -
                1
              
            
            ⁡
            
              [
              
                
                  Im
                  ⁢
                  
                    {
                    
                      V
                      C
                    
                    }
                  
                
                
                  Re
                  ⁢
                  
                    {
                    
                      V
                      C
                    
                    }
                  
                
              
              ]
            
          
          =
          
            
              tan
              
                -
                1
              
            
            ⁡
            
              (
              
                
                  -
                  ω
                
                ⁢
                
                  
                
                ⁢
                
                  R
                  T
                
                ⁢
                C
              
              )
            
          
        
      
    
  




The equations for capacitor voltage magnitude and phase delay show how the value of RT affects triggering. Diac triggering occurs (and thus triac triggering also occurs) when VC reaches diac breakover voltage. If capacitance and circuit frequency are fixed values, then RT and VS are the only variables that will affect the time required for VC to reach the diac breakover voltage.
With reference now to FIG. 11, an embodiment of the phase-control power controller 38 of the present invention converts a line voltage at the line terminals 40 to an RMS load voltage. The controller 38 includes a control circuit 42 that is connected to the line terminals 40 and load terminals 44, the resistance element 30 and the capacitor 32 that clip the load voltage in the manner described above.
FIG. 12 shows the control circuit 42 in greater detail. Circuit 42 includes an analog load voltage sensor 50 that includes a first energy emitter 52 (such as an LED) that provides an energy output (an optical output when using an LED) related to an RMS load voltage. Circuit 42 also includes a comparison circuit 54 that varies a resistance in the RC network of resistance element 30 and capacitor 32 responsive to the optical output of first light emitter 52. The comparison circuit 54 includes a first energy sensor 56, such as an optically coupled transistor, that senses the energy (e.g., optical) output from the first energy emitter 52, a first load sensitive resistor 58 connected to the first energy sensor 56 and that emits an amount of thermal energy corresponding to an amount of energy sensed by the first energy sensor 56, and two resistors 60, 60′ connected in series, with the RC network connected between the two resistors. One 60 of the two resistors 60, 60′ is a thermally dependent resistor that has a resistance that corresponds to the amount of thermal energy emitted by the first load sensitive resistor 58 and that varies the resistance in the RC network. The two resistors 60, 60′ form a voltage divider that adjusts the circuit behavior of the RC network thereby allowing analog load regulation.
Analog load sensing circuit 50 may also include a second energy emitter 52′ that provides an energy output related to an RMS load voltage. Comparison circuit 54 may also include a second energy sensor 56′ that senses the energy output from the second energy emitter 52′, a second load sensitive resistor 58′ connected to the second optically energy sensor 56′ and that emits an amount of thermal energy corresponding to an amount of energy sensed by the second energy sensor 56′. Another 60′ of the two resistors 60, 60′ may be a thermally dependent resistor that has a resistance that corresponds to the amount of thermal energy emitted by the second load sensitive resistor 58′.
The analog load voltage sensor 50 establishes a DC signal at node A that is related to, but not the same as, the RMS load voltage. The load (the lamp in a preferred embodiment) is connected across the load terminals 44 at LAMPH and LAMPL. Current limiting resistor 64 ensures that minimal current is drawn from the load. A full-wave bridge 66 and filter capacitor 68 set the DC signal level approximately at the peak of the clipped load voltage waveform. This peak is not the same as RMS load voltage but can be related to RMS load voltage so as to make the DC signal useable as a surrogate for the RMS load voltage. The DC signal is determined by the voltage across resistor 70. That is, resistors 70 and 72 form a voltage divider so that the signal is proportional to the approximate peak waveform voltage across capacitor 68.
The analog load voltage sensor 50 also establishes a DC reference signal at node B to which the DC signal at node A is compared. Zener diode 74 is chosen so that it is always in a state of reverse breakdown during circuit operation. Resistor 76 acts as a current limiting resistor so that very little power is dissipated by the Zener diode 74. The reverse breakdown voltage of the Zener diode 74 establishes the DC reference signal.
The reference signal at node B and the DC signal at node A are compared using at least one of the optically coupled units comprises of respective emitters and sensors 52, 56 and 52′, 56′. If the forward voltage of the energy emitter 52 (e.g., the forward voltage of an LED) is Vtr, then the following relations hold. If the voltage across resistor 70 is greater than the sum of the voltage across Zener diode 74 and Vtr, then emitter 52 will emit energy that is sensed by energy sensor 56 (e.g., the optically coupled transistor is turned ON) and a current will flow through resistor 58, producing heat that is sensed by resistor 60 whose resistance changes, thereby changing the resistance in the RC network. On the other hand, if the voltage across Zener diode 74 is greater than the sum of the voltage across resistor 70 and Vtr, then emitter 52′ will emit energy that is sensed by energy sensor 56′ (e.g., the optically coupled transistor is turned ON) and a current will flow through resistor 58′, producing heat that is sensed by resistor 60′ whose resistance changes, thereby changing the resistance in the RC network.
During operation, as the circuit warms up, resistances of resistors 60, 60′ rise together so that the operation of the RC network is not affected. When the line voltage varies, one of the resistors 60, 60′ is heated so that its resistance changes to change the voltage ratio of the voltage divider formed by resistors 60, 60′. Ultimately, the DC signal at node A approaches the reference signal at node B and thereby sets the conduction and delay angles shown in FIG. 7. This process is repeated to control the RMS load voltage so that is it substantially constant.
The phase-controlled power controller may, in an alternative embodiment, include an insulated gate bipolar transistor (IGBT) 80 instead of the diac 24 and triac 26 as illustrated schematically in FIG. 13. The operation of the IGBT 80 corresponds to that of the combination of the diac 24 and triac 26 and may be suitable for high voltage operation (e.g., above 300V).
The description above refers to use of the present invention in a lamp. The invention is not limited to lamp applications, and may be used more generally where resistive or inductive loads (e.g., motor control) are present to convert an unregulated AC line or mains voltage at a particular frequency or in a particular frequency range to a regulated RMS load voltage of specified value.
While embodiments of the present invention have been described in the foregoing specification and drawings, it is to be understood that the present invention is defined by the following claims when read in light of the specification and drawings.

## Claims

1. A lamp comprising a phase-control power controller within the lamp and connected to a lamp terminal,
said phase-control power controller including an analog load voltage sensor that provides an optical output related to an RMS load voltage and a phase-controlled dimming circuit that has a comparison circuit that varies a resistance in said phase-controlled dimming circuit responsive to the optical output from said load voltage sensor,
said analog load voltage sensor comprises a first light emitting diode that emits the optical output, and
said comparison circuit comprises a first optically coupled transistor that senses the optical output from said first light emitting diode, a first load sensitive resistor that emits an amount of thermal energy corresponding to an amount of optical energy sensed by said first optically coupled transistor, and two resistors connected in series, one of said two resistors having a resistance that corresponds to the amount of thermal energy emitted by said first load sensitive resistor and that varies the resistance in said phase-controlled dimming circuit.

2. The lamp of claim 1, wherein said analog load voltage sensor further comprises a second light emitting diode that emits the optical output, and said comparison circuit further comprises a second optically coupled transistor that senses the optical output from said second light emitting diode, a second load sensitive resistor that emits an amount of thermal energy corresponding to an amount of optical energy sensed by said second optically coupled transistor, and wherein a second one of said two resistors has a resistance that corresponds to the amount of thermal energy emitted by said second load sensitive resistor.

3. The lamp of claim 1, wherein said phase-controlled dimming circuit further includes a capacitor, a diac, and a triac that is triggered by said diac.

4. The lamp of claim 1, further comprising a base and a light-transmitting envelope, and wherein said phase-control power controller is within said base.

5. The lamp of claim 1, wherein said phase-control power controller is an integrated circuit.

6. The lamp of claim 5, further comprising a base and a light-transmitting envelope, and wherein said integrated circuit is within said base.