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NBS TECHNICAL NOTE 851

U.S. DEPARTMENT OF COMMERCE/ National Bureau of Standards

Computer System Capacity

Fundamentals
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards' was established by an act of Congress March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology and facilitate their effective application for public benefit. To this end, the Bureau conducts

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iaL

1974 Computer System Capacity Fundamentals

D. J. Kuck

Department of Computer Science

University of Illinois Urbana, Illinois

Prepared for the

Systems and Software Division

Institute for Computer Sciences and Technology

U <j i National Bureau of Standards Washington, D.C. 20234

4. .

*°*eAv o*

U.S. DEPARTMENT OF COMMERCE, Frederick B. Dent, Secretary

NATIONAL BUREAU OF STANDARDS, Richard W. Roberts, Director

Issued October 1974
Library of Congress Catalog Card Number: 74-600148

National Bureau of Standards Technical Note 851

Nat. Bur. Stand. (U.S.), Tech. Note 851, 25 pages (Oct. 1974) CODEN: NBTNAE

U.S. GOVERNMENT PRINTING OFFICE WASHINGTON: 1974

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402 (Order by SD Catalog No. C13.46:851). Price 80 cents.
FOREWORD

The Institute for Computer Sciences and Technology at the National

Bureau of Standards , U.S. Department of Commerce/ and the Association for Computing Machinery , the nation's largest technical

society for computing professionals , have been jointly sponsoring

a series of workshops and action conferences on national issues.

These workshops were designed to bring together the best talents

in the country in their respective areas to establish a consensus

on (1) current state of the art, (2) additional action required,

and (3) where the responsibility for such action lies.

An ACM/NBS Workshop Planning Committee on Computer Capacity meeting was held at NBS in February , 1974. One of the discussions

resulted in a new theoretical definition of capacity. Those

participating in the discussion were: Dr. George Dodd, General

Motors Research Laboratory , Chairman; Professor James C. Browne,

University of Texas; Mr. Walter M. Carlson, IBM Corporation;

Dr. Sidney Fernbach, Lawrence Livermore Laboratory; Dr. Aaron

Finerman, State university of New York at Stoneybrook; Dr. Ronald

A. Finkler , Institute for Defense Analyses; Professor Michael J. Flynn, The Johns Hopkins university; Mr. Henry S. Forrest, Control

Data Corporation; Mr. S. Jeffery, National Bureau of Standards

;

Professor David Kuck, University of Illinois; Mr. George Lindamood,

National Bureau of Standards; Dr. Michael Muntner, General Services

Administration ; Mr. James Pomerene , IBM Corporation; Mr. Paul Roth,

National Bureau of Standards; Mr. Jules Aronson, National Bureau

of Standards

.

It was felt that the results of the discussion were significant,

and that they should be refined and published. Dr. Kuck was kind

enough to undertake this task and produce the following paper.

TABLE OF CONTENTS

Page

1. Introduction 1

2. Capacity in Overlapped Machines 2

3. Capacity in Non-Overlapped Machines ... 12

4. Processor-Memory-Disk Systems 15

5 . Primary Memory Size vs . B 17

6. Conclusion 19

Computer System Capacity Fundamentals

D. J. Kuck

Abstract

A framework for the study of computer capacity is given

by means of a definition of capacity in terms of speeds

of various parts of a computer as well as memory size.

The calculation of theoretical capacity is given for

several combinations of processor, memory, and I/O bandwidth for both overlapped and nonoverlapped machines

.

The tradeoff between primary memory size and I/O bandwidth is discussed in terms of the new definition.

Key words: Capacity; computer; evaluation; measurement;

performance

.

1 . Introduction

On mips and mops

an d mega fl ops

,

and binary

capaci ty

.

This report is an attempt to outline a formal structure for the study of

computer capacity. Several traditional measures will be discussed and

some new measures will be introduced. Our goals for the use of measures of computer capacity include:

1. Quantification of upper bounds on a given machine' s raw

theoretical speed for various kinds of computation.

2. Comparisons between diverse computer systems for some

set of computations

.

3. Evaluation of the actual performance of a given machine

on some job mix compared with its theoretical capacity.

4. Guidelines for improving a given system's cost/performance.

Traditionally , people have often quoted computer speeds in mips (millions

of instructions per second). But the execution of an "instruction" yields

rather different effects on various machines. The range is from some simple indexing operation on a traditional machine to a vector inner

product instruction on a modern pipeline processor. Thus, as computer

organizations diverged from one another, mops (millions of operations per

second) became a more reasonable measure. But in many numerical calculations, floating-point arithmetic operations are the raison d'etre for the

computer and logical operations, shifts, etc., are "overhead." Thus,

megaflops (millions of floating-point operations per second) may be the

important measure.

1
Quoting megaflops is of course quite- irrelevant for most computations

performed in the real world every day. In many computations, e.g., data

base management, file processing, simulation, etc., almost no floating

point arithmetic is performed . The primary memory speed and often

input/output speeds are the most important to quote in evaluating or comparing machines . Our formultaion will include consideration of the

type of computation being performed in terms of ratios such as primary

memory to processor bandwidth used by a computation.

We will attempt to bring together in a uniform way measures of the

speeds of various parts of a computer as well as memory size. The two

main measures which concern us are speed (of processor , primary and

secondary memory) and size of primary memory. By definition, speeds are

given in units per second and bits/second is the simplest such measure.

It is traditional to call the bit rate of a communication channel its

capacity. Similarly, sizes of memories in bits may be thought of as capacities. Since we shall be discussing speeds and sizes together, it seems reasonable to refer to the whole notion as "computer capacity"

In addition to the above machine characteristics , our model will include

characteristics of the programs being executed. In particular, we are concerned with the fractions of a computation which use each of the

three major parts of a system: processor , primary memory and secondary

memory. Thus, our model could be used by independently measuring

machine and program characteristics , and relating them through the

capacity surfaces we derive.

One difficult question is how to deal with the control unit. It has the

potential to allow the several major parts of a computer to operate

simultaneously and thereby increase capacity in a major way. We shall

briefly discuss "serial" control whereby only one function can be

performed at a time. Our major attention will be given to computer

systems in which the processor , primary and secondary memory all can operate simultaneously in an overlapped way. The models we discuss can be thought of as assuming a perfect "lookahead" control unit.

Alternatively , any idleness due to the control unit may be considered to be lumped together with the processor. Degradations in system capacity

due to variously constrained control units could be an interesting area for further study. In fact, the control unit could be treated as a fourth dimension in Figure 6 of Section 4

2 . Capacity in Overlapped Machines

In this section we define processor , memory and system capacity . These

definitions are given in terms of machine parameters (our a's) and

program parameters (our $'s) . There is a good deal of symmetry in much

of the following , and we illustrate this by displaying a number of

equations

Let us consider a clocked machine with a processor, i.e., an arithmetic

and logical unit, operating at maximum bandwidth (i.e,, data rate) B
bits/second. Let the primary memory bandwith be B bits/second. We

define

B B

a = JB-> and ex = -P > . pm ts mp B p m

For any given computation, the total available bandwidth of the pro- cessor or memory may not be used. Thus, we define B < B to be the

p - p

bandwidth of the processor which is actually used in some computation,

Similarly, we define B < B a.s the used bandwidth of the memory for a m — m

given comuptation. Also, for any given computation we define

> 1,

u u _ p m

pm u BP

and

6 = m ' P

B

U+BU

> 1 , mp u — ' Bm

so it follows that

and

B

U

i - 1 = -£L- > 0,

pm u _

BP

3 - 1 = —^— > 0. mp u —

Bm

We may interpret I/B as the fraction of some computation in which the

processor is engaged. Similarly, -L_ = j_ 1 is the fraction of a

p pyim given computation in which the memory is engaged.

If we assume that each memory cycle and each processor operation require

the same amount of time, then the above can be interpreted as follows.

For a machine with a control unit which overlaps memory and processor

operation, 2/3 is the processor fraction of the total number of

pm

instructions executed or the processor fraction of the total bandwidth

used for some computation. For a machine with a control unit
which allows no overlap of processor and memory operation, 1/8 is the

processor fraction of the total number of instructions executed.

Obviously , similar statements hold for 1/8 . 3 ' mp

Next we consider the notion of the capacity of the processor, the

memory and the combination of the two. We shall define capacities in

bits/second. Since we are interested in maximum possible data rates,

we shall assume that either the memory or the processor bandwidth is

saturated in any given computation we discuss. Thus, all our discussion of capacity will assume that for the type of computation under

consideration no faster data rate is possible on the machine we are

considering.

Let us define

B y = m

> 1 m

and

Y = P > 1 P

BP

which we call the memory freedom and processor freedom , respectively

When y = 1, the computation is said to be memory bound and when y = 1,

the computation is said to be processor bound . As outlined in the

preceding paragraph, our subsequent discussions of capacity will assume

that either Y = 1 or y = 1 , or both.

We can relate machine parameters (CX's), program parameters ($'s) and

freedoms (y's) as follows. Since

__2L= Bm % m c B£_

v B Bu pm u P P m Bm

and since

Bmp -

I u pm Bm

we have

^m

= apm 3!£_

T pppm
Since CXpm

= l/&mp, we can derive a similar expression by interchanging

m's and p's in this equation.

Now we define, for any given computation on any given machine with

overlapped processor and memory, the processor capacity

CP

=

a

'^-1"P pm

pm'1 * it a <R -1

otherwise. (j)

Note that a > B -I is equivalent to pm — pm

B R

U m > Dm

B — u P BP

B B ze y

js. U 2- u B B m p

Y > Y 'm _ <p -

But since we are assuming that either y = 1 or y — 1 , this implies

that y = 1. Thus, in the processor bound situation our definition sets

C = B which is the maximum processor data rate.

On the other hand, if anm < Br,TM - 1 / it follows that y < v / i>ut since f"1 — yui 'm — p

y' rr, = lory„ = lwe conclude that y = 1, and we are memory bound. m 'P 'm Thus i B = b". Now the definition of Cp

can be rewritten in this case

as ^^^B B u Y

c = P^p = 5L_ = b

p B -1 u/ PPm Bm/B

But since ym

= 1 , we have C f= B

u in the case of a memory bound

computation

Thus, the processor capacity is defined to be the fraction of the

processor bandwidth which can be used for this computation , given the

5
fact that memory bandwidth is saturated.

If we rewrite processor capacity as

C = —— a p

yp

b

p

we can interpret it as B if memory freedom is greater than processor

freedom for some computations and as B times the ratio of the freedoms

otherwise. We emphasize that the processor only reaches its maximum

capacity B when Y > V p m — p

We can derive an expression for memory capacity C with analogous

characteristics to processor capacity . Thus, we write

a b c = i BE m

if a < 6 - l m ) ttmprl mp - mp

jg otherwise.

m

Since am„B„ = B / BTM„ " ^ =

r and B = ot B we can express C in

mp m p ^mp a -1 m pm p * m J pm

terms of B as follows

P

I (&pm

~1)B

P ^ 6 nm - 1 < a

Cm

-\ pm ^ pm

ar,„ B otherwise, pm p (3)

If we define system capacity C to be the total system bandwidth

available for any calculation, by properly adding Equations 1 and 3 we obtain

Dpjjj 1 £>m P pm — ^pm

C = \ (1+$ ~1)B otherwise,

s pm p

so a 6 c = 1 g -i p

s 1 ypm if a < & -l pm — pm

otherwise

®pm

Bp (4)
This can be expressed in terms of B as m

C =

s

a B mp mp„

g -7 gm if a ' 6 - 1 mp

J mp - mp

otherwise.

PmpBm ('5;

I /Vote that maximum system capacity occurs when both the memory and

processor are bound, i.e., V = Y = !• Thus, from Equation 4, if

p m

a =3 ~ 1 we have

pm pm

O-pm^pm _J

s o -1 BP

(1 +o -1 'OpoPp ppm ppm e

7 B = d+-^)B = (l+JS^B = B + B B_7 m aTM, xpm m Bm m m P

Thus, the maximum system capacity is the sum of the maximum processor

and memory bandwidths

To make matters concrete, we give in Figure 1 examples of capacities

for a =2 and various P values. In Figure 1 we denote activity by pm pm

X and inactivity by 0. We show two columns under the label "memory" to denote that the memory bandwidth is twice the processor bandwidth, i.e.,

0. =2. The capacities are shown under the columns of activity

Overall results are plotted in Figure 2.

In Figure 3 we plot system and processor capacity for various values of

a . Note that the processor can perform at its maximum capacity

over a wider range of problems (B Values) for larger a . Note

pm pm

also that the memory capacity which is available for memory to memory

(or 1/0} operations becomes greater for larger a. It should be

remarked that as $ approaches 1, reasonable system performance

depends on high frequency of register to register operations

(or cache to cache operations)
pm

= 4/3 = 3/2

processor memory

X X

X

X

X X

X

X

• •

m . B + B/3 4B

pm

processor memory

X X

X

X X

X

•

•

. .

3B_ 2

= 2 = 3 pm

processor

X

memory

X

X X

X X

• •

pm

processor

X

memory

X X

X X X

X X X

• •

B + B = 2B B + 2B = 3B

Figure 1. Overlapped Processor and Memory, a =2
pm

= 4 pm

= 5

processor memory

X X

X X

X X X

X X X

X X X

X X X

X X

X X

X X X

X X X

X X X

X X X

• •

• •

processor memory

X X

X X X

X X

X X X

X X

X X X

' •

• •

. .

B „ 5B — + 2B =

2 2

¥ * » - f

Figure 1 (continued) . Overlapped Processor and Memory, apm

= 2
pro- cessor

- 3B

2B

^J I J I I I U I I u ^J

2 i. 4 3

2 1

4 5

memory

10

pm

Figure 2. Capacity for a =2

pm

10
- 5B

- 4B

3B

2B

memory

2_ 2

4 5 10

pm

Figure 3. Capacities for Various a Values

pm

11
3 . Capacity in Non^-Overlapped Machines

To contrast the previous section with a simpler machine and demonstrate

how capacities vary as a function of machine organization , we now

disallow the simultaneous operation of memory and processor . However,

we do assume a perfect lookahead control unit. Figure 4 Illustrates the

situation for a = 2.

It may be seen that in the case of non-overlapped processor and memory,

we have (using the notation of the previous section) :

a B

c = Pm P

P a + 6 -I

' pm pm

(6)

c

PJn

p pm P m

a + B -1 pm pm

(7)

and

C = Pm P^P

s a + R -1 pm wpm (8)

We plot the capacity of a non-overlapped machine for a = 2 in

pm

Figure 5. Note the contrast with Figure 2 , an overlapped machine.

Here the processor and memory capacities only reach their maximum

bandwidth at the limits of 1/6 . Note also that a good deal less

pm

system capacity is left over for 1/0 activities

We can easily show that an overlapped machine' s capacities are all

greater than or equal to a non-overlapped machine' s. Thus, from

Equations 1 and 6 we see that

nonoverlapped =

C

P

Pm V

a +3 -i

pm pm

a B PS P

pm

-2

since a > in the first case, and

pm

similar ways we can show that

overlapped C

I > 1 in the second case

pm — In

non-overlapped C < overlapped C m — m

and

non-overlapped C < overlapped C

s — s12
= 2 = 3

processor memory

X X

X

X

X X

X

X

•

• •

processor

X

memory

X X

X

X X

X

X X

*

2B/3 + 2B/3 = — B/2 + B = ?*L2

= 4 = 5

processor memory

X X

X X

X

X X

X

X X

X X

X

X X

X

•

processor memory

X X

X X

X

X X

X X

X

•

£ . 4B

3

+ T

5B_ 3

2B ___ 6B S

~E~ + = —B 5 5 5

Figure 4. Non-overlapped Processor and Memory/ o. — 2 13
processor

2B

memory

Figure 5. Non-overlapped Capacity for a = 2

14
4. Processor-Memory-Disk Systems

Now we turn to a complete system with three components—processor and

primary memory as above, together with a secondary memory which we

shall refer to as a disk. We shall assume at all times that one of

these three components is operating at its highest data rate, i.e., its

bandwidth is saturated. We also assume a control unit which overlaps

the operation of the processor , the primary memory and the disk. We

first give some definitions which are analogous to those of Section 2.

Let B, be the disk or I/O bandwidth,

a Then

and

B

d apd B ' P

md Bm

B a = -£ • dp B

d

a - dm

Bm

We also define

u u B «,

Pd u BP

B

U +B»

o m a md u Bm

with ft, and 3, being defined similarly. It follows that processor

capacity may be written as: as b

Pm P = ?!- if a < B -I and a, < 6 , -1

I -1 B -1 pm — pm dm — am pm pm

r = \ s^= e- = / if a < B .-J and a > 3 . -1 C

p 10-1 Bpd pd - pd dm - dm

I pd

r if a > B -I and a , > , -1 Bp pm - pm pd - pd

15
Similarly, we have for memory capacity:

C = m

a b

mp m

3 -i

mp

a , b md m

B

mp

B

md

-1

md

-1

if a > 3 -1 and a J > 3 , -1

pm — pm pd — pd

if a , < 3 .-I and a _, < 3 J -2

md - raa pd — pd

and for disk capacity:

if a < 3 -1 and a _, > 3 „-J , pm — pm md — md

C =

d

dm d = s

= m

dm dm

dp d = BP

dp VJ

if a . > 3 .-1 and a < 3 -1 md — md pm — pm

if a, < 3, -1 and a > 3 -1 dp — dp pm — pm

if a < S -1 and a _, < 3 J -I md — md pd — pd

By summing these capacities for consistent conditions , we obtain

saturated system capacities as follows:

16
(1 + l + _J ; H if a > B -j

'

pm — pm

and a < B -j dp — dp

1 + i ; pP

1

• +

1 ) pm am

fl c^ = / tf + — + K-{ b if a < B -1

s ,•: _ ? -/)--. pm — pm

and a > 6 -j ma — ma

pd md

and a _, < B -1 md — md

It should be noted that in each of these three cases, if the conditions

are written as equalities, then the maximum capacity is obtained. In each case this reduces to

max C = B + B + B , . s p m a

To make matters concrete , in Figure 6 we sketch a surface for B = B, B P

B - 2B, and B = — . The processor capacity is shown as a plateau

of height B which runs off to along the memory-disk axis. The top

surface is the system capacity. In the region labelled I, the system

is processor bound, and in II and III it is memory and disk bound,

respectively . Where these three regions meet, the max S = 3.5B

point is located.

5. Primary Memory Size vs. B

It is well known that there exists a trade-off between primary memory

size and I/O bandwidth. Our purpose here is to sketch an analysis

of this trade-off and to relate it to our previous discussion of

capacity

Let the primary memory size be N words of w bits each, for a total of

wN bits. The time required to fill this memory from a disk of bandwidth

B, (assuming B < B ) is wN/B , sec.

a dm a For simplicity , assume a given computation operates on the entire

memory. Assume the computation requires Na time steps. For example,

given an nxn matrix, an n step algorithm would give a = 3/2, since

2 n = N if the matrix (or a single nxn partition) fills primary memory.

ct Now the time required for the entire computation would be wN /C sees.

17
disk

Figure 6. Capacity Space

18
On the average, the system would be balanced if the processing time were

equal to the input time (assuming no output) , that is:

wNa/C = wNB

d

C

JU-1 = _£.

which gives us

N =1 (9)

as a relationship between memory size N, I/O bandwidth B , and processor

capacity C

P

The above model can be easily refined in various ways to provide for

input and output of data arrays, to provide for multiple buffering, and

so on.

6. Conclusion

The point of this report is to provide a framework for the study of

computer capacity . We have explored several aspects of the question

and Figure 6 shows a system capacity surface as a function of processor

memory and disk bandwidth. For a given class of computations, this

surface corresponds to a memory size given by Equation 9 in Section 5.

While we have glossed over many details, the model described here could

be useful in the various ways mentioned in the Introduction.

For example, if we were given a set of computations and a machine

configuration we could easily determine a Figure 6 type surface from the

machine parameters. From the computational algorithms , we could

estimate the various P values as discussed in Section 2. This would

allow a determination of our operating point in capacity space. While

the ideal point is where C = C + C + C , , a prudent region is

s p m d

probably somewhere between that point and the processor corner of

Figure 6 for "numerical" problems. For "business" -type problems it

may be between there and the memory corner of Figure 6. For the class

of algorithms under consideration, Equation 9 could be used to make

memory size trade-offs.

Given some qualitative idea of the operating rules a user prefers,

one could use this model to make quantitative sensitivity studies of

capacity as a function of bandwidth and memory size. This could lead

to improved system cost/effectiveness

19
Note that for any given capacity surface, degradation due to operating

system overhead, etc., can be quantified by plotting actual performance

data in capacity space. In this case, the surfaces shown will serve

as theoretical upper bounds on system performance

20
NBS-114A (REV. 7-73)

U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBS TN-8512. Gov 't Acce;

No.

3. Recipient's Accession No

4. TITLl- AND SUBTITLE 5. Publication Date October 1974

Computer System Capacity Fundamentals 6. Performing Organization Code 640.00

7. AUTHOR(S)

David J. Kuck

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS NATIONAL BUREAU OF STANDARDS DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

10. Project/Task/Work Unit No

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12. Sponsoring Organization Name and Complete Address (Street, City, State, ZIP) NBS

13. Type of Report & Period Covered Final

14. Sponsoring Agency Code

15. SUPPLEMENTARY NOTES

Library of Congress Catalog Number: 74-600148

16. ABSTRACT (A 200-word or less tactual summary of most significant information. If document includes a significant bibliography or literature survey, mention it here.)

A framework for the study of computer capacity is given by means of a definition of capacity in terms of speeds of various parts

of a computer as well as memory size. The calculation of

theoretical capacity is given for several combinations of

processor, memory, and I/O bandwidth for both overlapped and

nonoverlapped machines. The tradeoff between primary memory

size and I/O bandwidth is discussed in terms of the new

definition.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name; separated by semicolons) Capacity; computer; evaluation; measurement; performance.

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USCOMM-DC 29042-P74

U.S. GOVERNMENT PRINTING OFFICE: 1974— 583-012:18

NBS TECHNICAL PUBLICATIONS

PERIODICALS JOURNAL OF RESEARCH reports National Bureau

of Standards research and development in physics, mathematics, and chemistry. Comprehensive scientific papers five complete details of the work, including laboratory data, experimental procedures, and theoretical and mathematical analyses. Illustrated with photographs, drawings, and charts. Includes listings of other NBS papers as issued. Published in two sections, available separately:

• Physics and Chemistry (Section A)

Papers of interest primarily to scientists working in these fields. This section covers a broad range of physical and chemical research, with major emphasis on

standards of physical measurement, fundamental constants, and properties of matter. Issued six times a

year. Annual subscription: Domestic, $17.00; Foreign,

$21.25.

• Mathematical Sciences (Section B)

Studies and compilations designed mainly for the mathematician and theoretical physicist. Topics in mathematical statistics, theory of experiment design, numerical analysis, theoretical physics and chemistry, logical design and programming of computers and computer

systems. Short numerical tables. Issued quarterly. Annual subscription: Domestic, $9.00; Foreign, $11.25. DIMENSIONS/NBS (formerly Technical News Bulletin) —This monthly magazine is published to inform

scientists, engineers, businessmen, industry, teachers,

students, and consumers of the latest advances in science and technology, with primary emphasis on the work at NBS. DIMENSIONS/NBS highlights and reviews such

issues as energy research, fire protection, building- technology, metric conversion, pollution abatement,

health and safety, and consumer product performance.

In addition, DIMENSIONS/NBS reports the results of Bureau programs in measurement standards and tech- niques, properties of matter and materials, engineering- standards and services, instrumentation, and automatic

data processing. Annual subscription: Domestic, $6.50; Foreign, $8.25.

N0NPERI0DICALS Monographs—Major contributions to the technical liter- ature on various subjects related to the Bureau's scientific and technical activities. Handbooks—Recommended codes of engineering and

industrial practice (including safety codes) developed

in cooperation with interested industries, professional

organizations, and regulatory bodies. Special Publications—Include proceedings of high-level national and international conferences sponsored by NBS, precision measurement and calibration volumes, NBS annual reports, and other special publications appropriate to this grouping such as wall charts and

bibliographies. Applied Mathematics Series—Mathematical tables, manuals, and studies of special interest to physicists, engineers, chemists, biologists, mathematicians, computer programmers, and others engaged in scientific and technical work.

National Standard Reference Data Series—Provides

quantitative data on the physical and chemical properties of materials, compiled from the world's literature and critically evaluated. Developed under a world-wide program coordinated by NBS. Program under authority

of National Standard Data Act (Public Law 90-396). See also Section 1.2.3.

Building Science Series—Disseminates technical infor- mation developed at the Bureau on building materials, components, systems, and whole structures. The series presents research results, test methods, and performance criteria related to the structural and environmental functions and the durability and safety characteristics of building elements and systems.

Technical Notes—Studies or reports which are complete

in themselves but restrictive in their treatment of a

subject. Analogous to monographs but not so comprehensive in scope or definitive in treatment of the subject area. Often serve as a vehicle for final reports of work performed at NBS under the sponsorship of other government agencies. Voluntary Product Standards—Developed under pro- cedures published by the Department of Commerce in Part 10, Title 15, of the Code of Federal Regulations. The purpose of the standards is to establish nationally recognized requirements for products, and to provide

all concerned interests with a basis for common under- standing of the characteristics of the products. The

National Bureau of Standards administers the Voluntary Product Standards program as a supplement to the activities of the private sector standardizing

organizations. Federal Information Processing Standards Publications (FIPS PUBS) —Publications in this series collectively constitute the Federal Information Processing Standards Register. The purpose of the Register is to serve

as the official source of information in the Federal Gov- ernment regarding standards issued by NBS pursuant

to the Federal Property and Administrative Services Act of 1949 as amended, Public Law 89-306 (79 Stat. 1127), and as implemented by Executive Order 11717

(38 FR 12315, dated May 11, 1973) and Part 6 of Title 15 CFR (Code of Federal Regulations). FIPS PUBS

will include approved Federal information processing standards information of general interest, and a complete index of relevant standards publications. Consumer Information Series—Practical information, based on NBS research and experience, covering areas

of interest to the consumer. Easily understandable language and illustrations provide useful background

knowledge for shopping in today's technological marketplace. NBS Interagency Reports—A special series of interim

or final reports on work performed by NBS for outside sponsors (both government and non-government). In

general, initial distribution is handled by the sponsor;

public distribution is by the National Technical Infor- mation Service (Springfield, Va. 22151) in paper copy

or microfiche form. Order NBS publications (except Bibliographic Subscription Services) from: Superintendent of Documents, Government Printing Office, Washington, D.C. 20402. BIBLIOGRAPHIC SUBSCRIPTION SERVICES

The following current-awareness and literature-survey bibliographies are issued periodically by the Bureau:

Cryogenic Data Center Current Awareness Service

(Publications and Reports of Interest in Cryogenics). A literature survey issued weekly. Annual subscription: Domestic, $20.00; foreign, $25.00. Liquefied Natural Gas. A literature survey issued quarterly. Annual subscription: $20.00. Superconducting Devices and Materials. A literature survey issued quarterly. Annual subscription: $20.00. Send subscription orders and remittances for the preceding bibliographic services to the U.S. Department

of Commerce, National Technical Information Service, Springfield, Va. 22151. Electromagnetic Metrology Current Awareness Service (Abstracts of Selected Articles on Measurement

Techniques and Standards of Electromagnetic Quantities from D-C to Millimeter-Wave Frequencies).

Issued monthly. Annual subscription: $100.00 (Special rates for multi-subscriptions). Send subscription order and remittance to the Electromagnetic Metrol- ogy Information Center, Electromagnetics Division, National Bureau of Standards, Boulder, Colo. 80302.
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