NBS SPECIAL PUBLICATION, 400-

1

National Bureau oTStanaards

Library, E-01 Admin. BIdg.

OCT 1 1981

191025

Semiconductor

Measurement Technology

Quarterly Report

July 1 to September 30, 1973
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards' was established by an act of Congress March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology

and facilitate their effective application for public benefit. To this end, the Bureau conducts

research and provides: (I) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau consists of the Institute for

Basic Standards, the Institute for Materials Research, the Institute for Applied Technology,

the Institute for Computer Sciences and Technology, and the Office for Information Programs.

THE INSTITUTE FOR BASIC STANDARDS provides the central basis within the United

States of a complete and consistent system of physical measurement; coordinates that system

with measurement systems of other nations; and furnishes essential services leading to accurate and uniform physical measurements throughout the Nation's scientific community, industry, and commerce. The Institute consists of a Center for Radiation Research, an Office of Measurement Services and the following divisions: Applied Mathematics — Electricity — Mechanics — Heat — Optical Physics — Nuclear

Sciences - — Applied Radiation ' — Quantum Electronics ' — Electromagnetics '' — Time

and Frequency ' — Laboratory A.strophysics ' — Cryogenics

THE INSTITUTE FOR MATERIALS RESEARCH conducts materials research leading to improved methods of measurement, standards, and data on the properties of well-characterized

materials needed by industry, commerce, educational institutions, and Government; provides

advisory and research services to other Government agencies; and develops, produces, and

distributes standard reference materials. The Institute consists of the Office of Standard

Reference Materials and the following divisions: Analytical Chemistry — Polymers — Metallurgy — Inorganic Materials — Reactor

Radiation — Physical Chemistry.

THE INSTITUTE FOR APPLIED TECHNOLOGY provides technical services to promote

the use of available technology and to facilitate technological innovation in industry and Government; cooperates with public and private organizations leading to the development of

technological standards (including mandatory safety standards), codes and methods of test; and provides technical advice and services to Government agencies upon request. The Institute consists of a Center for Building Technology and the following divisions and offices: Engineering and Product Standards — Weights and Measures — Invention and Innovation — Product Evaluation Technology — Electronic Technology — Technical Analysis — Measurement Engineering — Structures, Materials, and Life Safety ' — Building

Environment ' — Technical Evaluation and Application ' — Fire Technology.

THE INSTITUTE FOR COMPUTER SCIENCES AND TECHNOLOGY conducts research and provides technical services designed to aid Government agencies in improving cost effec- tiveness in the conduct of their programs through the selection, acquisition, and effective

utilization of automatic data processing equipment; and serves as the principal focus within

the executive branch for the development of Federal standards for automatic data processing

equipment, techniques, and computer languages. The Institute consists of the following

divisions: Computer Services — Systems and Software — Computer Systems Engineering — Information Technology.

THE OFFICE FOR INFORMATION PROGRAMS promotes optimum dissemination and

accessibility of scientific information generated within NBS and other agencies of the Federal Government; promotes the development of the National Standard Reference Data System and

a system of information analysis centers dealing with the broader aspects of the National Measurement System; provides appropriate services to ensure that the NBS staff has optimum

accessibility to the scientific information of the world. The Office consists of the following

organizational units: Office of Standard Reference Data — Office of Information Activities — Office of Technical

Publications — Library — Office of International Relations.

'Headquarters and Laboratories at Gaithersburg, Maryland, unless otherwise noted; mailing address Washington, D.C. 20234.

' Part of the Center for Radiation Research.

» Located at Boulder, Colorado 80302.

* Part of the Center for Building Technology.
Semiconductor Measurement Technology

Quarterly Report, July 1 {p September 30, 1973

'

\ ^

' r '

'—

W. Murray Bullis, Editor

Electronic Technology Division

Institute for Applied Technology

National Bureau of Standards

Washington, D.C. 20234

Jointly Supported by:

The National Bureau of Standards,

The Defense Nuclear Agency, and The Defense Advanced Research Projects Agency

U.S. DEPARTMENT OF COMMERCE, Frederick B. Dent, Secretary

\ , NATIONAL BUREAU OF STANDARDS, Richard W. Roberts, Direcfor

Issued March 1974

National Bureau of Standards MAY 6 1974
Library of Congress Catalog Number: 74-600040

National Bureau of Standards Special Publication 400-1

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-1, 68 pages (Mar. 1974) CODii,N: XNBSAV

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1974

For sale by tlie Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402 (Order by SD Catalog No. C13.10:400-l). Price $1.15
TABLE OF C 0 N T E ^1 T S

SEMICONDUCTOR MEASUREMENT TECHNOLOGY

PAGE

Preface viii

1. Introduction 1

2. Highlights 3

3. Resistivity; Dopant Profiles • 6 3.1. Spreading Resistance Methods • 6 3.2. Junction Capacitance-Voltage Method 6

3.3. Mathematical Models of Doping Profiles 9 3.4. Diffused Layer Sheet Resistance 11

3.5. Silicon Resistivity Standards 12

4. Crystal Defects and Contaminants 16

4.1. Thermally Stimulated Current and Capacitance Measurements 16

4.2. Energy Level Model for Gold-Doped Silicon 19

5. Insulator Films 20

6. Test Patterns 22

6.1. Process Development 22

6.2. Metal-To-Base Contact Resistor Study 22

7. Photolithography

.

26

7.1. Introduction 26

7.2. Mask Inspection 26

7.3. Photoresist Materials 26

8. -Metallization 28

9. Wafer Inspection and Test 31

10. Die Attachment 32 10.1. Heat Flow Analysis 32

10.2. Void Detection in Transistor Die Attachment 32

10.3. Summary 33

11. Interconnection Bonding 35

11.1. Metallurgical Systems for Ultrasonic Bonding 35

11.2. Burn-out Characteristics of Fine Bonding Wire 35

11.3. Dissemination Activities .... 39

12. Hermeticity 40

13. Thermal Properties of Devices 41

13.1. Thermal Resistance Methods 41

iii
TABLE OF CONTENTS

PA(

13.2. Analysis 4: 13.3. Standardization Activities 4.

14. Microwave Diodes 4' 14.1. Repeatability Studies 4' 14.2. Radiation Hardness Study 4'

15. High-Frequency Measurements 4'

16. References 4*'

Appendix A. Semiconductor Technology Program Staff 5!

Appendix B. Semiconductor Technology Program Publications 5!

Appendix C. Workshop and Symposium Schedule - 51

Appendix D. Standards Committee Activities 5(

Appendix E. Solid-State Technology & Fabrication Services 5{

iv
LIST OF FIGURES

PAGE

Dopant density profiles on the heavily- and lightly-doped sides of a p-n junction as determined from idealized C-V data modified to simulate

a random, normally distributed error with standard deviation of 0.05 percent

in the measurement of C and V 7

Dopant density profiles on the lightly-doped side of a p-n junction as determined from idealized C-V data corrected and not corrected to take

account of the penetration of the space charge layer on the heavily-doped

side 8

Schematic diagram of dopant distribution in silicon-oxide structure showing

both laboratory coordinate, y, and moving coordinate, z 10

Surface dopant density of a p-type Gaussian diffused layer in uniformly

doped n-type silicon as a function of the product of sheet resistance

and junction depth for various background dopant densities, 13

Surface dopant density of an n-type Gaussian diffused layer in uniformly

doped p-type silicon as a function of the product of sheet resistance

and junction depth for various background dopant densities, 14

Surface dopant density of a p-type Gaussian diffused layer in uniformly

doped n-type silicon as a function of the product of sheet resistance

and junction depth for various background dopant densities, , showing the effect of using different relationships between hole

mobility and impurity density in the calculation 15

Dynathermal response of a gold-doped silicon n-MOS capacitor showing

features due to the gold acceptor 17

Isothermal, equilibrium, high-frequency capacitance response of a gold-doped silicon n-MOS capacitor measured at room temperature 17

Dynathermal response of a gold-doped silicon n-MOS capacitor showing

phase I current and phase II current and capacitance response of the

gold acceptor as a function of initial gate voltage, Vgj, for a heating

rate of 9.3 K/s and final gate voltage of -30 V 18

Hall effect activation energy plot for the gold acceptor in n-type silicon ... 18

Photomicrograph of the metal-to-base contact resistor, test structure

No. 16 of test pattern NBS-2 24

Schematic view of a section through the contact window of the metal-to-base

contact resistor test structure pictured in figure 11 24

V
LIST OF FIGURES

PAG

13. Percent increase in junction-to-case temperature difference of diodes

with voids over that of their respective controls measured under steady

state and transient conditions as a function of percent effective void

area in the diode die attachment 33

14. Bond pull strength of ultrasonlcally bonded, 1-mil diameter aluminum

wire, single-level, double bonds as a function of the peak-to-peak

vibration amplitude of the bonding tool tip 36

15. Scanning electron micrograph of the surface of the thick-film gold

metallization used in these ultrasonic bonding experiments 37

16. Scanning electron micrograph of a 5-mil diameter aluminum wire after

burn out on heating to about 1100 "C for 3 min showing the oxide

surface coating 39
LIST OF TABLES

PAGE

1. Mobility Equation Constants 12

2. Measurements on Test Pattern NBS-2; Run No . 2 , 3 23

3. Burn-Out Current for 10-mm Length of Gold Wire 37

4. Burn-Out Current for 10-nun Length of Aluminum Wire 38

5. Comparison of Infrared and Electrical Thermal Resistance Measurements 43

6. Comparison of Infrared and Electrical Thermal Resistance Measurements

for the Round-Robin Test Devices 43

7. Change in Conversion Loss on Repetitive Measurements of 1N23-Equivalent

Schottky-Barrier Diodes 45

8. Change in Conversion Loss on Repetitive Measurements of 1N23-Equivalent

Schottky-Barrier Diodes Selected for Radiation Hardness Study 45

9. Variability of Typical S-Parameter Measurements 48

vii
PREFACE

The Semiconductor Technology Program serves to focus NBS efforts to enhance the performance, interchangeability , and reliability of discrete semiconductor devices and integrated

circuits through improvements in measurement technology for use in controlling device fabrication processes and in specifying materials and devices in national and international commerce. Its major thrusts are the development of carefully evaluated and well documented

test procedures and associated technology, for use on production lines and in the exchange

of devices and materials, and the dissemination of such information to the electronics comI munity. Application of the output by industry is expected to contribute to higher yields, ? lower cost, and higher reliability of semiconductor devices. In addition, the improvements i

in measurement technology will lead to greater econom.y in government procurement and will

provide a basis for controlled improvements in fabrication processes and in essential devicdj

characteristics.

The Program receives direct financial support principally from three major sponsors:

* t the Defense Advanced Research Projects Agency (ARPA) , the Defense Nuclear Agency (DNA)

,

and the National Bureau of Standards (NBS). The ARPA—supported portion of the Program,

Advancement of Reliability, Processing, and Automation for Integrated Circuits with the

National Bureau of Standards (ARPA/ IC /NBS )

, addresses critical Defense Department problems

in the yield, reliability, and availability of integrated circuits. The DNA-supported por- i tion of the Program emphasizes aspects of the work which relate to radiation response of

electron devices for use in military systems. There is considerable overlap between the in-i terests of DNA and ARPA and both interests parallel the measurement-oriented mission of NBS.i

Cooperation with industrial users and suppliers of semiconductor devices is achieved

through NBS participation in standardizing organizations; through direct consultations with i device and material suppliers, government agencies, and other users; and through periodicall

scheduled symposia and workshops. In addition, progress reports, such as this one, are | regularly prepared for issuance in the NBS Special Publication 400 sub-series. More detaile

reports such as state-of-the-art reviews, literature compilations, and summaries of technica

efforts conducted within the Program are issued as these activities are completed. Reports

of this type which are published by NBS also appear in the Special Publication 400 sub-serie

Announcements of availability of all publications in this sub-series are sent by the Government Printing Office to those who have requested this =-^rvice. A request form for this pur^-

pose may be found at the end of this report.

* Through ARPA Order 2397, Program Code UDIO (NBS Cost Center 1+259555).

t Through Inter-Agency Cost Reimbursement Order 714-8II (NBS Cost Center 4259522).

X Through Scientific ... and Technical Research Services Cost Centers 4251126, 4252128 and

4254115.

viii
SEMICONDUCTOR MEASUREMENT T E C H fJ 0 L 0 G Y

QUARTERLY REPORT

JULY 1 TO SEPTEHBER 50, 1973

Abstract: This quarterly progress report, twenty-first of a series,

describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Principal ac- complishments during this reporting period include (1) extension of the technique

for measuring thermally stimulated current and capacitance to include measurements on MOS capacitors, (2) completion of the development of the thermal response

method for evaluation of transistor die attachment, (3) analysis of the interlaboratory comparison of transistor scattering parameter measurements, (4) preliminary review of measurement problems in the photolithographic aspects of semiconductor device processing, of problems associated with certain hermeticity testing

procedures, and of methods for evaluating metallization step coverage, and (5)

initiation of new activity on characterization of oxide films in MOS structures

and analysis of diffusion profiles. Results are also reported on spreading resistance, capacitance-voltage, and sheet resistance measurements; the activation

energy of the gold acceptor in silicon; evaluation of the base-to-metal contact

resistor test structure; metallurgical systems for ultrasonic bonding; burn-out

characteristics of fine gold and alxominum bonding wire; transistor thermal re- sistance measurements; and microwave diode conversion loss measurem.ents . Supplementary data concerning staff, publications, workshops and symposia, standards

committee activities, and technical services are also included as appendices.

Key Words: Contact resistance; die attachment; dopant profiles; electrical

properties; electronics; gold-doped silicon; hermeticity; metallization; methods

of measurement; microelectronics; microwave diodes; mobility; MOS devices; oxide

films; photomasks; photoresist; resistivity; resistivity standards; scanning

electron microscopy; semiconductor devices; semiconductor materials; semiconductor process control; sheet resistance; silicon; S-parameters ; spreading resistance; test patterns; thermal resistance; thermally stimulated capacitance;

thermally stimulated current; wire bonds.

1. I N T R 0 D U C T I 0 N This is the twenty-first quarterly report to the sponsors of the Semiconductor Technol-

• Program. It summarizes work on a wide variety of measurement methods for semiconductor

;erials, process control, and devices that are being studied at the National Bureau of

i^ndards. The Program is a continuing one, and the results and conclusions reported here

\

"t subject to modification and refinement.

j The work of the Program is divided into a number of tasks, each directed toward the

\Ay of a particular material or device property or measurement technique. This report is

'divided according to these tasks. Highlights of activity during the quarter are given in

tion 2. Subsequent sections deal with each specific task area. References cited are

ted in the final section of the report.
INTRODUCTION

The report of each task includes a narrative description of progress made during this

reporting period. Additional information concerning the material reported may be obtained

directly from individual staff members identified with the task in the report. The organization of the Program staff and telephone ntmibers are listed in Appendix A.

Background material on the Program and individual tasks may be found in earlier quarterly reports as listed in Appendix B. From time to time, publications are prepared which

describe some aspect of the program in greater detail. Current publications of this type

are also listed in Appendix B. Reprints or copies of such publications are usually available on request to the author.

Communication with the electronics community is a critical aspect both for receiving

guidance in planning future program activities and for disseminating results of the work

to potential users. Formal channels for such communication occur in the form of workshops

and symposia sponsored or co-sponsored by NBS. Currently scheduled seminars and workshops

are listed in Appendix C. In addition, the availability of proceedings from past workshops

and seminars is indicated in the appendix.

An important part of the work that frequently goes beyond the task structure is partic-'

ipation in the activities of various technical standardizing committees. The list of personnel involved with this work given in Appendix D suggests the extent of this participation

In many cases, details of standardization efforts are reported in connection with the work

of a particular task. Current standardization activities, including those not associated

with a particular task, are summarized at the end of section 2.

Technical services in areas of competence are provided to other NBS activities and

other government agencies as they are requested. Usually these are short-term, specialized

services that cannot be obtained through normal commercial channels. To indicate the kinds

of technology available to the program such services provided during the period covered by

this report are listed in Appendix E.
2. HIGHLIGHTS

Considerable expansion in the scope of the program occurred during this reporting period

|.h the inclusion of a new effort on Advancement of Reliability, Processing, and Automation

Integrated Circuits with the National Bureau of Standards (AEPA/IC/NBS) funded by the ense Advanced Research Projects Agency. New tasks were established in the areas of insu-

'or films, photolithography, and hermeticity.

Significant technical accomplishments during this reporting period included:

1. extension of the technique for measuring thermally stimulated current and

capacitance to include measurements on metal-oxide-semiconductor (MOS)

capacitors

I 2. completion of the development of the thermal response method for

evaluation of transistor die attachment,

3. analysis of the interlaboratory comparison of transistor scattering

parameter measurements, and

4. preliminary review of measurement problems in the photolithographic

aspects of semiconductor device processing, of problems associated with

certain hermeticity testing procedures, and of methods for evaluating

metallization step coverage.

I In addition, the first of a series of workshops to aid in communication with the elec-

•nics community was held. This workshop, on measurement needs for controlling integrated

rcuit processing and assembly, had the dual objectives of formally announcing the

'A/IC/NBS program to the semiconductor industry and of giving the industry a forum to pro-

(e additional input for use in program definition and planning. The results of the workup are reported in detail elsewhere [1].

Following are highlights of other activities during this quarter.

I Resistivity3 Dopant Chccpacterization — Development of calibration curves for the OTS

•eading resistance system continued with generation of the curve for n-type silicon in the

|ige 0.1 to 100 fi'cm. Theoretical study of the application of the junction capacitance-

.tage method for measuring diffusion profiles continued with evaluation of the effect of

idom errors in the measured values of capacitance and voltage on the derived net dopant

isity on either side of the junction. Mathematical analysis of the boron redistribution

>blem began with formulation of the problem for both uniform and nonuniform initial distbutions. The effect of uncertainty in mobility value on diffusion profiles derived from

Lremental sheet resistance measurements was studied by comparing results obtained with the

e of two different relationships for hole mobility as a function of impurity density in

';ype silicon. A multipass round-robin experiment between NBS and six experienced laboraries was designed to test the stability and multilaboratory precision to be expected from

|i silicon resistivity standard reference materials now available.

Crystal Defects and Contaminants — The dynathermal current and capacitance responses

a gold-doped n-MOS capacitor were found to display two distinct features: one, which is

3
HIGHLIGHTS

similar to the feature in the junction response, is characteristic of electron emission from

the gold acceptor, and a second at higher temperature, which is not found in the junction re

sponse, is characteristic of hole emission from the gold acceptor. Additional Hall effect

measurements on a specimen of n-type silicon with a phosphorus density about 10^^ cm~^ and a

gold density about three times greater yielded an activation energy vjithin less than 1 meV

of that obtained earlier on a less heavily doped specimen.

Insulator Films — Studies of silicon oxide films by ion microprobe mass analysis,

electron spectroscopy for chemical analysis, and Auger spectroscopy are being initiated.

Apparatus is being designed and constructed for use in studying the bias-temperature stress

test for characterizing oxide stability. At the request of one of the major sponsors, a program has been initiated to document procedures and tests necessary to achieve radiationhardened MOS integrated circuits.

Test Patterns — Several modifications were made in the processing procedure as part

of a continuing task to demonstrate the application of test patterns in improving and con- trolling fabrication processes. Although some improvements were made, further iterations

are needed to achieve desired values for various characteristics. Study of the metal-tobase contact resistor test structure showed that although the normalization of the measured

contact resistance is uncertain, this structure is suitable for identifying deviations from

nominal values of contact resistance which might occur in a production run.

Wafer Inspection and Test — Construction was begun of an optical flying-spot scanner

for use in evaluating damage to device structures during inspection or test with a scanning

electron microscope.

Interconnection Bonding — Characterization of metallurgical systems for ultrasonic

bonding continued with confirmation of the previously reported high bond strength for gold

wire on aluminum pads, tentative establishment of suitable bonding conditions for gold wire

on gold thick-film metallization, and determination of compatible schedules for bonding

aluminum wire both to aluminum thin-film bonding pads on silicon dioxide over silicon and

to gold thick-film metallization on alumina substrates. A brief study was carried out on

the burn out of fine gold and aluminum wire as a result of Joule heating. In addition to the technical effort, dissemination of the methods and technology developed for controlling

and testing ultrasonic wire bonding continued at a high level throughout this period.

Thermal Properties of Devices — Repeatability tests of the emitter-base voltage,

emitter-only switching technique for measuring thermal resistance of transistors were completed. Additional calculations with a somewhat more complex model were carried out to establish an appropriate extrapolation procedure for use in analyzing thermal resistance

measurements; as in the simpler case, a plot of the logarithm of surface temperature as a function of time results in the most nearly straight lines over the appropriate range of

delay times.

4
HIGHLIGHTS

] Microwave Diodes — Additional repeatability studies of the conversion loss measurement

'stem were made using Schottky-barrier mixer diodes. Groups of diodes were selected for

» in a study of the effect of gamma and neutron irradiation on the noise characteristics

these diodes.

Standardization Activities — Fifteen staff members participated in the fall meetings

ASTM Committee F-1 on Electronics, held in Palo Alto, California, on September 5-7. Most

30 assisted with the first ARPA/NBS Workshop, held on the final day of the Committee

2tings.

j' Editorial work was carried out on five ASTM Committee F-1 draft documents and was

;Ltiated on an EIA-JEDEC document. Two documents were reviewed technically for other

andards groups. Work continued on two round-robin experiments being conducted by ASTM

littee F-1.

' Dissemination Activities — Organizational activities were undertaken for a workshop on

jdiation Effects in MOS Technology. This workshop, cosponsored by the IEEE Nuclear and

jasma Sciences Society, the IEEE Electron Devices Group, and MBS, is scheduled for December

'and 7, 1973, at Washington, D. C. No proceedings of this Workshop are to be printed.

j Planning activity also continued for the Spreading Resistance Symposium, scheduled for ne 13-14, 1974, at Gaithersburg, Maryland (NBS Tech. Note 788, p. 64). This symposium is

[sponsored by ASTM Committee F-1 and NBS. It will immediately follow the June meeting of

'ie committee.

Hermeticity was selected as the subject of the second ARPA/NBS Workshop, which is

peduled to be held on March 29, 1974, at Gaithersburg, Maryland. Topic areas to be disissed include failure due to leaks (correlation of leak rate and failure, failure mechanisms,

ntamination analysis, and nature of leaks) and evaluation and intercomparison of leak rate

esurement procedures (helium mass spectrograph, radioisotope, and new methods).

} The third ARPA/NBS Workshop was tentatively scheduled for September 5 and 6 in Scotts-

|le, Arizona. The subject of this Workshop is design, evaluation, and use of test patterns.

I is designed to follow and supplement an informal mini-symposium on test patterns planned

;p: the January meeting of ASTM Committee F-1 in New Orleans.
3. RESISTIVITYj DOPANT PROFILES

3.1. Spreading Resistance Methods

In preparation for constructing a calibration curve for phosphorus-doped silicon, a series of wafers was screened for radial uniformity using the spreading resistance instrument. Each wafer was freshly chem-mechanically polished on the surface to be probed by

spreading resistance and lapped on the opposite side. Four-probe resistivity measurements

were made on the lapped surface of 13 wafers which showed less than 10 percent variation in

spreading resistance within the central half-radius region. These had room temperature re- sistivity in the range from about 0.1 to 100 J^'cm. There was a linear relationship between

spreading resistance and resistivity as measured by the four-probe method, but there were

discrepancies of as much as 30 percent from the line of regression. No further work will be

undertaken until a more complete set of specimens of n-type material is available to fill

out the calibration curve.

Discrepancies of 50 to 80 percent in the calibration of spreading resistance for high

resistivity boron-doped wafers, previously reported, have not yet been explained. A set of

wafers adjacent to those which yielded some of the most discrepant points previously observed in this p-type material was prepared by the same chem-mechanical polishing treatment

as before but measurement of these wafers has not yet been completed.

(J. R. Ehrstein and D. R. Ricks)

3.2. Junction Capaci tance- Vol tage Method

Theoretical investigation continued into the feasibility of using capacitance-voltage

(C-V) measurements to profile a layer diffused into homogeneous background material. Previously, it was shown that this method requires the background dopant density, N, , to be

b known to 1 percent or better in order to obtain a reasonably accurate diffused-layer profile (NBS Tech. Note 806, pp. 10-12). In the present phase, effects of variation in measurement of capacitance and voltage on the profile wfere studied. As an illustration,

idealized C-V data corresponding to junction voltage between 0.3 V forward bias and 100 V reverse bias were generated for the case of a Gaussian diffusion in which the surface dopant

density, N^, was 10-^^ cm"^, the junction depth, X_. , was 1.0 ym, and N^ was 10-^^ cm~^. The

relative capacitance interval, AC/C, was taken to be 10 percent around zero bias, decreasing

to 6 percent at large reverse bias. These ideal data were permuted using random numbers to simulate a measurement error of 0.1 percent (two standard deviations) in both C and V. No

systematic error was assumed. These permuted data were then processed to compute dopant

profiles on both the lightly-doped (homogeneous) and the heavily-doped (diffused- layer)

sides of the p-n junction. A composite of these profiles is shown in figure 1. It can be seen that the scatter in the diffused-layer profile significantly exceeds that of the profile on the homogeneous side. Larger and more commonly encountered errors in C would in- crease the scatter of both profiles but would have a more pronounced effect on the diffusedlayer profile. For the conditions considered here the practical range over which one can profile a diffused layer is limited to dopant densities between 6 and 30 times the

6
RESISTIVITY; DOPANT PROFILES

T

\ 1 r

DISTANCE FROM JUNCTION (>itn)

Figure 1. Dopant density profiles on the

heavily- and lightly-doped sides of a p-n

junction as determined from idealized C-V data

modified to simulate a random, normally distributed error with standard deviation of 0.05

percent in the measurement of C and V. (The

doping density profile on the heavily-doped

side was assumed to be Gaussian with surface

doping density of 10^^ cm"^ and junction depth

of 1.0 ym ,as shown by the solid curve to the

left of the origin. One point on the heavilydoped side of the junction, 2.28 x 10^^ cm'^

at 0.6 ym, fell outside the range of the plot.

The doping density on the lightly-doped side was taken as 10-^^ cm~^.)

)

: ikground dopant density. In this range the measured value of the diffused-layer dopant

Isity is within a factor of two of the true value.

i

1 In addition to errors introduced by measurement error in the capacitance and the relae capacitance ratio, which have been considered by Amron [2], the error in the computed

Ifused-layer profile is increased by the interaction of these two effects with the differ-

] ije of large numbers called for in the data reduction algorithm. The net dopant density,

,.) , on the heavily-doped side of the junction at the edge of the space-charge region which

! penetrated a distance A from the junction is [3]

1 N(A)-^ = N(W)-1 - N(B)-^ (1)

lire the total space-charge width W = A + B and N(B) is the net dopant density on the

jhtly-doped side of the junction at the edge of the space-charge region which has penetrated

jistance B from the junction. The quantities derived from capacitance-voltage values are

'o and W. When N(A) becomes large compared to N(B) , as in the case of an abruptly diffused

.ction, N(B) and B approach N(W) and W, respectively. In the data reduction algorithm,

j>) and B are estimated. As N(B) and B approach N(W) and W, respectively, the calculated

l.ues of N(A) and A become much less reliable.

I

I A theoretical study was also made of the error found in the profile of the lightlyj'ed side of various diffused junctions when the diffused-layer correction [3] is not ap-

.ed. Such information is useful in quantifying these errors and in providing guidelines

developing diffusion schedules which will minimize the need for these corrections.

The diff used- layer correction accounts for the fact that the space-charge layer peneites not only the lightly-doped side of the junction but also the heavily-doped diffused

7
RESISTIVITY; DOPANT PROFILES

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CO T3 C

(U (U O. 13 Oa 4J

I c

>^ CO ^ .H O- • •H O

> 13 -O

(U <U H I (u e

J3 CJ

4-1 • o

CO

01 rH

•H 13

<4H CU O 4J u o

a. CU

>-i >^ u

4J o

•H O

COC2 4-1 0) O

C

4-1 -a SCO CO a.o ^Q O

. 13

C--J CU 4J

CU o

(-1 (U 3 ^

•H O

a

CU O rH

13C

14H 14-1 CO o o u

4-1 O

CU 13 ro

I C B O o

•H

4-1 Ln C O

3 rH

CU H c"

13

CO ^

13-1 ^

•r( O O

CO rH rH

8
RESISTIVITY; DOPANT PROFILES

jyer. As above, the junctions were assumed to be formed by a Gaussian diffusion into

if ormly-doped background material. The junction depth, X., was taken as 1.0 pm and the

rface dopant density, N^, was taken as 10^^ cm~^. Corrected and uncorrected profiles were

Iculated from idealized C-V data for which the voltage ranged from 0.3 V forward bias to eakdown or 100 V (whichever is smaller) and for which the capacitance was decremented apoximately 10 percent for each successive C-V data pair. Profiles calculated for backjound dopant densities, , of 10 10^^, 10^^ and 10^ cm~^ are shown in figure 2.

The uncorrected profiles, N(W) vs. W, are represented by squares, and the corrected

ofiles, N(B) vs. B, are represented by circles. Connecting lines join data points obined .f rom the same C-V data pair. Note that the uncorrected profiles give erroneously low

lues of dopant density which gradually approach the correct value at large distances

om the junction. Note also that the uncorrected profiles give erroneously large values

r the distance from the junction. This is important when profiling epitaxial layers, for causes the epitaxial-substrate interface to appear farther from the junction than it

tually is. Also illustrated is the fact that the errors increase as N^ approaches N^.

The profiles of figure 2 are valid for both p^n or ri^p junctions. Peripheral effects

ve been neglected and dopant impurities were assumed to be fully ionized. When calculatg the capacitance and voltage, the dielectric constant of silicon was assumed constant

th a value 1.036 x 10~^^ F/cm and the built-in voltage was taken as 0.7 V. For materials

th a different dielectric constant, the respective loci of the N(W) vs. W and N(B) vs. B rves would be unchanged, but a particular point on a locus would correspond to a different

pacitance-voltage pair. (R. L. Mattis and K. G. Buehler)

3. Mathematical Models of Doping Profiles

To couple laboratory efforts on production and measurement of doping profiles in sili-

, a mathematical study of the diffusion and oxidation processes was begun. The initial

ase is directed toward solution of the problem of redistribution of impurities during the

dation of silicon considering both uniform and nonuniform initial impurity distributions

^ the silicon.

' When a silicon wafer is thermally oxidized, silicon comes from the wafer to form the

..licon dioxide. This means that during the oxidation, the silicon surface moves with rellect to its original position. As oxidation proceeds, dopant atoms in the silicon are ' in

isence either rejected from the oxide or incorporated into the oxide. This effect causes pant atoms to be redistributed within the silicon.

A mathematical description of the physical processes involved in this redistribution

oblem has been given elsewhere [4-7]. These authors consider the dopant impurities to be

jisentially uniformly distributed in the silicon prior to oxidation. It is the purpose of

le present study to use numerical methods to solve for the final dopant profiles where

initially the dopants are either uniformly or nonuniformly distributed within the silicon.
RESISTIVITY; DOPANT PROFILES

OXYGEN

ORIGINAL

SILICON —

SURFACE

OXIDE

/

SILICON

Zo

I 1—

0 Yo

-Z

Y

Figure 3. Schematic diagram of dopant

distribution in silicon-oxide structure

showing both laboratory coordinate, y, and moving coordinate, z.

As in previous work [4-7], the silicon is treated mathematically as a semi-infinite

slab with its surface exposed to heated oxygen. As shown in figure 3, the y-axis of the

laboratory frame extends into the slab perpendicularly to the surface. In this analysis,

the oxide thickness, ZgCt), is assumed to increase parabolically with time according to

Zo(t) = kt^l^ (2)

where A is a proportionality constant. The position of the oxide-silicon interface at time

t with respect to the initial silicon surface is given by

(3)

yo(t) = azo(t)

where a is some constant fraction.

The kinetics of the oxide-layer growth [6] are such that all the increase in volume

undergone by a thin layer of silicon when it is oxidized takes place at the oxide-silicon

interface. Away from this growth front the oxide is being uniformly convected to the left

with a speed (1 - a)dzQ(t)/dt relative to the laboratory frame. Consequently, there is both

diffusive and convective transport of the impurity in the oxide. It is convenient to introduce a moving coordinate system, z = y + (1 - a)zo(t), in the oxide layer with its

origin at the oxide surface. Then the impurity concentration in the oxide, Ci(z,t), obeys,

in the moving frame, the simple diffusion equation

9Ci(z,t)/8t = Di82Ci/3z2 (4)

for 0 < z < Zg(t). In the silicon there is only diffusion; therefore, in the laboratory

frame

3C2(y,t)/9t = D292C2/9y2 (5)

for y > ygCt) where C2(y,t) is the impurity concentration in the silicon.

At the oxide-silicon interface, Ci and C2 are coupled for t > 0 by the equilibrium

condition

C2[yo(t).t] = mCi[zo(t),t] (6)

10
RESISTIVITY; DOPANT PROFILES

ere m is the specified segregation (or distribution) coefficient. Another condition,

plicable to the oxide-silicon interface, follows from the conservation of mass:

C2(yo.t)(ct - m-l)dzn/dt = Di9Ci/3z| _ - DzSCa/Syl _ . (7) z-Zq Y-Yq

,e boundary condition at the oxide-oxygen interface is assumed to be

Ci(0,t) = Cs (8)

ere is a specified constant. This assumption is somewhat arbitrary; an alternative

ndition which could be assumed at this interface is 9Ci/3z = 0 [6].

Equations (4) through (8) and the uniform initial condition, C2(y,0) = C^, where is

constant background concentration, specify the uniform redistribution problem. It has

alytic solutions given elsewhere [5,6] for specific cases. This class of problem is apicable to MOS devices. Equations (4) through (8) and the nonuniform initial condition for

> yo> C2(y,0) = C(y), where C(y) is a nonuniform dopant concentration, specify the nonunirm redistribution problem. This class of problem is applicable to diffused and implanted

;yers in bipolar silicon devices.

With these formulations of the redistribution problem, it is possible to develop numerial solutions for a variety of cases including the oxidation of silicon slices both uniIrmly doped and diffused with boron. (S. R. Kraft and M. G. Buehler)

Diffused Layer Sheet Resistance

In the fabrication of semiconductor devices it is common practice to obtain the surface

pant density, Nq , of a diffused layer from the measurement of the diff used-layer sheet restance, R ; the junction depth, X.; the background dopant density, N, ; and an assumed funcS J D onal form for the diffused layer. Irvin [8] has expressed these relations graphically by

ing his well-known curves which relate resistivity, and hence carrier mobility, u, to

ipant density, N^, by means of straight-line approximations. Recently, empirical expres-

'ons [9] have appeared which relate the carrier mobility data of Irvin to dopant density,

re recently, Wagner [10] has published a modified hole mobility expression based on his

rk on boron-implanted silicon. These expressions have the form

mm + (y - y .„)/[l + N./N ^f)""] (9) max mm i rer

,'ere the constants, y , y . , N and a, are listed in table 1.

' max mxn ref

The expression for the sheet resistance R^ of a diffused layer with a Gaussian profile

R^-1 = q f y(N - N, )dx (10)

s Q b

fere q is the electronic charge, y is given by eq (9) with N = N + N, , N = N„ exp(-x^/L^),

NBS Applied Mathematics Division

11
RESISTIVITY; DOPANT PROFILES

Table 1 — Mobility Equation Constants

Type y , Cm^/V'S

max

a

_ 3 cm ^ Reference

n 1330 65 0 72 8. 5 X 10^° [9]

P

495 47.7 0 76 6.3 X lOis [9]

P

495 47.7 0 76 1.9 X 1017 [10]

and L = X. [«.n(No/N^) ] 1' ^ . Surface dopant density is plotted as a function of the product of

R and X. in figure 4 for a p-type layer diffused into uniformly doped n-type silicon and in

figure 5 for an n-type layer diffused into uniformly doped p-type silicon. This form of

presentation is more convenient for direct use by a process engineer than the form employed

by Irvin [8]. Since curves in figure 5 are based on Caughey and Thomas' fit to Irvin's

data, the curves are similar to those which appear in Irvin [8], but differences occur for

No > 10^° cm~^ where the expression of Caughey and Thomas fails to fit Irvin's data. The

curves in figure 4 are based on Wagner's mobility expression.

The importance of the value of hole mobility assumed in computing the sheet resistance

is illustrated in figure 6. For example, there is a difference of a factor of two between

values for the surface dopant density for N, = 10^^ cm~^ and R X. = 1000 J^'ym calculated

b s J using the two expressions. As indicated previously (NBS Tech. Note 806, pp. 21-23), the

hole mobility at Nj = lO^^ cm"^ is about 240 cm^/V's from Caughey and Thomas [9], whereas

from Wagner [10] it is about 340 cm^/V's. Similar differences occur throughout much of the

impurity density range of interest. (T. E. Griffin and M. G. Buehler)

3.5. Silicon Resistivity Standards

A simple multipass round-robin experiment has been designed to test both the stability

and the multilaboratory precision which can be expected from the silicon resistivity standard reference materials now available from NBS (NBS Tech. Note 806, pp. 8, 66). This

experiment is to involve NBS and six other laboratories who have previously collaborated

with ASTM Committee F-1 on Electronics in the measurement of bulk silicon resistivity. In the experiment itself each laboratory is expected to measure two sets of standard reference

material wafers to be circulated among the laboratories specifically for this test in addition to submitting data taken at specified intervals on the standard silicon wafers which it owns. The experiment is expected to begin soon after the participating laboratories obtain

their sets of standards and to run for 12 to 18 months. (J. R. Ehrstein and F. H. Brewer)

12
Figure A. Surface dopant density of a p-type Gaussian diffused layer in uniformly

doped n-type silicon as a function of the product of sheet resistance (300 K) and

junction depth for various background dopant densities, N, .

13
RESISTIVITY; DOPANT PROFILES

SHEET RESISTANCE JUNCTION DEPTH PRODUCT (XI /a m)

Figure 5. Surface dopant density of an n-type Gaussian diffused layer in uniformly

doped p-type silicon as a function of the product of sheet resistance (300 K) and

junction depth for various background dopant densities, N .

14
RESISTIVITY; DOPANT PROFILES

SHEET RESISTANCE JUNCTION DEPTH PRODUCT (a-ftm)

Figure 6. Surface dopant density of a p-type Gaussian diffused layer in uniformly

doped n-type silicon as a function of the product of sheet resistance (300 K) and

junction depth for various background dopant densities, , showing the effect of

using different relationships between hole mobility and impurity density in the

calculation.

15
^. CRYSTAL DEFECTS AMD CONTAMITiANTS

4.1. Thermally Stimulated Current and Capacitance Measurements

The dynathermal current and capacitance response of the gold acceptor were measured

in a gold-doped n-MOS capacitor. The capacitor was fabricated on the same gold-doped die

as the previously studied gold-doped p^n junction (MBS Tech. Note 806, p. 13). The MOS

capacitor had a 20-mil (0.5-mm) diameter gate on a 0.5-ym thick oxide which was thermally

grown on a 10-n*cm n-type silicon epitaxial layer. The capacitor was mounted on a TO-5

header along with a temperature sensing diode. This configuration and an inexpensive cryostat used for the measurements have been described previously (NBS Tech. Note 806, pp. 13-

16).

The dynathermal current and capacitance response of the gold-doped n-MOS capacitor is

shown for various heating rates in figure 7. ITie gold defect centers were charged by

increasing the gate bias to Vg2 = -30 V from a value Vgi = -15 V which was applied at room

temperature and held on the capacitor as it was cooled to liquid nitrogen temperature. The

value of Vgi was such that an inversion layer of holes is formed at the oxide-silicon interface. This layer prevents the fast surface states from acting as hole and electron generation centers. An isothermal C-V plot, shown in figure 8, illustrates the gate voltage for

which inversion is achieved.

The dynathermal response of figure 7 indicates the presence of two distinct phenomena.

The first occurs at about 225 K when electrons are released from the gold acceptor; this is

termed the majority carrier, phase I response. The second occurs at about 280 K where holes

govern the generation rate of the gold acceptor; this is termed the minority carrier, phase

II response.

The heating rate dependence of the current and capacitance response, as illustrated in

the figure, indicates that the peak in the current 1^ during the majority carrier, phase I response occurs at emission temperatures which shift from 218 to 235 K. This is in good

agreement with values obtained for the gold doped p^n junction reported previously. The

peak in the current during the minority carrier, phase II response occurs at emission temperatures which shift from 273 to 292 K depending upon the heating rate. The capacitance

step also shifts with heating rate and for the majority carrier, phase I response, the shift

is similar to that observed in the p^n junction. From the capacitance values C2li and C2lf»

the gold density N^ can be found from the expression originally derived for the case of a p n junction [11]

2(Vg2 - Vgi) Ci^ (C2lf2 - Czli^) (en + ep)

N (11)

q£A2(Ci2 - C2lf^) (Ci^ - C-ilt'^)

where e and e are the electron and hole emission rates [12], q is the electronic charge,

n p

e is the dielectric constant of silicon, and A is the area of the MOS capacitor. For this

MOS capacitor it was found that N = 2.2 x 10^^ cm"^. It is interesting to note that when

16
CRYSTAL DEFECTS AND CONTAMINANTS

I 1 1

INVERSION

1 1

c,

1 -

A /

"DEEP DEPLETION

B —-A-

/ C2II

1 I 1 1 1 1

Figure 7. Dynathermal response of a golddoped silicon n-MOS capacitor showing features due' to the gold acceptor. (Heating

rate: 1.6 K/s, curves A; 4.8 K/s, curves B; and 9.3 K/s, curves C; Device 2107.7. The

left hand current scale refers to the curves labeled Ij and the right hand current scale to the curves labeled Iji. The

scale of the lower capacitance curves is

expanded to show the Phase I capacitance

transition which cannot be distinguished

on the upper curves. The deep depletion

condition, as indicated by the label on the upper capacitance curves, occurs when

the potential is changed in a time short

compared with the emission time constant

at the temperature of the change, in this case "^77 K. The capacitance curves labeled

*-'2li> '^2If> and C211 were measured at a gate voltage of Vg2 = -30 V. The topmost

capacitance curve, Cj, was measured at Vgi = Vg2 = -30 V, but would have been the same if

measured at Vgi = Vg2 = -15 V.)

180 200 220 240 260 280 300 320

TEMPERATURE (K)

15

|;|gure 8. Isothermal, equilibrium, highrequency capacitance response of a goldf'ped silicon n-MOS capacitor measured at om temperature. (Device No. 2107.7.)

Uiu

10

<

Q.<

ACCUMULATION

A-DEPLETION

inversion/

-20 -10 0

GATE VOLTAGE (V)

10

17
CRYSTAL DEFECTS AND CONTAMINANTS

10

8

6

4

2

0

1.0 <

Q-0.8

^ 0-6 q:a.^0.4

(J

u.Q.

HIo

<o

<

CL<o

0.2

Q

1 1 1 1

Vgl = - 30V

1 1

-25V

777^

-20V

- 15 V J:

-10V

1 1 1 1 1 1

I 1/ Ml 1 1

It J 1 -Vgl = - lOV -W 1 / / - -15V--^/ / i

'

- 20Vx/ / /

/ - 15V-/_ \

/ - 20VA' \\

-25Vy/

i

-25V/V\\|

100 <

80 ^

60

1-z

UJ

q:

q: 4C ^o

- 20

0

180 200 220 240 260 280 300 320

TEMPERATURE (K)

Figure 9. Dynathermal response of a golddoped silicon n-MOS capacitor showing

phase I current and phase II current and

capacitance response of the gold acceptor

as a function of initial gate voltage,

Vgl, for a heating rate of 9.3 K/s and

final gate voltage of -30 V. (Device No. 2107.7. The curves for Vgi = -15 V, cor- respond to curves C in figure 7.)

T(K)

Figure 10. Hall effect activation energy

plot for the gold acceptor in n-type silicon. (Specimen 5N950-144.)

18
CRYSTAL DEFECTS AMD CONTAMINANTS

iie capacitance pulls out of deep depletion and reaches its inversion value, the current

jirough the MOS capacitor shuts off.

The bias dependence of the current and capacitance dynathermal response is shown in

Igure 9 for a heating rate of 9.3 K/s and Vg2 = -30 V. Since Vgi = Vg2 for the topmost

^pacitance curve, there is no charging of the space-charge layer. In the figure it is

^en that the peak in the majority carrier phase I current, Ij., is independent of bias and

Incurs at 235 K. The peak in the minority carrier phase II current, Ij-j-* is somewhat bias

tependent, for this peak depends on the space-charge width which, as seen in the capacitance

Bsponse, is bias dependent. If Vgi is more positive than -10 V, hole inversion does not

,2cur at the oxide-silicon interface and the generation centers there cause excess leakage

,arrents which greatly distort the current response. (W. E. Phillips and M. G. Buehler)

12. . Energy Level Model for Gold-Doped Silicon

The activation energy of the gold acceptor in silicon was determined from measurements

j|f the Hall coefficient as a function of temperature on a phosphorus-doped specimen with an

fnitial room temperature resistivity of 5.3 J^'cm. Gold was evaporated on both sides of the

ffilicon wafer and diffused at 950°C for 144 h; then both wafer faces were lapped to a depth

f 125 ym to remove excess surface gold before ultrasonically cutting a Hall bar for the

lectrical measurements. The room temperature resistivity after gold diffusion was

i.9 X lO** f2*cm. A gold density of 3.3 x 10^^ cm~^ was determined by neutron activation

]Inalysis on a specimen from the same wafer as the Hall bar.

The activation energy of the gold acceptor was computed from the data shown in figure

D by means of a least squares analysis [13] for the slope. The data points included in the

I:nalysis are shown by circles; the points excluded because of their deviation from linearity

re shown as squares. The calculated energy of 0.5381 ± 0.0004 eV represents the value at ero kelvin of the energy difference between the conduction band edge and the gold acceptor

jevel with the assumption that this difference is a linear function of temperature. The

ncertainty in the energy is the square root of the estimated variance of the slope and does

jot take into account systematic errors which might be present [14]. The energy difference

Ibtained from this specimen is in good agreement with the value of 0.5373 eV measured preI iously on another specimen (NBS Tech. Note 773, pp. 13-14).

(W, R. Thurber and M. G. Buehler)

19
5. INSULATOR FILMS

Characterization of silicon dioxide and other insulator films in metal-insulatorsemiconductor (MIS) device structures is an essential aspect of obtaining the stable insulator characteristics needed for the reliable operation of MIS integrated circuits. One

particularly critical class of problems relates to the radiation sensitivity of thermally

grown silicon dioxide in MOS devices.

The observed instability of silicon which is induced by ionizing radiation and is manifested by the build up of positive charge is believed to be due to hole trapping [15]. Optical absorption measurements and electron parametric resonance data indicate that the

density of hole traps in silicon dioxide tends to increase with increased sodium concentration. Non-bridging oxygen atom.s are known to behave as hole traps and to be enhanced by

the presence of alkali impurities [16]. Consequently, the increased density of non-bridging

oxygen atoms arising from the presence of sodium contamination seems to be to blame for the

observed oxide behavior.

Large concentrations of sodium are located at both the metal and silicon interfaces of

dry, thermally grown silicon dioxide [17, 18]. Just how the sodium distribution relates to

the radiation sensitivity of an MOS structure needs to be explored. Ion microprobe mass

analysis (IMMA) is a highly sensitive technique with which the sodium profile can be examined. There is, however, some concern about perturbing the impurity atom profile during ion

sputtering. To assess the nature of this and other problems associated with this application of IMI4A, detailed study of this technique is being started in cooperation with the NBS

Analytical Chemistry Division. Initially, measurements are being made of several silicon

dioxide-silicon structures, one of which was implanted with 80 keV sodium ions to a density

10 '•^ cm~^. This study will employ the ion microprobe mass analyzer at NBS.

Another technique, electron spectroscopy for chemical analysis (ESCA) , can lead to a basic understanding of the perturbing effects of sodium on silicon-oxygen bonding and hole

trapping. With this technique only a very shallovz surface layer is explored. A study of

growth characteristics of silicon dioxide in the presence of impurities, such as sodium, is

being planned in cooperation with the NBS Physical Chemistry Division.

(D. C. Lewis and A. G. Lieberman)

The vacuum capability of the apparatus to be used for this study has been improved by

two orders of magnitude by replacing the elastomer O-rings by machined gold rings. As a consequence, the sensitivity level is now 5 percent of a monolayer or an impurity surface

density of about 10^^ cm~^. Although sodium ion densities 100 times less than this can cause electrically observable effects in MOS devices, it is assumed that data obtained at detectable impurity densities can be extrapolated to situations of lesser density.

These specimens consisting of a O.S-ym thick film of silicon dioxide, grown at 1000°C

followed by a 20 min anneal in nitrogen, on a <100> surface of 7 to 13 Q'cm, p-type silicon were supplied by H. L. Hughes of the Naval Research Laboratory.

20
INSULATOR FILMS

i An Auger electron gun is available which can be added to this ESCA spectrometer to

jbtain resolutions as small as 0.7 eV, five times better than the resolution of commercially

vailable Auger apparatus. (N. E. Erickson and J. T. Yates )

Oxide stability is m.ost often characterized electrically by means of the blasemperature stress test [19] in which shifts in flat-band voltage of an MOS capacitor are bserved after stressing with an applied voltage at some elevated temperature. In preparaion for detailed study of this test, a hot-cold stage with appropriate electrical feedhroughs is being designed and constructed. (M. G. Buehler and A. W. Stallings)

A substantial research effort to develop radiation hardened MOS integrated circuits has

'een supported by various government agencies for the past several years. The results of

'his work are reported in scattered locations and in a number of different formats. Conseuently, it is difficult to obtain a complete picture of the process technologies proposed

or producing such circuits and to ascertain their relative merits. At the request of one

|E the sponsors of the Program, an effort has been initiated to document process technology

|ad test procedures which have been developed under government contract.

(A. G. Lieberman and E . C. Lewis)

j

I

I

I

,i

NBS Physical Chemistry Division

21
6. TEST PATTERNS

6.1. Process Development

Several modifications were made in the processing procedure as part of a continuing

task to demonstrate the application of test patterns in improving and controlling fabrication processes. Run No. 2.3 was made on four 3-fi*cm, n-type bulk silicon slices and four

10-fi'cm, n/ri' epitaxial silicon slices; two slices of each type were doped with gold to a density of about 10^^ cm"^. The emitter-base junction depth was nominally 0.5 |im and the

base-collector junction depth was nominally 1.7 pm. Representative electrical data from

both bulk and epitaxial slices without gold doping are summarized in table 2.

Process changes were made to reduce the base and emitter sheet resistance, the metalto-emitter contact resistance, the back-side contact resistance, and the fixed oxide charge

density, each of which was previously higher than the respective target value (NBS Tech.

Note 806, pp. 39-41). In most cases, further iterations appear to be required in order to achieve the target values.

It was found that use of a 0.6 percent antimony-doped gold layer evaporated onto the

back side of the slice after etching in CP-6 and alloyed for 30 min at 500°C in a nitrogen

atmosphere substantially reduced the back-side contact resistance. However, the value

achieved on bulk slices remained higher than desired.

Elimination of the staining of the boron-diffused regions prior to phosphorous deposition failed to reduce the metal-to-emitter contact resistance to an acceptable value. The

fixed oxide charge density remains at a higher level than desired on most slices. This is

due to the poor quality of the deionized water (p < 7.5 Mfi'cm) used in the clean-up and

oxidation steps. Im.proved water treatment is expected to cure this problem.

(R. L. Mattis, M. G. Buehler, T. F. Leedy, and J. Krawczyk)

6.2. Metal -To-Base Contact Resistor Study

As part of a continuing study of the structures on test pattern NBS-2 (NBS Tech. Note

788, pp. 16-17), a series of measurements was made on the metal-to-base contact resistor,

structure number 16 on the test pattern. This structure can be understood with the help of

the photograph of figure 11 and the schematic cross-section of figure 12. A current, I, is

passed through contact pads 1 and 4 and the voltage, V, is measured between contact pads 2 and 3. The substrate is allowed to float electrically during the measurement, and the cur- rent is reversed to check for linearity. The current path is indicated in figure 12. The

metallization, as seen in the figure, lies on top of the oxide everywhere except in the con- tact window and in contact pads 1 and 3. Similarly, the diffused region is under oxide

everywhere except for the contact window and the contact pads 1 and 3. The measurement is

therefore a Kelvin resistance measurem.ent ; the voltage-current ratio (V/I) v/hen multiplied

by 6.45 yields the metal-to-base contact resistance in units of microohm' square centimetres

for a square contact window 1.00 mil (25.4 ym) on a side.

22
TEST PATTERNS

Table 2 — Measurements on Test Pattern NBS -2; Run No. 2.3

Test

itructure^ Quantity Measured

Measured

Bulk

Value

Epitaxial

Target

Value

14 Base Sheet Resistance, 73 87 100±20

15 Emitter Sheet Resistance, n/n

1.6 0.2 10±5

16 Metal -to-Base Contact

Resistance, (yfi-cm^)

10.9 11 .4 <50

17 Metal -to-Emitter Contact

Resistance, (yfi-cm^)

38.4 43.8 <5

' 18 Back-side Contact Resistance, 9. 9.0 0.25 <1

1 12 Fixed Oxide Charge Density, cm"2

5.5 X IQii 2.5 X lOii (2.5±0.5) X lOii

12 Collector Oxide Thickness, nm

520 500 500±50

12 MOS C-V Collector Doping

Density, cm"^

1.7 X 1015 5.5 X lOi'* —

6 Junction C-V Collector

Doping Density, cm"^

1.7 X 1015 7.5 X 101'+ —

6 Junction Bulk Leakage

? 5 V, nA/cm^

29 17 <5

Base-Collector Junction

Depth (um)

1 .71 1 .92

See table 1 and figure 6, NBS Tech. Ncte 788, pp. 16-17 for identification of test

structures

I

I

23
TEST PATTERNS

Figure 11. Photomicrograph of the metal-to-base contact resistor, test structure No. 16 of test pattern NBS-2. (The contact

window (A) is nominally 1 mil (25 pm) on a side. The centerto-center spacing between adjacent bonding pads (1, 2, 3, 4) is

11 mils (0.28 mm) .)

Figure 12. Schematic view of a section through the contact vjindow of the

metal-to-base contact resistor test structure pictured in figure 11.

(The current path is through pad 4, the metallization stripe (D) , the contact window (A), the p''' diffused layer (C) , and contact pad 1. To measure

the potential difference, V, contact is made to the metal side of the contact window through the narrow metallization stripe leading to pad 2 and

to the dif fused-layer side by the narrow diffused region leading to pad 3. The metallization is isolated from the diffused layer and the n-type silicon substrate (E) everywhere except at pads 1 and 3 and the contact window

(A) by an oxide layer (B).)

24
I TEST PATTERNS

Several experiments were carried out on this test structure. In one experiment, the

I letal- to-base contact resistance was mapped over a specimen surface in a manner similar to he map of base sheet resistivity reported previously (NBS Tech. Note 806, pp. 41-43).

alues of metal-to-base contact resistance were 22.4 ± 2.5 yf^*cm^ for a base sheet resisance of 182 ± 6 f2/ . This value for contact resistance and the values listed in table 2

ire roughly 10 to 20 times larger than ideal values quoted in the literature [20,21] for

.luminum on boron-doped silicon. This difference can be attributed, at least in part, to

;he geometry of the contact structure. Because the current path on either side of the conact is parallel with the plane of the contact interface, only a fraction of the contact

,.rea carries a significant current. Hence, the area used to normalize the volt-current ratio

1.0 contact resistance is actually substantially less than the window area which was used to

,'btain the values reported. Because of overetching, the contact windows may be somewhat

Larger than the nominal size. This also affects the normalization because the actual current carrying area is proportional to the length of the side of the contact area.

I In a second experiment it was established that the n-type substrate of the test struc-

|;ure must be left floating with no electrical connections in order to confine the return

:urrent to the diffused layer.

I A third experiment verified the linearity of AV as a function of I over the range from

1.1 to 20 mA. This suggests that although it is nonuniform, the current distribution across

^;he contact window area does not change over a considerable range. Consequently, the test

ijitructure appears to be suitable as a process monitor which can identify deviations from the

jiominal contact resistance even though it may not yield absolute values for normalized contact resistance. (F. R. Kelly, R. L. Mattis, and M. G. Buehler)

The range of values quoted is for two sample standard deviations on Slice No. 3, Run

No. 2,2. The base is a diffused boron layer, nominally 1.7 um deep.

25
7. PHOTOLITHOGRAPHY

7.1. Introducti on

Failures in the photolithographic processing of semiconductor devices can cause both

low production yields and poor device reliability. Most of these failures can be related

either to faulty masks or failures of the photoresist to perform as desired. To establish

the extent and nature of problems associated with the photolithographic processes, a literature search was initiated, and discussions were held with numerous individuals involved in >, the use of photolithography in various aspects of the microelectronics industry.

7.2. Mask Inspection

The need for mask inspection methods to detect faulty masks prior to their use in production was determined to be the most critical need. This criticality results from the

relatively long time, several days to a few weeks, that is required for the replacement of ! a faulty mask. Also, because a mask or set of masks is used to produce many successive

devices in production, a faulty mask, undetected for only a short time, can produce a rela- I

a tively large number of defective devices.

For these reasons, the development of methods to inspect and detect faulty masks, prior,

to their use in production represents a potential cost per part reduction and an increase in)

yield. Such inspection methods need to include accurate and rapid dimensional measurements . to insure the proper alignment and registration of masks used in the successive steps of

device manufacture. In addition, these methods need to include a rapid, reliable means of

detecting flaws such as pinholes, thereby assuring the use of only high quality masks.

Initial efforts are being directed toward examination of optical and micrometrology

problems associated with mask making and mask inspection in the industry with the cooperation of the NBS Optical Physics Division.

7.3. Photoresist Materials

In these discussions it was also determined that measurements of photoresist properties

are needed that can be made prior to the use of the resist and interpreted in terms of subsequent resist behavior. The performance and behavior of photoresists are ultimately con- trolled by the chemistry of the polymers. The most important performance characteristics

and their relation to polymer properties are [22-24]:

Adhesion — If the polymer is composed of molecular fractions which

are relatively short-chained, solvents, etches, and moisture can more easily

permeate the polymer and attack the polymer-wafer surface bonding.

Resolution — Failure of the polymer to form sufficient cross linking

can lead to poorly defined edges, low adhesion, and poor resolution through

swelling caused by solvent permeation. Poor resolution can also be caused

by the presence of large particles of gel or polymeric material. All of

26
PHOTOLITHOGRAPHY

these effects can lower the resistance of the photoresist to acid and

moisture attack.

Pinhole propensity — This can be increased by the presence of gel and

particulate polymeric material in the resist.

Photosensitivity — Polymer molecules of relatively short chain lengths

or failure to have enough photoactive and cross linking sites will cause insufficient cross linking upon exposure and fail to adhere properly. Too

many of these sites will cause excessive cross linking and lead to difficulty in completly removing the photoresist.

Wet and dry coating thicknesses — These properties are directly influenced by the viscosity and solids content, both of which are interrelated

through the poljnner characteristics.

Illumination characteristics also influence the performance of photoresist films. The

nteraction of light with the layers and interfaces of composite photoresist-coated wafers

jan result in light scattering and a subsequent loss in resolution. Light scattered into

rotected regions can also result in exposure of the photoresist' in undesired regions. Nonuniform illumination across the mask-photoresist-wafer composite during exposure can lead to osses in resolution, and over- and under-exposed areas on the same wafer resulting in poor

reduction yields.

I

I Initially, the feasibility of using light scattering measurements to monitor the cleanIjiness, and gel and polymeric particle content of photoresists will be investigated. In

jddition, an improved mask is being obtained to facilitate completion of the development and

ijvaluation of the test procedure for measuring velocity and acceleration of photoresist

IIIpinners (NBS Tech. Note 592, pp. 46-47). (D. B. Novotny)

27
8. METALLIZATION

The study of tests and test patterns used to determine the adequacy of metal coverage

over oxide steps was initiated by studying the literature and discussing the problems associated with quality-of-metallization tests with representatives of the microelectronics

industry. One example of the magnitude of the problems associated with improper m.etallization and metal step coverage is given by Schnable and Keen [25] who reported that 25 percent

of the failures observed in a group of bipolar integrated circuits that had undergone operating life tests at rated voltage at 125°C were attributable to open metal interconnections

over oxide steps; this was the largest single cause of failure. These tests were reported

in 1970; since that time many improvements have been made in metallization processes. For

example, tapered oxide steps are now generally used rather than straight steps; properly

done, this technique can eliminate thinning of metal over an oxide step [26]. At this time

many manufacturers simply inspect metallization of their products on a periodic basis unless otherwise required by a parts buyer.

The different tests described in the literature for evaluating quality of metallization can be divided into three categories:

1. Examination of the metallization on a fabricated device using a scanning

electron microscope (SEM)

.

2. Testing the metallization with a current pulse.

3. Measuring the noise associated with current passing through a metal test

stripe.

The problem of metal step coverage has been studied and controlled most often through

the use of the SEM [27]. The use of SEM inspection to discriminate between "good" and "bad"

metallization has been widely used to design and optimize metallization processes. This

technique is well developed and documented. Various standards for SEM inspection have been

written; perhaps the most widely referenced is that prepared by Anstead and Adolphsen [28],

Other similar documents are those by Klippenstein and Devaney [29], and Beall [30]. Althougl

the SEM is a useful tool it has several disadvantages which limit its utility in a productior

environment

1. The instrument itself is expensive.

2. It requires a highly trained operator.

3. The inspection procedure is slow.

4. The interpretation is subjective.

5. The primary electron beam may damage the active semiconductor regions of

the device being inspected.

Despite these drawbacks, it is doubtful that SEM inspection will be supplanted entirely even

if other currently envisioned metallization tests are developed. Of the various metallization tests which have been proposed, only SEM inspection gives sufficient information to determine anything other than that the metallization failed.

28
METALLIZATION

The current pulse test was developed to circumvent the shortcomings of SEM inspection

{escribed above. In the pulse test, it is assumed that if metal is thinner, as at an oxide

tep, its local resistance is high. Hence, if the stripe is pulsed sufficiently rapidly

i.here is local adiabatic heating at the thinned region which will result in metal burn out

,.f the pulse is long enough and large enough. This is clearly a go/no-go test. The metal

.an fail this test for a variety of reasons, thinned oxide steps, scratches in the metal,

•tc. ; it is not possible to ascertain why the metal failed from the results of a pulse test.

The current pulse test relies on Joule heating to melt the metallization locally. The

.eat must be generated adiabatically since the temperature distribution of a metal stripe in

i teady state is determined principally by parameters of the geometry, oxide, and metal rather

;han local defects in the metallization.

The utility of the current pulse test is the center of some dispute at this time. The

central unresolved question is how short a current pulse is required to heat a metal defect

jidiabatically . Gurev has reported experiments in which the pulse test was able to discrimijiate between 30 and 45 percent metal step coverage [31]; however, in a subsequent series of

jixperiments he was not able to correlate the results of his tests with the results of SEM

nspection [32]. Crosthwait, Ghate, and Smith [33] have reported experiments in which the

results of the current pulse test did not correlate with the results of SEM inspection. In

ill these experiments pulse widths of 50 ns or longer were used.

In comparing the results of these experiments with an adiabatic theory, it was found

that the predictions of the theory were not consistent with the experimental results. On

:he other hand, a simple steady-state model, developed as part of this study, provides a consistent explanation of the results. This finding suggests that the pulse length used

iith the current pulse test must be shortened if the adiabatic approximation is to be valid.

iJo reports of experiments have been found in which pulses shorter than 50 ns were used.

At least four variations of the pulse test have been considered:

1. Nondestructive single pulse — The pulse width and amplitude are adjusted

so that acceptable metallization does not burn out; burn out of a test

stripe constitutes failure.

2. Resistance change — The pulse width and amplitude are adjusted so that

the resistance of a test stripe of acceptable metallization is not

affected significantly by the pulse; the resistance is measured before

and after the pulse, and a change greater than some specified amount

constitutes failure.

3. Destructive single pulse — The pulse width and amplitude are adjusted

to burn out even the best metallization; the quality of metallization

is determined by the time required for burn out, longer times indicating

better quality.

29
METALLIZATION

4. Destructive repetitive pulsing — Pulses of constant width are repeated

with increasing amplitude until burn out occurs; the quality of metallization is determined by the pulse amplitude required for burn out, higher

amplitude indicating better quality.

A difficulty in interpreting the results of the different types of current-pulse experiments

is that there are no clear cut experimentally verified relationships between them.

In the current-noise test, current is passed through a metal stripe and the resulting

noise is monitored. Experiments with molybdenum and aluminum [26,34] have shown .that when

the current density is sufficiently large, a metal stripe with defective metallization is

much noisier than a stripe with good metallization.

The physical mechanisms which generate the noise are not well understood. To some extent thermal heating of the material may be responsible; however, the marked current dependence of the noise index suggests that other processes, in particular electromigration, may

contribute to the noise. It would be desirable if the noise test could measure the propensity of a particular metallization to migrate since metal migration is a common failure

mechanism. (D. C. Lewis)

30
9. WAFER INSPECTION AND TEST

An optical flying-spot scanner is being assembled in preparation for examination of

j.tegrated circuits before and after exposure to the beam of a scanning electron microscope

EM). Use of the scanner is expected to assist in evaluation of the susceptibility of ingrated circuits to degradation during SEM inspection and in determination of appropriate

erating conditions for use in such inspections.

The scanner is designed to use electromechanically driven mirrors to deflect the beam

cm a low-powered helium-neon laser in a raster pattern focussed on the integrated circuit

be examined. The electrical signal from the integrated circuit which results from the

.ectron-hole pairs generated by the laser light is displayed on an oscilloscope with a

'ster sweep in synchronism with the laser raster. A scanner of this type has been described

jeviously in the literature [35] and has been used to analyze the operation of functioning

.miconductor devices [35] and to observe process-induced device degradation [36]. However,

.e present system has considerably improved characteristics including a spot size on the

iiecimen of 1 um diameter, a choice of incident wavelength (0.633 or 1.15 ym) , a range of

.ster frame times (10~^ to 10^ s) , and the capability of providing junction currents over

he range 10"^^ to 10"'+ A. (D. E. Sawyer)

In a continuing search of the technical literature on SEM examination of semiconductor

ivices, several papers which discuss SEM- induced damage to, or changes in the electrical

liaracteristics of, devices were collected. (M. J, Wirtz and D. E. Sawyer)

31
10. DIE ATTACHMENT

10.1. Heat Flow Analysis

The analysis of heat flow to determine the limitations of themial response techniques

for detecting poor die adhesion in mesa diodes bonded to TO-5 headers was completed using

the TRUMP thermal analysis computer program [37]. The data given in figure 13 compare the

results of the void detection study for mesa diode lots I, J, and L (NBS Tech. Note 717,

p. 20) with those of calculations using TRUMP. The structure shown in the insert was used

to approximate the true TO-5 header-chip structure. Cylindrical symmetry and circular,

centrally located voids were assumed. The shaded area in the model indicates that part of

the structure that has a temperature that is above the temperature of the reference point,

the outside of the metal shell, for the 10-ms heating power pulse that was used in determining the transient thermal response. The solid curves give the calculated results for the

percent increase in steady-state and transient thermal response of devices with a void above

that of devices without voids as a function of void area in percent. The data points are

the results of measurements performed on the mesa diode chips bonded to the TO-5 headers

with various size voids. These points indicate the percent increase in transient thermal

response of the devices with a void above the average response of their respective control

devices as a function of effective void area in percent. Effective void area was determined

by comparing the experimentally determined percent increase in steady-state thermal response

of devices with a void above the average response of their respective control devices with

the calculated curve. Most of the deviation from the calculated transient response curve

is due to the fact that the voids were not all centrally located and that the area around

the dimples were not always completely bonded. For example, the triangles represent devices

with uncontrolled voids; these devices were analyzed with radiographic techniques and found

to have large unbonded regions in addition to the dimpled area.

The approach taken in this analysis differed somewhat from that taken previously (NBS

Tech. Note 727, pp. 25-27) where it was assumed that the approximate percent void area was based on the dimple area divided by the available chip bonding area as long as the voided

devices were in control. This assumption was made due to the difficulty in accurately predicting the effects of variations in void location, in bonded area around the void, and in

thickness of die attachment material itself on the device thermal response. The corre- spondence of the experimental points with the calculated transient response curve in the

figure suggests that the simplified model satisfactorily represents the actual devices under

test, so that the system can be calibrated by determining the effective void area from the

calculated steady-state thermal response as was done in the present analysis.

10.2 Void Detection in Transistor Die Attachment

Study of the application of thermal response measurements to the detection of voids in

transistor die attachment was completed. A second group of three sets of power transistor

chips, 60-mils (1.52-mm) square, was bonded onto TO-66 headers with various size dimples

ultrasonically machined into the bonding surface to produce, if the bonding were perfect.

32
DIE ATTACHMENT

1 \ \1 -JUNCTION -MESA DIODE CHIP ^mw METAr~

Figure 13. Percent increase in junction-tocase temperature difference of diodes with

voids over that of their respective controls

measured under steady state and transient

conditions as a function of percent effective

void area in the diode die attachment. (See

text for identification of symbols.)

0 10 20 30 40 50 60 70 80

PERCENT EFFECTIVE VOID AREA

)id sizes of 15, 25 or 40 percent of the chip bonding surface. Ten control devices with

j) intentional voids were bonded with each of three sets of devices with various diameter

[mples.

i

1 To determine the pulse width for maximum sensitivity to voids, measurements of steadyiate thermal response and transient thermal response for heating power pulse widths ranging

rom 1 to 100 ms were made on devices with and without voids. The results indicated that

|l»r these transistors a 5-ms heating power pulse gave the maximum sensitivity. Measurements

[ the change in emitter-base voltage (NBS Tech. Note 743, pp. 23-24) indicated that while

ie devices without intentional voids were in control, the devices with various sizes of

imples were not. The measured voltage change is proportional to the thermal response if

le temperature coefficient of the emitter-base voltage is assumed to be constant.

The percent relative sample standard deviation for the transient thermal response meairement of the controls for the three sets of voided devices ranged from 1.2 to 1.6 percent.

>r the three sets of devices with voids, the percent relative sample standard deviation

mged from 14.8 to 16.9 percent. The percent increase in sensitivity to voids of transient

iiermal response over the steady-state thermal response measurements ranged from 57 to

j>9 percent; the grand average was approximately 100 percent. Even in this case where the

Le attachment is so poor that the increase in sensitivity is less striking ,. the advantage

I the transient thermal response technique over methods requiring heat sinking is neverthefss evident.

.3. Summary

This concludes the laboratory phase of the semiconductor device die attachment evaluaton study. Practical advantages of using the transient thermal response techniques for

I 33
DIE ATTACHMENT

screening semiconductor devices for poor die attachment have been demonstrated over the course of this study. It was found that the technique is [38]:

1. Sensitive — It can be used to detect voids as small as 15 percent of

the chip bonding area.

2. Convenient — It can be performed on finished devices and requires

minimal, if any, heat sinking.

3. Fast — It can be automated.

4. Adaptable — It can be used for testing a wide variety of device types.

(F. F. Oettinger and R. L. Gladhill)

34
' 11. INTERCONNECTION BONDING

1. Metallurgical Systems for Ultrasonic Bonding

I Characterization of various metallurgical bonding systems of interest for microelec-

)nic devices continued. Last quarter a study was made of one manufacturer's gold wire

:rasonically bonded to thin film aluminiom on silicon oxide substrates. This wire was md to yield a high bond strength over a very wide range of ultrasonic power (NBS Tech.

:e 806, pp. 36-38). The result was verified during the present quarter with two more lots

gold wire of different manufacture, breaking strengths, and alloy composition.

Tentative results on the ultrasonic bonding characteristics were obtained for gold wire

' gold thick-film metallization. A satisfactorily wide range of bonding force and ultralic power yielded strong bonds with these materials providing the bonding time was infeased to about 500 ms or more.

The ultrasonic bonding characteristics of 1-mil (25-iJm) diameter aluminum (1% silicon)

!:e to both aluminum thin-film metallization on silicon oxide over silicon and gold thickj.m metallization on an alumina ceramic substrate were studied. l^Jhen bonding silicon dice

':o hybrid circuits, bonding machine constraints usually require that both the bond to the

j:allization on the die and the bond to the thick-film conductor be made with the same

iding force. An extensive bonding machine parameter optimization procedure, involving a

ijige of bonding force, bonding time, and tool tip vibration amplitude, was carried out for

1ph systems. From figure 14 it is seen that a 25 gf (0.25 N) bonding force, a 45-ms bonding

ie, and, for example, a 50-iJin. (1.3 um) peak-to-peak tool tip vibration amplitude produced

'ipisfactory bonds on both metallizations. Somewhat stronger bonds were obtained on the

[ck-film gold when a bonding force of 30 gf (0.29 N) was used, but with this force the

ids to the thin-film aluminum were significantly weaker. The greater variability in

rength of the bonds made to the thick-film gold occurred because of somewhat greater diffiity in controlling the loop height, and, perhaps more importantly, because of the irregular

i.ure of the gold surface as illustrated in the scanning electron micrograph in figure 15.

Ij Studies were also begun using platinum wire on thick-film gold and thin-film aluminum

I '.allization. Initial results indicate that platinum wire can be bonded to these metallir.ions with' bonding parameters similar to those of aluminum wire. If these results are conjmed by more complete studies and if no secondary complications occur, it may be that plat-

|im wire should be given further consideration for use in hybrids, since it does not form

liermetallic compounds with gold, which can be a major problem with aluminum wire [39].

Ij (G. G, Harman and C. A. Main)

jj2. Burn-out Characteristics of Fine Bonding Wire

The current burn-out properties of round and ribbon aluminum and gold bonding wire were

[died on 10-mm lengths of wire in air at 23°C. The aluminum wire specimens were obtained

im two sources. They contained 1% silicon, 1% magnesium, or 2V2% magnesium, or consisted

rja proprietary alloy. No significant differences in burn out were observed among these

'oys. The gold wire specimens were of 99.99% purity and were also obtained from two

:! 35
INTERCONNECTION BONDING

TYPICAL BOND DEFORMATION (wire diameters)

1.1 1.2 1.5 1.9 2.0 2.6 2.9 ^ 10

I

IlU

Q.

O

m

n

I

J L n10

J L 20 30 40 50 60 70 80 90 100

TIP VIBRATION AMPLITUDE { fJ.\n.)

a) Aluminum wire bonded to thin-film aluminum metallization on silicon dioxide over silicon.

TYPICAL BOND DEFORMATION (wire diameters)

1.0 1.2 1.5 2.0 2.3 2.6 3.0 2.9

20 30 40 50 60 70 80 90 100

TIP VIBRATION AMPLITUDE (/xin.)

b) Aluminum wire bonded to a 90-percent gold, 10-percent glass

binder thick-film metallization on an alumina substrate.

Figure 14. Bond pull strength of ultrasonically bonded, 1-mil (25-Mm) diamet

aluminum (1% silicon) wire, single-level, double bonds as a function of the

peak-to-peak vibration amplitude of the bonding tool tip. (Increasing vibration amplitude corresponds to increasing power; the small numbers below the

data points represent settings of the power control on the bonder. The bonding force was 25 gf (0.25 N) and the bonding time was 45 ms. Foot length of

the bonding tool used was 4.5 mils (114 pm) . The error bars represent one sample standard deviation above and below the mean of 10 to 15 values.)

36
INTERCONNECTION BONDING

Figure 15. Scanning electron micrograph

of the surface of the thick-film gold

metallization used in these ultrasonic

bonding experiments. (Magnification:

^400 X.)

jirces. The voltage across the 10-mm length of wire was increased gradually while monitor-

; the current until the wire burned out and ceased conducting.,

I The burn-out characteristics of the gold wire were as expected. Results are listed in

pie 3 which shows the diameter or cross sectional dimensions, the cross sectional area,

^ the current at which the wire burned out.

The aluminiun wire, however, burned out in an unusual manner. At one point in the voltrrent characteristic, the current decreased abruptly. At this point the wire, which

pwed white hot, xvas far above the melting temperature of aluminum. Although the wire

Table 3 — Burn-Out Current for 10-mm Length of Gold Wire

i Cross Sectional Dimensions

Cross Sectional Area, Burn-Out

in. (ym) in.

(ym2) Current, A

001^- (25.) 0.78 X 10-6 (5.0 X 102) 0.56

001^ (25.) 0.78 (5.0 ) .0.56

'0.56

0015 X 0.0005 (38. X 13) 0.75 (4.8 ) 0.52

0015 X 0.0005 (38. X 13) 0.75 (4.8 ) 0.50

.003 X 0.0005 (76. X 13) 1.5 (9.7 ) 0.89

.003 X 0.001 (76. X 25) 3.0 (19. ) 1.34

002^ (51.) 3.1 (20. ) 1.39

L005 X 0.001 (130. X 25) 5.0 (32. ) 2.0

005^ (130.) 20. (130. ) 6.1

Diameter

37
INTERCONNECTION BONDING

Table 4 — Burn-Out Current for lO-mm Length of Aluminum Wire

Cross Sectional Dimensions,

in. ( um

)

Cross Sectional Area,

in. 2 (ym^)

Composition

0.001^ (25.) 0.78 X 10-6 (5.0

0.001^ (25.) 0.78 (5.0

0.001^ (25 ) 0. 78 (5.0

0.001^ (25.) 0.78 (5.0

0.0015 X 0 0005 (38. X 13) 0.75 (4.8

0.0015 X 0 0005 (38. X 13) 0.75 (4.8

0. 001

5

X 0 0005 (38. X 13) 0.75 (4 8

0.0021 X 0 0004 (53. X 10) 0.84 (5.3

0.003 X 0 0005 (76. X 13) 1 .5 (9 7

0.002^ (51.) 3.1 (20.

0.005 X 0 001 (30. X 20) 5.0 (32.

0.003^ (76.) 9.1 (59.

0.003^ (76.) 9.1 (59.

0.005^ (130.) 20. (130.

0.01 X 0 002 (250. X 51) 20. (130.

0.01^ (250.) 78. (500.

0.01^ (250.) 78. (500.

0.01^ (250.) 78. (500.

1% Si Mo Si

1% Si

2.5% Mg

1% Si

VL Si

V/o Mg

2.5% Mg

1% Mg

1% Si

1% Si

b

1% Si

b

1% Si

b

1% Si

1% Mg

0.49

0.39

.0.375

<0.408

(0.35

'0.355

0.392

(0.415

'0.465

0.375

0.37

0.565

(1.15

n.2i

1.5

2.2

2.2

4.75

4.5

15.5

14.7

14.6

Diameter

99% aluminum, impurities unspecified

melted, it apparently developed a thick aluminum oxide sheath that contained and protected

the liquid metal. Up to 10 min was required for burn out under these conditions. However,

after the melting point had been reached but before burn out, the wire would often open up

when the current was switched off or reduced so that the wire temperature dropped below the

melting point of aluminum. Consequently the current where the abrupt change occurred was chosen as the practical burn-out current. Data on the various aluminum wires tested are listed in table 4. Figure 16 is a scanning electron micrograph of a section of a 5-mil

(1.3 mm) diameter aluminum wire after burn out. The cracked oxide sheath is evident.

(H. K. Kessler)

I

38
INTERCONNECTION BONDING

Figure 16. Scanning electron micrograph of a 5-mil (0.13-inm) diameter

aluminum wire after burn out on heating to about 1100°C for 3 min showing

the oxide surface coating. (Magnification: '\^380 X.)

.3. Dissemination Activities

In addition to the technical activities reported above, dissem.ination of the methods

id technology developed for controlling the ultrasonic bonding process and for testing wire

j)nds continued at a high level throughout this period. Visits were made to five industrial

rganizations , and 23 people visited or called NBS to obtain information in this area. A

immary report of the work carried out during the past five years was readied for publication

1^0]. (G. G. Harman and H. K. Kessler)

f

39
12. HERMETICITY

An assessment of the role of hermeticity and measurements needs was initiated based

upon published papers, other agency reports, standards, and direct communications with industrial representatives. The effort to ensure hermeticity represents a significant fraction

of device cost, including cost of appropriate package structures, of inspection of package

components before assembly, and of fine and gross leak tests after assembly. Further device

degradation due to contamination, principally water vapor, from outside the package is a widely recognized failure mode. Yet lack of measurement correlation for the same test method

at different stations and for different test methods at the same station, discrepancies in

the theory upon which standards for test procedures are based, subjective nature of some preferred test procedures, and scarcity of definitive data linking leak size to device failure were noted.

The theoretical models relating leak size to measured leak rate are in need of revision

in several areas. Firstly, while current practice is to compute leak size by laminar (viscous) flow theory for the radioisotope method, and by free molecular flow theory for the

helium leak detector method, it should be apparent that such a procedure can produce large

differences in computed leak size for any given leak rate. For example, a difference of an order of magnitude or more for a leak in the 10"^ atm-cm^/s range may result for usual con- ditions of initial pressurization. Transition flow analysis is more appropriate for leak

sizes encountered in practice and should provide the basis for both procedures. Secondly,

the rate of escape of gas from the package after pressurization needs better definition,

particularly for extending the range of these methods to larger leak sizes. Thirdly, at the

five and more atmospheres of pressurization often employed, the flow mechanism of helium or krypton tracer gas into the package may differ significantly. Finally, a better understanding of the passage of water vapor through small channels and the correlation to leak sizes

determined from leak rates measured with a more ideal gas is needed. Examination of these'

factors is in progress.

Assistance is being given ASTM Committee F-1 on Electronics in the organization of an interlaboratory evaluation of the helium mass spectrometer method [41] for testing fine

capillary leaks in large volume ('^1 cm^) containers. The experiment is intended particularly to check the Howl and Mann theory [42] for relating measured to actual leak rate.

(S. Ruthberg)

40
13. THERNAL PROPERTIES OF DEVICES

1. Thermal Resistance Methods

Long-term, single-operator measurements, to check the repeatability of the equipment

measuring thermal resistance of transistors by the V^g emitter-only switching technique,

e completed. These measurements confirmed the preliminary result reported previously

S Tech. Note 806, pp. 51-53) that the repeatability is nearly independent of the magnie of the measured thermal resistance, but that it is limited by a minimum resolvable

ction-to-case temperature difference of a few hundreths degree Celsius.

Twenty-two sets of measurements were made on three single diffused transistors in TO-3

s over a period of three weeks. During the heating, the collector current and voltage

e 1 A and 20 V respectively; during calibration, the measuring current was 6 mA and the

lector voltage was 2 V. The devices were tested with a- case temperature of 60°C and a mea- ing current of 6 mA. The average value and the pooled sample standard deviation of the

sured junction-to-case thermal resistance were 0.79 and 0.01°C/W, respectively. (S. Rubin)

Further studies were performed on 12 transistors to compare measurements of thermal

istance using the V emitter-only switching technique with that of the thermal resistance

ived from measurements of peak junction temperature made with the infrared microradiometer

viously such comparisons have been reported for high-current, low-voltage conditions (NBS

h. Note 773, pp. 28-29) and high-voltage, low-current conditions (NBS Tech. Note 788,

48-50), both with case temperature of 25°C. In addition, current crowding in three of

devices under the high-voltage, low-current conditions was verified (NBS Tech. Note 806,

47-49). In the present study, comparisons were made under high-current, low-voltage

ditions at elevated case temperatures. The thermal resistance of each of the devices was

jjsured with a collector-emitter voltage of 20 V and a case temperature sufficient to raise

1 junction temperature to approximately 80 percent of its rated value. The collector cur-

't was held at 1 A, except in the case of two low-gain devices for which the collector

rent was 0.5 A. The temperature coefficient of the emitter-base junction voltage, V ,

|d as the temperature sensitive parameter, was determined first between 25 and 100°C and

jond between the multiple of 25''C nearest to the case temperature used during the measurets and 175°C, except in the case of two low-gain devices for which the upper limit in the

ond determination was 150*'C. It was found that the slope of V„-, as a function of T for

EB C onstant collector-emitter voltage can vary slightly for temperatures above 125°C.

The results of the thermal resistance measurements are summarized in table 5, which

Its the junction-to-case thermal resistance derived from measurements of V„„ using the

calibration curves with the thermal resistance derived from the peak junction temperaJe measured with the infrared microradiometer. For "the electrical measurements, V_,„ was sured 50 ys after the heating power was terminated. The difference between the eleccally measured thermal resistance derived from the low- and high-temperature calibrations

that determined from the infrared measurements, expressed as a percentage of the latter,

I listed in column 3, labeled A^, and column 4, labeled A^, respectively, of table 5. The

41
THERMAL PROPERTIES OF DEVICES

maximum difference between the data in columns 3 and 4 is less than 6 percentage points. ThI

approximation of using the calibration curve for a temperature range between 25 and 100°C

also gives a higher, and thus more conservative, value of thermal resistance. The advantage;

of this calibration procedure is that the temperature controlled heat sink need not be designed for temperatures higher than 100°C. (S. Rubin, D. L. Blackburn, and F. F. Oettinger)

13.2. Analysis

A preliminary study using the TRUMP [37] computer program, undertaken to determine the

optimum extrapolation procedure for semiconductor device thermal resistance measurements,

indicated that a log-linear extrapolation procedure is appropriate for use on devices that can be approximated by a circular silicon die on an infinite heat sink for the first few

hundred microseconds of cooling (NBS Tech. Note 806, pp. 49-51). Further studies were perfomed taking into account the effects of the change in silicon thermal conductivity with

temperature. In addition, a copper slab 0.15 cm thick and the same diameter as the silicon

die was added between the silicon and the infinite heat sink which was assumed to be at 0°C.

The TRUMP program was again used to calculate the peak surface temperature during the first

200 ys of cooling for heat source areas 100, 42 and 22 percent of the silicon chip surface

area. In addition, the average surface temperature of the heat source area, T^.^^^, was computed from the TRUMP results as in the previous calculations

.

The four extrapolation procedures investigated were log-log, linear-linear, linear-log

and log-linear. Again, the last of these, in which the logarithm of the surface temperature

is plotted as a linear function of time, yielded the most nearly linear plot; the cooling

curves were found to be approximately straight and parallel throughout the interval 20 to 100 MS. The extrapolated values of average temperature, which is usually the quantity determined in electrical measurements of thermal resistance, were 20 and 24 percent lower than i the calculated peak temperature at t = 0 for the cases where the heat source area was 42 and

22 percent of the chip surface area, respectively. These values are about the same as found

previously for the simpler model. For the case where the entire chip surface comprised the

heat source area, the extrapolated value was only 5 percent lov/er than the computed peak

temperature at t =0. This difference is about half that found for the simpler model.

13.3. Standardization Activities

To compare the electrically measured thermal resistance with thermal resistance derived

from the peak junction temperature, the peak junction temperature of the power transistors

used in a preliminary round-robin experiment on thermal resistance measurements was measured

with an infrared microradiometer . The results of the round-robin experiment, which was con- ducted in cooperation with JEDEC Committee JC-25 on Power Transistors, showed that the

highest electrically measured thermal resistance is obtained with the V^^ emitter-only

switching technique (NBS Tech. Note 806, pp. 45-47).

(F. F. Oettinger and R. L, Gladhill)

42
THERMAL PROPERTIES OF DEVICES

Table 5 — Comparison of Infrared Table 6 — Comparison of Infrared and

and Electrical Thermal Electrical Thermal Resistance Measurements

Resistance Measurements for the Round-Robin Test Devices

'ice

(lO.

D 1 / T D ^ °C/W

01 Device

No. Case

Type

ReJcdR).

°C/W

A 0/ A , lo

1 6.5 -19 7 -21 .

101 TU

0 70

3 2.8 -12 1 -15.7 102 TO-3 0 70 -21.4

4 3.9 -34 6 -37.9 103 TU-3 0 78

5 3.9 -15 1 -20.

104 ru

0 89 on o

6

1 5.8 -16 7 -17.8 105 TO-3 1 uo -ic . 4

8 8. 3 -22 8 -24.

106 1 U-i 1 61 -CO. U

9 3.6 -8 6 -13.9 107 TO-3 1 65 -35.8

10 4.2 -34 5 -36.7 108 TO-3 1 88 -25.0

13 4.0 -20.3 -26.0 109 TO-66 2 03 -14.3

14 3.7 -12 7 -18.1 110 TO-66 2 65 -11.7

15 8.2 -6 3 -8.7 111 TO-66 2 72 -11 .8

16 7.9 -5 9 -7.8

j The results of the present experiments are presented in the last column of table 6 as

p difference between the thermal resistance calculated from the junction temperature depmined electrically 50 ys after the termination of power by the V _ emitter-only switching

thod and that determined from the infrared measurements, expressed as a percentage of the

t:ter. For reference, thermal resistance, (IR) , derived from the infrared measurements

(| 0 J

ij also listed in the table. During the power portion of the electrical measurements, the

Llector-emitter voltage was 20 V and the collector current was 2.0 A, for the devices in

•3 cases, or 1.0 A, for the devices in TO-66 cases. For a number of the devices tested,

fE hottest region on the chip was found to be hear the emitter lead. The infrared measuretit is therefore somewhat uncertain because of possible interference of the emitter lead

ch the optical path of the infrared microscope. For these measurements this was probably

't a serious problem because under the operating conditions used in the study the temperate gradients across the active regions of the chip were small so that the hottest region

the chip was not well defined. (D. L. Blackburn, S. Rubin, and F. F. Oettinger)

j Final revision of the proposed thermal resistance test method for signal diodes was

npleted in preparation for its circulation as JEDEC Semiconductor Committee Letter Ballot

1-20-73-73. Comments were received on a users guide for making thermal characteristics

jsts on microelectronics devices, recently letter balloted in JEDEC Committee JC-11 on

jChanical Standardization, and modifications are being made to incorporate these comments.

(F. F. Oettinger)

43
1^1. MICROWAVE DIODES

14.1. Repeatability Studies

The mixer conversion loss repeatability studies were continued using a larger number ofj

Schottky-barrier diodes from three manufacturers. These measurements are intended to delineate the measurement system repeatability and to provide a reference level for the diodes to, be irradiated for a study of the radiation hardness of Schottky-barrier diodes designed as direct replacements for MIL- type 1N23 series X-band diodes (see 14.2.).

Fifty diodes have been measured to date, ten diodes from each of three manufacturers

with a specified overall average noise figure limit of 6.0 dB, and ten diodes from each of

two manufacturers with a limit of 6.5 dB. All of the diodes were measured twice for conversion loss, self-bias, local oscillator return loss (SWR) , output conductance, and forward

current (at a given d-c voltage). The 6.5 dB diodes had previously been measured twice for

conversion loss and self-bias only. In addition, photographs were made of the currentvoltage characteristics of all diodes, and the junction capacitance was measured at three

values of reverse bias for all diodes except those which exhibited a high reverse conductance which reduced the capacitance sensitivity at some bias levels below a usable value at

the small signal level required. Some diodes were unsuitable for use in the repeatability

studies because they exhibited a high conversion loss (>6 dB) at the initial or succeeding

measurements.

The results of these measurements are summarized in table 7 vjhich lists the mean value

and sample standard deviation of the change from the previous measurement. (J. M. Kenney)

14.2. Radiation Hardness Study

At frequencies above several gigahertz, most receivers are now being designed to use Schottky-barrier diodes for mixing. A preliminary study to assess the permanent radiation

damage to typical, commercially available, Schottky-barrier diodes on exposure to both fast

neutrons (E > 10 keV) and ^°Co gamma rays was undertaken in cooperation with the Harry

Diamond Laboratories.

The diodes to be studied are of the type designed as direct replacements for MIL type

1N23 series X-band diodes, as have been used in the repeatability studies (see 14.1.). In

use, these diodes are mounted in fixed-tuned standard holders [43] which were designed to hold point-contact diodes of the 1N23 type. To facilitate mounting and to select diode

polarity, a cap can be attached at either end of the diode.

Diodes for this study were selected from the lots measured in the repeatability study.

Only diodes for which the measured conversion loss changed by less than 0.1 dB in repetitive

measurements and for which the measured conversion loss never exceeded 6 dB were chosen. A

summary of the conversion loss data for the selected diodes is listed in table 8. Diodes were selected in groups of multiples of three from each lot so that equal numbers of diodes

The measured conversion loss is approximately 1.5 dB lower than the overall average noise

figure

.

44
MICROWAVE DIODES

Table 7 — Change in Conversion Loss on Repetitive Measurements

of 1N23-Equivalent Schottky-Barrier Diodes

Lot

Specified

Noise Figure

Limit, dB Repetition Manufacturer Mean, dB

Odlll^ 1 C O UClllUui u Deviation, dB

Number of

ncd iU 1 a U 1 c Diodes

1 D . u 1 An n 1 QV

o

L D . u 1 DD U . UUr 11 nu

00 D . U 1 L -u . UUh- oo

D . 3 1 nM n nn 7

4 6.5 2 A -0.100 0.218 4

4 6.5 3 A -0.139 0.113 2

5 6.5 1 B 0.001 0.040 9

5 6.5 2 B 0.019 0.051 9

5 6.5 3 B -0.038 0.030 9

Table 8 — Change in Conversion Loss on Repetitive Measurements

of 1N23-Equivalent Schottky-Barrier Diodes

Selected for Rad iation Hardness Study

Specified

Noise Figure Measurement Sample Standard Number of

Lot Limit, dB Repetition Manufacturer Mean, dB Deviation, dB Diodes

1 6.0 1 A -0.002 0.051 6

2 6.0 1 B 0.003 0.029 9

3 6.0 1 C 0.007 0.020 6 4 6.5 1 B -0.001 0.040 9 4 6.5 2 B 0.019 0.051 9

4 6.5 3 B -0.038 0.030 9

45
MICROWAVE DIODES

from each lot could be used for a gamma irradiation group, for a neutron bombardment group,

and for an unirradiated control group. An attempt was made to balance the three groups in

terms of diode stability, and the assignment of the diodes within the groups was made at ran- dom after the groups were formed. It was found that many of the diodes from manufacturer A

appeared to be unusually sensitive to mechanical shock, and all but one of the ten 6.5 dB

diodes from this source were found not to be acceptable, so that this lot could not be

represented

.

In preparation for the irradiation, conversion loss measurements on three of the lots were repeated after removal and reattachment of the cap. Only the "forward" polarity was

used, and care was taken to obtain the same cap orientation, in case of asymmetry. The re- peatability seemed to be about the same despite this extra factor.. The diodes can, therefore, be irradiated without the caps, reducing the size and mass of the irradiated structure

and also reducing the possibility of secondary radiation from the diode in the holder, from

which only the cap protrudes. (J. M. Kenney and N. J. Berg^)

Unfortunately, the first Schottky-barrier diode used in the repeatability studies (NBS

Tech. Note 805, pp. 54-5 5) was from this lot.

Harry Diamond Laboratories, Washington, D. C. 20438. (Contract S-402391-4.)

46
15. HIGH-FREQUENCY HEASUREFIENTS

Analysis was completed of the results of the interlaboratory comparison of transistor

jttering parameter measurements conducted for the Air Force Weapons Laboratory (NBS Tech.

^es 743, pp. 42-43; 754, p. 35; 773, pp. 34-36; 788, pp. 55-57; and 806, pp. 56-57) [44].

B test was designed to determine the extent of the agreement between transistor measurets made in different laboratories by different personnel using the procedure and equipt normally employed by the participating laboratory. To provide the necessary data each

fticipating laboratory measured the S parameters of a set of selected transistors of three

es. In addition, each laboratory measured a number of passive devices to provide data

' the assessment of within-laboratory variability and, to assist in identifying the source unacceptably large variability if this proved to be necessary.

; S parameters were measured in 100 MHz increments at frequencies from 200 to 2000 MHz.

each frequency the four measurements made on the passive devices by each laboratory were

Iraged to obtain a mean for the laboratory, and the within-laboratory sample standard devilon was calculated as a measure of the dispersion of the data about this mean. The means

]each of the laboratories were then averaged to obtain the overall mean, and the sample

indard deviation was calculated as a measure of the between-laboratory variability (NBS

h. Note 788, p. 56)

! The upper frequency limit for measurement of S-parameters on the transistors was 1000

[lBOO MHz depending on type. Only the between-laboratory variability of the transistor

surements was determined, because the transistors were measured only once at each bias

1 frequency. For the magnitudes of the S and h parameters, the sample standard deviation

expressed as a percentage of the overall mean to obtain the relative standard deviation

llcoef f icient of variation. The sample standard deviation was used as a measure of the

lability of the phase measurements.

] As an illustration, the variability of the 17 measurements of each of the four S paramj'rs made on each of the six 2N3960 transistors at a bias current of 2.5 mA by the five

ticipating laboratories which used automatic network analyzers is summarized in table 9. maximum, mean, and minimum sample standard deviations obtained in the 102 sets of data

each parameter f are listed. In addition, the variability of h^ and h. , calculated from y fe le

measured S parameters, is indicated. Measurements made by the laboratory which used

ual equipment fell within the same range as those made on the automatic systems.

!

! The extreme variability of the s^^^^ measurements is due in large part to the variability

reduced by the differences in calibration procedures employed by the participants when

Ing the transistor fixture (NBS Tech. Note 773, p. 35). In addition, the variability of

I magnitude of S2.j^ was excessive because the signal level applied to the transistor base

d by one of the participants exceeded the requirements for small-signal conditions.

If these sources of variability are eliminated, for example, by specifying the calibra-

[n method to be used and by specifying a maximum signal level to the transistor under test,

I variability of S-parameter measurements could be expected to be considerably reduced.

47

}
HIGH-FREQUENCY MEASUREMENTS

Table 9 — Variability of Typical S-Parameter Measurements

max mean

min

All Laboratories

Magnitude,

%

45.9

12.6

3.5

Phase,

deg

34.2

0.7

Three Laboratories

Magnitude,

%

7.5

4.5

0.6

Phase,

deg

8.2

1.8

0.1

'21

max mean

min

9.9

2.9

0.9

3.3

1.1

0.2

5.4

2.7

0.7

1.7

0.7

0.1

M2

max

mean

min

5.2

2.4

0.9

1.7

0.9

0.2

6.6

3.0

0.2

2.2

0.9

0.1

'22

max mean

min

8.9

4.4

1 .6

3.1

2.0

0.7

4.8

2.8

0.8

3.5

2.0

0.5

'fe

max

mean

min

8.6

3.4

0.8

5.0

1.6

0.4

7.0

2.2

0.2

3.0

1.1

0.2

ie

max mean

min

23.1

5.2

1.1

12.0

3.1

0.5

2.6

1.0

0.0

3.0

1 .6 0.3

The extent of this reduction is suggested by analyzing the results of the measurements aftei

excluding two laboratories because of apparent calibration anomalies and the 200 MHz data

because of the excessive signal level used by one of the remaining laboratories. The last

two columns of table 9 contain the results of this analysis.

Examination of data from the other transistor groups and at other biases shows that the

results presented in the table are typical of the entire sample used in the interlabqratory

comparison. (G. J. Rogers

]

48
16. REFERENCES

Schafft, H. A., Semiconduotor Measurement Technology: ARPA/NBS Workshop I. Measurement Problems in Integrated Circuit Processing and Assembly, NBS Spec. Publ. 400-3

(February 1974)

Amron, I., Errors in Dopant Concentration Profiles Determined by Differential Capacitance Measurements, Electroohem. Tech. 5_, 94-97 (1967).

Buehler, M. G. , Peripheral and Diffused Layer Effects on Doping Profiles, IEEE Trans.

Electron Devices ED-19 , 1171-1178 (1972)

Attalla, M. , and Tannenbaum, E., Impurity Redistribution and Junction Formation in Silicon by Thermal Oxidation, Bell System Tech. J. 39, 933-946 (1960).

Grove, A., Leistiko, Jr., 0., and Sah, C. T., Redistribution of Acceptor and Donor

Impurities during Thermal Oxidation of Silicon, J. Appl. Phys. 35, 2695-2701 (1964).

Ku, H., Redistribution of Solutes during Thermal Oxidation of Silicon, J. Appl. Phys.

35, 3391-3397 (1964).

Margalit, S., Nevgroschel, A., and Bor-Lev, A., Redistribution of Boron and Phosphorus

in Silicon After Two Oxidation Steps Used in MOST Fabrication, IEEE Trans. Electron

Devices ED-19 , 861-868 (1972).

Irvin, J. C, Resistivity of Bulk Silicon and of Diffused Layers in Silicon, Bell

System Tech. J. 41, 387-410 (1962).

Caughey, D. M. , and Thomas, R. E., Carrier Mobilities in Silicon Empirically Related

to Doping and Field, Proc. IEEE 55_, 2192-2193 (1967).

Wagner, S., Diffusion of Boron from Shallow Ion Implants in Silicon, J. Electroohem.

Soo. 119 . 1570-1576 (1972).

Buehler, M. G. , Thermally Stimulated Measurements: The Characterization of Defects in

Silicon p-n Junctions, Semiconductor SiliGon/1973, H. R. Huff and R. R. Burgess, eds .

pp. 549-560 (Electrochemical Society, Princeton, N. J., 1973).

Sah, C. T., Forbes, L. , Rosier, L. I., Tasch, Jr., A. F., and Tole, A. B., Thermal

Emission Rates of Carriers At Gold Centers in Silicon, Appl. Phys. Letters 15_, 145-148

(1969)

Natrella, M. G. , Experimental Statistics, NBS Handbook 91 (August 1, 1963), 115-5.1.3.

Thurber, W. R. , Lewis, D. C, and Bullis, W. M. , Resistivity and Carrier Lifetime in

Gold-Doped Silicon, AFCRL Report AFCRL-TR-73-0107 , January 31, 1973, pp. 14-24.

(Available from the National Technical Information Service, Springfield, Virginia

22151, Accession No. AD 760150.)

Hughes, H. L. , A Survey of Radiation-Induced Perturbations in Metal- InsulatorSemiconductor Structures, 9th Annual Proceedings , Reliability Physics 1971 , Las Vegas,

Nevada, March 31-April 2, 1971, pp. 1-7. (Available from Publications Sales Dept.,

The IEEE, 345 E. 47th Street, New York, New York 10017, Catalog No. 71-C-9-PHY.)

Hughes i H. L. , Baxter, R. D., and Phillips, B. , Dependence of MOS Device Radiation

Sensitivity on Oxide Impurities, IEEE Trans. Eucl. Sci. NS-19 , No. 3, 256-263 (1972).

Yon, E. , Ko, W. H. , and Kuper, A. B., Sodium Distribution in Thermal Oxide on Silicon

by Radiochenical and MOS Analysis, IEEE Trans. Electron Devices ED-13 , 276-280 (1966).

Hofstein, S. R. , Proton and Sodium Transport in SiO Films, IEEE Trans. Electron

Devices ED- 14 , 749-759 (1967).

49
REFERENCES

19. Schroen, W. H. , Aiken, J. G., and Brown, G. A., Reliability Improvement by Process

Control, 10th Annual Proceedings^ Reliability Physics 1972, Las Vegas, Nevada, April 5-

7, 1972, pp. 42-48. (Available from Publication Sales Dept., The IEEE, 345 E. 47th

Street. New York, New York 10017, Catalog No. 72CH0628-8-PHY .

)

20. Ting, C, and Chen, C. Y., A Study of the Contacts of a Diffused Resistor, Solid-State

Electronics 14, 433-438 (1971)

.

21. Shepela, A. , The Specific Contact Resistance of Pd„Si Contacts on n~ and p-Si, SolidState Electronics 16, 477-481 (1973).

22. Dunham, K. R. , Solid-State Photoresist Technology, Solid-State Technology 14_, No. 6,

41-46 (1971).

23. Clark, K. G. , Properties and Processes for Photoresists in Semiconductor Manufacture,

Parts 1 and 2, Solid-State Technology 14, No. 6, 52-56 and No. 9, 48-53 (1971).

24. Fremesser, J. A., Analytical Controls in Photoresist Manufacture, Proc. Microelectronia

Seminar, San Diego, California, December 11-12, 1972, pp. 16-20. (Available from

Eastman Kodak Co., Rochester, New York 14650, Kodak Publication No. P-312.)

25. Schnable, G. L., and Keen, R. S., On Failure Mechanisms in Large-Scale Integrated Circuits, Advances in Electronics and Electron Physics, Vol. 30, L. Marton, ed. , pp. 79-

138. (Academic Press, New York, 1971.)

26. Kern, W. , Vossen, J. L. , and Schnable, G. L., Improved Reliability of Electronic

Devices Through Optimized Coverage of Surface Topography, 11th A.nnual Proceedings

,

Reliability Physics 197Z, Las Vegas, Nevada, April 3-5, 1973, pp. 214-273. (Available

from Publications Sales Dept., The IEEE, 345 E. 47th Street, New York 10017, Catalog

No. 73CH0755-9-PHY.)

27. Adolphsen, J. W. , and Anstead, R. J., Use of the Scanning Electron Microscope As A

Semiconductor Production Line Quality Control Tool, Silicon Device Processing, C. P. Marsden, ed., pp. 384-391, NBS Spec. Publ. 337 (November 1970).

28. Anstead, R. J., and Adolphsen, J. W. , Specification for Scanning Electron Microscope

Inspection of Semiconductor Device Metallization, GSFC-S 311-P-12A, NASA-Goddard Space

Flight Center, Greenbelt, Maryland (12 November 1971).

29. Klippenstein, E. T., and Devaney, J. R. , Scanning Electron Microscope Inspection Procedure for Microcircuits , JPL Procedure EP 505 978, Jet Propulsion Laboratory, Pasadena,

California (September 1971).

30. Beall, J. R. , Scanning Electron Microscope Microelectronic Inspection Criteria Report,

Martin Marietta Corporation, Denver, Colorado (September 1972).

31. Gurev, H. S., A Current Pulse Screening Test for Metal Step Coverage, 11th Annual Proceedings, Reliability Physics 1973, Las Vegas, Nevada, April 3-5, 1973, pp. 245-253.

(Available from Publication Sales Dept., The IEEE, 345 E. 47th Street, New York, New

York 10017, Catalog No. 73CH0755-9-PHY .

)

32. Gurev, H. S. , A Current Pulse Screening Test for Metal Step Coverage, Air Force Weapons

Laboratory Report AFWL-TR-73-107 (March 1973).

33. Crosthwait, Jr., D. L., Ghate, P. B., and Smith, D. M. , Screening of Metallization Step

Coverage on Integrated Circuits, 11th Annual Proceedings, Reliability Physics 1973,

Las Vegas, Nevada, April 3-5, 1973, pp. 254-256. (Available from Publication Sales

Dept., The IEEE, 345 E. 47th Street, New York, New York 10017, Catalog No. 73CH0755-9-

PKY.)

50
REFERENCES

Vossen, J. L. , Screening of Metal Film Defects by Current Noise Measurements, Appl.

Phys. Letters 23, 287-289 (1973).

. Potter, C. N., and Sawyer, D. E. , A Flying-Spot Scanner, Rev. Sai. Instrum. 39_, 180-183

(1968).

Potter, C. N. , and Sawyer, D. E., Optical Scanning Techniques for Semiconductor Device

Screening and Identification of Surface and Junction Phenomena, Physics of Failure in

Electronics, Vol. 5, T. S. Shilliday and J. Vaccaro, eds . , pp. 37-50 (1967). (Available from National Technical Information Service, Springfield, Virginia 22151, Accession No. AD 655397.)

Edwards, A. L. , TRUMP: A Computer Program for Transient and Steady-State Temperature

Distributions in Multidimensional Systems, Lawrence Radiation Laboratory, Univ. of

I California, Livermore, California, UCRL-14754, Rev. II, 1 July 1969. (Available from

National Technical Information Service, Springfield, Virginia 22151, Accession No. UCRL-14754.)

. Oettinger, F. F. , and Gladhill, R. L., Theinnal Response Measurements for Semiconductor

Device Die Attachment Evaluation, Technical Digest, 1972 Int. Electron Devices Meeting,

VJashington, D. C, December 3-5, 1973, pp. 47-50. (Available from Publication Sales

Dept., The IEEE, 345 E. 47th Street, New York, New York 10017, Catalog No. 73CH0781-5-

ED.)

I, Goldfarb, S. Wire Bonds on Thick Film Conductors, Proceedings 1971 21st Electronic

Components Conference, Washington, D. C, May 10-12, 1971, pp. 295-301. (Available

from IEEE, 345 E. 47th Street, New York, New York 10017, Catalog No. 71 C7-PMP.)

^ Harman, G. G. , Ed., Semiconductor Measurement Technology: Microelectronic Ultrasonic

i Bonding, NBS Spec. Publ. 400-2 (January 1974).

h Tentative Recommended Practices for Determining Hermeticity of Electron Devices with a

' Helium Mass Spectrometer Leak Detector, ASTM Designation F134-72T, Annual Book of ASTM

i Standards, Part 8. (Available as a separate reprint from American Society for Testing

1 and Materials, 1916 Race Street, Philadelphia, Pennsylvania 19103.)

Howl, D. A., and Mann, C. A., The Back-Pressurising Technique of Leak-Testing, Vacuum

15, 347-352 (1965).

Diode Test Holder, 9.375 GHz (X-Band) , DESC Assembly Drawing D65019 and Sliding Load

j (X-Band), DESC Assembly Drawing C 65042. (Available from DESC-ES, 1507 Wilmington Pike,

Dayton, Ohio 45401.)

Sawyer, D. E. , Rogers, G. J., and Huntley, L. E., Measurement of Transit Time and Related Transistor Characteristics, Air Force Weapons Laboratory Report AFWL-TR-73-54

October 1973. (Available from National Technical Information Service, Springfield,

Virginia 22151, Accession No. AD 914258.)

51
APPENDIX A SEMICONDUCTOR TECHNOLOGY PROGRAM STAFF

* Coordinator: J. C. French

* Secretary: Miss B. S. Hope

Consultant: C. P. Marsden^^

F. H. Brewer

Dr. M. G. Buehler

Miss F. C. Butler"*

M. Cosman

Mrs. K. E. Dodson'+

Dr. J. R. Ehrstein

.T. E. Griffin'^

Semiconductor Characterization Section

(301) 921-3625

Dr. W. M. Bullis, Chief

F. R. Kelly'^ Dr. R. Y. Koyama

Mrs. K. 0. Leedy

Dr. D. C. Lewis

R. L. Mattis

Dr. A. G. Lieberman

H. E. Dyson

G. G. Harman

W. J. Keery

H. K. Kessler

Semiconductor Processing Section

(301) 921-3541

Dr. A. H. Sher, Chief

J. Krawczyk

T. F. Leedy

Y. M. Liu

§ Miss C. A. Main

Electron Devices Section

(301) 921-3622

F. F. Gettinger, Acting Chief

D. L. Blackburn

V. L. Boxwell

R. L. Gladhill

Mrs. A. D. Glover"*

Part Time

Secretary

Summer

Telephone

Telephone

Telephone:

Telephone

:

(301) 921-3357

(301) 921-3621

(301) 921-3622

(301) 921-3625

J . M . Kenney

Mrs. B. A. Oravec

M. K. Phillips

11+

M. C. Rhodes

G. J. Rogers

U

52
APPENDIX B SEMICONDUCTOR TECHNOLOGY PROGRAM PUBLICATIONS

or Reports

A review of the early work leading to this Program is given in Bullis, W. M. , Measuret methods for the Semiconductor Device Industry — A Review of NBS Activity, NBS Tech.

e 511, December, 1969.

Quarterly reports covering the period July 1, 1968, through June 30, 1973, were pubhed as NBS Technical Notes with the title Methods of Measurement for Semiconductor MateIs, Process Control, and Devices. These reports may be obtained from the Superintendent

Documents (Catalog Number C. 13. 46: XXX) where XXX is the appropriate technical note number

rof iche copies are available from the National Technical Information Service (NTIS)

ingfield, Virginia 22151.

luarter' Ending NBS Tech. Note Date Issued NTIS Accession

ikember 30, 1968 472 December 1968 AD 681330

Jjember 31, 1968 475 February 1969 AD 683808

;|ch 31, 1969 488 July 1969 AD 692232

30, 1969 495 September 1969 AD 695820

itember 30, 1969 520 March 1970 AD 702833

^mber 31, 1969 527 May 1970 AD 710906

ich 31, 1970 555 September 1970 AD 718534

je 30, 1970 560 November 1970 AD 719976

itember 30, 1970 571 April 1971 AD 723671

.lember 31, 1970 592 August 1971 AD 728611

ch 31, 1971 598 October 1971 AD 732553

le 30, 1971 702 November 1971 AD 734427

itember 30, 1971 717 April 1972 AD 740674

lumber 31, 1971 727 June 1972 AD 744946

ch 31, 1972 733 September 1972 AD 748640

30, 1972 743 December 1972 AD 753642

tember 30, 1972 754 March 1973 AD 757244

ember 31, 1972 773 May 1973 AD 762840

ch 31, 1973 788 August 1973 AD 766918

E 30, 1973 806 November 1973

rent Publications

As various phases of the work are completed. publications are prepared to summarize

ults or to describe the work in greater detail. Copies of most such publications are

|ilable and can be obtained on request to the editor or the author.

yer, D. E. , Rogers, G. J., and Huntley, L. E., Measurement of Transit Time and Related

asistor Characteristics, Air Force Weapons Laboratory Report AFRL-TR-73-54 (October 1973)

"liable from National Technical Information Services, Springfield, Virginia 22151,

ession No. AD 914258.

afft, H. A., Failure Analysis of Wire Bonds, 11th Annual Proceedings^ Reliability Physics

Las Vegas, Nevada, April 3-5, 1973, pp. 98-104. (Available from Publication Sales

;t., The IEEE, 345 E. 47th Street, New York, New York 10017, Catalog No. 73CH0755-9-PHY .

I
APPENDIX B

]

Leedy, K. 0., Scanning Electron Microscope Examination of Wire Bonds from High-Reliability j Microelectronic Devices, NBS Tech. Note 785 (August 1973). .\

Oettinger, F. F. , and Gladhill, R. L., Thermal Response Measurements for Semiconductor

Device Die Attachment Evaluation, Technical Digest, 1972 International Electron Devices

Meeting, Washington, D. C, December 3-5, 1973, pp. 47-50. (Available from Publications

Sales Dept., The IEEE, 345 E. 47th Street, New York, New York 10017, Catalog No. 73CH0781-

5ED.) \

Harman, G. G., Ed., Semiconductor Measurement Technology: Microelectronic Ultrasonic Bondini

NBS Spec. Publ. 400-2 (January 1974). ^

Schafft, H. A., Semiconductor Measurement Technology: ARPA/NBS Workshop I. Measurement

Problems in Integrated Circuit Processing and Assembly, NBS Spec. Publ. 400-3 (February .197/

Forman, R. A., Thurber, W. R. , and Aspnes, D. E., The Second Indirect Band Gap in Silicon,

to be published in Solid State Communications.

54

I
APPENDIX C WORKSHOP AND SYMPOSIUM SCHEDULE

oceedings or Reports of Past Events:

Symposium on Silicon Device Processing, Gaithersburg, Maryland, June 2-3, 1970 —

Proceedings: NBS Spec. Publ. 337 (November 1970).

ARPA/NBS Workshop I. Measurement Problems in Integrated Circuit Processing and

Assembly, Palo Alto, California, September 7, 1973 — Report: NBS Spec. Publ.

400-3 (February 1974).

lendar of Future Events:

ARPA/NBS Workshop II. Hermeticity, Gaithersburg, Maryland, March 29, 1974. For

information, contact H. A. Schafft or S. Ruthberg (301) 921-3625.

Spreading Resistance Sympositmi, Gaithersburg, Maryland, June 13-14, 1974. (Cosponsored

by ASTM Committee F-1 and' NBS) . For information, contact J. R. Ehrstein

(301) 921-3625 or-P. H. Langer (215) 439-7131.

* ARPA/NBS Workshop III. Test Patterns, Scottsdale, Arizona, September 6, 1974. For

information, contact H. A. Schafft or M. G. Buehler (301) 921-3625.

Tentative date and location.

55
APPENDIX D STANDARDS COMMITTEE ACTIVITIES

ASTM Committee F-1 on Electronics

M. G. Buehler, Semiconductor Measurements Subcommittee; Process Controls Section

W. M. Bullis, Editor, Semiconductor Crystals Subcommittee; Secretary, Editorial Subcommittee; Semiconductor Measurements, Semiconductor Processing Materials, Hybrid

Microelectronics, and Quality and Hardness Assurance Subcommittees; Insulating

Materials Section; Advisory Coimnittee

J. R. Ehrstein, Chairman, Resistivity Section; Semiconductor Crystals, Semiconductor

Processing Materials, Semiconductor Measurements, and Hybrid Microelectronics

Subcommittees

J. C. French, Chairman, Editorial Subcommittee; Secretary, Advisory Committee; Semiconductor Crystals, Semiconductor Processing Materials, Semiconductor Measurements,

Hybrid Microelectronics, and Quality and Hardness Assurance Subcommittees

G. G. Harman, Secretary, Interconnection Bonding Section

B. S. Hope, Committee Assistant Secretary

K. 0. Leedy, Chairman, Interconnection Bonding Section

T. F. Leedy, Dielectrics Section

D. C. Lewis, Semiconductor Crystals, Semiconductor Processing Materials, Semiconductor

Measurements, Hybrid Microelectronics, and Quality and Hardness Assurance

Subcommittees

C. P. Marsden, Committee Secretary; Advisory Committee

R. L. Mattis, Semiconductor Crystals, Semiconductor Measurements, and Editorial

Subcommittees

D. B. Novotny, Editor, Semiconductor Processing Materials Subcommittee

W. E. Phillips, Chairman, Lifetime Section; Secretary, Semiconductor Crystals Subcommittee; Semiconductor Processing Materials, Semiconductor Measurements, and Hybrid

Microelectronics Subcommittees

S. Ruthberg, Semiconductor Processing Materials, Hybrid Microelectronics, and Quality

and Hardness Assurance Subcommittees

A. H. Sher, Semiconductor Crystals, Semiconductor Processing Materials, and Hybrid

Microelectronics Subcommittees

W. R. Thurber, Semiconductor Crystals and Semiconductor Measurements Subcommittees

ASTM Committee E-10 on Radioisotopes and Radiation Effects

W. M. Bullis, Subcommittee 7, Radiation Effects on Electronic Materials

J. C. French, Subcommittee 7, Radiation Effects on Electronic Materials

Electronic Industries Association: Solid State Products Division, Joint Electron Device

Engineering Council (JEDEC)

J. M. Kenney, Microwave Diode Measurements, Committee JC-21 on UHF and Microwave Diodes

F. F. Oettinger, Chairman, Task Group JC-11,3-1 on Thermal Considerations for Microelectronic Devices, Committee JC-11 on Mechanical Standardization; Technical

56
' APPENDIX D

Advisor, Thermal Resistance Measurements, Committees JC-22 on Rectifier Diodes and

Thyristors, JC-20 on Signal and Regulator Diodes, JC-25 on Power Transistors, and

JC-30 on Hybrid Integrated Circuits

S. Rubin, Chairman, Council Task Group on Galvanomagnetic Devices

D. E. Sawyer, Task Group JC-24-5 on Transistor Scattering Parameter Measurement Standj ards, Committee JC-24 on Low Power Transistors

H. A. Schafft, Technical Advisor, Second Breakdown and Related Specifications, Committee

JC-25 on Power Transistors

E Electron Devices Group

! J. C. French, Standards Committee

1 J. M. Kenney, Chairman, Standards Committee Task Force on Microwave Solid-State Devices

II (Mixer and Video Detector Diodes)

H. A. Schafft, Chairman, Standards Committee Task Force on Second Breakdown Measurement

I Standards

!e Magnetics Group

1 S. Rubin, Chairman, Galvanomagnetic Standards Subcommittee

E Parts, Hybrids, and Packaging Group

W. M. Bullis , New Technology Subcommittee, Technical Committee on Hybrid Microelectronics

iety of Automotive Engineers

' J. C. French, Subcommittee A-2N on Radiation Hardness and Nuclear Survivability

; W. M. Bullis, Planning Subcommittee of Committee H on Electronic Materials and Processes

j F. F. Cettinger, Electronic Systems Steering Committee

I TC47, Semiconductor Devices and Integrated Circuits

,1

I S. Rubin, Technical Expert, Galvanomagnetic Devices; U.S. Specialist for Working Group

I 5 on Hall Devices and Magnetoresistive Devices

J

I

57
APPENDIX E SOLID-STATE TECHNOLOGY & FABRICATION SERVICES

Technical services in areas of competence are provided to other NBS activities and oth

government agencies as they are requested. Usually these are short-term, specialized ser- vices that cannot be obtained through normal commercial channels. Such services provided

during the last quarter, which are listed below, indicate the kinds of technology available

to the program.

1. Thin Metal Films (J. Krawczyk and T. F. Leedy)

Thin films of a gold-germanium alloy and nickel were evaporated onto gallium

arsenide substrates for the Harry Diamond Laboratories.

Thin films of chromium were evaporated onto quartz flats for the NBS Dimensional

Technology Section.

2. Ultrasonic Machining (J. Krawczyk and M. Cosman)

Holes were ultrasonically machined into sapphire plates for the Harry Diamond

Laboratories

.

Holes were ultrasonically machined in thermocouple junctions for the NBS Instrumentation Applications Section.

3. SEM Technical Services (W. J. Keery)

Scanning electron micrographs of marble specimens from the Lincoln Memorial were

taken for the NBS Materials and Composites Section.

*

4. Channel Electron Multipliers and Silicon Nuclear Radiation Detectors (Y. M. Liu)

Evaluation of channel electron multipliers for the NASA Goddard Space Flight Center

continued. The fatigue characteristics (degradation of gain and resolution as a function of! radiation exposure) of a wide-mouth multiplier of the type to be used in sounding rocket

auroral particle experiments were determined.

A commercial silicon surface barrier detector with keyhole-shaped electrodes on both sides was scanned first with a f inely-collimated beam of 1.5-MeV protons to determine

edge effects and then uncollimated 14-MeV protons to determine the counting sensitivity of

the regions of the device outside the keyhole area.

+

5. Ribbon Wire Technology (H. K. Kessler)

Assistance to the Naval Electronics Laboratory Center, San Diego, in the implementation of NBS-developed ribbon wire technology on their pilot production line continued.

Pull strength measurements and analysis of data from NBS and NELC results were performed to

aid NELC in achieving control of ribbon wire bonding parameters. A five-day visit was also

made to NELC -to implement control procedures . ,

* NBS Cost Center 4254429

t NBS Cost Center 4254448

58
Announcement of New Publications on Semiconductor Measurement Technology

Superintendent of Documents,

Government Printing Office,

Washington, D.Co 20402

Dear Sir:

Please add my name to the announcement list of new publications to be issued in the series: National Bureau of Standards Special Publication 400-.

Name

Company

Address

City State Zip Code

(Notification Key N-413)
NBS-1 14A (REV. 7-73)

U.S. DZPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. publk:ation or report no. NBS SP-400-1

2. Gov't Accc-s.sion No.3. Recipient'.s Acces.sion No.

4. TITLE AND SUBTITLE 5. Publication Date March 1974

Semiconductor Measurement Technology: Quarterly Report

July 1 to September 30, 1973.

6. Performing Organization Codi

7. AUTHOR(S)

W. Murray Bullis, Editor

8. Performing Organ. Report No

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

10. Project/Task/VCork Unit No. See Item 15

12. Sponsoring Organization Name and Complete Address (Street, City, State, ZIP) NBS,

Washington, D. C. 20234; Defense Advanced Research Projects

Agency, 1400 Wilson Blvd., Arlington, Va. 22209; Defense Nuclear

Agency, Washington, D. C. 20305.

1 1. Contract/Grant No. ARPA

Order 2397, Pgm Code

^DIO; DNA lACRO 74-811, 13. Type of Report & Period Covered Interim July

to September 30, 19731

14. Sponsoring Agency Code

15. SUPPLEMENTARY NOTES 4251126, 4252128, 4254115, 4259522, 4259555.

16. ABSTRACT (A 200-word or less {actual summary of most sigr^idcant information. If document includes a significant

bibliography or literature survey, mention it here.) ThiS quarterly prOgreSS report, tWenty-firSt Of H

series, describes NBS activities directed toward the development of methods of measure

ment for semiconductor materials, process control, and devices. Principal accomplishments during this reporting period include (1) extension of the technique for measurin

thermally stimulated current and capacitance to include measurements on MOS capacitors

(2) completion of the development of the thermal response method for evaluation of tra: sistor die attachment, (2) analysis of the interlaboratory comparison of transistor

scattering parameter measurements, (4) preliminary review of measurement problems in tl photolithographic aspects of semiconductor device processing, of problems associated

with certain hermeticity testing procedures, and of methods for evaluating metallizati

step coverage, and (5) initiation of new activity on characterization of oxide films ii MOS structures and analysis of diffusion profiles. Results are also reported on spreading resistance, capacitance-voltage, and sheet resistance measurements; the acti|

vation energy of the gold acceptor in silicon; evaluation of the base-to-metal contact!; resistor test structure; metallurgical systems for ultrasonic bonding; burn-out characteristics of fine gold and aluminiom bonding wire; transistor themal resistance measurt

ments; and microwave diode conversion loss measurements. Supplementary data concerning

staff, publications, workshops and symposia, standards committee activities, and techni,

cal services are also included as appendices. j

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name; separated by semicolons) Contact resistance; die attachment; dopant profiles; electricc

properties; electronics; gold-doped silicon; hermeticity; metallization; methods of mes surement; microelectronics; microwave diodes; mobility; MOS devices; oxide films; photc

masks; photoresist; resistivity; resistivity standards; scanning electron microscopy;

semiconductor devices; semiconductor materials; semiconductor process control; sheet re sistance; silicon; S-parameters; spreading resistance; test patterns; thermal resistance; thermally stimulated capacitance; thermally stimulated current; wire bonds.

18. AVAILABILITY . Unlimited

I

' For Official Dist ribution. Do Not Release to NTIS

Order From Sup. of Doc, U.S. Government Printing Office Washington, D.C. 20402, SD Cat. No. C13 . 10 ! 4U0-1

Order From National Technical Information Service (NTIS)

Springfield, Virginia 22151 (Microfiche only)

19. SECURITY CLASS

(THIS REPORT)

UNCL ASSIFIED

20. SECURITY CLASS

(THIS PAGE)

UNCLASSIFIED

21. NO. OF PAGEI

22. Price 51.15

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