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U.S. DEPARTMENT OF COMMERCE/National Bureau of Standards

A Satellite-Controlled Digital Clock

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NBS TECHNICAL PUBLICATIONS

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A Satellite-Controlled Digital Clock

OF STANDARDS

LIBRARY JUL 2 2 1976

^- /6cA(ft>cai

J. V. Cateora

D. D. Davis

D. W. Hanson

Time and Frequency Division

Institute for Basic Standards

National Bureau of Standards

Boulder, Colorado 80302

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U.S. DEPARTMENT OF COMMERCE, Elliot L. Richardson, Secretary

James A. Baker, III, Under Secretary

Dr. Betsy Ancker-Johnson, Assistant Secretary for Science and Technology

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director

Issued June 1976
NATIONAL BUREAU OF STANDARDS TECHNICAL NOTE 681

Nat. Bur. Stand. (U.S.), Tech Note 681, 46 pages (June 1976)

CODEN: NBTNAE

For sale by the Superintendent of Documents, U.S. Government Printing Office , Washington, D.C. 20402

(Order by SD Catalog No. C13. 46:681) $1.05
CONTENTS

1. INTRODUCTION

2. SYSTEM DESCRIPTION

2.1 FORMAT

2.2 TIME CODE DISTRIBUTION

2 .

3

TIME CODE GENERATION

2.4 TIME CODE RECEPTION

3. DIGITAL CLOCK DESCRIPTION

3 .

1

DIGITAL CLOCK CIRCUITRY

3.2 SOFTWARE LISTING

3.3 DIGITAL CLOCK PERFORMANCE

4. CONCLUSION

5. REFERENCES

FIGURES

FIGURE 1 SMS/GOES COVERAGE

FIGURE 2 INTERROGATION MESSAGE AND TIME CODE FORMATS

FIGURE 3 TIME CODE DISTRIBUTION

FIGURE 4 TIME CODE GENERATION AND CONTROL EQUIPMENT

FIGURE 5 RECEIVER BLOCK DIAGRAM

FIGURE 6 TIME DELAY THROUGH A GEOSTATIONARY SATELLITE AT 115° WEST

LONGITUDE

FIGURE 7a TYPICAL DELAY DIURNALS FOR THE EASTERN SATELLITE WITH

WALLOPS ISLAND TRANSMITTING

FIGURE 7b TYPICAL DELAY DIURNALS FOR THE WESTERN SATELLITE WITH

WALLOPS ISLAND TRANSMITTING

FIGURE 8a SOFTWARE FLOW CHART

FIGURE 8b SOFTWARE FLOW CHART (CONTINUED)

FIGURE 9a RAM MAP

FIGURE 9b REGISTER MAP

FIGURE 10 DIGITAL CLOCK BLOCK DIAGRAM

FIGURE 11 MICROPROCESSOR CLOCK PHASE LOCKED TO DATA CLOCK

FIGURE 12 DIGITAL CLOCK SCHEMATIC

FIGURE 13 DIGITAL CLOCK DISPLAY SCHEMATIC

FIGURE 14 DIGITAL CLOCK, DISPLAY, AND PATH DELAY SLIDE RULE

1

1

3

3

6

6

10

14

20

20

40

41

2

4

5

7

8

9

9

11

12

15

15

16

18

19

21

22
FIGURE 15a DISPLAY BOARD (FRONT) 23

FIGURE 15b DISPLAY BOARD (BACK) 24

FIGURE 15c CLOCK BOARD (FRONT) 2 5 FIGURE 15d CLOCK BOARD (BACK) 26

FIGURE 15e CLOCK BOARD COMPONENT LAYOUT 27

FIGURE 15

f

DISPLAY BOARD COMPONENT LAYOUT 2 7 FIGURE 16 UTC(MBS) - SATELLITE CLOCK (MICROPROCESSOR) 36

FIGURE 17 DIGITAL CLOCK PERFORMANCE MEASUREMENT SETUP 37

FIGURE 18 UTC(NBS) - SATELLITE CLOCK (TTL) 39
A SATELLITE-CONTROLLED DIGITAL CLOCK

J. V. Cateora, D. D. Davis, and D. W. Hanson

A digital clock, resettable and controlled by the time code

relayed by NOAA's SMS/GOES satellites, is discussed. The clock's

design is based upon a four-bit microprocessor and uses the redundancy of the data to improve its performance. Satellite position

is included in the clock's display for delay corrections to the

received time.

A discussion of the generation, distribution, and reception of

the time code is also included to aid the explanation of the clock's

operation and performance.

Key Words: Clock; microprocessor; satellite; time; time code.

1. INTRODUCTION

This report describes a digital clock developed by the National Bureau of

Standards (NBS) which is controlled by a time code transmitted from the National

Oceanic and Atmospheric Administration's (NOAA's) meteorological satellites.

The first two satellites launched in this series are known as the Synchronous

Meteorological Satellites (SMS) with all others following designated as Geostationary Operational Environmental Satellites (GOES) . Long-range plans for

these NOAA Satellites call for the positioning of one satellite at approximately

135 degrees West Longitude, another at 75 degrees West Longitude, and a third

to be an in-orbit spare. The approximate coverage of these satellites is shown

in figure 1. As these satellites deteriorate with age, replacement satellites

will be launched. This planned configuration of satellites is expected to be

in effect by early 1976. During most of 1975, one satellite was operated from

115 degrees West Longitude, an intermediate point between the two planned locations mentioned.

The time code is used by NOAA in a data collection program where the SMS/

GOES satellites relay data from remote observing platforms such as buoys, automatic weather stations, ships, aircraft, and balloons to a processing facility.

Many of these platforms will use the time code to date the data as they are collected or to time order their data transmissions to the satellites. NBS

designed and implemented the time code for these satellites. To insure com- patibility of the time code with the data collection platforms (DCP) , NBS designed a digital clock using a simple low-cost microprocessor. The microprocessor approach to the digital clock design was taken because it offered

the lowest cost and provided the flexibility to include or delete functions

through software changes rather than hardware redesign.

The microprocessor-based digital clock described in this report has a number

of interesting and innovating features. It uses a priori information to improve

the effective bit error rate experienced in the satellite link. It also provides the information needed to compute the propagation path delay corrections

to the received signals. The total system performance has indicated a 20 ys

precision with accuracies better than 100 ys. The digital clock, once set by

the satellite time code, continues to keep time with or without reference to the

satellite signal.

The parts cost for the digital clock without the power supply is less

than $200 at the time of this writing. Power input is approximately 7 watts or

160 mA at -10 volts dc and 1 ampere at 5 volts dc.

2, SYSTEM DESCRIPTION

This section describes the time code system including its generation, distribution, format, and reception. The reception of the time code is described

assuming the use of a receiver which was developed under a NOAA contract. This

receiver is part of the Data Collection Platform Radio Set (DCPRS) designed for
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unattended operation over long periods of time, severe environments, and low

power consumption. Obvious improvements can be achieved if the receiver is

designed as a timing receiver and the above mentioned requirements relaxed.

Because no other receiver existed at this time, all references to reception

assume the use of this receiver.

2 . 1 FORMAT

The time information, a digital time code, is multiplexed into an interrogation message format relayed by the SMS/GOES satellites. The interrogation

message is used to activate a transfer of a DCP ' s collected data to NOAA's

Wallops Island, Virginia, facilities via the SMS/GOES satellites. The format

consists of a 15-bit maximum-length sequence (MLS) for message synchronization

immediately followed by 31 bits comprising a (31, 21) binary Bose-ChaudhuriHocquenghem (BCH) code. Four additional bits preceed each MLS sequence beginning on the 0.5 second and comprise a binary coded decimal (BCD) character

of the time code.

Figure 2a shows the interrogation message format: Four time code bits

followed by 15 bits of the message synchronization word and 31 bits of the

address word. The pattern is repeated every 0.5 second, at a 100 bits per sec- ond rate. The leading edge of the first bit to every time code character defines the UTC 1/2 second mark. Figure 2b is the time code format; four bits

are extracted from the interrogation frame every half second for 30 seconds.

The first 40 bits is the time code synchronization message consisting of 10

BCD character A's beginning on the UTC minute mark and 10 BCD 5's beginning

at the UTC half minute mark.

Following the code synchronization message are 10 BCD characters of the

time code followed by 13 BCD characters representing the satellite's current

position in geocentric longitude and latitude and its radial departure from

a reference orbit expressed in microseconds.

2.2 TIME CODE DISTRIBUTION

The interrogation message is sent to the SMS/GOES spacecraft at S-Band

from Wallops Island, Virginia, and is retransmitted to the earth through a global antenna at approximately 469 MHz. The Manchester coded message phasemodulates the carrier ±60 degrees. The interrogation message is received

mainly by data collection platform radio sets (DCPRS) which provide the

communication interface with rain and river gauges, ships, buoys, seismograph

stations, tide gauges, and tsunami detectors. The DCPRS recovers the data and

a data clock from the received interrogation message, the data clock being

used for symbol synchronization.

When a DCPRS is addressed, its stored data are transmitted to the SMS for

relay to the Wallops Island Command and Data Acquisition Station (CDA) . In some cases, such as the monitoring of seismic activities, it is desirable to

label the data with the date of occurrence. Attempts to use internal clocks

set by infrequent clock carries or by reception of HF or LF radio signals are expensive, labor intensive, and subject to an unacceptable failure rate. The

time-of-year code in the interrogation format eliminates these problems and

provides the SMS/GOES DCS user with a cheap, reliable, and simple system for

data labeling or any other time ordered function required at remote sites or

in difficult environments.

Figure 3 illustrates the time code distribution. Derived from atomic

clocks located at the CDA in Wallops Island, Virginia, the time code is com- bined with the current satellite position, multiplexed with the interrogation

address and sync word and transmitted to the satellites at S-Band. The satellites transpond the signal back to earth at approximately 469 MHz where it

is received by the DCPRS' s.

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2.3 TIME CODE GENERATION

NBS has installed at the CDA at Wallops Island, Virginia, equipment to

generate the time code and maintain Coordinated Universal Time (UTC) to within

a few microseconds of the master clock at NBS in Boulder, Colorado. Figure 4 is a block diagram of the equipment. There are two atomic frequency standards

each driving a clock and format generator making two independent systems. Each

system, provides the time code and satellite position to DCS racks A and B for

multiplexing into the interrogation channels of the two SMS/GOES satellites.

All components of each system are hacked with rechargeable batteries with sufficient capacity to operate four hours without primary power. Should a failure

be experienced in one of the time reference systems the other can be switched in

until it is repaired. The frequency of the atomic frequency standards can be

compared to the NBS frequency standard in Boulder, Colorado, using a frequency

meter operating on television sianals. This comparison is accomplished by NBS

staff at routine intervals. Satellite position is computed at NBS Boulder from

orbital elements issued by NASA's Goddard Space Flight Center and sent to

Wallops Island by telephone. An automatic answerina system connects the telephone line to a memory bank which stores the positions in the form of a large

table valid for 128 hours for the two satellites. The time code format generator addresses the memory with the date (days, hours, and minutes) and fetches

the currently valid position for multiplexing into the interrogation message.

The interrogation channels on both satellites are monitored continuously

in Boulder. Any failure or drift of the clocks at Wallops Island is automatically noted for appropriate action.

2.4 TIME CODF RECEPTION

The interrogation channel is received by the DCPRS which usually consists

of a receiver and transmitter. A block diagram of the receiver is shown in

figure 5. The transmitter section of the DCPRS has been left out since it has

no bearing on this discussion. The demodulator consists of a phase lock loop ^ with a 10 Hz loop bandwidth and a timing recovery loop to derive the data clock

for symbol synchronization. The demodulator provides outputs of data and data

clock, the two inputs to the digital clock. The signals from the satellite

occupy a bandwidth of 400 Hz, and have a sianal level of approximately -139 dBm

at the output of an isotropic antenna. A DCPRS receiver and digital clock has

been successfully and reliably operated using both linearly and circularly

polarized antennas v/ith gains as low as 3 dB.

The signal delay from Wallops Island to the earth's surface via the SMS/

GOES satellites is nominally 260,000 ys. This delay is a function of distance

from the subsatellite point as shown in figure 6. As a first order correction

for delay, the time signals are advanced by 260,000 ys at Wallops Island thereby

forcing them to be nearly on time when arriving at the earth's surface. Since

the satellite is not in a perfect geostationary orbit, that is, it has some inclination and eccentricity, the delay experienced at any one point has a diurnal component. ^he magnitude of the diurnal is also position dependent. Typical peak-to-peak values of the diurnals for the Eastern and Western satellites

are shown in figures 7a and 7b.

The data clock is a sequence of alternating ones and zeros used for symbol

synchronization. The RAM clock measures the accumulation of time. The microprocessor clock is the oscillator governing the function of the microprocessor.

The digital clock refers to the system (microprocessor, software, 1/0, and display) used to maintain time referenced to the time code from the satellite.

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FIGURE 5- RECEIVER BLOCK DIAGRAM

FIGURE 6. TIME DELAY THROUGH A GEOSTATIONARY

SATELLITE AT 115° WEST LONGITUDE
LONGITUDE

FIGURE 7a. TYPICAL DELAY DIURNALS FOR THE EASTERN SATELLITE

WITH WALLOPS ISLAND TRANSMITTING

LATITUDE

LONGITUDE

FIGURE 7b. TYPICAL DELAY DIURNALS FOR THE WESTERN SATELLITE WITH WALLOPS ISLAND TRANSMITTING
3. DIGITAL CLOCK DESCRIPTION

The digital clock was built to interface with NOAA's DCPRS's as they

existed in early 1974. A microprocessor design was chosen because of its potential low cost and simplicity. The microprocessor design replaced a previous

random logic design amounting to 80 integrated circuit packages. Special features and properties of time messages were used in the microprocessor design.

For example, each successive time-code frame differs only by 30 seconds, the

length of the frame. Thus the messages have a large degree of redundancy. This

fact was used to, in effect, increase the signal-to-noise ratio or lower the bit error rate. The a priori information was used as follows: The microprocessor

stores the time-of-year in random access memory (RAM.) and continually updates

itself by counting the 100 Hz data clock. During every time-code frame received

from the satellite the microprocessor compares its RAM time with the new time

message. If there is agreement, everything is assumed to be in order. If there

is disagreement, the microprocessor will continue to assume that the RAM clock

has the correct time, but after four consecutive time frame disagreements the

RAM. clock is assumed to be in error. The microprocessor will then reset its

RAM clock to the next time code message providing the satellite time is being

received as evidenced by the presence of the MLS and time code synchronization

word. This procedure is referred to as an error bypass capability.

The 100 Hz data clock from the receiver is also subject to noise introducing

additional zero crossings that can be interpreted by the microprocessor as 0.01

second increments in time. To minimize the effect of this noise and provide a reliable and continuous 100 Hz to count even without the satellite signal, the

microprocessor system crystal oscillator is divided down to 100 Hz and phase

locked to the received data clock. The phase locked 100 Hz is then used as the

time base for the microprocessor time-of-year (TOY) clock.

The two above mentioned procedures have used the cyclic nature of the data

and data clock to improve the performance of the digital clock.

The satellite ephemeris is displayed as received. Consequently, it is

susceptible to more error than the TOY. One can only look for consistency in

the display from frame to frame. The display is updated at the 00 and 30

seconds. Two successive frames of the same data insure the correct satellite

position data is being displayed.

To fully understand the details of the operation of the digital clock, it

is well to review the basic tasks it accomplishes. P thorough familiarity with

the format of the interrogation channel is important to this understanding.

Repeated reference to the software flow chart, figures 8a and 8b would also

be helpful. We begin the explanation by assuming that the digital clock has

just been connected to the receiver and is receiving the interrogation channel

properly. The digital clock has available to it the data and the data clock.

It must look at the data clock for a negative going transition to identify when

to sense the data and acquire one bit of information. In other words, it

acquires symbol synchronization by looking at the data clock. When the proper

data clock transition is recognized, it samples the data and stores the sampled

bit in memory, an index register of the CPU. In fact, the last 15 bits of data

have been stored in index registers. After each bit is received and stored,

the last 15 bits stored are examined for the MLS (100010011010111). If the latest

stored 15 bits match the sequence stored in program memory, MLS synchronization

is declared. The microprocessor now knows the location of the four bits in

every interrogation frame constituting a time code BCD character. The microprocessor then loads these four bits every half second into an index register

and examines it to determine if it is part of the time code synchronization

word, a BCD A or 5 depending on whether the frame is in the first or second

half of the minute. When 10 consecutive A's or 5's are found, time code synchronization is declared. The next four bits to be loaded are the tens of seconds

(TS) of the time code, then unit minutes (UM) , tens of minutes (TM) , etc., for

the next 11 1/2 seconds or 21 four bit characters finishing with the units of

microseconds of the satellite distance. These data are all written into RAM

memory.

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The microprocessor now counts bits and frames until it arrives at the TS

character of the next frame. It does not search for MLS or code sync again since

total synchronization may be maintained by simply counting the 100 Hz time base over to the beginning of the next time code frame. On the second pass of a time

code frame the microprocessor only compares the newly arrived character of the

TOY with the corresponding internal RAM character. Should this comparison fail

anywhere in the TOY frame it will be counted as a frame error. If four con- secutive frame errors occur, the microprocessor will begin a new search for MLS

and time code sync. When successfully achieved the satellite TOY will be written into the RAM clock, resetting the RAM clock. If the microprocessor does not

find MLS and time code synchronization it will not disturb the RAM clock. This

prevents the RAM clock from being reset when no satellite signal is present.

The RAM clock consists of characters representing days, hours, minutes,

seconds, tenths of seconds, and hundredths of seconds. The data clock is

derived at Wallops Island from an atomic clock. Each cycle of the data clock

represents 1/100 of an atomic second and is counted by the microprocessor to

update its RAM clock. The microprocessor has its system oscillator phase locked

to the incoming data clock. If the data clock is lost, the internal oscillator

will continue to provide the 0.01 s count to keep the RAM clock accurate.

The RAM clock, excluding the 0.1 s and 0.01 s digits, is multiplexed for

display by LED's under microprocessor control. The satellite position is

loaded into RAM memory every frame as received. At the 00 and 30 second RAM

storage of position is transferred to an external shift register and multiplexed

to LED's under independent control. Consequently, if the satellite signal is

lost, the satellite position will also disappear from the display.

The program for controlling the microprocessor occupies two 8 bit x 256

programmable Read Only Memories (pROMs) , that is, 512 eight-bit bytes. The

actual program requires about 460 bytes.

The program consists of a main program called START of about 210 bytes,

subroutine WAIT of about 175 bytes, subroutine SPOS of about 25 bytes, subroutine L0AD4 of about 30 bytes and subroutine WAIT100 of about 20 bytes.

The main program START first establishes "MLS" sync by comparing the

latest 15 bits received with the 15 bits of the known MLS pattern stored in

pROM. This locates the correct starting point in the bit stream to start looking for BCD characters, that is, identifies the BCD characters of the time code.

Next, START looks for 10 "A" or 10 "5" characters in order to establish

"CODE" or frame sync. Every 30 seconds the code contains either ten 1010-

(BCD character "A") patterns starting at 00 s or ten 0101- (BCD "5") patterns

starting at 30 s. Once "CODE" sync has been established the next BCD character

received will be tens of seconds. Establishment of "MLS" and "CODE" sync is

indicated by lights on the digital clock's display board.

When the digital clock is first turned on, and after both sync words are

found, the received TOY and satellite position are written into RAM by START.

In subsequent passes of the received code only position information is written

into RAM unless discrepancies are found between the received TOY and the TOY

stored in RAM.

Subroutine WAIT is called by START to find data bits as they appear at the

input port. When one is found, WAIT increments the RAM clock by 0.01 s. WAIT

also contains the coding for displaying the TOY. When an 8000 Hz transition is

sensed at the input port, WAIT displays one digit of the TOY.

Subroutine SPOS is called by WAIT after the RAM clock has been updated and

the time is 0.00 or 30.00 s. When called, SPOS loads the satellite position

characters from RAM into the position display hardware which otherwise runs independently of the microprocessor.

-13-
L0AD4 is called by main program START to reconstruct a BCD character from

four data bits. L0AD4 calls WAIT to locate the necessary four bits and stores

the built-up BCD character in an index register reserved for this purpose.

WAIT100 is a subroutine of 18 bytes whose only purpose is to keep the

clock's 1 pps as nearly on time as possible. It is called by WAIT when time

is .99 s and waits only for the next .01 s pulse to occur, the instant when the

1 pps should be output, and ignores any 8000 Hz pulses for display. As soon as the .01 s pulse is sensed by WAIT100 it outputs the 1 pps. If a scheme such

as WAIT100 were not used, the microprocessor could sense an 8000 Hz pulse and

be occupied by performing its display function when the .01 s pulse, signaling

a change in unit seconds, occurs and could not output the 1 pps until many program steps later. The use of WAIT100 keeps the 1 pps on time within about 30 us. Without WAIT100 the 1 pps occurs randomly within 400 us of being on time.

A complete listing of the program appears on pages 28 through 35. Figures

9a and 9b show the microprocessor's register maps. Figure 10 shows a loaical

block diagram of the program.

3.1 DIGITAL CLOCK CIRCUITRY

The 4004 Central Processing Unit (CPU) , 4702A programmable Read Only

Memory (pROM) , 4002 Random Access Memory (RAM) , 4008 Address Latch and 4009

Input/Output Multiplexers, 4201 Clock Generator, and TTL random logic packages

form the microprocessor digital clock (see figure 10) . The 4000 family of MOS

microprocessor chips was chosen primarily because they are low cost four-bit

devices and well suited for handling four-bit characters. The 4004 CPU was selected because of its low cost, easy availability and its proven history of

use.

The microprocessor has one four-line input port, to which the received

satellite signals are connected and eight four-line output ports which are assigned as follows:

Output Port Function

Input port reset

1 Satellite position BCD character

2 Time-of-Year display strobe

3 Time-of-Year BCD character

4 "MLS" and "CODE" sync indicator lights

5 1 pulse per second voltage pulse

6 spare

7 spare

One RAM output Port is also used to disable the satellite position display clock

while the satellite position display is being serviced.

The hardware is divided between two circuit boards. One board contains the

microprocessor along with its input and output circuitry. The other board con- tains seven-segment Light Emitting Diodes (LED's) and associated TTL random logic

to display the 22 time-of-year and satellite position characters. The 9 time-ofyear LED's are multiplexed one digit at a time at approximately an 8000 Hz rate

under microprocessor control. The 13 satellite position characters are stored

in a hex-32 shift register and multiplexed by a free-running hardware clock at

about a 60 kHz rate. The satellite position display is updated by the microprocessor every half minute at 00 and 30 seconds. This combination of display

methods was chosen to avoid LED flicker associated with multiplexing 22 characters under the control of a processor with many other sequential tasks.

-14-
t i r

31 and 46 Counter

Reconslruct BCD Chor

RAM Char Wnle Select, 37 Counter -4 1 hSave Data In "2" Sit -+ h- HTOY Output Port Select _| -j 4_

Multiplex Port Select

General Use

REG

PAIR

31 and 46 Counter

10 A/S Counter, Write Flag, Frame Error Counter

RAM Chor Write Select, 37 Counter

TOY Char. Error

I 1 f

TOY Choracter

Multiplex Counter

Generol Use

I J_

FIGURE 9a. RAM MAP

REG CHAR STATUS CHAR 12 3 4 5 6 7 8 9 A B C D E F D 1 2 3 8

- 4

2

1

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1

3 SRC

EVEN

MLS SYNC PATTERN

FIGURE 9b. REGISTER MAP

12 4 8 12 4 8 12 4 8 12 4 8 10 10 1 1 1 1 1 1 12 3 4 5 6 7 8 9 10 II 12 1314 1516 2 2 B E

-Received First Data Is Transmitted

-Filled In Last Least Significant

Bit First

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The Manchester encoded TOY and position data phase modulates the 469 MHz

carrier ±60 degrees. Fron this are derived a 100 Hz data clock and serial

binary data. The microprocessor's basic clock is 4.096 MHz which is frequency

divided by 8x2x16x16x10 (=40960) to provide a frequency of 100 Hz. This 100 Hz

signal is phase compared with the 100 Hz data clock and a voltage proportional

to the phase difference is fed back to a pair of varactor diodes in parallel

with the 4.096 MHz microprocessor clock crystal to phase lock the 4.096 MHz

clock to the recovered data clock. Figure 11 is a block diagram of the phase

lock loop and microprocessor input circuitry. The phase lock loop and input

port arrangement is important because if the satellite signal is lost for any reason or for any length of time, the 100 and 8000 Hz signals will still be

present as they are now being derived from the crystal controlled microprocessor

system clock. Fven though the 100 Hz data clock is lost, the microprocessor

will continue to update its RAM clock with the accuracy of the microprocessor's

system clock. The satellite position information is not updated under these

conditions and will be lost.

The microprocessor's one input port is connected as shown in figure 12.

The 100 Hz satellite data clock is fed to the input port's "1" line through a 7474 latch. The "2" line is fed the 8000 Hz, through a latch also, derived

from the frequency divider chain operating on the 4.096 MHz microprocessor

clock. The input port "4" line is not used and the "8" line is connected to

the received 100 Hz serial binary data.

The microprocessor, through software program control, samples the input

port "1" line connected to the 100 Hz satellite data clock. If a 100 Hz transition is sensed the program updates an internal BCD clock stored in RAM by 0.01 s. The RAM clock is in the form of 11 4 bit BCD characters representing DDD , HH,

MM, SS, ts, hs, that is, Day, Day, Day, Hour, Hour etc., down to .Is, .01 s. The

.01 s update of the RAM clock and the appropriate carries ripple up to the tens

of hours BCD character. The characters representing days are set by actually

reading the received code into RAM.

The sensing of a 100 Hz transition at the input port "1" line also triggers

the storage of data present at the "8" line as one bit of the four bits of a BCD charater. Four 100 Hz data clock transitions, sensed at the appropriate

time, will therefore cause the RAM clock to be updated and one BCD character

representing TOY or satellite position to be saved.

After looking for a 100 Hz transition, and whether or not one is found, the

microprocessor next attempts to sense an 8000 Hz transition at the input port's

"2" line. If an 8000 Hz transition is sensed, one digit of the date will

be displayed on a 7-segment LED display character. If no 8000 Hz transition is

sensed the microprocessor loops back and continues attempting to find either a 100 or an 8000 Hz transition. Basically then, the microprocessor spends its

time looking for one of two conditions, a 100 or an 8000 Hz transition and then

either updates its RAM clock or displays a character. Although the RAM clock

contains BCD characters representing .01 and .1 s they are not displayed.

The microprocessor continuously compares the received TOY characters with

the TOY characters stored in RAM. If four consecutive comparison frame errors occur the next received TOY character is rewritten into RAM and will be displayed. Four consecutive frame errors were chosen as the criterion for resetting

the RAM clock to lessen the possibility of a noisy or marginal received signal

causing an unintentional time reset. Experience with the digital clock under

noisy signal conditions has shown this to be a good choice, but not necessarily

the optimum strategy for all environments.

Display of TOY is accomplished by a 7-segment decoder on the display board

which receives the BCD data and time-of-day characters from output port #3 and

drives the display segments. The associated multiplex count from output port

#2 is decoded by a 1 to 16 multiplexer with 2N3638 transistors driving the LED

strobe inputs.

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Figure 13 shows the wiring diagram of the display board. Figure 14 shows

the clock, display, and a "delay slide rule." This slide rule is used to com- pute the delays from Wallops Island, VA, to the user's location via the satellite using the satellite position data contained in the time code format. See

references 1-3 for more detail on the design and use of this slide rule. Figures

15a - 15f provide board layout and component location information.

The satellite position display consists of a hex-32 shift register which

stores the 13 satellite position characters plus three blank characters twice

over. The 32 characters are then clocked out of the shift register in sequence

by a hardware clock on the display board that runs independently of the microprocessor. The output of the shift register goes into a 7-segment decoder and

the 13 position characters are displayed. The position display runs by itself

and receives attention from the microprocessor only at 00 and 30 s when the

hex-32 shift register is reloaded. Presently the satellite position changes

only each half hour and the shift register receives the same satellite position

information 6 consecutive times. However, in the future it may become desirable to update the position information at a higher rate.

3.2 SOFTWARE LISTING

Pages 28-35 show a listing of the digital clock's software. The program

was punched into standard 80 column data processing cards only as a convenient

method of documentation. The format of the listing is as follows:

Column

1 Hexadecimal page or ROM chip number

2 Blank

3-4 Hexadecimal instruction address within ROM chip

5 Blank

6-7 Hexadecimal microprocessor instruction

8 Blank

9-18 1 to 10 character label

19 Blank

20-22 1 to 3 character operation mnemonic

2 3 Blank

24-33 1 to 10 character operand (data, register, condition, label, etc.)

34-37 Blank

38-80 Comments

Some 4 00 4 instructions require two bytes in which case the second line of

the instructions may contain data or a jump address.

3.3 DIGITAL CLOCK PERFORMANCE

The digital clock has been in operation for many months in a number of

locations but at this time only NBS at Boulder has explored its full potential.

The chart shown in figure 16 illustrates the long-term performance of the digital

clock. The chart represents the time difference between the NBS master clock

and a 1 pps from the digital clock and was obtained using the equipment shown

in figure 17. The chart shows a peak-to-peak noise of less than 40 ys. The

chart also shows the delay diurnal with a peak-to-peak value of approximately

450 ys. This chart was made during November 1975, when the satellite's inclination was approximately 1/2 degree.

The accuracy of the digital clock is dependent upon the correct assignment

of path and equipment delays. The receiver and digital clock delays were studied

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Rl 5

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C8 - 4.7 yf tant.

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FIGURE 15f. DISPLAY BOARD COMPONENT LAYOUT

-27-
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JUN - - 020

COMMENTS

-N&5 SATELLITE -CONTROLLED DIGITAL CLOCK,

TIME OF YEAR ANO SATELLITE POSITION

IN THIS VERSION THE 1 HZ OUTPUT IS

GGN-TROLL-EO TO WITHIN 33 MICRO ScCGNDS

SET I N D E X --REGISTERS 2 THRU F—» G

TU^N OFF MLS AND CODE SYNC LIGHTS

ANOTHER JMS -

- WAIT

FIM PI

2 C CLB

SERIAL SRC PI

ROM

RAR

WRM

ISZ °3

- SERIAL

THIS OATA IS THE MLS SYNC

ADORESSES ARE THt 3AMEAS

GO TO WAIT ANO STAY UNTIL A ICO 0» AN 8000

HZ TRANSITION OCCURS

S^LcCT RAM 0/REG 2/CHARS C THRU F WHERE

15 BIT MLS SYNC PATTERN WILL BE STORED AS

Thi BITS ARE RECEIVED

SHIFT RAM CrirtRS C THRU

BIT TO MAKE ROOM FOP A F (MLS) RIGHT ONE

NEWLY RECEIVED BIT

PATTERN ANO IS STORED HERE BECAUSE THESc ROM

B+E RAM CHARACTER AfrfrRt SSES OF THE ftECETVE-0

MLS SYNC PATTERN ANO THIS SIMPLIFIES THEIR COMPARISON LATER AT ADO. 0<+6 (WILL 3E EXECUTFD AS NOPS>

CHAR F STILL SELECTcO Itt RAM — SETS 16TH

3IT OF k MLS RECEIVED CHARACTERS =

REG 8 CONTAINS A DATA BIT IN ITS 2 POSITION

THIS WAS STOREO IN REG 8 8V WAIT WHEN A 1-&G HZ TRANSITION WAS SENSED ANO A JUMP TO

COUNT OCCURRED

S H IF T OAT-A SACK TO THt ft PO SIT ION READY T~0 ADD TO RAM

SELECT RAM 0/REG 2/CHAR C

RDM

RAR

CLC

RAL

WRM

CLB

LD R6

RAL

RAL

FIM P0

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G 43 32 FIN Pi

44 FC CLE

45 A3 LO R3

46 £6 S8H

47 1C JCN Al

46 21 - ANOTHER

49 71 ISZ Rl

4A 42 - OK

13 4B 20 FIM PC

4C 40 4 4D 21 SPC PC 4E DE LDP P 4F E2 WRR

50 2E FIM ?7

51 It 1 P

Q 52 51 AGAIN JMS - 53 00 -<- WAIT

54 7c I5Z RE 55 52 - AGAIN

56 7F ISZ RF

57 52 - AGAIN

G 5 8 6 LDH 6 59 BD XCH RO

5A 51 JMS -

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5F. 2E MORE FIM P7

5F 2 2 D 60 51 MOPE+2 JMS - 61 CO - WAIT

62 7h ISZ E 63 60 - MORE t-'i 64 7F ISZ F

G 65 60 - MORE+2

66 51 JMS -

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6t» FO CODE SYNC CL n

G 69 20 FIM PC

6A A5 A 5 6B AO LO ^ n 6C 9C SUE RC

60 14 JCN AO

6E 78 - CONTINUE

6F FC CLP

70 Al LO Rl

71 9C SUE RC

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73 78 - CONTINUE

74 06 LDM 6 75 EO XCH RL

fl 76 40 JUN - 77 02 - START

79 70 CONTINUE ISZ RD

79 5E - MORE

u 7A 2C FIM PC

7B 40 4 a 7C 21 SRC PO

70 OC Lon C 7E E2 WRR

7F

ADD NEWEST BIT RLCElYE-Q TO -6 POSITION OF

CHARACTER C, I.E. STORE IT IN RAM

PUT CONTENTS OF ADDRESS OC INTO PI

PUT CONTENTS OF R3 (= E) INTO ACCUMULATOR

SUBTRACT r%AM CHAR C FROM ACCUMULATOR

IF CHAR C = ( ACCUMULATOR INCREMENT Rl ANO

JUMP TO OK TO TEST NEXT RAM CHARACTER

AGAINST DATA

IF THIS POINT IS REACHED MLS MATCHES —

TURN ON MLS LIGHT

Sc.T UP P7 TO COUNT 31 CALLS TO WAIT

MAKE 31 LALLS TO WAIT TO SKIP 31 BITS

BETWEEN MLS AND BOO CHA c ACTcR

INITIALIZE 10 A/5 COUNTER

CALL LOA04 TO MAKE 4 CALLS TO WAIT TO GET

ONE BOO CHARACTER

SET UP TO MAKc 46 CALLS TO WAIT

SKIP 4b CITS BETWEEN BCD CHARACTERS -- ONCE

MLS SYNC IS ESTABLISHED FRAME SYNC ANO CODE

RECEIVING IS DONE 3Y SKIPPING BITS BETWEEN

BCD CHARACTERS

GET' NEXT ECD CHARACTER

ScT UP TEST FGR A OR 5 CHARACTER, THAT IS

LOOK FOR FRAME SYNC

LOAD THE CHARACTER A INTO THE ACCUMULATOR

JUMP TO CONTINUE IF CONTENTS OF RC = CHARACTER A LOAD CHARACTER 5 INTO ACCUMULATOR

JUMP TO CONTINUE IF CONTENTS OF RC - 5

RESET THE 10 A/5 COUNTER TO 6, I.E. GET

READY TO COUNT 10 AS OR 10 5S ANO GO BACK

TO START

GO TO MORE IF NOT 10 AS OR 10 5S FOUND

CODE SYNC IS ESTABLISHED IF THIS POINT IS

REACHED

TU<H OH CODE SYNC LIGHT (KEEP MLS LIGHT Of* ALSO)

-29-
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c 90 60 INCREMENT INC RO

BE AD LO RC

BF

RO IS NOW USED FOR THE WxITc TIME OF YEAR

(TOY) FLAG SET IT = 3

S.L-ECT TOY .91 SECONO CHAkACTER IN RAM

W-ITf- HUMuREGTH SECOND CHARACTER = < IN RAM

W-ITE TENTH SECONO CHARACTER = 5 IN C »H

WRITE UNIT SECOND ChA-ACTLR = < IN RAi

FINDING Id AS OR 13 5S CONSTITUTES COC'E SYNl, ThAT IS LOCATE STAnT OF TOY COll -

COO! SYNC OCCURS AT < . 5 1» ANO 3<*. 54 StCOND

THEREFORE iET UNIT SECONO = k TENTHS SECONO - 5 HUNuREOTHS SECONO = k

StT UP TU SELECT RAM O/KcG J/LHARS b THRU F TIME OF YEAR (TUY)

3> T •'->, TOY CHAxACT_r KRUR FLAG = 3

•5-.T JP U6 31 T COUNTER

SKIP <4& BITS LiETWEEN 9C0 CHARACTERS

GET NEXT TIME OF YEAR CHARACTER

TEST WRITE FLAo (*Q) -- IF NOT = JUMP TO

lO^FAkE -- zLSti WRITE TOY INTO RAM

WPI1E TOY CHARACTERS INTO RAM G/REG 3/

CHARACTcR^ C THPU F INCkcMENT AND TtST FOR 10 TOY CHARACTcRS

READ ANO WRITTEN INTO RAM OP COMFARtJ

TEST R9 (TOY CHAR ERROR FLAG) TO SE;_ IF AT

LEAST ONE TOY CHARACTcR EPROk OCCURRED

DURING THc LAST FkAMc. IF IT DID -- GO TO

INCREMENT TO INCREMENT FRAME cRROR COUNTER

tLSn RESlT FRAME ERROR COUNTER TO 3E ABLE

TO COUNT < CONSECUTIVE FRAME ERRORS

INCREMENT TOY CHAR lRROR COUNTER

-30-
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C8 E 8 SBM

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CA 1U JCN Au

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CC 01 LOM 1

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3 09 13 1 3 OA 2t NEXT13 Fir, 97

CB 2 2 D DC 51 AGAIN13 JMS - 00 OG - WAIT

C D£ 7E ISZ Rt OF DC - A&AIN13

CO 7F ISZ RF El DC - AGAIN13

E2 51 JMS - E3 EO - LOA.Q<*

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E6 EO W^M

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C EB

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EEEF

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o fi BD B F2 2F NEXT37 FIM P7

9 F3 EC E C

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a F5 OC - WAIT

F6 7f ISZ RF7 Fk - AGAIN5u

F8 7F ISZ RF

F9 Fk - AGAIN50

FA 7A ISZ RA

F3 F2 - NEXT37

FC 7S ISZ R*

FO F2 - > N1XT37

FE «fO JUN - FF AC - ITOO

IF RO = THEN < CONSECUTIVE FRAME ERRORS

OCCURRED — GO bACK TO START -- ELSE GO ON

TO RECEIVE SATtLLIT- POSITION INFORMATION

ARRIVE HERE IF WRITE FLAG IRQ) IS NOT = 3

TO COMPARE TCY CHARACTEk IN RC WITH TOY

CHARACTER IN RAM

GO TO RcTURN IF TOD CHARACTER IS THE SAME

SlT -9, CHAR ERROR FLAG =1 ANO GO TO RETURN

IF TOY CHARACTER IS NOT THE SAME

INITIALIZE 13 WORO CuUNT ANO SElECT OF

RAM O/REG 1/CHARACTERS 3 THRU F SATELLITE

POSITION

INITIATc <*6 BIT COUNTER

SKIP <+6 BITS oETWcEN SAT. POS . , CHAR ACTERS

GLT NEXT SATELLITE POSITION CHARACTER

WRITE S*T. POS. CHAR. INTO RAM

INCREMENT SAT. POS. UHAK. ADDRESS IN RAM

WHEN THIS POINT IS REACHtO 13 SAT. POS.

uHakACTF.RS HAVE BEEN RECfclVEO AND WRITTEN

INTO RAM

INITIALIZE FOR 67 FRAME COUNT

INITIALIZE FOR 50 BIT COUNT

SKIP 50 BITS IN A FPAME

SKIP Z7 FRAMES BETWEEN ENu OF SATELLITE

POSITION ANO START OF TIME OF YEAR

GO BACK TO RECEIVl. TIME OF YEAR AGAIN

-31-
4- flfl FO W ATT

1 01 22

1 02 00

4 9^ 2 3

1 3<f EA

1 C5 F6

4 0* 12

1 07 30

1 08

1 99 F6

1 0A 12

1 08 OF

1 GC 41

1 CO 0C

1 CE

1 OF 02 DISPLAY

1 10 E2

1 11 A 7

1 12 1C

1 13 18

1 14 26

1 15 35

i 16 24

1 17 25

1 18 27 NZc'RO

1 19

1 1A E2

1 16 25

1 1C A5

1 10 F4

1 IE E2

1 IF 27

1 20 E9

1 21 F4

1 22 E?

1 23 67

1 24 65

1 25 41

1 26

1 27

1 28

1 29

1 2A

1 28 Bb COUNT

1 2C 01

1 20 E2

1 2E 22

1 2F 20

1 30 23

1 31 DF

1 32 E2

1 33 88

1 34 Fl

1 35 F6

1 36 Fl

1 37 B8

1 38 22

1 39 33

1 3A 23

1 3B E9

1 3C F?

1 3D F8

1 3E EC

1 3F 63

CL8

FIM PI

SRC 4*4 RO?

RAR

40+^-64

- COUNT

RA<= JCN CI

- DISPLAY

JUN - - WAIT

LOM

WRR

LO

JCV

FIM

3FIM

2SRC

LOM

WRF

S = C LD

CM A WRR

SRC

ROM

CMA

WRR

INC

R7

Al

NZE RO

5P2

5P3

P2

R5

P3

°7

INC -R5 JUN -WAIT

XCH RH

LOM 1 WRR

FIM PI

2SRC PI

LOM F WRP

XCH RS

CLC

RAR

CLC

XCH R3

FIM PI

3 3 SRC PI

ROM

I AC

OAA

WRM

INC R3

CLEAR ACCUMULATOR A NO C A RRY

SELECT IN/OUT PORT NO. FOR INPUT AND

R-E-SE-T

JrF 43-9 t+Z IS PRESENT JUMP TO COUNT

ROT ATE-34£9 HZ- INTO CARRY POS44ION

IF 8000 HZ IS PRESENT JUMP TO OISPLAY

CONTINUE LOOKING FOR 100 OR 800G HZ

T^ANilTION

RESET afioO HZ

TEST IF ~7, RAM TOY CHAR AOORESS IS NOT = O

IF R7 = RESET RAM CHIP/ REG/CHAR SELECT

AND ^ES^T MUX STROBE ANO MUX OUTPUT PORT

FOR TIM;l OF YEAR CHARACTER

W

;.ITE BlANK DATA (BLANK = NOT - F)

WRIU OUT TIME OF YEAR STROBE

W^ITE OUT TIME OF YEAR CHARACTER

INCREMENT RAM TOY CHARACTER AOORESS

INCREMENT STROBE

GO BACK ANO WAIT FO* ANOTHER 100 OR 8300 HZ TRANSITION

SAVE INPUT PORT NO. IN *8 TEMPORARILY

W^ITE OUT 1 TO RESET 1J0 HZ LATCH ON

OUTPUT PORT NO. G POINT TOY STR05E AT DISPLAY DIGIT'NO.

WHEN 8000 HZ OCGUkS TO MINIMIZE OISPLAY

FLICKER -- PREVENTS A OiGIT FROM STAYING ON

WHILE CLOCK IS BEING UPOATEO

RESTORE INPUT PORT No . 3 UATA TO ACCUMULATOR

CLEAR 100 HZ FROM CARRY

CLEAR 8-306 HZ (IF PRESENT*

SaVE DATA IN R8 2 BIT POSITION

SELECT RAM 0/REG 3/CHAR 3 THRU F, THAT IS

START WITH TOY .01 SECOND CHARACTER

REAO .01 SECOND CHARACTER INTO ACCUMULATOR

INCREMENT RAM CLOCK BY .31 SECOND

IF CY=1 OR ACCUMULATOR IS GREATER THAN 9 SET ACCUMULATOR = ACCUMULATOR 6

WRITE .01 S BACK INTO SAME RAM LOCATION

-32-
i 40 23 SRG PI

1 41 F7 TCC

1 uz SE- AOM

1 43 ES OAA

1 44 EG WRM

1 45 12 JCN CI

1 46 60 - USE 6

1 47 2C FIN PO

1 48 90 9

1 49 9 SUb RC

1 4A 1C JCN Al

1 48 58 - NOT NINE

1 4C Fl CLC

1 40 20 F I

M

PO

1 4E 33 3 3

1 4F 21 SRC PO

1 50 E9 ROM

1 51 20 Fl* PC

1 52 90 9 a 1 53 9C SUB RC

1 54 1C JCN Al

1 55 58 - NOTNINF

1 56 41 J UN -

1 57 E0 - WAIT1GQ

1 58 Fl NOTNINr CLC

1 59 20 FIM PC

1 5A 5C 5

1 58 21 S°C PO

1 5C DP LOM F

1 50 E2 WRR

1 5£

1 5F

i 60 63 USEC INC R3

1 61 23 SPC PI

1 62 F7 TCC

1 63 EL ADM

1 64 FF OAA

1 65 EC WRM

1 66 63 INC R3

1 67 23 SRC PI

1 63 F7 TCC

1 69 EB ADM

1 6A EO WRM

1 6B DA LDM 10

1 6C EE AOM.

1 60 1A JCN CO

1 6E 71 - MINUTE

1 6F DO LDN

1 70 EO WRM

1 71 63 MINUTE INC R3

1 72 23 S

D C PI

1 73 F7 TCC

1 74 EB ADM

1 75 FF, OAA

1 76 EG WRM

1 77 63 INC R3

1 78 23 SRC PI

1 79 F7 TCC

1 7A £8 ADM

1 70 EO W»M

1 7C DA LOM 10

1 70 EB AOM

1 7E 1A JCN CO

1 7F 82 - HOUR

tN&R-E HE-NT RAM £H ARAGTER--Ar&0*£-5S

CLEAR ACCUMULATOR, MOVE CARRY TO 1 POSITION

OF ACCUMULATOR, CLEAR CARRY

ADD .1 S IN RAM TO CA*RY FROM .01 S CHARACTER IN RAM -- DECIMAL ADJUST ACCUM.

If CY FROM .1 SECOND = 1 DONT TEST FOR ^S

BECAUSE AFT£R THE SUBTRACTION CY IS CLEARED

TENTHS SECOND STILL IN ACCUMULATOR — TEST

FOR TENTHS SECOND = 9

READ .01 SECOND INTO ACCUMULATOR AND TEST

FOR . 01 SECOND = 9

IF .1 ANO .01 SECOND = .99 JUMP TO SPECIA;

WAIT ROUTINl WHICH ONLY WAITS FOR ICO HZ TRANSITION -- ELSc OUTPUT TO PORT NO. 5

OUTPUT F (NEC LOGIC 0) TO PORT NO. 5

ScLECT UNIT SECOND CHARACTER IN RAM

ADD UNIT SECOND CHAkACTER IN >xAM TO CARRY

FROM TENTHS icCONO IN ACCUMULATOR

WRITE UNIT SECOND CHARACTER INTO RAM

SELECT TENS OF SECOND ChARACTER IN *AM

WkITE TENS OF SECOND CHARACTER INTO RAM

ACCUMULATOR STILL CONTAINS T^NS OF SECOND--

ADO 10 -- IF TENS OF SECOND WAS A 6. THEN A CARRY OCCURS -- IF SO SET TENS ScCOND = ANO ADD THE CARRY TU UNIT MINUTES. IF TENS

SECOND CARRY = TH^N SET TcNS SECOND = C SELECT UNIT MINUTE CHARACTER IN RAM

ADD UNIT MINUTE IN RAM TO CARRY FROM TENS

OF SECOND

W^ITE UNIT MINUTES INTO RAM

SELECT TENS OF MINUTES CHARACTER IN RAM

ADD TENS OF MINUTE CHARACTER IN RAM TO

CAR*Y Fk.OM UNIT MINUTES IN ACCUMULATOR AND

WRITE TENS OF MINUTES INTO RAM

IF TENS OF MINUTES = 6 CA^RY OVER TO UNIT

HOURS

JUMP TO HOUR IF TENS OF MINUTES CARRY =

-33-
i -a^ 04 L^M -0 1 81 EO WRM

1 82 63 HOUR INC R3

i 83 23 SRC PI

1 &k F7 rcc

1 85 E3 AON

1 86 F6 OAA

1 87 EO WRM

1 88 6 3 INC R3

i 89 23 SRC PI

1 8A F7 TCC

1 8B EB ADM

i ec EO WRM

1 80 FC CLG

1 8E 22 FIM PI

1 8F 35 3 5

1 90 23 SRC PI

1 91 F9 ROM

1 92 1U JCN AO

1 93 95 - Te~ST33

1 9*» ca BUL

1 95 22 TEST03 FIM PI

1 96 36 3 6

1 97 23 SRC PI

1 98 E9 ROM

1 99 lit JuN AO

1 9A A2 - If NTHS

1 99 22 FIM PI

1 9C 30 3

1 90 92 sue r:

1 9£ Ik JCN AO

1 9F A2 - TENTHS

1 AO FC CLG

1 Al CG B^L

1 A2 22 TL NTHS FIM PI

1 A3 3k 3 k

1 A«» 23 S

S C Fl

1 A5 E9 ROM

1 A6 Ik JCN AC

1 A7 AP - HUNDREDTHS

1 A8 CC B^L

1 A9 22 HUNDREDTHS FIM PI

1 AA 33 3 3

1 A3 23 SRC PI

1 AC E9 ROM

1 AO l<f JCN AC' 1 AE Ck - SFOS

1 AF CD 3 JL

1 BO FO WAIT1G0 Cl6

1 61 2C FIM pp

1 B2 GO J C 1 63 21 SRC PC

1 R<+ EA read ROR

1 B5 F6 =>AF 1 66 1A JCN CC

1 07 Qk - REAG

1 B8 20 FIN PO

1 P9 50 5 G 1 BA 21 SRC PO

1 BB OE LTM E

1 °C E2 HRP

1 BO 01 LDt^ 1

1 BE E2 WRR

1 BF FO CL2

WRIT- UNIT HOUR INTO RAM

SrLtCT TcNS OF HOURS CHARACTER IN RAM

WRITE TENS OF HOURS INTO RA*

READ UNIT SECONO INTO ACCUMULATOR

IF UNIT SECOND = C GO TEST FOR TENS OF

SECOND = u DR 3 -- cLSE RETURN

•<-.AD TENS OF SECOND INTO ACCUMULATOR

IF TENS OF SCCONC = C 0' 3 GO TtST TliMTHS

Sf-ONO = 3 « ElSE RETURN

IF TENTHS OF StCONO = G GO TEST FOR

HUNDREDTHS OF ScCONOS = — cLSE RETURN

IF HUNDREDTHS ScCONO = GO StRVlCE

SATELLITE POSITION DISPLAY -- ELSE RETURN

SPECIAL WAIT ROUTINE TO KEEP 1HZ ON TIME

SELECT IN/OUT PO-\T NU.O FOR INPUT A NO RESET

IF ICG HZ IS NOT FR-5fcNT GO BACK ANC WAIT

SOME MORE — ELSE OUTPUT 1 HZ

OUTPUT E (NEG. LOGIC 1) TC PORT NO. s

WRITE OUT 1 TO RESET 130 hZ LATCH ON

OUTPUT PORT NO. L

-34-
i GO <fl J u^ -

1 CI 6G - USrC

1 C2

1 C3

1 C<* 20 SPOS FII1 PC

1 C5 13 1 3

1 CO 21 src PC1 U 01 LDM 1

1 C8 El WMF

1 C9 22 FIf-' Pi

1 CA IE 1 p

1 CB 21 ^"AM SRC PC

1 cc E9 RU M

1 CO 23 SRC PI

1 CE Fit CM A

1 OF E? WFR

l no 21 SRC Fl

1 Dl 03 LDM 3

1 n2 El WMP

1 03 01 LDM 1

1 Dk El W-'P

1 05 71 ISZ Kl

1 C6 Cr - RFAM

1 07 7 3 ISZ R3

1 08 CO - Rf AM

1 G9 DC L M

1 OA El WMP

1 08 CC 6HL

1 CC

1 DO

1 OE

1 OF

1 F.O DC LOAD** LOM

1 £1 no XCH RF

1 E2 51 JMS -

1 F3 Q - WAIT

1 E<+ Ab LD R4

1 E5 Fl CLC

1 EO F6 RAR

1 E7 80 ADD Rt

1 E9 BC XCH SC

1 E9 51 J MO -

1 EA CO - WAIT

1 EB A8 LU RS

1 FC 6C ADD f? C

1 EO BC XCH RC

1 EE 51 JMS -

1 FF - WAIT

1 FO A3 LO Rt

1 Fl Fl CLC

1 F2 FE RAL

1 F3 8C A 00 RC

1 F*f EC XCh RC

1 F5 51 J

M S

-

1 F6 OC - WAIT

1 F7 AP LD Rfl

1 F8 Fl ClO

1 F9 F5 RAL

1 FA F5 OAL

1 F3 8C ADD RC

1 FC ac XCH RC

1 FD CO BOL

1 FE

1 FF

GO BACK TO PROCESS UNIT SECONDS

SET UP SELECT OF RA M O/REG 1/LHARACTF~S 3 THRU F, SATELLITE POSITION

WRITE A 1 TO RAM OUTPUT PORT TO TURN OFF

2516 SHIFT REGISTERS CLOCK

SET UP OUTPUT PORT NO. 1 SELECT AND Pi

Rr.AO A SATELLITE POSITION CHA- FROM RAM

WP1TL OUT A SATELLITE POSITION CHARACTER TO OUTPUT PO-T NUMBER 1 WRITE A 2 TO RAM OUTPUT PORT TO CLOCK OATA

INT G 2518 SHIFT REGISTER -- BUT A 1 MUST

STILL 3^ UOiNG OUT TO KEEP SHIFT REGISTERS

CLOCK OFF

INCREMENT SATELLITE POSITION CHAR ADDRESS

FILL HEX-32 SHIFT REGISTER <2518> TWICE,

THAT IS, 2*(13 ChAR + 3 BLANKS) = 32 CHAr

WRITE A C TO RAM OUTPUT PORT TO TURN SHIFT

KcSlSTtKS CLOCK BACK ON

CLEAR RC IN PREPARATION TO RECONSTRUCT BCD

GhARACT c R IN RC

GO TO WAIT TO GIT BCD CHARACTER 1 BIT

MOVE uATA 3IT TO 1 POSITION AND ACQ TO RC

GET BOO CHARACTER 2 BIT

DATA BIT IS ALRcADY IN 2 POSITION -- JUST

ADO IT TO RC

GFT BCD CHARACTER h BIT

MOtfc DATA BIT TO k POSITION AND ADO TO RC

GET BCD CHARACTER 8 BIT

MOVE DATA BIT TO 3 POSITION AND AOU TO RC

-35-
oto

tO

UJOOOo

I-<

to

-36-
RECEIVER

Data

Data Clock

Ipps From NBS Master Clock

DIGITAL CLOCK

Ipps

IME INTERVAL COUNTER

START STOP

FIGURE 17- DIGITAL CLOCK PERFORMANCE MEASUREMENT SETUP

37-
separately. The digital clock's delay was measured to be -5074 ys with no significant variation over an observed time of a few weeks. The delay is rather

artificial since it is a function of software and can be set to any value by

instruction. As an example the software can be adjusted to effectively remove delay from the digital clock. The receiver's delay was measured as a function

of signal level and modulation index with the results shown below. The manufacturer specified the receiver's operating range to be between -100 and -130

dBm. The receiver delay for different modulation index was also investigated.

Input Signal

Level

(dBm)

-100

-105

-110

-115

-120

-125

-130

Delay (ys)

Modulation Index

±50° ±60° ±70° - 10,874

10,844

0,838 10,829

10,800

10,748

10,697

10,814

0,626 10,598 10,576

The delay versus signal level over the full manufacturer's specified range

amounted to nearly 300 ys with rather small sensitivity to modulation index.

The receiving system variability implies problems when attempting to achieve a 100 ys time synchronization. A change in antenna gain, local interference

adding to the receiver's total power input, or receiver gain changes can cause problems. The reason for the receiver's delay sensitivity is believed due to

the absence of automatic gain control (AGC) . A limiter was used in the second

IF only. It must be remembered that this receiver was optimized to enhance an ability not directly related to time recovery. Simple modifications should

stabilize its delay considerably.

A discussion of path delay correction will be based on the results shown in

figure 18 taken in the same manner as that of figure 16, but using a clock which

counts the 100 Hz transitions using only TTL circuitry rather than under microprocessor software control. The resolution of the TTL approach is better than

10 ys whereas the microprocessor, using 4 machine cycles (instructions 1B4

through 1B7) , had a peak-to-peak variation of approximately 40 ys. In either

case the following discussion is valid. The equipment delay in this case was

46,162 ys, most of this due to the clock using TTL only for 100 Hz transition

counting.

In figure 18, at point X, the time interval counter indicates UTC(NBS) - Satellite Clock = 40370 ys. The satellite clock also for point X provides the

satellite's position as: Satellite Longitude 114.92°W

Satellite Latitude - 0.38°

Satellite Radius 46 ys

-38-
0£

-39-
The coordinates of NBS Boulder, Colorado, and Wallops Island, Virginia, are:

Longitude Latitude

NBS/Boulder, CO 105.26°W 40.00°N

Wallops Island, VA 75.46°W 37.85°N

Using the delay slide rule, the path delays are computed to be:

Wallops Island to SMS2 128839 ys

SMS2 to NBS/Boulder 125418 ys

Total Path Delay 254257 ys

Equipment Delay 46162 ys

Total Delay 300419 ys

Time Advance at Wallops Island 260000 ys

Expected Time Difference of

Decoder Clock 1 pps and NTC(NBS)

UTC(NBS) - Digital Clock = 40,419 ys

The measured value was

UTC(NBS) - Digital Clock = 40,370 ys

It is therefore concluded that

Wallops Island - UTC(NBS) = 49 ys

Part or all of this difference can be associated with:

a) Satellite position error

b) Equipment delay error at Boulder

c) Clock error at Wallops Island

d) Equipment delay at Wallops Island (assumed negligible)

e) Ionosphere and troposphere (not accounted for)

4. CONCLUSION

A simple and inexpensive clock has been designed using a four-bit

microprocessor which is set and controlled by the interrogation channel of a SMS/GOES satellite. Preliminary measurements show the clock and its associated

system to provide a time resolution of better than 40 microseconds and an accuracy better than 100 microseconds. The accuracy is presently limited by the

delay uncertainty in the system, mainly the receiver, and by the uncertainty

in the satellite's predicted position.

NBS is continuing an effort to reduce and account for all sources of error. A delay stable receiver to reduce the equipment delay uncertainty will be developed in later phases of the program. A potentially more accurate satellite

ephemeris generator will replace the present generator and a path delay correcting clock will be developed, as an extension to the basic clock described, to

allow for high accuracy automatic time recovery.

-40-
5 . REFERENCES

[1] . Hanson, D. W. , Hamilton, W. F., "Time and Frequency Broadcast Experiments

from the ATS-3 Satellite," NBS Technical Note 645, (November 1973).

[2]. Hanson, D. W. , Hamilton, W. F., "Satellite Broadcasting of WWV Signals,"

IEEE Transactions on Aerospace and Electronic Systems, Vol. AES , No. 5,

pp. 562-573, (September 1974).

[3]. Hamilton, W. F., Hanson, D. W. , "A Synchronous Satellite Time Delay

Computer," NBS Technical Note 638, (July 1973).

-41-
NBS-114A (REV. 7-73)

U.S. DEPT. OF COMM.

BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO.

NBS-TN-681

2. dov't Accession

No.

3. Recipient's Accession No.

4. TITLE AND SUBTITLE

A Satellite-Controlled Digital Clock

5. Publication Date June 1976

6. Performing Organization Code

7. AUTHOR(S)

J. V. Cateora, D. D. Davis, and D. W. Hanson

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUKEAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

10. Project/Task/Work Unit No. 2776043

11. Contract/Grant No.

12. Sponsoring Organization Name and Complete Address (Street, City, State, ZIP)

Same as item 9

13. Type of Report & Period Covered

Final

14. Sponsoring Agency Code

NBS

15. SUPPLEMENTARY NOTES

None

16. ABSTRACT (A 200-word or less factual summary of most significant information. If document includes a significant

bibliography or literature survey, mention it here.)

A digital clock, resettable and controlled by the time code relayed

by NOAA's SMS/GOES Satellites, is discussed. The clock's design is

based upon a four bit microprocessor and uses the redundancy of the data

to improve its performance. Satellite position is included in the

clock's display for delay corrections to the received time.

A discussion of the generation, distribution, and reception of the

time code is also included to aid the explanation of the clock's

operation and performance.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name; separated by semicolons

)

Clock; microprocessor; satellite; time; time code.

18. AVAILABILITY , fc Unlimited

~2 For Official Distribution. Do Not Release to NTIS

| X

' Order From Sup. of Doc, U.S. Government PtiatiagjQffice

" Washington, D.C. 20402, SD Cat. No. CI 3 • ^O : Po '

]] Order From National Technical Information Service (NTIS)

Springfield, Virginia 22151

19. SECURITY CLASS

(THIS REPORT)

UNCLASSIFIED

20. SECURITY CLASS

(THIS PAGE)

UNCLASSIFIED

21. NO. OF PAGES

46

22. Price

Si. 05

USCOMM-DC 29042-P7 U.S GOVERNMENT PRINTING OFFICE:1976-677-347 / 1274 REGION NO. 8
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards' was established by an act of Congress March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology

and facilitate their effective application for public benefit. To this end, the Bureau conducts

research and provides: (1) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau consists of the Institute for Basic Standards, the Institute for Materials Research, the Institute for Applied Technology,

the Institute for Computer Sciences and Technology, and the Office for Information Programs.

THE INSTITUTE FOR BASIC STANDARDS provides the central basis within the United

States of a complete and consistent system of physical measurement; coordinates that system

with measurement systems of other nations; and furnishes essential services leading to accurate and uniform physical measurements throughout the Nation's scientific community, industry,

and commerce. The Institute consists of the Office of Measurement Services, the Office of Radiation Measurement and the following Center and divisions:

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materials needed by industry, commerce, educational institutions, and Government; provides

advisory and research services to other Government agencies; and develops, produces, and

distributes standard reference materials. The Institute consists of the Office of Standard

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the use of available technology and to facilitate technological innovation in industry and Government; cooperates with public and private organizations leading to the development of

technological standards (including mandatory safety standards), codes and methods of test; and provides technical advice and services to Government agencies upon request. The Insti- tute consists of the following divisions and Centers: Standards Application and Analysis — Electronic Technology — Center for Consumer

Product Technology: Product Systems Analysis; Product Engineering — Center for Building

Technology: Structures, Materials, and Life Safety; Building Environment; Technical Evaluation and Application — Center for Fire Research: Fire Science; Fire Safety Engineering.

THE INSTITUTE FOR COMPUTER SCIENCES AND TECHNOLOGY conducts research and provides technical services designed to aid Government agencies in improving cost effec- tiveness in the conduct of their programs through the selection, acquisition, and effective utilization of automatic data processing equipment; and serves as the principal focus within

the executive branch for the development of Federal standards for automatic data processing

equipment, techniques, and computer languages. The Institute consists of the following

divisions: Computer Services — Systems and Software — Computer Systems Engineering — Information Technology.

THE OFFICE FOR INFORMATION PROGRAMS promotes optimum dissemination and

accessibility of scientific information generated within NBS and other agencies of the Federal Government; promotes the development of the National Standard Reference Data System and

a system of information analysis centers dealing with the broader aspects of the National Measurement System; provides appropriate services to ensure that the NBS staff has optimum

accessibility to the scientific information of the world. The Office consists of the following

organizational units: Office of Standard Reference Data — Office of Information Activities — Office of Technical

Publications — Library — Office of International Relations — Office of International Standards.

1 Headquarters and Laboratories at Gaithersburg. Maryland, unless otherwise noted; mailing address Washington, D.C. 20234.

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^

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'^K-lQl6 s

TS> YEARS NBS 1901-1976