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NBSIR 80-2006-2 AlllOS Q3T30S

Semiconductor Technology

Program

Progress Briefs

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W. Murray Bullis, Editor

Electron Devices Division Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

U.S. Department of Commerce

Washington. D.C. 20234

KJune 1980

Prepared for The Defense Advanced Research Projects Agency

The National Bureau of Standards

The Division of Electric Energy Systems, Department of Energy

The Division of Distributed Solar Technology, Department of Energy

The Defense Nuclear Agency

The Charles Stark Draper Laboratory

The Naval Air Systems Command

The Air Force Wright Aeronautical Laboratories

The Naval Weapons Support Center

The Solar Energy l^esearch Institute

The Naval Avionics Center

The Lewis Research Center, National Aeronautics & Space Administration

The Office of Naval Research

The Naval Ocean Systems Center

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80-2006-

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NBSIR 80-2006-2

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AlllOS 03T30S

Semiconductor Technology

Program

Progress Briefs

HAT10M4A. BVBSAl or 8TAMDAXD9

UBItAKT

OCT 1 0 1980

x>04p- r

W. Murray Bullis, Editor

Electron Devices Division Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

U.S. Department of Commerce

Washington, D.C. 20234

June 1980

Prepared for The Defense Advanced Research Projects Agency

The National Bureau of Standards

The Division of Electric Energy Systems, Department of Energy

The Division of Distributed Solar Technology, Department of Energy

The Defense Nuclear Agency

The Charles Stark Draper Laboratory

The Naval Air Systems Command

The Air Force Wright Aeronautical Laboratories

The Naval Weapons Support Center

The Solar Energy Research Institute

The Naval Avionics Center

The Lewis Research Center, National Aeronautics & Space Administration

The Office of Naval Research

The Naval Ocean Systems Center
SEMICONDUCTOR TECHNOLOGY PROGRAM

TABLE OF CONTENTS

MOSFET dc Profiler 3 Heavy Doping Effects in Silicon .... 3 PVW Applications 3 Ion-Implanted Profiles 4 Optical Linewidth Measurements 5 Transistor Switching Characteristics . . 6 Process -Induced Radiation Damage .... 7 Acoustic Emission Testing 8 Work in Progress 8 Recent Publications 9 Publications in Press 10

ABSTRACT — This report provides information on the current status of NBS work on measurement technology for semiconductor ma- terials, process control, and devices. Re- sults of both in-house and contract research are covered. Highlighted activities include: studies of MOSFET dc profiler, heavy

doping effects in silicon, WW applications,

ion-implanted dopant profiles, optical linewidth measurements on wafers, process- induced radiation damage, transistor switching characteristics, and acoustic emission

testing. Brief descriptions of selected

on-going projects are included, and recent publications cuid publications in press are listed. The report is not meant to be ex- haustive; contacts for obtaining further in- formation are listed. KEY WORDS — Electronics; integrated circuits; measurement technology; microelectronics; semiconductor devices; semiconduc- tor materials; semiconductor process control; silicon.

Preface

This report covers results of work during the forty-seventh quarter of the NBS Semiconductor Technology Program. This Program serves to focus NBS research on improved measurement technology for the use of the semiconductor device community in specifying materials,

equipment, and devices in national and international commerce, and in monitoring and con- trolling device fabrication cuid assembly. This research leads to carefully evaluated,

well-documented test procedures and associated technology which, when applied by the industry, are expected to contribute to higher yields, lower cost, and higher reliability of semiconductor devices and to provide a basis for controlled improvements in fabrication processes and device performance. By providing a common basis for the purchase ^ecifications of government agencies, improved measurement technology also leads to greater economy

in government procurement. Financial support of the Program is provided by a variety of Federal agencies. The sponsor of each technical project is identified at the end of each

entry in accordance with the following code: 1. The Defense Advanced Research Projects

Agency; 2. The National Bureau of Standards; 3. The Division of Electric Energy Systems,

Department of Energy; 4. The Division of Distributed Solar Technology, Department of Energy; 5. The Defense Nuclear Agency; 6. The C. S. Draper Laboratory; 7. The Naval Air Systems

Conmand; 8. The Air Force Wright Aeronautical Laboratories; 10. The Naval Weapons Support

Center; 11. The Solar Energy Research Institute; 12. The Naval Avionics Center; 13. The Lewis Research Center, National Aeronautics and Space Administration; 14. The Office of Naval Research; and 15. The Naval Ocean Systems Center. This report is provided to disseminate results rapidly to the semiconductor community.

It is not meant to be complete; in particular, references to prior work either at NBS or elsewhere are omitted. The Program is a continuing one; the results and conclusions re- ported here are subject to modification and refinement. Further information may be ob- tained by referring to more formal technical publications or directly from responsible

staff members, telephone: (301) 921-listed extension. General information, past issues of progress briefs, and a list of publications may be obtained from the Electron Devices Division, National Bureau of Standards, Washington, D.C. 20234, telephone: (301) 921-3786.

2
<NBS> Semiconductor Technology Program

Progress Briefs

MOSFET dc Profiler

As part of a study aimed at characterizing a variety of buried-layer implants

under simulated CCD processing steps,

a MOSFET dc profiler was used to profile

four different ion implants of the type

used for radiation-hardened, buriedchannel CCD imagers. The purpose of the

study is to obtain data which may lead

to an implant schedule which will yield

greater CCD radiation tolerance without

sacrificing full-well capacity. The

profiler is a rectangular MOSFET with a channel length of 28 ym, fabricated on an n-type <11 1> silicon wafer with nominal room-temperature resistivity of 10 fi’cm. Two wafers were implanted with phosphorus at 140 keV to a fluence of 1.5 x 10^^ or 3 X 10^^ cm“^ through an oxide

approximately 10 nm thick to randomize

the distribution of the implanted ions.

The overall agreement between the re- sults obtained from the two profiling

methods is generally quite good; but

there are some systematic differences.

A more detailed analysis is being made.

[Sponsor: 2] (G. P. Carver, x3541,

and J. R. Ehrstein, x3625)

Heavy Doping Effects in Silicon

A Study was completed of the disappearance of shallow donor impurity levels in

silicon and germanium at large dopant

densities which results from freecarrier screening of the impurity ions.

The ground state eigenfunctions eind eigenvalues were calculated for electrons

described by an ellipsoidal effective- mass Hamiltonian in the screened Coulomb

field of an isolated donor impurity

atom. An extreme case in which the

longitudinal-to-transverse effectivemass ratio is 100: 1 was also considered.

The solutions were obtained with the use of a two-dimensional finite-element

analysis which includes adaptive mesh

procedures. terticular care was taken

to assure that there is no addition of

electron states to the total number as- sociated with the perfect crystal. The

study was restricted to donors because

the valence band is degenerate, and

therefore the mathematics associated

with shallow acceptor impurity levels is more complex.

The results show that the donor level moves closer in energy to the conduction

band with increasing donor density.

Only moderate carrier densities ('^^10^^ cm“^ for silicon and '\/10^® cm“^ for germemium) at room temperature are needed

to cause the impurity levels to com- pletely disappear into the conduction

band. It is concluded that a more heavily doped, essentially uncompensated

semiconductor should be treated as simply degenerate with appropriate cujcount

taken of the band distortions which cure due to the interactions of the conduction electrons with the screened impurity ions as well as with each other. In- clusion of a distinct impurity band at high dopant densities, which has the effect of pinning the Fermi energy within

the forbidden gap, is not correct.

[Sponsor: 2] (J. R. lowney euid C. L. Wilson,

x3625, A. H. Kahn,* and J. L. Blue+

)

PWV Applications

The test results from a process validation wafer (PVW) were successfully uti-

*NBS Ceramics, Glass, and Solid State Science Division.

"^NBS Scientific Computing Division. 3
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Wafer maps shcMing correlation between

metal-to-ri*' contact resistance (left)

and sheet resistance of the layer

(right). Darker symbols represent

larger values.

lized to identify an unsuspected problem

affecting wafer fabrication process control in a radiation-hardened silicongate CMOS/SOS process at a commercial

manufacturer. Ibe PVW contained test

pattern NBS-16 replicated at 95 sites on the wafer. This test pattern contains a wide variety of parametric test structures, including MOSFETs , contact resistors, cross-bridge sheet resistors, euid capacitors, in addition to random fault

test structures.

Test results from 18 PVWs indicated a wide range in the magnitude of metal-tori*- contact resistance from lot to lot

and across a wafer. Very little variation in the metal-to-p'*’ contact resistance was observed indicating that the

problem was not a function of the

contact-window photolithography process.

Wafer maps of metal-to- r& contact re- sistance and sheet resistance for

the PVW accompanying one of the wafer

lots are seen in the accompanying fig- ures. The approximate correlation between the two maps suggests that the cause of high metal-to-n'*’ contact re- sistance was a low phosphorus concentration at the silicon surface. This surface concentration was controlled by a phosphorus implant through the gate ox- ide layer into the source and drain re- gions of the epi island. Subseo[uent

testing of MOS capacitors indicated that

the gate oxide was thicker in the areas

of lowest phosphorus concentration. It was concluded that vcuriations in the

gate oxide thickness caused the peak of

the phosphorus implant to vary between

the silicon and silicon dioxide, vrtiich in turn resulted in significant variations in the number of phosphorus atoms

reaching the silicon surface cind caused

the observed variation in metal-to-n'*’ contact resistance. It was possible to solve this problem by increasing the

accelerating potential of the implant to reduce the effect of gate oxide thick- ness on the number of idiosphorus atoms

which reach the silicon. [Sponsor; 8] (L. W. Linholm, x3541

fon-Implanted Profiles

Atom depth distributions for arsenic

channeled deeply in the <110> direction

of a silicon crystal, measured by secon- dary ion mass spectrometry ( SIMS ) , show

agreement with carrier depth distributions previously measured for similar

(but lower fluence) 300-keV arsenicchanneled implcints by differential

capacitance-voltage (C-V) profiling

techniques. The silicon wafers were cut from 100-fi*cm float-zoned crystals with

(110) faces. The cursenic was implanted

at several angles with respect to the

<110> crystallographic direction: accu- rately aligned (within '^^0.05 deg of the

<110> axis, for maximum eixial channeling) eund 0.50, 1.00, amd 2.00 deg away

from the <110> axis in a direction to- ward a random equivalent orientation

(REO). Alignment angles were measured

by Rutherford backscattering.

The atom depth distributions were mea- sured using a cesium ion beam and by re- cording the secondary positive ions at mass 75. The SIMS crater depths were measured using a surface profiioraeter

The atom densities were determined by

equating the integrals of the depth distributions to the implantation fluences.

The excellent background-subtracted detection limit of 1 X lO^^cm"^ for ar- senic in silicon was instrumental in obtaining the results reported here.

4
The carrier depth distributions were measured by differential capacitancevoltage techniques on 125-pm diameter

gold Schottky barrier diodes. Tlie use of 100 fi’cm float-zoned silicon was re- sponsible for the detection limit of

about 1 X 1 0 1 cm” 3 for the carrier profiles. Hie estimated error in both the

SIMS and C-V depth scales is +10%; however, the agreement found between the

two different techniques suggests a smaller error. The results are illustrated in the ac- companying figure. Hiese results show

that the atom depth distributions of eur- senic channeled in the <11 0> direction

of silicon can be measured by SIMS, that

these depth distributions euid those of

the associated carriers measured by differential C-V profiling are simileu: in

shape and both give a most probable

channeling range at the peak of the

DEPTH, Depth distribat ions of atoms measured by

SIMS and of associated carriers measured

by differential C-V for 300-keV arsenic

ions channeled in the <110> direction of

a silicon lattice as a function of

al ignment angle.

channeled distribution of 3.35 to 3.40

pm and a maximum channeling range of

about 4.0 pm for the 300-keV ion energy,

that the saturated or maximum cursenic

atom density achievable under these con- ditions is 'T'1.5 X 10^^ cm”^, that no significant redistribution of channeled

arsenic atoms occurs ijpon annealing at 800®C for 30 min, that little if any

degradation of the channeled profile oc- curs for 0.50-deg misalignment from the

<110> direction of silicon, and that

significant degradation, as measured by

both SIMS (atom density) and C-V (associated carrier distribution) , occurs for

misalignment euigles of 1.0 and 2.0 deg.

[Sponsor: 1] (D. R. %ers,+ x3625)

Optical Linewidth Measurements

In contrast to earlier work with nearly

opaque photomasks, optical linewidth

measurements on wafers encompass materials with a much wider variation in optical parameters 2uid material profiles.

Accurate optical edge detection requires

corrections for both the relative re- flectance and phase at the line edge be- cause of the partial coherence present

in optical microscopes used for linewidth measurements. However, measurement systems which cannot provide the

appropriate corrections and cannot detect edge location accurately can be

calibrated, provided that the repeatability of the measurement is satisfactory. The NBS reflected light scanning photometric microscope was used to calibrate

a wafer made by contact printing an an- tireflective chromium mask onto a 150-nm

thick layer of silicon dioxide on silicon. The wafer was plasma etched to get

the steepest possible material edges.

The pattern contained linewidths between

0.5 and 11 ym with both polarities.

This wafer was then measured on a variety of commercially available linewidth

measurement systems. In each case, the

*NBS contact: work carried out by R. G. Wilson, H. L. Dunlap, D, M, Jamba, and P. K. Vasudev of Hughes La- boratories and V. R. Deline and C. G. Hopkins of Charles Evans and Associates.

5
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_ LINEWIDTH (pm)

Difference (measured values minus NBS

values) for filar (dashed) and imageshearing (solid) systems vs. NBS laser

1 inewidth measurements . Filar and

image-splitting systems used center of

dark band at the line edge for measurement. These data apply only to a 150-nm

thick etched silicon dioxide layer.

optical microscope was set up following

the NBS-recommended procedures for photomasks which includes the use of Kohler

illumination, a coherence parameter R

of 2/3, and broadband green (WR60) spectral illumination.

Measurements were made with an optical

filar eyepiece (dashed crosshair) , a coincidence-setting image-shearing system with video display, two types of

photometric scanning systems using different edge detection methods, and a video image-scanning system. Ihe re- sults for the first two of these systems are shown in the accompanying figure.

The principal effect illustrated is the

polarity-dependent edge detection error expected from use of the center of the

dark interference band to determine the

edge location. In both cases, the data

could be used as calibration data to correct for this known systematic

error.

In principle, since the calibration

curve is material dependent, a calibration curve is required for each material

and each thickness corresponding to each

step in the wafer fabrication process

where linewidth measurements are made.

However, it is not feasible to provide

calibration wafers for, or calibrate,

linewidth measurement systems for all

combinations of relative reflectance and

phase for all materials of interest. An alternative approach is to supply a small number of calibration wafers and

calibrate the system using the one which most closely matches the un)cnown

in relative reflectance and j^ase. The

maximum possible error would be known

and a correction could be applied if the

relative reflectance and phase of the

unknown were measured. The accuracy of

this proposed calibration method is dependent upon the predictability and precision of the calibration curves for a given instrument euid remetins to be determined for systems in use in the IC industry.

Details of this work were presented at the S.P. I.E. Seminar on Developments in

Semiconductor Lithography V in March and

will appear in volume 221 of the

S.P. I.E. Proceedings^ [Sponsors: 2,7]

(D. Nyyssonen, J. M. Jerke, and D. B. Novotny, x3621, and Y. M. Liu, x3541)

Transistor Switching Characteristics

When a transistor which has an inductive

load at its collector terminal begins to turn off, the voltage at the collector

rises as the inductor attempts to maintain a constant current. For high voltage, fast switching transistors, the

voltage can rise rapidly, perhaps as much as 500 V in 100 ns. In roost applications, the maximum voltage rise is

limited by a voltage clamping circuit

connected to the collector. Usually,

the voltage clamp consists of a semiconductor diode in series with a voltage source (clamp voltage) aurranged in such

a manner that the bias on the diode is

equal to the difference between the collector voltage and source voltage. When

the collector voltage is lower than the

clamp voltage, the diode is reverse biased. When the collector voltage rises

slightly above the clamp voltage, the

6
OscilloscopG traces of voltage overshoot

using a clamp circuit ivith a semiconductor diode or a vacuum tube diode. The

vertical scale is 100 volts per division; the horizontal scale is 50 nano- seconds per division. The overshoot is about 100 V for the semiconductor diode,

about 50 V for the vacuum diode.

diode is forward biased, the current is

shunted from the transistor, and the

collector voltage is limited to the

cleunp voltage less the relatively small

voltage drop across the diode.

The response characteristics of the diode are such that a finite time {''60 ns)

is required for even the fastest semiconductor diodes which can handle the

power levels involved to switch from a reverse-bias condition to a forwaurd-bias

condition. Ihis results in am overshoot

of the collector voltage adxjve the claunp

voltage for a time comparable with the reverse recovery time of the diode. The

overshoot has been observed to be over

100 V for some very fast bipolau: transistors tested on the NBS secondbreakdown test circuit. Because of the

overshoot, these very fast devices appear to experience second breakdown at lower claunp voltages than they would if no overshoot occurred.

To reduce the overshoot, the semiconductor diodes in the NBS circuit were re- placed with vacuum tube diodes (6CG3)

which, because they have no charge storage, assume their conducting state much

more rapidly than the semiconductor diodes. The result has been to eliminate

overshoot in some instances and substantially reduce it in others. The accom- panying figure illustrates a worst case condition where the overshoot reduction

is 50%. Hie remaining overshoot is due

to inductance.

The vacuum diode claunp has two disadvantages. First, it has a voltage drop

('''45 V at 10 A) substantially larger

than that of the semiconductor diode

this can be corrected for in establishing and recording the clamp voltage.

Second, it introduces am increased parasitic capacitance at the collector of

the device being tested. The effect of

this increased capacitance on the

second-breakdown characteristics of the

device being tested has not been fully

determined. Therefore, the vacuum diode

claunp is only used when the voltage

overshoots are a problem; at other

times, the semiconductor diode clamp is

used. [Sponsor: 13]

(D. W. Berning, x3621

)

Process-Induced Radiation Damage

Estimates have been made of the radiation dose absorbed in critical device

dielectric layers during the application

of ion-beam lithography (IBL) to facilitate comparison of this technique with

other lithographic techniques delivering

a radiation dose to device structures

during processing. Calculations were made for a typical structure in which a silicon substrate is covered by a 0.05-)jm thick film of silicon dioxide

which is covered by a 1 . 0-ym thick film

of aluminum or polysilicon which is in

turn covered with a 1.0-ym thick film of

photoresist to be patterned by IBL. The results indicate that although 200-

keV protons at a fluence of 2 x 10^3

cm” 2 can deposit several hundred megarads* into the oxide through the alumi- num or polysilicon, the radiation absorbed dose in critical oxide layers can be essentially eliminated by carefully

*The Si unit for absorbed dose is the gray (Gy) which

IS equivalent to one joule per kilogram; 1 Gy = 100 rad.

7
matching the ion beam energy to the material configuration. In general, this means operating with a beam energy which

is as low as practicable after accounting for mask membrane penetration and

allowing for loss of resolution due to beam scattering and which is high enough

to achieve uniform exposure and minimize

lateral scattering in the resist. Uiis

ability to reduce the radiation absorbed

dose in the oxide may provide a significant advantage over electron-beam or x-ray lithography. [Sponsor: 2] (K. F. Galloway, x3625

)

Acxxjstic Emissbn Testing

In a study to evaluate the use of acoustic emission monitoring of glass-tometal seals in hybrid packages during

temperature cycling from -55® to 125®C, an acoustically quiet temperature cycling system is essential to avoid interference with the signals from the seals. A thermoelectric temperature cycling

system was investigated because it was expected that such a system would be

acoustically quiet. However, it was observed that the thermoelectric modules

themselves emitted large bursts of

acoustic emission, especially when they were cooling. A series of experiments was conducted to determine the origins of the acoustic

emission bursts. Hie results of these

experiments suggested that twinning or other crystallographic changes occurred

in the bismuth telluride elements as a result of rapid temperature changes.

In addition, several thermoelectric modules that had been cycled more than 1000

times «uid had become inefficient on the

cooling cycle were visually examined

around their bismuth telluride element

solder joints. Microcracks were observed in the solder, and surface recon- struction of the solder was evident indicating that recrystallization had

taken place. Also, some cracks were observed in the bismuth telluride elements.

As a consequence of these results, it

does not appear possible to use thermoelectric temperature cycling equipment

in electronic or other applications that

require acoustic emission monitoring.

It should be noted that most of the

thermoelectric module degradation processes, such as cracks, are considered

to result from the large range of the

temperature cycling. Thermoelectric

modules are generally used only for

cooling from room temperature, and crack

propagation emd solder reconstruction

would probably not occur in this temperature range. Twinning of the bismuth

tellviride should not degrade the perfor- mance of the cooling modules. [Spon- sors: 12,2] (G. G. Ibrman, x3621)

Work in Progress ...

Gross Leak Testi ng — Further tests were carried out to determine why the leak

rate as measured by the two-chamber mode

of the rapid cycle leak test was larger

than predicted for leak sizes in the

range from about 2 x 10“^ atm*anVs to about 4 X 10~^ atm*cm^/s. The original

model assumed leiminar viscous flow; the

model was extended to include mixed flow

through the leak channels to determine

if other flow mechanisms become significant at these relatively small gross

leak sizes. However, agreement with

experimental results was not obtained

with the mixed-flow model. Since the

measurements in question were near the

threshold capability, further studies were carried out to reevaluate the background leak rate for these test capsules. The results showed that the ear- lier reference capsule gave etnomalously

low sorption effects; data corrected to the proper background level conform to theory at the small values. [Sponsor:

2] (S. Ruthberg, x3621

)

Carbon i n Si 1 i con — it was demonstrated

that the distribution of carbon in a silicon wafer can be measured with adequate sensitivity «urid with a 1-mm spatial resolution using a Poiirier trans8
form infrared spectrometer. An x-ray

topography station is being set up to study the carbon-induced strain in the

silicon lattice. It is expected that

the spatially resolved infrared measure- ments will facilitate correlation of the

carbon density distribution with x-ray

topography data. [Sponsor: 2] (A. Baghdadi, x3625)

Analysis of C-V Profiles — a new, high

accuracy, finite-element method is being

used to calculate capacitance-voltage

curves for dopant profiles which are piecewise approximated by up to 200 ex- ponential segments. An incremental

charge approach is used to calculate the

capacitance; use of the depletion approximation is avoided. Hiis procedure

has been extended to allow profile calculation using self-consistent iteration. An initial profile deduced from

the measured C-V data (using the classical Schottky equation) is input to an exact numerical calculation of the C-V

characteristic. This characteristic is

then iteratively improved by correcting

the doping profile directly. This cor- rection procedure provides two to five

times the resolution of the uncorrected

procedure. [Sponsor: 2] (C. L. Wilson, x3625)

Unintentional Channeling During Ion Imp1 antati on — a study is nearing completion of the effects of surface oxide

layer thickness on the implantation profiles of boron implemted into (100)-

oriented silicon at 0-deg tilt. "nie through-the-oxide configuration is customeurily employed in order to randomize

the implant profile. Ibis study was mo- tivated by two trends which have recently evolved in ion implemtation for sili- con device fabrication: implemtation at 0-deg tilt to improve uniformity for

large diameter wafers, and the use of

thinner gate oxides to satisfy device

scaling rules. Boron was implanted into

(100) silicon at 0.0 + 0.1 deg through

various thicknesses of thermally grown

silicon dioxide. The implcints were performed at room temperature at 150 keV to

a fluence of 4.0 x 10^^ cm“^. The oxide

surface layers examined were 8, 34, 101,

or 140 nm thick, as determined by ellipsometry. The boron profiles were determined by secondary ion mass spectrometry. TSie boron profile for implantation

through an 8-nm oxide surface layer was only slightly degraded from that seen for accurately aligned implantations into bare ( 1 00 ) -oriented silicon, while

implantation through oxides 34 nm thick

or greater resulted in profiles similar

to those obtained from random equivalent

implantations into crystalline silicon.

Work is proceeding to evaluate existing

analytic theories on the basis of these

results. [Sponsors: 1,2]

(D. R. Myers,* x3625)

Recent Publicatbns ...

Larrabee , R. D. , and Thurber , W. R.

,

Theory and Application of a Two-Layer

Hall Technique, IEEE Trans. Electron

Devices ED-27 , 32-36 (Jeuiuary 1980).

Jerke, J. M. , Ed., Semiconductor Measurement Technology: Accurate Linewidth Measurements on IntegratedCircuit Photomasks, NBS Spec. Publ.

400-43 (February 1980).

Kenney, J. M. , Semiconductor Measurement

Technology: Modulation Measurements

for Microwave Mixers, NBS Spec. lUbl.

400-16 (February 1980).

Buehler, M. G. , The dc MOSFET Dopant

l»rofiie Method, J. Electrochem, Soc.

127 , 701-704 (March 1980).

Carver, G. P. , eind Rubin, S. , Development of Test Structures for Characterization of the Fabrication and Perfor- mance of Radiation-Hardened ChargeCoupled Device (CCD) Imagers, Annual

Report, December 1, 1978 to November

30, 1979, NBSIR 80-2000 (March 1980).

Nyyssonen, D. , Linewidth Measurement

Spotlight, Semiconductor International

3 (3), 39-56 (March 1980).

Thurber, W. R. , A Comparison of Measurement Techniques for Determining Phosphorus Concentrations in Semiconductor

Silicon, J. Electron. Mater. 9, 551-560

J. Comas, Naval Research Laboratory, and R. G. Wilson, Hughes Research Laboratories, also contrib- uted to this work. Dr. Comas' research was sup- ported in part by the Office of Naval Research.

.9
(March 1980).

*Hasegawa, S., Performance Characteristics of a Thin-Film Aluminum Oxide Hu- midity Sensor, Proa. 30th Eleatvonia

Components Conf.y San Francisco, CA,

April 28-30, 1980, pp. 386-391.

Ruthberg, S., A Rapid Cycle Method for

Gross Leak Testing with the Helium Leak

Detector, Pvoa. 30th Eleatvonia Components Conf., San Francisco, CA, April

28-30, 1980, pp. 128-134.

Publications in Press . .

Albers, J. H. , amd Novotny, D. B., In- tensity Dependence of Photochemical Reaction Rates for Photoresists, J. Eleatvoahem. Soa. Buehler, M. G. , Hie Use of Electrical

Test Structure Arrays for Integrated

Circuit Process Evaluation, J. Eleatvoahem. Soa.

Bullis, w. M. , Semiaonduatov Measurement

Teahnology: Metrology for Submicrometer Devices and Circuits, NBS Spec.

Publ. 400-61.

Bullis, W. M. , Semiconductor Measurement

Technology, Progress Report, April 1 to

September 30, 1977, NBS Spec. Publ.

400-45.

Bullis, W. M. , and Scace, R. I., Hie NBS

Semiconductor Technology Program and

VLSI, NBSIR 80-2057.

Carver, G. P. , Linholm, L. W. , and Russell, T. J., Hie Use of Microelectronic

Test Structures to Characterize IC Materials, Processes, and Processing

Equipment, Solid State Teahnology.

*Duffy, M. T., Zanzucchi, P. J. , Ham, W. E., Corboy, J. F. , and Cullen, G. W.

,

Semiaonduatov Measurement Teahnology:

Method to Determine the Quality of Sapphire, NBS Spec. Publ. 400-62.

Ehrstein, J. R. , Spreading Resistance

Calibration for Gallium- or AluminumDoped Silicon, J. Eleatvoahem. Soa. Ehrstein, J. R. , Some Considerations Re- garding Film Thickness Standards for

the Semiconductor Industry, Pvoa. Miavoeleatvonia Measurement Teahnology

Seminar

San Jose, CA, March 12-13,

1980.

•Reports of contract research.

Harman, G. G. , The Use of Acoustic

Emission to Determine the Integrity of

Large Hybrid Packages, NBSIR 80-2055.

*Kasden, H. L. , Linewidth Measurement by

Diffraction Pattern Analysis, NBS-GCR79-175.

Lankford, W. F. , and Schafft, H. A.,

Drafting Test Methods for Photovoltaic

Systems, NBSIR 80-2060.

Larrabee, R. D. , and Blackburn, D. L.

,

Theory and Application of a Nondestructive Photovoltaic Technique for the

Measurement of Resistivity Variations

in Circular Semiconductor Slices,

Solid-State Eleatronias.

*Lehovec, K. , auid Fedotowsky, A., Scanning Light Spot Analysis of Faulty

Solar Cells, Solid-State Eleatronias.

Lowney, J. R. , and Larrabee, R. D. , Hie

Use of Fick's Law in Process Modeling,

IEEE Trans. Eleatron Deviaes.

Myers, D. R. , Semiaonduatov Measurement

Teahnology: Technical Impediments to More Effective Utilization of Neutron

Transmutation Doped Silicon for High

Power Device Application, NBS Spec.

Publ. 400-60.

Myers, D. R. , Wilson, R. G. , and Comas,

J., Considerations of Ion Channeling

for Semiconductor Microstructure Fabrication, J. Vac. Sai. Teah.

Myers, D. R. , Koyama, R. Y. , eind Phillips, W. E., An Implantation Predeposition Technique for Deep Level Characterization, Radiat. Eff.

Myers, D. R. , eind Wilson, R. G. , Alignment Effects on Implantation Profiles

in Silicon, Radiat. Eff.

Myers, D. R. , Roitman, P. , Mayo, S. , and

Horowitz, D. , Electronic Properties of

Ion-Implanted Silicon Annealed with

Microsecond Dye-Laser Pulses, Proa. Mater. Res. Soa. Symp. on Laser and

Eleatron Beam Proaessing of Mater.,

Cambridge, Massachusetts, November

26-30, 1979.

Oettinger, F. F. , and Larrabee, R. D.

,

Measurement Techniques for High Power

Semiconductor Materials and Devices:

Annual Report, October 1, 1978 to September 30, 1979, NBSIR 80-2061.

Novotny, D. B. , Experimental Photoresist

Sensitometry and Exposure Modeling,

(Continued on Back Cover)

10
NBS*114A tREV. 0>76)

U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO.

NBSIR 80-2006-2

2.Gov*t Acs«Mion No. 4. Acce$S^ort No.

4. TITLE AND SUBTITLE

Semiconductor Technology Program - Progress Briefs

5. Publication Date June 1980

AiioniNiaOisanizaSoa Codt

7. AUTHOR! S) W. Murray Bullis, Editor8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS DEPARTMENT OF COMMERCE

WASHINGTON, DC 20234

ia>P(oJoct/TaSi/Work (kitt No.

11. Contract/Grant No. See item 15.

12. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS rsir.er, ciiy. Si.r«. ZIP)

ARPA, Arlington. VA 22209| NBS. Washington. DC 20234: Oopt. of Energy. Washington. DC

20S45| ONA. Washington. DC 2030Si C. S. Draper Laboratory. Caabrldoe. HA 02139; NAVAIR, Arlington. VA 28369; APAL, Wrlght-Patterson APB, OH 4S433; NWSC, Crane, IN 47622; SERI, Golden. CO 80401; NAC. Indianapolis. IN 46218; NASA-Lewls Research Center, Cleveland. OH

4413S; ONR. Arlington, VA 22217; NOSC, San Diego, CA 921S2.

13. Type of Report & Period Covered Interim

January to March 1980

M. Smaortni AaMcy Code

15. SUPPLEMENTARY NOTES

AAPA Orders 2397 snd 3832; D«pc. of Energy. Interagency Agreement EA-77-A0 1-60 1i), T. 0. A021-

BE5 and T. O. AOS4-SBi DHh lACRO 80-826i C. S. Draper Laboratory. P. 0. DL-H-163208 (Navy contract N 00030-78-C-0100); NAVAIR, N0019-70-1P-'39003i APWAL, HIPR PY1 I7S80N3 tOSr NWSC, P. O. N0006480NR30027| NAC. P. O. NOO 16 380HPOO0 1 ; SEKl, EG-77-C01-40421 NASA-Lawla. C-32810-O| ONR. NOOOl 4-79-f-OOS 1 ) HOSC. MIPRs N6600 179HP000S2 and N6600 180HP00017.

15. ABSTRACT (A 200>tvord or /eaa (actual autnmary of moat s( 4hi/fcanr information, tt document includea a aignUicant bibliography or

literature auraey, mention it here.)

This report provides information on the current status of NBS work on measurement technology for semiconductor materials, process control, and devices. Results of both

in-house and contract research are covered. Highlighted activities include: studies

of MOSFET dc profiler, heavy doping effects in silicon, IVW applications, ioniiqplanted dopant profiles, optical linewidth measurements on wafers, process-induced

radiation damage, transistor switching characteristics, and acoustic emission testing.

Brief descriptions of selected on-going projects are included, and recent publications

and publications in press are listed. The report is not meant to be exhaustive; contacts for obtaining further information are listed.

17. KEY WORDS (aix to twelve entriea; alphabetical order; capitalize only the drat letter of the firat key word unteaa a proper name;

aeparated by aemicolona) Electronics; integrated circuits; measurement technology; microelectronics; semiconductor devices; semiconductor materials; semiconductor process control; silicon.

18. AVAILABILITY Unlimited 19. SECURITY CLASS 21. NO. OF

(THIS REPORT) PRINTED PAGES

1 1 For Official Distribution. Do Hot Release to NTIS UNCLASSIFIED 11 nOrder From Sup. of Doc., U.S. Government Printing Office, Washington, DC

20402, SD Stock No. SN003.003-

20. SECURITY CLASS

(THIS PAGE)

22. Price

[3T1 Order From National Technical Information Service (NTIS), Springfield, VA. 22161 UNCLASSIFIED $5.00

11

USCOMM-DC
(Continuei from Page 10) Proc. Soc. Photo-Optical Instfum.

Engrs, 221 , Developments in Semiconductor Microlithography V. Nyyssonen, D. , Calibration of Optical

Systems for Linewidth Measurements on Wafers, Proc. Soc. Photo-Optical Instrum. Engrs. 221 , Developments in

Semiconductor Microlithography V. *Quate, C. F. , Innovative Measurement

Technology for the Semiconductor Device

Industry — "The Acoustic Microscope - A New Instrument for Viewing Integrated

Circuits," NBS-GCR-80-204.

Sawyer, D. E., and Kessler, H. K. , Laser Scanning of Solar Cells for the Display

of Cell Operating Characteristics and

Detection of Cell Defects, IEEE Trans. Electron Devices.

Sawyer, D. E. , Kessler, H. K. , and

Schafft, H. A., Measurement Techniques

for Solar Cells, Annual Report:

September 15, 1977 to December 14,

1978, NBSIR 80-2027.

Scace, R. I., ASTM Standard Test Methods

for the Semiconductor Industry, Proc. 1980 Tech. Symp. SEMICON/EUROPA,

March 13, 1980. Thurber, W. R. , Mattis, R. L. , Liu, Y. M., and Filliben, J. J. , ResistivityDopant Density Relationship for

Phosphorus-Doped Silicon, J. Electrochem. Soc

*Wilson, R. G. , and Comas, J. , Correlation of Atomic Distribution and Implantation Induced Damage Profiles in Be Ion-Implanted Silicon, Radiat. Eff.

*Wilson, R. G. , and Comas, J., Atomic and

Carrier Depth Distributions of Beryllium Implanted in Silicon and Their

Thermal Redistribution, J. Vac. Sci.

Tech.

*Wilson, R. G. , and Comas, J., Channeling

and Random Equivalent Depth Distributions of 150-keV 3Li, 4 Be, and ^sB Im- planted into <100> and <110> Silicon,

J. Appl. Phys.

"Wilson, R. G. , and Weglein, R. D.

Acoustic Material Signatures Using the

Reflection Acoustic Microscope, Proc. 1st Intemat. Symp. Ultrasonics Mater. Characterization, Washington, DC, June

8-10, 1978.

•Reports of contract research.

U.S. DEPARTMENT OF COMMERCE. Philip M. Klutznick. Secretary

Luther H. Hodges, Jr., Deputy Secretary

Jordan J. Baruch. Assistant Secretary for Productivity, Technology, and Innovation

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director