NBSIR 74-577-2

Remittance Processing System,

Volume II (Reference Volume I)

Philip D. Shupe, Jr. Paul Meissner

James R. Park

Computer Systems Engineering Division

Institute for Computer Sciences and Technology

National Bureau of Standards

Washington, D. C. 20234

September 1974

Interagency Report

Prepared for Internal Revenue Service

Systems Development Division

Washington, D. C. 20224

UU) !.:oo»:ArHic

Si I r E T

i. i 'Im' l.i' !! '\ w NBSIR 74 -577-2 No.

Mi.i A- o >i him.!:

i^i::;]'i:TANC}: ruocESSiKG SYsrrM

7. Ai.iii(m(S) p|.,j,2^ip shupc, Jr; Paul Heissner; James R. Park

vTT'i'Ki OKMINv. ()K(.AM/A"1 ION' .\AM! AM ' AIM)!; i;:v> NATIONAL fJUREAU Of- STAHDARDS

DEPARTMrNT OF COM'.'.E'RCE WASHirx'GTON, D.C. 20254

1 2. S(><'i>.-:oriii;; O.'xuniz.i; ion N'.imc and (.oi.;plf U AdJicss (Slrci l, City, Sui<u, ZIP)

Internal Revenue Service

SysLeviis Development: Division

1111 C'cnstituticn Avenue, N. W.

War-hin<-ton . D. C. 2017 h

l>. 1 'iil>i t( ,11 ioli I J.U-- September 17, 197A

650.01

NBSIR 74-577-2 ! 6504567 i

.tiriir.ici Cif .lilt .Vo. IRS Cont. 'l?.~h^>'},.

7.3-558. and 74-1013

13. I ypc of Kcpor! I'lrioC

( -OV CTfd Interagency Report

14. Sponsoiiiu; .^:••..ncy C.oi IRS

16. .'\i'S'ri<. A(" r (A 200-i'.or:l or le^s foctit.il .s.-ji.^i.'iry ol Lioat i^i f^fii lic<ir.: itifoni:<ilion. If Jocdnjcnf mdiidcs' a .'. i^njt/c.^nf

l)ih! ii.i(\r.q!iy or litcrntoro survey, m<:tlion it lirrn.) The Roi.Tj' I tance Processing System is a prototype developed for the InLernal Revc-iiue

Service to test a new concept in automatinj' tiie procesi.ing of taxpayer rensittance.s

Central to the new processing concept was Lhij integr.jtioa of the Direct Data Entry

System. Initial Eiitry Station with equipment co,;iponerii;s that v;ouId eliii'inatc a luimbar of individual inaivjal operation-^ ^ per;i;it operator interface with, the central

ODES con!]-»uLer, and ])rovide for verification of initial entry, cheek endorsement, audit

trail data, renitrance docurunitation , and affixing inf orraa tion to taxpayer doc»3r.:on Latio:":

accoippanying the reiaittance. This report describes the equlpiiient vJiich was configured

to implciuent these processes and to demonstrate the viability of the concept.

17. KI-.^' V.OI(l)>i (^ix to tivi lv entries; olfhabK'liC:)! ordvt. capitalize only tlic /.r.sf Ic'.Icr of the first key noni unltsbi .7 proper \ noinr': scp^irati.d by SL inic olori.s ) Audit traij ; check endorsenent; check liandling; datci entry; document laijeling; labe.Lii-,g;

listing; man machine interface; MICR printing; re.raittance processing; remittance regisLe

L.J '"f Official Disiribui ion. Do Noi i^clcasc to KiiS

[ ! OfJi. r From Sup. of O.-r.., t'.S. (io\ i ninu-iit I'riniim^ Oflico

V.a-:liini-,ton, D.C. 20,02, Sl \( i- . \... ( 1

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NBSIR

REMITTANCE PROCESSING SYSTEM,

VOLUME II (Reference Volume I)

Philip D. Shupe, Jr. Paul Meissner

James R. Park

Computer Systems Engineering Division

Institute for Computer Sciences and Technology

National Bureau of Standards

Washington, D. C. 20234

September 1974

interagency Report

Prepared for

Internal Revenue Service

Systems Development Division

Washington, D. C. 20224

1 .

U. S. DEPARTMENT OF COMMERCE. Frederick B. Dent, Secretary

NATIONAL BUREAU OF STANDARDS, Richard W. Roberts. Director
Remittance Processing System

Volume II

(Reference Volume I)

This volume contains the drawings for the Remittance

Processing System described in Volume I.
RPS Drawing List

2.0 Remittance Processing System Controller (RPSC)

3.0 Remittance Processing Device (RPD)

4.0 S102/S103 Modifications

5.0 Teletype Modifications

6.0 Control Panel and Display

7.0 RPD Console

8.0 Labeler

9.0 Test Equipment

NOTE: In several instances precise identification of a product (s).

has been made because the product is a part of an assembly cr device

and is a part whose physical dimensions or technical characteristics

must, in the even of injury or failure, be duplicated exactly in a successful replacement part. In no case does such identification

imply recommendation or endorsement by the National Bureau of Standards,

nor does it im.ply that the material or equipment identified is

necessarily the best available for the purpose.

1
2.0 RPSC

2.1 Transparency

2.1.1 Priority, T SET, Carr. Det, DTR

2.1.2 CTS, DSR

2.1.3 RTS, RSET

2.1.4 Transmit Data

2.1.5 Receive Data

2.1.6 Local Clock

2.1.7 Output Circuits for the OCX Data Link

2.1.8 LED Indicators

2.1.9 Noise Decoupler

2.1.10 Power-Monitor for Switching T-BAR Relay

2.1.11 Wire Chart for T-BAR Bridging Relay

2.2 Data Flow

2.2.1 Shift Register

2.2.2 Longitudinal Parity Register

2.2.3.1 Character Generator, MU, MN

2.2.3.2 Character Generator Gating

2.2.3.3 Character Generator Codes

2.2.4 Address Register

2.2.4.1 Control Signals to Annex Sheet 1 of 2

2.2.4.2 Control Signals to Annex Sheet 2 of 2

2.2.5.0 Address Register Select "0"

2.2.5.1 Address Register Select "1"

2.2.5.2 Address Register Select "2"

2.2.5.3 Address Register Select "3"

2
2. 2. 5. A Address Register Select

2.2.5.5 Address Register Select

2.2.5.6 Addpess Register Select

2.2.5.7 Address Register Select

2.2.6.0 Output Drive for Select "0"

oZ

9 A 1 wu tpu

Dr ive M-i II X

2. 2.6.2 Output Drive for Select "2"

2. 2.6.3 Output Drive for Select ii^ii

2. 2.6.4 Output Drive for Select "4..

2. 2.6.5 Output Drive for Select 11511

2. 2.6.6 Output Drive for Select "6"

2. 2.6.7 Output Drive for Select 1,711

No Address, SBZ

'4"

,5.1

•6"

'7"

2.2.8 RPSC Master Reset

2.3 Control Circuits

2.3.1 Advance Phase Counter

2.3.2 Abort; FIN; Ld Brf.l; GXM Inh; XSel

2.3.3 Phase Counter2.3.4 Reset Phase Counter

2.3.5 Character Clock Generator

2.3.6 ETXD; PE

2.3.7 CLl; CL2; LP Str. ; XChCi ; 4CF

2.4 Reply

2.4.1 Data Out Gating

2.4.2 ROM Bit Counter

2.4.3 Priority Transmit

2.4.4.1 Output Buffers

2.4.4.2 Output Buffer Control

3
2.4.5 Station Priority

2.4.5.0 Station Priority AKL

2.4.5,1 Station Priority AKL 1

2.4.5.2 Station Priority AKL 2

2.4.5.3 Station Priority AKL 3

2.4.5.4 Station Priority AKL 4

2.4.5.5 Station Priority AKL 5

2.4.5.6 Station Priority AKL 6

2.h.5.1 Station Priority AKL 7

2.4.6 Address Switch Gating

2.4.7 Control Signals

2.4.8 Control Signals from Annex

2.5 RPAN (RPSC ANNEX)

2.5.1 LGS, LAI, LA(f)

2.5.2 X8, X9, XIO, Xll, PCI, PCc]), LOSW

2 . 5 . 3 AK8

2.5.4 AK9

2.5.5 AKIO

2.5.6 AKll

2.5.7 LSWcf)

2.5.8 LSW 1

2.5.9 LSW 2

2.5.10 LSW 3

2.5.11 LSW 4

4
2.5.12 LDTA

2.5.13 SEL 8

2.5.14 SEL 9

2.5.15 SEL 10

2.5.16 SEL 11

2.5.17 CAcf), CAl, CA2, CA3 , CA4 , ANEN, MRST

2.5.18 CIK, DT, CLl, CL2, XCHCL, P3

2.5.19 8 Outputs

2.5.20 9 Outputs

2.5.21 10 Outputs

2.5.22 11 Outputs

2.5.23 LOIGN, LOBZ

2.5.24 SW 8

2.5.25 HDRE

2.5.26 SW 9

2.5.27 SW 10

2.5.28 HDRE

2.5.29 SW 11

2.6.1 Integrated Circuit Layout RPS Controller

2.6.2 Integrated Circuit List RPS Controller

3.0 RPD

3.1 Common Control

3.1.1 BZ, ACK, MSGEN
3.1.2 CLRM, CLRMCi

3.1.3 ABORT RAAC, LGT, CCF

3.1.4 Longitudinal Parity

3.1.5 Shift Register

3.1.6 Ld Mcr, Ld AT, Ld Doc, Ld TTy

3.1.7 Lateral Parity

3.1.8 OK Pr.

3.1.9 Timing Pulses

3.1.10 Mn (j) ^ Mn 7; M; cj) ^ M; 15

3.1.11 +; V; ?; ETX, CCer

3.1.12 SLd, SLd C , GSD

3.2 TTY LISTER CONTROL

3.2.1 THRL (TTY Control)

3.2.2 TA(J) ^ TA7 Address Counter

3.2.3.0 TM«^

3.2.3.1 TM 1

3.2.3.2 TM 2

3.2.3.3 TM 3

3.2.3.4 TM 4

3.2.3.5 TM 5

' V

3.2.3.6 TM 6

3.2.4 Teletype Data

3.2.5 Teletype OK

3.2.6 FFF

3.2.7 TETX

6
3.2.8 TD TD 6

3.2.9 TTy 1 (Ribbon Motion)

3.2.10 FF, TAB TTY 2 -> TTy 4

3.3.1 ATEN; ATP

y

3.3.2 AT

3.3.3 ATDT (Memory)

3.3.4 Address Counter AA cj) AA6

3.3.5 F Sew; AA7 n

3.3.6 ATOK

3.4.1 DcEn; Dc Pr

3.4.2 DcC^

3.4.3 Dc Dt (Memory)

3.4.4 Shift register DDcf), DDI, DD2, DD3, Print Command

3.4.5 Address Register

3.4.6 Data 2° ^ 2^

3.4.7 Dc OK, DERR

3.5.1 MCREN, MCR PR

3.5.2 MCR C\

3.5.3 Address Counter MA(t)-MA6

3.5.4 MDt (Memory)

3.5.5.1 GMDP, S, 1, 2, 4, 8, 16

3.5.5.2 KBS 1, 2, 4, 8, 16

3.5.6 MCR OK

3.5.7 BFIN; McR2-; MCR5

3.5.8 EOES; DEDS

3.5.9 I BRPR-; lAM

7
3.5.10 II lAT; NATPR; GAT

3.5.11 III NFAT; RMAC; LDBR; LPMCR

3.5.12 IV RPT PL; CLRBR; RPBR

3.5.13 V MAN

3.5.14 VI MSTRS3.5.15 V FATF

3.6.1 Integrated Circuit Layout KPD

8
Section V

Modifications of the Model 37

Teletype for the RPD

List of Drawings

5.1 AC Power Circuits

TTY Dwg. No. 1022 SD-Bl

5.2 DC Power Supply Circuits

TTY Dwg. No. 1022 SD-B2

5.3 Selector Magnet Driver

TTY Dwg. No. 1022 SD-B4

5.4 Alarm Circiaits

TTY Dwg. No. 1022 SD-B5

5.5 End of Line and Low Paper Alarm Modified

Stunt Box, Modified Ribbon Shift

9
6.0 Manual Control and Error Display

6.1.1 Proceed. Reoeat . Cancel All—

6.1.2 Buzz, "Go"

6.1.3 Check MICR 813

6 14

6 1 5 IjWWy vJCLlliy OL^JLJ

6 1 7

6 18 X1/2/ ^ PPS X XT O

6.2.1 TTYPR- X J. X X XV y RPTTT- XvX XXX y fANTT- iiJ-l X X

6.3.1 PROAT-* RPAT-' CANAT ^

X xw/riX } x\x-n.x ^ v>ruiri.x

6.3.2 atT

6.3.3 ATPO. AT7

6.4.1 RPT Dr • Dor En • Cancel Dr • T.ah

6.4.2 \X.'X. dW J-JLlg \_>CLJ.l ^ CJ-.X C-U /

6 4 3 DPT • Dr 0w' Dr 1 Tin? Tin Tin it

6.5.1 MCM; PRMCR-; RPTMC-; CANMC6.5.2 MCRl

6.5.3 MCR3

6.5.4 MCR4

Section VII

The RPD Operator's Console

List of Drawings

7.0.1 RPS Floor Plan

7.0.2 General Arrangement of Console Equipment

7.1.1 Table Top

7.1.2 Catch-pan

10
7.1.3 Table Top Center Support

7.1.4 Modified Endorser Table Top Sh. 1

7.1.5 Modified Enclosure Table Top Sh. 2

7.1.6 Track Cover, Right

7.1.7 Track Cover, Left

7.1.8 Not Used

7.1.9 Keyboard Pan

7.1.10 Accessory Drawer

7.1.11 Power Control Panel

7.1.12 Power Control Box

7.1.13 Running Time Meter Mount

7.1.14 Rear Frame Unit

7.1.15 End Frame Unit

7.1.16 Table Leg Extenders «

7.1.17 Endorser Modification

7.1.18 Transformer Rail

7.1.19 Support Spacer for Transformer Rail

7.1.20 Drop Leaf Support Angle

7.1.21 Spacer Block for Drop Leaf Mounting

7.1.22 Panel Drilling Pattern for Drop Leaf Mounting

7.1.23 Paper Catcher Mount

7.1.24 Paper Bin Switch Moimting Bracket

7.1.25 Terminal Guard for Isolation Tranformer

7.1.26 Legs for Display Unit

7.1.27 Transformer Mounting Plate

11
8.0 RPD Document Labeling Device

8.1 Timing Diagrams

8.1.1 Timing Diagram for the Labeling Logic Sequences, Sheet 1

8.1.2 Timing Diagram for the Labeling Logic Sequence, Sheet 2

8.2 Logic Diagrams

8.2.1 RUN, GDE

8.2.2 LWR, RZE, SMR

8.2.3 SMD, BRK, DPT, DTFF

8.2.4 DCPOS, STMP

8.2.5 FWD, STEPF, STEPB, STEP SPCH

8.2.6 SYNFF, ADCN, STROBE

8.2.7 COUNTER

8.2.8 HLTR, HLTF

8.2.9 DATA PATH

8.2.10 SHER

8.2.11 VAC , NOVO

8.2.12 LBFN, DCFIN

8.2.13 DCLMP

8.2.14 STPCL /: • v/^i.'.

8.2.15 POWER, PAPOT

8.2.16 HDRE

8.2.17 HRDF

8.2.18 HDRG

8.2.19 Chip Layout

Wiring Schematic

12
8.3.1 Wiring Schematic for the RPD Document Labeler

8.4 Mechanical Drawings for the RPD Docianent Labeler

8.4.1 Main Mounting Plate

8.4.2 Labeler Hanger Angle

8.4.3 Shelf Mounting Angle

8.4.4 Support Foot

8.4.5 Guide Plate

8.4.6 Guide Plate Assembly

8.4.7 Deflector Plate

8.4.8 Deflector Counterweight Assembly

8.4.9 Deflector Plate Weight

8.4.10 Deflector Hanger — RH

8.4.11 Deflector Hanger — LH

8.4.12 Entry Guide Plate

8.4.13 Belt Support Plate

8.4.14 Belt Pulley, Driving

8.4.15 Belt Pulley, Idler

8.4.16 Driving Pulley Shaft and C Ring

8.4.17 Idler Pulley Shaft

8.4.18 Pulley Bearing Support

8.4.19 Belt Drive Motor Pulley

8.4.20 Superseded by 8.4.70

8.4.21 Motor Capacitor Mounting Strap

8.4.22 Dociment Stop Block — LH

1
8.4.23 Document Stop Block - RH

8.4.24 Stop Block Plate

8.4.25 Sensor Shoe Support - LH

8.4.26 Sensor Shoe Support - RH

8.4.27 Sensor Shoe - LH

8.4.28 Sensor Shoe - RH

8.4.29 Document Stop Assembly

8.4.30 Document Stop Plate

8.4.31 Lamp Holding Clamp

8.4.32 Not Assigned

8.4.33 Reel Flange Knob

8.4.34 Outer Reel Flange

8.4.35 Reel Hub

8.4.36 Inner Reel Flange

8.4.37 Reel Base

8.4.38 Reel Shaft

8.4.39 Reel Assembly

8.4.40 Reel Damper Assembly

8.4.41 Carrier Bearing Mount

8.4.42 Carrier Arm Shaft

8.4.43 Label Carrier Arm

8.4.44 Carrier Gasket

8.4.45 Vacumn Connector

8.4.46 Vacuumn Hold-Down Plate

8.4.47 Protective Bushing

14
8.4.48 Carrier Bell Crank

8.4.49 Actuator Connecting Rod Shaft

8.4.50 Actuator Connecting Rod

8.4.51 Actuator Bell Crank

8.4.52 Actuator Cam

8.4.53 Cam Switch Mounting Plate

8.4.54 Mounting Plate Spacer

8.4.55 Actuator Motor Mounting Spacer

8.4.56 Stamp Platen

8.4.57 Platen Drive Yoke

8.4.58 Platen and Shear Return Spring

8.4.59 Stamp Solenoid Yoke Guide

8.4.60 Solenoid Mounting Block

8.4.61 Stamp Assembly

8.4.62 Label Shear Motinting Bracket

8.4.63 Shear Solenoid Support

8.4.64 Shear Yoke Guide

8.4.65 Label Shear Yoke

8.4.66 Shear Solenoid Plunger Stop

8.4.67 Blade Support Block

8.4.68 Blade Clamp

8.4.69 Label Shear Assembly

8.4.70 Superseded by 8.4.71

8.4.71 Belt Drive Motor Mount

15
REMITTANCE PROCESSING SYSTEM CONTROLLER (RPSC)

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RPSC

TRANSPARENCY

LED INDICATORS

6-12-73 2.1.8
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RPSC

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TRANSPARENCY

NOISE DECOUPLER

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RPSC T-BAR Bridging Relay Wire Chart

From To From To

DECK FIN FLUG & PIN DECK PIN PLUG & PIN

1 1 fU-c 1 9 Fk-e

2 1 Pl-17 2 9 F2-h

3 1 pU-a 3 9 Fh-c

1 2 fU-f 1 10 P^-j

2 2 Pl-U 2 10 P2-5,6

3 2 Fh-D 3 10 Fh-f

1 3 Fh-K 1 11 Fh-m

2 3 PI5

2 11 P2-20

3 3 fU-h 3 11 PU-k

1 k f4-n 1 12 Pii-r

2 h Pl-20 2 12 P2-15

3 k Fh-L 3 12 PU-n

1 5 fU-s 1.4 1 Fh-n

2 5 Pl-15 5 1 F2-3

3 5 Pi+-F 6 1 Fh-s

1 6 pU-v 4 2 PU-x

2 6 Fl-3 5 2 P2-2

3 6 Fh-T

/

D 2 Fh-v

1 T Fh-Y ll 3 Pii-AA

2 7 Fl-2 5 3 Fh-z

3 7 fU-w 6 3 F-hy .

1 8 PU-b

2 8 P2-1T

3 8 Pi|-Z

Note: (l) See Figure 3.1 Section II for connector location.

(2) T-BAR relay deck 1 is the top deck of relay as mounted. Deck

6 is the bottom deck. Fin numbers are read counter clockwise

starting vith 1 on lover right hand corner of deck.

T-BAR RELAY

2. 1. II 28

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4/13/72 2.2.3.2
CHARACTER GENERATOR COOES

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SOH 0 0 0 0 0 0 1 0 1 STX 0 0 0 0 0 1 0 0 2

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DEL 1 1 1 1 1 1 1 7 15

CF 0 1 0 0 0 0 1 2 1

33

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DATA FLOW

CHARACTER GENERATOR CODES

1/12/72 2.2.3.3

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0 IGN

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2 I6N

3 IGN

4 IGN

5 IGN

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7 IGN

FROM NI8-6 '

See RPSC Annex Mod. Dwg.

0 BZ

I BZ

2 BZ

3 BZ

4 BZ

5 BZ

6 BZ

7 BZ

SBZ

FROM NI8-8 ' See RPSC Annex Mod. Dwg.

NO ADDRESS, SBZ

RPSC

DATA FLOW

10/15/73 2.2.7

5 3
+ 5V

hSv

2.4.7. 2

M 16 - 10

MASTER RESET

EI5-1

HEADER

""k SM I0,II,I2~|

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RPSC

DATA FLOW

MASTER RESET

8/7/72 2.2.8

54
5 5
56

58



Bit Count

2Bf .0

2Bf.2

Bit0,Sw

from

2.4.2 ^

Bit2,Sw

Bit4,Sw

Bit7,Sw

AIO

Bit 0,ROM

Bit 7,R0M

Sel ROM

62

RPSC

REPLY

DATA OUT GATING

4-11-72 24

RPSC

REPLY

Priority Xmit

2-8-72 2.4.3
OQ 00 CD CD

OJ <M CSlOJ

^ in to »—»«—»-

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Bt3,Sw

Bt2,Sw

Bt I ,Sw

Bt0,Sw

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2.4.5 [h9-8] LOSW

NPIO-11-12

2.4.5

11

C11

11

2.4.2 8

PC1-

PC0-

2.4.5 [PI4-I5] EO

BC2

BC1

BC0

to annex

10

II

_13

1

12

13

12

13

K- 17-11

77

LOSW+

LOSWANC1

ANC1 -

ANC0

-(T) ANC0-

{w) HIEOt

(x^ HIEO-

-(7) BC2 +

<D

BC2-

BC1 +

BC1-

BC0 +

BC0-

RPSC

REPLY

Control Signals To Annex

2.4.7
LDTALDTA +

LGSLGS +

from annex

0

&

LOIGNLOIGN+ (EE

LOBZ

LOBZ +

- &

1/2 8820

13

LA - ©—

H

LAI + ©

i

LA0 - ©—

LA0 + ©

i

13

8

1/2 7420

/

13 MI3

MI3

MI3

7402

1

1

A22

> [2.4.5]

?

[2.2.7]

78

RPSG

REPLY

Control Signals

From Annex

2.4.8
AK8-

AK9

AKIOAKIl9318

4

3

2

1 4

1.17

1

13

10 6

12

1

7

10

5

9

2.9

LGS, LAI , LA0

RPAN

7 9

No. I Date 4/23/73

2 5 I
Jl-Z ANCI - (3

ANCI

Jl-AANC0

PC I

XII8250

Jl-DLOSW-O"

Jl-C

UOSWV

80

LOSW

X8,X9,XI0, XII PC0, PCI, LOSW

No. 2

Date

RPAN

4/23/73

2.5 2
81

83
84
PC I

SW9-0

LSW 0

85

LSW ^

No.

Dote

R PAN

4/20/ 73

2.5.7
PC I

SW8> I SW9'I

SWI0- I

8230

i! 12

10

1.8

13

14 LSW I

10

86

LS

RPAN

No.

8

Dote

4/20/ 73

2 5 8
8230

SW8-2

SW9-2

SWI0-2

SWII-2

PC

II 12

10

1.9

13

14 LSW 2

10

87

LSW 2

R PAN

No.

9

Dote

4/20/73

2.5.9
PC I

PC^

8230

SW8- 3

SW9- 3

SWI^-3

SWIl-3

1 1 12

10

1.10

13

14 LSW 3

10

88

LSW 3

No. 10

Dote

R PAN

4/20/ 73

2.5.10
PC

8230

SW8-4

SW9-4

SWII- 4

LSW4

89

LSW 4

No. 1

Dott

R PAN

4/20/73

2.5.11
LSW0

LSWI = LSW2

LSW 3

LSW 4

PR I

8230

I2

3

4

5

6

7

9

BC0

2.19

BCI 2.21

12

13

1.12

BC2

Jl-H- O BCI +

VJ BC2-

^

Jl-K-

\J BC2 +

15

14

+ 5v \J LDTALOSW

LSW0

LSW I LSW 2

LSVV 3

LSW 4

PR I

12

3

4

15 9

5 2.22

10

1

1

12

13

8

T

90

^8262

LDTA

No. 12

Ddte

RPAN

4/23/73

2.5,12
z<

Q.q:

12 o <o

00

_JUJ

to

toz o
92
93
94
ACA0 + [jl-S-]

ACAI - [jl-V-]

ACAI + [jl-U-j

ACA2 - [^Jl-X-]

ACA2 + [jl-W-]

ACA3 - [jl-Z-j

ACA3 + [Jl-Y-]

ACA4 - [Jl- BB]

ACA4 + [^JI-Aa]

ENCMP - [jI-DD]

ENCMP + [jl- CC]

RST - [JI-R-1

RST + [JI-P-]

1/6 3.15

7404

CA0-

CAI -

CA2

CA3 -

CA4-

AN EN -

MRSTANEN.MRST

CAO, -I, -2,-3,-4

RPAN

95 No. I 7

Dote _4^23£73

2 5 17
CLK- [Jl-L] O

CLK+ [J'~*^J O

DT- [Jl-B] O

DT+ [J I -A] Q

CLI- [Jl-F] O

CLI +

CLK I

CLK 2

1/2 3,17

8820

1/6 3.18

7404

1/2 3.19

r 1 r\ K.8820 CL2- [Jl-J] CJ

CL2+ [Jl-H]

CHCL-[J|-N] O

CHCL+ [Jl-M] O

P3- [Jl-D] O i3

P3+ [Jl-C] Q

DT

DT2

CLI A

CLI B

CL2 A

CL2B

XCHCLI

1/6 3

7404

24 >0 X CHCL2

P3- I

P3- 2

96

XCHCL, P3

CLKI. DT. CLI,CL2

R PAN

No. 18 Date

4/23/73

2 5 18

IQ.o

I 0>

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<

a.

(r

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98
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99
CL

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1-o

100
8I6N9IGNlOIGNIII6N8BZ9BZ10 BZIIBZ13

i/2

7420 ^ '^

1/2

7420 4.18

LOIGN +

JI-EE

LOIGN -

1/2

8830 4.19

LOBZ - Q Jl -JJ

+ 5 V

LOIGN, LOBZ

101

RPAN

No. 23

Dote 4/23/73

2.5. Z3
HDRS

SW8- I SW8-0

SW8

RPAN

102

No. 24

Date 4/23/73

2.5.24
HDRE

o

1 14

2 13

3

3. 2

12

4 10 II

5 10

6 9

7 8

SW9-4

SW9-3

SW9-2

SW9- I SW9-0

103

HDRE

RPAN

No. 25

Date 4/23/73

2,5.25
SW9 -4

SW9- 3

SW9-2

SW9-I

SW9- 0

HDRS X

1 14

2 1 3

3.3

3 12

4 10 II

5 10

6 9

7 8

104

SW9

RPAN

No. 26

Date 4/23/73

2.5.26
HDRSn\

1 14

SWIO- 4 2 13

3.-4

SWIO- 3 3 12

SWIO- 2 4 10 II SWI^- 1 5 10

SWI0-0 6 9

7 8

105

SWIO

RPAN

No. 27

Date 4/23/73

2.5.27
HDRE

+ 5V

Q

SWI0- 4

SWI0-3

SWI0-2

SWI0- I

SWI0- ^

1 14

2 13

3 3. 5 12

4 10 1

1

5 10

6 9

7 8

SWII- 4

SWII- 3

SWII- 2

SWII- I

SWII- 0

106

HDRE

R PA N

No.28

Date 4/23/73

2.5.28
HDRS

1 14

2 13

3 3.6 '2

^ 10

5 10

6 9

7 8

sw

107

No. 29

Dote

RPAN

4/23/73

2.5.29
2 3

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REMITTANCE PROCESSING DEVICE (RPD)

113

115

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117

119
120
121
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122

ETX NOT USED

;j|>o!i Cmp. 3

Mj7 H 1/4"

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6 3.6

1/4"

pJ7402

O 2.16

Ld AT. -i13

NOT USED

IN 2- PASS

J

Mn I

Mn4

Mj 8

Mn 0

2.14

12 r Ld.CC

D Q

1/2 c

7474_

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9

8

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ICR ©

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DcSp; Cmp 3

Br.Kr, ETX, CCer.

RPD

Common Control

124

2-22-73
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127
128
129
130
131
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TD6

TD5 —TD4

TD3 —TD2

TDI — TD0

135
136
137

TM 6

TM5

14

<

15

II

10

> 5

<

6

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TM3

TM2

TM

TM0

f 3

A3

B2

f 2

A2 8233

0 . 1 z

B 1

f 1 Al

fa

Se SI

FFF

13

12

+ V

15

II

10

2

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B3

f 3

A3

B2

f 2

A2 8233

5.11

81

f 1 Al

sa

f 0

Aa

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r 139

12

TD6

TD5

TD4

TD3

TD2

TDI

TD0

TD0 — TD6

RPD

5/17/72 3.2.8

Conn.

J1

FF ay

TAB 0

EOL

(Z>

Paper (Z\

Out Vl/

Pope

Low

DTR

Grnd (w>

2

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:::iH

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1_J A

O 4 O

7L. iB:§.2ilB6-_j8

I o

I 14

6.1

7|_6B^-82IB6 _ j

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6.2

8

7^G£-82]B4 _ J

7 i_GB;82^IA4 j n 14 O

I 6.4

L8

7 L^J'l.^!?^ _l

U) ."

2 ' 9 ^4r^1 6.5

7L"6B-82IC4 J

IK

IK

6.63

(

IK

6.610

'6.6.11

FF

TAB

T Ty 2

TTy 3

TTy5

TTy4

6-VWO—*—O + 5 V

IK

6.6.2

FF, TAB. TTy 2- TTy 4

141

RPD

5-17-74 3.2.10

143
144

>

4- 146

148
o

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CM

ro o

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4-24-73 3.4.7

156
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