A111D3 DfiVSTfi

NATL INST OF STANDARDS & TECH R.I.C.

All 103087598

Blackburn, David L/Safe operatina area I QC100 .U57 NO.400-44, 1977 cl^VelfpUB-C

FECIAL PUBLICATION 400-44

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

Safe Operating Area Limits

for Power Transistors
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^, Semiconductor Measurement Technology:

Safe Operating Area Limits for Power Transistors

'7

David L. Blackburn

Electronic Technology Division

Institute for Applied Technology

National Bureau of Standards

Washington, D.C. 20234

I U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary

Dr. Sidney Harman, Under Secretary

Jordan J. Baruch, Assistant Secretary for Science and Technology

S, NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director

Issued September 1977
Library of Congress Cataloging in Publication Data

Blackburn, David L. Safe operating area limits for power transistors. (Semiconductor measurement technology) (National Bureau of Standards special publication ; 400^)

Supt. of Docs. Cat. no.: C13.10:400^.

1. Power transistors—Testing. I. Title. II. Series. III. Series: United

States. National Bureau of Standards. Special publication ; 400-44. QC100.U57 no. 400-44 [TK7871.92] 602Ms [621.317] 77-608172

National Bureau of Standards Special Publication 400-44

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-44, 20 pages (Sept. 1977) CODEN: XNBSAV

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402

Price $1—Stock No. 003-003-01833-3

-MIS. .OVrPN^PNT PR.Nim. OPFICF : 1977 0-240^70
PREFACE

This is the script for the third in a series of videotape presentations being

distributed on loan without charge in order to disseminate more effectively to the

semiconductor community the measurement technology improvements developed under the

Semiconductor Technology Program in the Electronic Technology Division of the National

Bureau of Standards (NBS)

.

The Semiconductor Technology Program serves to focus NBS efforts to enhance the

performance, interchangeability , and reliability of discrete semiconductor devices and

integrated circuits through improvements in measurement technology for use in specifying

materials and devices in national and international commerce and for use by industry in

controlling device fabrication processes. Its major thrusts are the development of carefully evaluated and well documented test procedures and associated technology and the

dissemination of such information to the electronics community. Application of the output

by industry will contribute to higher yields, lower cost, and higher reliability of semiconductor devices. The output provides a common basis for the purchase specifications of

government agencies which will lead to greater economy in government procurement. In addition, improved measurement technology will provide a basis for controlled improvements

in fabrication processes and in essential device characteristics.

The Program receives direct financial support principally from two major sponsors:

The Defense Advanced Research Projects Agency (ARPA) , and the National Bureau of Standards

The ARPA-supported portion of the Program addresses critical Defense Department problems in

the yield, reliability, and availability of integrated circuits. Other portions of the

Program emphasize aspects of the work which relate to the specific needs of the supporting

agency. Measurement oriented activity appropriate to the mission of NBS is an essential

aspect in all parts of the Program. Support for the work reported here came solely from

NBS.

Essential assistance to the Program is also received from the semiconductor industry

through cooperative experiments and technical exchanges. NBS interacts with industrial

users and suppliers of semiconductor devices through participation in standardizing or- ganizations; through direct consultations with device and material suppliers, government

agencies, and other users; and through periodically scheduled symposia and workshops. In addition, progress reports are regularly prepared for issuance in the NBS Special Publication

400 sub-series. More detailed reports such as state-of-the-art reviews, literature

compilations, and summaries of technical efforts conducted within the Program are issued

as these activities are completed. Reports of this type which are published by NBS also

appear in the Special Publication 400 sub-series. Announcements of availability of all

publications in this sub-series are sent by the Government Printing Office to those who

have requested this service. A request form for this purpose may be found at the end of

this report.

Through ARPA Order 2397, Program Code 7D10 (NBS Cost Center 4257555).

Principally through the Electronic Technology Program (Cost Center 4257100)

.
I
Semiaonductor Measurement Technology:

Safe Operating Area Limits for Power Transistors

Videotape Script

by

David L. Blackburn

This is a script of a videotape presentation which addresses

deficiencies of present methods for measuring and specifying the power

dissipation capabilities and safe operating area (SOA) limits for power

transistors. These deficiencies result from not including adequately

the effects of significant temperature nonuniformities which occur, primarily

for high-voltage, low-current conditions. Firstly, the specified thermal

resistance of a transistor can be applied strictly only when the junction

temperature is relatively uniform, otherwise the power capability of the

device can be grossly overestimated. Secondly, the use of the standard

method for measuring junction temperature can lead to a serious underestimate of the peak junction temperature if the temperature distribution

is not uniform. Finally, the traditional SOA limits do not consider the

phenomenon of thermal instability and the hot spots that ensue. As a result,

devices can operate with potentially dangerous hot spots within operating

limits that traditionally have been considered to be safe. It is proposed

that the SOA limits be revised to exclude operating conditions where thermal

instability and hot spots can occur. A method for detecting the onset of

thermal instability and triggering a circuit to turn-off the transistor

under test is described. This approach can be used to develop the

revised SOA limits in a nondestructive way.

Key Words: Hot spots; junction temperature; measurement technology;

nondestructive test; reliability; safe operating limits; second

breakdown; semiconductor devices; thermal characterization; thermal

instability; thermal resistance; transistors.

Thermal resistance and junction temperature are parameters which are widely used to determine how much power a transistor may dissipate. They are also used to help to determine the safe operating area limits of power transistors.

Unless we know how to interpret these parameters and limits, we may reduce the performance, reliability, and life of the transistors we use. There are several problems

we should be aware of. First, the concept of thermal resistance can be applied for only

certain operating conditions. Second, the measurement of junction temperature as commonly

performed can lead to serious underestimates of the actual temperatures. Finally, the

forward-bias safe operating area limits of power transistors are frequently inadequate.

Even if the transistor operates within its specified safe operating area, the peak junction temperature may be far in excess of the maximum rated junction temperature.

We have developed what we believe to be an improved nondestructive method for

specifying safe operating area limits for transistors. By using this method, the region

of excessively high temperatures is excluded from the safe operating area.
R

e \

Q

Tr

Tj-Tr

Q

R

Before we discuss this method, let us ThGrmSl ElSCtriCSl review the concept of thermal resistance

and the measurement of junction temperature — first for the ideal world and then

for the real world where temperature non- uniformities and hot spots can occur.

The concept of thermal resistance

provides a simplistic way of indicating

the power dissipation capability of a Vl ~V2 transistor. It can be understood by

analogy between thermal and electrical

characteristics. [Graphic 1] Temperature difference, T - T , is analogous

J K Graphic 1 to voltage difference, " ^2 ' ^^^^ flow,

Q, corresponds to electrical current, I; and thermal resistance, R. , to electrical resistance R. By measuring the junction tem9 perature for a given power dissipation, we can calculate the thermal resistance of the

transistor. We then have a number which can be used as a measure of the power dissipation handling capability of the transistor. For a given maximum allowed junction tem- perature, the lower the thermal resistance, the higher the power which can be dissipated

in the transistor.

Implicit in the use of thermal resistance is the assumption that we have a method

for accurately measuring the junction temperature. If the temperature is uniform across

the device, a number of electrical parameters of the transistor can be used to measure

the temperature. They are the forward junction voltages (which are measured at a particular current), the junction leakage

currents, and the current gain. We have

found that the best one to use is the

forward voltage of the emitter-base junction.

0)

Ui

CD +J

O

>

0

(/) CO OQ

k.

0

E

Lli

Jl>J;

Temperature

Graphic 2

The basis for using the emitter-base

forward voltage as a thermometer can be seen by this relationship. [Graphic 2] For a constant forward current density,

the magnitude of the emitter-base forward

voltage decreases linearly with increasing temperature. If we increase the current density, the curve shifts upward but

the slope does not change significantly.

The temperature coefficient of the

forward voltage is determined for a device
CLOCK PULSE

Graphic 3

type by selecting an appropriately small foirward current and measuring the forward

voltage for different ambient temperatures. These ambient temperatures can be generated

with a hot plate or an oven. This is the procedure that is used in the calibration step

of a standard method to measure junction temperature.

This standard was developed by NBS in cooperation with the Joint Electron Device

Engineering Councils Committee on Power Transistors. The standard was published by the

Electronic Industries Association in 1975 [1].

The measuring circuit used with the standard method is called the emitter-only

switching circuit; the only switching that occurs is at the emitter of the device

being tested. [Graphic 3] The collector voltage is maintained at a constant value

during both the heating and measurement cycles. This voltage is the same as used in the

calibration step.

To measure the junction temperature for a given power level, heating power, which

is controlled by V^^, is applied to the device under test. The power dissipation is

equal to the product of the collector current and the collector-emitter voltage. After

the transistor reaches a steady-state temperature, the heating current is switched from

the device by diverting it to ground through transistor Q which has been turned on by

the clock pulse. Now only the small measuring current, 1^, is applied to the device

under test. Its magnitude is controlled by VMM

The emitter-base voltage is sensed by the sample-and-hold unit as quickly as possible after the heating current has been removed and its value displayed on the digital

[1] Thermal Resistance Measurements of Conduction Cooled Power Transistors, EIA

Recommended Standard, RS - 313 - B (Revision of RS-313-A) , October 1975 (Electronic Industries Association, 2001 Eye Street, N.W. , Washington, DC 20006).

3
Graphic 4A

voltmeter. The junction temperature can

be calculated using the temperature coefficient of the forward voltage that was obtained in the calibration part of the

procedure, where the same measuring current 1^, and the same collector voltage

were used. The thermal resistance of the

transistor is then calculated from the

measured power and the measured junction

temperature

.

Until now we have tacitly been in the

ideal world of uniform current and tem- perature distributions in transistors.

The junction voltage can be uniquely

related to temperature only when the entire junction is at the same temperature. The real world, though, is usually not like

that.

Let us see why. This power transistor has had its cap removed so that we can look

directly at the transistor chip. Let us take a closer look. Under the microscope we can see that the emitter and base regions are interdigitated . [Graphic 4A] I took a similar

transistor and coated the surface of the chip with a thermographic phosphor to display

its temperature distribution while it dissipates power [2]. This phosphor fluoresces

when it is illuminated with near ultraviolet radiation. The intensity of the fluorescence decreases as the temperature increases. Hotter areas of the phosphor appear

darker than cooler ones.

This is how the coated chip looks when illuminated with ultraviolet radiation for a high-current, low-voltage operating condition. [Graphic 4B] There is not much variation

in the intensity of the fluorescence. This indicates a relatively uniform temperature

across the transistor chip, and implies that the power dissipation and therefore the

collector current density are also relatively uniform. Now, let us increase the collector-emitter voltage and decrease the ' collector current in a way that keeps the power

dissipation constant. [Graphic 4C] The fluorescence is no longer uniform. In fact

there is a well defined dark spot which tells us that this area is much hotter than the

surrounding area. This is a stable hot spot. Nearly all of the collector current

passes through this spot. So we see that severe temperature nonuniformities can and do occur in transistors. We expect to see the most severe nonuniformities for low-current,

high-voltage operations.

[2] Brenner, D.J., A Technique for Measuring the Surface Temperature of Transistors by Means of Fluorescent Phosphors, NBS Tech. Note 591, July 1971.

4
Graphic 4C

This shows that the thermal resistance of the transistor is not constant. We have

not changed the power dissipation in the transistor by changing the current and voltage.

Yet, the peak junction temperature in the transistor has changed dramatically. In this case it has changed by about 150°C.

Usually a thermal resistance value for the transistor is calculated from measurements made under high-current, low-voltage conditions. But if we do this, we can seriously underestimate the peak junction temperature which exists for other operating

conditions.

There is yet another problem. If we do have a nonuniform temperature distribution

over the junction, what temperature do we measure when we use the electrical method that

I have just described? Let us take a look at this problem in a little more detail using

this cutaway view of a transistor, which shows the base metallization and diffusion,

5
Graphic 5C

the emitter metallization and diffusion,

and the collector region. [Graphic 5A]

During calibration to determine the

temperature coefficient of the forward

voltage, the transistor is in a uniform

temperature environment. It is conducting

the small measuring current, represented

by these few vertical lines. [Graphic 5B]

The power dissipation is extremely small

so the junction temperature is essentially

uniform as indicated by the horizontal

line

.

With heating power applied to the

transistor, the steady-state temperature

and current distribution might be represented in this way for a high-current, lowvoltage operating condition. [Graphic 5C]

We do not expect appreciable nonuniformi- / ties, even though there may be some small

ripples in the temperature distribution;

these ripples result from the effect

of the emitter fingers.

To measure the forward voltage, the

heating current is diverted from the device

leaving only the measuring current which

has assumed the uniform distribution of

the heating current. [Graphic 5D] Therefore, the measuring current will have es- sentially the same distribution it had

during calibration. Because the measurement and calibration conditions are very

similar, an accurate measurement of the

junction temperature can be obtained.

Consider, though the case where we

try to measure the junction temperature

when the heating current is constricted

as we have seen for low-current, highvoltage conditions. [Graphic 5E] When

we divert the heating current, the measuring current, which essentially takes the

6
Graphic

Graphic 5F

distribution of the heating current, is very much different from the relatively

uniform distribution we had during calibration. [Graphic 5F] The critical

difference is that the density of the

measuring current is much higher than that

during calibration! We are no longer on

the calibration curve we developed earlier

to obtain the temperature coefficient of

the forward voltage. We are on some higher

one

.

But we must know what the measurement

current density is in the hot spot to know how to shift the calibration curve. This can be determined from the cooling

response of the transistor [3]. Doing

this we can obtain estimates of the peak

junction temperature which are only about

10 percent below the value obtained from

direct infrared measurements. But if we ignore the change in current density, we can underestimate the peak junction

temperature by as much as 40 percent or even more.

So , in the real world we have to realize that the thermal resistance is not constant, the junction temperature is not

a unique quantity, and significant underestimates of the peak junction temperature are possible.

I have talked about hot spots and

temperature nonuniformities . What causes

the current in the transistor to constrict

to generate these hot spots? The answer,

in brief, is thermal instability. In 1963,

[3] Blackburn, D.L., An Electrical Technique for the Measurement of the Peak Junction

Teniperature of Power Transistors. Thirteenth Annual Proceedings, Reliahilitu Physios

1975, pp. 142-150, 1975.

7
Scarlett, Shockley, and Haitz [4] first wrote about the nature of thermal instability.

In 1976 we, with Dr. Philip Hower of the Westinghouse Research Labs, were able to show

that it is possible to predict quite accurately operating conditions where thermal

instability will begin [5], [6], [7].

This thermal instability can lead to a runaway condition which ends in second breakdown and, generally, device failure. For some operating conditions, however, internal

processes act degeneratively on the increasing current density to check this instability.

If the instability is checked, a stable hot spot will be formed. Temperatures in such

hot spots are typically greater than 200°C and often in excess of 300°C. The dominant

process that works to stabilize the current density is the base widening effect which

occurs at high current densities [5], [7]. This occurs in nearly all transistors except

for single-diffused structures where no stable hot spots have been found [5].

There are several ways for measuring the onset of thermal instability. Let us look

at two of them. When stable hot spots occur, the common emitter gain of the transistor

decreases suddenly. We can see the development of a hot spot while we monitor the tran- sistor gain. [Video Insert] This phosphor-coated transistor chip is illuminated with

near ultraviolet light so that we can observe the temperature distribution over the

surface of the chip. On the cathode ray screen we plot the collector voltage, on the

horizontal axis, and the base current, on the vertical axis. We keep the collector

current constant so the base current varies inversely with transistor gain. As the

collector voltage is increased, the base current decreases slightly until suddenly the

hot spot occurs. The voltage has to be decreased considerably before the hot spot

suddenly disappears and the base current decreases abruptly. This is what we call thermal

hysteresis [8]. We can cycle the applied voltage a number of times to show it is quite

repeatable

.

You would not ordinarily be aware that the transistor is in such a hot-spot mode

unless you were specifically trying to detect it. However, the switching time, gain,

and linearity of the transistor are affected by the presence of the hot spot. Both

[4] Scarlett, R.M. , Shockley, W. , Haitz, R.H. , Thermal Instabilities and Hot Spots in

Junction Transistors, Physics of Failure in Eleatronias , M.E. Goldberg and J. Vaccaro, Eds., Spartan Books, Baltimore, Md, 1963, pp 194-203.

[5] Hower, P.L., Blackburn, D.L., Rubin, S., and Oettinger, F.F., Stable Hot Spots and

Second Breakdown in Power Transistor, PESC '76 Beaord, 1976 Power Electronios

Specialists Conference ^ pp 234-246 .

[6] Blackburn, D.L. , Rubin, S., and Rogers, G.J., Measurements of Power Transistor

Thermal Instabilities, Stable Hot Spots, and Second Breakdown, lEdM Technical

Digest^ 1976 International Electron Device Meeting, pp. 151-154.

[7] Hower, P.L., A Model for Stable Hot Spots in Transistors, lEDM Technical Digest,

1976 International Electron Devices Meeting, pp. 147-150.

[8] Oettinger F.F. , and Rubin, S., The Use of Current Gain as an Indicator for the

Formation of Hot Spots due to Current Crowding in Power Transistors, Tenth Annual

Proceedings, Reliability Physics 1972, pp. 12-18.

8
TIME

Graphic 6

switching time and gain are reduced and

nonlinear amplification is increased [9]

by the hot spot.

A simpler way to detect the onset of

thermal instability is by measuring the

emitter-base voltage, which is temperature

sensitive [10], [11], [12], If we apply a pulse of power to the transistor and monitor the emitter-base voltage as the tran- sistor heats, the voltage decreases.

[Graphic 6] A continuous concave upward

curve such as this would indicate no instability. If a hot spot forms, we would see a step in the curve. This step

is caused by the sudden increase in the rate of heating of the transistor caused by the

thermal instability. Sometimes this step is clearly evident, but sometimes it is

difficult to discern. To accent the step we can take the time derivative of the emitterbase voltage. [Graphic 7] Instead of looking for a step, we need only look for a pulse.

[9] Sawyer, D.E., and Berning, D.W., Mapping Nonlinearities Over the Active Region of

Semiconductors Devices, Proa lEEEj vol. 64, pp. 1636-1637, November 1976.

[10] Oettinger, F.F. , Blackburn, D.L. , and Rubin, S., Thermal Characterization of Power

Transistors, IEEE Trans. Electron Devices, vol. ED-23, pp. 831-838, August 1976.

[11] Blackburn, D.L., and Rubin, S., A Nondestructive Method for the Determination of

Forward-Biased Safe-Operating-Area Limits for Power Transistors, PESO '77 Record,

1977 Power Electronics Specialists Conference , (to be published)

.

[12] Rubin, S., and Blackburn, D.L. , A Test Unit for the Nondestructive Determination of

Forward-Biased Safe-Operating-Area Limits of Power Transistors, Proceedings of 1977

Industrial Applications Society Annual Meeting, (to be published).

9
In the laboratory, [Video Insert] an oscilloscope is used to monitor the derivative of the emitter-base voltage. We

keep the emitter current constant and progressively increase the collector voltage

with each successive power application.

At first we see no pulse. Then when the

voltage is great enough for thermal instability to occur, a pulse appears. As

the voltage increases, the pulse moves to the left. The thermal instability occurs sooner after the application of power for

greater values of applied voltage.

We can also connect a protective turnoff circuit which is activated when the

pulse begins. It senses the leading

edge of the pulse and turns off the tran- sistor before it can enter into a fully

Excerpt From Video Insert

developed hot-spot mode and reach any

significant temperature extremes.

I have talked about thermal Instability being stabilized by internal processes. For many operating conditions these processes are not capable of checking the instability.

For these conditions, second breakdown occurs. Very high localized currents and temperatures are present when the transistor goes into second breakdown. Usually the transistor

is either degraded or destroyed.

Here is an extreme case of what second breakdown can do to a transistor. [Video

Insert] The current and temperature at the outer edges of these two emitter fingers

became so great during second breakdown that two holes were formed extending completely

through the die to form a collector-to-emitter short circuit. [Excerpt From Video

Insert] This is a common failure mode of second breakdown.

The possibility of destruction through second breakdown is a primary reason for the use of safe operating area limits in transistor data and specification sheets. But these

safe operating area limits are dictated not only by the limits imposed by second breakdown; they are also determined by the limits imposed by the thermal resistance as well

as the maximum current and voltage limits.

fi The maximum safe operating area limits for transistors are usually plotted as the

log of the collector current against the log of the collector-emitter voltage.

10
o

o

Current

Limit

O

Voltage

Limit

Thermal

Limit

log V,CE log V,

Graphic 8A

\

Second

Breakdown

Limit

CE

Graphic 8B

[Graphic 8A] The maximum current is

determined by such considerations as the

size of the chip and interconnecting

wires, the metallization, and the minimum

allowable transistor gain. The maximum

voltage is set by the breakdown characteristics of the collector-base junction.

The establishment of these two limits is

generally straightforward.

Continuing to fill in the gap between these two limits , we have the thermal limit. [Graphic SB] In this region,

the temperature distribution over the

device is still relatively uniform so that the thermal resistance for the

transistor can be used. For a maximum

safe junction temperature, set by the

manufacturer, a maximum allowed power can

be calculated using the thermal resistance of the transistor. This power is constant

and translates as a line with a slope of minus one.

The maximum safe operating area limit specification is completed with the secondbreakdown limit. [Graphic 8C] The traditional way of determining the second-breakdown

limit for a transistor type is to submit many devices to a destructive second breakdown

test. They are operated in successively more stressful conditions until second breakdown

occurs. The voltage and current are noted. By doing this for enough transistors over

ij the voltage-current area of interest, a line can be drawn which is safely below all

!j of the points at which second breakdown would be expected to occur.

I 11

log VcE

Graphic 8C
o

Traditional

Safe

Operating

Area

log VcE

u

o

Second

Breakdown

Thermal

Instability

Stable

Hot-Spots

Graphic 8D

log

Graphic 8E

o

O

log MCE

Graphic 8F

This then completes the traditional

maximum safe operating area limits that are usually specified. [Graphic 8D]

They do not take into consideration the

existence of hot spots. Yet hot spots

may actually appear within these limits,

usually in this region.

Let us take a closer look at the

region where hot spots do occur. In our work with Dr. Hower , we found that very

specific relationships exist between thermal Instability, stable hot spots, and

second breakdown [5]. [Graphic BE]

Thermal instability always precedes second

breakdown. Stable hot spots exist in this

region. Slightly to the left of the thermal Instability limit, the junction temperature

is relatively uniform and may be only 30°C to 40°C above the case temperature. A fraction of a volt to the right, the transistor is in a hot-spot mode. The temperature is

nonuniform with the peak temperature often above the maximum allowed junction temperature

for the transistor. If while in the hot-spot mode the voltage is increased sufficiently,

the transistor will go into second breakdown. At lower currents and higher voltages, hot

spots may not be stable and thermal instability will continue directly into second breakdown.

Superimposing this relationship on the traditional safe operating area [Graphic 8F]

12
O

Proposed

Safe

Operating

Area

we can see that hot spots can appear within

the maximum safe operating area limits

as they are presently specified. Therefore we propose that the safe operating

area for transistors be revised to include

protection against operation in the hotspot mode. [Graphic 8G ] Within this

revised safe operating area, we can be

assured that the transistor will be operated so that the junction temperature will

be relatively uniform and below its maxi- mum rated junction temperature.

log y

While hot spots may not be immediately destructive, the very high localized

temperatures can be expected to be degradGraphic 8G ing to the transistor with time. In this

vein, recent work by Gaur and others [13] at IBM has shown crystal damage in transistors operating repeatedly under hot-spot-like

conditions. Furthermore, the hot spots degrade gain and switching speed, and introduce

nonlinear amplification. Therefore, the revised safe operating area represents a realistic limit for achieving the maximum reliability, performance, and life of transistors

for operation under forward base drive conditions.

The limits of this area for a given device type can be determined nondestructively —

without sacrificing any transistors. This can be done by using the method I described

involving the derivative of the emitter-base voltage to detect the onset of thermal

instability. The derivative pulse can trigger a circuit to turn off the transistor under

test before it is damaged by high, localized temperatures. This method is easily implemented not only by the device manufacturer who generates and verifies the safe operating

area specifications of his product but also by the device user as a check of the products

he buys.

Our discussion has centered around DC operation. For pulsed operation these limits

move out and shift somewhat relative to each other. Depending on operating points,

thermal instability and second breakdown can be initiated in times that range from

milliseconds to microseconds. But the concepts developed for establishing these limits

can also be applied in the case of pulsed operation.

[13] Gaur, S.P., Lowe, G. , and Thorpe, W. , Power Transistor Crystal Damage in Inductive

Load Switching: A Reliability Concern, Fifteenth Annual Proceedings^ Reliability

Physios 1977, (to be published).

13
Let me briefly review the points I made about the thermal characterization of power

transistors

.

First, the concept of thermal resistance cannot be used indiscriminately to define

the maximum power the transistor can dissipate. To do so may grossly overestimate the

power capability of the transistor.

Second, accurate measurement of the junction temperature is not straightforward.

Temperature nonuniformities that can occur will result in serious underestimates of the

actual peak junction temperature, if current density differences are not taken into ac- count .

Third, the traditional way of developing safe operating areas of transistors may

allow potentially dangerous hot spots to occur within the safe operating areas.

Finally, a method is now available which can be used to develop a revised safe

operating area which avoids conditions where hot spots can occur.

CREDITS

Presented by: The National Bureau of Standards

Graphics: Eugene P. Ralston and Raymond W. Gates

Producer: Susan Lieberman

Executive Producer: Harry A. Schafft

Videotaped by: Video Electronics Branch

Division of Administrative Services,

Energy Research and Development Administration

Teleprompter script typed by E. Jane Walters

Camera copy of script typed by Valerie Claggett

14
NSS-114A (REV. 7-73)

U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBS Spec. Publ. 400-44

2. Gov't Ac<fession No.

3. Recipient's Accession No.

4. TITLE AND SUBTITLE

Semioonduotor Measurement Teohnology : Safe Operating Area

Limits for Power Transistors: Videotape Script

5. Publication Date September 1977

6. Performing Organization Code

7. AUTHOR(S)

David L. Blackburn

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

10. Project/Task/Work Unit No.

11. Contract/Grant No.

12. Sponsoring Organization Name and Complete Address (Street, City, State, ZIP)

Same as 9.

13. Type of Report & Period Covered

14. Sponsoring Agency Code

15. SUPPLEMENTARY NOTES

Library of Congress Catalog Card Number: 77-608172

16. ABSTRACT (A 200-word or less factual summary almost si^ificant information. If document includes a significant

bibliography or literature survey, mention it here.) This is a script of a videotape presentation which addresses deficiencies of

I present methods for measuring and specifying the power dissipation capabilities and

safe operating area (SOA) limits for power transistors. These deficiencies result

from not including adequately the effects of significant temperature nonuniformities

which occur, primarily for high-voltage, low-current conditions. Firstly, the

j specified thermal resistance of a transistor can be applied strictly only when the

junction temperature is relatively uniform, otherwise the power capability of the

^ device can be grossly overestimated. Secondly, the use of the standard method for

i measuring junction temperature can lead to a serious underestimate of the peak junction temperature if the temperature distribution is not uniform. Finally, the traditional SOA limits do not consider the phenomenon of thermal instability and the hot

spots that ensue. As a result, devices can operate with potentially dangerous hot

spots within operating limits that traditionally have been considered to be safe.

It is proposed that the SOA limits be revised to exclude operating conditions where

thermal instability and hot spots can occur. A method for detecting the onset of

thermal instability and triggering a circuit to turn-off the transistor under test

is described. This approach can be used to develop the revised SOA limits in a (nondestructive way.

r7. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name; separated by semicolons)

Hot spots; junction temperature; measurement technology; nondestructive test;

reliability; safe operating limits; second breakdown; semiconductor devices; thermal

I characterization; thermal instability; thermal resistance; transistors.

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