# Patent

## Title
Zero voltage switching

## Abstract

A method for providing non-resonant zero-voltage switching in a switching power converter. The switching power converter converts power from input power to output power during multiple periodic switching cycles. The switching power converter includes a main switch and an auxiliary capacitor adapted for connecting to the main switch, and an inductor connectible to the auxiliary capacitor. When the main switch is on, a previously charged (or previously discharged) auxiliary capacitor is connected to the main switch with auxiliary switches. The main switch is switched off with zero voltage while discharging non-resonantly (charging) the auxiliary capacitor by providing a current path to the inductor. The auxiliary capacitor is disconnected from the main switch. The voltage of the auxiliary capacitor is charged and discharged alternatively during subsequent switching cycles. The voltage of the auxiliary capacitor stays substantially the same until the subsequent turn off of the main switch during the next switching cycle with substantially no energy loss in the auxiliary capacitor.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a Continuation of co-pending application Ser. No. 14/585,280 filed on Dec. 30, 2014, which is a Continuation of application Ser. No. 13/338,330 (now U.S. Pat. No. 8,957,645) filed on Dec. 28, 2011, which is a Continuation of application Ser. No. 12/409,604 (now U.S. Pat. No. 8,111,052) filed on Mar. 24, 2009, which claims priority from Application 61/039,046 filed on Mar. 24, 2008. The entire contents of these applications are incorporated herein by reference in their entirety.
The present application claims priority from U.S. provisional application 61/039,046 filed on Mar. 24, 2008 by the present inventors.


BACKGROUND
1. Technical Field
The present invention relates to switching converters and to specifically a method and devices for zero voltage switching for reducing switching losses in switching converters.
2. Description of Related Art
FIG. 1 shows a typical conventional buck-boost DC-to-DC converter circuit 20. The buck circuit of buck-boost DC-to-DC converter 20 has an input voltage Vin with an input capacitor C1 connected in parallel across Vin. Two switches are implemented as field effect transistors (FET) with integral diodes: a high side buck switch Q1 and a low side buck switch Q2 connected in series by connecting the source of Q1 to the drain of Q2. The drain of Q1 and the source of Q2 are connected parallel across an input capacitor C1. A node A is formed between switches Q1 and Q2 to which one end of an inductor 206 is connected. The other end of inductor 206 is connected to the boost circuit of buck-boost DC-to-DC converter 20 at a node B. Node B connects two switches: a high side boost switch Q4 and a low side boost switch Q3 together in series where the source of Q4 connects to the drain of Q3 to form node B. The drain of Q4 and the source of Q3 connect across an output capacitor C2 to produce the output voltage Vout of buck-boost DC-to-DC converter 20.
FIG. 2a illustrates the buck phase or on-state circuit of DC-to-DC converter circuit 20 shown in FIG. 1, the input voltage source Vin is directly connected to inductor 206 and the load is isolated from Vin because Q1 is on, Q2 is off, Q3 is on and Q4 is off. These switch positions: Q1 on, Q2 off, Q3 on and Q4 off; result in accumulating energy in inductor 206 since source Vin is directly connected to inductor 206. In the on-state, output capacitor C2 supplies energy to the load.
FIG. 2b illustrates the boost phase or off-state circuit of DC-to-DC converter circuit 20, Inductor 206 is connected in parallel across the load and capacitor C2 because Q1 is off, Q2 is on, Q3 is off and Q4 is on. Q1 being off isolates inductor 206 from the input voltage (Vin) and capacitor (C1). The stored energy in inductor 206 (as a result of the previous On-state) is transferred from inductor 206 to C2 and the load.
Two common methods of operating DC-to-DC converter circuit 20 are in either continuous mode or discontinuous mode. If the current through the inductor 206 never falls to zero during a commutation cycle (i.e. the time period to perform both the on-state and the off-state), DC-to-DC converter circuit 20 is said to operate in continuous mode and typically the on-state operates for a shorter period of time when compared to the off-state. Discontinuous mode of operation for DC to DC converter circuit 20 occurs when the amount of energy required by the load is small enough to be transferred in a time period smaller than the whole commutation cycle. Typically, the current through inductor 206 falls to zero for a short time period after the off-state period and therefore inductor 206 is completely discharged at the end of the commutation cycle. The commutation cycle therefore includes the on-state, the off-state and the short time period during which the inductor current is zero.
A conventional “resonant” method for achieving virtually zero power loss when switching a switch is to apply a direct current voltage input voltage Vin across a switch (with a diode connected across the switch, the diode is reverse biased with respect to Vin) in series with an inductor L and a capacitor C. The output voltage of the circuit is derived across the capacitor. The output voltage of the circuit could then in principle be connected to the input of a power converter, for example a buck-loaded series tank circuit with load. The resonant frequency of the series inductor L and capacitor C is given by Eq. 1 and the corresponding resonant periodic time T given in Eq. 2.

fo=1⁄2π(L C)1/2  Eq.1

T=1/fo  Eq.2

A pulse response of the circuit means that when the switch turns on, there is both zero current in the inductor and zero voltage across the capacitor (Power=Volts X Current=0×0=zero power loss at turn on). During steady state operation of the circuit, the inductor current and capacitor voltage are sinusoidal and have a 90 degrees phase shift with respect to each other. When the switch turns off (the on period of the switch corresponds to half of the resonant periodic time) there is zero current in the inductor and maximum positive voltage (i.e. Vcapacitor=Vin) across the capacitor (Power=Volts X Current=Vin×0=zero power loss at turn off).
BRIEF SUMMARY
According to an embodiment of the present invention there is provided a method for providing non-resonant zero-voltage switching in a switching power converter. The switching power converter converts power from input power to output power during multiple periodic switching cycles. The switching power converter includes a main switch and an auxiliary capacitor adapted for connecting to the main switch, and an inductor connectible to the auxiliary capacitor. When the main switch is on, a previously charged (or previously discharged) auxiliary capacitor is connected to the main switch with auxiliary switches. The main switch is switched off with zero voltage while discharging non-resonantly (charging) the auxiliary capacitor by providing a current path to the inductor. The auxiliary capacitor is disconnected from the main switch. The voltage of the auxiliary capacitor is charged and discharged alternatively during subsequent switching cycles. The voltage of the auxiliary capacitor stays substantially the same until the subsequent turn off of the main switch during the next switching cycle with substantially no energy loss in the auxiliary capacitor. The switch may include a: silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, electrical relay, reed relay, solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), and/or triode for alternating current TRIAC.
According to the present invention there is provided a switching converter including a buck stage and/or a boost stage including a main switch connecting an input voltage terminal to a first node; an auxiliary capacitor adapted for connecting to the main switch and an inductor adapted for connecting to the first node. The first node is connectible to the auxiliary capacitor by at least two current paths. When the main switch is on, a previously charged (or previously discharged) auxiliary capacitor is connected across the main switch typically with auxiliary switches. The main switch is switched off with zero voltage while discharging (charging) the auxiliary capacitor by providing a current path to the inductor. The auxiliary capacitor is disconnected from the switch. The voltage of the auxiliary capacitor is charged and discharged alternatively during subsequent switching cycles. The voltage of the auxiliary capacitor stays substantially the same until the subsequent turn off of the main switch during the next switching cycle with substantially no energy loss in the auxiliary capacitor. The switching converter may include a single buck stage or a single boost stage.
According to the present invention there is provided a switching converter included a plurality of main switches interconnected in a full bridge topology, the main switches including a first switch, a second switch, a third switch and a fourth switch. A pair of input voltage terminals are attachable at a first node connecting the first and third switches and at a second node connecting the second and fourth switches. A first output voltage terminal is operatively attached at a third node connecting the third and fourth switches. A second output voltage terminal is operatively attached at a fourth node connecting the first and second switches. Bidirectional switches are interconnected in a full bridge topology. The bidirectional switches include a first bidirectional switch, a second bidirectional switch, a third bidirectional switch and a fourth bidirectional switch. The third node connects the first and third bidirectional switches and the fourth node connects the second and fourth bidirectional switches. An auxiliary capacitor connects at one end at a node connecting the first and second bidirectional switches and at the other end at a node connecting the second and fourth bidirectional switches. The main switches are preferably configured to be periodically switched on and off during a plurality of switching cycles. One or more of the main switches is on. A previously charged (or previously discharged) auxiliary capacitor is connected across the main switch typically with auxiliary switches. The main switch is switched off with zero voltage while discharging (charging) the auxiliary capacitor by providing a current path to the inductor. The auxiliary capacitor is disconnected from the switch. The voltage of the auxiliary capacitor is charged and discharged alternatively during subsequent switching cycles. The voltage of the auxiliary capacitor stays substantially the same until the subsequent turn off of the main switch during the next switching cycle with substantially no energy loss in the auxiliary capacitor. A first inductor is typically attachable between the first output voltage terminal and the third node. A second inductor is typically attachable between the second output voltage terminal and the fourth node. The first and second inductor is optionally a single split inductor or inductor is a single inductor connected in series to a transformer primary or other circuitry.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
FIG. 1 shows a typical conventional buck-boost DC-to-DC converter circuit.
FIG. 2a illustrates the buck phase or on-state circuit of conventional DC-to-DC converter circuit.
FIG. 2b illustrates the boost phase or off-state circuit of DC-to-DC converter circuit 20;
FIG. 3 (FIGS. 3a-3d) illustrate a buck-boost DC-to-DC converter, according to an embodiment of the present invention;
FIG. 4 shows a flow diagram of a method for zero voltage switching, running in either continuous or discontinuous mode during the turn off of main switches Q1 and/or Q3, according to embodiments of the present invention;
FIG. 5 shows another embodiment of present invention as applied to a full bridge switched DC-to-DC converter.
FIG. 6 shows a timing diagram of selected voltages and currents in the embodiment of FIG. 5.



The foregoing and/or other aspects will become apparent from the following detailed description when considered in conjunction with the accompanying drawing figures.
DETAILED DESCRIPTION
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures.
It should be noted, that although the discussion herein relates to buck, boost, buck-boost full bridge switching topologies, the present invention may, by non-limiting example, alternatively be configured as well using other types of switching power DC-DC converters including half bridge, flyback, Cuk, as well as DC-AC inverters for both power supply and regulation applications.
Before explaining embodiments of the invention in detail, it is to be understood that the invention is not limited in its application to the details of design and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.
The term “switch” as used herein refers to any type of switch known in the art of electronics switches such as silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, electrical relay, reed relay, solid state relay, insulated gate field effect transistor (IGFET), DIAC, and TRIAC.
The term “zero voltage switching” (or “ZVS”) as used herein is that the peak voltage across a switch, is reduced to substantially zero volts when the switch is being turned either on or off.
The term “cycle” or “commutation cycle” refers to the periodicity of main switch positions in a circuit which performs a process of electrical power conversion or inversion.
The term “power converter” as used herein applies to DC-to-DC converters, AC-to-DC converters, DC-to-AC inverters, buck converters, boost converters, buck-boost converters, buck/boost converters, full-bridge converters and half-bridge converters or any other type of electrical power conversion/inversion known in the art.
The term “buck-boost” converter as used herein refers to a buck converter followed by a boost converter.
The term “non-resonant” as used herein to exclude resonant and quasi-resonant circuits and methods as arc known in the prior art for achieving zero voltage switching.
The terms “charging” and “discharging” in the context of the present invention in reference to charging and discharging a capacitor, are used herein interchangeably except that current flow while charging and discharging is usually in the opposite direction.
Reference is now made to FIG. 3 (FIGS. 3a-3d) showing a buck-boost DC-to-DC converter 40 according to an embodiment of the present invention. A buck circuit 42 of buck-boost DC-to-DC converter 40 has an input voltage Vin with an input capacitor C1 connected in parallel across Vin. Two switches Q1 and Q2 are connected in series at node A by connecting the source of Q1 to the drain of Q2. The drain of Q1 and the source of Q2 are placed in parallel across capacitor C1. A zero-voltage switching feature according to embodiments of the present invention is provided using components: switches Qbu, Qabu, auxiliary (AUX) capacitor Cbu, and diodes D2bu and Dabu in buck circuit 42. The cathode of diode D2bu is connected to one end of capacitor Cbu. The other end of Cbu is connected to the drain of switch Qbu. The drain of Qabu and the anode of diode D2bu are connected in parallel across capacitor C1. The cathode of diode Dabu is connected to the source of switch Qbu. The anode of diode Dabu and the source of switch Qabu are connected across with capacitor Cbu. Node A shared by the cathode of diode Dabu and the source of switch Qbu is connected to the buck end of inductor 206.
The other end of inductor 206 is connected to a boost circuit 44 of buck boost DC-to-DC converter 40 at node B. Two switches Q4 and Q3 are connected in series. The source of Q4 connects to the drain of Q3 at node B. The drain of Q4 and the source of Q3 connect across capacitor C2, across capacitor C2 is the output voltage Vout of buck-boost DC-to-DC converter 40. Additional components: switches Qbo, Qabo, auxiliary (AUX) capacitor Cbo, and diodes D1bo, Dabo are added to achieve zero-voltage switching in boost circuit 44. The anode of diode D1bo is connected to one end of capacitor Cbo. The other end of Cbo is connected to the source of switch Qbo and the drain of Qabo. The source of Qabo and the cathode of diode D1bo are connected in parallel across capacitor C2. The anode of diode Dabo is connected to the drain of switch Qbo. The node between the anode of diode Dabo and the drain of switch Q3 are connected to node B. The cathode of diode Dabo and the source of switch Qbo are connected across with capacitor Cbo.
Reference is still made to buck-boost DC-to-DC converter 40 shown in FIGS. 3a -3d which illustrate operation of buck-boost DC-to-DC converter 40. Reference is now also made to FIG. 4 showing a flow diagram of a method for zero voltage switching, in boost and/or buck topologies during the turn off of main switches Q1 and/or Q3, according to embodiments of the present invention.
Step A. Before switching phase: In FIG. 3a, current flow in buck circuit 42 and boost circuit 44 is indicated by arrow markings and gray shaded line. In buck circuit 42, switch Q1 is on (step 400), switch Q2 is off and switch Qbu is on. Auxiliary (AUX) capacitor Cbu is previously charged to Vin and connected to the source of Q1 (step 402). IL current flows from input, through Q1 through node A to inductor 206.
Meanwhile, in boost circuit, Q3 is on, Q4 is off, Qbo is on. Cbo is previously charged to Vout. IL current flows from inductor 206 through node B.
Step B. Switching off phase: In FIG. 3b, current flow in buck circuit 42 and boost circuit 44 is indicated by the arrow markings and gray shaded lines. Switch Q1 turns off at substantially zero voltage (step 404). Switch Qbu is still on. IL current (of inductor 206) discharges capacitor Cbu to zero voltage through node A through diode D2bu. Q2 turns on and Qbu turns off disconnecting (step 406) auxiliary (AUX) capacitor Cbu.
Meanwhile, in boost circuit 44 Q3 turns off at substantially zero voltage. IL current (of inductor 206) discharges capacitor Cbo to zero voltage through node B through diode D1bo. Q4 turns on and Qbo turns off disconnecting auxiliary (AUX) capacitor Cbo.
Thus ends one switching cycle. Now, for the next switching cycle:
Step C. Before switching phase: In FIG. 3c current flow in buck circuit 42 and boost circuit 44 is indicated by the arrow markings and Grey shaded line. Switch Q1 is on, Switch Q2 is off (step 400). Switch Qabu turns on. Cbu remains discharged from the previous switching cycle and still connected to the source of Q1 (step 402). IL current flows from input through node A, through Q1 to inductor 206.
Meanwhile in boost circuit 44: Q3 is on, Q4 is off, Qabo turns on. Cbo remains discharged from the previous switching cycle.
Step D. Switching off phase: In FIG. 3d, current flow in buck circuit 42 and boost circuit 44 is indicated by the arrow markings and Grey shaded line. Switch Q1 turns off with substantially zero voltage (step 404). Switch Qbu is still on. IL current (of inductor 206) charges capacitor Cbu to Vin voltage through node A through diode Dabu. Switch Q2 turns on. Qabu is turned off and auxiliary (AUX) capacitor Cbu disconnected from the source of Q1 (step 406).
Meanwhile in the boost circuit 44, Q3 turns off at substantially zero voltage. IL current (of inductor 206) charges capacitor Cbo to Vout voltage through node B through diode Dabo. Q4 turns on and Qabo turns off.
Thus ends the second switching cycle. Now, for the next switching cycle the sequence starts again at Step A.
FIG. 5 shows a further embodiment of present invention as applied to a full bridge DC to DC converter 50. Full bridge DC to DC converter 50 has four main switches Sm,1, Sm,2, Sm,3 and Sm,4 connected together in a full bridge configuration. Each of the four main switches (Sm,1, Sm,2, Sm,3 and Sm,4) have respective diode shunts connected in parallel thereto. The diodes placed across switches Sm,1 and Sm,2 are in both the same direction similarly the diodes of Sm,3 and Sm,4 are both in the same direction. All diodes connected across switches Sm,1Sm,2, Sm,3 and Sm,4 are reverse biased with respect to the input voltage Vin. An input voltage (Vin−) of full bridge DC-to-DC converter 50 is connected across the node between switches Sm,2 and Sm,4 and an input voltage (Vin+) is connected at the node between switches Sm,1, and Sm,3. An output voltage (Vout−) of full bridge DC-to-DC converter 50 is connected across the node between switches Sm,1 and Sm,2 connected through a split inductor 500a and output voltage Vout+ is connected at the node between switches Sm,3 and Sm,4 through a split inductor 500b . A bi-directional switch unit 502 includes four bidirectional switches. Each bidirectional switch includes has two switches in series, e.g. (Sa,1, Sa,2) each with a diode connected across each switch with the diodes connected in opposite directions. Bi-directional switch unit 502 is connected at X1 to the node between switches Sm,1 and Sm,2 and at X2 to the node between switches Sm,3 and Sm,4. Bidirectional auxiliary switches are formed between nodes Y1 and X1 using switches Sa,1 and Sa,2, between nodes Y1 and X2 using switches Sa,5 and Sa,6, between nodes Y2 and X1 using switches Sa,3 and Sa,4 and between nodes Y2 and X2 using switches Sa,7 and Sa,8. An auxiliary capacitor Caux is connected between nodes Y1 and Y2.
In different embodiments the present invention may be configured to operate in either continuous or discontinuous current mode. The operation of full bridge circuit 50, according to a feature of the present invention and with reference again to FIG. 5 and FIG. 6 which shows a timing diagram of selected voltages and currents for steps A to H is as follows:

    A) Switches Sm,2, Sm,3, Sa,3, Sm,4, Sm,5, and Sa,6 are turned on, all other switches are off. Current flows from Vout− to Vin− through inductor 500a, and through main switch Sm,2. Current flows from Vin+ to Vout+ through Sm,3 and through inductor 500b. Capacitor Caux is charged so that node Y1 approaches Vin+ and node Y2 approaches Vin−.
    B) Sm,2 and Sm,3 are switched open (off). Switches Sa,3, Sm,4, Sa,5, and Sa,6 remain on. During the switching open of Sm,2 and Sm,3 current from inductor 500a and 500b is diverted respectively through bidirectional switches (Sa,3 Sa,4) and (Sa,5 Sa,6) with voltage across switches Sm,2 and Sm,3 substantially zero. All inductor current flows through Caux from node Y2 to node Y1 which during a period of time dependent on the current in inductors 500a and 500b and the capacitance of Caux inverts the voltage across Caux so that node Y1 is charged to a voltage level equal to Vin− and node Y2 is charged to a voltage level equal to Vin+ via auxiliary capacitor Caux 
    C and D) Once Caux is fully charged and inverted, node Y1 is charged to Vin− and Y2 is charged to Vin+, current now flows from Vout− through inductor 500a through parallel connected diode of Sm,1 and current flows from Vin− through the parallel connected diode of Sm,4, and through inductor 500b to Vout+.
    E) Auxiliary switches Sa,3, Sa,4, Sa,5, and Sa,6 are now turned off with no current flowing through them nor a voltage across them.
    F) Main switches Sm,1 and Sm,4 are turned on with substantially zero voltage across them, diverting most of the current from flowing through their parallel connected diodes to flowing through switches Sm,1 and Sm,4 themselves.
    G) Before the turn on of Sm,2 and Sm,3, main switches Sm,1 and Sm,4 are turned off with zero voltage across them so that current flow is diverted again through their parallel connected diodes.
    H) Main switches Sm,2 and Sm,3 turn on to begin the next switching cycle. Current of inductor 500a flows from Vout− through inductor 500a, through switch Sm,2 to Vin−; and current of inductor 500b flows from Vin+ through Sm,3 to Vout+.
    I) Auxiliary switches Sa,1, Sa,2, Sa,7 and Sa,8 are turned on with zero voltage and zero current.
    J) Sm,2 and Sm,3 open at zero voltage. All inductor current flows now through from Vout− through inductor 500a, through bidirectional switch (Sa,1,Sa,2), through Caux, through bidirectional switch (Sa,1,Sa,2) from node Y1 to node Y2 which over a period of time (dependent on the current in inductors 500a and 500b and the capacitance of Caux) inverts again the voltage across Caux so that node Y1 is charged to a voltage level equal to Vin+ and node Y2 is charged to a voltage level equal to Vin− (as it was in (1)).
    K) Current flows from Vout− through inductor 500a, through the parallel connected diode of Sm,1 to Vin+. Current flows from Vin− through the parallel connected diode of Sm,4 and through inductor 500b to Vout−.
    L) Auxiliary switches Sa,1, Sa,2, Sa,7, and Sa,8 are turned off with zero voltage and zero current.
    M) Main switches Sm,1 and Sm,4 are turned on at zero voltage forcing the current through themselves from Vout− through inductor 500a, through Sm,1, and from Vin− through Sm,4 and through inductor 500b to Vout+.
    N) Before Sm,2 and Sm,3 are turned on, main switches Sm,1 and Sm,4 are turned off with zero voltage, the current flowing again from Vout− through inductor 500a, through the diode of Sm,1, through Vin+ and from Vin− through the diode of Sm,4 and through inductor 500b to Vout+.
    O) Main switches Sm,2 and Sm,3 turn on to begin the next switching cycle. The current flows again from Vout− through inductor 500a, through Sm,2 to Vin− and from Vin+, through Sm,3 and through inductor 500b to Vout+.
    P) Sa,3, Sa,4,Sa,5, and Sa 6 are turned on with zero voltage and zero current.


During the two switching cycles as shown, auxiliary capacitor Caux is charged and discharged by the inductor current with substantially no energy loss due to switching.
The definite articles “a”, “an” is used herein, such as “a converter”, “a switch” have the meaning of “one or more” that is “one or more converters” or “one or more switches”.
Although selected embodiments of the present invention have been shown and described, it is to be understood the present invention is not limited to the described embodiments. Instead, it is to be appreciated that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and the equivalents thereof.

## Claims

1. A method comprising:
charging, through a first switch, a capacitor during a first switching cycle when the first switch is closed at a first time;
discharging the capacitor to an output terminal through an inductor connected between a first node and the output terminal when the first switch is open; and
charging, through a second switch, the capacitor during a second switching cycle when the second switch is closed at a second time.

2. The method of claim 1, further comprising:
discharging the capacitor to the output terminal when the second switch is off.

3. The method of claim 1, wherein discharging the capacitor further comprises discharging the capacitor to an additional output terminal through an additional inductor connected between a second node and the additional output terminal.

4. The method of claim 3, wherein the inductor and the additional inductor are connected in series.

5. The method of claim 1, wherein connecting the capacitor across the first switch comprises connecting the capacitor using a bidirectional switch unit.

6. The method of claim 5, wherein the bidirectional switch unit comprises a plurality of bidirectional switches arranged in a full bridge topology.

7. The method of claim 6, one or more of the plurality of bidirectional switches comprises first and second switch-diode pairs arranged in series.

8. The method of claim 7, wherein diodes in the first and second switch-diode pairs are connected in opposite directions.

9. The method of claim 1, further comprising
charging the capacitor with current from the inductor during one or more switching cycles.

10. The method of claim 9, wherein charging the capacitor with current from the inductor comprises inverting a voltage across the capacitor.

11. A method comprising:
charging a capacitor through a first switch of a plurality of main switches;
diverting current from an inductor to the capacitor through at least one bidirectional switch of a plurality of bidirectional switches while the first switch is off;
inverting a charge on the capacitor; and
charging the capacitor across through a second switch of the plurality of main switches.

12. The method of claim 11, wherein the plurality of main switches are arranged in a full bridge topology.

13. The method of claim 11, wherein the plurality of bidirectional switches are arranged in a full bridge topology.

14. The method of claim 11, further comprising:
diverting current from the inductor to the capacitor through a different bidirectional switch from the at least one bidirectional switch when the second switch while the second switch is off.

15. The method of claim 11, wherein a voltage across the first switch is substantially zero while the current is diverted from the inductor to the capacitor.

16. A method comprising:
connecting a first terminal of a capacitor to a first voltage source via a first main switch of a plurality of main switches and a first bidirectional switch of a plurality of bidirectional switches;
connecting a second terminal of a capacitor to a second voltage source via a second main switch of the plurality of main switches and a second bidirectional switch of the plurality of bidirectional switches;
disconnecting the first and second terminals from the first and second voltage sources by turning the first and second main switches off;
diverting current from a first inductor to the first terminal via the first bidirectional switch; and
diverting current from a second inductor to the second terminal via the second bidirectional switch.

17. The method of claim 16, further comprising inverting a charge on the capacitor.

18. The method of claim 16, wherein the first voltage source is a positive voltage source and the second voltage source is a negative voltage source.

19. The method of claim 16, wherein the voltages across the first and second main switches is substantially zero when the current is diverted from the first and second inductors.

20. The method of claim 16, wherein the first and second inductors are connected in series.