^^^^' °' ^o,

'it \in

National Bureau of Standards

Library, E-01 Admin. Bldg.

OCT 6 1981

1911ii3

^^^^^ NBS TECHNICAL NOTE

. 6/5755^

1105

U.S. DEPARTMENT OF COMMERCE/ National Bureau of Standards

A 20 Bit -

^Switched D/

QC

100

.U5753

NO. 1105

1979

c,2
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards' was established by an act of Congress on March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology

and facilitate their effective application for public benefit. To this end, the Bureau conducts

research and provides: (1) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau's technical work is per- formed by the National Measurement Laboratory, the National Engineering Laboratory, and

the Institute for Computer Sciences and Technology.

THE NATIONAL MEASUREMENT LABORATORY provides the national system of

physical and chemical and materials measurement; coordinates the system with measurement

systems of other nations and furnishes essential services leading to accurate and uniform

physical and chemical measurement throughout the Nation's scientific community, industry,

and commerce; conducts materials research leading to improved methods of measurement,

standards, and data on the properties of materials needed by industry, commerce, educational

institutions, and Government; provides advisory and research services to other Government

agencies; develops, produces, and distributes Standard Reference Materials; and provides

calibration services. The Laboratory consists of the following centers:

Absolute Physical Quantities^ — Radiation Research — Thermodynamics and

Molecular Science — Analytical Chemistry — Materials Science. THE NATIONAL ENGINEERING LABORATORY provides technology and technical ser- vices to the public and private sectors to address national needs and to solve national problems; conducts research in engineering and applied science in support of these efforts; builds and maintains competence in the necessary disciplines required to carry out this research and technical service; develops engineering data and measurement capabilities;

provides engineering measurement traceability services; develops test methods and proposes

engineering standards and code changes; develops and proposes new engineering practices;

and develops and improves mechanisms to transfer results of its research to the ultimate user. The Laboratory consists of the following centers:

Applied Mathematics — Electronics and Electrical Engineering' — Mechanical

Engineering and Process Technology- — Building Technology — Fire Research —

Consumer Product Technology — Field Methods.

THE INSTITUTE FOR COMPUTER SCIENCES AND TECHNOLOGY conducts

research and provides scientific and technical services to aid Federal agencies in the selection,

acquisition, application, and use of computer technology to improve effectiveness and

economy in Government operations in accordance with Public Law 89-306 (40 U.S.C. 759), relevant Executive Orders, and other directives; carries out this mission by managing the Federal Information Processing Standards Program, developing Federal ADP standards

guidelines, and managing Federal participation in ADP voluntary standardization activities; provides scientific and technological advisory services and assistance to Federal agencies; and

provides the technical foundation for computer-related policies of the Federal Government.

The Institute consists of the following centers:

Programming Science and Technology — Computer Systems Engineering.

'Headquarters and Laboratories at Gaithersburg, MD, unless otherwise noted; mailing address Washington, DC 20234. ^Some divisions within the center are located at Boulder, CO 80303.
A 20 Bit + Sign, Relay

Switched D/A Converter

\Dt tU'C- CX.^<^

T. Michael Souders

Donald R. Flach

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, DC 20234

.^< "' 'o. i

V) J

U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary

Luther H. Hodges, Jr., Under Secretary

Jordan J. Baruch, Assistant Secretary for Science and Technology

C NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director

Issued October 1979
National Bureau of Standards Technical Note 1105

Nat. Bur. Stand. (U.S.), Tech. Note 1 105, 21 pages (Oct. 1979) CODEN: NBTNAE

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1979

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402

Stock No. 003-003- Price (Add 25 percent additional for other than U.S. mailing)
Contents

Introduction 1

Design Considerations 2

Polarity and Range Selection 2

Ladder and Trimming Circuits 2

Swi tches 3

Vol tage Reference 4

BCD Codi ng 4

Self-Calibration Circuit 4

Linearity Calibration 5

Optional Offset Binary Coding 7

Conclusion 7

Appendi x 8

References 9

m

A 20 BIT + SIGN, RELAY SWITCHED D/A CONVERTER

T. Michael Souders

Donald R. Flach

A multirange, 20-bit + sign, voltage output D/A converter

is described. The converter exhibits less than 1 ppm (of full

scale range) linearity error, and temperature coefficients of

gain, offset and linearity of less than 0.5 ppm/°C. The design is based on the R-2R ladder network in the current steering mode, using miniature latching relays with mercury wetted

contacts for switching. Ten buffered, temperature-controlled

unsaturated standard cells comprise the voltage reference.

Techniques with design details are presented for minimizing errors due to relay thermal emf's, for implementing a selfcalibration of linearity errors, and for obtaining optional

coding formats. Calibration techniques are discussed and re- presentative calibration data are presented.

Key Words: Digital-to-analog converter; high resolution;

multirange; R-2R ladder; relay switching; self-calibration;

twenty bits + sign; voltage output.

INTRODUCTION

In 1975 a new program was initiated at the National Bureau of

Standards to provide measurement support for the burgeoning electronic

instrumentation industry. An initial requirement of the program was for

an accurate, digitally programmable voltage source to serve as a reference standard. High resolution, linearity and stability, as well as ease and flexibility of operation were the primary performance requirements. A D/A converter having the following specifications was developed to meet these criteria.

• Code Format - Binary Sign-Magnitude, with BCD option requiring

external code converter. TTL compatible inputs.

•Voltage Ranges - ±10 V, ±5 V, ±2.5Vand ±10 V BCD for use with

code converter.

.Resolution - 20 bits + sign, i.e., 10 yV, 5 yV and 2.5 yV

respectively on the 10 V, 5 V and 2.5 V ranges,

bipolar or unipolar.

•Conversion Rate - 100/s, max.

• Linearity - Less than 1 ppm of Full Scale Range (±10 V) after

self-calibration.
•Temperature Coefficients (gain, offset, linearity) - less than

0.5 ppm/°C each, near room temperature.

A self-calibration feature has been included which permits the

linearity of the eight most significant bits to be measured and adjusted

if necessary.

DESIGN CONSIDERATIONS

The basic R-2R ladder network, used in the current switching mode

(Fig. 1), was selected for this design [1]. It has the advantages of

having only two binarily related resistor values, low voltage current

switching, constant power dissipation in the resistors regardless of

switch positions, as well as easy implementation of a self-calibration

technique.

Polarity and Range Selection

A schematic diagram illustrating a more complete implementation is

given in Fig. 2. Polarity and range switching precede the ladder, before the reference voltage is attenuated. These functions are accomplished with amplifier circuits Al and A2, and their respective switches

Sp and Sn. The magnitudes of the two reference polarities are matched

by adjusting the offset voltage of amplifier Al with a panel accessible

trim potentiometer not shown in the figure. Gain adjustment is accomplished by injecting a variable current into the summing node of A2. As

this current is always of the same polarity as the main input current

through Rj^,, the exact value of Rj^, which is nominally (1 .019)«(2R) , is

chosen appropriately to produce an initial negative gain error of approximately 100 ppm. When properly offset, the gain may be adjusted by

100 ppm in both directions by varying Pg.

Ladder and Trimming Circuits

The ladder resistance R was chosen to be 10**^, optimizing the

tradeoff between errors due to amplifier performance, leakage resistance, and switch and wiring resistance. The resistors are etched bulk

metal of a proprietary design. For the most critical applications

(polarity, range, eight most significant ladder bits and output) the

resistors are hermetically sealed in miniature (1 cm x 1 cm x 0.3 cm)

oil-filled cans. These have been matched to better than 10 ppm and ex- hibit temperature coefficients of ±1 ppm/°C and tracking temperature

coefficients of ±0.5 ppm/°C. The quality and tolerances of resistors

used in less critical positions were chosen accordingly.

Operational amplifiers Al -A3 require performance consistent with

20 bit (1 ppm) accuracy, i.e., open-loop gain in excess of 120 dB, s/ery

low offset voltage drift with time and temperature, low offset and bias

currents, low noise, and for A3, settling time (including thermal tails)

of less than 1 ms (see Appendix). Amplifier A4 used in the self calibration circuit described later, requires in addition, a high common

2
mode rejection ratio and yery high input impedance (>10^^f^). Offset

adjustments are available from the front panel for each of these amplifiers.

Bit trimming circuits are provided for adjusting the eight most

significant bits using a non-interacting current injection technique.

The trimming currents are driven through high impedance into the low

voltage nodes shown in Fig. 2. The currents are derived from variable

voltages slaved to the ladder reference voltage. With the component

values shown in the figure, the total adjustment range is ±100 ppm for

each bit. Twenty-turn trimming potentiometers give resolution on the

order of 0.1 ppm.

Switches

For the current steering function, switches having very low and

repeatable contact resistance, and relatively low thermal emf's are re- quired. The performance sought for the most critical switches is approximately 1 m$^ contact repeatability and 1 yV/°C net thermal emf.

Unfortunately, switches offering such low contact resistance generally

have mercury wetted contacts and hence higher thermal emf. Miniature

latching relays with mercury wetted contacts, mounted in 14 pin dual

inline packages were chosen for this task. The switch design minimizes

the thermal emf problem by having the junctions in close proximity, and

when operated statically (without power to the coils) under normal am- bient laboratory conditions exhibit thermal emf's of only 1 -2 yV. For

these same relays, however, large emf's (-150 yV) result from internal

thermal gradients when the relay coils are continually energized. To

minimize this problem, the relay coils are pulsed for approximately

2.5 ms, just long enough to insure that the relay has latched in the

proper position. The circuit of Fig. 3 is used to produce this 2.5 ms drive pulse. Note that a dual one-shot IC is required for each relay,

rather than a single one-shot to provide an enable pulse to all relays

in parallel. This additional circuitry was included to ensure that

each relay is pulsed when and only when the input logic changes state.

Since in many applications only a single or a few bits are changed in

each new word, this technique considerably reduces the average power

supplied to each relay. In applications in which the D/A converter is

ramped up or down one bit at a time, for example, only the least significant bit is exercised at the full word rate, and consecutively

higher bits are exercised proportionately less often. Figure 4 shows

representative plots of the maximum emf's developed across a relay as

a function of switching rate and pulse duration. Equilibrium at the

maximum values indicated was reached after about 5 min. operation at

the designated switching rate.

Finding an exact expression for the resultant error contributions

of the relay thermal s in the general case (arbitrary distribution of

thermals among the relays and arbitrary configurations of switch states)

is a formidable problem. However, the results of extensive measurements

and calculations indicate that the worst-case error voltage will not

exceed 2.5en, where e^ is the maximum thermal emf present in any relay.
This maximum occurs, for example, when continually changing between the

codes 11101010 10101010 1011 and all zeros (0000 0000 0000 0000 0000),

changing between all ones and all zeros gives half of the maximum error

or 1.25en5 and changing only one bit at a time gives an error of 0.5en

or less. These figures have been experimentally determined using a simulation circuit. The worst-case code contains an alternating pattern

since this substantially reduces the total effective resistance in

series with each ON switch. Reducing the conversion rate will, as Fig.

4 suggests, reduce en and hence the resulting errors, proportionately.

Voltage Reference

To achieve the greatest time and temperature stability for the re- ference voltage, ten unsaturated standard cells connected in series and

mounted in a temperature controlled air bath were used (Fig. 5). The

output from these ten cells is buffered with a FET input, low drift,

high gain follower amplifier also mounted in the controlled air bath.

As is shown in the figure, four-wire sensing at the load is provided to

reduce the dependence on connecting leads.

BCD Coding

For a number of applications, BCD coding is more convenient than

binary. The manual calibration of digital voltmeters, for example, proceeds much faster when the voltage source is decimally programmable,

eliminating the need for binary-to-decimal conversion calculations. To

accomodate such applications, a BCD voltage range has been provided

which is used, together with an external hardwired BCD-to-binary code

converter, to provide decimally coded output voltages. The additional

BCD voltage range is necessary since binary full scale of 2^° (=1048576)

is approximately 5"= higher than the nearest convenient decimal full

scale of 1000000. To obtain the 10.00000 V full scale output voltage

for a decimal input code of 1000000 requires a range multiplication

factor of Z^VlO^ = 1.048576, as indicated in Fig. 2,

Self-Cal ibration Circuit

The R-2R ladder network chosen makes possible the use of a simple

self-calibration technique for measuring and adjusting the linearity

errors (Fig. 6). With the addition of a switch to select the voltages

at the nodes indicated, a follower amplifier to buffer the selected

voltages, and a 2/1 resistive divider, the technique can be implemented.

It is designed to compare the weight of each bit with the sum of all the

less significant bits, recognizing that each bit ideally is equal to the

sum of the less significant bits, plus 1 LSB. To assure the accuracy of

the self-calibration technique, it must first be determined that no significant superposition errors exist [2], i.e., that the errors asso- ciated with each individual bit are code-independent, and are directly

additive. An independent calibration is required to determine this.
To test the eight most significant bits (1-8), the technique proceeds as follows:

1. The 10 V range and positive polarity are selected.

2. Bits 1-8 are set to "0" (off-state) and bits 9-20 are set

to "1". Switch Sg is set to node 8.

3. The microvoltmeter (yVM) is adjusted to zero (with its offset

control), if necessary.

4. Bits 1-7 and 9-20 are set to "0", and bit 8 is set to "1".

5. The yVM should read 6.67 yV (1 LSB x divider ratio). Bit 8

is adjusted for the proper reading if in error.

6. Bits 1 - 7 are set to "0", bits 8-20 are set to "1", and

switch S^ is set to node 7.

7. The yVM is again readjusted to zero.

8. Bits 1-6 and 8-20 are set to "0" and bit 7 is set to "1".

9. Bit 7 is adjusted for 6.67 yV on the yVM.

Proceed in like fashion measuring and adjusting bits 6 through 1 in suc- cession. The detector is zeroed each time a new node is selected to

eliminate systematic errors due to amplifier offsets, finite common-mode

rejection, and errors in the resistive divider ratio.

Note that small adjustment errors made in the first few steps of

this process propagate in geometric proportion as the adjustment procedure continues, so that the error in adjusting bit 8 is multiplied by

2^ (128) when the most significant bit is adjusted. This multiplied

error is primarily a gain error (rather than linearity error) and can

be readjusted to zero by performing a gain adjustment after the selfcalibration is completed.

For applications in which the D/A converter is used in automated

test systems, this self-calibration technique can be automated as well

by replacing the manual s\v1.;ch S^. with an electronically programmable

one, and using a digital yVM or its equivalent to measure the selfcalibration voltages. The technique could be used either to flag an out-of-tolerance linearity error for subsequent manual readjustment, or

to compute and store error corrections to be automatically applied,

either with software or hardware.

LINEARITY CALIBRATION

In a converter of this type, superposition errors can arise from

several sources, and their magnitudes should be determined, particular-
ly if the self-calibration technique is to be used and relied upon for

routine verification and adjustment. Typical error sources can include

excessive resistance in common ground buses, and code-dependent selfheating in the output amplifier's feedback resistor. To verify the ac- curacy of the self-calibration technique, and to provide a means for

checking the polarity bit, an independent calibration is needed.* This

is conveniently accomplished by using an accurately knov;n Kel vin-Varley

Divider (KVD) as a comparison standard as illustrated in Fig. 7. The

calibration procedure is as follows:

1. The DAC input code is set to "000... 000", Sg, S and S„ are

set to the UP position connecting the output of A3 to the

detector. The offset voltage of output amplifier A3 is adjusted to zero (detector null).

2. The polarity bit Sp is set to "+", S„ is set to the down

position, disconnecting the reference voltage, and the DAC

input code is set to "111.. .111". The offset voltage of the

range amplifier A2, as propagated to the output and measured

by detector D, is adjusted to zero.

3. Switches Sp and Sp are set to the DOWN position connecting

the KVD to the detector, S„ is set to the UP position reapplying the reference voltage, and the KVD is set to 0.5000000.

The offset voltage of the polarity amplifier Al is adjusted

for detector null. This adjusts the polarity bit.

4. Switches Sp and S„ are set to the UP position to compare the

DAC output with that of the KVD, a selected DAC input code is

set, and the detector is then balanced by adjusting the KVD

setting. The codes and KVD settings are recorded. All twenty

major code transitions for each polarity are then measured in

like fashion. Table 1 gives the first eight transitions in

the first column.

5. The data is normalized by arithmetically offsetting and scaling the KVD settings to force the negative and positive endpoints to their ideal values (-9.99999 and +9.99999). The

normalized data can then be compared at any code setting to

the ideal value of that code, thereby obtaining linearity

errors for each code setting. This has been done for the

eight major code transitions of each polarity in Table 1.

Note that if offset binary coding is used instead of sign-magnitude,

the polarity bit would automatically be included in the selfcalibration routine.
OPTIONAL OFFSET BINARY CODING

If even greater code format flexibility is desired, the modifications made in Fig. 8 will add an offset binary coding capability. When

the code selector switch is in the sign-magnitude position, the two

paralleled resistors return the configuration to that of Fig. 2. In the

offset binary mode, amplifier A6 introduces the necessary offsetting

voltage. The sign bit switch Sp in this mode normally remains in the

"+" position, although complementary coding will result simply by re- versing the sign. Since this sign bit is no longer used, the resolution with offset binary coding is half that of bipolar sign-magnitude,

i.e., vs . If implemented, the self-calibration circuit must

still be used in the sign-magnitude mode, although the calibration

should be valid, in the offset binary mode as well, with the added advantage of the new sign bit (bit 1) being included in the calibration.

CONCLUSION

The completed instrument (less the standard cells reference) is

shown in the photograph of Fig. 9. The digital input code is displayed

in the upper left corner with LED's driven from the input latches.

Screwdriver access to all critical trimming potentiometers, including

gain, sign-bit, offsets, and eight most significant bits, is provided

from the front panel. The self-calibration mode selection switch is seen near the center of the panel. Terminals are available for output

voltage, ladder reference voltage, and the self-calibration test voltage.

The instrument, designated NBS DAC-20, has been in use for nearly

three years, serving as a reference standard in both manual and automatic test systems for evaluating high resolution digital voltmeters,

A/D converters and D/A converters [3]. During this time DAC-20 has

exhibited linearity stability of approximately 2 ppm/yr., so that the

self calibration interval should be six months to maintain 1 ppm

linearity. The observed zero offset stability has been even better.

No direct information is available for the gain stability since the

gain is frequently adjusted in service to match that of instruments

under test.

During the course of these applications, an additional advantage

of using relay switching has become apparent. The inherent isolation

afforded between analog and digital commons greatly reduces problems

resulting from analog-to-digital ground loops, which can otherwise be severe when making automated measurements with ppm resolution.
APPENDIX

The settling time of amplifier A3 can be measured with the circuit

of Fig. 10. A clean 50 Hz squarewave signal is applied to the amplifier

under test, and the settling waveform is viewed at the settling node

marked s, with a high resolution oscilloscope. The time required after

an input voltage transition for the voltage at node s to settle to and

remain within 1/2 (due to the divider ratio) the desired error band is

the settling time. Note that the final "settled" voltage will depend

on the amplifier's offset voltage as well as on the match between the

resistors R. and Rr making up the divider. Schottky diodes are provided

to clamp the settling node to ±0.5V to protect the oscilloscope's input

amplifier from excessive overload. It is important to select an input

amplifier which can recover from the overload to the desired accuracy in

less than the desired settling time of the amplifier under test.

The settling time should be measured for the maximum positive and

negative voltage transitions that will be encountered, e.g., +10 V -> -10 V and -10 V ^ +10 V. Rate related effects can also be checked by

varying the frequency and duty cycle of the input waveform.
REFERENCES

[1] D. Scheingold, Ed., Analog-Digital Conversion Handbook , Norwood,

MA: Analog Devices, 1972, p. 11-38.

[2] J. Naylor, "Testing Digital/Analog and Analog/Digital Converters",

IEEE Trans. Circ. and Syst., Vol. CAS-25, No. 7, July 1978.

[3] T. M. Souders and D. R. Flach, "An Automated Test Set for High

Resolution A/D and D/A Converters", to be published in 1979 EEMTIC

issue of IEEE Trans. Instrum. Meas.
TABLE 1

DAC-2Q Input Code

- nil nil nil nn nil

- oni im nil nn nn

- 1000 0000 0000 0000 0000

- 0100 0000 0000 0000 0000

-0011 nil nil nil nn

- 0001 nil nil nil nn

- 0010 0000 0000 0000 0000

- 0001 0000 0000 0000 0000

- 0000 nil nil nn nn

- 00000111 nil nil nn

-0000 1000 0000 0000 0000

- 0000 0100 0000 0000 0000

- 0000 0011 nn nn nn

- 0000 0001 nil nil nn

- 0000 0010 0000 0000 0000

-0000 0001 0000 0000 0000

- 0000 0000 nil nil nn

+ 0000 0000 nil nil nn

+ 0000 0001 0000 0000 0000

+ 0000 0010 0000 0000 0000

+ 0000 0001 nil nil nn

+ 0000 0011 111111111111

+ 0000 0100 0000 0000 0000

+ 0000 1000 0000 0000 0000

KVD

Setting

Offset

& Gain

Corrected

Settings ^

Settings

Normalized

to ±1.0'

PPM

of

20 V FSR

0.0092918 0.0000005 -0.9999990 0.0

0.2546457 0.2500002 -0.4999997 0.4

0.2546453 0.2499997 -0.5000006 0.3

0.3773225 0.3749998 -0.2500004 0.2

0.3773233 0.3750006 -0.2499988 -0.1

0.4386619 0.4375007 -0.1249986 -0.2

0.4386613 0.4375001 -0.1249998 -0.1

0.4693308 0.4687503 -0.0624994 -0.3

0.4693315 0.4687510 -0.0624980 -0.5

0.4846662 0.4843761 -0.0312479 -0.6

0.4846655 0.4843754 -0.0312492 -0.4

0.4923327 0.4921877 -0.0156246 -0.2

0.4923334 0.4921884 -0.0156232 -0.4

0.4961671 0.4960947 -0.0078106 -0.4

0.4961664 0.4960940 -0.0078120 -0.2

0.4980832 0.4980471 -0.0039058 -0.2

0.4980838 0.4980477 -0.0039046 -0.3

0.5019160 0.5019525 +0.0039050 +0.1

0.5019165 0.5019530 +0.0039060 +0.1

0.5038333 0.5039061 +0.0078122 +0.2

0.5038327 0.5039055 +0.0078110 +0.2

0.5076664 0.5078118 +0.0156236 +0.2

0.5076670 0.5078124 +0.0156248 +0.1

0.5153341 0.5156247 +0.0312494 +0.3

^ Offset by -0.0092913 to bring -Full Scale to 0.0000005.

0.9999995

Scaled by 0.997078 - 0.0092913

' Nornialized to ±1.0 by multiplying x 2 and subtracting (offsetting by)

1.0.

10
TABLE 1 (continued)

DAC-20 Input Code

+ 0000 0111 nil nil nil

+ 0000 nil nil nil nil

+ 0001 0000 0000 0000 0000

+ 0010 0000 0000 0000 0000

+ 0001 nil nil nil nil

+ 0011 nil nil nil nil

+ 0100 0000 0000 0000 0000

+ 1000 0000 0000 0000 0000

+ 01 11 1 1 11 1 1 11 11 1 1 11 11 + 1111 nil nil nil iiii

Offset PPM

KVD & Gain Settings of

Setting Corrected Normal ized 20 V

P Settings ^

0.5156240

to ±1.0 2

+0.0312480

FSR

0.5153335 +0.5

0.5306683 0.5312492 +0.0624984 +0.3

0.5306689 0.5312498 +0.0624996 +0.2

0.5613385 0.5625001 +0.1250002 -0.1

0.5613378 0.5624994 +0.1249988 +0.1

0.6226765 0.6249996 +0.2499992 -0.1

0.6226771 0.6250002 +0.2500004 -0.2

0.7453546 0.7500006 +0.5000012 -0.6

0.7453540 0.7500000 +0.5000000 -0.5

0.9907078 0.9999995 +0.9999990 0.0

n
ref

o

R R

2R

S1

h

-VA/^ f •• •

2R

S3

2R I2R

S4 iSn

II h

Fig. 1 R-2R Ladder Network

Polarity Range Sp

^" I JOV 2R^ ^

10V BCD

R|^s;l.019(2R) 0.5R p Rp Rt—' rH

P, P2 P3 P4 Pg

out

Ladder Trimming

Fig, 2 20-Bit D/A Converter Circuit

12
Data From

o

Input

Latch

*

1/6 7404 Y

7Kn VF

16 15 14

1 O.S.

1/2 74123 ^

7Kft 1/i.F

Peripheral Driver

16 7 6 9 O.S.

V2 74123

12

Q

6 75453

Relay

Drive Voltage

I

V

Relay

Fig. 3 Relay Logic and Drive Circuit

|iV

-o "O'

-o "1

25 50 75 100

Conversion Rate c/s

Fig. 4 Relay Thermal emf s as a Function of Switching Rate and

Pulse Duration

13
Temperature Controlled

Air Bath

10.19 V

r

10 Unsaturated

Standard

Cells

V u A i\

+V-V c

Power

Supply

Ref. Input

DAC-20

Fig. 5 Reference Voltage Supply

ss ^

Off " 1

A4

-ref Q

-NVA". f ^^»^>^v n vvwt ii— • •

-O • • • •-

3 4*««8

9 P

2R

SI 6 S2 i S3

fi oY Yi or Yi

S4

2R

1 0'

; f

A3

2R

Gal Output —o-«

r^icrovolt

r\/leter

Fig. 6 Self-Calibration Circuit

14
I —\^^^^—O 5r

R R R 2R

2R 1 2R 1 2R 2R 2R

J>SA J>S2 J>SZ /S4 /S20 |

JiL—

.

fio? ^0? jio? ^0? ^0?

I p^

• i • • • i f— +^

A3 9

J S

Fig. 7 Linearity Calibration Circuit

R

Eref Q

*R R

^-Sp

A1

A2

V: A6

2R

^wvw • -vvwv—

2R l2R

VSWV ••!

2R l2R

• « 'VVVW I

i 2R

2R

Offset- Binary

iS1 iS2 iS3 J>SA i>S20

i^O? ^0? ^0? ^0? ^0?

2R ? SignIVIag.

A3 Eout

o

Fig. 8 Optional Offset Binary Coding

15
'

^^^>opg^^l^^^W g

= = = i = = 1^^W

###9

• •

;. tit

3 t :CV«:r>TEa <m •'? i-^4-JP

Fig. 9 Completed Instrument

Rj R,

in

ru

R(

A\NAVRf

High Resolution

Oscilloscope

Schottky

Diodes

Rf = Ri = R{ = R| = 10^Q

T

Fig. 10 Amplifier Settling Time' Measurement

16
NBS-114A (REV. 9-76)

U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. Tech Note 1105

^ 3. R«ci$>ieftt's Acctosion Ho.

4. TITLE AND SUBTITLE 5. Publication Date October 1979

A 20 BIT + SIGN, RELAY SWITCHED D/A CONVERTER *.Perfe»s>insg Organization Cods

7. AUTHOR(S)

T. Michael Souders and Donald R. Flach

8. Performing Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, DC 20234

18. Prej8ct/ta^/Wofk ihiU No.

11. Contract/Grant No.

12. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS fSfreet, City, state. ziP)

same as 9 above

13. Type of Report & Period Covered N/A

14. %)8ffisor}ng Agotcy Code

1,^ .\\%«„v-;\,\ 15. SUPPLEMENTARY NOTES

I I Document describes a computer program; SF-185, FIPS Software Summary, is attached.

16. ABSTRACT (A 200-word or /e*« factual summary of moat significant information. If document includes a significant bibliography or

literature survey, mention it here.)

A multirange, 20-bit + sign, voltage output d/a converter is described. The

converter exhibits less than 1 ppm (of full scale range) linearity error, and

temperature coefficients of gain, offset and linearity of less than 0.5 ppm/°C.

The design is based on the R-2R ladder network in the current steering mode, using

miniature latching relays with mercury wetted contacts for switching. Ten buffered,

temperature-controlled unsaturated standard cells comprise the voltage reference.

Techniques with design details are presented for minimizing errors due to relay thermal emf's, for implementing a self-calibration of linearity errors, and

for obtaining optional coding formats. Calibration techniques are discussed and

representative calibration data are presented.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of the first key word unless a proper name;

separated by semicolons) Q i g j ^a 1 - to -ana 1 og converterj high resolution; multirange; R-2R

ladder; relay switching; self-calibration; tv;enty bits + sign; voltage output

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