AlllDD TfiS137

NATL INST OF STANDARDS & TEC^

NBS

PUBLICATIONS

A1 11 009851 37

NBS SPECIAL PUBLICATION 400*65

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

liconductor Measure.

Patterns NBS-28 and NBS-28A:

Random Fault Interconnect Step

Coverage and Other Structures
NATIONAL BUREAU OF STANDARDS

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Semiconductor Measurement Technology:

Test Patterns NBS-28 and NBS-28A: Random Fault

Interconnect Step Coverage and Other Structures

Michael A. Mitchell

Loren W. Linholm

Center for Electronics and Electrical Engineering

National Engineering Laboratory

National Bureau of Standards

Washington, DC 20234

Sponsored by:

Naval Air Systems Command

Arlington, VA 20360

Air Force Wright Aeronautical Laboratories Wright-Patterson AFB, OH 45433

U.S. DEPARTMENT OF COMMERCE, Malcolm Baldrige, Secretary

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director

Issued March 1981
Library of Congress Catalog Card Number: 80-600197

National Bureau of Standards Special Publication 400-65

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-65. 35 pages (Mar. 1981) CODEN. XNBSAV

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1981

For sale by the Superintendent of Documents, U.S. Government Printing Oflfice, Washington, D.C. 20402

Price $2.00

(Add 25 percent for other than U.S. mailing)
Table of Contents

Page

Abstract 1

1 • Introduction 1

2. Random Fault Step-Coverage Structures 2

3. Process Parametric Structures 3

4. Physical Analysis Test Structures 7

Summary 9

Acknowledgments 9

References 10

List of Figures

1. NBS-28 test pattern, composite of all levels 11

2. Detail of upper left-hand corner of random fault interconnect

step-coverage test structure on NBS-28 13

3. Level 1 of NBS-28, source and drain definition level 15

4. Level 2 of NBS-28, polysilicon definition . 17

5. Level 3 of NBS-28 contact window definition 19

6. Level 4 of NBS-28, metal definition 21

7. Level 5 of NBS-28, passivation openings 23

8. NBS-28A test pattern, composite of all levels 25

9. Level 1 of NBS-28A, source and drain definition 27

10. Level 2 of NBS-28A, polysilicon definition 29

11. Level 3 of NBS-28A, contact window definition 31

12. Level 4 of NBS-28A, metal definition 33

13. Level 5 of NBS-28A, passivation openings 35

14. Metal double cross bridge structure 37

iii
Page

15. Polysilicon double cross bridge structure 39

16. Dif f usion/implant double cross bridge structure 41

17. Field oxide surface leakage structure 43

18. Gate oxide surface leakage structure 45

19. Prof ilometer 47

20. Schematic of a longitudinal section through the middle of the

prof ilometer 49

iv
Sem-ieonductov Measuvement Technology

:

TEST PATTERNS NBS-28 and NBS-28A: RANDOM FAULT INTERCONNECT

STEP COVERAGE AND OTHER STRUCTURES

Michael A. Mitchell and Loren W. Linholm

Electron Devices Division

National Bureau of Standards

Washington, DC 20234

ABSTRACT

This report describes microelectronic test structures for detection of random faults in interconnect step coverage and associated

process parametric and physical analysis test structures included

in two test patterns, NBS-28 and NBS-28A, recently designed under

the device test structure program at the National Bureau of Standards. Information about the geometry and application of the test

structures in these two test patterns is provided for those who

wish to fabricate or utilize the test patterns prior to their com- plete evaluation at NBS. Test pattern NBS-28 consists of a random

fault test structure for measuring the integrity of metal interconnects stepping over polysilicon lines. The structure is a metal

serpentine 0.93 m long with 8-]am linewidth and spacings stepped

over polysilicon lines with 8-i-im linewidths and spacings. The ser- pentine is divided into nine arrays containing 150, 220, 480, 950,

2880, 5760, 13440, 28800, and 62400 steps, respectively. Test pattern NBS-28A contains three similar, but reduced, step-coverage

structures with 4-, 2-, or l-ym linewidths and spacings. Test pattern NBS-28A also contains 37 other microelectronic test structures

for providing process parameter or physical analysis information.

Some of these are new structure designs which are now undergoing

development and evaluation.

Key Words

:

Electronics; interconnect; microelectronics; random

fault; step coverage; test structures.

1. INTRODUCTION

Microelectronic test structures are useful for measuring a variety of material and process parameters which affect the functioning of integrated circuits

[1]. One critical parameter is the density of random faults. As a part of a comprehensive project to develop and evaluate microelectronic test structures, the National Bureau of Standards has designed two test patterns,

NBS-28 and NBS-28A, for detecting random faults in interconnect step coverage. This report provides information about the geometry and application for

those who wish to fabricate the test pattern^j prior to their complete evaluation at NBS. The test patterns are compatible with a simple nMOS or pMOS

process. The structures in the test patterns are divided into three general

groups: random fault structures for interconnect integrity; process parametric structures; and physical analysis structures. These are discussed in

sections 2 through 4.

1
2. RANDOM FAULT STEP-COVERAGE STRUCTURES

Interconnections represent one of the most serious problems in VLSI circuits

[2] . The number of faults is proportional to interconnect area, and thus the

problems of detecting and eliminating faults become worse with ever- increasing IC size and complexity. For example, with 12 interconnection levels, circuit wiring will consume more than half the area of a die with 25,000

gates; with fewer levels the area consumed is even greater [2]. The random

fault structures on test patterns NBS-28 and NBS-28A are intended to assess

the capability of a process to produce a single level of fault-free metal interconnects as a function of area and as a function of linewidth and spacing.

The present structure configuration is an extension of the random fault step

coverage test structure on test pattern NBS-7 [3-5] redesigned to include

more steps with smaller dimensions, and to permit investigation of methods of

testing and data analysis in more detail.

Test pattern NBS-28, shown in figure 1, contains a metal interconnect stepcoverage test structure, and two alignment structures for positive and negative photoresist. The pattern was designed to be fabricated in a selfaligned silicon gate nMOS or pMOS process. The step-coverage structure is a serpentine of metal with lines and spacings of S-ym stepping over polysilicon

lines with 8-ijm widths and spaces. A deposited oxide typically 700 nm thick

separates the metal and polysilicon. The profile of this oxide over the

polysilicon step is strongly dependent on processing and is one of the major

factors affecting the quality of the metal interconnect. The serpentine,

0.93 1 m long, is subdivided into nine subarrays containing 150, 330, 480,

960, 2880, 5760, 13440, 28800, and 62400 steps. A configuration such as this

permits the interconnect yield, i.e., the fraction of unfaulted subarrays of

interconnect area A on a wafer, to be measured experimentally. The serpentine configuration has the advantage of compactness. It has the disadvantage

that a short between metal lines, an unintended fault, may interfere with

measurement of the intended fault, an open circuit.

Double probe pads on the structure are used for two purposes. (1) A continuity test between the two probes on each pad can be used to detect a prober

registration problem or an improperly etched passivation layer. (2) A precise four-probe resistance measurement can be made which may be useful in detecting shorts. Current is applied through two probes and voltage is mea- sured with two other noncurrent-carrying probes to eliminate the effects of

contact resistance between probe and pad.

The polysilicon lines are not connected together electrically, except for two

which are connected together at one end and to probe pads at the other end.

A four-probe resistance measurement can be made to check the quality of the

long polysilicon lines. The resistance of these lines can be estimated using

the sheet resistance and linewidth data which can be obtained from the double

cross-bridge structures, such as those included in test pattern NBS-28A.

A detail of a portion of the upper left-hand corner of the step-coverage

structure is shown in figure 2. The solid bars are metal and the light bars,

polysilicon. The detail shows the connection between the leftmost two polysilicon lines and the extensions of the metal lines leading to the contact

pads on the left side of the structure.

2
The test pattern was designed to be fabricated in a self-aligned silicon gate

rjMOS or pMOS process [6] . The five mask levels required to fabricate it are shown in figures 3 through 7. The first mask level, in figure 3, is used to

define MOSFET sources and drains and other windows in the thermal oxide for

doping with impurities by means of diffusion or ion implanting. The second

mask level, in figure 4, is used to define polysilicon features. The third

mask level, in figure 5, is used to cut windows in the oxide levels for

metal-to-diffusion/implant or metal-to-polysilicon regions. The fourth mask,

in figure 6, is used to define metal features. The fifth mask, in figure 7,

is used to cut windows through the passivation layer to the bonding pads.

The structures numbered 1, 2, and 3 in test pattern NBS-28A in figure 8 are reductions of the B-ym linewidth and spacing random fault step-coverage

structure to 4-, 2- and l-ym lines and spacings, respectively. The total

length of metal line in each is 46.6, 23.3, and 11.6 cm, respectively. The

five mask levels required to fabricate test pattern NBS-28A are shown in fig- ures 9 through 13. They serve the same functions as those described for test

pattern NBS-28.

3. PROCESS PARAMETRIC STRUCTURES

Process parametric structures are electrical test structures used for assessing material, process, and device parameters. When a problem is encountered

with the process, the process parametric structures can be helpful diagnostic

tools. There are 28 process parametric structures, all on the NBS-28A test

pattern (see fig. 8). They include: capacitors, contact resistors, double

(orthogonal) cross bridges, MOSFETs , inverters, an NAND gate, and surface

leakage structures. Key dimensions of these structures are given in table 1. There are four capacitors (4 through 7): circular geometry with polysilicon

over gate oxide over diffusion; square geometry with polysilicon over gate

oxide over diffusion; circular geometry with metal over deposited and field

oxide over substrate; and square geometry over deposited and field oxide over

substrate. These are used for dielectric measurements and for comparison of

the effects of round and square geometry on the measured value of capacitance .

The contact resistors (8 and 9) are used for the four-probe measurement of

contact resistance of metal-polysilicon and metal-diffusion/implant contacts .

The double cross bridges are a new design, an extension of the cross bridge

[7] . They are intended for measuring metal, polysilicon, and diffusion/implant sheet resistance and linewidth in orthogonal directions. The three

structures (10, 11, and 12) are shown in more detail in figures 14, 15, and

16, respectively. A second four -probe bridge sheet resistor has been added

to the original cross bridge with its long axis normal to the four-probe

bridge sheet resistor in the cross bridge. The metal sheet resistance and

linewidth obtained from structure 10 are useful for estimating the resistance

of the metal lines in the random fault structures.

The MOSFETs (13 through 22, 27, 28, and 30), inverters (23 through 26), and

NAND gate (29) are used to determine if the process can produce a working

3
active device and to compare the performance of active devices of differing

channel and gate geometries. ,

The two structures for measuring surface leakage are new and included in the

test pattern for initial evaluation. The first surface leakage structure

(31), shown in figure 17 in more detail, is intended to measure conductance

along a field oxide-substrate interface. A serpentine of field oxide is produced by etching a pattern with interdigitated fingers in the oxide with mask

level 1 (fig. 9). The fingers are doped in the diffusion/implant step of the

process. Leakage current between the fingers is measured with an ammeter in

series with a voltage source connected between the top and bottom probe pads

of the structure in figure 17. The effective conducting serpentine region

(between the fingers) is 8 ym long and 14.5 mm wide. Metal covers the ser- pentine and most of the interdigitated fingers for biasing if necessary.

The second surface leakage structure (32), shown in figure 18, is intended to

measure the conductance along the gate oxide-substrate interface. In this case a serpentine of polysilicon over gate oxide in the self-aligned silicon

gate process is used to define intedigitated fingers (see mask level 2, fig.

10). These are also doped in the diffusion/implant step of the process. The

leakage measurement and serpentine geometry are the same as in structure num- ber 31. The polysilicon can be used for biasing, if necessary.

4
Table 1. Process Parametric Structures.

Structure Description

No.

4. Round capacitor with 0.0829 mm^ area, comprised of polysilicon

over gate oxide over diffusion/implant.

5. Same as 4 except square geometry with same area.

6. Square capacitor with 0.0829 mm area, comprised of metal over field oxide.

7. Same as 5 except for round geometry with same area.

8. Four terminal contact resistor with 8-ym square window, metal-todiffusion/implant.

9. Same as 8 except for metal-to-polysilicon.

10. Double cross bridge with center-to-center distance between the

voltage taps, L,^ = 120 ym; linewidth, W^jj = 16 ym; voltage tap

width, Dj^ = 8 ym; and voltage tap length, Tj^^ = 32 ym.

11. Same as 10 except the conductor is polysilicon instead of metal

and Tj^ = 16 ym. The polysilicon is deposited on a gate oxide

over a diffusion/implant window to simulate a silicon gate.

12. Same as 11 except the conductor is a diffusion/implant region instead of polysilicon.

13. FET with 160-ym wide channel and 28-ym wide self-aligned polysilicon gate.

14. FET with 160-ym wide channel and 26-ym long channel. Unlike the

other FETs in this test pattern, this FET has a metal gate 28 ym

wide over field oxide.

15. FET with 120-ym wide channel and 8-ym wide self-aligned polysilicon gate.

16. FET with 12-ym wide channel and 8-ym wide self-aligned polysilicon

gate.

5
Table 1. (continued)

Structure Description

No.

17. Same as 15 except channel and gate width are reduced 1/2.

18. Same as 15 except channel and gate width are reduced 1/2.

19. Same as 15 except channel and gate width are reduced 1/4.

20. Same as 15 except channel and gate width are reduced 1/4.

21. Same as 15 except channel and gate width are reduced 1/8.

22. Same as 15 except channel and gate width are reduced 1/8.

23. Inverter made of structures 15 and 16 (S-ym gates).

24. Inverter made of structures 17 and 18 (4-ym gates).

25. Inverter made of structures 19 and 20 (2-ym gates).

26. Inverter made of structures 21 and 22 (1-ym gates).

27. Structure 15 reduced 1/8. The entire structure is reduced rather

than just the channel width and gate width as in structure 21.

28. Structure 16 reduced 1/8. The entire structure is reduced rather

than just the channel width and gate width as in structure 22.

29. NAND gate formed by adding structure 15 to structure 23.

30. Short channel MOSFET test structure. There are 9 gates of 1-,

1.5-, 2-, 2.5-, 3-, 3.5-, 4-, 6-, and 8-ym width [8].

31. Field oxide surface leakage structure. The effective field oxide

surface is 14.5 mm wide by 8 ym long.

32. Gate oxide surface leakage structure. The effective gate oxide is

14.5 mm wide by 8 ym long.

5
4. PHYSICAL ANALYSIS TEST STRUCTURES

Physical analysis structures are visual, mechanical, and analytical test

structures used for process control. Eight physical analysis structures

which are described in table 2 are located on test pattern NBS-28A. These

are the structures niimbered 33 through 40 in figure 8. They include visual

aids for alignment, linewidth resolution, and etch control; a profilometer

for mechanical thickness measurements; diffusion/implant and polysilicon

areas for measurement of impurity profiles by means of secondary ion mass spectroscopy (SIMS area); and two sets of alignment marks, one for positive

and one for negative photoresist. Each set contains marks for coarse and

fine alignment. Coarse alignment marks for positive and negative photoresist

are also provided on NBS-28.

For clarity, a larger scale drawing of the profilometer (structure number 37

in fig. 8) is shown in figure 19. Figure 20 is a schematic of a longitudinal

section through the middle of the profilometer showing the approximate thicknesses of the various levels.

7
Table 2. Physical Analysis Structures.

Structure Description

No.

33. Secondary ion mass spectroscopy (SIMS) area; 240-ym square

dif f usion/implant with 232-ym square passivation window.

34. Secondary ion mass spectroscopy (SIMS) area; 240-ym square

polysilicon with 232-ym square passivation window.

35. Resolution structure on each mask level with 1-, 2-, 4-, 8-, and

15- ym linewidths.

36. Etch control structure on each mask level with 0-, 1-, 2-, 4-, and

8-ym spacing on levels 1, 3, and 5, and 0-, 1-, 2-, and 4-ym spacing on levels 2 and 4.

37. Profilometer structure for mechanical thickness measurements.

Details are shown in figures 19 and 20.

38. NBS logo.

39. Positive photoresist mask alignment marks. There are two sets,

for coarse alignment (64- by 64-ym squares concentric with 56- by

56-ym squares), and fine alignment (32- by 32-ym squares

concentric with 28- by 28-ym squares). Mask levels are indicated

by bars following each set of alignment marks.

40. Same as 39 except that the structure is for use with negative

photoresist.

8
SUMMARY

The structures in two recently designed test patterns, NBS-28 and NBS-28A,

have been described. They fall into three groups: random fault structures

for assessing the capability of a process to produce fault-free interconnects

stepping over polysilicon lines; process parametric structures which include

electrical test structures such as capacitors, contact resistors, double cross bridges, MOSFETs , inverters, a NAND gate, and developmental surface

leakage structures designed to provide various data for process control; and

physical analysis structures such as alignment marks, visual aids for etch

control resolution, a prof ilometer , and SIMS areas.

ACKNOWLEDGMENTS

The authors gratefully acknowledge the help of W. M. Bullis, R. Mattis, and

D. Blackburn in the preparation of this manuscript. We appreciate the

suggestions for the general form of the surface leakage structure by G. P.

Carver and for the addition of an orthogonal bridge sheet resistor to the cross bridge by Tom Russell.

9
REFERENCES

1. Carver, G. P., Linholm, L. W. , and Russell, T. J., Use of Microelectronic

Test Structures to Characterize IC Materials, Processes, and Processing

Equipment, Solid State Teohnology 23, 85-92 (September 1980).

2. Technology, Eleotvonics 53, 531-563 (April 17, 1980).

3. Buehler, M. G. , and Sawyer, D. E., Microelectronic Test Patterns and

Custom ICS, Civouits Manufacturing V7, 46-56 (February 1980); figure 8,

structure #39.

4. Russell, T. J., Maxwell, D. A., Reimann, C. T. , and Buehler, M. G.

,

A Microelectronic Test Pattern for Measuring Uniformity of an Integrated

Circuit Fabrication Technology, Solid State Technology 22, 71-74

(February 1979).

5. Bullis, W. M. , Ed., Semiconductor Measurement Technology, Progress

Report, April 1, 1977 to September 30, 1977, NBS Spec. Publ. 400-45,

(August 1980).

6. Penny, W. M. , and Lau, L. , MOS Integrated Circuits (Van Nostrand Reinhold

Company, New York, 1972), p. 182.

7. Buehler, M. G. , Grant, S. D. , and Thurber, W. R. , Bridge and van der Pauw

Sheet Resistors for Characterizing the Line Width of Conducting Layers,

J. Electrochem, Soc, 125, 650-654 (1978).

8. Wilson, C. L. , Scanning Electron Microscope Measurements on Short

Channel MOS Transistors, Solid-State Electron. 23, 345-356 (1980).

10
11

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Figure 3. Level 1 of NBS-28, source and drain definition level (nMOS or pMOS

process). This level is only necessary when being processed with drop-ins of

other test patterns or integrated circuits on the same wafer.

15

Figure 4. Level 2 of NBS-28, polysilicon definition.

17

! m

Figure 5. Level 3 of NBS-28 contact window definition.

19

Figure 6. Level 4 of NBS-28, metal definition.

21

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23

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27

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29

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35

37

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Level 2, Polysilicon

Level 3, Contact

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Level 4, Metal

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Window Cut

Figure 15. Polysilicon double cross bridge structure. The dimensions are

Ljjj = 120 irni, Wjjj = 16 ym. Dm = 8 \sa, and Tj^ = 16 ym.

39

Level 1, Diffusion/Implant

Level 3, Contact

i Window Cut

Level 4, Metal

Level 5, Passivation

Window Cut

Figure 16. Diffusion/implant double cross bridge structure. The dimensions

are Lj^ = 120 ym, W^. = 16 ym, D~ = 8 ym, and T^^ = 16 ym.

41

43

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49
NBS-n4A IREV. 2-8C) U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET (See instructions)

1. PUBLICATION OR

REPORT NO. br 4U'J-d5

2. Performing Organ. Report No, 3. Publication Date

March 1981

4. TITLE AND SUBTITLE

Semiconductor Measurement Technology: Test Patterns NBS-28 and NBS-28A: Random

Fault Interconnect Step Coverage and Other Structures

5. AUTHOR(S)

Michael A. Mitchell and Loren W. Linholm

6. PERFORMING ORGANIZATION {if joint or other than NBS. see instructions) NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON, D.C. 20234

7. Contract/Grant No. N000-19-79-1P-99003 & F4l l7';8nN^iitn

8. Type of Report & Period Covered Final

9. SPONSORING ORGANIZATION NAME AND COMPLETE ADDRESS (Street. City. State, ZIP)

Naval Air Systems Command , Air Force Wright Aeronautical Laboratories

Arlington, VA 20360 ^ Wright-Patterson AFB, OH 45433

10. SUPPLEMENTARY NOTES

Library of Congress Catalog Card Number: 80-600197

[^J Document describes a computer program; SF-185, FlPS Software Summary, is attached.

11. ABSTRACT (A 200-worcl or less factuai summary of most significant information. If document includes a si gnificant

bi bl iography or literature survey, mention it here) This report describes microelectronic test structures for detection of random faults

in interconnect step coverage and associated process parametric and physical analysis

test structures included in two test patterns, NBS-28 and NBS-28A, recently designed

under the device test structure program at the National Bureau of Standards. Information about the geometry and application of the test structures in these two test pat- erns is provided for those who wish to fabricate or utilize the test patterns prior

to their complete eva 1 uat ion at NBS. Test pattern NBS-28 consists of a random fault

test structure for measuring the integrity of metal interconnects stepping over polysilicon lines. The structure is a metal serpentine 0.93 m long with 8-ytn linewidths

and spacings stepped over polysilicon lines with 8-ym linewidths and spacings. The

serpentine is divided into nine arrays containing 150, 220, 480, 960, 2880, 57^0,

\3kkO, 28800, and 62400 steps, respectively. Test pattern NBS-28A contains three

similar, but reduced, step-coverage structures with k- , 2-, or 1-ym linewidths and

spacings. Test pattern NBS-28A also contains 37 other microelectronic test structures

for providing process parameter or physical analysis information. Some of these are

new structure designs which are now undergoing development and evaluation.

12. KEY WORDS (Six to twelve entries; alpli abeti cal order; capitalize only proper names; and separate key words by semicolon s) Electronics; interconnect; microelectronics; random fault; step coverage; test

structures

13. AVAILABILITY

f] Unlimited

I I For Official Distribution. Do Not Release to NTIS

rjT] Order From Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. ^ 20402.

Order From National Technical Information Service (NTIS), Springfield, VA. 22161

14. NO. OF

PRINTED PAGES

35

15. Price

Order From Sup. of Doc, U.S. Government Printing Office, Washington, DC

20402.
Announcement of Semiconductor Measurement Technology

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NBS TECHNICAL PUBLICATIONS

PERIODICALS

JOURNAL OF RESEARCH—The Journal of Research of the National Bureau of Standards reports NBS research and develop- ment in those disciplines of the physical and engineering sciences in which the Bureau is active. These include physics, chemistry,

engineering, mathematics, and computer sciences. Papers cover a broad range of subjects, with major emphasis on measurement

methodology and the basic technology underlying standardization. Also included from time to time are survey articles on topics

closely related to the Bureau's technical and scientific programs. As a special service to subscribers each issue contains complete

citations to all recent Bureau publications in both NBS and non- NBS media. Issued six times a year. Annual subscription: domestic

SI3; foreign SI6.25. Single copy. S3 domestic: S3. 75 foreign. NOTE: The Journal was formerly published in two sections: Section A "Physics and Chemistry" and Section B "Mathematical

Sciences." DIMENSIONS/NBS—This monthly magazine is published to in- form scientists, engineers, business and industry leaders, teachers,

students, and consumers of the latest advances in science and

technology, with primary emphasis on work at NBS. The magazine

highlights and reviews such issues as energy research, fire protection, building technology, metric conversion, pollution abatement,

health and safety, and consumer product performance. In addition, it reports the results of Bureau programs in measurement

standards and techniques, properties of matter and materials, engineering standards and services, instrumentation, and

automatic data processing. Annual subscription: domestic SI I; foreign $13.75. NONPERIODICALS

Monographs—Major contributions to the technical literature on

various subjects related to the Bureau's scientific and technical activities. Handbooks—Recommended codes of engineering and industrial practice (including safety codes) developed in cooperation with in- terested industries, professional organizations, and regulatory

bodies. Special Publications—Include proceedings of conferences sponsored by NBS, NBS annual reports, and other special publications

appropriate to this grouping such as wall charts, pocket cards, and

bibliographies. Applied Mathematics Series—Mathematical tables, manuals, and

studies of special interest to physicists, engineers, chemists,

biologists, mathematicians, computer programmers, and others engaged in scientific and technical work.

National Standard Reference Data Series—Provides quantitative data on the physical and chemical properties of materials, compiled from the world's literature and critically evaluated. Developed under a worldwide program coordinated by NBS under

the authority of the National Standard Data Act (Public Law

90-396).

NOTE: The principal publication outlet for the foregoing data is the Journal of Physical and Chemical Reference Data (JPCRD)

published quarterly for NBS by the American Chemical Society

(ACS) and the American Institute of Physics (AIP). Subscriptions,

reprints, and supplements available from ACS, 1 155 Sixteenth St., NW, Washington, DC 20056.

Building Science Series—Disseminates technical information developed at the Bureau on building materials, components,

systems, and whole structures. The series presents research results,

test methods, and performance criteria related to the structural and

environmental functions and the durability and safety characteristics of building elements and systems.

Technical Notes—Studies or reports which are complete in themselves but restrictive in their treatment of a subject. Analogous to monographs but not so comprehensive in scope or definitive in treatment of the subject area. Often serve as a vehicle for final reports of work performed at NBS under the sponsorship of other government agencies.

Voluntary Product Standards—Developed under procedures

published by the Department of Commerce in Part 10, Title 15, of

the Code of Federal Regulations. The standards establish nationally recognized requirements for products, and provide all concerned interests with a basis for common understanding of the

characteristics of the products. NBS administers this program as a supplement to the activities of the private sector standardizing

organizations. Consumer Information Series—Practical information, based on NBS research and experience, covering areas of interest to the con- sumer. Easily understandable language and illustrations provide

useful background knowledge for shopping in today's tech- nological marketplace. Order the above NBS publications from: Superintendent of Documents, Government Printing Office, Washington, DC 20402. Order the following NBS publications—FIPS and NBSIR's—from

the National Technical Information Services, Springfield, VA 22161.

Federal Information Processing Standards Publications (FIPS

PUB)—Publications in this series collectively constitute the Federal Information Processing Standards Register. The Register

serves as the official source of information in the Federal Govern- ment regarding standards issued by NBS pursuant to the Federal Property and Administrative Services Act of 1949 as amende

Public Law 89-306 (79 Stat. 1127), and as implemented by F" ecutive Order 1 1717 (38 FR 12315, dated May 11, 1973) and Part 6 of Title 15 CFR (Code of Federal Regulations).

NBS Interagency Reports (NBSIR)—A special series of interim or

final reports on work performed by NBS for outside sponsors

(both government and non-government). In general, initial dis- tribution is handled by the sponsor; public distribution is by the National Technical Information Services, Springfield, VA 22161,

in paper copy or microfiche form.
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