3 NBS SPECIAL PUBLICATION 400-17

U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards

Semiconductor

Measurement Technology

Progress Report

October 1 to December 31, 1974
NATIONAL BUREAU OF STANDARDS

The National Bureau of Standards' was established by an act of Congress March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology

and facilitate their eflFective application for public benefit. To this end, the Bureau conducts

research and provides: (1) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau consists of the Institute for Basic Standards, the Institute for Materials Research, the Institute for Applied Technology,

the Institute for Computer Sciences and Technology, and the Office for Information Programs.

THE INSTITUTE FOR BASIC STANDARDS provides the central basis within the United

States of a complete and consistent system of physical measurement; coordinates that system

with measurement systems of other nations; and furnishes essential services leading to accurate and uniform physical measurements throughout the Nation's scientific community, industry,

and commerce. The Institute consists of the Office of Measurement Services, the Office of Radiation Measurement and the following Center and divisions:

Applied Mathematics — Electricity — Mechanics — Heat — Optical Physics — Center

for Radiation Research: Nuclear Sciences; Applied Radiation — Laboratory Astrophysics " — Cryogenics ' — Electromagnetics " — Time and Frequency -. THE INSTITUTE FOR MATERIALS RESEARCH conducts materials research leading to improved methods of measurement, standards, and data on the properties of well-characterized materials needed by industry, commerce, educational institutions, and Government; provides

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the use of available technology and to facilitate technological innovation in industry and Government; cooperates with public and private organizations leading to the development of technological standards (including mandatory safety standards), codes and methods of test; and provides technical advice and services to Government agencies upon request. The Insti- tute consists of the following divisions and Centers: Standards Application and Analysis — Electronic Technology — Center for Consumer

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THE INSTITUTE FOR COMPUTER SCIENCES AND TECHNOLOGY conducts research and provides technical services designed to aid Government agencies in improving cost effec- tiveness in the conduct of their programs through the selection, acquisition, and effective utilization of automatic data processing equipment; and serves as the principal focus within

the executive branch for the development of Federal standards for automatic data processing

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divisions: Computer Services — Systems and Software — Computer Systems Engineering — Information Technology.

THE OFFICE FOR INFORMATION PROGRAMS promotes optimum dissemination and

accessibility of scientific information generated within NBS and other agencies of the Federal Government; promotes the development of the National Standard Reference Data System and

a system of information analysis centers dealing with the broader aspects of the National Measurement System; provides appropriate services to ensure that the NBS staff has optimum

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organizational units: Office of Standard Reference Data — Office of Information Activities — Office of Technical

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1 Headquarters and Laboratories at Gaithersburg. Maryland, unless otherwise noted; mailing address Washington, D.C. 20234.

- Located at Boulder, Colorado 80302.
NOV 2 6 1975

Semiconductor Measurement Technology

Progress Report, October 1 to December 31, 1974 ' ^

W. Murray BuUis, Editor

Electronic Technology Division

Institute for Applied Technology

National Bureau of Standards

Washington, D.C. 20234

Jointly Supportefl by: The National Bureau of Standards,

The Defense Nuclear Agency,

The Defense Advanced Research Projects Agency, and

The Navy Strategic Systems Project Office

U.S. DEPARTMENT OF COMMERCE, Rogers C. B. Morton, Secretary

James A. Baker, III, Under Secreiary

Dr. Betsy Ancker-Johnson, AssisfOnt Secretary for Science and lechno/ogy

NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director

Issued November 1975
National Bureau of Standards Special Publication 400-17

Nat. Bur. Stand. (U.S.), Spec. Publ. 400-17, 79 pages (Nov. 1975) CODEN: XNBSAV

U.S. GOVERNMENT PRINTING OFFICE

WASHINGTON: 1975

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402 (Order by SD Catalog No. C13.10:400-17). Price $1.40 . (Add 25 percent additional for other than U.S. mailing).
TABLE OF CONTENTS

SEMICONDUCTOR MEASUREMENT TECHNOLOGY

PAGE

Preface viii

1. Introduction 2

2. Highlights 3

3. Process Chemicals Characterization 6 3.1. Introduction 6 3.2. Boron Nitride 7 3.3. Hydrogen Chloride 7

4. Resistivity; Dopant Profiles 8 4.1. Standard Reference Materials 8 4.2. D5niamic MOS C-V Method 8 4.3. Mathematical Models of Dopant Profiles 11

4.4. Reevaluation of Irvin's Curves

.....

13

5. Crystal Defects and Contaminants , 15

5.1. Thermally Stimulated Current and Capacitance Measurements 15

6. Oxide Film Characterization 18

6.1. X-Ray Photoelectron Spectroscopy 18

6.2. X-Ray Dose in Electron Beam Evaporators 20

7. Test Patterns 22

7.1. Sheet Resistors 22

7.2. Square Array Collector Resistor 25

7.3. MOS Capacitor Over Collector 26

7.4. Base-Collector Diode 27

7.5. Charge-Coupled Device Test Pattern 28

8. Photolithography 32 8.1. Automated Photomask Inspection 32 8.2. Photomask Metrology .

'. 36

9. Epitaxial Layer Thickness 39 9.1. Transient Capacitance Methods 39

10. Wafer Inspection and Test 42

10.1. Flying-Spot Scanner 42

10.2. Scanning Electron Microscopy — Electron-Beam Induced Damage 43

10.3. Automated Scanning Low Energy Electron Probe 46

11. Interconnection Bonding 47

11.1. In-Process Bond Monitor 47

12. Hermeticity 49

12.1. Dry Gas Gross Leak Procedures 49

12.2. Calibration Stand for Gross Leaks 51

13. Thermal Properties of Devices 52 13.1. Thermal Resistance Methods — Darlington Pairs 52 13.2. Transient Thermal Response

...

55

14. References 57

iii
TABLE OF CONTENTS

PAGE

Appendix A. Semiconductor Technology Staff 61

Appendix B. Semiconductor Technology Program Publications ... 62

Appendix C. Workshop and Symposium Schedule 65

Appendix D. Standards Committee Activities 66

Appendix E. Solid-State Technology & Fabrication Services 68

Index 69

iv
LIST OF FIGURES

PAGE

1. Experimental equilibrium and non-equilibrium high frequency capacitancevoltage characteristics of an «-type MOS capacitor 10

2. Experimental oscilloscope traces of voltage, V(t), and non-equilibrium

capacitance, C(t), as a function of time for an n-type MOS capacitor 10

3. Dopant profile calculated from non-equilibrium capacitance-voltage

characteristics 10

4. Finite difference grid used in solving boron redistribution problem 12

5. Calculated reduced phase II current from gold acceptor defects in an n-type

silicon MOS capacitor as a function of temperature for ''^/f'^. = 100, H = 0.2, G = 1, and various values of 6 16

6. Calculated reduced phase II current from gold acceptor defects in an n-type

silicon MOS capacitor as a function of temperature for 6 = 10 K/s, H = 0.2, G = 1, and various values of N./N 16

d t

7. Calculated reduced phase II current from gold acceptor defects in an n-type

silicon MOS capacitor as a function of temperature for 6 = 10 K/s,

Nj/N = 100, G = 1, and various values of H 16

a t

8. Calculated reduced phase II current from gold acceptor defects in an n-type

silicon MOS capacitor as a function of temperature for B = 10 K/s,

Nj/N = 100, H = 0.2, and several values of G 16

a t I

9. Capacitance-voltage characteristic and dynathermal current and capacitance

response of an ideal gold-doped n-type silicon MOS capacitor 17

10. Scaled heating rate appropriate to obtain various emission temperatures

during the phase II response from gold acceptor defects in an n-type

silicon MOS capacitor 17

11. Metamorphoses of carbon Is, oxygen Is, and silicon 2p photoelectron

peaks upon heating 19

12. Absorption of X-rays generated by bombarding aluminum with 10-keV

electrons 21

13. Scaled line drawings of base sheet resistor structures on test pattern

NBS-3 showing critical dimensions 22

14. Sheet resistance as a function of position along a wafer diameter . . 23

15. Sheet resistance as a function of position along the diameter of wafers

etched for different times 23

16. Width of base diffusion window as measured electrically using eq (10) with

X. = 0.083 mil and from photomicrographs along the diameter of wafers

eiched for different times 24

17. Expanded schematic views of the bridge sheet resistor structure

illustrating the measurement of L and W from the photomicrographs 24

18. Square array collector resistor structure 25

19. MOS capacitor over collector structure 27 v
LIST OF FIGURES PAGE

20. Typical high-frequency capacitance-voltage characteristics of a p-type

silicon MOS capacitor showing the effect of surface inversion around

the periphery, the true equilibrium characteristic, and a non-equilibrium,

deep depletion characteristic . 27

21. Base-collector diode 28

22. Cross sectional view through phase 3 electrode of CCD test structure .... 29

23. Block diagram of TV/microscope automatic mask inspection system . . 32

24. Polarizing laser interferometer mounted on window of scanning electron

microscope 36

25. Typical single-line and three-line patterns on artifact for

standardization of line width measurements 37

26. Ideal capacitance-time characteristics for an MOS capacitor on a thin epitaxial layer 40

27. Capacitance-time characteristics for an MOS capacitor on a thin

epitaxial layer when voltage breakdown occurs at voltages less

than the maximum applied bias voltage but greater than the bias

voltage which corresponds to the depletion edge at the layersubstrate interface 40

28. Capacitance-time characteristics for an MOS capacitor on a thin

epitaxial layer when voltage breakdown occurs at voltages lower

than the bias voltage which corresponds to the depletion edge at

the layer substrate interface 40

29. Step-relaxation capacitance-time characteristic for an MOS

capacitor on a thin epitaxial layer when the steady state depletion

width equals or exceeds the layer thickness 40

30. Plot of epitaxial layer thickness and dopant density showing

regions where thickness can be measured by both the ramp-voltage

and step-relaxation methods, by only the ramp-voltage method,

and by neither of these methods 41

31. Pictorial diagram of light and signal paths of dual-laser

flying-spot scanner 42

32. Characteristics of 741 operational amplifiers as a function of

exposure time in a 20 keV beam of a scanning electron microscope 44

33. Characteristics of C-MOS 4007 circuit after various exposures to

a 20 keV beam of a scanning electron microscope 45

34. Block diagram of automated scanning low energy electron probe 46

35. Gas handling circuit for rapid gas cycling technique for measurement

of gross leaks 49

36. Vacuum circuit for calibration system for gross leaks and vacuum

gauges 51

37. Four-terminal Darlington transistor with external resistors 53

38. Voltage between output emitter and input base as a function of the

collector-emitter voltage of the output transistor for a constant

vi
LIST OF FIGURES PAGE

collector current showing onset of hot spot formation and thermal

hysteresis 54

39. Electrically measured average junction temperature as a function

of the area of heat source 56

LIST OF TABLES

PAGE

1. Intermediate Results of Interlaboratory Test on SRM 1520 9

2. Boron Concentration in Silicon at the Moving Boundary between

the Silicon and Silicon Dioxide 12

3. Preliminary Resistivity-Carrier Density Data for PhosphorusDoped Silicon at 300 K 14

4. Calibration of TLDs using the Backward Radiation from Thick

Aluminum Target Bombarded by 10 keV Electrons 21

5. Comparison of Resistivity Measured by Square Array Test Structure

with Resistivity Measured by Four-Probe Method before Processing 26

6. Metallization Area 29

7. MOS Capacitor Parameters 30

8. MOS Transistor Parameters 30

9. Critical Parameters for TV/Microscope Mask Inspection Systems with

a 20 by 20 mm Image Tube Target 33

10. Scan Times for Two State-of-the Art TV/Microscope Mask Inspection

Systems 35

11. Comparative Measurements of the Width of a Chromium Line on Glass .... 38

12. Summary of Analysis of Limitations of Transient Capacitance Methods

for Measuring Epitaxial Layer Thickness 41

13. Dose Accumulated in Gate Oxide for 1 Second SEM Exposure 45

14. Typical Examples of Leak Rates Measured using Rapid Gas Cycling

Gross Leak Test 50

15. Calibration Constants for a Four-Terminal Darlington Pair 53

16. Thermal Resistance Measurements on Four-Terminal Darlington 53

17. Thermal Resistance Measurements on Integrated Darlington

Transistors 54

vii
PREFACE

The Semiconductor Technology Program serves

to focus NBS efforts to enhance the perform

mance, interchangeabllity , and reliability

of discrete semiconductor devices and integrated circuits through improvements in measurement technology for use in specifying

materials and devices in national and international commerce and for use by industry in

controlling device fabrication processes.

Its major thrusts- are the development of

carefully evaluated and well documented test procedures and associated technology and the

dissemination of such information to the

electronics community. Application of the

output by industry will contribute to higher

yields, lower cost, and higher reliability

of semiconductor devices. The output provides a common basis for the purchase specifications of government agencies which will

lead to greater economy in government procurement. In addition, improved measurement

technology will provide a basis for con- trolled improvements in fabrication processes and in essential device characteristics.

periodically scheduled symposia and workshops. In addition, progress reports, such

as this one, are regularly prepared for is- suance in the NBS Special Publication 400

sub-series. More detailed reports such as state-of-the-art reviews, literature compilations, and summaries of technical efforts

conducted within the Program are issued as these activities are completed. Reports of

this type which are published by NBS also

appear in the Special Publication 400 subseries. Announcements of availability of

all publications in this sub-series are sent by the Goverjiment Printing Office to those

who have requested this service. A request

form for this purpose may be found at the

end of this report.

The Program receives direct financial support principally from three major sponsors:

the Defense Advanced Research Projects Agency (ARPA) , the Defense Nuclear Agency

(DNA),^ and the National Bureau of Standards

(NBS) . In addition, the Program receives

support from the U.S. Navy Strategic Systems

§ Project Office. The ARPA-supported portion

of the Program, Advancement of Reliability,

Processing, and Automation for Integrated

Circuits with the National Bureau of Standards (ARPA/ IC /NBS )

, addresses critical Defense Department problems in the yield, re- liability, and availability of integrated

circuits. The DNA-supported portion of the

Program emphasizes aspects of the work which

relate to radiation response of electron devices for use in military systems. There is

considerable overlap between the interests

of DNA and ARPA. Measurement oriented ac- tivity appropriate to the mission of NBS is

a critical element in the achievement of the

objectives of both other agencies.

Essential assistance to the Program is also

received from the semiconductor industry

through cooperative experiments and technical exchanges. NBS interacts with industrial users and suppliers of semiconductor devices through participation in standardizing

organizations; through direct consultations

with device and material suppliers, government agencies, and other users; and through

Through ARPA Order 2397, Program Code 5D10

(NBS Cost Center 4259555).

Through Inter-Ageiicy Cost Reimbursement

Order 75-816 (NBS Cost Center 4259522).

Through Scientific and Technical Research

Services Cost Centers 4251126, 4252128,

and 4254115.

Code SP-23, through project order

N0016475P070030 administered by Naval Am- munition Depot, Crane, Indiana (NBS Cost

Center 4251533) and Code SP-27, through

IPR SP6-75-4 (NBS Cost Center 4251547).

viii
SEMICONDUCTOR MEASUREMENT TECHNOLOGY

PROGRESS REPORT

October 1 to December 31, 1974

Abstract: This progress report describes NBS activities

directed toward the development of methods of measurement for

semiconductor materials, process control, and devices. The

emphasis is on silicon device technologies. Principal accom- plishments during this reporting period include (1) initiation

of development of -measurement technology for characterizing

boron nitride diffusion sources and hydrogen chloride purging

gas, (2) application of dc electrical methods with a sensitivity of about 0.1 pm to the measurement of critical dimensions

such as the width of diffusion windows, (3) completion of an initial comparison of line-width measurements made with an image shearing eyepiece and a filar eyepiece, and (4) development of procedures for measuring electrically the thermal re- sistance of the output transistor of integrated Darlington

pairs. Also reported are the intermediate results of an interlaboratory evaluation of standard reference wafers for resistivity, evaluation of the deep-depletion method for measuring

dopant density with an MOS capacitor, progress on development

of mathematical models of dopant profiles, initial results of

the reevaluation of Irvin's curve for n-type silicon, analysis

of thermally stimulated current and capacitance measurements on MOS capacitors, study of surface carbon contamination which

occurs during measurement of silicon by X-ray photoelectron

spectroscopy, preliminary measurements of absorbed dose from

electron-beam evaporation of aluminum films, initial evaluation

of the CCD test structure operating as an MOS capacitor and an MOS transistor, analysis of a TV-microscope system for photomask inspection, initial study of calibration procedures and

artifacts for photomask metrology, analysis of the range of

applicability of MOS C-V methods for epitaxial layer thickness

measurement, use of an optical flying-spot scanner, assessment

of damage to selected integrated circuits caused by inspection

with a scanning electron microscope, mathematical modeling of

ultrasonic bonding, a dry gas method for gross leak testing,

and measurements of transistor thermal response. Supplementary

data concerning staff, publications, workshops and symposia,

standards committee activities, and technical services are also

included as appendices.

Key Words: Boron nitride; boron redistribution; capacitancevoltage methods; Darlington pairs; deep depletion; dopant profiles;

electrical properties; electron beam evaporator; electron beam induced damage; electronics; epitaxial layer thickness; filar eyepiece; flying-spot scanner; hermeticity; hydrogen chloride gas;

image shearing eyepiece; laser interf erometry ; measurement methods;

microelectronics; micrometrology ; MOS devices; oxide films; photomask inspection; resistivity; scanning electron microscope; scan- ning low energy electron probe; semiconductor devices; semiconductor

materials; semiconductor process control; silicon; test patterns;

thermal resistance; thermal response; thermally stimulated current; ultrasonic bonding; wire bonds; x-ray photoelectron spectroscopy.

1
1 . I N T R 0 D U C T I 0 fl

This is a report to the sponsors of the

Semiconductor Technology Program on work

during the twenty-sixth quarter of the Program. It summarizes work on a wide variety

of measurement methods for semiconductor materials, process control, and devices that are being studied at the National Bureau of

Standards. The Program, which emphasizes

silicon-based device technologies, is a con- tinuing one, and the results and conclusions

reported hSre are subject to modification

and refinement.

The work of the Program is divided into a number of tasks, each directed toward the

study of a particular material or device

property or measurement technique. This re- port is subdivided according to these tasks.

Highlights of activity during the quarter

are given in section 2. Subsequent sections

deal with each specific task area. References cited are listed in the final section

of the report.

The report of each task includes a narrative

description of progress made during this re-j

porting period. Additional information con- cerning the material reported may be obtained directly from individual staff members identified with the task in the report.

The organization of the Program staff and

telephone numbers are listed in Appendix A.

Background material on the Program, and individual tasks may be found in earlier quarterly reports as listed in Appendix B. From

time to time, publications are prepared that

describe some aspect of the program in

greater detail. Current publications of

this type are also listed in Appendix B. Reprints or copies of such publications are usually available on request to the author.

Communication with the electronics community

is a critical aspect both as input for guidance in planning future program activities

and in disseminating the results of the work

to potential users. Formal channels for

such communication occur in the form of

workshops and symposia sponsored or co- sponsored by NBS. Currently scheduled seminars and workshops are listed in Appendix C. In addition, the availability of proceedings

from past workshops and seminars is indicated in the appendix.

An important part of the work that frequently goes beyond the task structure is participation in the activities of various technical standardizing committees. The list of

personnel involved with this work given in

Appendix D suggests the extent of this participation. In most cases, details of

standardization efforts are reported in con- nection with the work of a particular task.

Technical services in areas of competence

are provided to other NBS activities and

other government agencies as they are re- quested. Usually these are short-term,

specialized services that cannot be obtained through normal commercial channels.

To indicate the kinds of technology available to the Program, such services provided

during the period covered by this report are listed in Appendix E.

2

X
2 . HIGHLIGHTS

shments in the resistivity range 0.3 to 5.6 Q'cm as ude (1) in- a beginning to the reevaluation of the re- ement tech- lationship between resistivity and free

itride dif- electron density. In this range the data

ide purging agree closely with the published data of

ical meth- Irvin as fitted by Caughey and Thomas.

Particularly significant accompli

during this reporting period incl

itiation of development of measur

nology for characterizing boron n fusion sources and hydrogen chlor

gas, (2) application of dc electr

ods with a sensitivity of about 0.1 ym to the measurement of critical dimensions such

as the width of diffusion windows, (3) com- pletion of an initial comparison of linewidth measurements made with an imageshearing eyepiece and a filar eyepiece, and

(4) development of procedures for measuring

electrically the thermal resistance of the

output transistor of integrated Darlington

pairs. Highlights of progress in these and

other technical task areas are listed below.

Process Chemiaals Charaaterization — In- vestigations of methods for characterizing

selected process chemicals were begun at the

Pennsylvania State University with ARPA

funding. The initial studies are concentrating on methods for determination of deleterious impurities in boron nitride diffusion sources and water vapor content of hydrogen chloride gas.

Resistivity; Dopant Profiles — The interlaboratory evaluation of the long-term precision attainable with silicon standard reference wafers for resistivity measurement by

the four-probe method reached its half-way

point. Four of the six participating laboratories exhibit good control over their measurements and agreement to much less than 1 percent both with the certified resistivity

of the laboratory-owned wafers and with the

grand average resistivity of the circulating

wafers

.

The deep depletion capacitance-voltage characteristic of an MOS capacitor was investiI gated as a means for determining dopant density of the semiconductor. Four possible

sources of error were considered. The deepj depletion method yields a dopant density

I value more characteristic of the bulk than

the more traditional C - C . method. max mm

A finite difference algorithm was successfully used to solve the moving boundary boron redistribution problem. The solutions

for several appropriate sets of conditions

j were compared with the time independent exj act solution to provide a bench mark prior

I to making calculations for other conditions

I not amenable to exact solution.

Data were obtained on n-type silicon wafers

Crystal Defects and Contaminants — The an- alysis of the thermally stimulated current

and capacitance response of mid-gap

acceptor-type defects was extended to the case of an MOS capacitor. The phase I current response was found to yield the same emission temperature as that of a p'^n junction. The sensitivity of the phase II re- sponse to various parameters was determined.

Oxide Film Characterization — Further study

of x-ray photoelectron spectra from the surface of a silicon specimen during various

heating cycles confirmed that the carbon

film arises from an as yet unidentified re- sidual gas in the spectrometer.

Oxide characterization work has been focussed on the study of techniques for determining and controlling the quality of fur- nace environments used in growing gate oxides and in subsequent annealing. In con- junction with this effort, a quadrupole mass spectrometer was assembled for measurement

of the gas atmosphere in the oxidation furnace, preliminary measurements of sodium

contamination in a variety of processing materials were made using flame emission spectroscopy, and steps were taken for determining stability of the oxides produced.

A preliminary measurement was made of the

radiation field present during the operation

of an electron beam evaporator. During a typical evaporation of an aluminum gate

electrode, the gate oxide receives an absorbed dose of the order of 0.1 to 1.8 x 10^ rad(Si02) (0.1 to 1.8 x lo'* J/kg) from

the aluminum K radiation. An additional

a dose of approximately similar magnitude a- rises from the bremsstrahlung continuum.

Test Patterns — Evaluation of the test structures on test pattern NBS-3 was begun

with detailed investigation of the four base

sheet resistors. By combining dc measurements on van der Pauw and bridge structures

it was possible to determine the width of

the base diffusion window. This technique,

which is sensitive to changes in width of

about 0.1 pm, utilizes measurements which

can be made quickly and at low cost on com3
HIGHLIGHTS monly available automatic equipment. The

results agreed well with measurements scaled

from a photomicrograph.

Other test structures on test pattern NBS-3

are being used in the reevaluation of Irvin's

curves. These include the square-array collector resistor, which yielded resistivity

values in good agreement with standard fourprobe measurements; a circular MOS capacitor

over the collector; and a circular basecollector junction.

Initial measurements in the evaluation of

the CCD test structure connected as an MOS

capacitor or as an MOS field effect transistor were completed.

Pho toti thography — Detailed analyses of

various state-of-the-art technologies for

automatic inspection of photomasks were begun. The criteria selected were ability to detect a defect of dimension 2 um and misregistration of ±0.25 pm. The first system

analyzed was one composed of a TV camera

tube which views the mask through a microscope. It was concluded that inspection of

a 3 in. by 3 in. mask in 11 or 12 min would

be possible using state-of-the-art components

although this is significantly faster than

existing prototype of this system.

A polarizing interferometer with 1 nm displacement resolution was constructed for use

in making in situ measurements of the position of a scanning electron microscope stage.

Preliminary measurements using standard

stages revealed the need for a more rigid

stage assembly with fewer than the usual degrees of freedom for micrometrology experiments .

A preliminary experiment established that it

is possible to transfer a line-spacing measurement to a line-width measurement using a multilayer metal artifact In a scanning electron microscope (SEM) . The artifact was designed for use in calibrating the magnification of a SEM; it does not simulate the con- ditions encountered in making dimensional

measurements on photomasks. A different ar- tifact was designed with 1 to 10 pm wide

lines to simulate the properties of a photomask. This artifact is intended to be fabricated in a film of chromium or iron oxide

on an optically flat glass plate.

Comparative measurements of the width of a chromium line on a glass substrate were made

using both bright field and dark field illumination and filar and image shearing eyepieces. The measured value was significantly

smaller when the filar eyepiece was used

with dark field illumination.

Epitaxial Layer Thickness — The rampvoltage and step-relaxation methods for measuring epitaxial layer thickness were analyzed to determine the ranges of thickness

and layer resistivity over which they can

be used. The ramp-voltage method was found

to be applicable over a wider range of parameters .

Wafer Inspection and Test — A second laser

and improved display amplifiers were added

to the flying-spot scanner. Observations

were made of a bipolar NAND gate and a C-MOS

inverter circuit.

Several typical integrated circuits were

studied to assess the damage caused by ex- amination with a scanning electron microscope. No significant damage occurred to a bipolar digital inverter under any condition

studied. Both a bipolar linear operational

amplifier and a C-MOS Inverter exhibited se- verely degraded characteristics when exam- mined with bias applied, but neither showed

significant changes when examined for typical times without bias.

Work continued at the Naval Research Laboratory on the development of an automated

scanning low energy electron probe as a noncontacting, non-damaging wafer test technique .

Interconnection Bondi'ng —

the uniform beam model for

vibration of an ultrasonic

tinued with the addition o dition to account for the

tip during the bonding ope

suits suggest that the amp loaded nodal positions and

be related to the force du

Development of

analysis of the

bonding tool conf a boundary con- force at the tool

ration. The re- litudes at the un- the tool tip can ring bonding.

Study of the non-destructive accoustic emission test to determine the bond quality of

beam lead, flip-chip, or other gang bonded

devices continued.

Hermeticity — The experimental phase of the

interlaboratory evaluation of the radioisotope method for leak testing semiconductor

devices was completed. Ten industrial or- ganizations participated in the test.

A rapid gas cycling technique is being evaluated for use as a quantitative, dry gas, gross leak test. Initial calculations suggest that the technique may be suitable for

a wide range of leak sizes.
HIGHLIGHTS

Thermal Properties of Deviaes — Further

study confirmed the feasibility of using the

modified emitter-only-switching method for

measuring the thermal resistance of the output transistor of a monolithic Darlington

circuit. It was also found that the voltage

between the base of the input transistor and

the emitter of the output transistor, measured during the power-off portion of the

thermal resistance measuring cycle, is a good indicator of the onset of a current

constriction in the output transistor.

Development of electrical techniques for es- timating peak junction temperature of power

transistors continued. It was established

that one of the necessary quantities, the

total active area of the device, can be determined from measurements of the heating

response of the device.

Work was initiated on an automatic stepping

stage for use with the infrared microradiometer in order to facilitate measurement

of surface temperature distributions on power devices and integrated circuits.

Recommendations concerning changes to the

thermal resistance methods in MIL-STD-750B

,

for discrete semiconductor devices, were

formulated at the request of EIA Committee

G-12 on Solid State Devices. These recom- mendations, which are based on standards developed by various EIA-JEDEC Committees and

draw heavily on prior NBS work, were submitted to the Defense Electronics Supply Center

for consideration.

5
3 . PROCESS C f] E f1 I C A L S CHARACTERIZATION

3.1. Introduction

An important factor for the improvement of

process control and reliability of digital

integrated circuits is the need to control

the purity of the various chemicals used

during the fabrication process. In many

cases these chemicals, such as diffusion

sources, epitaxy chemicals, and other chemicals are supplied by vendors with little or

no insight into the material purity levels

that are detrimental to device reliability

and performance. This is particularly true since normal chemical analysis techniques

which might be used by suppliers do not provide the necessary detectability limits.

Often only the electrical testing of the final device structure brings out the influence a particular chemical impurity has on device performance and in the case of integrated circuits it is generally impossible

to gain access to individual devices which

make up the circuit.

A new effort has been undertaken at the

Solid State Device Laboratory of Pennsylvania State University in order to develop measurement techniques for monitoring chemicals used in digital integrated circuit manufacturing. The study is aimed at chemicals

used in the three principal processes of oxidation, diffusion, and epitaxy. It is intended to analyze various chemicals, then

use these chemicals to process devices or

test patterns which can be analyzed by electrical tests. An important aspect of the

initial phase effort is the determination of

the detectability limits of the analytical

and electrical measurements and degree of

correlation of electrical measurement techniques with analytical measurements.

In the initial investigations the materials

to be characterized with respect to their

impurity levels are boron nitride, compositions of boron nitride with silica, and hydrogen chloride gas. These materials were

selected because of their wide use in diffusion and oxidation processes in digital integrated circuit fabrication. Boron nitride

wafers have gained acceptance as diffusion

sources as silicon wafer diameters have increased [1]. The use of hydrogen chloride

gas has recently gained wide acceptance in

the growth of high quality oxides particularly in MOS technology.

Boron nitride has evolved from a refractory

material to one used in semiconductor applications. Because of its original refractory

nature, the material has metallic impurities, in the 1 to 100 ppm levels, which can lead to reduced carrier lifetime and high reverse currents in p-n junctions. The

present study seeks to determine the tolerable level of these metallic impurities in

boron nitride diffusion sources. Experiments using emission spectroscopy, will be

conducted to determine the density at levels

of 0.5 ppm or greater of impurities, such as gold, iron, or copper, in the boron nitride

as manufactured. Next the boron oxide

glass transferred to the silicon wafer during diffusion will be analyzed using flameless atomic absorption, at levels of 1 ppm

or less, to determine how much of the impurity has been transferred. Then thermally

stimulated current and carrier lifetime mea- surements will be made to determine the

level and energies of impurities that are present in p-n junctions fabricated using

the boron nitride source.

These experiments will provide the necessary

correlation data needed to establish chemical purity standards and feedback to boron

nitride manufacturers. Boron nitride wafers

and powder which have been manufactured by

different techniques will be furnished by a cooperating supplier during the course of

the study.

The study of hydrogen chloride gas is focussed on the determination of the allowable

water vapor level. Studies have shown that

the presence of small amounts of water vapor

can destroy the passivation effects of hydrogen chloride [2]. Oxide layers will be

grown and examined for various levels of

water vapor in the hydrogen chloride . Dynamic growth rates as a function of time will

be measured for different levels of water

vapor using thermogravimetric analysis which

has a detectability limit of 5 nm of silicon

dioxide. The hydrogen chloride and water

vapor mixtures will be furnished by a second

cooperating supplier. (J. Stach")

Work conducted at the Pennsylvania State

University under NBS contract 5-35717.

NBS contact for additional technical information: R. I. Scace.

6
PROCESS CHEMICALS CHARACTERIZATION

3.2. Boron Nitride

Prints of the mask set for test pattern NBS2 (NBS Tech. Note 788, pp. 15-17) [3] have

been obtained and a process developed to enable the fabrication of boron nitride diffused diodes and gated MOS capacitors for

use in the study of boron nitride diffusion

sources. The electrical measurement methods

that are being emphasized initially include

thermally and optically stimulated techniques [4] and carrier lifetime. Mechanical,

electrical, and optical designs for the system to make measurements of thermally and

optically stimulated current and capacitance

were completed and the parts are being assembled. The system for measuring carrier

lifetime by the MOS capacitance method [5]

has also been designed.

The analysis of various boron nitride starting powders and the development of suitable

standards for emission spectroscopy measurements are currently being undertaken. A

joint effort with the supplier has been initiated to determine the impurity levels introduced during various stages of boron

nitride wafer fabrication in typical production runs. This lot of wafers (100% boron

nitride and boron nitride/silicon dioxide)

is then to be used to study impurity partitioning during activation (surface oxidation

of the boron nitride to boron oxide) and

diffusion. (J. Stach")

3.3. Hydrogen Chloride

The design of the system for thermogravimetric analysis has been completed. This includes thermal, gas handling, and specimen

fixtures. Arrangements have been made with

the cooperating manufacturer to supply various samples of hydrogen chloride for thermogravimetric analysis. Controlled amounts of

water vapor will be introduced from a special moisture mixture supplied by the manufacturer. (J. Stach")

7
4 . R E S I S T I V I T Y ; D 0 P A N T P R 0 F I L E S

4.1. Standard Reference Materials

In conjunction with offering for sale standard reference silicon wafers with certified

resistivity values for use with four-probe

measurements [6], NBS is conducting a multipass experiment with five other laboratories

to test the long-term precision attainable

with these wafers and to determine their

stability. The experiment requires each laboratory to measure monthly its own set of

standard reference wafers according to ASTM

Method F 84 [7] with the exception that only

two resistivity values instead of the normal

ten be measured for each wafer. Two additional sets of standard reference wafers are being circulated to the participating laboratories such that each month one of the laboratories also measures these circulating

wafers according to the same method except

that five measurements are made on each circulating wafer. The circulating wafers have

been to each laboratory once which brings the

experiment approximately to its half-way

point although some laboratories have reported more measurements than others on the

non-circulating wafers.

The results of this first phase of the ex- periment are summarized in table 1. With

two exceptions, the participants appear to have good control over the measurements.

Laboratory 2 shows a significant high-side

bias on its high-resistivity wafer as well

as the greatest variability in measurements

of in-house wafers. Laboratory 4 shows a strong high-side bias in all of its measurements despite the good reproducibility of

these measurements. The test will be con- cluded after each laboratory reports 12 sets

of measurements on its in-house wafers and

after the circulating wafers complete their

second cycle. (F. H. Brewer)

4.2. Dynamic MOS C-V Method

In the traditional high frequency MOS capacitance-voltage (C-V) measurement (NBS Spec.

Publ. 400-4, pp. 37-38), the rate of the

voltage bias sweep is kept slow enough to allow equilibrium in the inversion regime to be maintained through minority carrier generation. As a result, the semiconductor

space charge region assumes a fixed width

and the MOS capacitance saturates to its

minimum value, shown in figure 1 as C . . mm

If however, the sweep rate is rapid enough

that the minority carrier generation is insufficient to maintain equilibrium, the

semiconductor becomes depleted and the space

charge width increases. The capacitance as- sociated with this depletion regime is shown

as curve in figure 1. The dopant density

profile can be deduced from this C-V characteristic when it is analyzed according to standard models [8].

In the experiment, the bias applied to the

MOS capacitor is a repetitive (approximately

10 Hz) ramp or triangular voltage of the appropriate magnitude and polarity. A threeterminal capacitance bridge provides an analog signal proportional to the measured ca- pacitance. Both the analog capacitance signal and the applied ramp voltage are simultaneously displayed on a dual channel oscilloscope. Typical waveforms are shown in

figure 2 as they appear on the oscilloscope

face. The data acquisition and analysis

system employed permits processing of the

data displayed on the oscilloscope.

The algorithm for the calculation is based

on the expression for the dopant density,

N(X), at the edge of the space charge region

as deduced from the simple depletion model

[8]:

N(X) = PtT^ . (1)

where X is the depletion width, q is the

electronic charge, is the relative dielectric constant of silicon, eg the permittivity of free space, C is the measured

capacitance per unit area, and V is the

bias voltage. Under software control the

C(t) and V(t) waveforms are sampled and

stored; typically 1000 scans are averaged to produce a smooth curve. Time is used as an independent parameter to find the derivative

in eq (1) . From the smoothed capacitance

curve, the quantity [C(t)]~2 is calculated

and differentiated to obtain d [C (t) ]""^/dt

.

Similarly the smoothed voltage curve is differentiated to find dV/dt. The depletion

width corresponding to each value of bias

voltage is calculated from

K e s 0 (2)

where C is the oxide capacitance per unit

Q area and C is the measured capacitance per

unit area for the particular voltage.

8
RESISTIVITY; DOPANT PROFILES Tabl e 1 _ T ntprmpd i fl tp Results of Interlaboratory Test on SRM 1520

a

.

La bora tory- Owned IaI^ ov^ c iaM I" h Mom "i T Via Itlib WILiI INUIlllllCll ixt. o 1 b L 1 V 1 Ljr U 1 U.I o • rm

Certified INUlKUtri U

1

nV c 1 ciy c ^amnl

p

Laboratory Resistivity, M o A CI \ Y* om o

n "f" rica bU I trlllci 1 L r\t. b I o L 1 V 1 l,jr 5 9tH Dpv

Reporting Q-cm ra 11 o r\t:pUi LcU Q • cm /o

1 0.11 974 8 0.12006 0.21

2 0. 1 1825 6 0.11883 1 .24

3 0.11885 5 0.11 937 0. 58

4 0.12033 5 0.12261 0.66

5 0.11925 8 0.11849 1 .03

6 0 12056 6 0.11994 0.49

b. La bora tory- Owned Walcib WILil nUKIIilal i\t:b 1 b L 1 V I Ly U 1 1 U

Certified INUIHUci U 1 r\A\/V PK'rl C 1 u n P y c ^amnl

P

v.)Ctni|j 1 c Laboratory Resistivity, RpQi Qi'iui't'v/ stH npv Reporting Q'cm ra ii o r\cuui l-cu Q • cm "/

10

] 1 1 . 251 8 11 .309 0.27

2 11.118 6 11 .351 1 .65

3 n .178 5 11 .246

4 1 1 . 098 5 11 .406 0.40

5 11 .062 8 1 1 . 078 1 .23

6 11 .054 6 11 . 081 0.48

c . Circulating Wafers with Nominal Resistivity of 0.1 n " cm

Wafer A-13 Wafer A-17

Average Sample Average Sriinni p Laboratory Resistivity, Std. Dev., Resistivi ty

,

Reporting fi'Cm % Q'Cm °l10

Rp'f prpnrp'^ 0.1194 0.1200

1 0.1192 0.40 0.1198 0.13

2 0.1194 0.2 0.1197 0.1

3 0.1190 0.15 0.1197 0.37

4 0.1223 0.04 0.1240 nU . o^fiu

5 0.1196 0.21 0.1201 0.19

6 0.1183 0.21 0.1191 0.31

Average^ 0.11963 1.15 0.12040 1 .49

d . Circulating Wafers with Nominal Resistivity of 10 ^m

Wafer B-84 Wafer A-17

Average Sampl

e

Average ^r^mnl p Laboratory Resistivity, Std. Dev.

,

Resistivity, Std Rpv

Reporting U'Cm % n-cm 10

Rp"f prpnrp^^ 11.11 11 .20

"1 11.11 0.13 11.18 0.16

? 11 .05 0.6 11 .07 0.9

3 11.14 0.44 11.26 0.59

4 11 .39 0.39 11 .47 0.21

5 11.17 0.10 11 .25 0.11

6 n .05 0.13 11.10 0.31

Average^ 11.15 1.13 11 .22 1 .28

^The reference value was obtained from the overall average of two sets of readings by each of two operators at NBS taken over a period of two weeks.

^Mean and sample standard deviation of the individual laboratory averages.

9
RESISTIVITY; DOPANT PROFILES

-80 -60 -40 -20 0 20

V (volts)

Figure 1. Experimental equilibrium and

non-equilibrium high frequency capacitancevoltage characteristics of an n-type MOS

capacitor. (C = 7.54 pF; oxide thicknes

= 522 nm; the

C fb'

flat-band capacitance,

the flat-band voltage,

Figure 2. Experimental oscilloscope traces

of voltage, V(t), and non-equilibrium

capacitance, C(t), as a function of time

for an n-type MOS capacitor.

^ 6 " 4

2

1 1 1 1

\C(t)

1

1

1

1 0 10 20 30 40

TIME (msl

+ 20

0

-20

</> -40 +-o

>

-60

-80 +-«

-100

1x10'

E

o

00 1x10"

a.

1x10

- N= 1,06x10 cm

0.372^11

0.5 1.0 1.5 2.0 2.5 3.0 DISTANCE FROM INTERFACE [fim]

Figure 3. Dopant profile calculated from

non- equilibrium (deep depletion) capacitancevoltage characteristics.

10
RESISTIVITY; DOPANT PROFILES

Results of a typical measurement are shown

in figure 3 as a plot of dopant density

against distance from the silicon-oxide interface. The specimen used was phosphorusdoped with a nominal resistivity of 1 fi'cm. The wet oxide, grown at 1000°C for 150 min,

had a nominal thickness of 500 nm. The aluminum gate electrodes were evaporated with

an electron-beam evaporator and the wafer

was annealed in nitrogen for 30 min at 500°C.

There are at least four sources of error in

the profile which must be considered.

First, at large depletion depths the C(t) curve is changing very slowly. The differentiation in this region is then very sensitive to random fluctuations in the C(t) curve; as a result there is likely to be appreciable scatter in the calculated dopant

density at large distances from the interface, as can be seen in figure 3. Some improvement could be made by averaging over

longer periods of time or by using a larger

differentiation grid as the change in capacitance becomes small,

A second source of error is the effect of

fringing fields on the MOS capacitor. For materials of relatively low dopant density

10^^ cm~3) depletion depths can be

large ('\^ 10 pm) . This causes a spreading

of the electric fields away from. the gate

and could cause an increase in the measured

capacitance. This edge effect is serious

for devices where the maximum depletion

depth is a finite fraction of the device

radius. Typically, the presence of fringing fields causes the calculated dopant

density to be larger than the actual dopant

density; the error increases as the depletion depth increases.

The third source of error arises because of

limitations in the simple depletion model.

In the ideal case, depletion starts at the

flat-band voltage. Experimentally, the ca- pacitance near the flat-band voltage is always less than the theoretical depletion

capacitance. Therefore, the calculated profile lies above the true profile near the

flat-band condition until the true depletion

regime is entered. In the example shown in

figure 3, the first data point on the left

corresponds to a voltage slightly more negative than the flat-band voltage so this error may be present.

The fourth source of error arises from the

departure of the C—V characteristic from the

ideal as a result of fast interface states. Interface states contribute to the capacitance and will cause distortion or structure

in the calculated profile. When present

they exert their greatest influence in the

surface region of the profile.

One other point to be considered is the com- parison of the dopant density as determined

by the traditional C - C . method (NBS max min

Spec. Publ. 400-4, pp. 37-38) and that determined by the deep depletion method described here. The dopant density determined

by the C - C . method is the average den- max mm

sity within the equilibrium depletion depth.

In figure 3 the horizontal and vertical arrows indicate the dopant density (N) and the

equilibrium depletion depth (X^) determined

from this method. Note that the calculated

density is significantly higher than the

bulk density determined from the deep depletion technique which allows penetration of

the space charge region much farther than

the equilibrium high frequency technique

which is employed in the C - C . method. max mm

It is clear that the C - C . technique max mm

determines a dopant density which is more

characteristic of the surface region and

may have little relation to the bulk dopant

density. (R. Y. Koyama)

4.3. Mathematical Models of Dopant Profiles

This report outlines a finite difference

algorithm [9] for the solution of the boron

redistribution problem described previously

(NBS Spec. Pubis. 400-1, pp. 9-11, and

400-4, pp. 9-11). This algorithm consists

of a set of algebraic equations whose solution approximates the solution of the partial differential equations which govern the

boron concentration in the silicon and the

silicon dioxide (NBS Spec. Publ. 400-1, eqs

(4), (5), and (7), pp. 10-11).

As previously discussed two coordinate systems are used: in the silicon, a fixed

system with its origin at the initial silicon surface, and in the oxide, a system

with its origin at the oxide-air interface

which moves away from the initial silicon

surface with a velocity inversely proportional to the square root of the time. The

silicon-oxide interface moves in the opposite direction with a similar velocity.

The motion of this interface complicates the

11
PLSI5TIVITY, DOPAfiT PPOFILC':

AZ

0 —•

' • IZo(MM)

NL-1 NL

Yo (MM)h

NR NR + 1 N2

Figure 4. Finite difference grid used in solving boron redistribution probler

Table 2 - Boron Concentration in Silicon at the Moving Boundary

between the Silicon, and Silicon Dioxide

Case m Cb^ C2(yo(t))^^'^ k Zo(ktt) CB(2,Zo(k^t))^

la 1 .2 0.1 10 4.466 90 49 0.067 4.594

b 800 49 0.1988 4.594

2a 1.2 10 10 9.653 90 49 0.0669 9.558

b 800 49 0.1988 9.557

3a 1.2 0.1 10 6.187 800 1 8.82

b 800 5 7.122

c 800 49 6.386

4a 0.5 0.1 10 2.264 800 1 4.718

b 800 4 2.719

c 800 97 2.281

^Arbitrary units.

'^Calculated from analytic solution, ref. 11.

12
RESISTIVITY; DOPANT PROFILES

application of the finite difference technique. The grid used is depicted in figure

4. The mesh width At in the time domain and

the mesh widths Ay and Az in the silicon and

the oxide respectively are coupled. In the

oxide there are NL interior grid points (1,

2, .... NL-1, NL) separated by Az. The position of the interface at the time (MM) At

is denoted by z^(MM), where MM is the number

of time intervals since the beginning of the

oxidation; the distance between (NL)Az and

z (MM) varies. In the silicon the first

ofull mesh width to the right of the interface y^(MM) begins at (NR)Ay; the interior

grid points (NR, NR+1, N2), spaced Ay

apart, extend to (N2)Ay.

In the oxide the approximate solution has

the form Ci(niAz, kAt) for 1 < nj < NL and

k > 0 at the grid points and CB(1, z (kAt))

o for k > 0 at the boundary. In the silicon

the approximate solution has the form

C2(n2Ay, kAt) for NR < n2 < N2 and k > 0 at

the grid points and CB(2, y (kAt)) for k ^ 0 at the boundary.

The algebraic equations which comprise the

finite difference equations are obtained by

discretizing the integral-conservation

equivalents of the above mentioned partial

differential equations. In particular, the

differential form of the conservation of mass at the boundary, expressed in integral

form is

where Z H (NL)Az and Y E (NR)Ay. By ap- A jo proximating the derivatives in eq (3) by

their finite difference equivalents and the

integrals by quadratures, one obtains an implicit algebraic equation of the form

A-Ci(NL, MM) + B-CB(1, MM)

+ C'C2(NR, MM) + D-CB(2, MM) = F, (A)

where the coefficients A, B, C, D, and F are constants related to the grid approximation.

This equation and the boundary condition

(NBS Spec. Publ. 400-1, eq (6), pp. 10-11)

CB(2, MM) = mCB(l, MM)

,

where m is the segregation coefficient, re- present two equations in the unknown boundary values CB(1, MM) and CB(2, MM). These

equations and the usual implicit equations

associated with all the interior grid points

form a linear algebraic system which can be

solved by a variant of the well known method

for treating tridiagonal systems [10]. To provide a bench mark comparison, this system

was solved for several cases under conditions for which the analytic solution of

Grove et at. [11] can be obtained. Table 2 lists a comparison between these solutions.

If the segregation coefficient is substantially different from one, the value CB(2,

z^(kAt)) calculated for a very short time

after the oxidation begins is much larger

than the value Co (y (t)) calculated from the

o analytic solution. This is not unexpected

since C2(y^(t)), which is independent of

time, is not equal to . Hence C2(y^(t),t)

is discontinuous at time zero. The total

time taken for the approximate solution to reach its steady state value depends on the

time step employed; this time is shorter if

the time step is smaller.

(S. R. Kraft" and M. G. Buehler)

4.4. Reevaluation of Irvin's Curves

Detailed experimental redetermination of the

relationships between resistivity and dopant

density in silicon (NBS Spec. Publ. 400-4,

p. 13) was begun. The relationships as re- ported by Irvin [12] are in wide use throughout the industry; the graphical forms

of these relationships are commonly known as Irvin ' s curves

.

Preliminary data were obtained using appropriate test structures of Test Pattern NBS-3

(NBS Spec. Publ. 400-12, pp. 19-22) fabricated in three wafers of n-type (phosphorus

doped) silicon. Bulk resistivity of the

original n-type portion of the wafers was determined from measurements on structure

3.17, the collector four-probe resistor

(sec. 7.3), corrected to 300 K [13]. Free

carrier density was determined from measurements on structure 3.8, MOS capacitor

over collector (sec. 7.4), or on structure

NBS Mathematical Analysis Section, Applied

Mathematics Division.

13
RESISTIVITY; DOPANT PROFILES

3.10, base-collector diode (sec. 7.5). The

results of these measurements are summarized

in table 3.

The measurements made on the collector fourprobe resistor were very repeatable on a given device. The data reported in the table

are averages for several devices in the same general area on the wafer.

The carrier density values from the MOS ca- pacitor were determined by the deep depletion method (sec. 6.3). These values have

an estimated uncertainty of ±5 percent. The

base-collector diode is located a little

over 1 mm away from the MOS capacitor. Carrier density values were determined from the

diode by the junction capacitance-voltage

(C-V) method (NBS Tech. Note 788, pp. 9-11).

A set of carrier density values from a diode

had an average standard deviation of less

than 1 percent. Because of the strong dependence of the calculated carrier density

on the area of the base diffusion, the

diameter of the diffusion for this processing run was measured by photomicrographic

procedures and found equal to the nominal

value (432 ym) within 1 pm.

The carrier density values from the junction

C-V method were used for computing the mobil

ity as this method is considered to be better characterized than the MOS procedure at this time. The mobility value calculated

for each wafer is based on the average value

of resistivity and carrier density. The mo- bility values for these wafers are about 5 percent larger than those calculated by the

equation of Caughey and Thomas [14] which

closely fits Irvin's curve for n-type silicon. However, these preliminary results

suggest that the mobility calculated from

the Caughey-Thomas equation agrees with the

experimentally determined value within the

estimated errors in the resistivity range

studied. (W. R. Thurber , R. L. Mattis,

R. Y. Koyama, Y. M. Liu, and M. G. Buehler)

Table 3 - Preliminary Resistivity-Carrier Density Data

for Phosphorus-Doped Silicon at 300 K

SI ice No. A0.27Ph-l Al .OPh-1 5200

p, Ci'cm 0.299±0.01

5

1 .035±0.005 5.59±0.21

n, cm-3(M0S) (2 12±0.19) X 10i& (4.76±0.20) X 1015 8.34 X lOi'+b

n, cm"^(jcn) (2 00±0.03) X iQie (4.82±0.13) X 1015 8.20 X IQi'-^h

p, cm2/V-s(exp) 1044±55 1251 ±34 1362

u, cm2/v-s(calc) 1000 1188 1287

% diff^ 4.4 5.3 5.8

^[ufexr.j - ufcalc j]/u(calc)

b . single device

14
5 . CRYSTAL DEFECTS AND C a N T A fll 'J A f! T S

5.1. Thermally Stimulated Current and

Capacitance Measurements

The parameters were varied one at a time over the following ranges

:

Analysis of thermally stimulated current and

capacitance measurements continued with em- phasis on the thermally stimulated current

response from the gold acceptor in an n-type

silicon MOS capacitor. For the analysis, it was assumed that only those defects between

Wjj^, the steady state inversion width and

the depletion width at the gnd of phase II

of the dynathermal response measurement (NBS

Spec. Publ. 400-1, pp. 16-19), and W^^, the

depletion width at the start of the dynathermal response are initially charged and

that defects between the oxide-silicon

interface and W^^^ are uncharged. In order

to achieve this condition, the MDS capacitor is cooled to low temperatures with the

depletion width held at W^^^ by applying

a bias voltage sufficient to drive the ca- pacitor into the inversion region; once the

low temperature is reached, a larger bias

which widens the depletion width to is

applied.

Detailed calculations were carried out with

procedures analogous to those used previously in analyzing a p''~n junction (NBS Spec.

Publ. 400-12, pp. 8-11).* The phase I current response of the MOS capacitor was found

to be somewhat less than that of a p^n junction with the same values of donor density,

N^, and gold density, N^, biased so that the

portion of the depletion width in which the

defects are not charged is the same. However, under such similar bias conditions

the current response of the MOS capacitor is

related to that of the p'^n junction in such

a way that the maximum in the dynathermal

current response occurs at the same temperature, T^ , for both structures,

le

The phase II current response of an MOS ca- pacitor depends on the heating rate, 3, the

ratio Nj/N , the ratio H = W^^^/W^^., and

Q t ill ill

a geometrical parameter G = e W^^^/e X

o Ilf s o where e is the dielectric constant of silis con, e is the dielectric constant of silio con dioxide, and X is the oxide thickness,

o The sensitivity of the phase II current

response to these parameters was studied

assuming that the temperature is raised

slowly enough that steady state conditions

prevail (NBS Spec. Publ. 400-8, p. 32).

0.2 K/s £ 6 1 10 K/s

5 < N,/N < 100 — (1 t —

0.1

0.1

H <_ 0.9

G < 10

When not being varied the parameters were

held at 6 = 10 K/s, N7n = 100, H = 0.2,

Q t and G = 1. The individual results are shown

in figures 5-8. As shown in figure 5, an increase in the heating rate causes T^^^,

the temperature of the current maximum, to increase. This is the same behavior as that

observed for the phase I current peak T^ . le As shown in figure 6, a decrease in the density of generation sites relative to the

background dopant- density N^, causes T^^

d i le to increase, for it takes higher temperatures (higher hole emission rates) to satisfy the inversion conditions at the oxidesilicon interface. Likewise, as shown in

figure 7, reduction of the number of generation sites by restrictiop of the initial

depletion width (increasing H) causes T^^^

to increase. Finally, as shown in figure 8, a decrease in the oxide thickness relative

to W^j^ (an increase in G) also results in an increase in T^^ . He

The relationship between T^^^ and heating

rate scaled by the factor F previously discussed (NBS Spec. Publ. 400-4, p. 33) was shown to be independent of these parameters

over all ranges except for N^/N^ < 20. It was also shown that for all values of H, F can be determined from measurable capacitances :

F = ^Ilf^IIe'^^IIf^o 'He

= )(C

C C

o If

(C

? - C ^) If li \r,

^Ile^^ Ilf ^li ^

where the capacitances are identified in

figure 9 which shows the dynathermal current

and capacitance response of an ideal, golddoped n-type MOS capacitor.

The complete analysis, summarized here,

is being prepared for publication as a separate report.

15
CRYSTAL DEFECTS AND CONTAMINANTS

200 240 280

TEMPERATURE (Kl 320

10'

10'

10

1^ 10'

10

10

T

' r

N„/N, = 100- 50-

200 240 280

TEMPERATURE IKI 320

Figure 5. Calculated reduced phase II current from gold acceptor defects in an n-type

silicon MOS capacitor as a function of temperature for N./N^ = 100, H = 0.2, G = 1,

and various values of 6

.

Figure 6. Calculated reduced phase II cur- rent from gold acceptor defects in an n-type

silicon MOS capacitor as a function of tem- perature for 6 = 10 K/s, H = 0.2, G = 1, and

various values of N,/N . d t

10'

10^ -

\ 10'

10'

10'

1

1 ' 1

'

w

C/"^^-^ 0.5

/'^-----..^^o.a

^~~~~0.1 I.I,

200 240 280

TEMPERATURE IKI 320

Figure 7. Calculated reduced phase II cur- rent from gold acceptor defects in an n-type

silicon MOS capacitor as a function of temperature for B = 10 K/s, N^/N = 100, G = 1,

and various values of H.

200 240 280

TEMPERATURE (K) 320

Figure 8. Calculated reduced phase II cur- rent from gold acceptor defects in an n-type

silicon MOS capacitor as a function of tem- perature for 6 = 10 K/s, N^/N = 100, H = 0.2, and several values of G.

16
CRYSTAL DEFECTS AND COriTAMIUAMTS

TEMPERATURE

Figure 9. Capacitance-voltage characteristic and dynathermal cxirrent and capacitance

response of an ideal gold-doped n-type silicon MOS capacitor.

Experimentally, the factor F was determined

from the thermally stimulated current and

capacitance response of a gold doped n-type

MOS capacitor (Device 2107.7, NBS Spec. Publ

400-1, p. 17). The results of the computa250 260 270 280 290 300 310 EMISSION TEMPERATURE [K|

Figure 10. Scaled heating rate appropriate

to obtain various emission temperatures during the phase II response from gold acceptor

defects in an n-type silicon MOS capacitor.

(Solid curves: theoretical; : experimental,

device 2107.7, N /N = 25, H = 0.27, G = 0.90.)

tlons are presented in figure 10 in the form

6/F against T^.^^. Experimental data from

device 2107.7 are also shown.

(W. E. Phillips and M. G. Euehler)

17
5 . OXIDE F I L [1 CHARACTERIZATION

6.1. X-Ray Photoel ectron Spectroscopy

Considerable attention was given to determining the origin of the "carbide" carbon

peak previously found on heated silicon

specimens (NBS Spec. Publ. 400-4, p. 42). A sequence of carbon (Is), oxygen (Is) and

silicon (2p) XPS scans on an air-stabilized

silicon specimen were performed as a function of heating condition. Successive tem- perature levels were maintained for whatever

period of time was necessary for outgassing

to effectively cease. The heating was done

in such a fashion that the total pressure in

the chamber never exceeded 5 x 10~^ Torr

(7 X 10~^ Pa) , starting from a base pressure

of 3 X io~5 Torr (4 x 10"^ Pa).

A quadrupole mass spectrometer was used to monitor the gas composition. During the initial heating, water was by far the major

gas present; at higher temperatures, first

hydrogen and then carbon monoxide became

prominent. The evolution of carbon monoxide

was accompanied by lesser amounts of hydrogen and water. After the specimen had been

heated to approximately 1000°C, allowed to cool and then reheated, a short initial outgassing of hydrogen was observed, followed

by an intense evolution of carbon monoxide.

No evidence of an abundant hydrocarbon mass peak was observed at these higher temperatures. At temperatures below 400°C several

unidentified mass peaks were present which

could be due to outgassing from the silicon

specimen, the molybdenum electrical contact

spring in the specimen holder, or both.

Measurements of the silicon surface during

heating indicated large amounts of carbon

and oxygen with some silicon (di)oxide

(Si^02), figure 11a. Mild heating to 870°C,

figure lib, caused the carbon peaks to decrease. The oxygen signal appeared to increase, presumably because the overburden of

carbon containing material was removed.

Heating the specimen to 930°C, figure 11c,

caused a profound change in the spectra. Most of the oxygen was lost, the silicon

(di)oxide peak practically disappeared, and

the smaller remaining carbon peak shifted to higher kinetic energies. At 960°C, figure

lid, there appeared a further loss in oxygen, a further shift in the carbon peak to higher kinetic energies characteristic of

"carbide" carbon (Si£) and the appearance

of a new shoulder on the Si(2p) peak at the

position expected for silicon as silicon

carbide (SiC) . The specimen was then allowed to cool overnight. Spectra taken the

next day before heating, figure lie, showed

that a considerable amount of low kinetic

energy carbon and some additional oxygen

had been deposited. On heating to 960°C,

figure llf, most of the elemental carbon

was lost, some seemingly converted to car- bide as manifested by the growth of the

"carbide" carbon (SiO and silicon (SiC)

peaks. The intensity of the oxygen peaks

was also observed to diminish until at 1000°C oxygen could not be seen on the surface, figure llg. Although there was no apparent change in the total amount of car- bon present on the surface, both a narrowing of the carbide carbon peak and a further

growth of the carbide silicon peak were ex- perienced. In an additional experiment, the

silicon specimen was bombarded with argon to sputter all carbon from the surface and then

annealed at ~950°C. After allowing the specimen to sit overnight in the vacuum, a con- tamination layer appeared which was similar

to that which appeared after the specimen

was cooled overnight after heating to 960°C

(fig. lie) . When the specimen was reheated

to 960°C silicon carbide was again produced

(cf fig. llf). The conclusion is that most,

if not all, of the silicon carbide that

forms results from the interaction of residual carbon containing gases in the spectrometer with the silicon surface.

The large surface carbon to surface oxygen

ratio observed before heating is too large

to be due to a simple deposition of carbon

monoxide, although carbon monoxide was the

only carbon containing gas indicated by the mass spectrometer. One possibility is that

the carbon monoxide dissociates on the silicon with a loss of oxygen from the surface.

Another is that the hydrogen which evolved

during the initial stages of reheating is not only the result of thermal desorption

from the silicon and/or molybdenum surfaces

but could be due to a cracking of some adsorbed hydrocarbons such as methane, ethane,

ethylene, or even acetylene. Thus, although

the exact gaseous species responsible for

the formation of silicon carbide has not yet

been identified, it does seem clear that the

majority of the carbide comes not from the

bulk of the silicon but instead is a reaction product with an as yet unidentified re- sidual gas in the spectrometer.

ClI. E. Erickson", A. G. Lieberman,

T. E. Madey-, and J. T. Yates, Jr.-'O

UBS Surface Processes and Catalysis Section, Physical Chemistry Division.

18
OXIDE FILM CHARACTERIZATION

lev

Si 1—1 C,0 hJ^Xn

Cn /

ci/ y \

^' CARBON / \_

OXYGEN /

SILICON / \

KINETIC ENERGY |eV)

a. Unheated specimen.

CARBON

KINETIC ENERGY [eV] c. After heating to 930°C.

CARBON

OXYGEN

SILICON ^

KINETIC ENERGY |eV|

e. After cooling to room temperature in vacuum

.

KINETIC ENERGY leV] After heating to 870°C.

Si

I

CARBON ^

Sic

OXYGEr^ ' "--^/ \ SILICON^

KINETIC ENERGY [eV]

d. After heating to 960°C.

SiC

SI

i CARBON^

OXYGEN _— / \

SILICON —'sic \

KINETIC ENERGY |eV| f. After reheating to 960°C.

SI

I

CARBON ^

OXYGEN

^SILICON /' \

I'C

KINETIC ENERGY |eV|

g. After heating to 1000°C.

Figure 11. Metamorphoses of carbori Is, oxygen Is. and silicon 2p photoelectron peaks upon

heating. (The energy scale covers 960 to 972.5 eV for the carbon spectrum, 710 to 722.5

eV for the oxygen spectrum, and 1130 to 1155 eV for the silicon spectrum.)

19
OXIDE FILM CHARACTERIZATION

6.2. X-Ray Dose in Electron Beam

Evaporators

Electron beam evaporation of aluminum in vacuum is widely used in the metallization

process for fabricating semiconductor devices. Typically, the aluminum, held in a water cooled crucible, is melted by an electron beam with a beam energy and beam current of 10 keV and 0.5 A respectively. The

electron bombardment, in addition to evaporating the aluminum, generates characteristic x-rays and bremsstrahlung radiation (a

continuous spectrum of photons with energy

0 < E < electron beam energy) at the alumi- num surface. . The wafers being metallized

are also exposed to some of this radiation.

The effect of the low energy radiation produced in the metallization process on the

thermal oxides of MOS devices has been re- ported [15]. MOS transistor threshold voltage shifts of typically several volts were

observed after aluminum evaporation. These

shifts in threshold voltage were then re- moved by heating the metallized wafers to temperatures of 400°C or higher for short

periods of time. However, a residual effect

which affected the future radiation sensitivity of the device was observed in this

experiment

.

The purpose of the work reported here was to examine a measurement technique for determining the magnitude and characteristics of

the radiation impinging on wafers during the

metallization process by electron beam

evaporation.

Using published data, an estimate of the

energy deposited during metallization can be

made. The yield, Y, of x-rays emitted in

the backward direction (laboratory angle

0^ = 180 deg or 120 deg) from aluminum

bombarded by 10 keV electrons impinging nor- mally to the surface (target angle a = 0 deg) is 2.4 x 10""* photons per steradian*

electron [16]. These x--rays have an energy

of 1487 eV (2.382 x 10"^^ J). In an electron beam evaporator, the solid angle, Q,

subtended by a 2 inch (5 cm) diameter wafer

is approximately 10"^ sr; the exposure time

may vary between 100 and 300 s depending on

the evaporation rate and the thickness of

metal film to be deposited. The energy AE

(joules) deposited in a wafer by the alumi- num x-rays produced in this process (in

joules) can be calculated from

AE = YItf^E(K ) (6) a where I is the beam current (amperes), t is

the exposure time (seconds), and E(K^) is

expressed in electron volts. For an exposure time of 200 s and a beam current of

0.5 A, the energy deposited in the wafer is

approximately 0.36 J. The energy deposited

due to the continuous bremsstrahlung radiation is not included in this estimate since

precise data are not available for 10 keV

electrons interacting with thick aluminum

targets; as will be shown later, the bremsstrahlung dose may be of approximately similar magnitude to that of the radiation.

The energy deposited must be corrected for

the shielding effect of the metal film on

the wafer; as this film becomes thicker, it

creates a protective shield against the

radiation

.

A preliminary experiment* to measure the ra- diation field present during the operation

of an electron beam evaporator was performed

using calcium fluoride thermoluminescent

dosimeters (TLDs), 1/32 in. (0.79 mm) thick

and 1/8 in. (3.2 mm) square. Ten TLDs were

covered with Kaptont foils of varying thickness to avoid direct aluminization; for the

purpose of this experiment the electron beam

current was reduced to about 25 percent of

the value normally used for metallization.

These measurements yielded an absorption

curve showing at least two components of the

radiation field present during metallization

in an electron beam evaporator; a short

range component corresponding to 1.487 keV

aluminum K characteristic radiation and a a

long range component corresponding to the

continuous background. The evaporator parameters for this experiment are given in

table 4 and the absorption curve is shown

in figure 12.

This experiment was performed with the as- sistance of Dr. M. Ehrlick, NBS Applied

Radiation Division, who supplied the TLDs and the measuring equipment.

This material is identified in this report in order to specify adequately the

experimental procedure . Such identification does not imply recommendation or en- dorsement by the National Bureau of Standards , nor does it imply that the material

is necessarily the best available for the

purpose

.
OXIDE FILM CHARACTERIZATION

10

C9

0.1

b 1

1 1 1 1 1 =

4 EVAPORATOR fright scale] _

5 ACCELERATOR |lett scale] -

- \

- 1 11111 =

D 25 50 -75 100 125 150

100

10 ^

KAPTON THICKNESS [^m]

Figure 12. Absorption of x-rays generated

by bombarding aluminum with 10-keV electrons.

Table 4 — Calibration of TLDs using the

Backward Radiation from Thick Aluminum

Target Bombarded by 10 keV Electrons

ri rrpl PVri tor

Beam energy, keV 10 10

Beam current, A 0.15 2 X 10-5

Exposure time, s 60 500

e[_, deg 120 180

a, deg 0 0

n, sr 4.8 X 10-5 7.9 X 10-5

TLD reading, pC 135 4

To convert the TLD readinp.s to absorbed

energy requires a calibration factor. The

TLDs were calibrated'^ using the radiation

emitted at 180 deg when 10 keV electrons

from the NBS constant potential accelerator

impinged normally (a = 0 deg) on a thick

aluminum target. Using various thicknesses

of Kapton as an absorber, an absorption

curve similar to that resulting in the evaporator was measured. The results are also

shown in figure 12. Tlie zero-thickness

reading was approximately 4 ijC. From eq (6)

with Y = 2.4 X 10"'* photons per steradian*

electron, the total energy deposited is

2.8 The calibration constant for the

TLDs is therefore 0.07 yJ/yC. The total

energy deposited in the TLD in the evaporator corresponding to an extrapolated zeroKap ton- thickness reading of 135 yC is

9.5 yJ. If this is converted to the normal

metallization conditions for a 2 in. (5 cm)

wafer, the energy deposited on the wafer

would be 0.02 J. Since this value does not compare favorably with the previously calculated value of 0.36 J, the discrepancy

must be investigated. However, either of

the values leads to a large radiation dose

if the energy is uniformly incident on a film of silicon dioxide 100 nm thick on a

2 in. (5 cm) diameter silicon wafer. From

cross-section data [17] the fraction of incident energy absorbed in the oxide can be

calculated to be 2.4 percent. Therefore,

the absorbed dose in the oxide is about

1.8 X io'* J/kg (1.8 X 10^ rads(Si02)) for

incident energy of 0.36 J and about

10^ J/kg (10^ rads(S102)) f or incident en- ergy of 0.02 J. This estimate does not include the bremsstrahlung contribution.

The shielding effect of the deposited alumi- num is rather small for the aluminum K ra- a diation since a 1 ym thick aluminum film

transmits about 96 percent of the incident

1.5 keV photons. The low energy portion of

the bremsstrahlung continuum, however may be

absorbed by the deposited aluminum. Since

the photon distribution with energy in the

bremsstrahlung continuum is not known, it is

difficult to assess the dose absorbed in the

oxide. However, it seems likely from the

data obtained in this preliminary experiment

that an additional dose of -approximately

similar magnitude to that of the radiation arises from the bremsstrahlung continuum. (S. Mayo)

The calibration was performed in collaboration with Dr. C. E. Dick., NBS Applied

Radiation Division.

21
7 . TEST PATTERNS

7.1 . Sheet Resistors

As part of a study of the structures on test pattern NBS-3 (NBS Spec. Publ. 400-12, pp. 19-22), an analysis was undertaken of the

four base sheet resistors (devices 3.11,

3.22, 3.28, and 3.30). The analysis included an intercomparison of sheet resistance

values which showed that van der Pauw structures [18] whose active areas differ by

forty times yield values that generally differ by less than 1 percent. In addition,

the width of the base diffusion window as determined by electrical measurements on van

der Pauw and bridge structures was found to agree with measurements made on photomicrographs. The electrical measurements are sensitive to width changes that are smaller

than 5 pin. (0.12 ym) . These measurements

are important in the manufacture of semiconductors because of the significance of control of dimensions in designing and fabricating devices.

Base sheet resistors were fabricated in nominally 5 Q'cm, n-type (111) silicon substrates on which a 300 nm thick oxide was

grown in steam at 1100°C. Base diffusion

windows were etched in the oxide using a buffered hydrofluoric acid solution for

3 min. The boron nitride, predeposition

base diffusion was at 965°C for 25 min in

dry nitrogen. After a deglaze in 10 perc^ent

hydrofluoric acid solution, the base drivein diffusion was at 1100°C for 18 min in wet

oxygen, followed by 40 min in dry oxygen,

followed by 15. min in dry nitrogen. After

a subsequent phosphorus emitter diffusion at 1000°C for 20 min and a reoxidation at 925°C

for 45 jnin. followed by contact window opening and aluminum metallization, the base

sheet resistance was about 175 Q/D and the

junction depth as measured by the angle lap

and stain method [19] was about 2.1 ym.

Line drawings of sheet resistors 3.22 and

3.28 are shown in figure 13. The bridge

structure (3.28) was designed where possible

in accordance with the ASTM standard [20]

which requires that W ^ 3D, Lg ^ 5W, and

B _> 2W. In addition, the following are re- quired to minimize lateral diffusion and

over-etch effects: L > lOX. , A > 5X., and - J - J C > 5X., where X. is the junction depth.

Analysis of the potential distribution in

the van der Pauw structure (3.22) by means

of a conducting paper analog indicated that

it is necessary to have S ^ 3D and A ^ S/2

to insure that the error in the calculated

resistivity is less than 1 percent. Both

sheet resistors 3.22 and 3.28 have rectilinear boundaries to facilitate reproduction

by computerized pattern generation.

The sheet resistance was measured by the dc

four-probe method. Current was passed be- tween contacts Ii and I2, shown in figure

13, and the potential between contacts Vi and V2 was measured by means of a digital

voltmeter with 1 yV resolution. The linearity of the current-voltage characteristics

was studied for various values of current.

It was established that a current of 100 yA

is within the linear range of these resistors and produces a stable, noise-free voltage reading greater than 1 mV. In the case

of van der Pauw structures, an additional

measurement must be made with the contact

positions rotated 90 deg. In every configuration, the current is reversed to confirm

the linearity of the current-voltage relationship. Measurements were made on the same wafer as quickly as possible so as to minimize room temperature drift effects.

For resistors 3.22 and 3.28 measurements

ll V2 I2 A

w

T

a. Bridge structure (3.28). The centerto- center pad spacing is 6 mil (C.15 mirO.

b. Orthogonal van der Pauw structure (3.22).

The center-to-center pad spacing is 8 mil

(0.20 mm).

Figure 13. Scaled line drawings of base

sheet resistor structures on test pattern

NBS-3 showing critical dimensions.

22
TEST PATTERNS

were made in room light and with grounded

substrates. For resistors 3.11 and 3.30,

measurements were made in the dark using

ungrounded substrates. These conditions are necessary when significant junction leakage

exists as in resistor 3.30 which has a junction area significantly larger than that of

resistor 3.28. The field plate of resistor

3.11 was shown to have negligible influence

on the measured sheet resistance; it was permitted to float during the measurements.

For the van der Fauw structure, the sheet

resistance was computed from [18]

Rg(VDP) TJ_ V

In 2 I (7)

VDP

where the voltage current ratio is averaged

for both directions of current and for both

contact orientations. For the bridge structure the sheet resistance is computed froiTi W + aX R^(B) =

I (8) B

where L can be taken equal to the mask dimension L(mask) because it is not affected

by lateral diffusion or over etching. How- ever although the width W is greater than

the mask dimension:

where W accounts for over etching and aX

oe <^ J (with a = 0.3 and X^ the junction depth) ac- counts for lateral diffusion [21], W is frequently taken as W(mask)

.

Sheet resistance values as a function of position across a wafer are shown in figure

14. The sheet resistance values for the

bridge structure were calculated from eq (8)

using the nominal mask dimensions, W = W(mask) = 1.5 mil (38 ym) and L = L(mask) = 6.0 mil (152 ym) . The general shape of all

the curves is the same, but the sheet resistances measured on the three van der Pauw

structures are tightly clustered while the

value measured on the bridge structure is

significantly lower. This result suggests

that the true value of W is significantly

greater than W(mask)

.

In order to test the sensitivity of these

resistors to over etching of the base diffusion window, etch times were chosen so that one wafer was etched for 3 min, another

wafer for 6 min, and a third wafer for 9 min. The sheet resistance values shown in

figure 15, were computed as before using the

mask dimensions for W and L in computing

sheet resistance from measurements on the

bridge structure. The results show that the

W = W(mask) -I- aX. + W (9) 180

180

160

-600 -200 0 200 600

DISTANCE ACROSS WAFER Imil)

Figure 14. Sheet resistance as a function

of position along a wafer diameter. (van

der Pauw structures: , 3.30; O, 3.22; A,

3.11; Bridge structure: , 3.28.)

150

600 -200 0 200 600

DISTANCE ACROSS WAFER [mill Figure 15. Sheet resistance as a function

of position along the diameter of wafers

etched for different times. (A, , O: van

der Pauw structure (3.22); A, , •: Bridge

structure (3.28); A, : 3-min etch; , :

6-min etch; O, •: 9-min etch.

)

23
TEST PATTERNS

measurements on the bridge structure (3.28) are sensitive to the time used to etch the

base diffusion windows while the measurements on the van der Pauw structure (3.22) are not.

Equating Rg(B) and R^(VDP) and combining eqs

(7)-(9), with L = L(mask) leads to

to wafer with a tolerance better than

±20 yin (±0.5 ym) . Pairs of like boundaries, labeled A and C and D and E in fig- ure 17, are such that the degree of etching

does not affect the distance between such

boundaries. The distance L in eq (10) is

a distance between like boundaries and therefore can be taken directly from the photomask dimensions.

L(mask) R (VDP) (10)

Figure 16, demonstrates the effect of increased etch time on the width of the base

diffusion window as determined from measurement of R (B) and R (VDP). The measurements

s s were repeatable to within the range covered

by the open circles on the figure.

As an independent check of the diffusion

window widths calculated from the electrical

measurements, measurements were made directly on photomicrographs of various test structures. An optical microscope with a 40X objective was operated in the Nomarski

differential interference contrast mode.

The magnification as measured on the photomicrograph was 585X. From these photomicrographs it was established that test structure dimensions determined from "like

boundaries" are transferred from photomask

1.70

-600 -200 0 200 600

DISTANCE ACROSS WAFER (mil) Figure 16: Width of base diffusion window

as measured electrically using eq (10) with

X. = 0.083 mil (2.1 ym) (O) and from photo-

-'micrographs(D) along the diameter of wafers etched for different times, (A: 3-min

etch; B: 6-min etch; C: 9-min etch.)

The boundaries between oxide levels had a finite width as shown in figure 17. Since

it was assumed that the edges of the base

diffusion window occurred at the centers of

the appropriate transition regions, the distance between edges B and C corresponds to the width of the base diffusion window. In measuring this width, the distance between

edges A and C was taken from the photomask

dimensions. A scale was placed on the

photomicrograph at an angle such that the

distance between A and C was a convenient

multiple of the actual dimension. The distance between C and B could then be read

directly from the scale. The values obtained are plotted as open squares in figure

16. The error bars shown correspond to one- fourth the distance between scale divisions.

Both sets of values are in good agreement

and are larger in all cases than W(mask)

.

These results illustrate that the electrical

width measurements are sensitive to width

changes smaller than 5 yin. (0.12 ym) . In addition they can be made quickly and at low

cost using available automatic equipment.

Thus , these measurements are important in

the manufacture of semiconductors because

of their potential use as process control

and device design vehicles. (M. G. Buehler)

BASE

DIFFUSION

OXIDE -J

f SILICON-'

Figure 17, Expanded schematic views of the

bridge sheet resistor structure illustrating

the measurement of L and W from the photomicrographs. (The boundaries, shown cross- hatched, are exaggerated in width for

clarity.

)

2A
TEST PATTERflS

7.2. Square Array Collector Resistor

Structure 3.17 of test pattern NBS-3 (NBS

Spec. Publ. 400-12, pp. 19-22) Is a square

four-probe array designed to measure the

resistivity of the undiffused or collector

region of the pattern. The probes are narrow pipes of undiffused material surrounded

by a base diffusion of opposite type as shoim in figure 18. Emitter areas are dif^

fused into each pipe to give a low resistance contact to the collector material.

The measurement consists of passing current

between two adjacent probes, Ii and I2, and

measuring the voltage between the other two probes, Vi and V2. Assuming the substrate

to be semi- infinite in extent, the resistivity p is determined from [22]

P =

2 TT s 2-/2V V Y

= 10.726 s Y

a. Photomicrograph. (Magnification: '>-195X . )

where s is the probe spacing, V is the measured voltage, and I is the current. The

voltage is measured for both directions of

current and averaged. Also for accurate results it is necessary to rotate the electri-,

cal connections ninety degrees and average

the two sets.

The pipe regions are protected from the 1 to

2 ym deep base diffusion by squares in the

base mask which are 0.25 mil (6.3 ym) on a side. However, the pipe dimensions are re- duced by lateral diffusion of the base, and

the effective cross sectional area of the

pipe is further reduced by the depletion re- gion associated with the base-collector

junction. This causes a large voltage drop

along the pipe even at low currents. Above

some current (which depends on resistivity

since both the lateral diffusion and the

depletion width increase with increasing

collector resistivity but can be quite low

because of the large voltage drop) the

emitter-base junction breaks down, the measured voltage saturates, and the calculated

resistivity is below the actual value. For each wafer, a current large enough to provide a measurable'voltage but small enough

to avoid breakdown is chosen on the basis of

preliminary measurements.

The probe spacing used in the calculations

is the center-to-center distance of 2.250 mil

(57.15 ym) between the collector pipes as taken from the design dimensions. The four

probe spacings were checked by measurements

on a photomicrograph of the base mask and

found equal to the design value within about

b. Photomicrograph of pipe region,

(Magnification: 'v^675X.)

I I COLLECTOR REGION Zmm EMITTER REGION BASE REGION

I 1 OXIDE ALUMINUM

omnnini gold

c. Schematic cross section, scaled

in horizontal direction only.

Figure 18. Square array collector

resistor structure.

25
TEST PATTERNS

Table 5 - Comparison of Resistivity Measured by Square Array Test Structure

with Resistivity Measured by Four-Probe Method Before Processing

Slice No. Four-Probe"=^ Square Array % diff^^

A0.27Ph-l 0.287±0.010 0.276±0.019 -3.83

Al.OPh-1 1.013±0.012 1.007±0.030 -0.59

5200 5.34±0.08 5.19±0.12 -2.81

^Before processing.

b[( Square Array )/( Four-Probe ) - 1] x loo.

0.5 percent. Based on calculations by Ulilir

[22], the error due to finite wafer thickness is less than one percent for the wafers

used which are typically about 10 mil (0.25

mm) thick and have a conducting back side.

Measurements were made on three n-type

wafers being used for the reevaluation of

the resistivity-dopant density relationship

(sec. 4.4.). Before processing, the resistivity of each wafer was measured along

two perpendicular diameters by the fourprobe method [7] corrected for off-center

position [23]. After the test pattern was

fabricated, resistivity measurements were

made on two or more square-array structures

located near the center of the wafer. The

results are summarized in table 5 . The

variability indicated for the four-probe

measurements is the sample standard deviation of the values at the center of the

wafer and at four points 200 mils (5.1 mm)

from the center in each direction. The variability indicated for- the square-array measurements is the sample standard deviation

of measurements made on the structure located nearest to the center of the wafer

and three, four, or one adjacent devices located on perpendicular diameters for wafers

A0.27Ph-l, Al.OPh-1, or 5200, respectively.

Previous experience with material in this

resistivity range has shown that processing

does not significantly change the resistivity. (W. R. Thurber,

Y. M. Liu, and M. G. Buehler)

19, consists of a central gate electrode,

Gi, 15.0 mil (381 ym) in diameter over a uniform layer of oxide which is typically

0.3 to 0.5 ym thick. A circular emitter

diffusion outside the gate electrode provides a heavily doped region of the same conductivity type as the collector which

serves together with a metal ring, G3, as the topside collector contact. Between Gi

and G3 there is a circular field plate, G2,

4.5 mil (114 ym) wide, which is separated

from Gi by 0.5 mil (13 ym) and extends over

the edge of the emitter ring. A backside

collector contact is also provided.

Typical use of this structure consists of

measuring the capacitance, C, as a function

of the applied bias voltage, V, on Gi, which

is scanned uniformly from accumulation to inversion and back. When using a three ter- minal capacitance bridge, the gate Gi is the

"HI" electrode and either G3 or the backside

contact is the "LO" electrode; if the backside contact is used, G3 is left floating,

and vice-versa. The field plate, G2, is

biased according to the needs of the situation. For an ?t-type MOS capacitor, G2 is

usually grounded since the surface is accu- mulated at zero bias. For a p-type MOS

capacitor it is necessary to bias G2 with

sufficient negative voltage to cause accumu- lation at the surface. This is illustrated

in figure 20 which shows C-V characteristics

for a p-type MOS capacitor under different

bias conditions on G2.

7.3. MOS Capacitor Over Collector

Structure 3.8 of test pattern NBS-3 (NBS

Spec. Publ. 400-12, pp. 19-22) is an MOS

capacitor over the undiffused or collector

region of the wafer. This structure can be

used to measure the dopant density in the

wafer. The structure, illustrated in figure

At a bias on G2 more negative than the flatband voltage, V^^ (-18 V in this case), the true high frequency C-V characteristic is

obtained as illustrated by the curve labeled

V = -20 V in the figure. From this curve,

\jZ. it is possible to derive the dopant density

within a depletion depth of the surface of

the collector region by means of the usual

26
TEST PATTERNS

a. Photomicrograph. (Magnification: 'v90X . )

C - C . method (NBS Spec. Publ. 400-4, max mm ' pp. 37-38).

If the rate of scanning V is increased so

J. that it is high enough to prevent minority

carrier equilibrium, the deep depletion

characteristic (C^^ in fig. 20) is obtained.

From this curve, the dopant density characteristic of the bulk of the undiffused collector region can be determined by means of

the dynamic MOS C-V method (sec. 4.2.).

(R. Y. Koyama and M. G. Buehler)

O

O

O

1.0

0.8

0.6

0.4

1 1

1 p-MOS -

VG2=+2oy_

Vg2= -20y_

Vfb

1

1 1 -20 10 0

Vgi (volts)

10 20

Figure 20. Typical high-frequency

capacitance-voltage characteristics of a p-type silicon MOS capacitor showing the

effect of surface inversion around the

periphery (V^^^ " +20 V), the true equilibrium characteristic (V^^ ~ "20 V), and

a non-equilibrium, deep depletion characteristic (Cj^). (C = 12.4 pF,

o fb

-18 V.

)

7.4. Base-Collector Diode

Structure 3.10 of test pattern NBS-3 (NBS

Spec. Publ. 400-12, pp. 19-22) is a basecollector diode from which the dopant density in the undiffused or collector region

of the pattern can be measured by the junction C-V method. The structure, which is

illustrated in figure 21, consists of a 17.0 mil (432 ym) diameter diffused base

region of conductivity type opposite to that

of the collector to form a p'^n or Ti^p junction. The junction depth is typically 2 pm. Contact to the diffused region is made by means of an aluminum ring and disc configuration evaporated into windows cut in the oxide. Contact to the collector region is made

either by means of a doped gold layer alloyed

to the backside of the wafer or an emitter

ring diffusion on the topside of the wafer.

The emitter ring, which is of the same con- ductivity type as the collector, also serves

to limit the formation of surface channels

outside the active region of the structure.

Between the base diffusion and the emitter

ring there is a circular aluminum electrode

(gate) over the oxide to control the surface

near the junction (NBS Tech. Note 788, pp. 9-11)

.

When capacitance-voltage (C-V) measurements

are being made, the device is connected in

the manner shown in figure 21b. The gate is

held at ac ground and biased by a low

impedance voltage supply at some suitable

voltage such as the flat band voltage. The

10 kS^ series resistor serves to limit the

current in event the gate is shorted to the

collector. Bias is applied to the p-n junc27
TEST PATTERNS

tion through the capacitance meter. The

10 kfi series resistor serves to limit the

junction current when breakdown occurs. The

capacitance is read using a digital voltmeter connected to the analog output of the meter. A second digital voltmeter is used

to read the junction bias voltage. A dopant

density profile is then calculated from the

C-V data using a BASIC computer program

which includes appropriate corrections for

peripheral effects and for back depletion

into the diffused layer [24].

(R. L. Mattis and M. G. Buehler)

When the CCD is operated as a capacitor, the

capacitance is measured between the phase

three electrodes, connected to the aluminum

interconnect, and the substrate. The equivalent circuit model for this configuration

consists of the following five capacitors

connected in parallel:

1. Thin oxide/p~ substrate

2. Thick oxide/p~ substrate

3. Thin oxide/p'^ channel stop diffusion

4. Thick ox±de/p^ channel stop diffusion

5. Thick oxide/n''" interconnect diffusion

7.5. Charge-Coupled Device Test Pattern

This study was undertaken to investigate the

applicability of the charge-coupled device

(CCD) as a test structure for use in semiconductor process control. Before the CCD

is considered for use as a process control

tool, the parameters measured from the CCD

must be correlated with those measured by

other, better known, devices such as MOS

capacitors and MOS transistors. During this

quarter a model was developed for the CCD

operating as an MOS capacitor and comparisons of characteristics derived from measurements on a CCD were made with characteristics derived from measurements on MOS

capacitors and MOS transistors fabricated

on the same wafer (NBS Spec. Publ. 400-8,

pp. 26-27).

These capacitors can be identified in the cross sectional view through a phase three

electrode shown in figure 22.

The MOS capacitors formed over the p~ substrates are voltage sensitive, but those

formed over the p"^ and n"'" diffusions are assumed to be insensitive to voltage and

have capacitance values taken as the oxide

capacitance. It should be noted that the

MOS capacitor formed over p~ substrates includes the capacitance contributed by the

bonding pad. Because the ri^ phase one and

phase two interconnect diffusions are grounded (NBS Spec. Publ. 400-12, pp. 22-23),

the capacitance associated with these capacitors is eliminated from the measurement.

The CCD can also be operated as a capacitor

by using the input gate electrode. In this

28
TEST PATTERNS

BONDING PHASE 3 ELECTRODE ALUMINUM PHASE 3 INTERCONNECT

THICK OXIDE

THIN OXIDE

CHANNEL

STOP

CHANNEL PHASE 1 CHANNEL PHASE 2 CHANNEL

STOP INTERCONNECT STOP INTERCONNECT STOP

p" SUBSTRATE Figure 22. Cross sectional view through phase 3 electrode of CCD test structure,

configuration, the model must include the

first four capacitors listed above, but the areas of each are different.

The analysis of the MOS capacitance-voltage

characteristics of the CCD (NBS Spec. Publ.

400-12, pp. 23-24) using the above equivalent circuit model involves evaluating the area of the metallization over each region,

the thickness of the thin and thick oxides,

and the p" substrate dopant density. The area of the metallization over each region

was determined from the artwork supplied to

the photomask manufacturer; the procedure

ignores lateral diffusion and over-etch

effects (sec. 7.1.). The area calculated

for each of the capacitors identified above

is given in table 6 along with the areas of

the two MOS capacitors which were used in

the subsequent correlation studies.

The two oxide thicknesses were determined

from two capacitance measurements on the CCD

in the accumulation region, one using the

phase three electrodes and the second using

the input gate. These measurements provide

capacitance values for two equations containing the two unknown oxide thicknesses. To determine the p~ substrate density the CCD was connected as an MOS capacitor biased into

inversion. Care was taken to apply enough

bias so that both thin and thick MOS capacitors were inverted. To obtain the thin oxide inversion capacitance, the three other

capacitances described above were subtracted

from the measured inversion capacitance using

the appropriate areas and oxide thicknesses.

The substrate dopant density was determined

using the thin oxide capacitance, the thin

oxide inversion capacitance, and the strong

inversion approximation (which states that

the onset of inversion occurs when the surface potential is twice the difference between the bulk and intrinsic Fermi potentials.)

The results of these measurements on one 32-

bit circular CCD (device 2) on wafer 1 are summarized in table 7. For comparison, av- erage values of dopant density and oxide

thickness obtained from measurements on about 15 thin oxide MOS capacitors (device

Table 6 - Metallization Area

Device MOSCAP MOSCAP CCD (PHASE 3) CCD [INPUT GATE)

Device Number 21 13 2 2

Thin Oxide p- 6.59 X 10"'+ cm2 7.39 X 10"5 cm2 2.42 X 10-6 cm^

Thick Oxide p- 2.06 X 10-3 crTi2 2.90 X 10''+ 2.09 X lO-'*

Thin Oxide -p^ 2.44 X 10"^

Thick Oxide 1 .65 X 10-"+ 1 .28 X 10-6

Thick Oxide r& 6.33 X 10-5

29
TEST PATTERNS

Table 7 - MOS Capacitor Parameters (Wafer 1)

Device

Device Number

CCOa

2 MOSCAPb21

MOSCAPl^

13

Substrate Dopant

Density, cm"^ 1.6 X 10^6 (9.4±0.6) X 1015 (8.5±0.4) X 1015

Thin Oxide

Thickness, A 1200 950±30

Thick Oxid^ „ Thickness, A 7770±20

Single measurement.

'Mean value ± one sample standard deviation of measurements on about 15 capacitors of each type.

Table 8 - MOS Transistor Parameters (Wafer 3'

Device

Device Number

MOSFEt

26 CCD

2

Operation: Linear Region

Vy, V

Xq, a (Thin Oxide)

W/L

yp, cm2/V-s

0.26

-950^

-31 .4c

-590 —

0.19

960^

-^0.044 —

]

-^590

Operation: Saturation Region

Vy, V

Xq, a (Thin Oxide)

W/L

Pn, cm2/V-s

0.11

950^

31 .4^

-660

1.1 -950^

0.044-

-440

^Determined from measurements on device 13 on Wafer 1. ^An average value where depletion in the p" region under the thick

oxide was not included.

"^Calculated from the photomask dimensions, W(mask) = 10.0 mil (254 \im) and L(mask) = 0.400 mil (10.16 ym), corrected to account for lateral

diffusion; end effects were ignored.

30
TEST PATTERNS

13) and thick oxide MOS capacitors (device

21) on wafer 1 are also listed in the table.

Threshold voltages and channel mobilities

were determined from measurements on a 32-

bit circular CCD (device 2) (on wafer 3) operated as an MOS transistor and correlated

with similar quantities determined from measurements on an MOS field effect transistor

(device 26) on the same wafer. The operation of the 32-bit circular CCD as an MOS

transistor consists of holding all electrodes and the output gate at a dc potential

(45 to 50 V) and stepping the input gate (1 to 10 V) . Oscilloscope traces were obtained

by this method and parameters determined in

the linear and saturation regions using the

mathematical relations presented previously

(NBS Spec. Publ. 400-12, pp. 23, 25).

The results of this analysis are shown in

table 8 where the arrows indicate how re- sults were combined to obtain the channel

mobilities. For the MOS transistor, the

channel mobilities in both the linear and

saturation regions were calculated from the

appropriate equations; the oxide thickness

was assumed as the value found from measurements 'on the MOS capacitor (device 13) on wafer 1, and the W/L ratio was calculated

from the photomask dimensions with L re- duced by 2 pm and W increased by 2 ym to allow for lateral diffusion (end effects were ignored)

.

The W/L ratio for the CCD was obtained using

the channel mobility of the MOS transistor

operating in the linear region and the oxide

thickness determined from measurements on

the CCD connected as an MOS capacitor. This

ratio was found to be close to the design

value of about 0.01. This value of W/L and

the same value of oxide thickness were used

to calculate the channel mobility for the

drain current in the saturation region.

(I. Lagnado" and M. G. Buehler)

31

Naval Electronics Laboratory Center, San

Diego, California. Work conducted under

NBS Order No. 502498.
8. PHOTOLITHOGRAPHY

8.1. Automated Photomask Inspection

Detailed analyses were begun of the stateof-the-art technologies previously identified (NBS Spec. Publ. 400-4, pp. A9-50) as applicable to automated photomask inspection. The objects of these analyses are to assess the soundness of the physical principles on which a specific technology is

based, to identify the limitations of each

technology in the ability to detect photomask defects and the time required to do

this, and to identify areas where improvements could be made.

The smallest visual defect dimension to be

detected was chosen to be 2 ym. This dimension was chosen since defects of this size

or larger may be expected to print on a wafer while smaller defects generally will

not print [25]. The precision of registration of successive photomask functional patterns was chosen to be ±0.25 ym or less

which is the registration criterion that is now widely used in the industry [26]. Both

surface imperfections and surface flatness were considered in assessing the applicability of a technology to photoplate inspection.

The first technology analyzed consisted of

a system which employs a TV camera tube to view the array pf patterns through a microscope. The photomask is on a movable stage

which is stepped across the field of view of

the microscope. The photomask pattern information is imaged on the tube target, digitized, and compared with data representing

the correct pattern that is stored in a computer memory. This technology has its

primary application in visual defect detection. It may be applied to registration

inspection if the position of the stage is

known to sufficient accuracy which involves

the use of either a linear encoder or a laser interf erometr ically controlled stage. A schematic diagram of this system is shown

in figure 23.

The required resolution of the microscope

objective is determined by the smallest dimension, 6, of the defect that is to be detected. This resolution determines the minimvim value of the numerical aperture, NA

of the objective:

min'

NA ^ = 1.2A/6 , min

where X is the wavelength of the light used

to view the image. This equation is based

on the criterion that the light intensity be zero between the nearest two points to be

resolved [27]. For a 2 ym defect criterion

and A = 0.55 ym, a numerical aperture of

0.33 or larger is required.

The magnification of the microscope objective, ^^^y niay be selected from a host of

commercially available objectives provided

the numerical aperture criterion is satisfied. Another critical factor is the field

of view of the objective because it is this

that determines in part how fast the mask

may be inspected. An objective with a higher magnification produces a larger image at

TV Camera

TV

monitor

Digital

computer

I

Mag

tape

deck

Teletype

output

Figure 23. Block diagram of TV/microscope automatic mask inspection system.

32
PHOTOLITHOGRAPHY

the expense of reducing the size of the

field of view.

An image of the patterned mask is projected

onto the tube target through the microscope.

To utilize the tube efficiently the projected image must fill the target area which is

usually square or rectangular. Consequently,

the smaller target dimension, t; the side,

s, of the square inscribed in the circular

field of view of the microscope objective;

and the total optical magnification of the

microscope, ^, are related by

tot ^

\ot = •

The smallest image dimension that must be

resolved by the tube, R^, is the product of

the smallest defect dimension, 6, times the

total optical magnification;

The minimum number of scanned lines per

millimeter, I, is the reciprocal of this

product. Calculated values for comparison

of these parameters are given in table 9 for 20 by 20 mm target and selected values

of (5 and M , . . For these calculations A obj was chosen as 0.55 ym, and the values of s were calculated assuming fields of view of

typical microscope objectives [27].

The resolution of the TV tube and its modes

of operation are dependent on the tube design and construction. Both vidicon and

image dissector tubes are compatible with

this technology and each offers different

advantages

The target of the vidicon tube is coated

with a photoconductive coating such as antimony trisulfide or lead oxide. This target

is given a uniform negative charge by sweeping an electron beam across it; when a light

image is projected on the target, the target

coating discharge is, proportional to the

light intensity. This charge pattern is re- tained on the target; a sweeping electron

beam recharges the screen. The beam current

necessary to recharge an area of the screen

and the coordinates of the recharged area provide data that are digitized and read

into a computer. In this image data gathering process the charge pattern is erased.

Before data on a new target image can be

taken, it is necessary for the target to be

uniformly charged. Consequently, the entire

target area must be swept a second time by

the electron beam before a new image is projected on it. The tube cycle time is the sum of the time necessary to read the charge

pattern information and the time necessary

to completely erase the previous image. One

property of the vidicon is that the target

charge pattern remains after the target illumination ceases. Thus, stroboscopic techniques may be used with this tube.

The image dissector tube target is coated

with a photocathode material, generally some combination of sodium, potassium, cesium,

and antimony. When a spot of light strikes

the target, electrons are released and are focused onto an anode plate containing an aperture. A deflection field is applied,

and photoelectrons from various areas are selectively made to pass through this aperture. The current passing through this

aperture is amplified and recorded as a function of the location of the emitting

Table 9 - Critical Parameters for TV/Microscope Mask Inspection

Systems with a 20 by 20 mm Image Tube Target

o, pm ^\iin s. mm Mtot Rr, urn I, mm'

2 0.33 lOX 0,.8 25X 50 20

4 0.16 lOX 0,.8 25X 100 10

2 0.33 5X 1

.6 12. 5X 25 40

4 0.16. 5X 1

.6 12. 5X 50 20

33
PHOTOLITHOGRAPHY

target area by a computer. Unlike the vidicon, this tube has no image storage capability and the image disappears immediately

when the target illumination ceases. Consequently, although stroboscopic techniques

cannot be used with this tube, it is not regimented by a raster-scan mode. The flexibility this tube offers is a random-access

scanning capability that can be interfaced

with a computer programmed to recognize particular features in a scan and analyze automatically these features in greater detail

[28]. Electronic zoom is also possible with

this tube by changing the scan amplitude or frequency. Image dissector tube are available with a matrix of 2000 by 2000 resolvable points that are scanned at the rate of

0.5 microseconds per point or 2 seconds per

complete target scan. These tubes are not used in conventional raster-scanned TV applications because of their illumination

requirements which are 10^ to 10^ times

greater than vidicons.

The rate at which the image information can

be read from these targets is a function of

the time required to scan the target. The

standard (U.S.) television picture contains

a nominal 525 lines which are scanned 30 times a second. The advantage of using this scan rate is the economics of system con- struction; there is a myriad of commercial

electronic equipment that is designed to operate at this scanning rate. The use of a different scanning rate or a different number of scanning lines is possible, but may

involve the design and construction of special equipment.

The resolution of the TV tube is a function

of the target coating, the spot size of the

scanning beam for a vidicon or aperture size

for image dissector, and the number of scan

lines. The size of the scanning spot or aperture is a major factor in the ability to read the detail in the target image. Any

defect smaller than the spot is read as if

it were spread over the same area as the

spot, with correspondingly less intensity.

If two defects in the target image are separated by a distance of one spot diameter or

less the tube signal may not drop below the

threshold between the spots and they may not

be recognized as separate.

A criterion for defect detection is that the

spacing between successively scanned lines

be equal to or smaller than the tube image

of the smallest defect to be detected. This

spacing can be equated to the spot size.

Since the entire target area is scanned in

525 lines, the spot size or tube resolution,

R^, is given by

= H/525 ,

where H is the dimension of the target in

the direction perpendicular to the scan. The yalue of R must be equal to or less

than R . x Scanning the mask on a stage through successive fields of view under a microscope is

accomplished most rapidly by accelerating

the stage through a distance approximately

one half the edge dimension of the field of

view and decelerating the stage through the

remaining distance to the next field of view

so that it stops precisely positioned. The

stage may be designed so that the natural

frequency of the table moving as a rigid

body on its ways as a result of elastic deformation is tuned to the applied torque of

the motor and time of traverse [29]. When

this tuning is accomplished the stage vibration is negligible when the table stops

[29, 30].

The time required to inspect the mask is

the complete cycle time multiplied by the

number, N, of fields of view. The complete

cycle time is the sum of the time it takes

the stage to index to the next field of view

and the tube cycle time, if these steps are done sequentially. A comparison is given in

table 10 of the times required to scan a 3 by 3 in. (76 by 76 mm) field with a vidicon

tube with a 10 by 10 mm target area and with

an image dissector tube with a 25 by 25 mm

target area. In making the calculations it was assumed that the optical magnification

was 25X, that the stage acceleration was

4.9 m/s^, and that the distances for acceleration and deceleration were equal.

The shorter of the times shown in table 10

is too long compared to the representative

time of about 10 min which is typically allowed for an inspector to inspect the same mask [26]. However, it should be noted that

an inspector only partially inspects the

mask and relies on sampling statistics for

quality control. The automatic inspection

system does a 100 percent pattern inspection

on all of the arrays in the mask.

Equipment has been constructed using this

technology and a vidicon tube capable of

counting pinholes and spots in masks which

have device geometries with 2.5 pm linewidths [31, 32]. The combined optical and

34
PHOTOLITHOGRAPHY

Table 10 - Scan Times for Two State-of-the Art TV/Microscope Mask Inspection Systems

Scan Index Erase Total cycle Inspection

Tube s, mm time, ms time, ms time, ms time, ms N time, min

V id icon 0.4 33 18 33 84 35000 49

Image

Di ssector

1.0 2000 30 0 2030 5600 190

electronic magnification is 250X with a lOX

objective. The pinhole and spot counter operates with a fixed field of view which re- quires that the stage holding the mask be

indexed in fixed increments. The equipment

is capable of inspecting masks for wafer

sizes up to 2 in. (5 cm) in diameter. In operation defects are counted as many times

as they are intercepted by the TV camera

scan line. The size of the .smallest defect

counted is a function of the smallest mask

geometry. The electronics were designed so that defects are counted which are approximately 80 percent or more of the size of

the smallest line width on the mask. A

complete indexing cycle occurs every 8/30 s. The indexing cycle consists of 1/30 for information reading, 3/30 s for indexing and

4/30 s for complete tube erasure.

With such a system, a 100-percent inspection

of a 3 by 3 in. (76 by 76 mm) mask with a field of view of 0.8 by 0.8 mm would require

about 39 min. This time could be shortened

to about 11 min by performing the stage indexing and erasure simultaneously in 1/30 s. This would require the use of a stroboscopic

technique because the vidicon target could

not be illuminated during stage indexing.

Thus, the field of view could be illuminated

for 10 ys or less with a strobe and stage

indexing could be done during the information read out-erasure process. These modifications are within the current state-ofthe-art using vidicons with more sensitive

target coatings and stages that can operate

and index to the required accuracy at accelerations of about 10 m/s^ [30].

The speed of the system using an image dissector tube can also be improved. In principle, it is possible to construct a dissector tube using a 4 by 4 matrix of apertures,

although construction of such a tube would

be very expensive. This tube would scan a single field of view in 1/16 of the time now required. This would decrease the total

inspection time per mask to less than 12 min. The inspection time could be reduced

further by exploiting the random scanning

capability and the programmable features of

the image dissector tube to examine only

the critical portions of the patterns on the

mask. These features also would enable detailed examination of defects as they are scanned which is necessary for defect identif ication 5 but this is done by sacrificing

inspection speed. These operations are normally not possible with a vidicon.

For this system to operate using either a vidicon or an image dissector tube, the

signal change on going from a transparent

to opaque area must be sufficient that an electronic threshold setting can distinguish

between them. This places restrictions on both the signal-to-noise ratio of the TV

tube and on the resultant modulation transfer function (MTF) of the microscope and TV

tube. If the resultant MTF is too low the

system can not distinguish between the clear

and opaque areas and an erroneously low defect count may result. If the signal-tonoise ratio is not sufficiently low an er- roneously high defect count may result.

The application of this technology to registration and critical dimension measurements

is possible in principle. The location of

a line edge to a precision of 0.25 pm in- creases the resolution requirements of the

tube and optics. This can be accomplished

by using greater optical magnifications and

numerical apertures , and a larger number of scan lines on the tube target. Much more stringent requirements are also placed on knowing the precise location of the stage.

The stage location can be monitored with

35
PHOTOLITHOGRAPHY

Figure 24. Polarizing laser interferometer mounted

on window of scanning electron microscope.

the use of linear encoders or interferometers. The implementation of these modifications into this system can only be accom- plished with a corresponding decrease in

speed. (D. B. Novotny and D. R. Ciarlo-'O

8.2, Photomask Metrology

A polarizing laser interferometer with a 1 nm displacement resolution was constructed

for use with a scanning electron microscope

(SEM) . The SEM is being used for the accurate detection of a photomask line edge as the line is moved on a stage under a stationary electron beam. The interferometer

measures the distance traversed from one line edge to the other. A helium-neon laser

is the light source. Two perpendicular,

linearly polarized light beams, one from the

artifact mirror and one from a reference

mirror located within the interferometer,

overlap as they enter an analyzer. The analyzer measures the angle through which the

plane of polarization of the resultant light

beam rotates. An analyzer rotation of 180

degrees corresponds to an artifact mirror

movement of one quarter of a wavelength.

The beams reflect twice from the artifact

or stage mirror and twice from the reference

mirror. This doubles the interferometer

sensitivity as compared to single pass interferometer systems. A photograph of the

instrument, mounted on the SEM window, is

shown in figure 24.

To determine the stability of the SEM stage,

a mirror was mounted directly on the stage

and the stage position monitored over ex- tended periods of time. The stage used was

a typical stage with x, y, z, and (fi degrees

of freedom and. was not specifically designed

for this measurement. A positional stage

drift in one direction of about 20 nm/minute

was observed. Superimposed on this drift were occassional sporadic stage jumps of

about 100 nm.

This experimental arrangement is sensitive

to differences in optical path lengths

which may be caused by subtle movements of

the SEM vacuum housing. Such movements can

be eliminated by mounting the interferometer

within the SEM vacuum chamber. In addition,

a more rigid stage with fewer degrees of

freedom is being obtained for use with this

system. (A. W. Hartmant,

J. M. Jerket, and D. B. Novotny)

A preliminary experiment was carried out in

order to determine whether a line-center to line-center (or line-spacing) measurement

made on an artifact designed for calibration

Lawrence Livermore Laboratory, Livermore,

California 94550. Work conducted under

NBS Order No. 503183.

NBS Optics and Micrometrology Section, Optical Physics Division.

36
PHOTOLITHOGRAPHY

of the magnification of an SEM can also be

used to calibrate a microscope equipped with

a micrometer eyepiece and whether this instrument can,- in turn, be used to measure a line width with desired accuracy. The artifact consisted of gold lines approximately

1-ym wide in a nickel matrix. These gold

lines were separated by from 3 to 12 ym. This artifact also contained a copper line

approximately 3-ijm wide in the nickel matrix

that was parallel to and separated by many

micrometers from the gold lines. The linewidth measurements were made on this copper

line since it could be unambiguously identified and its edges could be more easily distinguished in the nickel matrix.

The distance between the centers of the parallel gold lines was accurately measured on

the NBS line-standard interferometer [33]

which related this distance to ,the wavelength of light with a sample standard deviation of 0.007 pm.

The experiment was performed by taking a scanning electron micrograph of the artifact

which included both the gold lines and the

copper line. The transparent negative of

this scanning electron micrograph was placed

in an optical comparator and the width of

the copper line was determined to be 3.13 ym

by scaling from the previously determined

line separation. The sample standard deviation for this measurement was about 0.02 pm.

The width of the copper line was also measured using a microscope fitted with a filar eyepiece. The artifact was examined

under bright field reflected illumination;

a narrow-pass filter with a band ceriter-at

486 nm was used on the illuminator. The

eyepiece was calibrated from the previously

determined line separation. With the filar

eyepiece the line width was found to be 3.25

ym with a sample standard deviation of

0.10 ym.

The results of this preliminary experiment

indicate that line-spacing to line width

measurement transfer may be possible with

this type of artifact and that such a calibration method may be used for line-width

measurements of metal lines in metal matrices. (F. W. Rosberryt,

J. M. Jerket, and D. B. Novotny)

It must be stressed that the artifact used

in the experiment described above differs in

several significant ways from an artifact

that would simulate the properties of a chromium-on-glass photomask. In the former,

there is no large difference in the optical

properties of the gold, nickel, or copper

lines. They all reflect light well, are

opaque, and are good electrical conductors.

These lines are all in the same plane on the

artifact surface with no edge profiles.

Chromium-on-glass photomasks consist of con- ductive and opaque lines on a non- conductive,

transparent substrate, and the line edges

are distinguished by height variations.

Figure 25 shows portions of an artifact, designed for use in establishing standards for

line-width measurements in the 1 to 10 ym

range, which simulates the properties of

such a photomask.

Figure 25. Typical single-line and three-line patterns on artifact for standardization of

line width measurements. (Dimensions in micrometers.)

37
PHOTOLITHOGRAPHY

The pattern is fabricated in a film of

chromium or iron oxide on a 6.4 mm thick,

optically flat glass substrate coated with

a thin layer of tin oxide, or other transparent, conductive material. This coating

is provided in order to permit the artifact

to be imaged both in the optical microscope

using transmitted light and in the SEM. The flatness tolerance of the glass (X/10 for

for X = 500 nm) is required in order that

the height variation of the artifact does

not cause magnification changes when the

artifact is used in the SEM. The pattern includes two narrow lines which are nominally

2 ym in width and separated by about 30 ym. Adjacent to these lines are 3 opaque bars,

nominally 1 ym, and 10 ym in width in a clear field. Nearby is an opaque field in

which there are 3 clear lines of the same nominal widths as the opaque bars. Additional similar patterns containing two

,

three, and four bars and openings of each

width spaced by a distance nominally equal

to the line width are also included in the

pattern.

The spacing between the two narrow lines can

be measured to an accuracy of about ±0.02 ym

by the existing NBS line standard interferometer [33]. The opaque bars on a clear

background and the reversed condition of

clear bars on an opaque background simulate

the two conditions of contrast typically en- countered in chromium and emulsion photomasks. The nominal widths of these bars were chosen to span the measurement range

of interest. The multiple patterns simulate

patterns found in integrated circuit masks

and can be used to study the effects of adjacent bars and spaces on the measurement.

In use it is intended that the line widths

on this artifact be calibrated by accurately detecting the line edges in an SEM and

using an in situ laser Interferometer to measure the line widths. A serrated edge

is provided at the edge of the opaque field

to assist in locating the position at which

the line-width measurement is actually made

to allow for accurate calibration even if

the bars or openings vary in width along

their length. Once calibrated, the artifact can be used to calibrate a measuring

system based on an optical microscope such

as a filar eyepiece or an image shearing

eyepiece. (J. M. Jerkef and D. B. Novotny)

The width of a chromium line on a glass substrate was measured using both filar and

image shearing eyepieces. Both bright field

and dark field reflected 486 nm illumination were used. The mean values obtained

for 20 measurements on the line, which was nominally 12 ym wide, under each of the

above conditions are listed in table 11.

Table 11 — Comparative Measurements of the

Width of a Chromium Line on Glass

Eyepiece II 1 umi nation

Bright Field Dark Field

Filar

Image Shearing

11 .76 ym 11 .06 ym

11 .87 ym 11 .83 ym

The sample standard deviation in each case was about 0.08 ym. The difference between

the widths measured using the filar and

image shearing eyepieces with bright field

illumination is less than two sample standard deviations while the difference mea- sured with dark field illumination is

greater than nine sample standard deviations. If the bright field and dark field

measurements are compared for the same type

of eyepiece, a significant difference oc- curs for the filar eyepiece. No explanation for this phenomenon has been formulated, but these discrepancies represent typical measurement discrepancies currently

found for this size pattern in the photomask and integrated circuit industries.

(F. W. Rosberryt,

J. M. Jerket, and D. B. Novotny)

38
9 . EPITAXIAL LAYER THICKNESS

9.1. Transient Capacitance Methods

An analysis was performed to study the limitations of the ramp-voltage and steprelaxation methods for measuring epitaxial

layer thickness (NBS Spec. Publ. 400-4, pp. 51-53). Both of these methods utilize the

transient capacitance of a aetal-oxidesemiconductor (MOS) capacitor or a metalphotoresist-semiconductor (M(PR)S) capacitor

(NBS Spec. Publ. 400-12, p. 26). Potential

limitations arise for three reasons: (1)

voltage breakdown may occur when the edge of

the depletion region is in the epitaxial

layer, (2) the steady-state depletion width

in inversion may be greater than the layer

thickness, and (3) the carrier lifetime in

the depletion region may be so short that no

transient can be observed. In discussing

these limitations it is necessary to ask not

only whether a real thickness measurement

can be made but also to inquire under what

circumstances an apparent measurement might

be mistaken for a real thickness measurement.

It is assumed that the voltage available to bias the capacitor is sufficient to drive

the depletion region into the substrate.

The ideal capacitance- time characteristics

(case 1) for the ramp-voltage and steprelaxation methods are illustrated in figure

26. In the figure, is the steady-state

capacitance in accumulation (the oxide ca- pacitance, C is the steady-state capacitance in inversion, is the capacitance

when the depletion edge is at the layersubstrate interface, (the value used to calculate the epitaxial layer thickness) , Cm

is the capacitance which corresponds to the

maximum applied bias voltage (deep depletion

region) , and C„,, is the capacitance which

corresponds to the breakdown voltage. The

voltage step in the step-relaxation method

is applied at a time, tg. Note that for

both methods a discontinuity in the slope of

the C-t curves occurs at C = C and that

C^, <C <C <C . ^ BV m t <=o First consider the effects of voltage breakdown under two conditions which might occur:

case 2, in which breakdown occurs after the

depletion edge has gone beyond the layersubstrate interface but before the maximum

bias voltage is reached (C <C„„<C ) , and m BV t case 3, in which breakdown occurs before the

depletion edge has reached the layersubstrate interface (C^<C^„) . In case 2,

t D V

illustrated in figure 27, the slope discontinuity can still be observed and the measurement made by both methods; in the rampvoltage method there is a finite slope between C and C , but the capacitance is

t BV constant after breakdown occurs. In case 3,

illustrated in figure 28, measurement is not possible because the capacitance is not

reached. This condition can be identified

by the flat response immediately following

the slope discontinuity in the ramp-voltage

method (fig. 28a) and by the absence of a slope discontinuity between the minimum and

in the step relaxation transient (fig.

28b) . Measurements of the step response of

a specimen were made under conditions which

appear to correspond to case 2. In these

instances there appeared to be a transition

from the ideal case to case 2 as the voltage

in inversion was made more negative. Case 3 was simulated using an MOS capacitor fabricated on a bulk n-type silicon slice having

a nominal 0.1 Q.-cm resistivity. Response

curves similar to those in figure 28 were observed in this experiment.

Consider now case 4 in which the steady state

depletion width exceeds the epitaxial layer

thickness. This case occurs if the dopant

density is sufficiently low that the depletion region extends into the substrate. If the dopant density in the substrate is very

large, the depletion region can penetrate

only a very small distance into the substrate

so that C ; C^. However, if the dopant

density in the substrate is not very large,

the depletion region may penetrate an appreciable distance and C < C . The transient 00 t in the ramp-voltage method is not affected

by the position of the depletion edge; the

slope discontinuity at C^ occurs whether

C^>C^ or C^<C^. However, as shown in figure

29, the step-relaxation transient exhibits

no slope discontinuity between the minimum

and C . Although C = C in most wafers of

oo '-^ oo practical interest, it is not possible to distinguish the occurrence of case 4 unambiguously from the occurrence of case 3 when using the step-relaxation method.

Therefore this method is not recommended for use when no slope discontinuity is observed.

The question of measurability of a particular

specimen can be resolved readily with the

help of figure 30 if one has or can assume

some prior knowledge of layer resistivity

39
EPITAXIAL LAYER THICKNESS

Figure 25. Ideal capacitancetime characteristics for an

MOS capacitor on a thin

epitaxial layer.

a. Ramp-voltage method. b. Step-relaxation method,.

Figure 27-. Capacitance-time

characteristics for an MOS ca- pacitor on a thin epitaxial

layer when voltage breakdown

occurs at voltages less than

the maximum applied bias voltage but greater than the bias

voltage which corresponds to

the depletion edge at the

layer- substrate interface.

a. Ramp-voltage method. b. Step-relaxation method,

Figirre 28. Capacitance-time

characteristics for an MOS ca- pacitor on a thin epitaxial

layer when voltage breakdown

occurs at voltages lower than

the bias voltage which corresponds to the depletion edge at the layer substrate interface.

a. Ramp-voltage method. b. Step-relaxation method.

cA

0 U

'CO Figure 29. Step-relaxation capacitancetime characteristic for an MOS capacitor

on a thin epitaxial layer when the steady

state depletion width equals or exceeds

the layer thickness.

and thickness. This knowledge can be very

approximate and still be useful. In figure

30, breakdown normally occurs in the layer

in those specimens whose dopant density and

layer thickness are such that they can be

represented by a point above the solid line

[34]. Such specimens cannot be measured by

either method. The broken line in figure 30 represents the case where the layer thickness

is equal to the steady state depletion width

40
EPITAXIAL LAYER THICKNESS

p-type p |fl.cm|

10 E

00

CO

0.1 X

0.01

"1

10 1 n type ^lll cml

1 01

1 1 10 ) o'l E 1 1 1 INJ 1 1 1 1 nil E oO \.

O - o \

o \ C

—

~E E "•"-^ A

E B

1 1 lllllll 1 1

1 1 1 1 mill

10'* 10'^ 10'^ 10'^ u

DOPANT DENSITY

Figure 30. Plot of- epitaxial layer thickness

and dopant density showing regions where

thickness can be measured by both the rampvoltage and step-relaxation methods (A), by

only the ramp-voltage method (B), and by

neither of. these methods (C). (O: measured

specimens .

)

so chat C^=C^ [35]. Specimens whose dopant

density and layer thickness are such that

they can be represented by a point below the

broken line fall "in case 4 and should not be

measured by the step-relaxation method.

Whether carrier lifetime presents a limitation depends largely on the response time of

the instrumentation being used to make the

measurement. When the carrier lifetime is

very short, the capacitance transient is

very fast so that only the steady-state ca- pacitance-voltage curve can be observed.

In some cases, cooling the specimen can slow

the response time to the extent that the ca- pacitance transient can be observed (NBS

Spec. Publ. 400-4, pp. 51-53) [36]. However,

it appears most likely that the measurement

is not possible when the lifetime is so short that no transient response can be observed. The effect of lifetime does not

appear in figure 30.

The results of the analysis are summarized

in table 12. Several words of caution need

to be added. First, for lower dopant densities, breakdown may occur at shallower

depths than indicated by the solid line in

figure 30 because of peripheral breakdown

effects [37]. Second, the step response of

bulk specimens may exhibit significant

changes in slope during the course of the

transient, but these are generally different from the distinct break which occurs at

a layer-substrate interface. Third, the

methods presented depend on the response

curves having a finite slope in the substrate in the absence of breakdom. More

heavily doped substrates tend to have flatter response curves which may make it difficult to distinguish between slope discontinuities at C and C„„. However, even

L DV for very heavy doping, sidewall spreading

of the depletion layer should cause the

slope to be finite. Fourth, the analysis,

although carefully considered, has been

only partially substantiated by experimental data. The specimens for which data

have previously been reported (NBS Spec.

Publ. 440-4, pp. 51-53) are shown as plotted points on figure 30. Note that they

all correspond to the ideal case which is

the most easily measured.

(R. L. Mattis and M. G. Buehler)

Table 12 - Summary of Analysis of Limitations of Transient Capacitance

Methods for Measuring Epitaxial Layer Thickness

Brea kdown Depletion Lifetime Measurement

Case Condition Condition Condition Possible By

1 Long Lifetime Either Method

2 ^BV'^^tC >C.

<x> t Long Lifetime Either Method

3 c >c.

°° t Long Lifetime Neither Method

4 c <c.

oo t Long Lifetime Ramp-Voltage Method

5 any any Short Lifetime Neither Method

41
10. WAFER I ri S P E C T I 0 N AND TEST

10.1. Flying-Spot Scanner

Additional modifications were made to the

optical flying-spot scanner to enhance its

usefulness. Additions and changes to the

optical system are illustrated in figure 31. The original laser (NBS Spec. Publ. AOO-8,

pp. 34-36) is now used only for 1.15 pm service, and an additional laser, shown on the

left, has been added for dedicated 0.633 pm

operation. Scanning is shifted between

these two wavelengths by moving mirror M3

which is mounted on a slide. As shown in

the figure,' M3 blocks the beam from the

1.15 ym laser and inserts the 0.633 pm beam

into the light path between the fixed mirror

M2 and the first scanning mirror V; for 1.15

pm operation, M3 is withdrawn from the light

path to the dotted position in the figure.

In addition, a half-wave plate has been

added to the light path of the 1.15 pm beam

to allow the polarization plane of the radiation to be rotated a:nd the intensity of the

ref lected-light signal to be adjusted.

The video amplifiers between the scanned

specimen and the display screen were re- placed by custom designed direct-coupled

amplifiers when it was discovered that under

certain conditions the former oscillated and

produced harmonics at frequencies close to the laser-mode-beat frequencies and so obscured these high-frequency measurements.

As an additional benefit, the present circuit permits one to obtain the response of

the specimen to laser-mode-beat modulated

light (NBS Spec. Publ. 400-12, p. 27) simultaneously with the response to unmodulated light. These two responses may be

electronically summed to present a composite response map on the display screen. In addition, a high- impedance specimen probe

was designed and added to the' system to couple the scanner to MOS circuits. It features an input impedance of 22 KO. in

shunt with a 3.1 pF capacitance, and it is

both direct-coupled and wide-band in con- sonance with the amplifiers which follow it.

Attempts to vary the light from the 0.633 pm laser by modulating the laser tube current were successful, and a modulator was con- structed which yields a 10 percent or greater modulation of the light for frequencies

between dc and 100 kHz. This is expected to enable the instrument to perform stroboscopic scanning measurements on integrated circuits to follow the internal information

flow, and locate defects which impede this

flow.

Several integrated circuits were observed

with the scanner in order to gain further

information regarding its operation. Most

of the observations were made using only

the two supply bus contacts; the displayscreen signal was obtained by sensing, via

a resistor, changes in the bus current.

This signal was combined with the one from

the ref lected-light circuit to produce on the screen the electrical response of the

integrated circuit superimposed on a map of

the surface metallization.

One of the circuits studied was a bipolar,

junction-isolated, two-input, NAND gate

(7438) . The electrical response of the circuit to the scanning light spot arises in

ANALYZER <iD

PHOTOCELL

DISPLAY SCREEN

FifTure 31. Pictoi'iai diagram of light and signal

,:3.cns of dual- laser flving-spot scanner.

42
WAFER INSPECTION AND TEST

the following way: current injected into

the base of a transistor, whether injected

across a junction or photogenerated within

the base region, is amplified by the tran- sistor if the transistor is biased appropriately. This amplified current is taken

from the supply bus. Thus, transistors operating in the active region, in which there

is significant small signal current gain, are readily identified as they show a large

photoresponse to 0.633 ym light and consequently produce an image on the display

screen. Changing the state of the NAND circuit yields a new map of the active ele- ments .

The 0.633 um radiation penetrates silicon

to a depth of only 1 or 2 pm at room tem- perature, but the 1.15 um light penetrates

quite deeply; the silicon is almost transparent at the latter wavelength. As isolation diffusions in integrated circuits

are commonly much deeper than a few micrometers, they are not seen on the monitor

screen as readily using 0.633 ym light as the active regions of the transistor which

generally are within a few micrometers of

the surface. However, the isolation diffusions of the NAND gate were easily displayed using 1.15 um radiation.

Additional information about the construction, as well as the operation, of the

integrated circuit is provided by highfrequency measurements using laser mode

beats: for example, diffusions surrounding

the bonding pads at the periphery of the die were detected. Thus, comparing observations

made using all of these available scanning

techniques can yield not only information

about the electrical behavior of the integrated circuit, but also information about

the sequence of steps employed in its fabrication.

As a beginning in the use of the scanner for

MOS integrated circuits, two complementary

transistors in a silicon-on-sapphire 4007

(dual complementary pair plus inverter) were

connected to form an inverter stage and

scanned with 0.633 ym light. As for the bipolar NAND gate work described above, the

signal for the display screen was obtained

from the supply voltage bus. The operation

of the circuit was changed by changing the

bias conditions, and one could readily distinguish which were the conducting transistors for each of the bias conditions.

(D. E. Cawyer and D. V;. Berning)

10.2. Scanning Electron Microscopy —

Electron-Beam Induced Damage

The well controlled low-energy electron beam

used by the scanning electron microscope

(SEM) is a potential source of damage -to microelectronic devices under examination.

Because an electron energy of approximately

200 keV or greater is necessary to cause displacement damage in silicon, the bulk

properties of the devices being examined are usually unchanged at typical electron accelerating voltages. However, the electron

energy deposition in the device materials

through ionization processes may result in

changes in the surface oxide properties.

The effect of this energy deposition on the

degradation of device electrical parameters

has been noted for both bipolar [38-42] and

MOS [42-49] devices. To illustrate the effects of exposure to SEM beams, the electrical parameters of a digital bipolar circuit,

a linear bipolar circuit, and an MOS circuit were monitored as a function of SEM

operating conditions.

The first integrated circuit to be examined

was a digital bipolar inverter, the 7404.

Of the six inverters on the 7404 chip, only

the characteristics of one were monitored.

Measurements were made to determine if the

device met the manufacturer's minimum specifications for both high-and-low-level outputs after exposure in an SEM operating with

an electron beam energy, E„, of 20 keV at a

D beam current, I , of 100 pA scanning an

B area, A^, of 0.02 cm^ . No change in electrical characteristics was detected after a 1000 s exposure with all leads grounded.

The same device was then exposed for 1000 s with a collector supply voltage of 4.75 V and an input voltage of 2.0 V and again for

1000 s with the same collector supply voltage but an input voltage of 0.8 V. No change in electrical characteristics was observed after either exposure. An additional 1000 s exposure with a beam current

of 1 nA produced no measureable damage.

This particular device appears Insensitive

to changes in surface oxide properties and

is not susceptible to SEM damage. Identical

results were obtained with other samples of

this device type.

A linear bipolar device, a 741 operational

amplifier, was the next integrated circuit

examined. The input offset current, I OS and the input offset voltage, V , were

OS monitored as a function of exposure time in
WAFER INSPECTION AND TEST

EXPOSURE TIME (s) EXPOSURE TIME (s)

a. Input offset current. b. Input offset voltage.

Figure 32. Characteristics of 741 operational amplifiers as a function of exposure time

in a 20 keV beam of a scanning electron microscope. («: Device not biased during exposure;

: Device biased during exposure .

)

the SEM. One sample was scanned with the

leads grounded while another had +15 V applied to the positive collector supply ter- minal and to the non-inverting input and

-15 V applied to the negative collector supply terminal and to the inverting input during exposure. The SEt'I operating conditions were

= 0.03 cm2, 1^ = 100 pA. Eg - 20 keV.

The changes in I and V as a function of ° OS OS exposure time in the SEM beam are shown in

figure 32. With bias applied during exposure, both I and V exceeded the manuOS OS facturer's maximum specifications after an exposure of less than 100 s. Additional

samples were examined and yielded similar

results.

The third integrated circuit type examined

was a C-MOS A007, a dual complementary pair

plus Inverter. The particular circuit used was fabricated using sllicon-on-sapphire

technology. The inverter characteristics

were first monitored as a function of SEM

voltage. No change in the inverter characteristics was observed when a single circuit

with leads floating was exposed successively

to 2.5, 5.0, and 10.0 keV beams for 1000 s intervals with = 100 pA and A =

a s 0.02 cm^. Changes, as shown in figure 33,

were observed when the circuit was exposed

to a 20.0 keV beam with the same values of

I and A . Measurements were made after exB s posure of the circuit for 50, 500, and 1000

s with the leads floating. Significant

shifts were observed after each exposure,

and the device was inoperative after the

1000 s exposure. Measurements were also

made after exposure of a different circuit

of the same type for 1, 10, and 50 s with

+5 V applied to both the drain and input

terminals. Severe shifts in characteristics

occurred after the 10 s exposure and after

50 s the device was inoperative. As is the case with exposure of these circuits to gamma radiation, the degradation of the CMOS

inverter characteristics is more severe when

exposed with voltages applied.

The electrical parameters of microelectronic

devices are usually sensitive to changes in

the oxide characteristics of those oxide

films near the active silicon regions. For

an MOS device such as the 4007, the ionizing

effects of the SEM electron beam can be measured in terms of the energy deposited in

the gate oxide. In order to facilitate the

comparison of SEM electron beam ionization

damage with the effects of other ionizing

sources, the radiation dose unit, the rad

which is defined as the amount of radiation

which deposits 100 ergs of energy per gram

44
WAFER INSPECTION AND TEST

1

1

1

'

A 08

B 50 s C 500 s D 1000

s

\

B

\c

D \

V,N (volts

a. Circuit not biased during exposure, ^DD = ^IN +5 V during exposure

,

Figure 33. Characteristics of C-MOS 4007 circuit after various exposures to a 20 keV beam

of a scanning electron microscope.

of irradiated material, is ordinarily em- ployed (1 rad = 10~2 J/kg)

.

If normal beam incidence and uniform electron flux over the rastered area is assumed

and the device structure above the critical

oxide is known, the radiation dose levels in

the pertinent surface oxides for a device

exposed to the SEM electron beam can be calculated from

Dose [rads(S102)] = 100 A T

s ox

(11)

where t is the scan time in seconds, f^^ is

the fraction of incident energy deposited in

the oxide, T is the oxide thickness in ox micrograms per square centimeter, and the re- mainder of the symbols have been defined

earlier. The fraction f^^ is the area under

the depth-dose curve [50] for that portion

of the total penetration distance subtended

by the oxide after proper account is taken

of the fraction of energy backscattered, f^,

B assumed for the present calculations to be

0.1 [51].

The dose accumulated in the gate oxide of the

4007 circuits was calculated from eq (11).

The structure above the 100 nm gate oxide

consisted of an aluminum film approximately

1.0 pm thick and a silicon dioxide overcoat

approximately 0.6 pm thick. The accumulated

dose per second of exposure time is given in

table 13 as a function of beam energy for I„

D

= 100 pA and A =0.02 cm^ . The experimental

observation of no degradation at 2.5, 5.0,

and 10.0 keV is in agreement with the calculations. A 71 s exposure of 20 keV electrons under these operating conditions results in a dose of 10^ rads(Si02), a sufTable 13 — Dose Accumulated in Gate

Oxide for 1 Second SEM Exposure

keV Dose, rads(Si02)

2.5 0.0 0.0

5.0 0.0 0.0

10.0 0.0 0.0

15.0 0.012 3.8 X 103

20.0 0.033 1.4 X 10^+

30.0 0.020 1.3 X 10"+

45
WAFER INSPECTION AND TEST

ficient dose to cause significant electrical

parameter changes for many classes of devices .

The SEM operating parameters utilized in

this report are typical of those used in

SEM topographical examinations of devices.

It is apparent that for some classes of devices little or no electrical parameter degradation occurs. However, for others, even

a brief examination can be destructive.

SEM induced degradation is a function of

accelerating voltage, beam current, scanned

area, exposure time and bias voltages applied to the device under test. (K. F. Galloway, W. J. Keery, and K. 0. Leedy)

10.3. Automated Scanning Low Energy

Electron Probe

The initial goals of the investigation of

the automated scanning low energy electron

probe (ASLEEP) (NBS Spec. Publ. 400-12, p. 28) are to construct the instrument and

demonstrate proof of principle by application of the instrument to the determination

of the uniformity of oxide films. The

effort encompasses research in electron gun

design, fabrication, and test as well as computer interfacing and software generation.

In preparation for the alignment and testing

of the electron gun for the ASLEEP system,

a uniform aluminum grid on a silicon dioxide

substrate has been fabricated. This grid is

used to measure the linearity of the beam

positioning circuitry and, as the computer

programming progresses, should allow calculation of a computerized correction factor

to remove beam steering errors. The system

response to one line of this grid can also

provide an estimate of the electron beam

spot size.

In order for the instrument to provide absolute surface potential measurements, a calibrated standard target is required. Since

the work functions of the low index planes

of tungsten have been exhaustively studied,

a standard target was fabricated from tungsten ribbon using recrystallization techniques [52-54]. When this single crystal

reference target is mounted on a vacuum ma- nipulator, either the reference or the speci- men under test may be placed in front of the

electron gun.

The computer control system has been acquired

and the necessary, software and interface

projects are underway.

(W. C. Jenkins- and G. P. Nelson-)

Basically, ASLEEP utilizes a low energy

electron beam under computer control to measure surface potential. A simplified block

diagram is shown in figure 34. The instrument has potential usefulness in areas ranging in complexity from incoming wafer acceptance to integrated circuit diagnostics.

Work conducted at the Naval Research

Laboratory, Washington, D. C. 20375

under NBS Order No. 501718. NBS contact

for additional technical information:

K. F. Galloway.

CONVERTER

D/A CONVERTER

DISPLAY aL | TAPE TERMINAL \\

\

COMPUTER

CATHODE SWEEP

TIME START PULSE

COUNTER JZi

-J STOP PULSE

CATHODE SWEEP ELECTRON COLLECTED SWEEP VOLTAGE GUN a CURRENT

CIRCUIT SPECIMEN

X DEFLECTION AMP a COIL

Y DEFLECTION AMP a COIL

ANALOG

D ISPLAY

CLOCK

AMPLIFIER rHRESHOLO DETECTOR

Figure Block diagram of automated scanning low energy electron probe*

46
11. I N T E R C 0 rUJ E C T I 0 fl B 0 fl D MI G

11.1. In-Process Bond Monitor

The study of the uniform beam model for motion of an ultrasonic bonding tool (NBS Spec.

Pubis. 400-8, pp. 37-39, and 400-12, pp. 29-30) was extended to include the force at the tool tip during the bonding operation. This force, F(f ,t) is related to the third

spatial derivative of the vibration amplitude at the tool tip by

F(P.,t) = -EI Y"'(il,t) ,

where EI is the flexural rigidity of the tool and 9, is the tool extension below the

horn. If the tool is driven sinusoidally at the horn, the boundary conditions to be

used are

Y(0,t) = a sinwt, Y'(0,t) = 0, Y"(S,,t) = 0, and Y"'(P,,t) = - ^

^t'^'' , (12) hi

where a is the vibration amplitude of the tool at the transducer horn (x = o) and u is

the vibration frequency.

The general solution to the equation which describes the motion of the tool in space

and time (NBS Spec. Publ. 400-4, pp. 65-66) is

Y(x,t) = Bisinh(qx) + B2COsh(qx) + B3sin(qx) + B4COs(qx), (13)

where q = (pAoo^ /EI) ^

, p is the volume density of the tool material, and A is the cross sectional area of the tool. Making use of eqs (12) in eq (13) and introducing

the dimensionless* variables Z = q8,, N = x/H, the solution may be shown to be in the

form

Y(N,t) = ^^^J^ly^ |a(Z) [sin(NZ) - sinll(;:JZ) ] + B'^(Z)cosh(NZ) + b" (Z)cos (NZ)

}

+ 2^|||^^^ ] [cosh(Z) + cos(Z)][sin(NZ) - sinh(NZ)]

+ [sinh(Z) + sin(Z) ] [cosh(NZ) - cos(NZ)][, (14)

where

D(Z) = 1 + cosh(Z)cos (Z) , A(Z) = sin(Z)cosh(Z) + cos (Z)sinh (Z) , and

B~(Z) = D(Z) ± sinh(Z)sin(Z)

.

It should be noted that the first term of eq (14) is just the solution of the driven

uniform beam in the unloaded phase of operation, Y (N,t). Hence, in the limit as the

tool tip-wire force goes to zero, Y(N,t) approaches the previously determined solution (NBS Spec. Publ. 400-8, pp. 37-39).

The solution, Y(N,t), can be simplified to

Y(N,t) = Y^(N,t) + F(5.,t)$(N),

where $(N) is defined as

47
INTERCONNECTION BONDING

tCN) = 2q^EI D(Z) it^osh^Z) + cos(Z)][sin(NZ) - sinh(NZ)]

+ [sinh(Z) + sin(Z)][cosh(NZ) - cos(NZ)]|.

At the ith node, the unloaded beam solution, Y (N .,t) is zero so the solution at the

O 01

node becomes

Y(N .,t) = F(£,t)4'(N .). (15) oi oi

From eq (15) it can be seen that the temporal evolution of the tool vibration amplitude

at a nodal position of the unloaded beam provides direct insight into the temporal evo- lution of the force at the tool tip during the bonding operation. An elucidation of

this force can provide information about the mechanism of ultrasonic bonding particularly in regard to the ultrasonically induced plasticity of the aluminum wire and the

relation of this plasticity to the bonding mechanism.

At the tool tip, N = 1, the solution becomes

Y(l,t) = ^ p^""^ [cosh(Z) + cos(Z)]+ [cosh(Z)sin(Z) - cos(Z)sinh(Z)] .

Hence, the amplitude at the tool tip also provides a measure of the force at the tool

tip during bonding. (J. H. Albers)

48
12. H E R ri E T I C I T Y

12.1. Dry Gas Gross Leak Procedures

The limiting factor in dry gas leak test procedures is the rapid depletion of the gas from the package interior which causes nondetection of large leaks. A Knudsen expansiondifferential sensing method was devised previously to eliminate this factor (NBS Spec.

Pubis. 400-4, p. 70, and 400-8, p. 42). Another procedure has now been considered as a possibility for extending the range of cur- rently available instruments by effectively

reducing the delay between the back pressurization phase and the detection of tracer gas which has penetrated the package. This procedure employs a rapid gas cycling technique.

In addition to reducing the delay time, the

procedure is intended to provide controlled

environmental conditions so that a quantitative relationship between true and measured

leak value can be reasonably well derived

while maintaining the testing time at an ac- ceptably low value. While the method may be

applied to either the helium leak detector or

the radiotracer apparatus, the description

which follows is for the former.

A single chamber doubles for pressurization

and detection. Dwell time is minimized by

rapid gas expansion, and excess helium is

diminished by dilution. The gas handling

circuit is shown schematically in figure 35; standard symbols [55] are used to indicate

the components. All valves are quick acting.

The ratio, r, of the ballast volume, Bj or

B2, to the volume of the chamber. A, in which

the devices to be tested are placed should be

100 or more. Helium is introduced into chamber A to the desired pressure for a specified

time of the order of seconds. The chamber is

then vented first to the atmosphere and then

into the ballast tank Bj in a continuous se- quence of about 1 s duration to reduce the

helium gas pressure surrounding the test specimens to a pressure of 1/r atm. Nitrogen

gas (or dry air) is then introduced into

chamber A to dilute the remaining helium

within about 1 s by a factor equal to the

product of the nitrogen pressure, P^ (in atmospheres), and the ratio r. The mixture in

chamber A and associated lines is again vented to atmosphere and expanded, first into Bj

and then into B2 . Thus, the pressure in

chamber A is reduced to 1/r^ atm by the

double expansion. The partial pressure of

helium in the chamber is 1/P r^ atm.

n At this time, with valves 7 and 8 closed and

valve 2 opened, any' helium in the chamber

remaining from the expansion and dilution

sequences or leaking from the specimen interiors would pass through the fixed leak,

FL, into the helium leak detector to give an indication. When the pressure in chamber A

is further reduced by the mechanical pump to low enough value, valve 1 may be opened and

valve 6 closed for unrestricted passage into

the leak detector.

The fixed leak and the final expanded pressure are of such values that the gas flow

rate into the leak detector does not cause

the detector internal pressure to rise above

operational limits. The maximum allowable

helium concentration in chamber A is then

set by the ratio of the leak detector limit

of indication to the value of the fixed leak

conductance. The minimum detectable indicated leak rate at any instant is approximately the product of the fixed leak conductance

and the partial pressure of helium in the

mixture surrounding the sample. This mini- mum detectable signal falls off with a time

constant determined by the pumping speed at

the chamber and the chamber volume.

To relate the measured leak rate, Q , to the m

leak size, L, it is necessary to calculate

the pressure in the specimen package at the

time of measurement. Since the test is con- cerned with the measurement of gross leaks,

I Me LD HXHXP 2 FL

Figure 35. Gas handling circuit for rapid

gas cycling technique for measurement of

gross leaks.

49
HERMETICITY

it is assumed that gas transport is essentially described by laminar viscous flow; under the conditions selected in the sequences,

diffusive flow is not a factor.

In the first step, the specimens are back

pressurized. The final internal pressure

Pi is

exp(-Ti/Ti)

exp(-Ti/Ti)

where is the helium pressure during pres- surization, is the pressurization time,

P Is atmosp^eric pressure, the time constant 1

1

VP„2/2P L, and V is the interior

0 t volume of the test package. When the gas

is expanded, the internal pressure falls to

6iPi = Pi 1 +

Ylti

2x1

.-1

Table 14 — Typical Examples of Leak Rates Measured using Rapid Gas Cycling Gross

Leak Test

T

' 1 <5n

1

' 2 5o2 Q /L

1 1 0. 67 0. 947 0.175 0. 39

10 0.6 0.77 0.537 0.789 2.6

100 0.25 0.99 0.257 0.987 0.31

Note

T2 =

P. = P

t n

2 s; t2- =

= b 10 s

atm; Tj =

; T = Ti

J.U ;.. ; tj =

= T2 = V/10

1 s;

L.

Pn Pc (i) (16)

Eq (16) can also be written

where tj is the time interval of gas venting

and expansion. Recharging with nitrogen

causes the internal pressure to increase to

^ n n

1 - /l - Yi6i\

\i + yi&i)

exp(-T2/T2)

1 +

1 - Yi<5

1 + Yl69

;xp(-T2/T2)

where T2 is the recharging time, P^ is the

recharging pressure, and the time constant

T2 = VP^2/2P^L. Finally, the gas is vented,

subjected to a double expansion, and opened

to the leak detector. The internal pressure

at the time of measurement is

52-fP, = P 3

where t2 is the time interval for this step.

The partial pressure of helium in the package is now (P^ - Pq)P2/PiP3 so that the measured leak rate is

Qjn = (Yiai - 1) 5i62^Y2a2 L,

where = Pj./Po ^"^^ "2 = ^n^^^'

To illustrate this result, calculations were

carried out for the case where P = P =5

t n atm, Ti = 10 s, ti = 1 s, T2 = 2 s, and t2 = 10 s. For these conditions = T2 = x - V/10 L where V is given in cubic centimeters

and L is given in atmosphere cubic centimeters per second. Results for time constants

of 1, 10, and 100 s are given in table 14. The calculations show that for these conditions a package with a 1 cm^ internal volume

and a lO"-'- atm-cm^/s leak would evidence a measured leak rate about 0.4 times the leak

size while a package with a 10~^. cm^- Internal

volume and a 10"^ atm'cm^/s leak would evidence a measured leak rate about 0.3 times

the leak size, all within the limits of typical apparatus. For the cases studied, the

helium remaining from the expansion and dilution sequences is negligible compared with

that leaking from the package.

Before the next cycle can begin, the ballast

volumes and associated lines must be pumped.

Pumpdown time is determined by ballast volume, pumping speed, final pressures, and se50
HERMETICITY

quencing. Calculation indicates that a pumpdown time of about 15 s is possible for ballast volumes of 10 H and a mechanical pump

rating of about 2.5 £/s.

(S. Ruthberg and W. A. Cullins)

12.2. Calibration Stand for Gross Leaks

The hermetic test procedures in development

(sec. 12.1) and interlaboratory comparisons

such as those being conducted with tentative

or draft procedures [56,57] in cooperation

with ASTM Committee F-1 on Electronics (NBS

Spec. Pubis. 400-4, p. 67; 400-8, p. 40; and

400-12, pp. 33-34) require correlation of

data to directly measured leaks. A general

purpose vacuum system has been designed

using available components and is being con- structed to provide a facility for the measurement and calibration of gross leaks and vacuum gauges used in such test procedures.

The vacuum circuit is shown schematically in

figure 36; standard symbols [55] are used to indicate the components. Appropriate manifolds may be substituted for the test chamber to permit such procedures as leak measurement by rate-of-rise [58] and precision

pressure point generation with reference to micromanometers for gauge calibration

[59-61]. (S. Ruthberg and W. A. Cullins)

VAC.

Figure 36 . Vacuum circuit for calibration

system for gross leaks and vacuum gauges.

51
13. THERMAL PROPERTIES OF DEVICES

13.1. Thermal Resistance Methods —

Darlington Pairs

In a continuing effort to assess the feasibility of using electrical measurements to determine accurately some of the thermal

properties of integrated Darlington transistors, measurements were made to verify several of the conclusions previously reached

(NBS Spec. Pubis. 400-8, pp. 46-49, and

400-12, pp. 35-37).

Although most integrated Darlingtons are three-terminal devices for which some junction voltages cannot be measured independently, soflie Darlingtons have four terminals

as depicted in figure 37. Since the four

terminals are available for measurement, the

individual emitter-base voltages of both the

input and output transistors (Vj and V2

,

respectively) can be measured directly when

the emitter-only switching method [62] is

used. Measurements were made on a device of

this type to test the validity of the as- sumptions made in deriving an expression for

the thermal resistance of the output transistor, R„^^„, (NBS Spec. Publ. 400-12, p.

37, eq (8))

eJC2 6JC(l+2) ejci (17)

where ^qjq^+2) thermal resistance

determined by measuring the series combination of both emitter-base junctions (using

the voltage Vj2 as the temperature sensitive

parameter) and Rq is the thermal resisr) J LI tance of the input transistor. In a threeterminal device, „ cannot be measured

6 J Cz independently. The assumptions made in deriving eq (17) are that the calibration con- stants for the input and output transistors

are equal and that R . can be measured

9 JCi

with sufficient accuracy.

Most three-terminal Darlingtons contain integral bias resistors. To facilitate com- parison with such devices, two resistors were added externally to the four-terminal

Darlington as shown in figure 37. This is necessary because in the measurement of thermal resistance the presence of bias resistors necessitates a larger measuring current,

I , than would be needed for an isolated dis- m

crete transistor in order to insure that the

junction voltages used as temperature sensitive parameters vary relatively linearly

with temperature.

The calibration constants of the individual

transistors of the four terminal Darlington were determined for measuring currents of 7 and 50 mA . The results are listed in table

15. It can be seen that for I = 50 mA they

m

are essentially equal, v/hereas for I = 7 mA

m there is a significant difference in their

values. Thus, the assumption that the input

and output transistors in an integrated Dar- lington pair have equal calibration con- stants appears to be reasonable if large

values of I are used. m

A series of thermal resistance measurements

was made on the four-terminal Darlington

under various conditions. The results are summarized in table 16.

The thermal resistance, R , of the input

6 JCI transistor, Qj, was measured in three ways. First, the voltage Vj was used as the tem- perature sensitive parameter (TSP) with I m

7 or 50 mA and emitter-only switching [62].

This measurement is identical to that which

would be performed on a discrete transistor

if the emitter-base voltage were used as the

TSP. Next, the voltage Vj^2 used as the

TSP, with emitter-only switching and a mea- suring current chosen large enough to turn

Ql on but small enough to keep Q2 , the output transistor, off. The appropriate value

depends on the magnitudes of Rj and R2 and

their ratio; in the present case I =1 mA. m Finally the collector-base voltage, V , was used as the TSP with I =1 mA and m emitter-and-collector switching (NBS Tech.

Note 743, pp. 34-35). This is sometimes

necessary because the ratio or magnitudes of

Rj and R2 may be such as to preclude a suitable measure of R^Tr-i from V12 using a small

value of I^. The collector-base junction

voltage is accessible on both three-terminal

and four-terminal Darlingtons (NBS Spec.

Publ. 400-12, p. 36). All three methods

yielded essentially the same result for

^ejci"

The thermal resistance, ^qjq2^ °^ output

transistor, Q2 , was measured directly by using the voltage V2 as the TSP with = 7 and 50 mA and emitter-only switching. Direct measurements of RgjQ2 "-ising the collector-base junction of Q2 as the temperature sensitive parameter proved unreliable

52
THERMAL PROPERTIES OF DEVICES

Figure 37. Four- terminal Darlington transistor with external resistors. (R^ = 100 Q; R2 = 2200 Q.)

Table 15 — Calibration Constants for

a Four-Terminal Darlington Pair

Transi stor I , mA

m Constant, mV/°C

Input 7 2.148

Output 7 1 .883

Input 50 2.129

Output 50 2.029

Table 16 — Thermal Resistance Measurements on Four-Terminal Darlington

Temperature

Sensi ti ve Parameter

Switching

Method mA QuantityDetermined °C/W

^1 emi tter-only 7 '^eJCl 3.00

^1 emi tter-only 50

'^eJCl 3.00

^12 emi tter-only 1 R ^ 9JC1

2.96

^CBl

emi tter-and-col lector 1 '^eJCl 2.92

'2 emi tter-only 7 ^eJC2

5.12

h

emitter-only 50

^eJC2

4.84

emitter-only 7 '^eJC(l+2)

3.90

hz emi tter-only 50

'^eJC(l+2)

3.84

Computed from eq (17) 7b

•^9002 4.84

Computed from eq (17) 50^^ '^eJC2 4.72

Value of Rq,„-, used in computation.

Value of I used for measuring P„,„/, „s.

53
THERMAL PROPERTIES OF DEVICES

Table 17 — Thermal Resistance Measurements

Integrated Darlington Transistors

on

Device °c/w

IC, A V

'^eJCl

°C/w

"^600(1+2)'

°C/W

^0JC2'

°C/W

(Computed)

'^eJC2

°C/W

(IR) T a 1.5 0.25 80 0.70 5.5 10.30 12.7

^2^ 1.5 0.25 76.5 0.61 4.05 7.49 10.7

^2 1.5 1.0 20 0.61 1 .09 1.57 1 .80

6M-1^ 1 .75 3.5 20 0.59 1.13 1 .67 2.19

1 .75 3.5 20 0.60 1.10 1 .60 1 .80

These operating conditions caused a severe current constriction.

Devices 6M-1 and N-2 5 bear same "2N" number but differ significantly in construction.

70 75

VcE (volts)

Figure 38. Voltage between output emitter

and input base as a function of the

collector-emitter voltage of the output

transistor for a constant collector current

showing onset of hot spot formation and

thermal hysteresis. (I = 0.25 A.)

54
THERMAL PROPERTIES OF DEVICES

because they varied greatly witli the magnitude of I . The results of these measurein merits are therefore not included in the

table.

Measurements of V^o at relatively large

values of I using emitter-only switching

m

result in values of thermal resistance,

^JC(l+2)' intermediate between R^^^^ and

R . ^iThile these values of thermal resis0 JC2 tance are significantly lower than the directly measured value of R , they can be

y J Lz combined with R^j^-. (measured using Vip and

6 J LI

I =1 mA) according to eq (17) to compute

m

R. . The calculated values are also list0 JLz

ed in table 16 where it can be seen that

they are 5. 5 and 2. 5' percent below the

values measured directly with I =7 and m

50 mA, respectively.

Measurements were made on several other devices to further test the validity of eq

(17). The results of these measurements,

all made on three terminal devices, are listed in table 17. Listed are the value

specified by the manufacturer for the

thermal resistance, RQ^r-! operating condi9 J L tions; R„ measured using a low value of

0 J LI measuring current; ^^qjqq+o) measured using

a high value of measuring current; R „ 0 J L Z computed from eq (17); and R . measured by

0 JLz means of an infrared microradiometer . The

agreement between the computed R and the

0 JLz infrared measured R^ is not significantly

0 J LZ different than might be expected for measurements on discrete 'devices even in the cases where a severe current constriction

occurs

,

As noted in table 17, the output transistor

of device T2 had a severe current constriction for two of the operating conditions

listed. It was found that the input-base

current changed only from 4.00 to 4.06 mA

when the constriction formed. Thus, in contrast to the case for a discrete transistor

[63] the dc current gain does not provide a satisfactory indicator of the formation of current constrictions in Darlingtons. This

is because of the small magnitude of the

input base current, particularly for the

high voltage-low current case where severe

current constriction and thermal hysteresis

occur, and also because of the bypass effect

of the bias resistors. However, the voltage

V12 between the input-base and outputemitter measured during the power-off portion of the emitter-only switching method of

the thermal resistance measuring cycle was

found to be an excellent substitute. This

is illustrated for device T2 in figure 38 which shows V12 as a function of collectoremitter voltage, V , for a collector curCE rent, I^, of 0.25 A as the current constriction forms and the device goes through

thermal hysteresis. (S. Rubin)

13.2. Transient Thermal Response

l\'ork continued on the development of a measurement technique based upon electrical

measurements for estimating the peak junction temperature of power transistors. This

technique requires that the total available

active area of the device, A^, be known because it is assumed that the low level sampling current, I , is uniformly distributed m

throughout A^ during calibration, but that

I is confined to the area of power generam

tlon, Aj^,, during measurement. As discussed

previously (NBS Spec. Publ . 400-12, pp. 37-40), if Aj, is known, the calibration

curve can be corrected to account for the

increased sampling current density during

measurement

.

Measurements made on numerous devices showed

that the heating response of a device can be

used to estimate A^ satisfactorily. If it

is assumed that the current is uniformly

distributed throughout A^ during the heating

pulse, that the heat flow is one dimensional, and that the principle of superposition

can be applied, the total available active

area of the device is given by

2P [v^ti + t2 ^T

= /pkc [T(t2) - T(0)]

(18)

where P is the power applied during the

pulse in watts, p is the mass density in

gram per cubic centimetre, k is the thermal

conductivity in watts per centimeter kelvin,

c is the thermal capacity in watt seconds

per gram kelvin, tj is the width of the

heating pulse in seconds, t2 is the time

55
THERMAL PROPERTIES OF DEVICES

between the end of the heating pulse and the

measurement in seconds, T(t2) is the junction temperature at the time of measurement

in degrees Celsius, and T(0) is the junction

temperature before power is applied in degrees Celsius. The power applied must be

great enough to raise the junction temperature by at least 30°C to achieve adequate

measurement precision. The pulse width was

chosen as 1 ms because this pulse width is generally long enough to result in a satisfactory temperature rise for reasonable

power levels while it is not too long to invalidate the assumption of uniform current

distribution. This is most likely to be the

situation for current levels near but below

the maximum allowed current, I„, for

C(max)

the device. Measurements were made on a number of devices with the result that the

value of calculated from eq (18) usually

varied by less than 10 percent when the

heating current varied from V,I^, , to C(max)

Eq (18) contains a correction to C(max)

allow for cooling during the delay following

the end of the heating pulse. This delay is

necessary to allow electrical switching

transients to subside before a reliable

electrical measurement can be made.

The computer model used to simulate the tem- perature distribution on the surface of a silicon chip heated in a central region was refined by the inclusion of a copper slug

between the chip and the heat sink. The re- sults of Kokkas [64] were used for this re- finement which enables the model to simulate

better an actual device. Curves of the

electrically measured average junction tem- perature expressed as a fraction of the peak

junction temperature are plotted against the

effective size of the heat source at steady

state in figure 39. The three curves are

for chips 100 mil (2.5 mm), 150 mil (3.8 mm)

and 200 mil (5.1 mm) on a side. The silicon

chip was chosen to be 10 mil (0.25 mm) thick.

These curves are for the silicon chip resting on a copper slug, 50 mil (1.3 mm) thick,

which in turn rests on an infinite heat sink.

It is interesting to note that the inclusion

of the copper slug has an insignificant effect on the curve for the 100 mil chip previously reported (NBS Spec. Publ . 400-12,

pp. 39-40). However, the curves for the 150

mil and 200 mil chips do show differences

between the two models. (D. L. Blackburn)

1 10 HEAT SOURCE AREA |mm^l

Figure 39. Electrically measured average

junction temperature as a function of the area of heat source. (Curve A: side of chip,

100 mil (2.5 mm); Curve B: side of chip,

150 mil (3.8 mm); Curve C: side of chip,

200 mil (5.1 mm).)

56
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.

31. Hartman, D. K., Glasbrenner, F. K., and

Colangelo, D., Part I Manufacturing In- Process Control and Measuring Techniques of Mask Evaluations, AF>fL-TR- 69-334 Technical Report, December 1970.

(Available to qualified requestors

from the Defense Documentation Center,

Cameron Station, Alexandria, Virginia

22314, Accession No. AD 881208.)

32. Bourdelais, R. J., Colangelo, D.,

McFadyen, R. J., and Elliott, J. F.

,

Instrument for Automatically Inspection Integrated Circuit Masks for Pinholes and Spots, U.S. Patent

3,795,452, March 5, 1974. (Governmentowned invention available for licensing; copy of patent available from

Commissioner of Patents, Washington,

D. C. 20231.)

33. Cook, H. D. , and Marzetta, L. A., An Automatic Fringe Counting Interferometer for use in the Calibration of

Line Scales, J. Res. Natl. Bur. Stand.

(U.S.) 65C, 129-139 (1961).

34. Gentry, F. E., Gutzwiller, F. W.

,

Holonyak, Jr., N., and Von Zastrow,

E. E., Semiconductor Controlled Rectifiers, pp. 42-52 (Prentice-Hall, Inc.,

Englewood Cliffs, New Jersey, 1964).

35. Grove, A. S., Physics and Technology

of Semiconductor Devices, pp. 264-271

(John Wiley and Sons, Inc., New York,

1967) .

36. Buehler, M. G., Impurity Centers in

p-n Junctions Determined from Shifts

in the Thermally Stimulated Current

and Capacitance Response with Heating

Rate, Solid-State Electronics 15 , 69-79 (1972).

37. Goetzberger, A., and Nicollian, E. H.,

MOS Avalanche and Tunneling Effects

in Silicon Surfaces, J. Appl. Phys.

38, 4582-4588 (1967).

58
REFERENCES

38. Green, D., Sandor, J. E. , O'Keeffe, T. W. , and Matta, R. K. , Reversible

Changes in Transistor Characteristics

Caused by Scanning Electron Microscope

Examination, Appl. Phys. Letters 6_, 3-4 (1965).

39. Thornton, P. R. , Hughes, K. A., Kyaw,

H., Millward, C, and Sulway, D. V.,

Failure Analysis of Microcircuitry by

Scanning Electron Microscopy, Mioroeleatronias and Reliability 6^, 9-16

(1967)

Illinois, 1969).

48. Thomas, A. G., Butler, S. R. , Goldstein, J. I., and Parry, P. D., Electron Beam Irradiation Effects in ThickOxide MOS Capacitors, IEEE Trans. Nual.

Soi. NS-21 , No. 4, 14-19 (1974).

49. Cohen, S., and Hughes, H. , SEM Irradiation for Hardness Assurance Screening and Process Definition, IEEE Trans.

Nual. Sci. NS-21 , No. 6, 387-389

(1974)

40. Lipman, J. A., Bruncke, W. C. , Crosthwait, D. L., Galloway, K. F., and

Pease, R. L. , Use of a Scanning Electron Microscope for Screening Bipolar

Surface Effects, IEEE Trans, llual. Soi.

NS-21 , No. 6, 383-386 (1974).

41. Pease, R. L., and Galloway, K. F. , Degradation of Bipolar Transistor Electrical Parameters During SEM Evaluation,

Mioroeleatronias and Reliability 13 , 549-550 (1974).

42. Snow, E. H., Grove, A. S., and Fitzgerald, D. J., Effects of Ionizing Radiation on Oxidized Silicon Surfaces and

Planar Devices, Proa. IEEE 55_, 1168-

1185 (1967).

43. Szedon, J. R. , and Sandor, J. E., The

Effect of Lov7-Energy Electron Irradiation of Metal-Oxide-Semiconductor

Structures, Appl. Phys. Letters 6_, 181-

182 (1965).

44. Speth, A. J., and Fang, F. F., Effects

of Low-Energy Electron Irradiation on

Si-Insulated" Gate FETs, Appl. Phys.

Letters ]_, 145-146 (1965).

45. Simons, M., Monteith, K. L., and Hauser, J. R., Some Observations on Charge

Buildup and Release in Silicon Dioxide

Irradiated with Low Energy Electrons,

IEEE Trans. Electron Devices ED-15 , 966-973 (1968).

46. MacDonald, N. C, and Everhart, T. E.,

Selective Electron-Beam Irradiation of

Metal-Oxide-Semiconductor Structures

,

J. Appl. Phys. 39_, 2433-2447 (1968).

47. MacDonald, N. C, Quantitative Scanning

Electron Microscopy: Solid State Applications, Ocannin/j Electron tHcroScopy/l'jC/J , 0. Johari and I. Corvln,

eds., pp. 431-437 (IITRI, Chicago,

50. Everhart, T. E., and Hoff, P. H., Determination of Kilovolt Electron

Energy Dissipation vs. Penetration Distance in Solid Materials, J. Appl.

Phys. 42_, 5837-5846 (1971).

51. Bishop, H. E., Electron Scattering in

Thick Targets, Brit. J. Appl. Phys.

18_, 703-715 (1967).

52. Pugh, J. W. , The Temperature Dependence

of Preferred Orientation in Rolled

Tungsten, Trans. AIME 212, 637-642

(1958)

53. Swalin, R. A., and Geisler, A. H., The

Recrystallization Process in Tungsten

as Influenced by Impurities, J. Inst. Metals 86_, 129-134 (1957).

54. Robinson, Dr., C. S., Rate of Crystal

Growth in Drawn Tungsten Wire as a Function of Temperature, J. Appl. Phys.

22, 647-651 (1942).

55. Graphic Symbols in Vacuum Technology,

Am. Vac. Soc. Standard 7.1-1966, J. Vac. Sci. Teahnol. 4_, 139-142 (1967).

56. Tentative Recommended Practices for

Determining Hermeticity of Electron

Devices with a Helium Mass Spectrometer

Leak Detector, ASTM Designation

F 134, Annual Book of ASTM Standards,

Part 43 (November 1974). (Available

as a separate reprint from American

Society for Testing and Materials,

1916 Race Street, Philadelphia, Pennsylvania, 19103.)

57. Draft Recommended Practices for Determining liermeticity of I'lectron Devices

by a Radioisotope Test, ASTM Committee

F-1 Draft 8005 (unpublished).

58. Method for Vacuum Leak Calibration,

Am. Vac. Soc. Standard 2.2-1968, J.

59
REFERENCES

Vac. Soi. Teahnol. 5_, 219-222 (1968).

59. Ruthberg, S., Calibration to High Precision in the Medium Vacuum Range with

Stable Environments and Micromanometer

,

J. Vac. Soi. Teohnol. 6_, 401-412

(1969)

.

60. Procedure for Calibrating Vacuum Gauges

of the Thermal Conductivity Type, Am, Vac. Soc. Standard 6.2-1969, J. Vac. Soi. Teahnol. b, 977-980 (1969).

61. Procedure for Calibrating Hot Filament

Ionization Gauges Against a Reference

Manometer in the Range 10""^ to 10~^

Torr, Am. Vac. Sec. Standard 6.4-1969,

J. Vap. Sai. Technol. 1_, 370-374

1970)

.

62. Thermal Resistance Measurements of Conduction Cooled Power Transistors,

JEDEC Publication No. 91, August 1974,

(Available from Engineering Department,

Electronic Industries Association, 2001

Eye Street, N.W., Washington, D. C. 20006.)

63. Gettinger, F. F., and Rubin, S., The Use of Current Gain as an Indicator

for the Formation of Hot "Spots Due to Current Crowding in Power Transistors,

Tenth. Annual Proceedings , Reliability

Physics 1972, Las Vegas, Nevada, pp. 12-18. (Available from Publication

Sales Dept., The IEEE, 345 E. 47th

Street, New York, New York 10017,

Catalog No. 72CH0628-8-PHY)

.

64. Kokkas , A. G. , Thermal Analysis of

Multiple-Layer Structures, IEEE Trans. Electron Devices ED-21 , 674-681 (1974).

60
APPENDIX A SEfllCONDUCTOR TECHNOLOGY PROGRAfl STAFF

Coordinator: J. C. French*

Secretary: Miss B. S. Hope*

Consultant: C. P. MarsdenHh

F. H. Brewer

Miss F, C. Butler"*"

M, Cosman

Mrs. K. E. Dodson"*^

Dr. J. R. Ehrstein

Semiconductor Characterization Section

(301) 921-3625

Dr. W. M. Bullis, Chief

Dr. M. G. Buehler, Asst. Chief

Dr. R. Y. Koyama

Dr. A. G. Lieberman

R. L. Mattis

Dr. S. Mayo

Dr. W. E. Phillips

Miss D. R. Ricks

L. M. Smith

Mrs. M. L. Stream"*" W. R. Thurber

Dr. J. H. Albers

Mrs. C. A. Cannon

W. A. Cullins

G. G. Harman

Semiconductor Processing Section

(301) 921-3541

Dr. A. H. Sher, Chief

S. Ruthberg, Asst. Chief — Assembly

H. A. Schafft, Asst. Chief — Processing

Miss D. L. Hines

H. K. Kessler

J. Krawczyk

T. F. Leedy

Y. M. Liu

+

Dr. D. B. Novotny

R. L. Raybold

I . Szabo

Mrs. E. Y. Trager

D. W. Berning

D. L. Blackburn

H. E. Dyson

Dr. K F. Galloway

Mrs, A. D. Glover+

Electron Devices Section

(301) 921-3622

F. Gettinger, Acting Chief

W. J. Keery

Mrs. K. 0. Leedy

Dr. D. C. Lewis

Mrs. B. A. Oravec^"*"

M. K. Phillips

G. J. Rogers

S. Rubin

D. E. Sawyer

M. W. Stoops^

L. R. Williams

H Part Time

+ Secretary

" Telephone: (301) 921-3357

t Telephone: (301) 921-3621

61
APPEflDIX B

S E M I C 0 n D U C T 0 R T E C H f] 0 L 0 G Y P R 0 G R A f1 P U B L I C A T I 0 fl S

B.l. Prior Reports

A review of the early work leading to this Program is given in Bullis, V,'. M. , Measurenent

Methods for the Semiconductor Device Industry — A Review of MBS Activity, >;ES Tech. Note

511 (December 1969).

Progress reports covering the period July 1, 1968, through June 30, 1973, were published

as NBS Technical Notes with the title, Methods of Measurement for Semiconductor Materials.

Process Control, and Devices:

Quarter Ending NBS Tech. ti'ote Date Issued NTIS Accession

eptember 30, 1968 472 December 1968 AL 681330

Jecemoer j±, lybo /, 1 ^ reDruar/ lyoy AD f^P DC jOP Tip WCf March 31, 1969 488 July 1969 AL 692232

June 30, 1969 495 September 1969 AD 695820

September ju, iyoy i.iarcn ly /'j PJJ 702833

December 31, 1969 527 May 1970 {Jj 710906

March 31, 1970 555 September 1970 AD 718534

June 30, 1970 560 November 1970 AD 719976

September 30, 1970 571 April 1971 AD 723671

December 31, 1970 592 August 1971 AD 728611

March 31, 1971 598 October 1971 AD 732553

June 30, 1971 702 November 1971 AD 734427

September 30, 1971 717 April 1972 AD 740674

December 31, 1971 727 June 1972 AD 744946

March 31, 1972 733 September 1972 AD 748640

June 30, 1972 743 December 1972 AD 7536^2

September 30, 1972 754 March 1973 AD 757244

December 31, 1972 773 May 1973 AD 762840

March 31, 1973 788 August 1973 AD 766918

June 30, 1973 806 November 197 3 AD 771018

After July 1, 1973, pro gress reports were issued in the NBS Special Publication1 400 si series with the title. Semiconductor Measurement Technology

Quarter Ending NBS Spec. Publ. Date Issued NTIS Accession

September 30, 1973

December 31, 197 3) March 31, 1974 / June 30, 1974

September 30, 1974

400-1

400-4

400-8

h00-12

March 1974

November 1974

February 1975

May 1975

AD 775919

COM 74-51222

AD/A 005669

AD/A 011121

B.2. Current Publications

As various phases of the work are completed, publications are prepared to sunmarize the

results or to describe the work in greater detail. Publications of this kind which have

been issued recently are listed below:

Ciarlo, D. R. , Schultz, P. A., and Novotny, D. B., Automated Inspection of IC Photomasks,

Proc. Soa. Pkoto-Optiaal Instrwnentation Engineers, Vol. 55, Technological Advances in

Micro and Sub-Micro Photofabrication Imagery, Society of Photo-Optical Instrumentation

Engineers, San Diego, California, August 21-23, 1974, pp. 84-89.

Marsden, C. P., Tabulation of Published Data on Electron Devices in the U.S.S.R. Through

December 1973, NBS Technical Note 835 (November 1974). (Supersedes NBS Technical Note

715.)

62
APPENDIX B

Ehrstein, J. R., Ed., Semioonduetor Measurement Technology: Spreading Resistance Symposium, NBS Spec. Publ. 400-10 (December 1974).

Schafft, H. A., Semioonduetor Measurement Technology: ARPA/NBS Workshop II. Hermeticity

Testing for Integrated Circuits, NBS Spec. Publ. 400-9 (December 1974).

Ehrstein, J. R., Improved Surface Preparation for Spreading Resistance Measurements on p-Type Silicon, Semiconductor Measurement Technology : Spreading Resistance Symposium,

J. R. Ehrstein, Ed., NBS Spec. Publ. 400-10 (December 1974), pp. 249-255.

Rogers, G. J., Sawyer, D. E., and Jesch, R. L., Semiconductor Measurement Technology:

Measurement of Transistor Scattering Parameters, NBS Spec. Publ. 400-5 (January 1975).

Sher, A. H. , Semiconductor Measurement Technology: Improved Infrared Response Technique

for Detecting Defects and Impurities in Germanium and Silicon p-i-n Diodes, NBS Spec.

Publ. 400-13 (February 1975).

Lewis, D. C., On the Determination of the Minority Carrier Lifetime from the Reverse Re- covery Transient of p?;R Diodes, Solid-State Electronics 18_, 87-91 (January 1975).

Blackburn, D. L., An Electrical Technique for the Measurement of the Peak Junction Temperature of Power Transistors, Thirteenth Annual Proceedings j Reliability Physics 1975, Las Vegas, Nevada, April 1-3, 1975, to appear.

Blackburn, D. L., and Gettinger, F. F., Transient Thermal Response of Measurements of

Power Transistors, IEEE Trans. Industrial Electronics and Control Instrumentation

IECI-22 , 134-141 (May 1975).

Galloway, K. F., Keery, W. J., and Leedy, K. 0., Integrated Circuit Damage Resulting from

SEM Examination, Proc. 25th Annual Electronic Components Conference, Washington, D. C,

May 12-14, 1975, pp. 263-266.

Buehler, M. G., Planar Test Structures for Characterizing Impurities in Silicon, Extended

Abstracts of the Meeting of the Electrochemical Society, Toronto, Ontario, May 11-16,

1975, pp. 403-404.

Rubin, S., Thermal Resistance Measurements on Monolithic and Hybrid Darlington Power Transistors, Proceedings 1975 IEEE Power Electronics Specialists Conference (PESO, Culver

City, California, June 9-11, 1975, to appear.

Kraft, R., Finite Difference Techniques for Diffusion and Redistribution Problems with

Segregation-type Boundary Conditions, Proceedings of the AICA International Symposium on Computer Methods for Partial Differential, Equations, Lehigh University, Bethlehem, Pa., June 17-19, 1975, pp. 328-334.

B.3. Availability of Publications

In most cases reprints of articles in technical journals may be obtained on request to the author. NBS Technical Notes and Special Publications are available from the Superintendent of Documents, U.S. Government Printing Office, Washington, D. C. 20402, or the

National Technical Information Service, Springfield, Virginia 22161, or both. Current

information regarding availability of all publications issued by the Program is provided

in the latest edition of NBS List of Publications No. 72 which can be obtained on request

to Mrs. K. 0. Leedy, Room B346, Technology Building, National Bureau of Standards, Washington, D. C. 20234.

B.4. Videotapes

Color videotape cassette presentation on improvements in semiconductor measurement

63
APPENDIX B

technology are being prepared for the purpose of more effectively disseminating the re- sults of the work to the semiconductor industry. These videotapes are available for distribution on loan without charge on request to H. A. Schafft, Room A317, Technology Building, National Bureau of Standards, Washington, D. C. 20234. Copies of these videotapes

may be made and retained by requestors. The first videotape. Defects in PN Junctions and

MOS Capacitors Observed Using Thermally Stimulated Current and Capacitance Measurements,

by M. G. Buehler has been completed and released for distribution. As an added feature,

arrangements can be made for the author to be available for a telephone conference call

to answer questions and provide more detailed information, following a prearranged showing of the videotape.
APPENDIX C WORKSHOP AND S Y Tl P 0 S I U f-l SCHEDULE

C.l. Proceedings or Reports of Past Events: Symposium on Silicon Device Processing, Gaithersburg, Maryland, June 2-3, 1970.

(Cosponsored by ASTM Committee F-1 and NBS) . Proceedings: NBS Spec. Publ . 337

(November 1970)

.

ARPA/NBS Workshop I. Measurement Problems in Integrated Circuit Processing and Assembly, Palo Alto, California, September 7, 1973. Report: NBS Spec. Publ. 400-3

(January 1974)

.

ARPA/NBS Workshop II. Hermeticity Testing for Integrated Circuits, Gaithersburg,

Maryland, March 29, 1974. Report: NBS Spec. Publ. 400-9 (December 1974).

Spreading Resistance Symposium, Gaithersburg, Maryland, June 13-14, 1974. (Cosponsored by ASTM Committee F-1 and NBS). Proceedings: NBS Spec. Publ. 400-10

(December 1974)

.

ARPA/NBS Workshop III. Test Patterns, Scottsdale, Arizona, September 6, 1974.

Report: NBS Spec. Publ. 400-15 (to appear).

ARPA/NBS Workshop IV. Surface Analysis for Silicon Devices, Gaithersburg, Maryland,

April 23-24, 1975. Report: NBS Spec. Publ. 400-23 (to appear).

C.2. Calendar of Future Events:

Reliability Technology for Cardiac Pacemakers, Gaithersburg, Maryland, July 28-29,

1975 (Workshop cosponsored by Food and Drug Administration and NBS)

.

65
APPENDIX D STANDARDS COnniTTEE ACTIVITIES

ASTM Committee F-1 on Electronics

J. H. Albers, Secretary, Packaging Subcommittee; Hybrid Microelectronics Subcommittee

M. G. Buehler, Chairman, Task Force on Test Patterns, Process Controls Section; Semiconductor Crystals and Semiconductor Measurements Subcommittees

W. M. Bullis, Secretary; Editor, Semiconductor Crystals Subcommittee

J. R. Ehrstein, Chairman, Resistivity Section; Semiconductor Crystals and Semiconductor Measurements Subcommittees

J. C. French, Chairman, Editorial Subcommittee; Awards Committee

G. G. Harman, Secretary, Interconnection Bonding Section; Hybrid Microelectronics

Subcommittee

K. 0. Leedy, Chairman, Packaging Subcommittee; Chairman, Interconnection Bonding

Section; Hybrid Microelectronics and Quality and Hardness Assurance Subcommittees

D. C. Lewis, Semiconductor Measurements and Quality and Hardness Assurance Subcommittees

C. P. Marsden, Honorary Chairman

R. L. Kattis, Editor, Semiconductor Measurements Subcommittee; Semiconductor Crystals

Subcommittee

J. F. Mayo-Wells, Secretary, Editorial Subcommittee

D. B. Novotny, Editor, Semiconductor Processing Materials Subcommittee

W. E. Phillips, Chairman, Lifetime Section; Secretary, Semiconductor Crystals Subcoimnittee; Semiconductor Processing Materials, Semiconductor Measurements, and

Hybrid Microelectronics Subcommittees

G. J. Rogers, Quality and Hardness Assurance Subcommittee

S. Ruthberg, Chairman, Hermeticity Section; Semiconductor Processing Materials,

Hybrid Microelectronics, and Quality and Hardness Assurance Subcommittees

H. A. Schafft, Chairman, Publicity Committee

A. H. Sher, Semiconductor Crystals, Semiconductor Processing Materials, and Hybrid

Microelectronics Subcommittees

W. R. Thurber, Semiconductor Crystals and Semiconductor Measurements Subcommittees

ASTM Committee E-10 on Radioisotopes and Radiation Effects

W. M. Bullis, Subcommittee 7, Radiation Effects on Electronic Materials

J. C. French, Subcommittee 7, Radiation Effects on Electronic Materials

D. C. Lewis, Subcommittee 7, Radiation Effects on Electronic Materials

Electronic Industries Association: Solid State Products Division, Joint Electron Device

Engineering Council (JEDEC)

F. F. Oettinger, Chairman, Task Group JC-11.3-1 on Thermal Considerations for Microelectronic Devices, Committee JC-11.3 on Mechanical Standardization for Microelectronic Devices; Chairman, Task Group JC-25-5 on Thermal Characterization of

Power Transistors, Committee JC-25 on Power Transistors; Technical Advisor,

Thermal Properties of Devices, Committees JC-13.1 on Government Liaison for Discrete Semiconductor Devices, JC-22 on Rectifier Diodes and Thyristors, JC-20 on Signal and Regulator Diodes, and JC-30 on Hybrid Integrated Circuits

S. Rubin, Chairman, Council Task Group on Galvanomagnetic Devices I

66
APPENDIX D

D. E. Sawyer, Task Group JC-24-5 on Transistor Scattering Parameter Measurement

Standard, Committee JC-24 on Low Power Transistors

H. A. Schafft, Technical Advisor, Second Breakdown and Related Specifications Committee JC-25 on Power Transistors

Electronic Industries Association: Government Products Division

F. F. Oettlnger, Chairman, Task Group G-12-08-74 on Recommendations for Military Usage

of Proposed Standards and Test Methods for Thermal Resistance, Committee G-12 on Solid State Devices

IEEE Electron Devices Group

J. C. French, Standards Committee

F. F. Oettlnger, Standards Committee Task Force on Second Breakdown Measurement Standards

H. A. Schafft, Standards Committee Task Force on Second Breakdown

Measurement Standards

IEEE Magnetics Group

S. Rubin, Chairman, Galvanomagnetlc Standards Subcommittee

Society of Automotive Engineers

J. C. French, Subcommittee A-2K on Radiation Hardness and Nuclear Survivability

W. M. Bullls, Planning Subcommittee of Committee H on Electronic Materials and Processes

lEC TC47, Semiconductor Devices and Integrated Circuits

S. Rubin, Technical Expert, Galvanomagnetlc Devices; U.S. Specialist for Working

Group 5 on Hall Devices and Magnetoresistive Devices

67
APPENDIX E

SOLID-STATE TECHNOLOGY a FABRICATION SERVICES

Technical services in areas of competence are provided to other NBS activities and other

government agencies as they are requested. Usually these are short-term, specialized

services that cannot be obtained through normal commercial channels. Such services provided during the last quarter, which are listed below, indicate the kinds of technology

available to the program.

E.l. Semiconductor Device Fabrication (J. Krawczyk and T. F. Leedy)

MOS capacitors with gates transparent to ultraviolet radiation were fabricated for the

Harry Diamond Laboratories.

E.2. Scribing (J. Krawczyk)

Iron-oxidft-coated glass substrates were cut to size using the wafer scriber for the Harry

Diamond Laboratories.

E.3. Thermocouple Repair (H. K. Kessler)

Miniature multijunction thermocouples were repaired for the NBS Electricity Division.

E.4. Semiconductor Device Assembly (H. K. Kessler)

Silicon wafers containing fifty arrays were diced and mounted to TO-5 headers for the Army

Electronics Command, Fort Monmouth, New Jersey. The interconnections were made by means

of ultrasonic bonding using aluminum and silver ribbon wire. These devices are to be used

for current density studies.

E.5. Scanning Electron Microscopy (W. J. Keery)

Scanning Electron Micrographs were taken of various cement samples for the NBS Materials

and Composites Section.

Scanning electron micrographs were made of diesel exhaust smoke particles for the NBS Fire

Technology Division.

A specimen of a Moire pattern test structure was examined for the NBS Optics and Micrometrology Section.

68
INDEX

acoustic emission 4 ARPA/NBS Workshop on Surface Analysis for

Silicon Devices 65

ARPA/NBS Workshop on Test Patterns 65

ASTM Method F 84 8

base-collector diode 27-28

base window width 22-24

beam-lead bonding 4 bond monitor, in-process 47-48

boron nitride 6-7

boron redistribution 11-13

bridge resistor 22-24

C - C . method 11 max mxn

carbon contamination 18-19

charge-coupled device test pattern 28-31

Darlington pairs 52-55

deep depletion 8, 10-11

diffusion window width 22-24

dopant profiles 8, 10-11

dry gas gross leak tests 49-51

electron beam evaporator 20-21

electron beam induced damage 43-46

electron spectroscopy for chemical analysis

18-19

emitter-only switching method 52-55

epitaxial layer thickness 39-41

filar eyepiece 38

four-probe array, square 25-26

four-probe method 8-9

flying-spot scanner 42-43

furnace qualification tests 3

gold-doped silicon 15-17

gross leak tests 49-51

hermeticity 49-51

hot spot formation 54-55

hydrogen chloride gas 6-7

image shearing eyepiece 38

infrared microradiometer , automatic 5 Irvin's curves 13-14

junction capacitance-voltage 14

laser interf erometry 36 leak rate, calibration 51

line-width standards 36-38

micrometrology 36-38

MIL-STD-750B 5 MOS capacitance-voltage 8, 10-11; 14 MOS capacitor 15-17; 26-27; 28-30

MOS transistor 30-31

NBS-3 test pattern 13; 22-28

over-etch characteristics 22-24

oxidation furnace qualification tests 2

photomask inspection 32-36

photomask measurement 36-38

p-n junction Il-IQ

radioisotope leak test 4 ramp-voltage method 39-41

rapid gas cycling gross leak test 49-51

resistivity standards 8-9

scanning electron microscopy, calibration

36-37

scanning electron microscopy, inspection by

43-46

scanning low energy electron probe 46

sheet resistor 22-24

square array collector resistor 25-26

SRM 1520 8-9

step-relaxation method 39-41

test patterns 22-28; 28-31; 37-38

thermal resistance 52-55

thermal response 55-56

thermally stimulated capacitance 15-17

thermally stimulated current 15-17

transient capacitance methods 39-41

TV/microscope mask inspection system 32-36

ultrasonic bonding 47-48

uniform beam model 47-48

van der Pauw resistor 22-24

x-ray damage 20-21

x-ray photoelectron spectroscopy 18-19

69
NBS-n4A (REV. 7-731

U.S. DEPT. OF COMM. BIBLIOGRAPHIC DATA

SHEET

1. PUBLICATION OR REPORT NO. NBS Spec. Publ. 400-17

2. Gov't Acccssioo

Mo.

3. Recipient's Accession No.

4. TITLE AND SUBTITLE

Semiconductor Measurement Technology:

October 1 to December 31, 1974

Progress Report

5. Publication Date November 1975

6. Performuig Organization Code

7. AUTHOR(S)

W. Murray Bullis, Editor

8. Perfotming Organ. Report No.

9. PERFORMING ORGANIZATION NAME AND ADDRESS

NATIONAL BUREAU OF STANDARDS

DEPARTMENT OF COMMERCE

WASHINGTON. D.C. 20234

10. Project/Task/Work Unit No.

.,11. Contract /Grant No , , ^, „

iSPtk Order 2i9/, Pgia. Code 5D10

DHA lACRO 75-816; SSPO Order

80O16475PO70O30. IPR SP6-75-4

12. Sponsoring Organization Name and Complete Address (Street, City, State, ZIP)

NBS - Washington, D. C. 20234

ARPA - 1400 Wilson Boulevard, Arlington, Va. 22209

DNA - Washington, D. C. 20305

SSPO - Washington, D. C. 20376

13. Type of Report & Period Covered Interim: October

1 to December 31, 1974.

14. Sponsoring Agency Code

16. ABSTRACT (A 200'Word or less factual summary ol most si0iilicant intormatian. It document includes a significant

bibtio^aphy or literature survey, mention it here.) This progress report describes NBS actiijities directed toward the dewelopmeivt of methods of measureiuent for semiconductor laaterials, process control, and devices. The eophasis is on silicon device technologies. Principal accoaplishments during this reporting period include (1) initiation of development of measurement technology for characterizing boron nitride diffusion sources and hydrogen chloride purging

gas, (2) application of dc electrical methods with a sensitivity of about 0-1 pm to the measureiiient of critical dinensions such as the width of diffusion windows, (3) coapletion of an initial conmparijon of line—width measuremients tmade with an image shearing eyepiece and a filar eyepiece, and (4) development

of procedures for measuring electrically the thenmal resistance of the output transistor of integrated

Darlington pairs. Also reported are the intenaediate results of an interlabcratory evaluation of standard reference wafers for resistivity, evaluation of the deep—dep] etion method for measuring dopant

density with an MOS capacitor, progress on deveiopaient of mathematical models of dopant profiles, initial results of the reevaluation of Irwin's curve for »i-type silicon, analysis of thermally stimulated

current and capacitance measurements on MOS capacitors, study of surface carbon contamination which

occurs during eeasurement of silicon by X-ray photoelectron spectroscopy, preliuinary measurements of absorbed dose froa electron—beam evaporation of aluainum filas, initial evaluation of the CCD test structure operating as an liOS capacitor and an MOS transistor, analysis of a TV—microscope systea for photomask inspection, initial study of calibration procedures and artifacts for photomask metrology,

analysis of the range of applicability of MOS C—V methods for epitaxial layer thickness measureaient

,

use of an optical flying-spot scanner, assessment of damage "to selected integrated circuits caused by

inspection with a scanning electron microscope, matheisatical modeling of ultrasonic bonding, a dry gas method for gross leak testing, and measurements of transistor thermal response. Supplesmentary data con- cerning staff, publications, workshops and symposia, standards committee activities, and technical ser- vices are also included as appendices.

17. KEY WORDS (six to twelve entries; alphabetical order; capitalize only the first letter of Bte first key word unless a proper name: separated by semicolons) ^^^^ nitride; boron redistribution; capacitance-voltage methods; Darlington

pairs; deep depletion; dopant profiles; electrical properties; electron beam evaporator; electron beam

epitaxial layer thickness; filar eyepiece; flying-spot scanner; henaetiinage shearing eyepiece; laser interferoaetry; measurement methods; micro— KOS devices; oxide films; photon_ask inspection; resistivity; scanning electron microscope; scanning low energy electron probe; semiconductor devices; seaiconductor materials;

semiconductor process control; silicon; test patterns; themaal resistance; thermal response; thermally

stimulated current; ultrasonic bonding; wire bonds; x-ray photoelectron spectroscopy.

induced damage; electronics

city; hydrogen chloride gas electronics; nicrometrology

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