# Patent

## Title
Methods and apparatus to effect hot reset for an on die non-root port integrated device

## Abstract

In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

## Background
TECHNICAL FIELD
Embodiments relate to power management of a system, and more particularly to power management of a multicore processor.
BACKGROUND
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, UltrabooksTM, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a portion of a system in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram of a processor in accordance with an embodiment of the present invention.
FIG. 3 is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention.
FIG. 4 is an embodiment of a processor including multiple cores.
FIG. 5 is a block diagram of a micro-architecture of a processor core in accordance with one embodiment of the present invention.
FIG. 6 is a block diagram of a micro-architecture of a processor core in accordance with another embodiment.
FIG. 7 is a block diagram of a micro-architecture of a processor core in accordance with yet another embodiment.
FIG. 8 is a block diagram of a micro-architecture of a processor core in accordance with a still further embodiment.
FIG. 9 is a block diagram of a processor in accordance with another embodiment of the present invention.
FIG. 10 is a block diagram of a representative SoC in accordance with an embodiment of the present invention.
FIG. 11 is a block diagram of another example SoC in accordance with an embodiment of the present invention.
FIG. 12 is a block diagram of an example system with which embodiments can be used.
FIG. 13 is a block diagram of another example system with which embodiments may be used.
FIG. 14 is a block diagram of a representative computer system.
FIG. 15 is a block diagram of a system in accordance with an embodiment of the present invention.
FIG. 16 is a block diagram of a system on a chip (SoC), according to an embodiment of the present invention.
FIG. 17 is a flow diagram of a method of effecting a hot reset (or link disable) for an accelerator device, e.g., a direct memory access (DMA) device, according to an embodiment of the present invention.
FIG. 18 is a flow diagram of a method to effect a hot reset (or link disable) for an input/output (I/O) device, e.g., a gigabit Ethernet (GBE) controller, according to embodiments of the present invention.



DETAILED DESCRIPTION
Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems. That is, disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower, rack, blade, micro-server and so forth), communications systems, storage systems, desktop computers of any configuration, laptop, notebook, and tablet computers (including 2:1 tablets, phablets and so forth), and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals having standard voice functionality such as mobile phones, smartphones and phablets, and/or in non-mobile terminals without a standard wireless voice function communication capability, such as many wearables, tablets, notebooks, desktops, micro-servers, servers and so forth. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatuses, and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.
Referring now to FIG. 1, shown is a block diagram of a portion of a system in accordance with an embodiment of the present invention. As shown in FIG. 1, system 100 may include various components, including a processor 110 which as shown is a multicore processor. Processor 110 may be coupled to a power supply 150 via an external voltage regulator 160, which may perform a first voltage conversion to provide a primary regulated voltage to processor 110.
As seen, processor 110 may be a single die processor including multiple cores 120a-120n. In addition, each core may be associated with an integrated voltage regulator (IVR) 125a-125n which receives the primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated and supplied by the IVR to only those components in the group. During power management, a given power plane of one IVR may be powered down or off when the processor is placed into a certain low power state, while another power plane of another IVR remains active, or fully powered.
Still referring to FIG. 1, additional components may be present within the processor including an input/output interface 132, another interface 134, and an integrated memory controller 136. As seen, each of these components may be powered by another integrated voltage regulator 125x. In one embodiment, interface 132 may be in accordance with the Intel® Quick Path Interconnect (QPI) protocol, which provides for point-to-point (PtP) links in a cache coherent protocol that includes multiple layers including a physical layer, a link layer and a protocol layer. In turn, interface 134 may be in accordance with a Peripheral Component Interconnect Express (PCIeTM) specification, e.g., the PCI ExpressTM Specification Base Specification version 2.0 (published Jan. 17, 2007).
Also shown is a power control unit (PCU) 138, which may include hardware, software and/or firmware to perform power management operations with regard to processor 110. As seen, PCU 138 provides control information to external voltage regulator 160 via a digital interface to cause the voltage regulator to generate the appropriate regulated voltage. PCU 138 also provides control information to IVRs 125 via another digital interface to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode). In various embodiments, PCU 138 may include a variety of power management logic units to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or management power management source or system software).
While not shown for ease of illustration, understand that additional components may be present within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of FIG. 1 with an integrated voltage regulator, embodiments are not so limited.
Note that the power management techniques described herein may be independent of and complementary to an operating system (OS)-based mechanism, such as the Advanced Configuration and Platform Interface (ACPI) standard (e.g., Rev. 3.0b, published Oct. 10, 2006). According to ACPI, a processor can operate at various performance states or levels, so-called P-states, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to ACPI, a processor can operate at various power states or levels. With regard to power states, ACPI specifies different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth).
Understand that many different types of power management techniques may be used individually or in combination in different embodiments. As representative examples, a power controller may control the processor to be power managed by some form of dynamic voltage frequency scaling (DVFS) in which an operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStepTM technology available from Intel Corporation, Santa Clara, Calif., to provide optimal performance at a lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoostTM technology to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (e.g., workload and availability).
Another power management technique that may be used in certain examples is dynamic swapping of workloads between different compute engines. For example, the processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power constrained situation, one or more workloads can be dynamically switched to execute on a lower power core or other compute engine. Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and/or other compute engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be made inactive during an inactive period of the duty cycle and made active during an active period of the duty cycle. Although described with these particular examples, understand that many other power management techniques may be used in particular embodiments.
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to FIG. 2, shown is a block diagram of a processor in accordance with an embodiment of the present invention. As shown in FIG. 2, processor 200 may be a multicore processor including a plurality of cores 210a-210n. In one embodiment, each such core may be of an independent power domain and can be configured to enter and exit active states and/or maximum performance states based on workload. The various cores may be coupled via an interconnect 215 to a system agent or uncore 220 that includes various components. As seen, the uncore 220 may include a shared cache 230 which may be a last level cache. In addition, the uncore may include an integrated memory controller 240 to communicate with a system memory (not shown in FIG. 2), e.g., via a memory bus. Uncore 220 also includes various interfaces 250 and a power control unit 255, which may include logic to perform the power management techniques described herein.
In addition, by interfaces 250a-250n, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment of FIG. 2, the scope of the present invention is not limited in this regard.
Referring now to FIG. 3, shown is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention. As shown in the embodiment of FIG. 3, processor 300 includes multiple domains. Specifically, a core domain 310 can include a plurality of cores 3100-310n, a graphics domain 320 can include one or more graphics engines, and a system agent domain 350 may further be present. In some embodiments, system agent domain 350 may execute at an independent frequency than the core domain and may remain powered on at all times to handle power control events and power management such that domains 310 and 320 can be controlled to dynamically enter into and exit high power and low power states. Each of domains 310 and 320 may operate at different voltage and/or power. Note that while only shown with three domains, understand the scope of the present invention is not limited in this regard and additional domains can be present in other embodiments. For example, multiple core domains may be present each including at least one core.
In general, each core 310 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 3400-340n. In various embodiments, LLC 340 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 330 thus couples the cores together, and provides interconnection between the cores, graphics domain 320 and system agent circuitry 350. In one embodiment, interconnect 330 can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain.
As further seen, system agent domain 350 may include display controller 352 which may provide control of and an interface to an associated display. As further seen, system agent domain 350 may include a power control unit 355 which can include logic to perform the power management techniques described herein.
As further seen in FIG. 3, processor 300 can further include an integrated memory controller (IMC) 370 that can provide for an interface to a system memory, such as a dynamic random access memory (DRAM). Multiple interfaces 3800-380n may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI) interface may be provided as well as one or more PCIeTM interfaces. Still further, to provide for communications between other agents such as additional processors or other circuitry, one or more interfaces in accordance with an Intel® Quick Path Interconnect (QPI) protocol may also be provided. Although shown at this high level in the embodiment of FIG. 3, understand the scope of the present invention is not limited in this regard.
Referring to FIG. 4, an embodiment of a processor including multiple cores is illustrated. Processor 400 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SoC), or other device to execute code. Processor 400, in one embodiment, includes at least two cores—cores 401 and 402, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 400 may include any number of processing elements that may be symmetric or asymmetric.
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 400, as illustrated in FIG. 4, includes two cores, cores 401 and 402. Here, cores 401 and 402 are considered symmetric cores, i.e., cores with the same configurations, functional units, and/or logic. In another embodiment, core 401 includes an out-of-order processor core, while core 402 includes an in-order processor core. However, cores 401 and 402 may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known core. Yet to further the discussion, the functional units illustrated in core 401 are described in further detail below, as the units in core 402 operate in a similar manner.
As depicted, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 400 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 401a, a second thread is associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 401a are replicated in architecture state registers 401b, so individual architecture states/contexts are capable of being stored for logical processor 401a and logical processor 401b. In core 401, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 430 may also be replicated for threads 401a and 401b. Some resources, such as re-order buffers in reorder/retirement unit 435, ILTB 420, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 415, execution unit(s) 440, and portions of out-of-order unit 435 are potentially fully shared.
Processor 400 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In FIG. 4, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 401 includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer 420 to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) 420 to store address translation entries for instructions.
Core 401 further includes decode module 425 coupled to fetch unit 420 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core 401 is associated with a first ISA, which defines/specifies instructions executable on processor 400. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders 425, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 425, the architecture or core 401 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
In one example, allocator and renamer block 430 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where allocator and renamer block 430 also reserves other resources, such as reorder buffers to track instruction results. Unit 430 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 400. Reorder/retirement unit 435 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 440, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 450 are coupled to execution unit(s) 440. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 401 and 402 share access to higher-level or further-out cache 410, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 410 is a last-level data cache—last cache in the memory hierarchy on processor 400—such as a second or third level data cache. However, higher level cache 410 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 425 to store recently decoded traces.
In the depicted configuration, processor 400 also includes bus interface module 405 and a power controller 460, which may perform power management in accordance with an embodiment of the present invention. In this scenario, bus interface 405 is to communicate with devices external to processor 400, such as system memory and other components.
A memory controller 470 may interface with other devices such as one or many memories. In an example, bus interface 405 includes a ring interconnect with a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices, such as a network interface, coprocessors, memory, graphics processor, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Referring now to FIG. 5, shown is a block diagram of a micro-architecture of a processor core in accordance with one embodiment of the present invention. As shown in FIG. 5, processor core 500 may be a multi-stage pipelined out-of-order processor. Core 500 may operate at various voltages based on a received operating voltage, which may be received from an integrated voltage regulator or external voltage regulator.
As seen in FIG. 5, core 500 includes front end units 510, which may be used to fetch instructions to be executed and prepare them for use later in the processor pipeline. For example, front end units 510 may include a fetch unit 501, an instruction cache 503, and an instruction decoder 505. In some implementations, front end units 510 may further include a trace cache, along with microcode storage as well as a micro-operation storage. Fetch unit 501 may fetch macro-instructions, e.g., from memory or instruction cache 503, and feed them to instruction decoder 505 to decode them into primitives, i.e., micro-operations for execution by the processor.
Coupled between front end units 510 and execution units 520 is an out-of-order (OOO) engine 515 that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine 515 may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file 530 and extended register file 535. Register file 530 may include separate register files for integer and floating point operations. Extended register file 535 may provide storage for vector-sized units, e.g., 256 or 512 bits per register.
Various resources may be present in execution units 520, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524, among other such execution units.
Results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) 540. More specifically, ROB 540 may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by ROB 540 to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, ROB 540 may handle other operations associated with retirement.
As shown in FIG. 5, ROB 540 is coupled to a cache 550 which, in one embodiment may be a low level cache (e.g., an L1 cache) although the scope of the present invention is not limited in this regard. Also, execution units 520 can be directly coupled to cache 550. From cache 550, data communication may occur with higher level caches, system memory and so forth. While shown with this high level in the embodiment of FIG. 5, understand the scope of the present invention is not limited in this regard. For example, while the implementation of FIG. 5 is with regard to an out-of-order machine such as of an Intel® x86 instruction set architecture (ISA), the scope of the present invention is not limited in this regard. That is, other embodiments may be implemented in an in-order processor, a reduced instruction set computing (RISC) processor such as an ARM-based processor, or a processor of another type of ISA that can emulate instructions and operations of a different ISA via an emulation engine and associated logic circuitry.
Referring now to FIG. 6, shown is a block diagram of a micro-architecture of a processor core in accordance with another embodiment. In the embodiment of FIG. 6, core 600 may be a low power core of a different micro-architecture, such as an Intel® AtomTM-based processor having a relatively limited pipeline depth designed to reduce power consumption. As seen, core 600 includes an instruction cache 610 coupled to provide instructions to an instruction decoder 615. A branch predictor 605 may be coupled to instruction cache 610. Note that instruction cache 610 may further be coupled to another level of a cache memory, such as an L2 cache (not shown for ease of illustration in FIG. 6). In turn, instruction decoder 615 provides decoded instructions to an issue queue 620 for storage and delivery to a given execution pipeline. A microcode ROM 618 is coupled to instruction decoder 615.
A floating point pipeline 630 includes a floating point register file 632 which may include a plurality of architectural registers of a given bit with such as 128, 256 or 512 bits. Pipeline 630 includes a floating point scheduler 634 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 635, a shuffle unit 636, and a floating point adder 638. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 632. Of course understand while shown with these few example execution units, additional or different floating point execution units may be present in another embodiment.
An integer pipeline 640 also may be provided. In the embodiment shown, pipeline 640 includes an integer register file 642 which may include a plurality of architectural registers of a given bit with such as 128 or 256 bits. Pipeline 640 includes an integer scheduler 644 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 645, a shifter unit 646, and a jump execution unit 648. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 642. Of course understand while shown with these few example execution units, additional or different integer execution units may be present in another embodiment.
A memory execution scheduler 650 may schedule memory operations for execution in an address generation unit 652, which is also coupled to a TLB 654. As seen, these structures may couple to a data cache 660, which may be a L0 and/or L1 data cache that in turn couples to additional levels of a cache memory hierarchy, including an L2 cache memory.
To provide support for out-of-order execution, an allocator/renamer 670 may be provided, in addition to a reorder buffer 680, which is configured to reorder instructions executed out of order for retirement in order. Although shown with this particular pipeline architecture in the illustration of FIG. 6, understand that many variations and alternatives are possible.
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of FIGS. 5 and 6, workloads may be dynamically swapped between the cores for power management reasons, as these cores, although having different pipeline designs and depths, may be of the same or related ISA. Such dynamic core swapping may be performed in a manner transparent to a user application (and possibly kernel also).
Referring to FIG. 7, shown is a block diagram of a micro-architecture of a processor core in accordance with yet another embodiment. As illustrated in FIG. 7, a core 700 may include a multi-staged in-order pipeline to execute at very low power consumption levels. As one such example, processor 700 may have a micro-architecture in accordance with an ARM Cortex A53 design available from ARM Holdings, LTD., Sunnyvale, Calif. In an implementation, an 8-stage pipeline may be provided that is configured to execute both 32-bit and 64-bit code. Core 700 includes a fetch unit 710 that is configured to fetch instructions and provide them to a decode unit 715, which may decode the instructions, e.g., macro-instructions of a given ISA such as an ARMv8 ISA. Note further that a queue 730 may couple to decode unit 715 to store decoded instructions. Decoded instructions are provided to an issue logic 725, where the decoded instructions may be issued to a given one of multiple execution units.
With further reference to FIG. 7, issue logic 725 may issue instructions to one of multiple execution units. In the embodiment shown, these execution units include an integer unit 735, a multiply unit 740, a floating point/vector unit 750, a dual issue unit 760, and a load/store unit 770. The results of these different execution units may be provided to a writeback unit 780. Understand that while a single writeback unit is shown for ease of illustration, in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in FIG. 7 is represented at a high level, a particular implementation may include more or different structures. A processor designed using one or more cores having a pipeline as in FIG. 7 may be implemented in many different end products, extending from mobile devices to server systems.
Referring to FIG. 8, shown is a block diagram of a micro-architecture of a processor core in accordance with a still further embodiment. As illustrated in FIG. 8, a core 800 may include a multi-stage multi-issue out-of-order pipeline to execute at very high performance levels (which may occur at higher power consumption levels than core 700 of FIG. 7). As one such example, processor 800 may have a microarchitecture in accordance with an ARM Cortex A57 design. In an implementation, a 15 (or greater)-stage pipeline may be provided that is configured to execute both 32-bit and 64-bit code. In addition, the pipeline may provide for 3 (or greater)-wide and 3 (or greater)-issue operation. Core 800 includes a fetch unit 810 that is configured to fetch instructions and provide them to a decoder/renamer/dispatcher 815, which may decode the instructions, e.g., macro-instructions of an ARMv8 instruction set architecture, rename register references within the instructions, and dispatch the instructions (eventually) to a selected execution unit. Decoded instructions may be stored in a queue 825. Note that while a single queue structure is shown for ease of illustration in FIG. 8, understand that separate queues may be provided for each of the multiple different types of execution units.
Also shown in FIG. 8 is an issue logic 830 from which decoded instructions stored in queue 825 may be issued to a selected execution unit. Issue logic 830 also may be implemented in a particular embodiment with a separate issue logic for each of the multiple different types of execution units to which issue logic 830 couples.
Decoded instructions may be issued to a given one of multiple execution units. In the embodiment shown, these execution units include one or more integer units 835, a multiply unit 840, a floating point/vector unit 850, a branch unit 860, and a load/store unit 870. In an embodiment, floating point/vector unit 850 may be configured to handle SIMD or vector data of 128 or 256 bits. Still further, floating point/vector execution unit 850 may perform IEEE-754 double precision floating-point operations. The results of these different execution units may be provided to a writeback unit 880. Note that in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in FIG. 8 is represented at a high level, a particular implementation may include more or different structures.
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of FIGS. 7 and 8, workloads may be dynamically swapped for power management reasons, as these cores, although having different pipeline designs and depths, may be of the same or related ISA. Such dynamic core swapping may be performed in a manner transparent to a user application (and possibly kernel also).
A processor designed using one or more cores having pipelines as in any one or more of FIGS. 5-8 may be implemented in many different end products, extending from mobile devices to server systems. Referring now to FIG. 9, shown is a block diagram of a processor in accordance with another embodiment of the present invention. In the embodiment of FIG. 9, processor 900 may be a SoC including multiple domains, each of which may be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, processor 900 may be an Intel® Architecture CoreTM-based processor such as an i3, i5, i7 or another such processor available from Intel Corporation. However, other low power processors such as available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, Calif., an ARM-based design from ARM Holdings, Ltd. or licensee thereof or a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, Calif., or their licensees or adopters may instead be present in other embodiments such as an Apple A7 processor, a Qualcomm Snapdragon processor, or Texas Instruments OMAP processor. Such SoC may be used in a low power system such as a smartphone, tablet computer, phablet computer, UltrabookTM computer or other portable computing device.
In the high level view shown in FIG. 9, processor 900 includes a plurality of core units 9100-910n. Each core unit may include one or more processor cores, one or more cache memories and other circuitry. Each core unit 910 may support one or more instructions sets (e.g., an x86 instruction set (with some extensions that have been added with newer versions); a MIPS instruction set; an ARM instruction set (with optional additional extensions such as NEON)) or other instruction set or combinations thereof. Note that some of the core units may be heterogeneous resources (e.g., of a different design). In addition, each such core may be coupled to a cache memory (not shown) which in an embodiment may be a shared level (L2) cache memory. A non-volatile storage 930 may be used to store various program and other data. For example, this storage may be used to store at least portions of microcode, boot information such as a BIOS, other system software or so forth.
Each core unit 910 may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit 910 couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller 935. In turn, memory controller 935 controls communications with a memory such as a DRAM (not shown for ease of illustration in FIG. 9).
In addition to core units, additional processing engines are present within the processor, including at least one graphics unit 920 which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor 925 may be present. Signal processor 925 may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip.
Other accelerators also may be present. In the illustration of FIG. 9, a video coder 950 may perform coding operations including encoding and decoding for video information, e.g., providing hardware acceleration support for high definition video content. A display controller 955 further may be provided to accelerate display operations including providing support for internal and external displays of a system. In addition, a security processor 945 may be present to perform security operations such as secure boot operations, various cryptography operations and so forth.
Each of the units may have its power consumption controlled via a power manager 940, which may include control logic to perform the various power management techniques described herein.
In some embodiments, SoC 900 may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 960a-960d enable communication with one or more off-chip devices. Such communications may be according to a variety of communication protocols such as PCIeTM GPIO, USB, I2C, UART, MIPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of FIG. 9, understand the scope of the present invention is not limited in this regard.
Referring now to FIG. 10, shown is a block diagram of a representative SoC. In the embodiment shown, SoC 1000 may be a multi-core SoC configured for low power operation to be optimized for incorporation into a smartphone or other low power device such as a tablet computer or other portable computing device. As an example, SoC 1000 may be implemented using asymmetric or different types of cores, such as combinations of higher power and/or low power cores, e.g., out-of-order cores and in-order cores. In different embodiments, these cores may be based on an Intel® ArchitectureTM core design or an ARM architecture design. In yet other embodiments, a mix of Intel and ARM cores may be implemented in a given SoC.
As seen in FIG. 10, SoC 1000 includes a first core domain 1010 having a plurality of first cores 10120-10123. In an example, these cores may be low power cores such as in-order cores. In one embodiment these first cores may be implemented as ARM Cortex A53 cores. In turn, these cores couple to a cache memory 1015 of core domain 1010. In addition, SoC 1000 includes a second core domain 1020. In the illustration of FIG. 10, second core domain 1020 has a plurality of second cores 10220-10223. In an example, these cores may be higher power-consuming cores than first cores 1012. In an embodiment, the second cores may be out-of-order cores, which may be implemented as ARM Cortex A57 cores. In turn, these cores couple to a cache memory 1025 of core domain 1020. Note that while the example shown in FIG. 10 includes 4 cores in each domain, understand that more or fewer cores may be present in a given domain in other examples.
With further reference to FIG. 10, a graphics domain 1030 also is provided, which may include one or more graphics processing units (GPUs) configured to independently execute graphics workloads, e.g., provided by one or more cores of core domains 1010 and 1020. As an example, GPU domain 1030 may be used to provide display support for a variety of screen sizes, in addition to providing graphics and display rendering operations.
As seen, the various domains couple to a coherent interconnect 1040, which in an embodiment may be a cache coherent interconnect fabric that in turn couples to an integrated memory controller 1050. Coherent interconnect 1040 may include a shared cache memory, such as an L3 cache, some examples. In an embodiment, memory controller 1050 may be a direct memory controller to provide for multiple channels of communication with an off-chip memory, such as multiple channels of a DRAM (not shown for ease of illustration in FIG. 10).
In different examples, the number of the core domains may vary. For example, for a low power SoC suitable for incorporation into a mobile computing device, a limited number of core domains such as shown in FIG. 10 may be present. Still further, in such low power SoCs, core domain 1020 including higher power cores may have fewer numbers of such cores. For example, in one implementation two cores 1022 may be provided to enable operation at reduced power consumption levels. In addition, the different core domains may also be coupled to an interrupt controller to enable dynamic swapping of workloads between the different domains.
In yet other embodiments, a greater number of core domains, as well as additional optional IP logic may be present, in that an SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations forth. As one such example, 4 core domains each having a given number of out-of-order cores may be provided. Still further, in addition to optional GPU support (which as an example may take the form of a GPGPU), one or more accelerators to provide optimized hardware support for particular functions (e.g. web serving, network processing, switching or so forth) also may be provided. In addition, an input/output interface may be present to couple such accelerators to off-chip components.
Referring now to FIG. 11, shown is a block diagram of another example SoC. In the embodiment of FIG. 11, SoC 1100 may include various circuitry to enable high performance for multimedia applications, communications and other functions. As such, SoC 1100 is suitable for incorporation into a wide variety of portable and other devices, such as smartphones, tablet computers, smart TVs and so forth. In the example shown, SoC 1100 includes a central processor unit (CPU) domain 1110. In an embodiment, a plurality of individual processor cores may be present in CPU domain 1110. As one example, CPU domain 1110 may be a quad core processor having 4 multithreaded cores. Such processors may be homogeneous or heterogeneous processors, e.g., a mix of low power and high power processor cores.
In turn, a GPU domain 1120 is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth, in addition to advanced calculations that may occur during execution of multimedia instructions. In turn, a communication unit 1140 may include various components to provide connectivity via various wireless protocols, such as cellular communications (including 3G/4G LTE), wireless local area techniques such as BluetoothTM, IEEE 802.11, and so forth.
Still further, a multimedia processor 1150 may be used to perform capture and playback of high definition video and audio content, including processing of user gestures. A sensor unit 1160 may include a plurality of sensors and/or a sensor controller to interface to various off-chip sensors present in a given platform. An image signal processor 1170 may be provided with one or more separate ISPs to perform image processing with regard to captured content from one or more cameras of a platform, including still and video cameras.
A display processor 1180 may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly communicate content for playback on such display. Still further, a location unit 1190 may include a GPS receiver with support for multiple GPS constellations to provide applications highly accurate positioning information obtained using as such GPS receiver. Understand that while shown with this particular set of components in the example of FIG. 11, many variations and alternatives are possible.
Referring now to FIG. 12, shown is a block diagram of an example system with which embodiments can be used. As seen, system 1200 may be a smartphone or other wireless communicator. A baseband processor 1205 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 1205 is coupled to an application processor 1210, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 1210 may further be configured to perform a variety of other computing operations for the device.
In turn, application processor 1210 can couple to a user interface/display 1220, e.g., a touch screen display. In addition, application processor 1210 may couple to a memory system including a non-volatile memory, namely a flash memory 1230 and a system memory, namely a dynamic random access memory (DRAM) 1235. As further seen, application processor 1210 further couples to a capture device 1240 such as one or more image capture devices that can record video and/or still images.
Still referring to FIG. 12, a universal integrated circuit card (UICC) 1240 comprising a subscriber identity module and possibly a secure storage and cryptoprocessor is also coupled to application processor 1210. System 1200 may further include a security processor 1250 that may couple to application processor 1210. A plurality of sensors 1225 may couple to application processor 1210 to enable input of a variety of sensed information such as accelerometer and other environmental information. An audio output device 1295 may provide an interface to output sound, e.g., in the form of voice communications, played or streaming audio data and so forth.
As further illustrated, a near field communication (NFC) contactless interface 1260 is provided that communicates in a NFC near field via an NFC antenna 1265. While separate antennae are shown in FIG. 12, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionality.
A power management integrated circuit (PMIC) 1215 couples to application processor 1210 to perform platform level power management. To this end, PMIC 1215 may issue power management requests to application processor 1210 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 1215 may also control the power level of other components of system 1200.
To enable communications to be transmitted and received, various circuitry may be coupled between baseband processor 1205 and an antenna 1290. Specifically, a radio frequency (RF) transceiver 1270 and a wireless local area network (WLAN) transceiver 1275 may be present. In general, RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 1280 may be present. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver 1275, local wireless communications, such as according to a BluetoothTM standard or an IEEE 802.11 standard such as IEEE 802.11a/b/g/n can also be realized.
Referring now to FIG. 13, shown is a block diagram of another example system with which embodiments may be used. In the illustration of FIG. 13, system 1300 may be mobile low-power system such as a tablet computer, 2:1 tablet, phablet or other convertible or standalone tablet system. As illustrated, a SoC 1310 is present and may be configured to operate as an application processor for the device.
A variety of devices may couple to SoC 1310. In the illustration shown, a memory subsystem includes a flash memory 1340 and a DRAM 1345 coupled to SoC 1310. In addition, a touch panel 1320 is coupled to the SoC 1310 to provide display capability and user input via touch, including provision of a virtual keyboard on a display of touch panel 1320. To provide wired network connectivity, SoC 1310 couples to an Ethernet interface 1330. A peripheral hub 1325 is coupled to SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to system 1300 by any of various ports or other connectors.
In addition to internal power management circuitry and functionality within SoC 1310, a PMIC 1380 is coupled to SoC 1310 to provide platform-based power management, e.g., based on whether the system is powered by a battery 1390 or AC power via an AC adapter 1395. In addition to this power source-based power management, PMIC 1380 may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC 1380 may communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310.
Still referring to FIG. 13, to provide for wireless capabilities, a WLAN unit 1350 is coupled to SoC 1310 and in turn to an antenna 1355. In various implementations, WLAN unit 1350 may provide for communication according to one or more wireless protocols, including an IEEE 802.11 protocol, a BluetoothTM protocol or any other wireless protocol.
As further illustrated, a plurality of sensors 1360 may couple to SoC 1310. These sensors may include various accelerometer, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to SoC 1310 to provide an interface to an audio output device 1370. Of course understand that while shown with this particular implementation in FIG. 13, many variations and alternatives are possible.
Referring now to FIG. 14, a block diagram of a representative computer system such as notebook, UltrabookTM or other small form factor system. A processor 1410, in one embodiment, includes a microprocessor, multi-core processor, multithreaded processor, an ultra low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor 1410 acts as a main processing unit and central hub for communication with many of the various components of the system 1400. As one example, processor 1400 is implemented as a SoC.
Processor 1410, in one embodiment, communicates with a system memory 1415. As an illustrative example, the system memory 1415 is implemented via multiple memory devices or modules to provide for a given amount of system memory.
To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage 1420 may also couple to processor 1410. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD or the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown in FIG. 14, a flash device 1422 may be coupled to processor 1410, e.g., via a serial peripheral interface (SPI). This flash device may provide for non-volatile storage of system software, including a basic input/output software (BIOS) as well as other firmware of the system.
Various input/output (I/O) devices may be present within system 1400. Specifically shown in the embodiment of FIG. 14 is a display 1424 which may be a high definition LCD or LED panel that further provides for a touch screen 1425. In one embodiment, display 1424 may be coupled to processor 1410 via a display interconnect that can be implemented as a high performance graphics interconnect. Touch screen 1425 may be coupled to processor 1410 via another interconnect, which in an embodiment can be an I2C interconnect. As further shown in FIG. 14, in addition to touch screen 1425, user input by way of touch can also occur via a touch pad 1430 which may be configured within the chassis and may also be coupled to the same I2C interconnect as touch screen 1425.
For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners. Certain inertial and environmental sensors may couple to processor 1410 through a sensor hub 1440, e.g., via an I2C interconnect. In the embodiment shown in FIG. 14, these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443 and a gyroscope 1444. Other environmental sensors may include one or more thermal sensors 1446 which in some embodiments couple to processor 1410 via a system management bus (SMBus) bus.
Also seen in FIG. 14, various peripheral devices may couple to processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435. Such components can include a keyboard 1436 (e.g., coupled via a PS2 interface), a fan 1437, and a thermal sensor 1439. In some embodiments, touch pad 1430 may also couple to EC 1435 via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM) 1438 in accordance with the Trusted Computing Group (TCG) TPM Specification Version 1.2, dated Oct. 2, 2003, may also couple to processor 1410 via this LPC interconnect.
System 1400 can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in FIG. 14, various wireless modules, each of which can correspond to a radio configured for a particular wireless communication protocol, are present. One manner for wireless communication in a short range such as a near field may be via a NFC unit 1445 which may communicate, in one embodiment with processor 1410 via an SMBus. Note that via this NFC unit 1445, devices in close proximity to each other can communicate.
As further seen in FIG. 14, additional wireless units can include other short range wireless engines including a WLAN unit 1450 and a Bluetooth unit 1452. Using WLAN unit 1450, Wi-FiTM communications in accordance with a given IEEE 802.11 standard can be realized, while via Bluetooth unit 1452, short range communications via a Bluetooth protocol can occur. These units may communicate with processor 1410 via, e.g., a USB link or a universal asynchronous receiver transmitter (UART) link. Or these units may couple to processor 1410 via an interconnect according to a PCIeTM protocol or another such protocol such as a serial data input/output (SDIO) standard.
In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit 1456 which in turn may couple to a subscriber identity module (SIM) 1457. In addition, to enable receipt and use of location information, a GPS module 1455 may also be present. Note that in the embodiment shown in FIG. 14, WWAN unit 1456 and an integrated capture device such as a camera module 1454 may communicate via a given USB protocol such as a USB 2.0 or 3.0 link, or a UART or I2C protocol.
An integrated camera module 1454 can be incorporated in the lid. To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) 1460, which may couple to processor 1410 via a high definition audio (HDA) link. Similarly, DSP 1460 may communicate with an integrated coder/decoder (CODEC) and amplifier 1462 that in turn may couple to output speakers 1463 which may be implemented within the chassis. Similarly, amplifier and CODEC 1462 can be coupled to receive audio inputs from a microphone 1465 which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC 1462 to a headphone jack 1464. Although shown with these particular components in the embodiment of FIG. 14, understand the scope of the present invention is not limited in this regard.
Embodiments may be implemented in many different system types. Referring now to FIG. 15, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in FIG. 15, multiprocessor system 1500 is a point-to-point interconnect system, and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. As shown in FIG. 15, each of processors 1570 and 1580 may be multicore processors, including first and second processor cores (i.e., processor cores 1574a and 1574b and processor cores 1584a and 1584b), although potentially many more cores may be present in the processors. Each of the processors can include a PCU or other power management logic to perform processor-based power management as described herein.
Still referring to FIG. 15, first processor 1570 further includes a memory controller hub (MCH) 1572 and point-to-point (P-P) interfaces 1576 and 1578. Similarly, second processor 1580 includes a MCH 1582 and P-P interfaces 1586 and 1588. As shown in FIG. 15, MCH's 1572 and 1582 couple the processors to respective memories, namely a memory 1532 and a memory 1534, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor 1570 and second processor 1580 may be coupled to a chipset 1590 via P-P interconnects 1562 and 1564, respectively. As shown in FIG. 15, chipset 1590 includes P-P interfaces 1594 and 1598.
Furthermore, chipset 1590 includes an interface 1592 to couple chipset 1590 with a high performance graphics engine 1538, by a P-P interconnect 1539. In turn, chipset 1590 may be coupled to a first bus 1516 via an interface 1596. As shown in FIG. 15, various input/output (I/O) devices 1514 may be coupled to first bus 1516, along with a bus bridge 1518 which couples first bus 1516 to a second bus 1520. Various devices may be coupled to second bus 1520 including, for example, a keyboard/mouse 1522, communication devices 1526 and a data storage unit 1528 such as a disk drive or other mass storage device which may include code 1530, in one embodiment. Further, an audio I/O 1524 may be coupled to second bus 1520. Embodiments can be incorporated into other types of systems including mobile devices such as a smart cellular telephone, tablet computer, netbook, UltrabookTM, or so forth.
Embodiments of the present invention support hot reset or link disable, on a system on a chip (SoC), of an on-die device while allowing the rest of the SoC to function normally, e.g., without shutting down the rest of the SoC. Embodiments use a combination of power control unit firmware and logic hooks to quiesce the on-die device and an associated bridge (e.g., PCIE to OSF bridge) that is to bridge a peripheral component interconnect express (PCIE) protocol of a root complex fabric to an on-chip system fabric (OSF) protocol of the on-chip device and vice versa, reset the device, and then release the reset, e.g., when control software releases the reset. To ensure that the SoC does not “hang up” (e.g., freeze, cease to operate) during the reset, each inbound transaction to the on-die device is handled either by responding with an “unsupported request” response (e.g., for reads), or by dropping the inbound transaction, e.g., for posted writes and messages.
FIG. 16 is a block diagram of a SoC, according to an embodiment of the present invention. The SoC 1600 includes a plurality of cores 16020-1602N, a memory interface 1604, a ring interconnect 1606, a ring interface 1607, a plurality of last level caches 16400-1640N, a root complex fabric 1608, root ports 1609, 1611, and 1613, a gigabit Ethernet (GBE) device 1620 and a corresponding bridge 1610 (e.g., PCIE to OSF bridge), a direct memory access (DMA) device 1630 and a corresponding bridge 1612 (e.g., PCIE to OSF bridge), PCIE ports 1614, and a power control unit (PCU) 1660 that includes reset logic 1650. In the embodiment shown in FIG. 16, the bridges 1610 and 1612 are PCIE to OSF bridges that convert from PCIE protocol to IOSF protocol and vice-versa. In other embodiments, other bridge types may be utilized. Each PCIE to OSF bridge 1610 and 1612 couples to a corresponding primary interface 1622, 1632 (e.g., OSF interface) of the corresponding device (1620, 1630) on one side, and to the corresponding root port 1609, 1611 on the other side.
In addition to the OSF primary interface, the GBE device 1620 and DMA device 1630 are each coupled via sideband interface 1624, 1634, respectively, to a sideband bus 1670 (e.g., an on-chip system fabric sideband). The sideband interface 1624, 1634 can be used for accessing registers of the corresponding device (1620, 1630) and for sending and receiving messages via the sideband bus 1670. The sideband interface 1624, 1634 may be used for debug access of the device registers of the corresponding device (1620, 1630) and for internal messaging or register access by on-chip firmware.
In operation, responsive to an indication (e.g., generated by software being executed on one or more of the cores 1602) to reset one (or both) of the devices 1620 and 1630, a status bit is set in a configuration register of the root complex fabric 1608 to indicate that hot reset (or link disable) is in progress. Dedicated firmware (“Pcode” herein) runs in the reset logic 1650 and is notified 1652, 1654 that the hot reset (or link disable) is to be conducted. In some embodiments, the reset logic 1650 includes a microcontroller of the power control unit (PCU) 1660, as well as firmware that is to be executed on the microcontroller.
To support the hot reset and/or link disable, one or both of the bridge 1610 and the bridge 1612 can be placed into a quiescent state that is triggered by writing (1656, 1658) into a configuration register of the corresponding bridge 1610/1612, which ensures that the bridge 1610/1612 stops granting credits for new outbound transactions from the device 1620/1630.
In order to quiesce the GBE device 1620, a “Reset Warn” (RSWARN) command 1662 may be sent to the GBE device 1620 from the reset logic 1650. On receiving the RSWARN command, the GBE device 1620 ceases to send out further transactions, begins to drop writes and messages that come to the GBE device 1620, and begins to respond to reads that come into the GBE device 1620 with an “unsupported request” response. Once all inflight transactions previously generated by GBE device 1620 are completed, the GBE device 1620 may indicate that a quiescent state is achieved by sending a reset acknowledge (RSACK) message 1664 to the reset logic 1650.
To quiesce the DMA 1630, a PCIE function level reset (FLR) command 1666 may be generated by the reset logic 1650 and sent to the DMA 1630.
For either the GBE device 1620 or the DMA device 1630, the device 1620/1630 might not respond to the RSWARN-based quiescent request or to the FLR. Therefore, (optionally) the Pcode may include a timeout timer (e.g., implemented in firmware in the reset logic 1650), which on timeout asserts the reset to the GBE device 1620 and/or to the DMA device 1630, regardless of whether the FLR/RSWARN-based quiescence is accomplished.
To ensure that no agents access the DMA device 1630 (e.g., via sideband interface 1634) while undergoing hot reset, once the sideband interface 1634 is idle it may be blocked from becoming active again by setting (e.g., via a signal 1672), a configuration bit (e.g., within DMA 1630) to prevent a transition of the sideband interface 1634 from idle to active. For either of the GBE device 1620 and the DMA device 1630, a status bit may be set (e.g., within the root complex fabric 1608) to indicate that the reset/link disable is active. Agents that attempt to access either of GBE device 1620 or DMA device 1630 via sideband interface may poll the status bit before being able to access the GBE device 1620 or the DMA device 1630.
Some register states in the GBE device 1620 or the DMA device 1630, e.g., register states related to power management functionality, may be saved (e.g., in RAM within the PCU 1660) before applying the reset/link disable, and those register states may be restored after reset/link disable is de-asserted.
In FIG. 16, any input/output peripheral device may be substituted for the GBE device 1620, and any accelerator device may substitute for the DMA 1630. Similar procedures to those presented herein for effecting hot reset or link disable are to be employed for each corresponding device, according to embodiments of the present invention.
FIG. 17 is a flow diagram of a method 1700 of effecting a hot reset (or link disable) of an accelerator device such as a DMA on a non-root bus of a system, according to an embodiment of the present invention. The method 1700 is applied to a DMA device, but is valid for any other accelerator/peripheral device on a secondary bus, e.g., non-root port integrated.
At block 1702, software, e.g., application software executed in a core of a processor, e.g., of a system such as an SOC, writes to a root port register (hot reset bit or link disable bit) to initiate a hot reset (or link disable) of the DMA device within the system, e.g., the SOC. Continuing to block 1704, power control unit firmware (“Pcode” herein) in a power control unit (PCU) of the SOC is notified that the hot reset/link disable is initiated.
Advancing to block 1706, Pcode sets a status bit in a configuration register of the DMA to indicate that hot reset/link disable is in progress. Pcode may save contents of DMA registers that are related to power management functionality, to Pcode RAM (e.g., situated in the PCU). Pcode triggers a function level reset (FLR) for all functions in the DMA.
For systems that include a DMA sideband interface to a sideband bus, moving to decision diamond 1708, when a DMA sideband interface is idle the method advances to block 1710; otherwise, the method waits until the DMA sideband interface is idle. Moving to block 1710, Pcode sets a bit in a configuration register (e.g., within the DMA sideband interface) to stop the DMA sideband interface transitioning from idle to active.
Proceeding to decision diamond 1712, a function level reset (FLR) timer runs until expired. At expiration of the FLR timer, proceeding to block 1714 Pcode sets a bridge quiesce register in a bridge (e.g., a PCIE to OSF bridge) that couples the DMA to a PCIE root complex fabric, which causes the PCIE to OSF bridge to become quiescent.
Continuing to block 1716, a bridge quiesce timer is set and runs until expired. Upon expiration of the bridge quiesce timer, advancing to block 1718, Pcode asserts a primary domain (e.g., OSF) reset to the DMA and to the corresponding (PCIE to OSF) bridge coupled to the DMA, which resets all logic clocked by a primary clock (e.g., OSF primary clock).
Moving to block 1720, Pcode clears the (PCIE to OSF) bridge quiesce bit. Proceeding to block 1722, the hot reset bit (or link disable bit) is cleared by the software. Continuing to block 1724, Pcode is notified that the hot reset bit has been cleared. Advancing to block 1726, Pcode de-asserts the reset to the DMA, restores the register values that were saved before the reset was asserted, de-asserts the reset to the (PCIE to OSF) bridge coupled to the DMA, and when sideband interface is employed, clears the hot reset in progress bit to unblock accesses via sideband interface to the DMA.
FIG. 18 is a flow diagram of a method to effect a hot reset (or link disable) for an input/output (I/O) device, e.g., a gigabit Ethernet controller (GBE device), according to embodiments of the present invention. The flow diagram 1800 uses a GBE device/peripheral as an example of an accelerator device, but the method can be applied to any other accelerator device on a secondary bus of a system such as the system of FIG. 16, e.g., non-root port integrated.
At block 1802, software (executed in a core of a system such as an SOC, e.g., SOC 1600 of FIG. 16) writes to a root port register to initiate a hot reset/link disable of the GBE device. Continuing to block 1804, Pcode firmware (situated in a power control unit (PCU)) is notified that the hot reset/link disable is initiated. Advancing to block 1806, Pcode sets a status bit in a configuration register of the GBE device to indicate that hot reset/link disable is in progress. Pcode saves contents of GBE registers (e.g., to Pcode RAM) that are used for power management functionality. Pcode sends a reset warn (RSWARN) message to the GBE device. On receipt of the RSWARN message, the GBE device stops sending out further transactions, begins to drop posted writes and messages that arrive, and responds to read/non-posted requests with an “unsupported request” response. Additionally, a RSWARN timer started.
Moving to decision diamond 1808, when an acknowledgement of receipt of RS WARN (RSACK) is received by Pcode, or when the RSWARN timer expires (e.g., if the GBE device does not respond to the RSWARN in a timely fashion), control moves to block 1810. At block 1810, Pcode sets a bridge quiesce register in a (PCIE to OSF) bridge coupled to the GBE device to ensure that the bridge will stop granting credits for new outbound transactions from the GBE device. Additionally, a bridge quiesce timer is started.
Proceeding to block 1812, when the bridge quiesce timer is expired, continuing to block 1814 Pcode asserts a primary domain reset to the GBE device and to the corresponding (PCIE to OSF) bridge, which resets all logic clocked by a (OSF) primary clock. Then the Pcode clears the bridge quiesce bit. All transactions toward the GBE device are master-aborted by the root port/PCIE root complex fabric.
Advancing to block 1816, the SW clears the hot reset (or link disable) bit. Proceeding to block 1818, notification that the hot reset bit (or link disable bit) is cleared is sent to the Pcode. Continuing to block 1820, Pcode de-asserts the reset to GBE device and then restores the register values that were saved before reset was asserted. Pcode de-asserts reset to the (PCIE to OSF) bridge coupled to the GBE device. Pcode then clears the “hot reset in progress” bit to unblock accesses via sideband interface to the GBE device.
Additional embodiments are described below.
In first example, a processor includes at least one core to initiate a hot reset, a peripheral device to couple to a root complex fabric via a peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge, and a power control unit including reset logic. The reset logic is to, responsive to initiation of the hot reset, decouple the peripheral device from the root complex fabric, and after the peripheral device is decoupled from the root complex fabric, assert a reset of the peripheral device while a first core of the at least one core is in operation.
A second example includes the elements of the first example. Additionally, the reset logic is to provide an indication of an impending hot reset to a root port of the root complex fabric.
A third example includes the elements of the second example and further includes the PCIE to OSF bridge. Responsive to receipt by the root port of the indication of the impending hot reset, the PCIE to OSF bridge is to refrain from granting credits for outbound transactions toward the root port that are received from the peripheral device.
A fourth example includes the elements of the first example. Additionally, the reset logic is to save power management contents of a first register of the peripheral device into storage of the power control unit prior to decoupling the peripheral device from the root complex fabric.
A fifth example includes the elements of the fourth example. Additionally, after the reset of the peripheral device is complete, the reset logic is to recouple the peripheral device to the root complex fabric by de-assertion of the reset and restoration of the power management contents of the first register retrieved from the storage of the power control unit.
A sixth example includes the elements of the first example. Further, the reset logic is to decouple the peripheral device from the root complex fabric by providing to the peripheral device a reset warn command. On receipt of the reset warn command the peripheral device is to drop a posted write request that is received.
A seventh example includes the elements of the first example. Additionally, the reset logic is to decouple the peripheral device from the root complex fabric by providing to the peripheral device a reset warn command. Upon receipt of the reset warn command the peripheral device is to respond to a read request with a response that indicates that the read request is unsupported.
An 8th example includes the elements of the first example. Additionally the reset logic is to decouple the peripheral device from the root complex fabric by providing to the peripheral device a reset warn command. Upon receipt of the reset warn command the peripheral device is to drop at least one incoming message responsive to receipt of the at least one incoming message.
A 9th example includes the elements of the first example. Additionally, the reset logic is to decouple the peripheral device from the root complex fabric by sending to the peripheral device a reset warn command. Responsive to receipt of the reset warn command and completion of pending transactions, the peripheral device is to indicate to the reset logic that the peripheral device is in a quiescent state.
A 10th example includes the elements of any one of examples 1 to 9. Additionally, the peripheral device includes a sideband interface to couple to a sideband bus and the reset logic, responsive to initiation of the hot reset, is to decouple the peripheral device from the sideband bus.
An 11th example includes the elements of any one of examples 1 to 9. The reset logic is further to actuate a quiesce timer that, upon exhaustion, indicates that the reset is to be asserted.
A 12th example is a system on a chip (SOC) that includes at least one core including a first core to initiate a reset, a peripheral device to couple to a root complex fabric via a peripheral component interconnect express (PCIE) to on-chip system fabric (OSF) bridge, and reset logic. The reset logic, responsive to initiation of the reset, is to decouple the peripheral device from the root complex fabric, and after the peripheral device is decoupled, assert a reset of the peripheral device while the first core is in operation.
A 13th example includes the elements of the 12th example. Additionally, the reset logic is to decouple the peripheral device from the root complex fabric by 0 the peripheral device and the PCIE to OSF bridge.
A 14th example includes the elements of the 13th example. Additionally, the reset logic is to, after quiescing the PCIE to OSF bridge, assert a reset of the PCIE to OSF bridge.
A 15th example includes the elements of any one of examples 12 to 14, where the peripheral device includes a sideband interface to couple to a sideband bus and responsive to initiation of the reset, the reset logic is to decouple the peripheral device from the sideband bus.
A 16th example is a computer-readable medium storing instructions that, in response to being executed on a computing device, cause the computing device to, responsive to a reset command, decouple a peripheral device of a system on a chip (SoC) from a route complex fabric of the SoC, and after the peripheral device is decoupled, assert a reset of the peripheral device while at least one core of the SoC is in operation.
A 17th example includes the elements of the 16th example, further including instructions to responsive to the reset command, decouple the peripheral device from a sideband interface that is to enable message transfer to and from the peripheral device, and including instructions to set a reset indicator that when set, causes the sideband interface to transition to an idle state, and after the sideband interface is transitioned to the idle state, set a sideband interface indicator to prevent the sideband interface from transitioning from the idle state to an active state.
An 18th example includes the elements of the 16th example, where the instructions to decouple the peripheral device from the route complex fabric include instructions to, prior to assertion of the reset of the peripheral device, quiesce the peripheral device. Also included are instructions to, prior to assertion of the reset of the peripheral device, quiesce a peripheral component interconnect express (PCIE) to on-chip system fabric (OSF) bridge that is to couple the peripheral device to the route complex fabric, where the PCIE to OSF bridge is to convert data between a PCIE protocol and an OSF protocol.
A 19th example includes the elements of the 18th example, further including instructions to de-assert the reset of the peripheral device after the reset of the peripheral device is complete and to 0 the peripheral device to the route complex fabric.
A 20th example includes the elements of any one of examples 16 to 19, and further includes instructions to save power management data stored in power management registers of the peripheral device to a storage prior to assertion of the reset, and after the reset is complete, restore the power management data to the power management registers of the peripheral device.
A 21st example is a method that includes decoupling, by a power control unit (PCU) of a system on a chip (SoC), a peripheral device of the SoC from a route complex fabric of the SoC responsive to receipt of a reset command, and after the peripheral device is decoupled, asserting, by the PCU, a reset of the peripheral device while at least one core of the SoC is in operation.
A 22nd example includes the elements of the 21st example, and further includes responsive to the reset command, decoupling the peripheral device from a sideband interface that is to enable message transfer to and from the peripheral device including setting a reset indicator that causes the sideband interface to transition to an idle state. The method also includes after the sideband interface is transitioned to the idle state, setting a sideband interface indicator to prevent the sideband interface transitioning from the idle state to an active state.
A 23rd example includes the elements of 21st example, and further includes, prior to assertion of the reset of the peripheral device, quiescing the peripheral device and quiescing a peripheral component interconnect express (PCIE) to on-chip system fabric (OSF) bridge that is to couple the peripheral device to the route complex fabric. The PCIE to OSF bridge is to convert data between a PCIE protocol and an OSF protocol.
A 24th example includes the elements of the 23rd example and further includes de-asserting the reset of the peripheral device after the reset of the peripheral device is complete and recoupling the peripheral device to the route complex fabric.
A 25th example includes the elements of any one of examples 21 to 24, and further includes saving power management data stored in power management registers of the peripheral device to a storage prior to assertion of the reset and after the reset is complete, restoring the power management data to the power management registers of the peripheral device.
A 26th example is an apparatus to perform the method of any one of examples 21 to 24.
A 27th example is an apparatus that includes means for performing the method of any one of examples 21 to 24.
A 28th example is a system on a chip (SOC) that includes at least one core including a first core to initiate a link disable, a peripheral device to couple to a root complex fabric via a peripheral component interconnect express (PCIE) to on-chip system fabric (OSF) bridge, and reset logic that responsive to initiation of the link disable, is to decouple the peripheral device from the root complex fabric and after the peripheral device is decoupled, assert a reset of the peripheral device while the first core is in operation.
A 29th example includes the elements of example 28, where reset logic is to decouple the peripheral device from the root complex fabric by quiescing the peripheral device and the PCIE to OSF bridge.
A 30st example includes the elements of example 29. Additionally, the reset logic is to, after quiescing the PCIE to OSF bridge, assert a reset of the PCIE to OSF bridge.
A 31th example includes the elements of example 28, where during assertion of the link disable, inbound transactions to the peripheral device are handled nonresponsively.
A 32nd example includes the elements of any one of examples 28 to 31, where the peripheral device includes a sideband interface to couple to a sideband bus and responsive to initiation of the link disable, the reset logic is to decouple the peripheral device from the sideband bus.
Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

## Claims

1. A processor comprising:
an on-chip peripheral device;
at least one core to provide an indication to initiate a hot reset, the hot reset comprising a reset of the on-chip peripheral device without shut-down of the at least one core;
a root complex fabric;
a peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge to couple the on-chip peripheral device to the root complex fabric; and
a power control unit including reset logic to, responsive to the indication to initiate the hot reset:
quiesce the on-chip peripheral device;
quiesce the PCIE to OSF bridge to decouple the on-chip peripheral device from the root complex fabric; and
in response to a determination that the on-chip peripheral device and the PCIE to OSF bridge are quiesced, cause a reset of the PCIE to OSF bridge and the reset of the on-chip peripheral device while a first core of the at least one core is in operation.

2. The processor of claim 1, wherein the reset logic is to provide an indication of an impending hot reset to a root port of the root complex fabric.

3. The processor of claim 2, wherein responsive to receipt by the root port of the indication of the impending hot reset, the PCIE to OSF bridge is to refrain from granting credits for outbound transactions toward the root port that are received from the on-chip peripheral device.

4. The processor of claim 1, wherein the reset logic is to save power management contents of a first register of the on-chip peripheral device into storage of the power control unit prior to decoupling the on-chip peripheral device from the root complex fabric.

5. The processor of claim 1, wherein the reset logic is to quiesce the PCIE to OSF bridge by setting a configuration register of the PCIE to OSF bridge.

6. The processor of claim 1, wherein the reset logic is to quiesce the on-chip peripheral device by providing to the on-chip peripheral device a reset warn command, wherein on receipt of the reset warn command the on-chip peripheral device is to drop a posted write request that is received.

7. The processor of claim 1, wherein the reset logic is to quiesce the on-chip peripheral device by providing to the on-chip peripheral device a reset warn command, wherein upon receipt of the reset warn command the on-chip peripheral device is to respond to a read request with a response that indicates that the read request is unsupported.

8. The processor of claim 1, wherein the reset logic is to quiesce the on-chip peripheral device by providing to the on-chip peripheral device a reset warn command, wherein upon receipt of the reset warn command the on-chip peripheral device is to drop at least one incoming message responsive to receipt of the at least one incoming message.

9. The processor of claim 1, wherein the reset logic is to quiesce the on-chip peripheral device by sending to the on-chip peripheral device a reset warn command, and responsive to receipt of the reset warn command and completion of pending transactions, the on-chip peripheral device is to indicate to the reset logic that the on-chip peripheral device is in a quiescent state.

10. The processor of claim 1, wherein the on-chip peripheral device includes a sideband interface to couple to a sideband bus and the reset logic is to decouple the on-chip peripheral device from the sideband bus responsive to initiation of the hot reset.

11. The processor of claim 1, wherein the reset logic is to cause the reset of the on-chip peripheral device and the reset of the PCIE to OSF bridge by asserting a primary domain reset to the on-chip peripheral device and the PCIE to OSF bridge, wherein the primary domain reset resets all logic clocked by a primary clock.

12. A system on a chip (SOC) comprising:
an on-chip peripheral device;
at least one core including a first core to provide an indication to initiate a reset of the on-chip peripheral device without shut-down of the at least one core;
a root complex fabric;
a peripheral component interconnect express (PCIE) to on-chip system fabric (OSF) bridge coupling the on-chip peripheral device to the root complex fabric; and
reset logic to, responsive to the indication to initiate the reset of the on-chip peripheral device:
quiesce the on-chip peripheral device;
quiesce the PCIE to OSF bridge to decouple the on-chip peripheral device from the root complex fabric; and
in response to a determination that the on-chip peripheral device and the PCIE to OSF bridge are quiesced, cause a reset of the PCIE to OSF bridge and the reset of the on-chip peripheral device while the first core is in operation.

13. The SOC of claim 12, wherein the reset logic is to quiesce the on-chip peripheral device by sending a reset warn command to the on-chip peripheral device.

14. The SOC of claim 13, wherein the reset logic is to quiesce the PCIE to OSF bridge by setting a configuration register of the PCIE to OSF bridge.

15. The SOC of claim 12, wherein the reset logic is to cause the reset of the on-chip peripheral device and the reset of the PCIE to OSF bridge by asserting a primary domain reset to the on-chip peripheral device and the PCIE to OSF bridge, wherein the primary domain reset resets all logic clocked by a primary clock.

16. A non-transitory computer-readable medium storing instructions that, in response to being executed on a computing device, cause the computing device to:
in response to an indication to initiate a reset of an on-chip peripheral device without shut-down of an entire system on a chip (SOC) that includes the on-chip peripheral device:
quiesce the on-chip peripheral device;
quiesce a PCIE to OSF bridge included in the SOC, the PCIE to OSF bridge to couple the on-chip peripheral device to a root complex fabric included in the SOC; and
in response to a determination that the on-chip peripheral device and the PCIE to OSF bridge are quiesced, cause a reset of the PCIE to OSF bridge and the reset of the peripheral device while at least one core of the SoC is in operation.

17. The computer-readable medium of claim 16, further including instructions to cause the reset of the on-chip peripheral device and the reset of the PCIE to OSF bridge by asserting a primary domain reset to the on-chip peripheral device and the PCIE to OSF bridge, wherein the primary domain reset resets all logic clocked by a primary clock.

18. The computer-readable medium of claim 16, wherein the PCIE to OSF bridge is to convert data between a PCIE protocol and an OSF protocol.

19. The computer-readable medium of claim 18, further comprising instructions to quiesce the on-chip peripheral device by sending a reset warn command to the on-chip peripheral device.

20. The computer-readable medium of claim 16, further comprising instructions to quiesce the PCIE to OSF bridge by setting a configuration register of the PCIE to OSF bridge.