# Patent

## Title
Self-biased multiple cascode current mirror circuit

## Abstract

A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET. Multiple cascode FETs, multiple output stages, high frequency bypass capacitors, and lowpass filters are also described.

## Background
BACKGROUND
Current mirrors can be used in analog circuits for providing current bias or signals to a variety of circuits. The output impedance of the current mirror can affect the accuracy of the current provided by the current mirror. High output impedance in current mirrors is desired for accurate replication of currents. Cascode transistors can be used to obtain high output impedance. A current mirror may also be characterized as having an output voltage swing. High voltage swing in current mirrors can be desired for accurate operation, such as with low power supply voltages, and for increased voltage signal amplitudes, which can improve the accuracy of analog circuitry utilizing the current mirrors.
Current mirrors are building blocks used in integrated circuits. In CMOS technologies, current mirrors operate on the principle that if the gate-source voltages of two identical transistors are equal, then their drain currents are equal. A current mirror's output impedance can be represented by the slope of the output current when graphed against the output voltage—the smaller the slope, the higher the output impedance. A high output impedance can be desirable for a current mirror because parameters of the circuits with which the current mirror is used can be detrimentally affected by a low output impedance (e.g., the common-mode rejection ratio of a differential transistor pair can be worse with low output impedance of a current mirror sourcing or sinking current to the differential pair). A current mirror's compliance voltage range parameter provides a measure of the output voltage range over which the current mirror can maintain a constant output current.
One approach to achieving high output impedance for a current mirror is to use one or more cascode transistors in series with an output transistor of the current mirror. While the cascode transistors themselves do not consume current, additional circuits that consume current can be needed provide bias voltages for their gates. Moreover, if cascode gate bias voltages are not well-controlled for ensuring transistor operation at the lower end or edge of the saturation region, a substantial reduction in the compliance voltage range can occur.
SUMMARY/OVERVIEW
The present inventor has recognized, among other things, that one approach to limit current consumption for the cascode bias circuits in current mirrors is to use a self-biased cascode device, such as in which the input current itself can be used to bias one or more cascode devices. A challenge in providing one or more self-biased cascodes is to achieve a large compliance output voltage range and enough voltage margin, such as to accommodate process, temperature, and input-current variations.
This document describes, among other things, a device that can include a self-biased cascode current mirror/scaler circuit (“mirroring” can include providing an output current that is a scaled version of the input current, rather than an output current that is identical in magnitude to the input current). The self-biased cascode current mirror/scaler circuit can include a bias field-effect transistor (FET). The bias FET can have a drain electrically coupled to a gate, and having a source. The bias FET can be biased using a first input current to generate a gate-source bias voltage, Vgs, between the gate and the source of the bias FET.
A first bias circuit can be electrically coupled to the bias FET, such as to receive the Vgs provided by the bias FET. The first bias circuit can be arranged to divide Vgs into a first voltage component (which can be specified at a FET threshold voltage) and a second voltage component (which can be specified at a FET drain-source saturation voltage ΔVds). An input FET of the current mirror/scaler can have a drain electrically coupled to receive a drain current (which can optionally be approximately equal to a drain current of the bias FET, or a function thereof). A first output stage can include a first output FET, having a gate electrically coupled to apply the voltage at the gate of the input FET. A drain of the output FET can provide a first output current that is mirrored or scaled as a specified function of the first input current. A first cascode FET can be in series with the first output FET to pass the first output current between a drain and a source of the first cascode FET. A gate of the first cascode FET can be biased by the first bias circuit at a voltage that is equal to the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds (e.g., of the input FET of the current mirror/scaler).



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an example of a self-biased cascode current mirror.
FIG. 2 shows an example of a self-biased multiple-cascode current mirror circuit.
FIG. 3 shows an example of a self-biased cascode current mirror circuit.
FIG. 4 shows an example of a self-biased multiple-cascode current mirror circuit.
FIG. 5 shows an example of a self-biased cascode current mirror circuit with a bias circuit including a transistor configured to operate at a threshold voltage.
FIG. 6 shows an example of a self-biased multiple-cascode current mirror circuit with a bias circuit including a transistor configured to operate at a threshold voltage.
FIG. 7 shows an example of a self-biased multiple-cascode current mirror circuit with a bias circuit including a transistor configured to operate at a threshold voltage and including isolated-well type transistors.
FIG. 8 shows an example of a self-biased multiple-cascode current mirror circuit that can include multiple output stages to provide multiple output currents.
FIG. 9 shows an example of a self-biased multiple-cascode current mirror circuit that can include multiple output stages to provide multiple output currents, and including isolated-well type transistors.
FIG. 10 shows an example of a self-biased current mirror circuit in which the cascode transistor gates can be biased from a different input current than used to bias the output transistor gate.
FIG. 11 shows an example of a self-biased current mirror circuit that can include one or more high frequency bypass capacitors.
FIG. 12 shows an example of a self-biased multiple-cascode current mirror circuit that can include one or more high frequency bypass capacitors.
FIG. 13 shows an example of a self-biased current mirror circuit that can include a lowpass filter such as at a gate of a cascode device.
FIG. 14 shows a generalized example of a self-biased multiple cascode current mirror circuit that can include one or more lowpass filters such as at one or more gates of the cascode devices, or one or more high frequency bypass capacitors, or both.
FIG. 15 shows a differential generalized example, which can be regarded similar to the circuit in FIG. 14.
FIG. 16 shows an example of a single-ended-output operational transconductance amplifier (OTA), which can incorporate the self-biased current mirror/scaler, such as shown in the various examples herein.
FIG. 17 shows an example of a self-biased multiple-cascode current mirror/scaler, e.g., similar to the one shown in FIG. 12, which can be employed to provide the current mirror CM0 in FIG. 16.
FIG. 18 shows an example of a differential-output operational transconductance amplifier.
FIG. 19 shows an example in which a self-biased multiple-cascode current mirror/scaler, e.g., similar to that shown in FIG. 8, can be employed as to provide the current source I1 in FIG. 18.
FIG. 20 shows an approach for providing a generalized cascode circuit for generating cascode voltages VCAS2, . . . , VCASN in FIG. 18.
FIG. 21 shows an example of an improved approach (relative to that shown in FIG. 20) for generating cascode voltages VCAS2, . . . , VCASN in FIG. 18, such as by using a self-biasing branch similar to the one used in the circuit of FIG. 6.
FIG. 22 shows an approach to a CMOS current mirror used for comparison in the computer-simulated plots of FIGS. 23-30.
FIGS. 23-25 show examples of the computer-simulated output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of FIG. 7.
FIG. 26 shows computer-simulated example of the output impedance zOUT of four circuit variants.
FIGS. 27-29 show the computer-simulated examples of output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of FIG. 7, such as for different values of N
FIG. 30 shows an example of the computer-simulated output impedance zOUT of four circuit variants.



DETAILED DESCRIPTION
FIG. 1 shows an example of a self-biased CMOS cascode current mirror. An input branch can include DC sources V1 and V2, and transistor M1. An output branch can include replica transistors MR1, MR2. Voltages V1 and V2 can be chosen such that all transistors operate in the saturation region. If all the transistors are assumed identical, saturation is met if the following conditions apply:

V1≧VT,   (1)

V2≧VDSAT,   (2)

where VT is the threshold voltage of the transistors and VDSAT is their drain-source saturation voltage. For increased or maximum compliance output voltage range of the current mirror (e.g., lowest possible voltage equal to 2VDSAT,EOS (at edge of saturation EOS) on output node E) and good current matching between input and output, voltages V1 and V2 should ideally assume their limit values, e.g., V1=VT and V2=VDSAT,EOS, which can be difficult to achieve. It can also be very difficult to ensure conditions (1) and (2) for a wide range of input currents. Process and temperature variations should also be accommodated, which can introduce additional restrictions.

FIG. 2 shows an illustrative example of a self-biased multiple-cascode current mirror circuit. In the generalized example of FIG. 2, an N≧1 number of identical output cascode devices MRk, k=1, . . . , N, can be used in the output branch, such as for an improved output impedance zOUT. The gates of the output transistors MRk can be connected to the intermediate nodes of a chain of ideally-equal voltage sources V2=V3= . . . =VN≧VDSAT; voltage V1 can be chosen such that is satisfies condition (1). In this way, all transistors in FIG. 2 can operate in saturation, and a substantially higher output impedance zOUT can obtained for larger N. Again, using certain circuits, it can be very difficult to ensure proper values for the voltages V1, V2, . . . , VN, such that all transistors operate at the lower limit of the saturation region VDSAT,EOS for maximum compliance output voltage range. The minimum achievable output voltage for the circuit in FIG. 2 is N·VDSAT.
FIG. 3 shows an example of a self-biased cascode current mirror circuit. In an example, the circuit can include an input branch that can include transistors M1, M2 and resistors R1, R2, and an output branch that can include transistors MR1, MR2. The transistors can be assumed to be identical (e.g., have same transconductance parameter K′, width W, length L, and threshold voltage VT), and the body effect (generally responsible for an undesirable increase in threshold voltage when the source node is at higher potential than the substrate node) can be assumed negligible. Resistors R1 and R2 can be assumed large enough such that input current IIN flows mainly through transistor M2 and only a small fraction of it through the resistors, such that




  
    
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          2
        
      
      
        
          R
          1
        
        +
        
          R
          2
        
      
    
    ⁢
    
      <<
      
        I
        IN
      
    
  
  ,




where VGS2=VC−VB (difference between voltages on nodes C and B). In an example, R1 and R2 can be used to generate the voltages V1 and V2 in the diagram of FIG. 1 as fractions of the gate-source voltage VGS2, such that all transistors operate in saturation. In an example in which current IIN serves as drain current for both M1 and M2, assuming that proportionality factor





  α
  =
  
    
      
        R
        2
      
      
        
          R
          1
        
        +
        
          R
          2
        
      
    
    <
    1
  




is chosen large enough such that M1 operates in saturation (M2 operates in saturation because of the diode connection), the following equation applies:





  
    
      
        
          
            V
            
              GS
              ⁢
              
                
              
              ⁢
              1
            
          
          =
          
            
              V
              
                GS
                ⁢
                
                  
                
                ⁢
                2
              
            
            =
            
              
                V
                T
              
              +
              
                
                  
                    2
                    ⁢
                    
                      I
                      IN
                    
                  
                  β
                
              
            
          
        
        ,
        
          

        
        ⁢
        
          
            where
            ⁢
            
              
            
            ⁢
            β
          
          =
          
            
              K
              ′
            
            ⁢
            
              
                W
                L
              
              .
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




The condition for transistor M1 to operate in saturation is VDS1≧VGS1−VT, which, using the node notations in FIG. 3, is equivalent to VB≧VGS1−VT. Using Eqn. (3), this can be re-written as:




  
    
      
        
          V
          B
        
        ≥
        
          
            
              
                2
                ⁢
                
                  I
                  IN
                
              
              β
            
          
          .
        
      
    
    
      
        (
        4
        )
      
    
  




At the same time, however, VB=VA−(1−α)VGS2, and VA=VGS1=VGS2, which yields:

VB=VGS2−(1−α)VGS2=αVGS2.  (5)

Using (3) and (5), the condition (4) for M1 to operate in saturation is re-written as:




  
    
      
        
          
            α
            ⁢
            
              
            
            ⁢
            
              V
              
                GS
                ⁢
                
                  
                
                ⁢
                2
              
            
          
          ≥
          
            
              
                2
                ⁢
                
                  I
                  IN
                
              
              β
            
          
        
        ;
      
    
    
      
        (
        6
        )
      
    
  
  
    
      
        
          
            α
            ⁡
            
              (
              
                
                  V
                  T
                
                +
                
                  
                    
                      2
                      ⁢
                      
                        I
                        IN
                      
                    
                    β
                  
                
              
              )
            
          
          ≥
          
            
              
                2
                ⁢
                
                  I
                  IN
                
              
              β
            
          
        
        ;
      
    
    
      
        (
        7
        )
      
    
  
  
    
      
        
          α
          =
          
            
              
                
                  R
                  2
                
                
                  
                    R
                    1
                  
                  +
                  
                    R
                    2
                  
                
              
              ≥
              
                α
                min
              
            
            =
            
              
                
                  
                    2
                    ⁢
                    
                      I
                      IN
                    
                  
                  β
                
              
              
                
                  V
                  T
                
                +
                
                  
                    
                      2
                      ⁢
                      
                        I
                        IN
                      
                    
                    β
                  
                
              
            
          
        
        ;
      
    
    
      
        (
        8
        )
      
    
  
  
    
      
        
          
            R
            2
          
          
            R
            1
          
        
        ≥
        
          
            1
            
              V
              T
            
          
          ⁢
          
            
              
                
                  2
                  ⁢
                  
                    I
                    IN
                  
                
                β
              
            
            .
          
        
      
    
    
      
        (
        9
        )
      
    
  




With all transistors in FIG. 3 assumed identical and conducting the same current, we have VGSR1=VGSR2=VGS1=VGS2=VA, and the drain-source voltage of MR1 (assuming VE is large enough so that MR2 is in saturation) can be calculated as:

VDSR1=VD=VA+αVGS2−VGSR2=αVGS2=VB=VDS1  (10)

Because VDSR1=VDS1 (from (10)), it follows that meeting condition (9) ensures operation in the saturation region for both M1 and MR1.
If α=αmin (e.g., as defined in (8)), all transistors can operate at the lower limit of the saturation region (“edge of saturation” or “EOS”). The voltage developed across R2 is a fraction (a) of a gate-source voltage (VGS2), which is not a strong function of IIN, allowing the circuit to tolerate a much wider input current range than certain other approaches. Although condition (9) can be met for a relatively wide input current range, process and temperature variations (which affect VT and β) will introduce limitations, and




  
    R
    2
  
  
    R
    1
  




can be chosen sufficiently large in order for (9) to be met under all conditions.

FIG. 4 shows another example, which is a generalization of the self-biased cascode concept of FIG. 3, using an N≧2 number of identical output cascode devices. In FIG. 4, as in FIG. 3, the input current IIN can be mainly accommodated by transistor M2 due to the fact that R1 and R2 can be assumed large enough such that




  
    
      V
      
        GS
        ⁢
        
          
        
        ⁢
        2
      
    
    
      
        R
        1
      
      +
      
        R
        2
      
    
  
  ⁢
  
    
      <<
      
        I
        IN
      
    
    .
  




In addition to the circuit of FIG. 3, the input branch can include additional equal resistors R3, . . . , RN (and equal to R2) such as for biasing the gates of additional identical transistors MR3, . . . , MRN, respectively. Because the drain of M2 can be connected in such a way that only the current flowing through R2 flows through R3, . . . , RN, the voltages developed across R2, R3, . . . , RN are each equal to αVGS2. In this way, the circuit can be regarded as conceptually similar to the circuit of FIG. 2, and condition (9) (with the same observations as for FIG. 3) can be met for all transistors to operate in saturation.

FIG. 5 shows another example that can provide a robust self-biased cascode current mirror. With all transistors assumed identical, resistor R2 can be chosen very large such that practically the entire input current flows only through transistor




  
    
      M
      2
    
    ⁡
    
      (
      
        
          
            
              V
              
                GS
                ⁢
                
                  
                
                ⁢
                2
              
            
            -
            
              V
              T
            
          
          
            R
            2
          
        
        ⁢
        
          <<
          
            I
            IN
          
        
      
      )
    
  
  .




At the same time, ignoring subthreshold conduction, body effect, velocity saturation, and other second-order behavior, because of the very small drain current of M3, it follows that VGS3≃VT. As a consequence, because M1 and M2 conduct practically the same drain current, the voltage across R2 is VGS2−VGS3 ̃VGS1 ̃VT=VDSAT. In this way, the circuit in FIG. 5 can be regarded as conceptually similar to the circuit in FIG. 1, with V1 ̃VT, and V2≃VDSAT, which are the ideal conditions for all the transistors to operate at the limit (edge) of the saturation region. In this example, the requirements for operation on saturation can be met regardless of process parameters (VT or β). In this way, the circuit can operate with all the transistors at the edge of the saturation region regardless of current IIN. Practically, limitations occur at the low end of the current range where maintaining





  
    
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          2
        
      
      -
      
        V
        T
      
    
    
      R
      2
    
  
  ⁢
  
    <<
    
      I
      IN
    
  




can be problematic, and at the higher end of the range where velocity saturation and possible headroom issues can tend to come into play.

FIG. 6 shows another example, which can be regarded as a generalization of the self-biased cascode circuit concept of FIG. 5, for an N≧2 number of output cascode devices. With the exception of transistor M3 in lieu of resistor R1, the circuit of FIG. 6 can be topologically identical to the circuit of FIG. 4 and can operate under the same general principles as the circuit in FIG. 2. In certain examples with large N, circuit adjustments can be made to the circuit of FIG. 6 for further robustness. For example, resistor R2 can be adjusted such that M3 operates slightly in subthreshold, and M2 can be slightly undersized relative to




  
    M
    1
  
  ⁡
  
    (
    
      
        
          W
          2
        
        
          L
          2
        
      
      ≤
      
        
          W
          1
        
        
          L
          1
        
      
    
    )
  




such that the voltage drops across R2, R3, . . . , RN are slightly larger than VDSAT,EOS.

FIG. 7 shows an example that is similar to the circuit of FIG. 6, but in which the transistors can be isolated-well type such as for insensitivity to body effect and better precision.
FIGS. 8 and 9 show other examples (using bulk and isolated-well transistors, respectively), which detail the connection of more than one output branch to the same input branch.
FIG. 10 shows an example of a current-amplifying multiple-cascode current mirror/scaler. The input branch can include input transistor M1 and input cascode transistor M2. A bias branch of a bias circuit can include bias transistors MBIAS1, MBIAS2, MBIAS3, and resistors RBIAS2, RBIAS3, . . . , RBIASN, such as in an arrangement similar to the input branch in FIG. 6. The output cascode devices MR2, MR3, . . . , MRN can receive their gate voltages from the bias branch. The current through transistor M1 can be mirrored by the (optionally scaled) transistor MR1 and applied to the output such as via the cascode devices, which can be biased close to the edge of the saturation region by the bias branch. The bias branch can be sized such that the cascode devices can operate at the maximum current without exiting the saturation region.
FIG. 11 shows an example of a self-biased cascode current amplifier. All capacitors (each can be as large as several picoFarads) are optional, and can provide additional low-impedance paths at high frequencies. With capacitor C1 providing a short-circuit at the frequencies of interest, transistor M1 can be diode-connected and can accommodate the signal component of iIN via the indicated path. At high frequencies, without C2 in the circuit, the small input impedance of the amplifier can be provided by the equivalent diode-connected transistors M1 and M2; with C2 in the circuit and shorting M2 at high frequencies, the input impedance reduces to the equivalent resistance of diode-connected M1 only. As in a regular current mirror, current amplification can be achieved by scaling MR1 (and implicitly MR2) relative to M1 and M2.
FIG. 12 shows an example of a self-biased multiple-cascode current amplifier, which can be regarded as a generalization of the circuit in FIG. 11 for an N≧2 number of output cascode devices. Capacitors C1, C2, . . . , CN (each can be as large as several pF) are optional and behave like short-circuits at high-frequencies. At high frequencies, without C2 in the circuit, the small input impedance of the amplifier can be ensured by the equivalent diode-connected transistors M1 and M2; with C2 in the circuit and shorting M2 at high frequencies, the input impedance reduces to the equivalent resistance of diode-connected M1 only. Current amplification can be achieved by scaling MR1 (and implicitly MR2, . . . , MRN) relative to M1 and M2.
FIG. 13 shows another example, which can be regarded as a variant of the circuit shown in FIG. 11. In an example, an additional gate resistor RMR2 (e.g., on the order of 10 KΩ or larger) and gate capacitor CMR2 (e.g., as large as several pF) can be connected to the gate of MR2, such as to provide a virtual short-circuit on the gate of MR2 at high frequencies.
FIG. 14 shows an example of a generalization for an N≧2 number of output cascode devices. In an example, additional resistors RMR3, . . . , RMRN and additional capacitors CMR3, . . . , CMRN can be connected to the gates of additional cascodes MR3, . . . , MRN, such as for providing short circuits to ground at high frequencies.
FIG. 15 shows a differential example, which can be regarded similar to the circuit in FIG. 14. In the example of FIG. 15, the input current signals can be of the form iIN+(t)=IDC+IIN cos(ω0t+Φ0) and iIN−(t)=IDC−IIN cos(ω0t+Φ0), which, owing to circuit symmetry, can help ensure that the midpoints of the circuits are signal virtual grounds. In this way, no additional capacitors need be required on the gates of cascode transistors MRA2, . . . , MRAN and MRB2, . . . , MRBN.
FIG. 16 shows an example of a single-ended-output operational transconductance amplifier (OTA), which can incorporate the self-biased current mirror/scaler, such as shown in the various examples herein.
FIG. 17 shows an example of a self-biased multiple-cascode current mirror/scaler, e.g., similar to the one shown in FIG. 12, can be employed to provide the current mirror CM0 in FIG. 16.
FIG. 18 shows an example of a differential-output operational transconductance amplifier in which the common-mode circuit for adjusting either I0 or I1 is omitted for clarity.
FIG. 19 shows an example in which a self-biased multiple-cascode current mirror/scaler, e.g., similar to that shown in FIG. 8, can be employed as to provide the current source I1 in FIG. 18.
FIG. 20 shows an approach for providing a generalized cascode circuit for generating cascode voltages VCAS2, . . . , VCASN in FIG. 18. The approach shown in FIG. 20 can use multiple cascode bias currents IC2, . . . , ICN, as well as a multiplicity of devices with unwieldy geometries MC2, . . . , MCN. The current through the main amplifying devices MA1 and MB1 is obtained as the difference between I0(=2I1) and (IC2+ . . . +ICN), which can be difficult to control.
FIG. 21 shows an example of an improved approach for generating cascode voltages VCAS2, . . . , VCASN in FIG. 18, such as by using a self-biasing branch similar to the one used in the circuit of FIG. 6. In an example, only one bias current is used for the cascode bias branch, all transistors have similar geometries, and the current through the main amplifying devices MA1 and MB1 is better controlled, being the difference between I0(=2I1) and just one current, I2.
FIG. 22 shows an approach to a CMOS current mirror used for comparison in the plots of FIGS. 23-30.
FIGS. 23-25 show examples of the computer-simulated output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of FIG. 7, such as for different values of N (N=1 corresponds to the current mirror circuit of FIG. 22) and input currents (25 μA, 100 μA, and 400 μA, respectively). In these examples, all transistors are high-voltage devices in a 65 nm CMOS process, with W=20 μm, L=0.5 μm; M2 is slightly undersized for additional cascode headroom, having W=15 μm, L=0.5 μm. Resistors R2, . . . , RN are 15 KΩ each. All cascoded current mirrors operate very well with minimal voltage headroom for the cascode devices, over a wide range of input currents.
FIG. 26 shows computer-simulated example of the output impedance zOUT of the four circuit variants under consideration; a substantial improvement in zOUT can be achieved as N is increased. All computer-simulated circuits exhibit robustness over temperature and process.
FIGS. 27-29 show the computer-simulated output current-voltage characteristics of the self-biased multiple-cascode current mirror circuit of FIG. 7, such as for different values of N (N=1 corresponds to the current mirror circuit of FIG. 22) and input currents (25 μA, 100 μA, and 400 μA, respectively). All transistors are low-voltage devices in a 65 nm CMOS process, with W=4 μm, L=0.1 μm; M2 is slightly undersized for additional cascode headroom, having W=3.2 μm, L=0.1 μm. Resistors R2, . . . , RN are 50 KΩ each. All computer-simulated cascoded mirrors operate very well with minimal headroom required for the cascode devices, over a wide range of input currents.
FIG. 30 shows an example of the computer-simulated output impedance zOUT of the four circuit variants under consideration; a substantial improvement in zOUT can be achieved as N is increased. All computer-simulated circuits exhibit robustness over temperature and process.
The present description has described biasing and operation in terms of a FET drain-source saturation voltage, VDSAT or ΔVds in saturation. To provide a wider range of output voltages that can be tolerated by the current mirror/scaler, it may be desirable to provide such biasing with the FET drain-source saturation voltage, VDSAT or ΔVds at the edge of saturation (EOS), however, this is not required, even though it is desirable.
Moreover, although certain devices have been described as “replicas,” it is understood that scaled replica devices can be provided, and that such scaling can be accomplished in a number of ways, such as by scaling the W/L ratios of the FETs, or by using a desired number of like parallel input FETs and a desired number of like parallel output FETs of the current mirror/scaler to obtain a desired current scaling.
Further, although the cascode FETs have been described together with the output FETs as “replicas” it is understood that this is not required. For example, a longer channel length output FET can be used together with one or more shorter channel cascode FETs in series therewith, which will increase the output impedance of the circuit, but can allow increased voltage swing by establishing a different ΔVds in saturation for the one or more cascode FETs than for the output FET, if desired.
The foregoing description and drawings of embodiments are merely illustrative of the principles of the invention. Various modifications can be made to the embodiments by those skilled in the art without departing from the scope of the invention, which is defined in the appended claims.

## Claims

1. A low voltage cascode current mirror device comprising:
a current mirror input FET;
a current mirror first output FET;
a first cascode FET in series with the current mirror first output FET; and
a bias circuit, arranged to bias gate terminals of the current mirror input and first output FETs at a FET drain-source saturation voltage ΔVds of the current mirror input summed with a FET threshold voltage generated by the bias circuit, and to bias a gate terminal of the first cascode FET at the FET drain-source saturation voltage ΔVds of the current mirror input FET summed with both a FET threshold voltage generated by the bias circuit and with a FET drain-source saturation voltage ΔVds generated by the bias circuit.

2. The device of claim 1, wherein the cascode current mirror device is included in an operational transcoductance amplifier (OTA).

3. The device of claim 1, wherein each of the FET drain-source saturation voltages (ΔVds) is specified as an edge of saturation voltage ΔVds,eos.

4. The device of claim 1, wherein a gate of the input FET is directly electrically connected to the gate of the first output FET.

5. The device of claim 1, wherein the input FET is a first input FET and further comprising a second input FET, wherein a gate of the first output FET is connected to a gate of the second input FET that is arranged in a current mirror configuration with the first output FET, and wherein the second input FET is biased using a second input current that is provided in addition to the first input current.

6. The device of claim 1, wherein the first bias circuit comprises:
a bias field-effect transistor (FET), having a drain electrically coupled to a gate, and having a source. the bias FET biased using a first input current to generate a gate-source bias voltage. Vgs, between the gate and the source of the bias FET; and
an active or passive voltage divider circuit to divide Vgs of the bias FET into a first voltage component of the voltage divider circuit specified at a FET threshold voltage of the bias FET and a second voltage component of the voltage divider circuit specified at a FET drain-source saturation voltage AVds of the same bias FET;
wherein the current mirror input FET is arranged to receive a drain current from the bias FET and from the active or passive voltage divider circuit;
wherein the current mirror first output FET includes a gate electrically coupled to apply a voltage equal to the voltage at the gate of the current mirror input FET, a drain of the current mirror first output FET providing a first output current that is mirrored or scaled as a specified function of the first input current; and
wherein the first cascode FET includes a gate that is biased by the first bias circuit at a voltage that is equal to the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds of the input FET.

7. The device of claim 2, wherein the OTA is a differential OTA.

8. The device of claim 6, wherein the first bias circuit is arranged to provide one or more additional FET drain-source saturation voltages ΔVds in series and summed with the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds; and
the first output stage comprises one or more additional cascode FETs in series with the first output FET to pass the first output current between a drain and a source of each of the cascode FETs, gates of the one or more additional cascode FETs respectively coupled to the first bias circuit to receive a corresponding number of one or more additional FET drain-source saturation voltages ΔVds in series and summed with the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds.

9. The device of claim 6, wherein the first bias circuit includes a diode-connected FET across which the first voltage component is provided.

10. The device of claim 6, including a first capacitor coupled to AC bypass the first voltage component of the first bias circuit.

11. The device of claim 6, comprising:
a first capacitor arranged to AC couple a gate of the first cascode FET to an AC ground; and
a first resistor, electrically coupled to the first capacitor to create a lowpass filter for a gate voltage of the first cascode FET.

12. The device of claim 6, comprising first and second ones of the self-biased cascode current mirror/scaler circuits, arranged in a differential configuration, wherein:
gates of the respective first cascode FETs of the first and second self-biased cascode current mirror/scaler circuits are electrically coupled by active or passive resistors to a common AC ground; and
drains of the respective first output FETs of the first and second self-biased cascode current mirror/scaler circuits provide respective first output currents in a differential relationship to each other.

13. The device of claim 6, wherein the current mirror input FET is in series with at least one of the bias FET and the first bias circuit.

14. The device of claim 8, comprising:
a first capacitor coupled to AC bypass the first voltage component of the bias circuit;
a second capacitor coupled to AC bypass the second voltage component of the bias circuit; and
one or more additional capacitors coupled to AC bypass the one or more additional FET drain-source saturation voltages ΔVds.

15. The device of claim 8, comprising:
a first capacitor arranged to AC couple a gate of the first cascode device to an AC ground; and
a first resistor, electrically coupled to the first capacitor to create a lowpass filter for a gate voltage of the first cascode FET.

16. The device of claim 8, comprising one or more additional output stages, arranged in parallel with the first output stage, to provide a corresponding one or more additional output currents, the one or more additional output stages respectively including:
an additional output FET, having a gate coupled to apply, at the gate of the additional output FET, a voltage at the gate of the current mirror input FET, a drain of the additional output FET providing an additional output current that is mirrored or scaled as a specified function of the first input current; and
an additional cascode FET, in series with the additional output FET to pass an additional output current between a drain and a source of the additional cascode FET, a gate of the additional cascode FET biased by the first bias circuit at a voltage that is the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds.

17. The device of claim 10, including a second capacitor coupled to AC bypass the second voltage component of the bias circuit.

18. The device of claim 13, wherein the first bias current is provided to a parallel combination of the bias FET and the first bias circuit.

19. The device of claim 15, comprising:
one or more additional capacitors arranged to respectively AC couple corresponding gates of the one or more additional capacitors to AC ground; and
one or more additional resistors, respectively electrically coupled to the one or more additional capacitors to create respective lowpass filters for gate voltages of the one or more additional cascode FETs.

20. The device of claim 16, wherein:
the first bias circuit is arranged to provide one or more additional FET drain-source saturation voltages ΔVds in series and summed with the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds; and
the additional output stage comprises one or more additional cascode FETs in series with the additional output FET to pass the additional output current between a drain and a source of each of the additional cascode FETs, gates of the one or more additional cascode FETs respectively coupled to the first bias circuit to receive a corresponding number of one or more additional FET drain-source saturation voltages ΔVds in series and summed with the second voltage component in sum with the first voltage component in sum with a FET drain-source saturation voltage ΔVds.

21. A device comprising:
a self-biased cascode current mirror/scaler circuit, comprising:
a bias field-effect transistor (FET), having a drain electrically coupled to a gate, and having a source, the bias FET biased using a first input current to generate a gate-source bias voltage, Vgs, between the gate and the source of the bias FET;

a first bias circuit, electrically coupled to the bias FET to receive Vgs, the first bias circuit arranged include an active or passive voltage divider circuit to divide Vgs into a first voltage component of the voltage divider circuit specified at a FET threshold voltage of the bias FET and a second voltage component of the voltage divider circuit specified at a FET drain-source saturation voltage ΔVds of that same bias FET.

22. The device of claim 21, comprising: an input FET, the input FET having a drain electrically coupled to receive a drain current specified as a function of the first input current, the input FET in series with the first bias circuit, wherein the first bias circuit is arranged to apply, at a gate of the input FET, the first voltage component in sum with a FET drain-source saturation voltage AVds of the input FET.

23. The device of claim 22, further comprising:
a first output stage, comprising:
a first output FET, having a gate electrically coupled to apply a voltage equal to the voltage at the gate of the input FET, a drain of the output FET providing a first output current that is mirrored or scaled as a specified function of the first input current; and
a first cascode FET, in series with the first output FET to pass the first output current between a drain and a source of the first cascode FET, a gate of the first cascode FET biased by the first bias circuit at a voltage that is the second voltage component in sum with a voltage at the gate of the first output FET; and

wherein the first bias circuit is arranged to provide one or more additional FET drain-source saturation voltages ΔVds in series and summed with the second voltage component in sum with a voltage at the gate of the first output FET; and
the first output stage comprises one or more additional cascode FETs in series with the first output FET to pass the first output current between a drain and a source of each of the cascode FETs, gates of the one or more additional cascode FETs respectively coupled to the first bias circuit to receive a corresponding number of one or more additional FET drain-source saturation voltages ΔVds in series and summed with the second voltage component in sum with the voltage at the gate of the first output FET.

24. The device of claim 22, further comprising:
a first capacitor coupled to AC bypass the first voltage component of the bias circuit;
a second capacitor coupled to AC bypass the second voltage component of the bias circuit;
one or more additional capacitors coupled to AC bypass the one or more additional FET drain-source saturation voltages ΔVds;
a first capacitor arranged to AC couple a gate of the first cascode device to an AC ground;
a first resistor, electrically coupled to the first capacitor to create a lowpass filter for a gate voltage of the first cascode FET;
one or more additional capacitors arranged to respectively AC couple corresponding gates of the one or more additional capacitors to AC ground; and
one or more additional resistors, respectively electrically coupled to the one or more additional capacitors to create respective lowpass filters for gate voltages of the one or more additional cascode FETs.

25. The device of claim 23, further comprising:
one or more additional output stages, arranged in parallel with the first output stage, to provide a corresponding one or more additional output currents, the one or more additional output stages respectively including:
an additional output FET, having a gate coupled to apply, at the gate of the additional output FET, a voltage equal to the voltage at the gate of the input FET, a drain of the additional output FET providing an additional output current that is mirrored or scaled as a specified function of the first input current; and
an additional cascode FET, in series with the additional output FET to pass an additional output current between a drain and a source of the additional cascode FET, a gate of the additional cascode FET biased by the first bias circuit at a voltage that is the second voltage component in sum with a voltage at the gate of the additional output FET.

26. A method comprising:
using a first input current to generate a bias FET gate-source bias voltage, Vgs;
dividing Vgs of the bias FET into a first voltage component specified at a FET threshold voltage of that same bias FET and a second voltage component specified at a FET drain-source saturation voltage ΔVds of that same bias FET;
applying at a gate of an input FET of a current mirror/scaler circuit the first voltage component in sum with a FET drain-source saturation voltage ΔVds of the input FET;
applying at a gate of an output FET of the current mirror/scaler circuit a voltage equal to the voltage at the gate of the input FET; and
applying at a gate of a cascode FET of the current mirror/scaler circuit a voltage that is the second voltage component in sum with a voltage at the gate of the first output FET.