# Patent

## Title
Packet Re-transmission controller for block acknowledgement in a communications system

## Abstract

A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with the pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

## Background
FIELD OF THE INVENTION
The present invention relates to a packet re-transmission controller for a block acknowledgement communications protocol in a wireless communication system.
BACKGROUND OF THE INVENTION
FIG. 1A shows a prior art protocol for acknowledging wireless packets on a per-packet basis. A wireless access point shown as AP1 102 transmits a first packet PKT1 106, which the wireless receiving station STA1 104 receives and acknowledges with an acknowledgement packet ACK1 108. The access point AP1 102 similarly sends additional packets PKT2, PKT3, PKT4, and PKT5, each of which is respectively acknowledged by ACK2, ACK3, ACK4, and ACK5. If a particular packet is not received or acknowledged such as PKT6 114, it is retransmitted 116 after an interval of time until it is acknowledged 118.
FIG. 1B shows a prior art block acknowledgement transmission protocol, whereby access point AP1 130 transmits a block of packets PKT1 through PKT6 134, along with a block acknowledgement request 136 which identifies the packets transmitted. If all packets were received, the station 132 sends a single acknowledgement 138 for the received packets PKT1 through PKT6. FIG. 1C shows a prior art block acknowledgement where packets 2 and 4 are not received. AP1 150 sends packets PKT1 through PKT6 154, along with block acknowledgement request 156. The station STA1 152 then acknowledges receipt of packets 1, 3, and 5-6. AP1 150 responds by re-transmitting packets 2 160 and 4 162 with a new block acknowledgement request 164 for retransmitted packets 2 and 4, which are later acknowledged 166.
FIG. 2A shows a block diagram for a prior art block acknowledgement processor 200. Packets to be transmitted are in the form of payload data stored in the host memory 204, which is typically external memory and coupled to a CPU 208 via a memory controller (not shown). The Central Processing Unit (CPU) 208 reads the payload data from host memory 204 and writes a particular block to be transmitted to the packet buffer 202, organizing the data in the packet buffer 202 by arrangement as payload data for each individual packet to be transmitted, shown as pkt1 through pkt 7 205. A Media Access Controller (MAC) 206 reads the packet data, one packet at a time, and forms a frame including a MAC (layer two) source and destination address, other header information, and a CRC (Cyclic Redundancy Check) as is known in the art of packet processing. The resulting data to be transmitted is transferred from host memory 204 and buffered into packet buffer 202, shown as pkt1 . . . pkt7. Optionally, the packet contents may be encrypted using the encryption engine 207 such as a packet at a time shown as epkt1 209, after which the baseband processor 210 performs digital processing and encoding necessary to provide a baseband signal suitable for modulation to a carrier frequency by the PHY 212, amplification 214, and transmission to the antenna 216.
FIG. 2B shows the prior art transmit process 250 performed by the CPU 208 and MAC 206 of FIG. 2A, whereby the CPU moves the data such as pkt1 through pkt7 from host memory to packet buffer in step 254, and the packets are successively transmitted 256 followed by the transmission of a block acknowledgement request 258 which includes identification of the packets transmitted in step 256. If an acknowledgement 260 is received from the remote station with all packets indicated as received, the process ends in step 266. If missing packets are detected, only the missing packets are transferred from host memory to packet memory 261, re-transmitted 262, which optionally includes re-encryption for encrypted packets, and a new acknowledgement request 214 is sent. An acknowledgement is subsequently received in step 260, either indicating all packets have been received, or providing a list of packets yet to be received.
FIG. 2C shows the arrangement of data in the packet buffer 202 of FIG. 2C, which may be an on-chip part of the MAC 206. The memory buffer 202 is divided into discrete units, each of which contains payload data for a particular packet which have been transferred from host memory 204. In one version of the prior art, when packets are not received by a station, such as packets 2 and 4 as shown 204, the packet buffer contents remain along with the previously sent packets, as shown in FIG. 2D, until the missing packets 204 are successfully transmitted, after which the packet buffer may be fully overwritten with the new packet buffer contents for the next block. During the interval of time awaiting confirmation of receipt of the block of data which includes the lost packets, the on-chip memory 202 is unavailable for any other purpose, such that for the example of a 7 packet transmission, for which 2 were lost, the received 5 packets remain in the buffer until the retransmitted two packets are acknowledged. In another version of the prior art, the host memory is used for temporary storage of transmitted packets until acknowledgement, which requires CPU bandwidth resources and MAC bandwidth and memory resources to re-transfer the missing packets from the host memory to packet buffer memory. If the lost packet requires encryption, the replacement packet it typically re-encrypted, requiring additional encryption resources.
One problem of the prior art block acknowledgement processors is that the packet buffer 202 remains filled with previously-sent packets, and remains unusable for a block of new packets until the missing packets of the previous block are transmitted and acknowledged.
Another problem of the prior art block acknowledgement processor is that computationally intensive operations, such as the encryption performed by processor 207, must be performed each time a packet is to be re-transmitted.
OBJECTS OF THE INVENTION
A first object of this invention is a packet re-transmit processor for a wireless system whereby pointers are used to identify packets to be transmitted, each packet to be transmitted is stored in a host memory, the retransmit controller is responsible for delivering the packets from a host memory to a MAC memory and to an optional encryption engine, thereafter to a block buffer, such that if a transmitted packet is not subsequently block acknowledged, the unacknowledged packet is retransmitted from the block buffer, thereby saving the time required to transfer the packet from host memory to packet memory, and the time and computation resources required to re-encrypt the packet.
A second object of the invention is a re-transmit processor which manages a pointer memory comprising a series of pointers to data stored in a host memory, where the re-transmit processor also manages delivery of data referenced by the pointers from a host memory to a media access controller (MAC) which also performs encryption, the encrypted packets being delivered to a block buffer under control of the re-transmit processor such that any packets which are not acknowledged are re-transmitted directly from the block buffer.
SUMMARY OF THE INVENTION
A wireless access point or station has a host memory for the storage of data to be transmitted, a pointer memory for storage and updating of pointers, each pointer being associated with a particular packet to be transmitted from the host memory, a media access controller (MAC) which optionally includes an encryption engine, and a block buffer for storing packets to be delivered to an output interface. A re-transmission controller handles the assignment of pointers to an associated packet stored in host memory, delivers the data referenced by the packet pointers to the MAC, which MAC adds headers, a CRC, and optionally encrypts the payload data, providing an encrypted packet to the block buffer. After each packet is delivered to the MAC, the associated pointer is cleared, and after each transmitted packet is acknowledged, the associated block buffer data is cleared. In this manner, the host memory contains only data that is to be delivered to the MAC, and the block buffer contains only transmitted data that has not yet been acknowledged by the remote station, which block buffer data is destined either for retransmission or deletion.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows a time diagram for wireless per-packet transmission and acknowledgement.
FIG. 1B shows a time diagram for a block wireless transmission and acknowledgement.
FIG. 1C shows a time diagram for a block wireless transmission and acknowledgement after loss of packets.
FIG. 2A shows the block diagram for a prior art block acknowledgement processor.
FIG. 2B shows a prior art transmit process for the processor of FIG. 2A.
FIG. 2C shows a diagram of the contents of a prior art packet buffer before packet transmission.
FIG. 2D shows a diagram of the contents of a prior art packet buffer after packet transmission with unacknowledged packets.
FIG. 3A shows the block diagram for an acknowledgement processor with a re-transmit controller.
FIG. 3B shows a process flowchart for the acknowledgement process of FIG. 3A.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 3A shows a block acknowledgement processor 300 for one embodiment of the present invention. Host memory 304 contains packets to be transmitted, as before, with packet pointer memory 302 containing pointers to the packets in host memory, shown for pkt1 through pkt7. The packet pointers may be a linked list, pointers to other pointers, or any system for referencing a plurality of packet as is known in the prior art such that each packet in a host memory 304 has an associated pointer stored in pointer memory 302. The CPU 306 is coupled to, and initializes, the pointer memory 302, host memory 304, and retransmit controller 310, after which the retransmit controller 310 uses the pointers stored in pointer memory 302 to direct packet data to the MAC 312, which may optionally contain an encryption stage 314, as was described earlier. During packet transmissions, packets to be transmitted such as pkt1 through pkt7 are addressed by respective pointers ptr1 through ptr7, each packet is moved from the host memory 304 to the MAC 312, which performs typical media access controller operations as described in IEEE standard 802.11a, b, g, or any of the wireless standards which describe the layer 2 mechanism for transport of data. Typically, a source MAC address, destination MAC address, header information, and a CRC are added by the MAC 312. Optionally, packet payload encryption 314 may be performed using the Wireless Encryption Protocol (WEP), or any of the available prior art protocols for data packet security. After encryption 314, the packets are stored in block buffer 316, which has sufficient storage for the number of data packets in a particular block transmission. The block buffer 316 is controlled by the retransmit controller 310, such that encrypted or unencrypted packets from the MAC 312 remain stored in the block buffer 316 after they are sent to the baseband processor 318, which converts to the required wireless signal protocol modulation type such as OFDM, and then upconverts the baseband symbol stream to a carrier frequency such as with PHY 320, amplified 322, after which the packets are transmitted to the remote station via antenna 324. The processor 300 also includes receive signal processing (not shown) which receives packets including block acknowledgement packets which indicate which particular packets of a block were successfully received, the received block acknowledgements applied from the receiver to input 308 of FIG. 3A. After a particular block acknowledgement for the packets in block buffer 316 is successfully received, the corresponding packets are removed from block buffer 316, whereas if an acknowledgement 308 is not received during a timeout interval, the packet is retransmitted using the missing packets remaining in packet buffer 316 until an acknowledgement for the particular transmitted packets 308 is received.
There are several advantages of the present block acknowledgement processor compared to the prior art of FIG. 2A. When packets pkt2 and pkt4 which were sent as encrypted packets are to be re-transmitted, the loss of just a single packet results in a retransmission operation which carries almost the same overhead as the original packet transmission in memory requirements, and a corresponding burden on resources which could be used for transmitting original packets. For the prior art FIG. 2A, the retransmission steps are:
1) Receive ACK which indicates packets pkt2 and pkt4 were not received.
2) Copy missing packets pkt2, pkt4 from Host Memory to Packet Buffer.
3) Establish pointers to begin transmitting missing packets pkt2 and pkt4 from Packet Buffer;
4) Encrypt packets pkt2 and pkt4;
5) send encrypted packets pkt2 and pkt4 to baseband processor for transmission to antenna 216;
6) After acknowledgement of pkt2 and pkt4 reception, delete block of packets pkt1 through pkt7 from host memory.
For the packet retransmission controller of FIG. 3A, the retransmission steps are:
1) Receive ACK which indicates packets pkt2 and pkt4 were not received.
2) Directly retransmit pkt2 and pkt4 from block buffer (pkts remain in block buffer until acknowledgement)
3) After acknowledgement of pkt2 and pkt4 reception, delete pkt2 and pkt4 from block buffer.
Additional functions can be performed by the block buffer 316 of FIG. 3A before placement of the packet in the block buffer. The host memory or packet descriptors may be read to establish address fields, sequence numbers, and other information such as QOS information for use in the packet stored in block buffer 316. Additionally, the packet may be formed and placed in the block buffer 316 after aggregation of two packets of the same type. If the aggregated packet is to be encrypted, the encryption can be performed over the resulting aggregated packet. Additionally, the block buffer 316 can perform the CRC computation on the encrypted or unencrypted packet, since the storage of the packet for retransmission until it is acknowledged as receives eliminates the requirement of re-computing the CRC or re-encrypting a retransmission packet at some point in the future.
There are many ways that the retransmit controller 310 may be realized, however the essential elements of the present invention are the use of a block buffer 316 that receives packets from the MAC 312 (which optionally includes data encryption 314), where the block buffer 316 maintains transmitted packets until they have been acknowledged, after which they are removed or overwritten with new packet transmission buffer data once an acknowledgement is received for an associated packet. Also associated with the re-transmit controller is a pointer memory, which has a set of pointers or descriptors that point to locations in the host memory 304. Each pointer is associated with a particular packet to be transmitted, and after the data stored in the host memory 304 associated with each pointer is moved to the MAC 312, the associated pointer is reinitialized, thereby freeing the pointer for use in storing a different packet. The advantage of storing pointers in on-chip pointer memory 302 rather than the actual packet is the dramatic reduction in memory requirement. The reduction in memory size requirement comes at the expense of greater latency in moving data from host memory to the media access controller, which the block buffer 316 greatly improves by reducing the latency and bandwidth required for retransmission events which would otherwise consume this bandwidth.
FIG. 3B shows a flowchart for the operation of the controller of FIG. 3A. After entry 350, the CPU chains packets in the host memory by arranging the pointers of the pointer memory in step 352. The packets are sent through the MAC and saved to the block buffer, optionally with aggregation or encryption, and are transmitted in step 354, followed by a block acknowledgement request in step 356, after which the unused pointers related to packets sent to the MAC are set to a value of FREE or UNUSED 358. The associated BLK_ACK packet includes the identifiers of the packets successfully received 360 by the remote station. If all packets were received the block buffer is cleared 362 and the process exits 368. If there are lost packets as evidenced by packet identifiers missing from the BLK_ACK packet, the successfully received packets are deleted from the block buffer 364, missing packets are transmitted directly from the block buffer 364, and a new BA_REQ is made 366, after which the process returns to step 360 to await the success or failure of the present re-transmit, after which the successfully received packets are deleted from block buffer 362, and unacknowledged packets are re-transmitted 364 with request for acknowledgement 366.

## Claims

1. A packet handing process for a retransmit controller coupled to a pointer memory, a host memory, a media access controller (MAC) having an input and an output, a block buffer coupled to said MAC output, and an ACK/Retransmit controller receiving acknowledgements for packets in said block buffer, the process having the steps:
a first step of moving a plurality of packets identified by said pointer memory from said host memory to said MAC, said MAC forming frames and transferring said frames to said block buffer;
a second step of transmitting said frames in said block buffer and sending an acknowledgement request;
a third step of receiving acknowledgement of received frames and identifying whether un-acknowledged frames are present in said block buffer;
a forth step of removing said acknowledged frames from said block buffer and retransmitting said un-acknowledged frames from said block buffer with an associated acknowledgement request, repeating said fourth step until no said unacknowledged frames remain.

2. The process of claim 1 where said MAC forming frames includes encryption of a packet.

3. The process of claim 1 where said MAC forming frames includes aggregation of more than one packet into a single frame.

4. The process of claim 1 where said MAC generates a frame check sequence (FCS) or cyclic redundancy check (CRC) from said packet.

5. The process of claim 1 where said retransmit controller generates a frame check sequence (FCS) or cyclic redundancy check (CRC) for said MAC output.

6. A process for a retransmit controller, the retransmit controller operative over a plurality of packet pointers, a host memory, a media access controller (MAC) having an input coupled to said host memory and an output coupled to a block buffer;
said process having a transmission step where packets in said host memory referenced by said pointer memory are transferred to said MAC input, formed into frames, and transferred to said block buffer for transmission;
said process having a re-transmission step where, upon receipt of an acknowledgement for a plurality of packets, any said acknowledgement which includes a frame in said block buffer causes the deletion of said frame, and any acknowledgement that does not include a frame in said block buffer causes the retransmission of said frame.

7. The process of claim 6 where said formed into frames step includes encrypting a packet into a frame.

8. The process of claim 6 where said forming into frames step includes aggregating more than one packet into a frame.

9. The process of claim 6 where said MAC generates a frame check sequence (FCS) or cyclic redundancy check (CRC) from said packet.

10. The process of claim 6 where said retransmit controller generates a frame check sequence (FCS) or cyclic redundancy check (CRC) for said MAC output.

11. A process for a retransmit controller, the retransmit controller operative over a received acknowledgement containing a list of previously received frames, the retransmit controller coupled to a block buffer containing frames which have been previously transmitted, said frames generated by a media access controller adding MAC addresses to payload data;
said process having a re-transmission step where, upon receipt of an acknowledgement for a plurality of packets, any said acknowledgement which includes a frame in said block buffer causes the deletion of said frame, and any acknowledgement that does not include a frame in said block buffer causes the retransmission of said frame.

12. The process of claim 11 where said deletion of said frame includes overwriting an associated range of frame memory with a new frame to be transmitted.

13. The process of claim 11 where said re-transmission step includes re-transmitting any un-acknowledged frame until an acknowledgement is received.

14. The process of claim 11 where said re-transmission step includes, upon receipt of a single acknowledgement indicating receipt or non-receipt of a plurality of associated said frames in said frame memory, repetitively updating a list of remaining un-acknowledged frames and re-transmitting said remaining un-acknowledged frames, deleting each associated acknowledged frame from said block buffer.