# Patent

## Title
Media streaming synchronization

## Abstract

A system and method for synchronously transmitting media data is described. Synchronization data may be transmitted by a cycle master for receipt by one or more cycle slaves. A cycle slave may update an internal state based on the synchronization data received from the cycle master. The cycle master may transmit media data to multiple cycle slaves. The media data output by the cycle slaves may be determined, in part, by the internal state. In one embodiment, the media data may determine which cycle slave receives particular media data.

## Background
RELATED APPLICATIONS
This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 11/197,773, entitled “Media Streaming Synchronization” filed Aug. 3, 2005 which claims priority of U.S. Provisional Patent Application 60/602,723, entitled “Media Streaming Synchronization” filed Aug. 18, 2004.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communication and, more particularly, to the synchronization of clocks in a media data source device and an end device for displaying the media data.
2. Description of the Related Art
Wireless networking can now advantageously provide the wireless distribution of entertainment streaming media to consumers. For example, the Sharp model LC-15L1U-S television can receive streaming audio/video streams from a DVD player using an IEEE 802.11b-based wireless network.
When media traffic is transferred over a wireless network, two different transport models can be used. In a first transport model, called a “pull” model, a receiver coupled to the end device (e.g. the television) requests data when it is needed from the source device (e.g. the DVD player). In this model, the receiver must predict when to request data from the source device such that the data will arrive, even in the event of transient transport failures and latency, in time for display. In a second transport model, called a “push” model, the transmitter coupled to the source device transmits data at a constant rate to the receiver (and thus the end device) for display.
In the push model, the rate at which the data enters the transmitter from the source device (i.e. the transmission rate) should match the rate that the data leaves the receiver to the end device (i.e. the consumption rate), with a fixed latency. Ensuring that the consumption rate substantially equals the transmission rate over a long period of time requires that the clocks of the transmitter and the receiver be synchronized. For example, in MPEG-2 based video stream transport, maintaining time synchronization between the transmitter and the receiver on the order of ±500 nanoseconds (ns) is desirable.
Problematically, drift between similarly specified system clocks could be on the order of 40 parts-per-million (ppm). For example, when a transmitter clock operating at 40 MHz is 20 ppm slow, a receiver clock also operating at 40 MHz could be 20 ppm fast. Although the IEEE 802.11 family of wireless networking standards provides a time synchronization function (TSF), the granularity of the synchronization promulgated is at best 1 microsecond (μs). Specifically, the IEEE 802.11 family of wireless networking standards calls for time synchronization to take place during beacon transmissions, which typically occur with a 100 millisecond period. As a result, using worst-case relative clock rate offsets, a 4 is timing error between transmitter and the receiver could accumulate between beacons.
Therefore, a need arises for a method and system for more closely synchronizing the transmitter and the receiver in a digital media transport system.
SUMMARY OF THE INVENTION
To transport real-time digital media data with low jitter over a wireless network, clocks in a cycle master and a cycle slave need to be accurately synchronized. In accordance with one aspect of the invention, a synchronization packet can be sent from the cycle master to the cycle slave, thereby providing a highly accurate time synchronization function. Specifically, this synchronization packet provides an end-to-end solution in which the media data entering the cycle master can leave the cycle slave with very low jitter (e.g. on the order of ±500 ns). Media data may include several media data types. For example, one media data type may be video media data. Another media data type may be center channel audio.
Media data may be transmitted from the cycle master to multiple cycle slaves. In one embodiment, clocks may be synchronized within the cycle master and the multiple cycle slaves. The media data may be output by the multiple cycle slave devices based upon the state of a clock within the cycle slave devices. In one embodiment, the cycle master may transmit media data to a cycle slave based upon a target address. The target address may be determined by the media data type.
A system for determining a destination for media data may include a cycle master, multiple cycle slaves and a media inspector. Clocks may be synchronized within the cycle master and the multiple cycle slaves. In one embodiment, the media inspector may examine the media data and determine a target address based upon the media data type. The cycle master may transmit media data to cycle slaves based upon the target address. In one embodiment, the cycle master may associate the target address with a MAC address of a cycle slave. In one embodiment, the output of the cycle slave may be based upon the state of the clock in the cycle slave.



BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 illustrates a block diagram of an exemplary wireless streaming media system.
FIG. 2 illustrates a block diagram of exemplary synchronization hardware for a cycle master.
FIG. 3A illustrates a block diagram of an exemplary cycle slave.
FIG. 3B illustrates a block diagram of exemplary synchronization hardware for a cycle slave.
FIG. 4 illustrates a timeline diagram of received signals and, in particular, the relationship of timing reference point (TRP) events, sequential synchronization packets, and cycles counted between TRP events.
FIG. 5 illustrates the layout of data in a synchronization packet.
FIG. 6A illustrates another timeline diagram of received signals and, in particular, the relationship of TRP events, non-sequential synchronization packets, and cycles counted between TRP events.
FIG. 6B illustrates an exemplary technique that can compensate for a missing synchronization packet.
FIG. 7 illustrates a method of synchronizing two clocks in source and end devices.
FIG. 8 is a block diagram of another embodiment of an exemplary wireless streaming media system.



DETAILED DESCRIPTION OF THE FIGURES
FIG. 1 illustrates an exemplary wireless media system 100 including a DVD player 101 (i.e. a source device) and televisions 105/108 (i.e. end devices) that can communicate using a wireless communication network. This wireless communication network includes transceivers 103, 106, and 109 as well as antennas 104, 107, and 110. In wireless media system 100, DVD player 101 can send a video/audio stream 102 (e.g. an MPEG-2 stream) to transceiver 103. In turn, transceiver 103, which functions as a transmitter, uses its antenna 104 to wirelessly transmit this data stream to any receivers. For example, both transceivers 106 and 109 (and their corresponding antennas 107 and 110) can function as receivers. Transceivers 106 and 109 can forward video/audio stream 102 to televisions 105 and 108, respectively. For simplicity, transceiver 103 is hereinafter called a “cycle master” whereas transceivers 106 and 109 are hereinafter called “cycle slaves”.
FIG. 2 illustrates exemplary synchronization hardware 200 for a cycle master. Synchronization hardware 200 can include an oscillator 201 coupled to a timestamp timer 202, thereby triggering timestamp timer 202 to increment upon each cycle of oscillator 201. (Thus, as used herein, the term “timestamp timer” counts time, not the timestamp values.) In one embodiment, oscillator 201 can be a 40 MHz crystal-based oscillator. A synchronization packet generator 203 samples the contents of timestamp timer 202 and periodically (based on a TRP event 208, described below) directs a synchronization insertion block 205 to insert a synchronization packet 204 into a stream of media packets 206. In one embodiment, synchronization packets 204 can be sent at 100 ms (or more frequent) intervals. Note that synchronization packet 204 is not merged into a media packet, but is rather interspersed between media packets 206. Thus, in one embodiment, synchronization insertion block 205 inserts synchronization packet 204 into the stream of media packets 206 as soon as possible after the receipt of synchronization packet 204. The combination of media packets 206 and synchronization packets 204, generically referenced as packets 207, are transmitted by the cycle master.
FIG. 3A illustrates an exemplary cycle slave 300 that can receive signals using an antenna 301. These signals can be provided to a packet detection block 302, which can detect packets 303. A timing reference point (TRP) event detection block 304 can determine TRP events 314 of a packet with high accuracy (e.g. on the order of ±50 ns). For example, an exemplary TRP event 314 could be a “medium_free” event (sometimes also called as an “rx_clear”) that is measured between the end of one packet and the beginning of the next packet. Other stable, detectable timing points associated with a packet can be used to provide equally viable TRP events. For example, other TRP events could include, but are not limited to, the start of a packet, the end of a packet, or the start/end of a Signal field (i.e. the encoded field indicating what type of data is being transmitted).
A packet type filter 354 determines whether packets 303 are media packets 305 or synchronization packets 306. Media packets 305 can be sent to a media packet separator 307, which extracts its associated timestamp 319A (which indicates a desired delivery time for the packet), and then forwards remaining media data 319B to a media gate 308. Note that media packet 305 can conform to the format discussed in U.S. patent application Ser. No. 10/934,869, entitled “Efficient Data Transmission By Data Aggregation”, filed on Sep. 3, 2004 by Atheros Communications, Inc., and incorporated by reference herein.
In one embodiment, media gate 308 can include a first-in-first-out (FIFO). Based on a gate control signal 309 (described in reference to FIG. 3B), a media gate 308 can send media packets 305 as a media stream 310. If a packet 303 is a synchronization packet 306 and a TRP event 314 occurs, then a synchronization packet separator 311 can identify a timestamp 312 and a sequence identifier 313 (both explained in reference to FIG. 4).
FIG. 3B illustrates exemplary synchronization hardware 320 for a cycle slave. Synchronization hardware 320 can include an oscillator 321 coupled to a timestamp timer 322, thereby triggering timestamp timer 322 to increment upon each cycle of oscillator 321. In one embodiment, oscillator 321 can also be a 40 MHz crystal-based oscillator (i.e. a similar oscillator as used in the cycle master). In another embodiment, oscillator 321 can have a frequency different than that of the cycle master. Notably, these nominally fixed frequencies of the cycle master and cycle slave oscillators and in particular the relationship between the frequencies, can be used to perform the functions described herein.
Timestamp 312, extracted from a synchronization packet (as shown in FIG. 3A), can be sent to a summing block 325. When a first TRP event 314 is detected, trigger 318 can initialize a timestamp delta counter 323, which then begins incrementing at the same 40 MHz rate as timestamp timer 322. When a subsequent TRP event 314 occurs (once again, using trigger 318), timestamp delta counter 323 can trigger summing block 325 to add the contents of timestamp delta counter 323 to timestamp value 312 (noting that TRP event 314 generates trigger 318 before timestamp 312 changes to reflect the subsequent packet) and send that sum to update timestamp timer 322. The advantages of using this TRP event to generate a value in timestamp delta counter 323 (called a “count”) are described in reference to FIG. 4.
FIG. 4 illustrates a timeline diagram 400 indicating the relationship between TRP events, received synchronization packets, and cycles counted from one TRP event to a subsequent TRP event (i.e. the count). Note that the TRP events are indicated in a system (i.e. a cycle master or a cycle slave) between any two packets and not just between synchronization packets. Therefore, a synchronization packet could be transmitted/received between multiple media packets. As described previously in reference to FIG. 3A and now described in further detail in reference to FIG. 5, each synchronization packet includes a timestamp and a sequence.
FIG. 5 illustrates an exemplary layout of a synchronization packet 500. Notably, synchronization packet 500 can advantageously conforms to a standard 802.11 packet. Specifically, synchronization packet 500 can include a frame control field (2 octets in length), a duration/identification field (2 octets in length), address 1-3 fields (each 6 octets in length), a sequence control field (2 octets in length), an address 4 field (6 octets in length), a frame body field (0-2312 octets in length), and an FCS field (4 octets in length). Notably, only two fields include relevant information: the frame control field 501 and the frame body 502.
In one embodiment, for packet type filter 354 (FIG. 3A) to detect that this is a synchronization packet (rather than a streaming data packet or a beacon packet, for example), software can set the frame type in frame control field 501 to indicate a synchronization packet (0x7) is being received. Note that frame type usage can be consistent with that described in the IEEE-802.11-1999 specification, §7.1.3.1.2, by using currently reserved bits.
The actual synchronization information can be provided in frame body 502. This synchronization information can include a timestamp 511 and a sequence number 512. Sequence number 512 can be compared to the sequence number of the last synchronization packet, thereby allowing a determination as to whether synchronization packets are sequentially received. Note that the values for sequence numbers are arbitrary, although consecutive sequence numbers typically vary by “1”.
In one embodiment, timestamp 511 can be 4 octets in length, i.e. 32 bits (or, in one embodiment, 31 bits with 1 bit reserved), whereas sequence 512 can be 2 octets in length, i.e. 16 bits. Note that the IEEE 802.11 standard provides for the processing of data in octets. Therefore, exemplary octets for timestamp 511 (i.e. sync timestamp 0, sync timestamp 1, sync timestamp 2, and sync timestamp 3) and sequence 512 (i.e. sync sequence 0 and sync sequence 1) are shown. In one embodiment, sequence 512 can include a running, 16-bit binary count of the synchronization packets sent by the cycle master (discussed in further detail in reference to FIGS. 6A and 6B).
A timestamp offset [7:0] register 315 (FIG. 3A) can be set to specify the number of bytes from the end of the header (i.e. the end of the address 4 field) to the first byte of timestamp 511. Similarly, a sequence offset [7:0] register 316 (FIG. 3A) can be set to specify the number of bytes from the end of the header to the first byte of sequence number 512. In one embodiment, these offset registers can be controlled by the software run by synchronization packet separator 311.
Hardware detects a synchronization packet 500 when the received address 1 (i.e. the network address to which the packet is being sent) matches a synchronization multicast address [47:0] value and the Basic Service Set ID (BSSID) also matches. Note that BSSID usage is consistent with that described in the IEEE-802.11-1997 specification, §7.2.2. In one embodiment, the synchronization multicast address can also be set in a register controlled by software.
Referring to FIG. 4, the timestamps (e.g. Tm(?), Tm(a), and Tm(b)) included within the synchronization packets (e.g. sync(a), sync(b), and sync(c)) are completely independent of the IEEE 802.11 timestamps that are transferred in beacons. Specifically, a beacon timestamp has a 1 is resolution, whereas the synchronization timestamp can have, for example, a 10-25 ns resolution. Moreover, the cycle master that generates the synchronization packet does not need to be an access point (AP), a hybrid coordinator (HC), or even the cycle master of the multimedia data. However, in accordance with one aspect of the invention, only one cycle master is allowed in a basic service set (BSS). Based on empirical measurements of crystal oscillators typically used in wireless networking equipment, the maximum difference in the clock frequency between the cycle master and the cycle slave is assumed to be 40 ppm.
Therefore, in general, the beacon packets can provide a first relatively coarse synchronization, whereas the synchronization packets can provide a second synchronization, wherein the second synchronization can be significantly more accurate than the first synchronization. This accurate synchronization is particularly useful for applications that wirelessly transmit streaming media data.
Advantageously, a baseband data formatter can indicate with accuracy the rising edge of a TRP event. As noted previously, TRP events can be generated after both synchronization and media packets. Therefore, in one embodiment shown in FIG. 3A, a counter trigger block 317 can receive both TRP events 314 as well as synchronization packets 306, thereby triggering a count that conforms with that shown in FIG. 4.
Specifically, in accordance with one aspect of the invention, the count can include the number of cycles between the end of one synchronization packet (e.g. sync (a), the first synchronization packet) and the end of the next synchronization packet (e.g. sync (b)). Notably, time synchronization relies on a synchronization packet that includes the timestamp at the rising edge of a TRP event for a previous synchronization packet that was sent. For example, sync (b) cannot include its own timestamp because the rising edge of a TRP event occurs after sync(b) has completed transmission. Therefore, sync(b) can include the timestamp Tm(a), which is associated with sync(a). For this reason, sync(a) has a “don't care” timestamp Tm(?), which is not used (i.e. ignored).
When the cycle slave receives a synchronization packet, a summing block (e.g. summing block 325 in FIG. 3B) can update its version of the timestamp (e.g. the value stored in timestamp timer 322) to the value of the received timestamp (e.g. timestamp 312) plus the count (e.g. Tm(a)+n). Note that in one embodiment, two synchronization packets must be received sequentially to perform an update on the timestamp. Notably, because the local timestamps of the cycle master and the cycle slave as well as the timestamp timer are generated by oscillators having substantially the same frequency, then Tm(a)+n should be equal to Tm(b) if there is no drift. That is, any drift between the two oscillators can be advantageously detected by measuring the difference between Tm(a)+n and Tm(b).
Notably, synchronization hardware 200 (FIG. 2) of the cycle master is tolerant to significant amounts of jitter because the insertion of the timestamp (e.g. timestamp 511) occurs in hardware as the synchronization packet is transmitted. In this manner, the synchronization packets can present an accurate accounting of transmit delays due to software or carrier-sensing delays. In one embodiment, because sequences are assigned based on specific timing constraints, software can queue the synchronization packets with their corresponding sequences, e.g. sequence 512, before transmission occurs.
As indicated above and referring back to FIGS. 3A and 3B, media packets 305 are held temporarily by media gate 308. Specifically, when the value stored by timestamp timer 322 (or a derivative value discussed below) is later than timestamp 319A (wherein timestamp 319A indicates a desired delivery time), then a comparator 329 outputs a gate control signal 309 that is provided to media gate 309. This gate control signal 309 triggers media gate 308 to send media data 319B in a media stream 310 to the end device for display.
In one embodiment, a summing block 331 can add a constant offset 330 to the value stored in timestamp timer 322 before it is used by media gate 308, thereby advantageously forming a fixed output delay for media stream 310. This delay effectively creates a buffer, which may be sized such that stream interruptions, for example, a retransmission of a packet incorrectly received, does not cause a stall in the flow of media stream 310.
In one embodiment, a digital delta trim block 327 can alter the increments used by timestamp timer 322. Specifically, digital delta trim block 327 may “tune” the increment based on a difference between the counts (as computed by timestamp delta counter 323) and timestamps 312. (Note that if both 40 MHz clocks in the cycle master and the cycle slave were running with exactly the same frequency, then the count and the difference in timestamps at the cycle slave would be the same.)
In a typical embodiment, time stamp counter 322 can increment by “1” on every cycle. However, in another embodiment, quicker agreement of cycle master and cycle slave clocks may be achieved by occasionally incrementing the value stored in timestamp timer 322 by 2 when the cycle slave clock is too slow. In yet another embodiment, quicker agreement of cycle master and cycle slave clocks may be achieved by occasionally incrementing the value stored in timestamp timer 322 by 0 when the cycle slave clock is too fast. Increment values other than +1 are referred to as “tuning” events and can occur every I samples apart (“span”).
Table 1 provides exemplary values illustrating the input data for a calculation of a span between a choice of a timestamp timer increment other than +1 and the choice of increment. Table 2 indicates the calculated tuning parameters using the exemplary values of Table 1. Note that the cycle slave timestamps (e.g. Ts(a) and Ts(b), generically shown as timestamp 332 in FIG. 3B) can be generated using hardware similar to that used in the cycle master (i.e. timestamp timer 202 and synchronization packet generator 203 shown in FIG. 2). In Table 2, the exemplary choices for alternative increment amounts are +2 and +0. Note that the synchronization packets shown in FIG. 4 (i.e. sync(a) and sync(b)) are used in the computations for illustration purposes.







TABLE 1







Delta Trim Calculation Exemplary Data











Name
Definition
Example















I
Current span value
100



Ts(a)
Time at slave at sync(a)
997



Ts(b)
Time at slave at sync(b)
2002



Tm(a)
Time at master at sync(a)
1000



Tm(b)
Time at master at sync(b)
2000



Ds
Time interval between sync(a)





and sync(b) at slave




Dm
Time interval between sync(a)





and sync(b) at master




E
Error: Difference between Ds and





Dm




S
Number of tuning events between





sync(a) and sync(b)




S′
Next version of S




I′
Next version of I

















TABLE 2







Calculated Tuning Parameters












Name
Equation
Calculation
Result
















Ds =
Ts(b) − Ts(a) =
2002 − 997 =
1005



Dm =
Tm(b) − Tm(a) =
2000 − 1000 =
1000



E =
Ds − Dm =
1005 − 1000 =
5



S =
Ds/I =
1005/100 =
10



S′ =
S − E =
10 − 5 =
5



I′ =
Ds/S′ =
1005/5 =
201










In this example, the time interval between sync(a) and sync(b) at the cycle slave (Ds) is 1005 cycles. That is, 1005 cycles have been measured between synchronization packets at the cycle slave. In contrast, the time interval between sync(a) and sync(b) at the cycle master (Dm) is 1000 cycles. That is, 1000 cycles have been measured between synchronization packets at the cycle master. The difference between Ds and Dm, i.e. the error (E), is 5 cycles. The previously determined number of tuning events (S), as determined by dividing Ds by the current span value (I), is 10 cycles. Therefore, the number of cycle slave clock cycles between synchronization packets should be reduced by 5. This value corresponds to the next version of S (S′). The next version of I (I′), which is determined by dividing Ds by S′, is 201 cycles.
Because the number of cycles measured between synchronization packets at the cycle slave exceeds the corresponding number of cycles at the cycle master, the increment value chosen for a tuning event is +0. In this example, the desired reduction in cycle slave clock cycles can be accomplished by performing 5 tuning events in which increments are +0 instead of +1. In one embodiment, if the number of cycles measured between synchronization packets at the cycle master exceeds the corresponding number of cycles at the cycle slave, the increment value chosen for a tuning event could be set instead to +2.
In some embodiments, the rate at which synchronization packets are transmitted can be varied. By initially sending more frequent synchronization packets, digital delta trim block 327 may receive more frequent updates and thus more quickly adapt the slave clock rate to the master clock rate. This adjustment advantageously accommodates a quick clock adjustment with a subsequent reduction in synchronization packet rate, thereby conserving shared bandwidth.
In one embodiment, the rate of synchronization packets can be adjusted by digital delta trim block 327 sending a feedback value 333 to the cycle master, wherein feedback value 333 indicates a measure of change in tuning values. For example, greater variation in digital delta trim block tuning values would trigger an increase in the synchronization packet rate. This rate adjustment technique can advantageously dynamically allocate synchronization packet bandwidth concomitant with need.
FIG. 6A illustrates a timeline diagram 600 indicating the relationship between TRP events, synchronization packets, and cycles counted from one TRP event to a subsequent, but not immediately sequential, TRP event (i.e. the sequence number between sync(a) and sync(c) will not be sequential). In this case, hardware should detect that at least one synchronization packet has been lost. Under these circumstances, the timestamp is difficult to update because the count is counting from the rising edge of timing for sync(a), and timestamp Tm(b) (included in synchronization packet sync(c)) assumes that a count from sync(b) has been made. Therefore, in one embodiment, the above-described missing synchronization packet can be handled by calculating one or more pseudo-timestamps representing a timestamp history and selecting the correct timestamp(s) for the calculation based on the received sequence number.
For example, if, in a synchronization packet, multiple timestamps representing the current timestamp associated with a sequence number n, {TSn, TSn-1 . . . TSn-m}, the difference in received, non-sequential sequence numbers can be used to select, for m skipped sync packets, a TSn-m for processing, because the previously received synchronization packet and currently received, non-sequential synchronization packet include sufficient information (assuming less than m synchronization packets have been lost) to treat the previously received synchronization packet and the currently received, non-sequential synchronization packet as though they were, effectively sequential. Advantageously, these additional timestamps (and associated synchronization packets) represent a small overhead (4 bytes per additional timestamp) over a single synchronization packet. In one embodiment, a timestamp value is not updated until sequential packets are received.
FIG. 6B illustrates an exemplary technique that can compensate for a missing synchronization packet. Step 610 determines if a received packet is in sequential order by comparing its sequence number, e.g. sequence number 512 (FIG. 5), and the sequence number of the last received synchronization packet. If the sequence numbers are sequential, then step 611 continues to process the synchronization packet. If the sequence numbers are not sequential, then step 612 can advantageously calculate one or more pseudo timestamps based on the current timestamp and a number of previously sent timestamps, wherein frame body 502 could include multiple timestamps 511 (e.g. timestamps 511A-511D, shown in the dashed box, each having 4 octets), called herein a compiled timestamp 511′.
For example, in one embodiment, a timestamp represents a time delta as measured by a TRP event (e.g. “medium_free” event). Compiled timestamp 511′ could include a compilation of synchronization timestamps, e.g. the current timestamp and from the last three previously sent timestamps. By comparing the received compiled timestamps 511′, the redundant information provided in timestamps 511A-511D can advantageously facilitate a reconstruction of probable timestamps that are missing. That is, assuming that four timestamps are provided in compiled timestamp 511′, then sequential packets should have three identical timestamps. If only two timestamps are identical, then one packet has not been received. However, by using the two identical timestamps and the current timestamp, a pseudo timestamp for the missing packet can be calculated.
FIG. 8 is a block diagram of another embodiment of an exemplary wireless streaming media system 800. The wireless streaming media system 800 may include multiple transceivers wherein at least one of the transceivers may be a cycle master. In this exemplary embodiment, transceiver 815 serves as a cycle master while transceivers 820, 825 and 830 are designated as cycle slaves. A wireless streaming media system may include at least two transceivers, however only four are shown here. Further, a wireless streaming media system may include an arbitrary maximum number of transceivers. For example, a wireless streaming media system supporting five audio signals may include seven transceivers: one for a cycle master, one for a video monitor or television, and five for audio signals.
The cycle slave transceivers 820, 825, and 830 are configured to receive media data from the cycle master. Cycle slave 820 may be coupled to the television 108 and may receive video media data. Cycle slaves 825 and 830 may be configured to receive audio media data for reproduction on speakers 850 and 851, which may be coupled to the cycle slaves 825 and 830 respectively.
A dvd player 805 may be coupled to a media inspector 810 and may provide media data, such as audio and video signals, to the media inspector 810. In one embodiment, multiple audio signals may be provided (such as left front, right front, center, left surround and right surround). Alternative embodiments may replace the dvd player 805 with other media data sources such as, but not limited to, VCRs and media-enabled personal computers.
The media inspector 810 examines the media data from the dvd player 805 and determines a target address associated with the media data. In one embodiment, the target address may correspond to a media data type. For example, one media data type may be video media data. Another media data type may be center channel audio. Thus, a particular media data type may be associated with an output location (e.g., center channel audio media data may be associated with a center channel speaker). A cycle slave may be associated with an output location. In one embodiment, the target addresses may be encoded with four data bits. The target address 811 and the related media data 812 are coupled to a port 817 included in the cycle master 815. In one embodiment, the port 817 may include multiple pins to receive the target address 811 and the media data 812. In one embodiment, the media inspector 810 may be external to the cycle master 815 as shown. For example, the media inspector 810 may be implemented by a field-programmable gate array (FPGA) or a state machine. In another embodiment, the media inspector 810 may be incorporated into the cycle master 815 or the dvd player 805.
The cycle master 815 may examine the target address 811 and determine to which client slave to transmit the related media data 812. In one embodiment, each client slave may have a related MAC (media access control) address. The cycle master 815 may use a table to associate a target address 811 to a MAC address and thus to a cycle slave. Table 3 below is an exemplary table mapping target addresses to MAC address.







TABLE 3







Target Address to MAC Address Map









Target Address
MAC Address
Cycle Slave












0
00-16-41-A0-C8-9A
Video Display


1
00-16-41-A0-C8-9B
Left Front Speaker


2
00-16-41-B0-C8-9C
Right Front Speaker


3
00-16-41-A0-C8-9D
Center Speaker


4
00-16-41-A0-C8-9E
Left Surround Speaker


5
00-16-3F-A0-C8-9F
Right Surround Speaker









The media synchronization techniques described in conjunction with FIGS. 2-7 may be applied to the wireless streaming media system 800 shown in FIG. 8 as well. In one embodiment, synchronization packets may be sent by the cycle master 815 to the cycle slaves 820-830. Since each cycle slave 820-830 includes the synchronization hardware described in FIGS. 3A and 3B, media data may be delivered by the cycle slaves synchronized to the cycle master timestamp timer 202 (FIG. 2).
The wireless streaming media system 800 advantageously transmits media data to multiple targets by transmitting media data to individual cycle slaves and enables relatively synchronous output of media data. For example, if media data is multicast, the cycle slaves may not be required to acknowledge the reception of the media data. Thus, the cycle master may not be alerted if a collision or other event that may corrupt the transmitted data may occur. In contrast, since media data is unicast (i.e., transmitted from one transceiver to another transceiver), cycle slaves may acknowledge reception of media data. Thus, the cycle master may retry sending dropped packets including media data.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. As such, many modifications and variations will be apparent.
For example, the IEEE-802.11-1999 specification provides a Frame Check Sequence (FCS) mechanism for detecting corrupted data packets. In one embodiment, software can perform a further validation of timestamp data by using the value stored in the FCS field of synchronization packet 500 (FIG. 5). Specifically, the software can check that the time reported in the timestamp is not inconsistent (i.e. a timestamp substantially greater than can be accounted for by relative clock drift) with previous timestamps, and the synchronization packet may be rejected if this check fails.
In one embodiment, both the beacon and the synchronization packets can provide synchronization functions. For example, referring to FIG. 7, a method 700 of synchronizing two clocks in source and end devices is provided. In step 701, a beacon packet can be used to provide a first synchronization accuracy. In step 702, a synchronization packet can be used to provide a second synchronization accuracy, wherein the second synchronization accuracy can be significantly better than the first synchronization accuracy. In one embodiment, performing step 701 before step 702 can facilitate more quickly attaining the second synchronization accuracy. That is, once the first, rough synchronization accuracy is achieved, fine tuning the synchronization using the above-described methods (see, for example, FIGS. 3A, 3B, and 4) can rapidly achieve the second, more accurate synchronization. With such improved synchronization accuracy, streaming media can be transmitted from the source device to the end device with minimal jitter.
Accordingly, it is intended that the scope of the invention be defined by the following Claims and their equivalents.

## Claims

1. A method of transmitting media data from a cycle master to multiple cycle slave devices and outputting the media data, the method comprising:
synchronizing clocks within the cycle master and the multiple cycle slave devices;
selecting one or more of the multiple cycle slave devices;
transmitting the media data to each selected cycle slave device using a target address associated with a media data type of the media data; and
outputting the media data from each selected cycle slave device based upon a state of a clock within each selected cycle slave device, wherein the outputting is controlled by an offset added to the clock within each selected cycle slave device.

2. The method of claim 1, wherein transmitting the media data includes associating each target address with an associated MAC address for a selected cycle slave device.

3. The method of claim 2, wherein the media data type of the media data includes at least one of audio and video.

4. The method of claim 2, wherein the selecting is performed using a table.

5. A system for determining a destination for media data, the system comprising:
a cycle master for transmitting the media data;
multiple cycle slaves, each cycle slave including a clock synchronized to a cycle master clock; and
a media inspector configured to determine which of the multiple cycle slaves receive the media data based on information associated with the media data,
wherein outputting of the media data from one or more selected cycle slaves is controlled by an offset added to the clock within each selected cycle slave.

6. The system of claim 5, wherein the media inspector determines which of the multiple cycle slaves receive the media data based on an identified output location of the media data, which corresponds to at least one cycle slave.

7. The system of claim 5, wherein the media inspector determines a target address based on a media data type of the media data.

8. The system of claim 7, wherein the target address is associated with an output location.

9. The system of claim 7, wherein the target address is four-bits wide.

10. The system of claim 5, wherein the media inspector includes an FPGA.

11. The system of claim 5, wherein the media inspector includes a state machine.

12. The system of claim 7, wherein the cycle master determines which of the multiple cycle slaves receive the media data based on the target address.

13. The system of claim 12, wherein the cycle master associates the target address with one or more cycle slave MAC addresses.

14. The system of claim 13, wherein the target address and the one or more cycle slave MAC addresses are stored in a table.

15. The system of claim 5, wherein the cycle master includes a port configured to receive a target address and the media data provided by the media inspector.

16. The system of claim 15, wherein the media inspector determines the target address based on a media data type of the media data.

17. The system of claim 16, wherein the cycle master associates the target address with one or more cycle slave MAC addresses.

18. The system of claim 17, wherein the target address and the one or more cycle slave MAC addresses are stored in a table.