# Patent

## Title
Bandgap reference circuit with low operating voltage

## Abstract

A bandgap reference circuit comprising a current mirror, an operational amplifier, first and second BJT transistors is disclosed. The current mirror comprises a first input terminal, a second input terminal and at least one output terminal. The operational amplifier is coupled to the current mirror, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have a zero or near zero threshold voltage. The first and second BJT transistors are coupled to two input terminals of the operational amplifier respectively, wherein at least one of the first and second BJT transistors is coupled to the output terminal of the current mirror through a conductive path.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a bandgap reference circuit, and more particularly to a bandgap reference circuit with low operating voltage.
2. Description of the Related Art
Reference voltage is typically required to provide a substantially constant output voltage despite gradual or momentary changes in input voltage, output current or temperature. In particular, many designers have utilized bandgap reference circuits due to their ability to provide a stable voltage supply that is insensitive to temperature variations over a wide temperature range. These bandgap references rely on certain temperature-dependent characteristics of the base-emitter voltage of a transistor. Bandgap reference circuits typically operate on the principle of compensating the negative temperature coefficient of a base-emitter voltage of a bipolar transistor with the positive temperature coefficient of the thermal voltage. In general cases, the temperature-independent voltage is around 1.25V, and if the system cannot provide sufficient voltage, the bandgap reference circuit may cause errors or fail to operate, i.e. based on the present architecture of bandgap reference circuits, the bandgap reference circuit cannot operate at a voltage 1.2V or lower.
BRIEF SUMMARY OF THE INVENTION
The invention provides an operational amplifier comprising a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth NMOS transistor. The first NMOS transistor has zero or near zero threshold voltage, a first gate for receiving a first input signal, a first source, and a first drain. The second NMOS transistor has zero or near zero threshold voltage, a second gate for receiving a second input signal, a second source, and a second drain. The third PMOS transistor has a third gate, a third source, and a third drain, wherein the third source is coupled to a high voltage source, and the third gate and the third drain are coupled to the first drain. The fourth PMOS transistor has a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is coupled to the high voltage source, and the fourth gate is coupled to the first drain and the fourth drain is coupled to the second drain. The fifth NMOS transistor has a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate receives a bias voltage, the fifth drain is coupled to the first source and the second source, and the fifth source is grounded.
The invention further provides an operational amplifier comprising a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth PMOS transistor. The first PMOS transistor has zero or near zero threshold voltage, a first gate for receiving a first input signal, a first source, and a first drain. The second PMOS transistor has zero or near zero threshold voltage, a second gate for receiving a second input signal, a second source, and a second drain. The third NMOS transistor has a third gate, a third source, and a third drain, wherein the third source is grounded, the third gate and the third drain are coupled to the first drain. The fourth NMOS transistor has a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is grounded, and the fourth gate is coupled to the first drain and the fourth drain is coupled to the second drain. The fifth PMOS transistor has a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate receives a bias voltage, the fifth drain is coupled to the first source and the second source, and the fifth source is coupled to a high voltage source.
The invention further provides a temperature-independent system comprising a positive temperature coefficient compensation unit, a negative temperature coefficient compensation unit, and an operational amplifier. The positive temperature coefficient compensation unit has a positive temperature coefficient k1 and outputs a first voltage V1. The negative temperature coefficient compensation unit has a negative temperature coefficient k2 and outputs a second voltage V2, wherein α1 and α2 satisfy a first equation: α1k1+α2k2=0. The operational amplifier has a first input terminal receiving the first voltage, a second input terminal receiving the second voltage and an output terminal outputting an output voltage Vo, wherein a first NMOS transistor and a second NMOS transistor respectively coupled to the first and the second input terminals have zero or near zero threshold voltage, and the output voltage Vo satisfies a second equation: Vo=α1V1+α2V2.
The invention further provides a bandgap reference circuit comprising an operational amplifier, a first resistor, a second resistor, a third resistor, a first bipolar transistor, and a second bipolar transistor. The operational amplifier has a first input terminal, a second input terminal receiving the second voltage and an output terminal, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have zero or near zero threshold voltage. The first resistor has a first terminal coupled to the output terminal, and a second terminal coupled to the first input terminal. The second resistor has a third terminal coupled to the output terminal, and a fourth terminal coupled to the second input terminal. The third resistor has a fifth terminal coupled to the second input terminal, and a sixth terminal. The first bipolar transistor has a first base, a first collector, and a first emitter, wherein the first base and the first collector are coupled to the first input terminal, and the first emitter is grounded. The second bipolar transistor has a second base, a second collector, and a second emitter, wherein the second base and the second collector are coupled to the sixth terminal, and the second emitter is grounded.
The invention further provides a bandgap reference circuit comprising a current mirror, an operational amplifier, first and second BJT transistors. The current mirror comprises a first input terminal, a second input terminal and at least one output terminal. The operational amplifier is coupled to the current mirror, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have zero or near zero threshold voltage. The first and second BJT transistors are coupled to two input terminals of the operational amplifier respectively, wherein at least one of the first and second BJT transistors is coupled to the output terminal of the current mirror through a conductive path.
A detailed description is given in the following embodiments with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is a cross section diagram of a native NMOS transistor.
FIG. 2 is a circuit diagram of an embodiment of an NMOS-input-based operational amplifier.
FIG. 3 is a circuit diagram of an embodiment of a PMOS-input-based operational amplifier.
FIG. 4 is a block diagram of an embodiment of a temperature-independent system.
FIG. 5 shows a method for obtaining a temperature-independent voltage.
FIG. 6 is a circuit diagram of an embodiment of a proportional-to-absolute-temperature voltage generator.
FIG. 7 is a circuit diagram of an embodiment of a bandgap reference circuit.
FIG. 8 is a circuit diagram of another embodiment of a bandgap reference circuit.
FIG. 9 is a circuit diagram of another embodiment of a bandgap reference circuit.



DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 is a cross section diagram of a native NMOS transistor. A gate structure 13 formed on the P-substrate 11 and a conductive metal area 15 is disposed on the gate structure 13 for receiving a bias voltage V. Two N-type doped regions 12 and 14 are formed in P-substrate 11 to form the source and drain of the native NMOS transistor. When the bias voltage V is applied on the gate structure 13, a channel 16 formed beneath the gate structure 13. In the native NMOS transistor shown in FIG. 1, the amount of the bias voltage V is extremely small, and can even be brought to zero, by adequate semiconductor process.
FIG. 2 is a circuit diagram of an embodiment of an NMOS-input-based operational amplifier. PMOS transistor M23 has a source coupled to a high voltage source VDD, a drain and a gate coupled to the drain. PMOS transistor M24 has a source coupled to the high voltage source VDD, a gate coupled to the gate of the PMOS transistor M23, and a drain coupled to an output voltage Vo. NMOS transistor M21 has a gate receiving a first input voltage V+, a drain coupled to the drain of the PMOS transistor M23, and a source. NMOS transistor M22 has a gate receiving a second input voltage V−, a drain coupled to the drain of the PMOS transistor M24, and a source coupled to the source of the NMOS transistor M21. NMOS transistor M25 has a gate receiving a bias voltage Vb, a drain coupled to the source of the NMOS transistor M21, and a source grounded. In this embodiment, the threshold voltages of the NMOS transistors M21 and M22 are zero, however, positive or negative threshold voltages near zero also apply. The term “near zero threshold voltage” herein may be, for example, a threshold voltage between −0.2V ̃+0.2V. In order to prevent the NMOS transistor M25 from entering the linear region, the saturation voltage of NMOS transistor M25 satisfies the equation:

VdsM25>VgsM25−VtM25 

=>VdM25>VgM25−VtM25 

Furthermore, in order to ensure that the NMOS transistor M21 is activated, the input voltage V+ satisfies the equation:

V+>VdM25+VtM21 

Since the threshold voltage of the NMOS transistor M21 is zero, thus, when the input voltage V+ is larger than VdM25, the NMOS transistor M21 is activated.
In order to ensure that the NMOS transistor M21 is at the saturation region, the saturation voltage of NMOS transistor M21 satisfies the equation:

VdM21>V+

Since the VdM21 is equal to VgM23, we can rewrite the equation as the following:

VgM23>V+

The high voltage source VDD provides the operating voltage to the operational amplifier shown in FIG. 2, and satisfies the equation:

VDD>VgM23+VtM23 

In brief, the operating voltage of the operational amplifier shown in FIG. 2 can be reduced due to the zero threshold voltage of NMOS transistors M21 and M22.
FIG. 3 is a circuit diagram of an embodiment of a PMOS-input-based operational amplifier. PMOS transistor M35 has a source coupled to a high voltage source VDD, a gate receiving a bias voltage Vb, and a drain. PMOS transistor M31 has a source coupled to the drain of the PMOS transistor M35, a gate receiving a first input voltage, and a drain. PMOS transistor M32 has a source coupled to the drain of the PMOS transistor M35, a gate receiving a second input voltage, and a drain coupled to an output voltage Vo. NMOS transistor M33 has a source grounded, a gate, and a drain, wherein the gate and the drain are coupled to the drain of the PMOS transistor M31. NMOS transistor M34 has a source grounded, a gate coupled to the gate of the NMOS transistor M33, and a drain coupled to the drain of the PMOS transistor M32. In this embodiment, the threshold voltages of the PMOS transistors M31 and M32 may be zero, and the operating voltage of the operational amplifier shown in FIG. 3 can be reduced due to the zero threshold voltage of PMOS transistors M31 and M32. The related description and derivation can be referred in the statement of FIG. 2.
FIG. 4 is a block diagram of an embodiment of a temperature-independent system. The operational amplifier 42 has two input terminal receiving input voltages from the positive temperature coefficient compensation unit 43 and the negative temperature coefficient compensation unit 44. The voltage from the positive temperature coefficient compensation unit 43 carries a positive temperature coefficient and the voltage from the negative temperature coefficient compensation unit 44 carries a negative temperature coefficient. The operational amplifier 42 utilizes an external circuit to eliminate the temperature coefficient based on the ratio of positive temperature coefficient to the negative temperature. In this embodiment, the transistors in the operational amplifier 42 for receiving input voltages have zero or near zero threshold voltages. The operational amplifier 42 outputs a temperature-independent voltage to the current/voltage generator 41. The current/voltage generator 41 generates at least one desired voltage/current to the peripheral circuit 45.
FIG. 5 shows a method for obtaining a temperature-independent voltage. L1(T) provides a voltage with a positive temperature coefficient, L2(T) provides a voltage with a negative temperature coefficient, and L3(T) is a combination of L1(T) and L2(T) for providing a temperature-independent voltage. L3(T) can be expressed as: L3(T)=L2(T)+kL1(T). We can adjust the value of k to eliminate the temperature coefficient, where k is based on the ratio of positive temperature coefficient to the negative temperature.
The base-emitter voltage of a bipolar transistor exhibits a negative temperature coefficient (TC). For a bipolar transistor, we can write Ic=Is*exp(VBE/VT), where VT=kT/q. The saturation current Is is proportional to μkTni2, wherein μ is the mobility of minority carriers and ni is the intrinsic minority carrier concentration of silicon. The parameter μ depends on the temperature, and the quantity is represented as μ∝μ0Tm, wherein m≈−3/2. The parameter ni also depends on the temperature, and the quantity is represented as ni2∝T3e−Eg/kt, where Eg≈1.12 eV is the bandgap energy of silicon. Thus, we can rewrite the saturation current Is as the following

Is=bT4+me−Eg/kT  (1)

where b is a proportionality factor. Writing VBE=VTln(IC/Is), we can compute the temperature coefficient of base-emitter voltage. Taking the derivative of VBE with respect to T, we can obtain the equation:




  
    
      
        
          
            ∂
            
              V
              BE
            
          
          
            ∂
            T
          
        
        =
        
          
            
              
                ∂
                
                  V
                  T
                
              
              
                ∂
                T
              
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            
              
                I
                C
              
              Is
            
          
          -
          
            
              
                V
                T
              
              Is
            
            ⁢
            
              
                ∂
                Is
              
              
                ∂
                T
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




From (1), we obtain




  
    
      
        
          
            
              V
              T
            
            Is
          
          ⁢
          
            
              ∂
              Is
            
            
              ∂
              T
            
          
        
        =
        
          
            
              (
              
                4
                +
                m
              
              )
            
            ⁢
            
              
                V
                T
              
              T
            
          
          +
          
            
              Eg
              
                kT
                2
              
            
            ⁢
            
              V
              T
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




With (1) and (3), we can write




  
    
      
        
          
            ∂
            
              V
              BE
            
          
          
            ∂
            T
          
        
        =
        
          
            
              V
              BE
            
            -
            
              
                (
                
                  4
                  +
                  m
                
                )
              
              ⁢
              
                V
                T
              
            
            -
            
              Eg
              /
              q
            
          
          T
        
      
    
    
      
        (
        4
        )
      
    
  




Equation (4) provides the temperature coefficient of the base-emitter voltage at a given temperature. With VBE=750 mV and




  
    T
    =
    
      300
      ⁢
      
        
      
      ⁢
      
        
          
             
            °
          
          ⁢
          K
        
        .
      
    
  
  ,
  
    
      
        ∂
        
          V
          BE
        
      
      
        ∂
        T
      
    
    =
    
      
        -
        1.5
      
      ⁢
      
        
      
      ⁢
      
        mV
        /
        
          
            
               
              °
            
            ⁢
            K
          
          .
        
      
    
  




To explain the positive temperature coefficient, please refer to FIG. 6. FIG. 6 is a circuit diagram of an embodiment of a proportional-to-absolute-temperature (PTAT) voltage generator. In FIG. 6, two identical transistors Q61 and Q62 (IsQ61=IsQ62) are biased at collector current of nIo and Io and their base current are negligible, then




  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            BE
          
        
        =
        
        ⁢
        
          
            V
            
              BE
              ⁢
              
                
              
              ⁢
              1
            
          
          -
          
            V
            
              BE
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
    
  
  
    
      
        =
        
        ⁢
        
          
            
              V
              T
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            
              nIo
              
                I
                
                  S
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
          -
          
            
              V
              T
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            
              Io
              
                I
                
                  S
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
        
      
    
  
  
    
      
        =
        
        ⁢
        
          VT
          ⁢
          
            
          
          ⁢
          ln
          ⁢
          
            
          
          ⁢
          n
        
      
    
  




Thus, the VBE difference exhibits a positive temperature coefficient:




  
    
      
        ∂
        Δ
      
      ⁢
      
        
      
      ⁢
      
        V
        BE
      
    
    
      ∂
      T
    
  
  =
  
    
      k
      q
    
    ⁢
    ln
    ⁢
    
      
    
    ⁢
    n
  




Voltages with negative and positive TCs are described, and if we want to obtain a temperature-independent voltage, we can use one voltage with positive TC and one voltage with negative TC and eliminate the temperature coefficient, as is shown in FIG. 5.
With the negative- and positive-TC voltages obtained above, we can develop a reference voltage having a zero temperature coefficient. We can write Vref=α1VBE+α2(VTln n), where VT ln n is the difference between the base-emitter voltages of bipolar transistors Q71 and Q72. FIG. 7 is a circuit diagram of an embodiment of a bandgap reference circuit. Amplifier 71 receives voltages Vo1 and Vo2, and the MOS transistors in amplifier 71 for receiving voltages Vo1 and Vo2 may have zero or near zero threshold voltage. Preferably, the amplifier 71 may be implemented as the ones shown in FIG. 2 and FIG. 3. In order to obtain approximate voltage at nodes N1 and N2, resistors R71 and R72 have the same resistance. In FIG. 7, the output voltage Vout can be expressed as:




  
    
      
        
          V
          out
        
        =
        
          
            V
            
              BEQ
              ⁢
              
                
              
              ⁢
              72
            
          
          +
          
            
              
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                n
              
              
                R
                ⁢
                
                  
                
                ⁢
                73
              
            
            ⁢
            
              (
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  73
                
                +
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  72
                
              
              )
            
          
        
      
    
  
  
    
      
        =
        
          
            V
            
              BEQ
              ⁢
              
                
              
              ⁢
              72
            
          
          +
          
            
              (
              
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                n
              
              )
            
            ⁢
            
              (
              
                1
                +
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    72
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    73
                  
                
              
              )
            
          
        
      
    
  




At room temperature



  
    
      
        
          ∂
          
            V
            BE
          
        
        
          ∂
          T
        
      
      =
      
        
          -
          1.5
        
        ⁢
        
          
        
        ⁢
        
          mV
          /
          °
        
        ⁢
        
          
        
        ⁢
        K
      
    
    ,
    
      

    
    ⁢
    and
  




  
    
      
        
          ∂
          
            V
            T
          
        
        
          ∂
          T
        
      
      =
      
        0.087
        ⁢
        
          
        
        ⁢
        
          mV
          /
          °
        
        ⁢
        
          
        
        ⁢
        K
      
    
    ,
  



in order to eliminate the temperature coefficient effect for the voltage, the value of





  ln
  ⁢
  
    
  
  ⁢
  
    n
    (
    
      1
      +
      
        
          R
          ⁢
          
            
          
          ⁢
          72
        
        
          R
          ⁢
          
            
          
          ⁢
          73
        
      
    
    )
  




is approximate to 17.2, the ratio of





  
    
      ∂
      
        V
        BE
      
    
    
      ∂
      T
    
  
  ⁢
  
    
  
  ⁢
  to
  ⁢
  
    
  
  ⁢
  
    
      
        ∂
        
          V
          T
        
      
      
        ∂
        T
      
    
    .
  




FIG. 8 shows an embodiment of a bandgap reference circuit. As shown, a bandgap reference circuit 100A comprises a current generation circuit 10A and a current-to-voltage generator 20. The current generation circuit 10A generates two identical output currents I4a and I4b, and the current I4b is obtained by combining currents I1, I2 and I3 since the currents I4a and I4b are identical. The current-to-voltage generator 20 generates an output voltage Vref according to the current I4b generated by the current generation circuit 10A.
The current generation circuit 10A comprises a current mirror CM, an operational amplifier OP, resistors R1, R2a, R2b and R3, and two bipolar transistors Q1 and Q2, in which the current mirror CM comprises two PMOS transistors MP1 and MP2 and the resistors R2a and R2b have the same resistance. In this embodiment, the transistors in the operational amplifier OP for receiving input voltages may have zero or near zero threshold voltage. For example, the transistors MP1 and MP2 have the same size, and the emitter area of the transistor Q1 can be N times that of the transistor Q2, in which N>1. The current-to-voltage generator 20 can be a resistor, a resistive element, a passive element or combinations thereof. In this case, the current-to-voltage generator 20 comprises a resistor R4.
The transistor MP1 comprises a first terminal coupled to a power voltage Vcc, a second terminal coupled to a node N1, and a control terminal coupled to the transistor MP2. The transistor MP2 comprises a first terminal coupled to the power voltage Vcc, a control terminal coupled to the control terminal of the transistor MP1 and a second terminal coupled to the resistor R4. The resistor R3 is coupled between the node N1 and a ground voltage GND, the resistor R2a is coupled between the nodes N1 and N2, the resistor R2b is coupled between the nodes N1 and N3, and the resistor R1 is coupled between the node N2 and the transistor Q1.
The operational amplifier comprises a first terminal coupled to the node N2 and a second terminal coupled to the node N3, and an output terminal coupled to the control terminals of the transistors MP1 and MP2 in the current mirror CM. The operational amplifier OP outputs a control signal to control the current mirror CM according to the voltages at the nodes N2 and N3.
The transistor Q1 comprises an emitter coupled to the resistor R1 and a collector coupled to the ground voltage GND and a base coupled to the transistor Q2. The transistor Q2 comprises an emitter coupled to the node N3 and a collector coupled to the ground voltage GND and a base coupled to the base of the transistor Q1. In this case, the bases of the transistor Q1 and Q2 are coupled to the ground voltage GND. Namely, the transistors Q1 and Q2 are diode-connected transistors.
If the base current is neglected, the emitter-base voltage VEB of a forward active operation diode can be expressed as:




  
    V
    EB
  
  =
  
    
      kT
      q
    
    ⁢
    
      ln
      ⁡
      
        (
        
          Ic
          Is
        
        )
      
    
  




Wherein k is the Boltzmannis constant (1.38×10−23 J/K), q is the electronic charge (1.6×10−29 C), T is temperature, IC is the collector current, and IS is the saturation current.
When the input voltages V1 and V2 of the operational amplifier OP are matched and the size of the transistor Q1 is N times that of the transistor Q2, the emitter-base voltage difference between the transistors Q1 and Q2, ΔVEB, becomes:




  
    Δ
    ⁢
    
      
    
    ⁢
    
      V
      EB
    
  
  =
  
    
      
        V
        
          EB
          ⁢
          
            
          
          ⁢
          2
        
      
      -
      
        V
        
          EB
          ⁢
          
            
          
          ⁢
          1
        
      
    
    =
    
      
        kT
        q
      
      ⁢
      ln
      ⁢
      
        
      
      ⁢
      N
    
  




Wherein VEB1 is the emitter-base voltage of the transistor Q1, and VEB2 is the emitter-base of the transistor Q2.
Because the input voltages V1 and V2 are matched by the operational amplifier OP, the voltages V1 and V2 can be expressed as:



  
    
      V
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        V
        ⁢
        
          
        
        ⁢
        2
      
      =
      
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            V
            
              EB
              ⁢
              
                
              
              ⁢
              1
            
          
          +
          
            I
            ⁢
            
              
            
            ⁢
            1
            ×
            R
            ⁢
            
              
            
            ⁢
            1
          
        
      
    
  




  
    
      I
      ⁢
      
        
      
      ⁢
      1
      ×
      R
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
        -
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            1
          
        
      
      =
      
        
          kT
          q
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
    
  



Thus, the current I1 through the resistors R2a and R1 can be expressed as:




  
    
      I
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        
          V
          T
        
        
          R
          ⁢
          
            
          
          ⁢
          1
        
      
      ⁢
      ln
      ⁢
      
        
      
      ⁢
      N
    
  
  ,




wherein thermal voltage is





  
    V
    T
  
  =
  
    
      kT
      q
    
    .
  




Because the resistors R2a and R2b are identical and the input voltages V1 and V2 are matched by the operational amplifier OP, the current I2 can be the same as the current I1.
Accordingly,




  
    
      I
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        I
        ⁢
        
          
        
        ⁢
        2
      
      =
      
        
          
            V
            T
          
          
            R
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
    
  
  ,




since the thermal voltage VT has a positive temperature coefficient of 0.085 mV/° C., and the currents I1 and I2 have positive temperature coefficient.

Thus, voltage V3 at the node N1 can be expressed as:

V3=I3×R3=I1×(R1+R2a)+VEB1=I2×R2b+VEB2 

Hence, the current I3 can be expressed as:




  
    I
    ⁢
    
      
    
    ⁢
    3
  
  =
  
    
      1
      
        R
        ⁢
        
          
        
        ⁢
        3
      
    
    [
    
      
        V
        
          EB
          ⁢
          
            
          
          ⁢
          2
        
      
      +
      
        (
        
          
            
              
                V
                T
              
              ⁢
              ln
              ⁢
              
                
              
              ⁢
              N
            
            
              R
              ⁢
              
                
              
              ⁢
              1
            
          
          ×
          R
          ⁢
          
            
          
          ⁢
          2
          ⁢
          b
        
        )
      
    
    ]
  




Because the emitter-base voltage VEB of the transistors has a negative temperature coefficient of −2 mV/° C., the current I3 has a negative temperature coefficient.
As the transistors MP1 and MP2 in the current mirror CM are identical, the current I4b is the same as the current I4a, and can be expressed as:




  
    I
    ⁢
    
      
    
    ⁢
    4
    ⁢
    a
  
  =
  
    
      I
      ⁢
      
        
      
      ⁢
      4
      ⁢
      b
    
    =
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        +
        
          I
          ⁢
          
            
          
          ⁢
          2
        
        +
        
          I
          ⁢
          
            
          
          ⁢
          3
        
      
      =
      
        
          
            2
            ⁢
            I
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            I
            ⁢
            
              
            
            ⁢
            3
          
        
        =
        
          
            
              (
              
                
                  2
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    b
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    1
                    ×
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              )
            
            ×
            
              V
              T
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            N
          
          +
          
            
              V
              
                EB
                ⁢
                
                  
                
                ⁢
                2
              
            
            
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
  




Hence, if a proper ratio of resistances of the resistors R1, R2a, R2b and R3 is selected, the current I4a will have a near zero temperature coefficient and low sensitivity to temperature. Namely, each current mirror output (currents I4a and I4b) of the current mirror CM will have a near zero temperature coefficient and low sensitivity to temperature.
Accordingly, the output voltage of the bandgap reference circuit 100A can be expressed as:




  
    V
    ref
  
  =
  
    
      I
      ⁢
      
        
      
      ⁢
      4
      ⁢
      b
      ×
      R
      ⁢
      
        
      
      ⁢
      4
    
    =
    
      
        
          (
          
            
              
                2
                ⁢
                R
                ⁢
                
                  
                
                ⁢
                4
              
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              
                R
                ⁢
                
                  
                
                ⁢
                2
                ⁢
                b
                ×
                R
                ⁢
                
                  
                
                ⁢
                4
              
              
                R
                ⁢
                
                  
                
                ⁢
                1
                ×
                R
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ×
        
          V
          T
        
        ⁢
        
          
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
      +
      
        
          
            R
            ⁢
            
              
            
            ⁢
            4
          
          
            R
            ⁢
            
              
            
            ⁢
            3
          
        
        ×
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
      
    
  




Note that the resistors R2a and R2b prevent direct connection of the input terminal of the operational amplifier OP, ensuring normal operation of amplifier OP. Without the resistor R3, the output voltage Vref of the bandgap reference circuit is limited to 1.25V, which cannot be operated in low voltage environments, in order to obtain a near zero temperature coefficient. Thus, the invention utilizes the resistor R3 to induce the current I3 with negative temperature coefficient to overcome such limitation, and if a proper ratio of resistances of the resistors R1, R2a, R2b, R3 and R4 is selected, the output voltage Vref will have low sensitivity to temperature and can be operated in low voltage environments.
FIG. 9 shows another embodiment of a bandgap reference circuit. As shown, the bandgap reference circuit 100B is similar to the circuit 100A shown in FIG. 1 except for the resistor R3. The resistor R3 is coupled between the node N1 and the resistor R4 rather than the ground voltage GND. In this embodiment, the transistors in the operational amplifier OP for receiving input voltages may have zero or near zero threshold voltage.
Similarly, currents I1 and I2 are equal and can be expressed as:




  
    I
    ⁢
    
      
    
    ⁢
    1
  
  =
  
    
      I
      ⁢
      
        
      
      ⁢
      2
    
    =
    
      
        
          V
          T
        
        
          R
          ⁢
          
            
          
          ⁢
          1
        
      
      ⁢
      ln
      ⁢
      
        
      
      ⁢
      N
    
  




The voltage V3 at the node N1 and the output voltage Vref can be expressed as:



  
    
      V
      ⁢
      
        
      
      ⁢
      3
    
    =
    
      
        
          
            
              V
              T
            
            ⁢
            
              
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            N
          
          
            R
            ⁢
            
              
            
            ⁢
            1
          
        
        ×
        R
        ⁢
        
          
        
        ⁢
        2
        ⁢
        b
      
      +
      
        V
        
          EB
          ⁢
          
            
          
          ⁢
          2
        
      
    
  




  
    Vref
    =
    
      
        R
        ⁢
        
          
        
        ⁢
        4
        ×
        
          [
          
            
              (
              
                
                  
                    V
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  -
                  Vref
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              )
            
            +
            
              2
              ⁢
              I
              ⁢
              
                
              
              ⁢
              2
            
            +
            
              (
              
                
                  
                    V
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  -
                  Vref
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              )
            
          
          ]
        
      
      =
      
        
          R
          ⁢
          
            
          
          ⁢
          4
          ×
          
            (
            
              
                
                  2
                  ⁢
                  V
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              -
              
                
                  2
                  ⁢
                  Vref
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              +
              
                2
                ⁢
                I
                ⁢
                
                  
                
                ⁢
                2
              
            
            )
          
        
        =
        
          
            1
            
              (
              
                1
                +
                
                  
                    2
                    ⁢
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              )
            
          
          ⁡
          
            [
            
              
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                ⁢
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
              +
              
                
                  (
                  
                    
                      
                        2
                        ⁢
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        2
                        ×
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                      
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        1
                        ×
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      
                        2
                        ⁢
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                      
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                  
                  )
                
                ⁢
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                N
              
            
            ]
          
        
      
    
  



Because the emitter-base voltage VEB of transistors has a negative temperature coefficient of −2 mV/° C., the current I3 has a negative temperature coefficient. Hence, if a proper ratio of resistances of the resistors R1, R2a, R2b, R3 and R4 is selected, the output voltage Vref will have low sensitivity to temperature and can be operated in low voltage environments. Similarly, if a proper ratio of resistances of the resistors R1, R2a, R2b, R3 and R4 is selected, the output voltage Vref will have low sensitivity to temperature, the currents I4a and I4b can also have low sensitivity to temperature, and the description thereof is omitted for simplification.
The bandgap reference circuits 100A and 100B of the invention can act as a necessary functional block for the operation of mixed-mode and analog integrated circuits (ICs), such as data converters, phase lock-loop (PLL) circuits, oscillators, power management circuits, dynamic random access memory (DRAM), flash memory, and much more. For example, the bandgap reference circuit 100A may provide the current I4b or the output voltage Vref to a core circuit and the core circuit executes functions thereof accordingly.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

## Claims

1. An operational amplifier of a bandgap reference circuit, comprising:
a first NMOS transistor having near zero threshold voltage, a first gate for receiving a first input signal of a pair of differential signals, a first source, and a first drain;
a second NMOS transistor having near zero threshold voltage, a second gate for receiving a second input signal of the pair of differential signals, a second source, and a second drain;
a third PMOS transistor having a third gate, a third source, and a third drain, wherein the third source is directly coupled to a high voltage source, and the third gate and the third drain are coupled to the first drain;
a fourth PMOS transistor having a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is directly coupled to the high voltage source, and the fourth gate is coupled to the first drain and the fourth drain is coupled to the second drain; and
a fifth NMOS transistor having a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate receives a bias voltage, the fifth drain is coupled to the first source and the second source, and the fifth source is directly grounded.

2. The amplifier as claimed in claim 1, wherein the first NMOS transistor comprises:
a p-type substrate;
a gate structure formed on the p-type substrate;
a first n-type region directly doped in the p-type substrate; and
a second n-type region directly doped in the p-type substrate, wherein the first n-type region and the second n-type region are symmetrical with respect to the gate structure.

3. The amplifier as claimed in claim 1, wherein the third PMOS transistor, the fourth PMOS transistor, and the fifth NMOS transistor also have near zero threshold voltage.

4. An operational amplifier of a bandgap reference circuit, comprising:
a first PMOS transistor having near zero threshold voltage, a first gate for receiving a first input signal, a first source, and a first drain;
a second PMOS transistor having near zero threshold voltage, a second gate for receiving a second input signal, a second source, and a second drain;
a third NMOS transistor having a third gate, a third source, and a third drain, wherein the third source is directly grounded, the third gate and the third drain are coupled to the first drain;
a fourth NMOS transistor having a fourth gate, a fourth source, and a fourth drain, wherein the fourth source is directly grounded, and the fourth gate is coupled to the first drain and the fourth drain is coupled to the second drain; and
a fifth PMOS transistor having a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate receives a bias voltage, the fifth drain is coupled to the first source and the second source, and the fifth source is directly coupled to a high voltage source.

5. The amplifier as claimed in claim 4, wherein the first PMOS transistor comprises:
a n-type substrate;
a gate structure formed on the n-type substrate;
a first p-type region directly doped in the n-type substrate; and
a second p-type region directly doped in the n-type substrate, wherein the first p-type region and the second p-type region are symmetrical with respect to the gate structure.

6. The amplifier as claimed in claim 4, wherein the third NMOS transistor, the fourth NMOS transistor, and the fifth PMOS transistor also have near zero threshold voltage.