# Patent

## Title
Integrated LDO with variable resistive load

## Abstract

To provide adequate compensation for a wide range of output loads, a low dropout (LDO) regulator has an amplifier, a pass transistor, a voltage divider, a compensation network, and a control circuit. The amplifier outputs a comparison result according to a reference signal and a feedback signal. The pass transistor generates an output current based on the comparison result of the amplifier. The voltage divider generates the feedback signal according to the output current. The compensation network couples the output of the pass transistor to a low-impedance node of the amplifier, and has a compensation capacitor and a variable resistor coupled to the compensation capacitor. The control circuit is coupled to the input of the pass transistor and to the variable resistor for controlling resistance of the variable resistor according to the output current of the pass transistor.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 61/096,865, filed on Sep. 15, 2008 and entitled “Adaptive Compensation for Integrated LDO with Variable Load,” the contents of which are incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to low dropout regulators, and particularly, to an integrated LDO with a variable resistive load compensation scheme.
2. Description of the Prior Art
Voltage regulator circuits are circuits placed between a power supply and a load circuit for providing a constant voltage to the load circuit regardless of fluctuations in power supply voltage. For example, a battery used to power a mobile phone may have a decreasing output voltage as the battery loses charge. In this case, the voltage regulator circuit can supply the constant voltage to the load circuit as long as the output voltage of the battery is greater than the constant voltage supplied to the load circuit of the mobile phone. A dropout voltage is then defined as a minimum voltage difference that must be present from an input of the voltage regulator to an output of the voltage regulator for the voltage regulator to supply the constant voltage. For example, a voltage regulator that supplies a constant voltage of 1.8V may be able to supply 1.8V as long as a power supply voltage is above 2.0V, in which case the dropout voltage is 200 mV (2.0V−1.8V). Low dropout regulators (LDOs) are voltage regulators that have a low dropout voltage. In modern applications, LDOs with dropout voltages lower than 50 mV are available.
Please refer to FIG. 1, which is a diagram of an LDO regulator 10 with a first compensation scheme. The LDO regulator 10 comprises a first stage amplifier 101, an inverting amplifier 102, a pass transistor MP, a mirror transistor MS, a current-to-voltage (I-V) convertor 103, a compensation capacitor CC, and a compensation resistor RC. The LDO regulator 10 outputs an output voltage OUT that is nominally constant for all input voltages VDD. A load ZL draws a load current IL from VDD through the pass transistor MP. A first resistor RA and a second resistor RB generates a voltage proportional to OUT that is compared with the reference voltage VREF to control OUT via the amplifiers 101, 102 and the pass transistor MP. The compensation capacitor CC and the compensation resistor RC provide frequency compensation that varies with the current outputted by the pass transistor MP due to voltage applied to the compensation resistor RC through the mirror transistor MS and the I-V convertor 103.
Please refer to FIG. 2, which is a diagram of an LDO regulator 20 with a second compensation scheme. The LDO regulator 20 comprises a first stage amplifier 201, a buffer 202, a pass transistor MP, a first resistor RA, a second resistor RB, a compensation resistor RC, and a compensation capacitor CC. The LDO regulator 20 outputs an output voltage OUT that is nominally constant for all input voltages VREF. A load ZL draws a current from the pass transistor MP. In operation, the LDO regulator 20 is similar to the LDO regulator 10. In addition, the first compensation scheme and the second compensation scheme vary slightly, but are similar in principle.
The LDO regulators 10, 20 described above have a number of drawbacks. First, the PSRR of both of the LDO regulators 10, 20 is not sufficiently high. This can be understood as follows. For the LDO regulator 10 in FIG. 1, a capacitance of value CL1=(1+A)CC loads the high impedance output terminal X of the first stage to AC ground. For the LDO regulator 20 in FIG. 2, a capacitance of value CL1=CC loads the high impedance output terminal X of the first stage to AC ground. It is to be noted that for adequate compensation, CC needs to be large for FIG. 2. Because of this, the PSRR frequency responses of the LDO regulators 10, 20 will each have a zero at 1/2πCL1ro1, where ro1 is the output resistance of the first stage.
Secondly, the compensations of the LDO regulators 10, 20 are not applied from the output node OUT. This means that the compensations do not move the output pole to a higher frequency.
Thirdly, the variable compensation resistors RC of the LDO regulators 10, 20 are MOSFETs. Therefore, in each case, tracking compensation provided by the variable compensation resistor RC is subject to substantial process variation and temperature variation of the MOSFET.
SUMMARY OF THE INVENTION
According to one embodiment, a low dropout (LDO) regulator comprises an amplifier, a pass transistor, a voltage divider, a compensation network, and a control circuit. The amplifier has a first terminal for receiving a reference signal, a second terminal for receiving a feedback signal, and an output terminal for outputting a comparison result according to the reference signal and the feedback signal. The pass transistor has an input terminal coupled to the output of the amplifier and an output terminal for generating an output current based on the comparison result of the amplifier. The voltage divider is coupled to the pass transistor for generating the feedback signal according to the output current. The compensation network couples the output of the pass transistor to a low-impedance node of the amplifier, and comprises a compensation capacitor and a variable resistor coupled to the compensation capacitor. The control circuit is coupled to the input of the pass transistor and to the variable resistor for controlling resistance of the variable resistor according to the output current of the pass transistor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a low dropout (LDO) regulator with a first compensation scheme according to the prior art.
FIG. 2 is a diagram of an LDO regulator with a second compensation scheme according to the prior art.
FIG. 3 is a functional diagram of an LDO regulator according to an embodiment of the present invention.
FIG. 4 is a circuit diagram of the LDO regulator of FIG. 3.
FIG. 5 is a frequency response diagram for the LDO regulator of FIG. 4 under very light loading.
FIG. 6 is a frequency response diagram for the LDO regulator of FIG. 4 under very heavy loading.
FIG. 7 is a frequency response diagram for the LDO regulator of FIG. 4 under moderate loading.
FIG. 8 is a representative plot of phase margin versus load current for the LDO regulator of FIG. 4 for various compensation resistor values.



DETAILED DESCRIPTION
Please refer to FIG. 3, which is a diagram of a low dropout (LDO) regulator 30 according to an embodiment of the present invention. The LDO regulator 30 comprises a first stage amplifier 301, a buffer 302, a pass transistor MP, a first resistor RA and a second resistor RB. The amplifier has a first terminal (−) for receiving a reference signal VREF, a second terminal (+) for receiving a feedback signal, and an output terminal (×) for outputting a comparison result according to the reference signal VREF and the feedback signal. The pass transistor has an input terminal coupled to the output of the amplifier, and an output terminal for generating an output current based on the comparison result of the amplifier. The first resistor RA and the second resistor RB form a voltage divider, which is coupled to the pass transistor for generating the feedback signal according to the output voltage OUT. The LDO regulator 30 also comprises a compensation network, which couples the output of the pass transistor MP to a low-impedance node (y) of the amplifier, and comprises a compensation capacitor CC and a variable resistor RC coupled to the compensation capacitor CC. A control circuit 303 is coupled to the input of the pass transistor MP and to the variable resistor RC for controlling resistance of the variable resistor RC according to the output current of the pass transistor MP.
In FIG. 3, the compensation is applied not to the high impedance output terminal (×), but to a low impedance node (y) of the first stage amplifier 301. Therefore, in this case, CL1=CP1, where CP1 (typically <100 fF) is the parasitic capacitance loading the node X to AC ground, which is much smaller than CL1=(1+A)Cc or Cc (typically >10 pF) for FIGS. 1 and 2, respectively. Therefore, the zero of the PSRR frequency response for FIG. 3 will occur at a much higher frequency compared to those for FIGS. 1 and 2. This means LDO regulator 30 will have better PSRR compared to the LDO regulators 10, 20 at high frequencies.
Please refer to FIG. 4, which is a detailed schematic of the LDO regulator 30 of FIG. 3. The variable resistor RC comprises a plurality of resistor sections RC1−RCn forming a resistor series having one end coupled to the compensation capacitor CC and another end coupled to the low-impedance node (y) of the amplifier. Adjacent resistor sections of the plurality of resistor sections, e.g. RC1 and RC2, form corresponding internal nodes. The variable resistor RC further comprises a plurality of switches SW1−SWn. Each switch, e.g. SW2, has an input coupled to the compensation capacitor CC and an output coupled to a corresponding internal node of the internal nodes.
The control circuit 303 comprises a plurality of transistors (current mirrors) MS1, MS2, . . . , MSn−1, MSn, which are transistors (typically identical in size) each of which carry a small fraction (α1−αn) of the current in the pass transistor MP, which is essentially the load current IL, since the current through RA, RB is negligible. The control circuit 303 further comprises a plurality of current references IR1−IRn (IR1<IR2< . . . <IRn-1<IRn), which are temperature independent current references. The MOS transistors MSi and current sources IRi (where i=1, 2, . . . , n−1, n) form a plurality of current comparators. Outputs di of these comparators may go high whenever the current in MSi exceeds IRi. The switches SW1, SW2, . . . , SWn-1, SWn may then modify the overall resistance of the compensation resistor RC by shorting corresponding resistor sections RC1−RCn of the variable resistor RC. SWi may be closed when di is high and open otherwise. It is easy to verify that RC=RC1+RC2+ . . . +RCn-1+RCn (maximum value) when IL=0. As the load current increases, RC reduces, and finally RC=0 when IL is maximum.
Looking into stability analysis of the LDO regulator 30 in FIG. 4, the basic idea of high-PSRR compensation (Ahuja compensation) is well known in the art. However, in the LDO regulator 30, the high-PSRR compensation is modified by inclusion of the compensation resistor RC in series with the compensation capacitor CC. It can be shown with small-signal analysis that the PSRR is not appreciably affected by the presence of RC. However, the resistor RC needs to be varied to track changes in the poles with changes in the load. The reason for the presence of RC and the need for its variability are explained below.
Using small-signal analysis, it can be shown that the loop-gain of the LDO has a low-frequency pole ωp1, a high-frequency pole ωp2, and a zero ωz. When the compensation is proper, then a unity gain frequency ω0 may be defined. The first three parameters are given by:




  
    
      
        
          ω
          
            p
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          1
          
            
              
                r
                2
              
              ⁢
              
                C
                2
              
            
            +
            
              
                R
                C
              
              ⁢
              
                C
                C
              
            
            +
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              
                r
                1
              
              ⁢
              
                r
                2
              
              ⁢
              
                C
                C
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          ω
          
            p
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            1
            
              
                r
                1
              
              ⁢
              
                
                  C
                  1
                
                ⁡
                
                  [
                  
                    1
                    +
                    
                      
                        (
                        
                          
                            1
                            
                              
                                r
                                1
                              
                              ⁢
                              
                                C
                                1
                              
                            
                          
                          +
                          
                            1
                            
                              
                                r
                                2
                              
                              ⁢
                              
                                C
                                2
                              
                            
                          
                        
                        )
                      
                      ⁢
                      
                        R
                        C
                      
                      ⁢
                      
                        C
                        C
                      
                    
                  
                  ]
                
              
            
          
          +
          
            
              
                R
                C
              
              ⁢
              
                C
                C
              
            
            
              
                
                  r
                  1
                
                ⁢
                
                  C
                  1
                
                ⁢
                
                  r
                  2
                
                ⁢
                
                  C
                  2
                
              
              +
              
                
                  (
                  
                    
                      
                        r
                        1
                      
                      ⁢
                      
                        C
                        1
                      
                    
                    +
                    
                      
                        r
                        2
                      
                      ⁢
                      
                        C
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  R
                  C
                
                ⁢
                
                  C
                  C
                
              
            
          
          +
          
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              
                C
                C
              
            
            
              
                C
                1
              
              ⁢
              
                
                  C
                  2
                
                ⁡
                
                  [
                  
                    1
                    +
                    
                      
                        (
                        
                          
                            1
                            
                              
                                r
                                1
                              
                              ⁢
                              
                                C
                                1
                              
                            
                          
                          +
                          
                            1
                            
                              
                                r
                                2
                              
                              ⁢
                              
                                C
                                2
                              
                            
                          
                        
                        )
                      
                      ⁢
                      
                        R
                        C
                      
                      ⁢
                      
                        C
                        C
                      
                    
                  
                  ]
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        
          ω
          z
        
        =
        
          1
          
            
              R
              C
            
            ⁢
            
              C
              C
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




where gm1 is transconductance of the first stage, gm2 is transconductance of the pass transistor MP, r1 is output resistance of the first stage, r2 is approximately load resistance RL, C1 is parasitic capacitance loading the first stage output, C2 is approximately load capacitance CL, CC is compensation capacitance, and RC is compensation resistance. It can be seen from the discussion above that there are two significant poles, and it is known that good stability can be achieved if the poles are kept far apart. However, the zero provided by RC and CC can also help improve compensation, which is described later. Generally, good stability is characterized by phase margins Φm from 45° to 90°, the higher the better.

To understand how compensation works, assume that RC=0. Then, (1), (2) and (3) reduce to:




  
    
      
        
          ω
          
            p
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          1
          
            
              
                r
                2
              
              ⁢
              
                C
                2
              
            
            +
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              
                r
                1
              
              ⁢
              
                r
                2
              
              ⁢
              
                C
                C
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  
  
    
      
        
          ω
          
            p
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            1
            
              
                r
                1
              
              ⁢
              
                C
                1
              
            
          
          +
          
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              
                C
                C
              
            
            
              
                C
                1
              
              ⁢
              
                C
                2
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  
  
    
      
        
          ω
          z
        
        =
        ∞
      
    
    
      
        (
        6
        )
      
    
  




For light loading, i.e. when r2=RL is very large, ωp1 is very small. On the other hand, ωp2 is large, since the term gm2CC/C1C2 is large. In other words, the separation between ωp1 and ωp2 is large and, therefore, adequate Φm is achieved for good stability. For moderately heavy loading, when r2=RL is moderately small, IL is moderately high, and gm2 increases, but less than proportionately with IL, because of the square-root relationship. Then, as can be seen from (4) and (5), ωp1 increases more than ωp2 does, and the separation of the poles decreases, reducing Φm and worsening the stability. From (6), the zero ωz is not present, which helps to improve the stability. However, at the heaviest loading, IL is maximum and gm2 is substantially large. Then again, from (4) and (5), it can be seen that ωp1 becomes smaller and ωp2 becomes larger, increasing the separation and improving the stability again. From the above discussion, it can be seen that if RC were not present, then stability would be good at very light and very heavy loads, but poor at intermediate loads.
Assuming RC is present, (1), (2), and (3) are valid. As can be seen from (1), if RC is large, ωp1 cannot become very large, and stability is therefore improved for low to moderate loads. However, from (2), it can be seen that a large RC also does not allow ωp2 to increase when IL and, consequently, gm2 is increased. On the contrary, ωp2 may actually be reduced with increasing IL as per the first and third terms in (2). Therefore, at high to moderate loads, the pole separation is low, and consequently the stability becomes poor if RC is high. However, from (3), it can be seen that RC and CC provide the zero ωz that can be used to improve the stability for moderate loads, when the pole separation is not too large, by placing it near ωp2, as shown in FIG. 7. In conclusion, some finite value of RC, if not too large, is beneficial for stability at moderate loading.
In summary, it can be seen that a high valued RC provides good stability at light and low-moderate loads, a low valued RC provides good stability at high-moderate loads, and a zero valued RC provides good stability at very heavy loads. FIGS. 5 and 6 show corresponding plots for very light and very heavy loading conditions, respectively. FIG. 8 shows a typical plot of how the phase margin Φm behaves with IL for four values of RC. Clearly, the phase margin Φm is not adequate for all IL for any one value of RC. It can also be seen that IT1, IT2, and IT3 are appropriate load current values for switching from one value of RC to another so that a minimum phase margin Φm of 50° can be maintained for any IL.
The compensations of the LDO regulators 10, 20 are not applied from the output node OUT. This means that the compensations do not move the output pole to a higher frequency. However, in the LDO regulator 30, the compensation is actually applied from the output OUT and, therefore, is capable of providing better frequency compensation. Further, the variable compensation resistor RC in FIGS. 1-2 are MOSFETs. Therefore, in each case, the tracking compensation provided by this resistor is subject to substantial process and temperature varations of the MOSFET. However, in FIG. 3, RC is a poly resistor, and is digitally switched in response to a predetermined value of the load current IL using the control circuit 303 that contains current comparators with accurate current references and, therefore, provides a more stable solution.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

## Claims

1. A low dropout (LDO) regulator comprising:
an amplifier having a first terminal for receiving a reference signal, a second terminal for receiving a feedback signal, and an output terminal for outputting a comparison result according to the reference signal and the feedback signal;
a pass transistor having an input terminal coupled to the output of the amplifier and an output terminal for generating an output current based on the comparison result of the amplifier;
a voltage divider coupled to the pass transistor for generating the feedback signal according to the output current;
a compensation network coupling the output of the pass transistor to a low-impedance node of the amplifier, the compensation network comprising a compensation capacitor and a variable resistor coupled to the compensation capacitor; and
a control circuit coupled to the input of the pass transistor and the variable resistor for controlling resistance of the variable resistor according to the output current of the pass transistor.

2. The LDO regulator of claim 1, wherein the variable resistor comprises:
a plurality of resistor sections forming a resistor series having one end coupled to the compensation capacitor and another end coupled to the low-impedance node of the amplifier, adjacent resistor sections of the plurality of resistor sections forming corresponding internal nodes; and
a plurality of switches, each switch having an input coupled to the compensation capacitor and an output coupled to a corresponding internal node of the internal nodes.

3. The LDO regulator of claim 2, wherein the control circuit comprises a plurality of current comparators, each current comparator comprising:
a current mirror coupled to the input of the pass transistor for mirroring the output current; and
a current reference coupled to the current mirror and a corresponding switch of the plurality of switches for shorting a corresponding resistor section of the plurality of resistor sections according to a current comparison result of the current reference and the current mirror.

4. The LDO regulator of claim 2, wherein the plurality of resistor sections is a plurality of poly resistors.

5. The LDO regulator of claim 1, further comprising:
a buffer having an input terminal coupled to the output terminal of the amplifier and an output terminal coupled to the input terminal of the pass transistor for outputting the comparison result of the amplifier to the pass transistor.

6. The LDO regulator of claim 1, wherein the voltage divider comprises:
a first resistor; and
a second resistor coupled to the first resistor.

7. The LDO regulator of claim 3, wherein the plurality of resistor sections is a plurality of poly resistors.

8. The LDO regulator of claim 3, further comprising:
a buffer having an input terminal coupled to the output terminal of the amplifier and an output terminal coupled to the input terminal of the pass transistor for outputting the comparison result of the amplifier to the pass transistor.

9. The LDO regulator of claim 3, wherein the voltage divider comprises:
a first resistor; and
a second resistor coupled to the first resistor.