# Patent

## Title
TCP/IP offload device

## Abstract

A TCP/IP offload network interface device (NID) is integrated with a processing device that executes a stack. The TCP/IP offload NID can either be a full TCP/IP offload device or a partial TCP/IP offload device. Common types of packets are processed by the NID in a fast-path such that the stack is offloaded of TCP and IP protocol processing tasks. A hash is made from the packet header and is pushed onto a queue. The hash is later popped off the queue and is used to identify an associated TCB number from a hash table. A mechanism caches hash buckets in SRAM and stores other hash buckets in DRAM. An “IN SRAM CAM” is used to determine whether the TCB associated with the identified TCB number is cached in SRAM or whether it must be moved from DRAM into the SRAM cache. A lock table and a “lock table CAM” mechanism is disclosed that facilitates multiple processors working on the protocol processing of a single packet.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit under 35 U.S.C. § 119(e) of Provisional Application Ser. No. 60/374,788, filed Apr. 22, 2002. The complete disclosure of Provisional Application Ser. No. 60/374,788 is incorporated herein by reference.


CROSS-REFERENCE TO COMPACT DISC APPENDIX
Compact Disc Appendix, which is a part of the present disclosure, includes a recordable Compact Disc (CD-R) containing information that is part of the disclosure of the present patent document. A portion of the disclosure of this patent document contains material that is subject to copyright protection. All the material on the Compact Disc is hereby expressly incorporated by reference into the present application. The copyright owner of that material has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which:
FIG. 1 is a diagram of a system 1 in accordance with one embodiment of the present invention.
FIG. 2 is a simplified diagram of various structures and steps involved in the processing of an incoming packet in accordance with an embodiment of the present invention.
FIG. 3 is a flowchart of a method in accordance with an embodiment of the present invention.
FIGS. 4, 5, 6, 7, 8 and 9 are diagrams that illustrate various system configurations involving a network interface device in accordance with the present invention.
FIG. 10 is a diagram of a controller in accordance with one embodiment of the present invention.
FIG. 11 is a table of datapath bandwidth in accordance with the embodiment of FIG. 10.
FIG. 12 is a table of CPU bandwidth in accordance with the embodiment of FIG. 10.
FIG. 13 is a table of pin assignments in accordance with the embodiment of FIG. 10.
FIG. 14 is a diagram of a processor in accordance with the embodiment of FIG. 10.
FIG. 15 is a table of instruction types in accordance with the processor of FIG. 14.
FIG. 16 is a table of sequencer behavior in accordance with the processor of FIG. 14.
FIG. 17 is a table of ALU operations in accordance with the processor of FIG. 14.
FIG. 18 is a table of ALU operands in accordance with the processor of FIG. 14.
FIG. 19 is a table of selected tests in accordance with the processor of FIG. 14.
FIG. 20 is a table of flag operations in accordance with the processor of FIG. 14.
FIG. 21 is a diagram of data flow in accordance with the embodiment of FIG. 10.
FIG. 22 is a diagram of data movement in accordance with the embodiment of FIG. 10.
FIG. 23 is a diagram of a SRAM control sequencer in accordance with the embodiment of FIG. 10.
FIG. 24 is a diagram of a memory controller in accordance with the embodiment of FIG. 10.
FIG. 25 is a timing diagram illustrating how data is read from SDRAM.
FIG. 26 is a timing diagram illustrating how data is written to SDRAM.
FIG. 27 is a diagram of a PCI master-out sequencer in accordance with the embodiment of FIG. 10.
FIG. 28 is a diagram of a PCI master-in sequencer in accordance with the embodiment of FIG. 10.
FIG. 29 is a diagram of a DRAM to PCI sequencer in accordance with the embodiment of FIG. 10.
FIG. 30 is a diagram of a PCI to DRAM sequencer in accordance with the embodiment of FIG. 10.
FIG. 31 is a diagram of a SRAM to PCI sequencer in accordance with the embodiment of FIG. 10.
FIG. 32 is a diagram of a PCI to SRAM sequencer in accordance with the embodiment of FIG. 10.
FIG. 33 is a diagram of a DRAM to SRAM sequencer in accordance with the embodiment of FIG. 10.
FIG. 34 is a diagram of a SRAM to DRAM sequencer in accordance with the embodiment of FIG. 10.
FIG. 35 is a diagram of a PCI slave input sequencer in accordance with the embodiment of FIG. 10.
FIG. 36 is a diagram of a PCI slave output sequencer in accordance with the embodiment of FIG. 10.
FIG. 37 is a diagram of a frame receive sequencer in accordance with the embodiment of FIG. 10.
FIG. 38 is a table of vlan priorities in accordance with the frame receive sequencer of FIG. 37.
FIG. 39 is a table of a receive buffer format in accordance with the embodiment of FIG. 10.
FIG. 40 is a table of a receive buffer descriptor in accordance with the embodiment of FIG. 10.
FIG. 41 is a table of a receive vector in accordance with the embodiment of FIG. 10.
FIG. 42 is a diagram showing a sequence of events for successful transmission of a packet in accordance with the embodiment of FIG. 10.
FIG. 43 is a diagram of a transmit descriptor in accordance with the embodiment of FIG. 10.
FIG. 44 is a diagram of a merge descriptor in accordance with the embodiment of FIG. 10.
FIG. 45 is a table of a transmit buffer format in accordance with the embodiment of FIG. 10.
FIG. 46 is a table of a transmit vector in accordance with the embodiment of FIG. 10.
FIG. 47 is a diagram of a queue manager in accordance with the embodiment of FIG. 10.
FIG. 48 is a table of dedicated queues in accordance with the queue manager of FIG. 47.
FIG. 49 is a table of queue identifications in accordance with the queue manager of FIG. 47.
FIG. 50 is a table of a PCI to DRAM or PCI to SRAM descriptor format in accordance with the embodiment of FIG. 10.
FIG. 51 is a table of a DRAM to PCI or SRAM to PCI descriptor format in accordance with the embodiment of FIG. 10.
FIG. 52 is a table of a SRAM to DRAM, DRAM to DRAM, or DRAM to SRAM descriptor format in accordance with the embodiment of FIG. 10.
FIG. 53 is a table of an ending status format of a DMA in accordance with the embodiment of FIG. 10.
FIG. 54 is a diagram of PCI logic blocks in accordance with the embodiment of FIG. 10.



DETAILED DESCRIPTION
FIG. 1 is a simplified diagram of a system 1 in accordance with a first embodiment. System 1 is coupled to a packet-switched network 2. Network 2 can, for example, be a local area network (LAN) and/or a collection of networks. Network 2 can, for example, be the Internet. Network 2 can, for example, be an IP-based SAN that runs iSCSI. Network 2 may, for example, be coupled to system 1 via media that communicates electrical signals, via fiber optic cables, and/or via a wireless communication channel. System 1 includes a network interface device (NID) 3 as well as a central processing unit (CPU) 4. CPU 4 executes software stored in storage 5. NID 3 is coupled to CPU 4 and storage 5 via host bus 6, a bridge 7, and local bus 8. Host bus 6 may, for example, be a PCI bus or another computer expansion bus.
In the illustrated particular embodiment, NID 3 includes an application specific integrated circuit (ASIC) 9, an amount of dynamic random access memory (DRAM) 10, and Physical Layer Interface (PHY) circuitry 11. NID 3 includes specialized protocol accelerating hardware for implementing “fast-path” processing whereby certain types of network communications are accelerated in comparison to “slow-path” processing whereby the remaining types of network communications are handled at least in part by a software protocol processing stack. In one embodiment, the certain types of network communications accelerated are TCP/IP communications. The embodiment of NID 3 illustrated in FIG. 1 is therefore sometimes called a TCP/IP Offload Engine (TOE).
For additional information on examples of a network interface device (sometimes called an Intelligent Network Interface Card or “INIC”), see: U.S. Pat. No. 6,247,060; U.S. Pat. No. 6,226,680; Published U.S. Patent Application No. 20010021949; Published U.S. Patent Application No. 20010027496; and Published U.S. Patent Application No. 20010047433 (the contents of each of the above-identified patents and published patent applications is incorporated herein by reference). System 1 of FIG. 1 employs techniques set forth in these documents for transferring control of TCP/IP connections between a protocol processing stack and a network interface device.
NID 3 includes Media Access Control circuitry 12, three processors 13-15, a pair of Content Addressable Memories (CAMs) 16 and 17, an amount of Static Random Access Memory (SRAM) 18, queue manager circuitry 19, a receive processor 20, and a transmit sequencer 21. Receive processor 20 executes code stored its own control store 22.
In some embodiments where NID 3 fully offloads or substantially fully offloads CPU 4 of the task of performing TCP/IP protocol processing, NID 3 includes a processor 23. Processor 23 may, for example, be a general purpose microprocessor. Processor 23 performs slow-path processing such as TCP error condition handling and exception condition handling. In some embodiments, processor 23 also performs higher layer protocol processing such as, for example, iSCSI layer protocol processing such that NID 3 offloads CPU 4 of all iSCSI protocol processing tasks. In the example of FIG. 1, CPU 4 executes code that implements a file system, and processor 23 executes code that implements a protocol processing stack that includes an iSCSI protocol processing layer.
Overview of One Embodiment of a Fast-Path Receive Path:
Operation of NID 3 is now described in connection with the receipt onto NID 3 of a TCP/IP packet from network 2. DRAM 10 is initially partitioned to include a plurality of buffers. Receive processor 20 uses the buffers in DRAM 10 to store incoming network packet data as well as status information for the packet. For each buffer, a 32-bit buffer descriptor is created. Each 32-bit buffer descriptor indicates the size of the associated buffer and the location in DRAM of the associated buffer. The location is indicated by a 19-bit pointer.
At start time, the buffer descriptors for the fee buffers are pushed onto on a “free-buffer queue” 24. This is accomplished by writing the buffer descriptors to queue manager 19. Queue manager 19 maintains multiple queues including the “free-buffer queue” 24. In this implementation, the heads and tails of the various queues are located in SRAM 18, whereas the middle portion of the queues are located in DRAM 10.
The TCP/IP packet is received from the network 2 via Physical Layer Interface (PHY) circuitry 11 and MAC circuitry 12. As the MAC circuitry 12 processes the packet, the MAC circuitry 12 verifies checksums in the packet and generates “status” information. After all the packet data has been received, the MAC circuitry 12 generates “final packet status” (MAC packet status). The status information (also called “protocol analyzer status”) and the MAC packet status information is then transferred to a free one of the DRAM buffers obtained from the free-buffer queue 24. The status information and MAC packet status information is stored prepended to the associated data in the buffer.
After all packet data has been transferred to the free DRAM buffer, receive processor 20 pushes a “receive packet descriptor” (also called a “summary”) onto a “receive packet descriptor” queue 25. The “receive packet descriptor” includes a 14-bit hash value, the buffer descriptor, a buffer load-count, the MAC ID, and a status bit (also called an “attention bit”). The 14-bit hash value was previously generated by the receive processor 20 (from the TCP and IP source and destination addresses) as the packet was received. If the “attention bit” of the receive packet descriptor is a one, then the packet is not a “fast-path candidate”; whereas if the attention bit is a zero, then the packet is a “fast-path candidate”. In the present example of a TCP/IP offload engine, the attention bit being a zero indicates that the packet employs both the TCP protocol and the IP protocol.
Once the “receive packet descriptor” (including the buffer descriptor that points to the DRAM buffer where the data is stored) has been placed in the “receive packet descriptor” queue 25 and the packet data has been placed in the associated DRAM buffer, one of the processors 13 and 14 can retrieve the “receive packet descriptor” from the “receive packet descriptor” queue 25 and examine the “attention bit”.
If the attention bit is a digital one, then the processor determines that the packet is not a “fast-path candidate” and the packet is handled in “slow-path”. In one embodiment where the packet is a TCP/IP packet, wherein the attention bit indicates the packet is not a “fast-path candidate”, and where NID 3 performs full offload TCP/IP functions, general purpose processor 23 performs further protocol processing on the packet (headers and data). In another embodiment where there is no general purpose processor 23 and where NID 3 performs partial TCP/IP functions, the entire packet (headers and data) are transferred from the DRAM buffer and across host bus 6 such that CPU 4 performs further protocol processing on the packet.
If, on the other hand, the attention bit is a zero, then the processor determines that the packet is a “fast-path candidate”. If the processor determines that the packet is a “fast-path candidate”, then the processor uses the buffer descriptor from the “receive packet descriptor” to initiate a DMA transfer the first approximately 96 bytes of information from the pointed to buffer in DRAM 10 into a portion of SRAM 18 so that the processor can examine it. This first approximately 96 bytes contains the IP source address of the IP header, the IP destination address of the IP header, the TCP source address (“TCP source port”) of the TCP header, and the TCP destination address (“TCP destination port”) of the TCP header. The IP source address of the IP header, the IP destination address of the IP header, the TCP source address of the TCP header, and the TCP destination address of the TCP header together uniquely define a single “connection context” with which the packet is associated.
While this DMA transfer from DRAM to SRAM is occurring, the processor uses the 14-bit hash from the “receive packet descriptor” to identify the connection context of the packet and to determine whether the connection context is one of a plurality of connection contexts that are under the control of NID 3. The hash points to one hash bucket in a hash table 104 in SRAM 18. In the diagram of FIG. 1, each row of the hash table 104 is a hash bucket. Each hash bucket contains one or more hash table entries. If the hash identifies a hash bucket having more than-one hash table entry (as set forth below in further detail), then the processor attempts to match the IP source address, IP destination address, TCP source address (port), and TCP destination address (port) retrieved from DRAM with the same fields, i.e., the IP source address, IP destination address, TCP source port, and TCP destination port of each hash table entry. The hash table entries in the hash bucket are searched one by one in this manner until the processor finds a match. When the processor finds a matching hash table entry, a number stored in the hash table entry (called a “transmit control block number” or “TCB number”) identifies a block of information (called a TCB) related to the connection context of the packet. There is one TCB maintained on NID 3 for each connection context under the control of NID 3.
If the connection context is determined not to be one of the contexts under the control of NID 3, then the “fast-path candidate” packet is determined not to be an actual “fast-path packet.” In one embodiment where NID 3 includes general purpose processor 23 and where NID 3 performs full TCP/IP offload functions, processor 23 performs further TCP/IP protocol processing on the packet. In another embodiment where NID 3 performs partial TCP/IP offload functions, the entire packet (headers and data) is transferred across host bus 6 for further TCP/IP protocol processing by the sequential protocol processing stack of CPU 4.
If, on the other hand, the connection context is one of the connection contexts under control of NID 3, then software executed by the processor (13 or 14) checks for one of numerous exception conditions and determines whether the packet is a “fast-path packet” or is not a “fast-path packet”. These exception conditions include: 1) IP fragmentation is detected; 2) an IP option is detected; 3) an unexpected TCP flag (urgent bit set, reset bit set, SYN bit set or FIN bit set) is detected; 4) the ACK field in the TCP header shrinks the TCP window; 5) the ACK field in the TCP header is a duplicate ACK and the ACK field exceeds the duplicate ACK count (the duplicate ACK count is a user settable value); and 6) the sequence number of the TCP header is out of order (packet is received out of sequence).
If the software executed by the processor (13 or 14) detects an exception condition, then the processor determines that the “fast-path candidate” is not a “fast-path packet.” In such a case, the connection context for the packet is “flushed” (control of the connection context is passed back to the stack) so that the connection context is no longer present in the list of connection contexts under control of NID 3. If NID 3 is a full TCP/IP offload device including general purpose processor 23, then general purpose processor 23 performs further TCP/IP processing on the packet. In other embodiments where NID 3 performs partial TCP/IP offload functions and NID 3 includes no general purpose processor 23, the entire packet (headers and data) is transferred across host bus 6 to CPU 4 for further “slow-path” protocol processing.
If, on the other hand, the processor (13 or 14) finds no such exception condition, then the “fast-path candidate” packet is determined to be an actual “fast-path packet”. The processor executes a software state machine such that the packet is processed in accordance with the IP and TCP protocols. The data portion of the packet is then DMA transferred to a destination identified by another device or processor. In the present example, the destination is located in storage 5 and the destination is identified by a file system controlled by CPU 4. CPU 4 does no or very little analysis of the TCP and IP headers on this “fast-path packet”. All or substantially all analysis of the TCP and IP headers of the “fast-path packet” is done on NID 3.
Description of a TCB Lookup Method:
As set forth above, information for each connection context under the control of NID 3 is stored in a block called a “Transmit Control Block” (TCB). An incoming packet is analyzed to determine whether it is associated with a connection context that is under the control of NID 3. If the packet is associated with a connection context under the control of NID 3, then a TCB lookup method is employed to find the TCB for the connection context. This lookup method is described in further detail in connection with FIGS. 2 and 3.
NID 3 is a multi-receive processor network interface device. In NID 3, up to sixteen different incoming packets can be in process at the same time by two processors 13 and 14. (Processor 15 is a utility processor, but each of processors 13 and 14 can perform receive processing or transmit processing.) A processor executes a software state machine to process the packet. As the packet is processed, the state machine transitions from state to state. One of the processors, for example processor 13, can work on one of the packets being received until it reaches a stopping point. Processor 13 then stops work and stores the state of the software state machine. This stored state is called a “processor context”. Then, at some later time, either the same processor 13 or the other processor 14 may resume processing on the packet. In the case where the other processor 14 resumes processing, processor 14 retrieves the prior state of the state machine from the previous “processor context”, loads this state information into its software state machine, and then continues processing the packet through the state machine from that point. In this way, up to sixteen different flows can be processed by the two processors 13 and 14 working in concert.
In this example, the TCB lookup method starts after the TCP packet has been received, after the 14-bit hash and the attention bit has been generated, and after the hash and attention bit have been pushed in the form of a “receive packet descriptor” onto the “receive packet descriptor queue”.
In a first step (step 200), one of processors 13 or 14 obtains an available “processor context”. The processor pops (step 201) the “receive packet descriptor” queue 25 to obtain the “receive packet descriptor”. The “receive packet descriptor” contains the previously-described 14-bit hash value 101 (see FIG. 2) and the previously-described attention bit. The processor checks the attention bit.
If the attention bit is set (step 202), then processing proceeds to slow-path processing. As set forth above, if NID 3 is a TCP/IP full-offload device and if the packet is a TCP/IP packet, then further TCP/IP processing is performed by general purpose processor 23. As set forth above, if NID 3 is a TCP/IP partial offload device, then the packet is sent across host bus 6 for further protocol processing by CPU 4.
If, on the other hand, the attention bit is not set (step 203), then the processor initiates a DMA transfer of the beginning part of the packet (including the header) from the identified buffer in DRAM 10 to SRAM 18. 14-bit hash value 101 (see FIG. 2) actually comprises a 12-bit hash value 102 and another two bits 103. The 12-bit hash value (bits [13:2]) identifies an associated one of 4096 possible 64-byte hash buckets. In this embodiment, up to 48 of these hash buckets can be cached in SRAM in a hash table 104, whereas any additional used hash buckets 105 are stored in DRAM 10. Accordingly, if the hash bucket identified by the 12-bit hash value is in DRAM 10, then the hash bucket is copied (or moved) from DRAM 10 to an available row in hash table 104. To facilitate this, there is a hash byte (SRAM_hashbt) provided in SRAM for each of the possible 4096 hash buckets. A six-bit pointer field in the hash byte indicates whether the associated hash bucket is located in SRAM or not. If the pointer field contains a number between 1 and 48, then the pointer indicates the row of hash table 104 where the hash bucket is found. If the pointer field contains the number zero, then the hash bucket is not in hash table 104 but rather is in DRAM. The processor uses the 12-bit hash value 102 to check the associated hash byte to see if the pointed to hash bucket is in the SRAM hash table 104 (step 204).
If the hash bucket is in the SRAM hash table 104 (step 205), then processing is suspended until the DMA transfer of the header from DRAM to SRAM is complete.
If, on the other hand, the hash bucket is not in the SRAM hash table 104 (step 206), then a queue (Q_FREEHASHSLOTS) identifying free rows in hash table 104 is accessed (the queue is maintained by queue manager 19) and a free hash bucket row (sometimes called a “slot’) is obtained. The processor then causes the hash bucket to be copied or moved from DRAM and into the free hash bucket row. Once the hash bucket is present in SRAM hash table 104, the processor updates the pointer field in the associated hash byte to indicate that the hash bucket is now in SRAM and is located at the row now containing the hash bucket.
Once the pointed to hash bucket is in SRAM hash table 104, the up to four possible hash bucket entries in the hash bucket are searched one by one (step 207) to identify if the TCP and IP fields of an entry match the TCP and IP fields of the packet header 106 (the TCP and IP fields from the packet header were obtained from the receive descriptor).
In the example of FIG. 2, the pointed to hash bucket contains two hash entries. The hash entries are checked one by one. The two bits 103 Bits [1:0] of the 14-bit hash are used to determine which of the four possible hash table entry rows (i.e., slots) to check first. In FIG. 2, the second hash entry 107 (shown in exploded view) is representative of the other hash table entries. It includes a 16-bit TCB# 108, a 32-bit IP destination address, a 32-bit IP source address, a 16-bit TCP destination port, and a 16-bit TCP source port.
If all of the entries in the hash bucket are searched and a match is not found (step 208), then processing proceeds by the slow-path. If, on the other hand, a match is found (step 209), then the TCB# portion 108 of the matching entry identifies the TCB of the connection context.
NID 3 supports both fast-path receive processing as well as fast-path transmit processing. A TCP/IP connection can involve bidirectional communications in that packets might be transmitted out of NID 3 on the same TCP/IP connection that other packets flow into NID 3. A mechanism is provided so that the context for a connection can be “locked” by one processor (for example, a processor receiving a packet on the TCP/IP connection) so that the another processor (for example, a processor transmitting a packet on the same TCP/IP connection) will not interfere with the connection context. This mechanism includes two bits for each of the up to 8192 connections that can be controlled by NID 3: 1) a “TCB lock bit” (SRAM_tcblock), and 2) a “TCB in-use bit” (SRAM_tcbinuse). The “TCB lock bits” 109 and the “TCB in-use bits” 110 are maintained in SRAM 18.
The processor attempts to lock the designated TCB (step 210) by attempting to set the TCB's lock bit. If the lock bit indicates that the TCB is already locked, then the processor context number (a 4-bit number) is pushed onto a linked list of waiting processor contexts for that TCB. Because there are sixteen possible processor contexts, a lock table 112 is maintained in SRAM 18. There is one row in lock table 112 for each of the sixteen possible processor contexts. Each row has sixteen four-bit fields. Each field can contain the 4-bit processor context number for a waiting processor context. Each row of the lock table 112 is sixteen entries wide because all sixteen processor contexts may be working on or waiting for the same TCB.
If the lock bit indicates that the TCB is already locked (step 211), then the processor context number (a four-bit number because there can be up to sixteen processor contexts) is pushed onto the row of the lock table 112 associated with the TCB. A lock table content addressable memory (CAM) 111 is used to translate the TCB number (from TCB field 108) into the row number in lock table 112 where the linked list for that TCB number is found. Accordingly, lock table CAM 111 receives a sixteen-bit TCB number and outputs a four-bit row number. When the processor context that has the TCB locked is ready to suspend itself, it consults the lock table CAM 111 and the associated lock table 112 to determine if there is another processor context waiting for the TCB. If there is another processor context waiting (there is an entry in the associated row of lock table 112), then it restarts the first (oldest) of the waiting processor contexts in the linked list. The restarted processor context is then free to lock the TCB and continue processing.
If, on the other hand, the TCB is not already locked, then the processor context locks the TCB by setting the associated TCB lock bit 109. The processor context then supplies the TCB number (sixteen bits) to an IN SRAM CAM 113 (step 212) to determine if the TCB is in one of thirty-two TCB slots 114 in SRAM 18. (Up to thirty-two TCBs are cached in SRAM, whereas a copy of all “in-use” TCBs is kept in DRAM). The IN SRAM CAM 113 outputs a sixteen-bit value, five bits of which point to one of the thirty-two possible TCB slots 114 in SRAM 18. One of the bits is a “found” bit.
If the “found” bit indicates that the TCB is “found”, then the five bits are a number from one to thirty-two that points to a TCB slot in SRAM 18 where the TCB is cached. The TCB has therefore been identified in SRAM 18, and fast-path receive processing continues (step 213).
If, on the other hand, the “found” bit indicates that the TCB is not found, then the TCB is not cached in SRAM 18. All TCBs 115 under control of NID 3 are, however, maintained in DRAM 10. The information in the appropriate TCB slot in DRAM 10 is then written over one of the thirty-two TCB slots 114 in SRAM 18. In the event that one of the SRAM TCB slots is empty, then the TCB information from DRAM 10 is DMA transferred into that free SRAM slot. If there is no free SRAM TCB slot, then the least-recently-used TCB slot in SRAM 18 is overwritten.
Once the TCB is located in SRAM cache 114, the IN SRAM CAM 113 is updated to indicate that the TCB is now located in SRAM at a particular slot. The slot number is therefore written into the IN SRAM CAM 113. Fast-path receive processing then continues (step 216).
When a processor context releases control of a TCB, it is not always necessary for the TCB information in SRAM 18 to be written to DRAM to update the version of the TCB in DRAM. If, for example, the TCB is a commonly used TCB and the TCB will be used again in the near future by the next processor context, then the next processor context can use the updated TCB in SRAM without the updated TCB having to have been written to DRAM and then having to be transferred back from DRAM to SRAM. Avoiding this unnecessary transferring of the TCB is advantageous. In accordance with one embodiment of the present invention, the processor context releasing control of a TCB does not update the DRAM version of the TCB, but rather the processor context assuming control of the TCB has that potential responsibility. A “dirty bit” 116 is provided in each TCB. If the releasing processor context changed the contents of the TCB (i.e., the TCB is dirty), then the releasing processor context sets this “dirty bit” 116. If the next processor context needs to put another TCB into the SRAM TCB slot held by the dirty TCB, then the next processor first writes the dirty TCB information (i.e., updated TCB information) to overwrite the corresponding TCB information in DRAM (i.e., to update the DRAM version of the TCB). If, on the other hand, the next processor does not need to move a TCB into an SRAM slot held by a dirty TCB, then the next processor does not need to write the dirty TCB information to DRAM. If need be, the next processor can either just update a TCB whose dirty bit is not set, or the next processor can simply overwrite the TCB whose dirty bit is not set (for example, to move another TCB into the slot occupied by the TCB whose dirty bit is not set).
In one specific embodiment, the instruction set of processors 13-15 includes the instructions in Table 1 below.









TABLE 1





OpdSel
Name
Description







0b011000000
CamAddrA
Write Only. CamAddr=AluOut[4:0].




This register is written to define which




one of the entries of the multi-entry




CAM A will be read from or written to.




The entry is either read from




CamContentsA register on a read, or the




entry is written into the CamContentsA




register on a write. CAM A is a




thirty-two entry CAM when CAMs A




and B are used together as a single




CAM. If CAM A is used separately,




then CAM A is an sixteen-entry CAM.


0b011000001
CamContentsA
Read/Write. When writing:




Cam Valid[CamAddrA]=~AluOut[16].




CamContents [CamAddrA]=




AluOut[15:0]. Accordingly, writing




bit sixteen “invalidates” the CAM




entry. The tilde symbol here indicates




the logical NOT.




When reading:




Bit 16=~CamValid[CamAddrA].




Bits 15-0=Cam Contents[CamAddrA].


0b011000010
CamMatchA
Read/Write. Writing a sixteen-bit value




into this register causes CAM A to




search its entries for a match with




valid CAM A entries. A subsequent




read of this register returns the




result of the search as follows:




Bit 5=contents not found.




Bits 4-0=If the contents were found




and the matched entry is valid, then bits




4-0 are the number of the CAM entry




which matched.


0b011000011
CamConfigAB
Write Only. CamSplit=AluOut[0]. If




CamSplit is set, then CAM A is split




into two sixteen-entry CAMs: CAM A




and CAM B. The following addresses




(CamAddrB, CanConentsB and




CamMatchB) are then available to use




the second part of the CAM (CAM B).


0b011000100
CamAddrB
Write Only. See the description of




CamAddrA above.


0b011000101
CamContentsB
Read/Write. See the description of




CamContentsB above.


0b011000110
CamMatchB
Read/Write. These registers




(CamAddrB, Cam ContentsB and




CamMatchB) are identical in use to




those for CAM A (see above), except




that they are for the second half of the




first CAM (CAM B).


0b011001000
CamAddrC
Write Only. This register for CAM C




is identical in function to the




corresponding register for CAM A.


0b011001001
CamContentsC
Read/Write. This register for CAM C




is identical in function to the




corresponding register for CAM A.


0b011001010
CamMatchC
Read/Write. This register for CAM C




is identical in function to the




corresponding register for CAM A.


0b011001011
CamConfigCD
Write Only. As in the case of CAM A




above, CAM C can be split into two 




sixteen-entry CAMs: CAM C and




CAM D.


0b011001100
CamAddrD
Write Only. This register for CAM D




is identical in function to the




corresponding register for CAM D.


0b011001101
CamContentsD
Read/Write. This register for CAM D




is identical in function to the




corresponding register for CAM D.


0b011001110
CamMatchD
Read/Write. This register for CAM D




is identical in function to the




corresponding register for CAM D.









One embodiment of the code executed by processors 13-15 is written using functions. These functions are in turn made up of instructions including those instructions set forth in Table 1 above. The functions are set forth in the file SUBR.MAL of the CD Appendix (the files on the CD Appendix are incorporated by reference into the present patent document). These functions include:
1) The INSRAM_CAM_INSERT function: Executing this function causes the TCB number present in a register (register cr11) to be written into the IN SRAM CAM (CAM A of the processor). The particular CAM slot written to is identified by the lower sixteen bits of the value present in another register (register TbuffL 18).
2) The INSRAM_CAM_REMOVE function: Executing this function causes the CAM entry in the IN SRAM CAM slot identified by a register (register cr11) to be invalidated (i.e., removed). The entry is invalidated by setting bit 16 of a register (register CAM_CONTENTS_A).
3) The INSRAM_CAM SEARCH function: Executing this function causes a search of the IN SRAM CAM for the TCB number identified by the TCB number present in a register (register cr11). The result of the search is a five-bit slot number that is returned in five bits of another register (register TbuffL 18). The value returned in a sixth bit of the register TbuffL 18 indicates whether or not the TCB number was found in the INSRAM_CAM.
4) The LOCKBL_CAM_INSERT function: Executing this function causes the sixteen-bit TCB number present in a register (register cr11) to be written into the LOCK TABLE CAM (CAM C of the processor). The particular CAM slot written to is identified by the value present in a register (register cr10).
5) The LOCKBL_CAM_REMOVE function: Executing this function causes the CAM entry in the LOCK TABLE CAM slot identified by a register (register cr10) to be invalidated (i.e., removed). The entry is invalidated by setting bit of another register (register CAM_CONTENTS_C).
6) The LOCK_TABLE_SEARCH function: Executing this function causes a search of the LOCK TABLE CAM for the TCB number identified by the TCB number present in a register (register cr11). The result of the search is a four-bit number of a row in the lock table. The four-bit number is four bits of another register (register cr10). The value returned in a fifth bit of the register cr10 indicates whether or not the TCB number was found in the LOCK TABLE CAM.
Compact Disc Appendix:
The Compact Disc Appendix includes a folder “CD Appendix A”, a folder “CD Appendix B”, a folder “CD Appendix C”, and a file “title page.txt”. CD Appendix A includes a description of an integrated circuit (the same as ASIC 9 of FIG. 1 except that the integrated circuit of CD Appendix A does not include processor 23) of one embodiment of a TCP/IP offload network interface device (NID). CD Appendix B includes software that executes on a host computer CPU, where the host computer is coupled to a NID incorporating the integrated circuit set forth in CD Appendix A and wherein the host computer includes a CPU that executes a protocol stack. CD Appendix C includes a listing of the program executed by the receive processor of the integrated circuit set forth in Appendix A as well as a description of the instruction set executed by the receive processor.
The CD Appendix A includes the following: 1) a folder “Mojave verilog code” that contains a hardware description of an embodiment of the integrated circuit, and 2) a folder “Mojave microcode” that contains code that executes on the processors (for example, processors 13 and 14 of FIG. 1) of the integrated circuit. In the folder “Mojave microcode”, the file “MAINLOOP.MAL” is commented to indicate instructions corresponding to various steps of the method of FIG. 3. In the folder “Mojave microcode”, the file “SEQ.H” is a definition file for the “MAINLOOP.MAL” code. Page 9 sets forth steps in accordance with a twenty-step method in accordance with some embodiments of the present invention. Page 10 sets forth the structure of a TCB in accordance with some embodiments. Page 17 sets forth the structure of a hash byte (called a “TCB Hash Bucket Status Byte”).
A description of the instruction set executed by processors 13-15 of FIG. 1 is set forth in the section of this document entitled “Mojave Hardware Specification.”
The CD Appendix B includes the following: 1) a folder entitled “simba (device driver software for Mojave)” that contains device driver software executable on the host computer; 2) a folder entitled “atcp (free BSD stack and code added to it)” that contains a TCP/IP stack [the folder “atcp” contains: a) a TCP/IP stack derived from the “free BSD” TCP/IP stack (available from the University of California, Berkeley) so as to make it run on a Windows operating system, and b) code added to the free BSD stack between the session layer above and the device driver below that enables the BSD stack to carry out “fast-path” processing in conjunction with the NID]; and 3) a folder entitled “include (set of files shared by ATCP and device driver)” that contains a set of files that are used by the ATCP stack and are used by the device driver.
The CD Appendix C includes the following: 1) a file called “mojave_rcv_seq (instruction set description).mdl” that contains a description of the instruction set of the receive processor, and 2) a file called “mojave_rcv_seq (program executed by receive processor).mal” that contains a program executed by the receive processor.
System Configurations:
FIGS. 4-9 illustrate various system configurations involving a network interface device in accordance with the present invention. These configurations are but some system configurations. The present invention is not limited to these configurations, but rather these configurations are illustrated here only as examples of some of the many configurations that are taught in this patent document.
FIG. 4 shows a computer 300 wherein a network interface device (NID) 301 is coupled via a connector 302 and a host bus 303 to a CPU 304 and storage 305. CPU 304 and storage 305 are together referred to as a “host” 306.
Rather than being considered coupled to a host, network interface device (NID) 301 can be considered part of a host as shown in FIG. 5. In FIG. 5, what is called a host computer 400 includes NID 301 as well as CPU 304 and storage 305. In both the examples of FIGS. 4 and 5, the CPU executes instructions that implement a sequential protocol processing stack. The network interface device 301 performs fast-path hardware accelerated protocol processing on some types of packets such that CPU 304 performs no or substantially no protocol processing on these types of packets. Control of a connection can be passed from the NID to the stack and from the stack to the NID.
FIG. 6 shows a computer 500 wherein NID 301 is coupled to CPU 304 and storage 305 by a bridge 501.
FIG. 7 shows a computer 500 wherein a network interface device (NID) 501 is integrated into a bridge integrated circuit 502. Bridge 502 couples computer 500 to a network 503. Bridge 502 is coupled to CPU 504 and storage 505 by local bus 506. CPU 504 executes instructions that implement a software sequential protocol processing stack. Bridge 502 is coupled to multiple expansion cards 507, 508 and 509 via a host bus 510. Network interface device 501 performs TCP and IP protocol processing on certain types of packets, thereby offloading CPU and its sequential protocol processing stack of these tasks. Control of a connection can be passed from the NID to the stack and from the stack to the NID.
In one version, NID 501 is a full TCP/IP offload device. In another version, NID is a partial TCP/IP offload device. The terms “partial TCP/IP” are used here to indicate that all or substantially all TCP and IP protocol processing on certain types of packets is performed by the offload device, whereas substantial TCP and IP protocol processing for other types of packets is performed by the stack.
FIG. 8 shows a computer 700 wherein a network interface device (NID) 701 couples CPU 702 and storage 703 to network 704. NID 701 includes a processor that implements a sequential protocol processing stack 705, a plurality of sequencers 706 (such as, for example, a receive sequencer and a transmit sequencer), and a plurality of processors 707. This embodiment maybe a full-offload embodiment in that processor 705 fully offloads CPU 702 and its stack of all or substantially all TCP and IP protocol processing duties.
FIG. 9 shows a computer 800 wherein a network interface device (NID) 801 couples CPU 802 and storage 803 to network 804. NID 801 includes a plurality of sequencers 806 (for example, a receive sequencer and a transmit sequencer), and a plurality of processors 807. In this example, CPU 802 implements a software sequential protocol processing stack, and NID 801 does not include a general purpose processor that implements a sequential software protocol processing stack. This embodiment may be a partial-offload embodiment in that NID 801 performs all or substantially all TCP and IP protocol processing tasks on some types of packets, whereas CPU 802 and its stack perform TCP and IP protocol processing on other types of packets.
In the realization of different embodiments, the techniques, methods, and structures set forth in the documents listed below are applied to the system, and/or to the network interface device (NID), and/or to the application specific integrated circuit (ASIC) set forth in present patent document: U.S. Pat. No. 6,389,479; U.S. Pat. No. 6,470,415; U.S. Pat. No. 6,434,620; U.S. Pat. No. 6,247,060; U.S. Pat. No. 6,226,680; Published U.S. Patent Application 20020095519; Published U.S. Patent Application No. 20020091844; Published U.S. Patent Application No. 20010021949; Published U.S. Patent Application No. 20010047433; and U.S. patent application Ser. No. 09/801,488, entitled “Port Aggregation For Network Connections That Are Offloaded To Network Interface Devices”, filed Mar. 7, 2001. The content of each of the above-identified patents, published patent applications, and patent application is incorporated herein by reference.
Although certain specific exemplary embodiments are described above in order to illustrate the invention, the invention is not limited to the specific embodiments. NID 3 can be part of a memory controller integrated circuit or an input/output (I/O) integrated circuit or a bridge integrated circuit of a microprocessor chip-set. In some embodiments, NID 3 is part of an I/O integrated circuit chip such as, for example, the Intel 82801 integrated circuit of the Intel 820 chip set. NID 3 may be integrated into the Broadcom ServerWorks Grand Champion HE chipset, the Intel 82815 Graphics and Memory Controller Hub, the Intel 440BX chipset, or the Apollo VT8501 MVP4 North Bridge chip. The instructions executed by receive processor 20 and/or processors 13-15 are, in some embodiments, downloaded upon power-up of NID 3 into a memory on NID 3, thereby facilitating the periodic updating of NID functionality. High and low priority transmit queues may be implemented using queue manager 19. Hardcoded transmit sequencer 21, in some embodiments, is replaced with a transmit processor that executes instructions. Processors 13, 14 and 15 can be identical processors, each of which can perform receive processing and/or transmit processing and/or utility functions. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the following claims that follow the “Mojave Hardware Specification” section below.
Mojave Hardware Specification
Features
1) Peripheral Component Interconnect (PCI) Interface.

    a) Universal PCI interface supports both 5.0V and 3.3V signaling environments;
    b) Supports both 32-bit and 64 bit PCI interface;
    c) Supports PCI clock frequencies from 0 MHz to 66 MHz;
    d) High performance bus mastering architecture;
    e) Host memory based communications reduce register accesses;
    f) Host memory based interrupt status word reduces register reads;
    g) Plug and Play compatible;
    h) PCI specification revision 2.2 compliant;
    i) PCI bursts up to 4 K bytes;
    j) Supports cache line operations up to 128 bytes;
    k) Both big-endian and little-endian byte alignments supported; and
    l) Supports Expansion ROM.


2) Network Interface.

    a) One internal 802.3 and ethernet compliant Mac;
    b) Gigabit Media Independent Interface (GMII) supports external PHYs;
    c) Ten Bit Interface (TBI) supports external SERDES;
    d) 10 BASE-T, 100 BASE-TX/FX and 1000 BASE-TX/FX supported;
    e) Full and half-duplex modes supported at 10/100 speeds;
    f) Automatic PHY status polling notifies system of status change;
    g) Provides SNMP statistics counters;
    h) Supports broadcast and multicast packets;
    i) Provides promiscuous mode for network monitoring or multiple unicast address detection;
    j) Supports “Huge Packets” up to 9018B; and
    k) Supports auto-negotiating Phys.


3) Memory Interface.

    a) External Dram buffering of transmit and receive packets;
    b) ECC error correction and detection;
    c) 64-bit data interface supports maximum throughput of 600 MB/s at 100 Mhz;
    d) Supports external FLASH ROM up to 1 MB, for diskless boot applications; and
    e) Supports external serial EEPROM for custom configuration and Mac addresses.


4) Protocol Processor.

    a) High speed, custom, 32-bit processor executes 100 million instructions per second;
    b) Processes IP, TCP, IPX and UDP protocols;
    c) Supports up to 32K resident TCP/IP contexts; and
    d) Writable control store (WCS) allows field updates and feature enhancements.


5) Power.

    a) 1.8/3.3V chip operation; and
    b) PCI controlled 5.0V/3.3V I/O cell operation.


6) Packaging.

    a) 272-pin plastic ball grid array.

General Description



Mojave (See FIG. 10) is a 32-bit, full-duplex, single channel, 10/100/1000-Megabit per second (Mbps), Session Layer Interface Controller (SLIC), designed to provide high-speed protocol processing for server and desktop applications. It combines the functions of a standard network interface controller and a protocol processor within a single chip.
When combined with the 802.3/GMII compliant Phy and Synchronous Dram (SDRAM), Mojave comprises one complete ethernet node. It contains one 802.3/ethernet compliant Mac, a PCI Bus Interface Unit (BIU), a memory controller, transmit fifo, receive fifo and a custom TCP/IP protocol processor. Mojave supports 10 Base-T, 100 Base-TX and 1000 Base-TX via the GMII interface attachment of appropriate Phys. Mojave also supports 100 Base-FX, and 1000 Base-FX via the TBI interface attachment of external Serdes.
The Mojave Mac provides statistical information that may be used for SNMP. The Mac can operate in promiscuous mode allowing Mojave to function as a network monitor, receive broadcast and multicast packets and implement multiple Mac addresses for each node.
Any 802.3/GMII/TBI compliant PHY/SERDES can be utilized, allowing Mojave to support 10 BASE-T, 10 BASE-T2, 100 BASE-TX, 100 Base-FX, 100 BASE-T4, 1000 BASE-TX or 1000 BASE-FX as well as future interface standards. PHY identification and initialization is accomplished through host driver initialization routines. PHY status registers can be polled continuously by Mojave to detect PHY status changes which are then reported to the host driver. The Mac can be configured to support a maximum frame size of 1518 bytes or 9018 bytes.
The 64-bit, multiplexed BIU provides a direct interface to the PCI bus for both slave and master functions. Mojave is capable of operating in either a 64-bit or 32-bit PCI environment, while supporting 64-bit addressing in either configuration. PCI bus frequencies up to 33 MHz are supported yielding instantaneous bus transfer rates of 266 MB/s. Both 5.0V and 3.3V signaling environments can be utilized by Mojave. Configurable cache-line size up to 256B will accommodate future architectures, and Expansion ROM/Flash support will allow for diskless system booting. Non-PC applications are supported via programmable big and little endian modes. Host based communication has been utilized to provide the best system performance possible.
Mojave supports Plug-N-Play auto-configuration through the PCI configuration space. Support of an external eeprom allows for local storage of configuration information such as Mac addresses.
External SDRAM provides frame buffering, which is configurable as 1 MB, 2 MB, 4 MB or 8 MB using the appropriate technology and width selections. Use of −10 speed grades yields an external buffer bandwidth of 88 MB/s. The buffer provides temporary storage of both incoming and outgoing frames. The protocol processor accesses the frames within the buffer in order to implement TCP/IP and NETBIOS. Incoming frames are processed, assembled then transferred to host memory under the control of the protocol processor. For transmit, data is moved from host memory to buffers where various headers are created before being transmitted out via the Mac.
1) Datapath Bandwidth (See FIG. 11).
2) Cpu Bandwidth (See FIG. 12).
3) Performance Features.

    a) 896 registers improve performance through reduced scratch ram accesses and reduced instructions;
    b) Register windowing eliminates context-switching overhead;
    c) Separate instruction and data paths eliminate memory contention;
    d) Totally resident control store eliminates stalling during instruction fetch;
    e) Multiple logical processors reduce context switching and improve real-time response;
    f) Pipelined architecture increases operating frequency;
    g) Shared registers and scratch ram improve inter-processor communication;
    h) Fly-by receive sequencer assists address compare and checksum calculation;
    i) TCP/IP-context caching reduces latency;
    j) Hardware-implemented queues reduce Cpu overhead and latency;
    k) Horizontal microcode greatly improves instruction efficiency;
    l) Automatic frame DMA and status between Mac and dram buffer; and
    m) Deterministic architecture coupled with context switching eliminates processor stalls.


4) Pin Assignments (See FIG. 13).
Processor.
The processor (See FIG. 14) is a convenient means to provide a programmable state-machine capable of processing incoming frames and host commands, directing network traffic and directing PCI bus traffic. Three processors are implemented using shared hardware in a three-level pipelined architecture which launches and completes a single instruction for every clock cycle. The instructions are executed in three distinct phases corresponding to each of the pipeline stages where each phase is responsible for a different function.
The first instruction phase writes the instruction results of the last instruction to the destination operand, modifies the program counter (Pc), selects the address source for the instruction to fetch, then fetches the instruction from the control store. The fetched instruction is then stored in the instruction register at the end of the clock cycle.
The processor instructions reside in the on-chip control-store, which is implemented as a mixture of ROM and Sram. The ROM contains 4K instructions starting at address 0×0000 and aliases every 0×1000 locations throughout the first 0×8000 locations of instruction space. The Sram (WCS) will hold up to 0×1000 instructions starting at address 0×8000 and aliasing each 0×1000 locations throughout the last 0×8000 of instruction space. The ROM and Sram are both 49-bits wide accounting for bits [48:0] of the instruction microword. A separate mapping ram provides bits [55:49] of the microword (MapAddr) to allow replacement of faulty ROM based instructions. The mapping ram has a configuration of 512×7 which is insufficient to allow a separate ma address for each of the 4K ROM locations. To allow re-mapping of the entire 4K ROM space, the map ram address lines are connected to the address bits Fetch [9:3]. The result is that the ROM is re-mapped in blocks of 8 contiguous locations.
The second instruction phase decodes the instruction which was stored in the instruction register. It is at this point that the map address is checked for a non-zero value which will cause the decoder to force a Jmp instruction to the map address. If a non-zero value is detected then the decoder selects the source operands for the Alu operation based on the values of the OpdASel, OpdBSel and AluOp fields. These operands are then stored in the decode register at the end of the clock cycle. Operands may originate from File, Sram, or flip-flop based registers. The second instruction phase is also where the results of the previous instruction are written to the Sram.
The third instruction phase is when the actual Alu operation is performed, the test condition is selected and the Stack push and pop are implemented. Results of the Alu operation are stored in the results register at the end of the clock cycle.
FIG. 14 is a block diagram of the CPU. FIG. 14 shows the hardware functions associated with each of the instruction phases. Note that various functions have been distributed across the three phases of the instruction execution in order to minimize the combinatorial delays within any given phase.
Instruction Set.
The micro-instructions are divided into nine types according to the program control directive. The micro-instruction is further divided into sub-fields for which the definitions are dependant upon the instruction type. The six instruction types are listed IN FIG. 15.
All instructions (See FIG. 15) include the Alu operation (AluOp), operand “A” select (OpdASel), operand “B” select (OpdBSel) and Literal fields. Other field usage depends upon the instruction type.
The conditional jump (Jct/Jcf) instruction causes the program counter to be altered if the condition selected by the “test select” (TstSel) field is true/false. The new program counter (Pc) value is loaded from either the Literal field or the AluOut as described in the following section and the Literal field may be used as a source for the Alu or the ram address if the new Pc value is sourced by the Alu.
The “jump” (Jmp) instruction causes the program counter to be altered unconditionally. The new program counter (Pc) value is loaded from either the Literal field or the AluOut as described in the following section. The format allows instruction bits 22:16 to be used to perform a flag operation and the Literal field may be used as a source for the Alu or the ram address if the new Pc value is sourced by the Alu.
The “jump subroutine” (Jsr) instruction causes the program counter to be altered unconditionally. The new program counter (Pc) value is loaded from either the Literal field or the AluOut as described in the following section. The old program counter value is stored on the top location of the Pc-Stack which is implemented as a LIFO memory. The format allows instruction bits 22:16 to be used to perform a flag operation and the Literal field may be used as a source for the Alu or the ram address if the new Pc value is sourced by the Alu.
The “Cont” (Cont) instruction causes the program counter to increment. The format allows instruction bits 22:16 to be used to perform a flag operation and the Literal field may be used as a source for the Alu or the ram address.
The “return from subroutine” (Rts) instruction, or the conditional Rts (Rtt/Rtf) if the selected condition is true/false, causes the current Pc value to be replaced with the last value stored in the stack. The Literal field may be used as a source for the Alu or the ram address. The unconditional return (Rts) allows instruction bits 22:16 to be used to perform a flag operation.
The Map instruction is provided to allow replacement of instructions which have been stored in ROM and is implemented any time the “map enable” (MapEn) bit has been set and the content of the “map address” (MapAddr) field is non-zero. The instruction decoder forces a jump instruction with the Alu operation and destination fields set to pass the MapAddr field to the program control block.
FIGS. 16-20 show sequencer behavior, ALU operations, ALU operands, selected tests, and flag operations.
Program Errors:
Hardware will detect certain program errors. Any sequencer generating a program error will be forced to continue executing from location 0004. The program errors detected are:
1. Stack Overflow: A JSR is attempted and the stack registers are full.
2. Stack Underflow: An RTS is attempted and the stack registers are empty.
3. Incompatible Sram Size & Sram Alignment: An Sram Operation is attempted where the size and the Sram address would cause the operation to extend beyond the size of the word, e.g. Size=4 Address=401 or Size=2 Address=563.
4. An Sram read is attempted immediately following an Sram write. Because an Sram write is actually done in the clock cycle of the following instruction, the sram interface will be busy during that phase, and an Sram read is illegal at this time.
5. An attempt was made to access a non-existent register.
Sram Control Sequencer (SramCtrl).
Sram is the nexus for data movement within Mojave. A hierarchy of sequencers, working in concert, accomplish the movement of data between dram, Sram, Cpu, ethernet and the Pci bus. Slave sequencers, provided with stimulus from master sequencers, request data movement operations by way of the Sram, Pci bus and Dram. The slave sequencers prioritize, service and acknowledge the requests
The data flow block diagram of FIG. 21 shows all of the master and slave sequencers of the Mojave product. Request information such as r/w, address, size, endian and alignment are represented by each request line. Acknowledge information to master sequencers include only the size of the transfer being acknowledged.
The block diagram of FIG. 22 illustrates how data movement is accomplished for a Pci slave write to Dram. Psi sends a write request to the SramCtrl module. Psi requests Dwr to move data from Sram to dram. Dwr subsequently sends a read request to the SramCtrl module then writes the data to the dram via the Mctrl module. As each piece of data is moved from the Sram to Dwr, Dwr sends an acknowledge to the Psi module.
Sram Control Sequencer (SramCtrl).
The Sram control sequencer (See FIG. 23) services requests to store to, or retrieve data from an Sram organized as 2048 locations by 128 bits (32 KB). The sequencer operates at a frequency of 200 Mhz, allowing both a Cpu access and a dma access to occur during a standard 100 Mhz Cpu cycle. One 200 Mhz cycle is reserved for Cpu accesses during each 100 Mhz cycle while the remaining 200 Mhz cycle is reserved for dma accesses on a prioritized basis.
The block diagram of FIG. 23 shows the major functions of the Sram control sequencer. A slave sequencer begins by asserting a request along with r/w, ram address, data path alignment and request size. SramCtrl prioritizes the requests. The request parameters are then selected by a multiplexer which feeds the parameters to the Sram via alignment logic. The requestor provides the Sram address which when combined with the other parameters controls the input and output alignment. Sram outputs are fed to the output aligner. Requests are acknowledged in parallel with the returned data.
External Memory Control (memctrl).
Memctrl (See FIG. 24) implements the memory controller function and registers for access to SDRAM, Flash memory, and external configuration jumpers. It also implements the register interface for the serial EEPROM and GPIO access. Memctrl functional module summaries:
memregs: The memregs module provides the configuration and control registers for all the functions of memctrl. memregs also implements the GPIO interface registers for reading, writing and directional control, the FLASH control registers for configuring and accessing FLASH, and registers associated with configuring the SDPAM controller. memregs is accessed through the CPU data path with all of its registers mapped to a CPU register address.
dramcfg_seq: The dramcfg_seq module contains the refresh logic, timers, and sequencer for the various configuration accesses that are performed. This also includes operations which take place during initialization.
flash_seq: The flash_seq module performs the various FLASH memory access sequences. This module also implements the programmable nature of the access time delays between the control signals and data accesses.
dramif: The dramif module arbitrates between the memctrl modules requesting access to the memory interface. This includes the dramcfg_seq, flash_seq, memregs, dramwrt and dramrd modules. The dramif module also muxes the row and column address for the SDRAM accesses, muxs the read and write control signals between dramrd, dramwrt, etc., and also controls the direction of the data bus interface. dramif attempts to ping-pong between reads and writes to maximize the overlap between read and write buffers and for fairness. This fairness can be overriden if a requester asserts it's urgent request signal for high priority conditions like impending buffer overflow or underflow. When the flash_seq has access to the interface the checkbits become address and control signals and the FSH_CS_L signal is asserted.
dramwrt: The dramwrt module implements the data and control path for all masters requesting write access to SDRAM. The dramwrt submodule dramwrt_mux arbitrates across all six dma requesters giving the following priorities from highest to lowest: RcvA, Q2d, Psi, S2d, P2d and D2d. dramwrt_mux will then mux the selected requester's data and address. The dramwrt_ldctrl will buffer the granted requester's data and ack the appropriate requester while the dramwrt_seq will proceed to initiate an SDRAM write operation. After dramwrt_seq gains control of the SDRAM interface via dramif, the buffered data will be selected from dramwrt_data data buffers and written to memory. If ECC is enabled, the dramwrt_data block will also compute the checkbits as the data passes through. This block can also force ECC errors at any bit in any location. Also, as the data is being written, the dramwrt_cksum block will checksum the data and indicate to the DMA requester when the checksum is complete. P2d and D2d are the only two requesters which have checksums calculated for their transactions.
dramrd: The dramrd module implements the data and control path for all masters requesting read access from SDRAM. The dramrd submodule dramrd_mux arbitrates across all six dma requesters, giving the following priorities from highest to lowest: XmtA, Pso, D2s, D2q, D2p and D2d. dramrd_mux also implements a state machine to overlap multiple read operations. So when a requester's read operation is being satisfied from SDRAM, another operation can be in progress with respect to bank activation and addressing. Once the dramrd_mux starts a transaction the dramrd_seq intiates the request for the interface via dramif and starts the actual read sequence. Once data starts to come back from the SDRAM the dramrd_data block will check it for ECC errors, if ECC correction and detection is enabled. The data is then stored in a 64 byte read buffer. Once there is enough data to write to the sram, the dramrd_unld sequencer will select data from the read buffer and request access to sram. The acks coming back from these sram writes are directed by the dramrd_mux to the original DMA requestor. Once all the requested data is delivered to the requestor, this operation is then complete.
External Memory Read Operations (dramrd).
The dramrd controller (See FIG. 24) acts only as a slave sequencer to the rest of the Mojave chip. Servicing requests issued by master sequencers, the dramrd controller moves data from external SDRAM or flash to the Sram, via the dramif module, in blocks of 64 bytes or less. The nature of the SDRAM requires fixed burst sizes for each of it's internal banks with ras precharge intervals between each access. By selecting a burst size of 4 words for SDRAM bank reads and interleaving bank accesses on a 4 word boundary, we can ensure that the ras precharge interval for the first bank is satisfied before burst completion for the second bank, allowing us to re-instruct the first bank and continue with uninterrupted dram access. SDRAMs require a consistent burst size be utilized each and every time the SDRAM is accessed. For this reason, if an SDRAM access does not begin or end on a 16 word boundary, SDRAM bandwidth will be reduced due to less than 64 bytes of data being transferred to sram during the burst cycle.
The Memory Controller Block Diagram (See FIG. 24) depicts the major functional blocks of the dramrd controller. The first step is servicing a request to move data from SDRAM to Sram in the prioritization of the master sequencer requests. This is done by dramrd_mux. Next the dramrd_mux selects the DMA requester's dram read address and sram write address and applies configuration information to determine the correct bank, row and column address to apply. The dramrd_seq will control the operations of applying the row and column addresses and sequencing the appropriate control signals. While reading the data from the SDRAM interface the dramrd_data block will perform error detection and/or correction on the data if this feature is enabled. Once sufficient data has been read, the dramrd_unld sequencer issues a write request to the SramCtrl sequencer which in turn sends an acknowledge to the dramrd sequencer. The dramrd sequencer passes this acknowledge along to the level two master with a size code indicating how much data was written during the Sram cycle allowing the update of pointers and counters. The dram read and Sram write cycles repeat until the original burst request has been completed at which point the dramrd sequencer prioritizes any remaining requests in preparation for the next burst cycle.
Contiguous dram burst cycles are not guaranteed to the dramrd controller as an algorithm is implemented in the dramif which ensures highest priority to refresh cycles followed by ping-pong access between dram writes and dram reads and then confiuration and flash cycles.
FIG. 25 is a timing diagram illustrating how data is read from SDRAM. The dram has been configured for a burst of 4 with a latency of 2 clock cycles. Bank A is first selected/activated followed by a read command 2 clock cycles later. The bank select/activate for bank B is next issued as read data begins returning 2 clocks after the read command was issued to bank A. Two clock cycles before we need to receive data from bank B we issue the read command. Once all 4 words have been received from bank A we begin receiving data from bank B.
External Memory Write Operations (dramwrt).
The dramwrt controller (See FIG. 24) is a slave sequencer to the rest of Mojave. Servicing requests issued by master DMA sequencers, the dramwrt controller moves data from Sram to the external SDRAM or flash, via the dramif module, in blocks of 64 bytes or less while accumulating a checksum of the data moved. The nature of the SDRAM requires fixed burst sizes for each of it's internal banks with ras precharge intervals between each access. By selecting a burst size of 4 words for SDRAM writes and interleaving bank accesses on a 4 word boundary, we can ensure that the ras precharge interval for the first bank is satisfied before burst completion for the second bank, allowing us to re-instruct the first bank and continue with uninterrupted dram access. SDRAMs require a consistent burst size be utilized each and every time the SDRAM is accessed. For this reason, if an SDRAM access does not begin or end on a 64 byte boundary, SDRAM bandwidth will be reduced due to less than 16 words of data being transferred during the burst cycle.
The memctrl block diagram (See FIG. 24) contains the major functional blocks of the dramwrt controller. The first step in servicing a request to move data from Sram to SDRAM is the prioritization of the level two master requests. This is done by the dramwrt_mux. Next the dramwrt_mux takes a Snapshot of the dram write address and applies configuration information to determine the correct dram, bank, row and column address to apply. The dramwrt_ldctrl sequencer immediately issues a read command to the Sram to which the Sram responds with both data and an acknowledge. The read data is stored within the dramwrt_data buffers by the dramwrt_ldctrl sequencer. The dramwrt_ldctrl sequencer passes the acknowledge to the level two master along with a size code indicating how much data was read during the Sram cycle allowing the update of pointers and counters. The dramwrt_seq has initiated an a bank activate command at this point. Once sufficient data has been read from Sram, the dramwrt_seq sequencer issues a write command to the dram starting the burst cycle and computing a checksum as the data passes by. In the typical case, all the required data will be read from Sram before the data is ready to be written to Sram, thus ensuring infrequent wait states on the SDRAM interface. ECC checkbits are also computed by the dramwrt_data block as the data moves out to the SDRAM interface. It is also possible to force ECC errors to any bit position within the data byte or checkbits. The Sram read cycle repeats until the original burst request has been completed at which point the dramwrt_mux prioritizes any remaining requests in preparation for the next burst cycle.
Since the ECC is a 8 bit ECC for a 64 bit word, writes not aligned to a 64 bit boundary will necessitate a read/modify/write cycle. When the dramwrt_ldctrl sequencer detects that a non-aligned write is required, it will generate a request for the read to the dramrd controller. The dramrd controller then returns the read data which is loaded into the write buffers. The dramwrt_ldctrl sequencer can then request the new data from the Sram, proceeding from this point in the same way as for an aligned operation.
Contiguous dram burst cycles are not guaranteed to the dramwrt controller as an algorithm is implemented in the dramif which ensures highest priority to refresh cycles followed by ping-pong access between dram writes and dram reads and then configuration and flash cycles.
FIG. 26 is a timing diagram illustrating how data is written to SDRAM. The dram has been configured for a burst of four with a latency of two clock cycles. Bank A is first selected/activated followed by a write command two clock cycles later. The bank select/activate for bank B is next issued in preparation for issuing the second write command. As soon as the first 4 word burst to bank A completes we issue the write command for bank B and begin supplying data. Banks C and D follow if necessary.
Pci Master-Out Sequencer (Pmo).
The Pmo sequencer (See FIG. 27) acts only as a slave sequencer. Servicing requests issued by master sequencers, the Pmo sequencer moves data from an Sram based fifo to a Pci target, via the PciMstrIO module, in bursts of up to 256 bytes. The nature of the PCI bus dictates the use of the write line command to ensure optimal system performance. The write line command requires that the Pmo sequencer be capable of transferring a whole multiple (1×, 2×, 3×, . . . ) of cache lines of which the size is set through the Pci configuration registers. To accomplish this end, Pmo will automatically perform partial bursts until it has aligned the transfers on a cache line boundary at which time it will begin usage of the write line command. The Sram fifo depth, of 256 bytes, has been chosen in order to allow Pmo to accommodate cache line sizes up to 128 bytes. Provided the cache line size is less than 128 bytes, Pmo will perform multiple, contiguous cache line bursts until it has exhausted the supply of data.
Pmo receives requests from two separate sources; the dram to Pci (D2p) module and the Sram to Pci (S2p) module. An operation (See FIG. 27) first begins with prioritization of the requests where the S2p module is given highest priority. Next, the Pmo module takes a Snapshot of the Sram fifo address and uses this to generate read requests for the SramCtrl sequencer. The Pmo module then proceeds to arbitrate for ownership of the Pci bus via the PciMstrIO module. Once the Pmo holding registers have sufficient data and Pci bus mastership has been granted, the Pmo module begins transferring data to the Pci target. For each successful transfer, Pmo sends an acknowledge and encoded size to the master sequencer, allow it to update it's internal pointers, counters and status. Once the Pci burst transaction has terminated, Pmo parks on the Pci bus unless another initiator has requested ownership. Pmo again prioritizes the incoming requests and repeats the process.
Pci Master-In Sequencer (Pmi).
The Pmi sequencer (See FIG. 28) acts only as a slave sequencer. Servicing requests issued by master sequencers, the Pmi sequencer moves data from a Pci target to an Sram based fifo, via the PciMstrIO module, in bursts of up to 256 bytes. The nature of the PCI bus dictates the use of the read multiple command to ensure optimal system performance. The read multiple command requires that the Pmi sequencer be capable of transferring a cache line or more of data. To accomplish this end, Pmi will automatically perform partial cache line bursts until it has aligned the transfers on a cache line boundary at which time it will begin usage of the read multiple command. The Sram fifo depth, of 256 bytes, has been chosen in order to allow Pmi to accommodate cache line sizes up to 128 bytes. Provided the cache line size is less than 128 bytes, Pmi will perform multiple, contiguous cache line bursts until it has filled the fifo.
Pmi receive requests from two separate sources; the Pci to dram (P2d) module and the Pci to Sram (P2s) module. An operation (See FIG. 28) first begins with prioritization of the requests where the P2s module is given highest priority. The Pmi module then proceeds to arbitrate for ownership of the Pci bus via the PciMstrIO module. Once the Pci bus mastership has been granted and the Pmi holding registers have sufficient data, the Pmi module begins transferring data to the Sram fifo. For each successful transfer, Pmi sends an acknowledge and encoded size to the master sequencer, allowing it to update it's internal pointers, counters and status. Once the Pci burst transaction has terminated, Pmi parks on the Pci bus unless another initiator has requested ownership. Pmi again prioritizes the incoming requests and repeats the process
Dram to Pci Sequencer (D2p).
The D2p sequencer (See FIG. 29) acts is a master sequencer. Servicing channel requests issued by the Cpu, the D2p sequencer manages movement of data from dram to the Pci bus by issuing requests to both the Drd sequencer and the Pmo sequencer. Data transfer is accomplished using an Sram based fifo through which data is staged.
D2p can receive requests from any of the processor's thirty-two dma channels. Once a command request has been detected, D2p fetches a dma descriptor from an Sram location dedicated to the requesting channel which includes the dram address, Pci address, Pci endian and request size. D2p then issues a request to the D2s sequencer causing the Sram based fifo to fill with dram data. Once the fifo contains sufficient data for a Pci transaction, D2s issues a request to Pmo which in turn moves data from the fifo to a Pci target. The process repeats until the entire request has been satisfied at which time D2p writes ending status in to the Sram dma descriptor area and sets the channel done bit associated with that channel. D2p then monitors the dma channels for additional requests. FIG. 29 is an illustration showing the major blocks involved in the movement of data from dram to Pci target.
Pci to Dram Sequencer (P2d).
The P2d sequencer (See FIG. 30) acts as both a slave sequencer and a master sequencer. Servicing channel requests issued by the Cpu, the P2d sequencer manages movement of data from Pci bus to dram by issuing requests to both the Dwr sequencer and the Pmi sequencer. Data transfer is accomplished using an Sram based fifo through which data is staged.
P2d can receive requests from any of the processor's thirty-two dma channels. Once a command request has been detected, P2d, operating as a slave sequencer, fetches a dma descriptor from an Sram location dedicated to the requesting channel which includes the dram address, Pci address, Pci endian and request size. P2d then issues a request to Pmo which in turn moves data from the Pci target to the Sram fifo. Next, P2d issues a request to the Dwr sequencer causing the Sram based fifo contents to be written to the dram. The process repeats until the entire request has been satisfied at which time P2d writes ending status in to the Sram dma descriptor area and sets the channel done bit associated with that channel. P2d then monitors the dma channels for additional requests. FIG. 30 is an illustration showing the major blocks involved in the movement of data from a Pci target to dram.
Sram to Pci Sequencer (S2p).
The S2p sequencer (See FIG. 31) acts as both a slave sequencer and a master sequencer. Servicing channel requests issued by the Cpu, the S2p sequencer manages movement of data from Sram to the Pci bus by issuing requests to the Pmo sequencer
S2p can receive requests from any of the processor's thirty-two dma channels. Once a command request has been detected, S2p, operating as a slave sequencer, fetches a dma descriptor from an Sram location dedicated to the requesting channel which includes the Sram address, Pci address, Pci endian and request size. S2p then issues a request to Pmo which in turn moves data from the Sram to a Pci target. The process repeats until the entire request has been satisfied at which time S2p writes ending status in to the Sram dma descriptor area and sets the channel done bit associated with that channel. S2p then monitors the dma channels for additional requests. FIG. 31 is an illustration showing the major blocks involved in the movement of data from Sram to Pci target.
Pci To Sram Sequencer (P2s).
The P2s sequencer (See FIG. 32) acts as both a slave sequencer and a master sequencer. Servicing channel requests issued by the Cpu, the P2s sequencer manages movement of data from Pci bus to Sram by issuing requests to the. Pmi sequencer.
P2s can receive requests from any of the processor's thirty-two dma channels. Once a command request has been detected, P2s, operating as a slave sequencer, fetches a dma descriptor from an Sram location dedicated to the requesting channel which includes the Sram address, Pci address, Pci endian and request size. P2s then issues a request to Pmo which in turn moves data from the Pci target to the Sram. The process repeats until the entire request has been satisfied at which time P2s writes ending status in to the dma descriptor area of Sram and sets the channel done bit associated with that channel. P2s then monitors the dma channels for additional requests. FIG. 32 is an illustration showing the major blocks involved in the movement of data from a Pci target to dram.
Dram to Sram Sequencer (D2s).
The D2s sequencer (See FIG. 33) acts as both a slave sequencer and a master sequencer. Servicing channel requests issued by the Cpu, the D2s sequencer manages movement of data from dram to Sram by issuing requests to the Drd sequencer.
D2s can receive requests from any of the processor's thirty-two dma channels. Once a command request has been detected, D2s, operating as a slave sequencer, fetches a dma descriptor from an Sram location dedicated to the requesting channel which includes the dram address, Sram address and request size. D2s then issues a request to the Drd sequencer causing the transfer of data to the Sram. The process repeats until the entire request has been satisfied at which time D2s writes ending status in to the Sram dma descriptor area and sets the channel done bit associated with that channel. D2s then monitors the dma channels for additional requests. FIG. 33 is an illustration showing the major blocks involved in the movement of data from dram to Sram.
Sram to Dram Sequencer (S2d).
The S2d sequencer (See FIG. 34) acts as both a slave sequencer and a master sequencer. Servicing channel requests issued by the Cpu, the S2d sequencer manages movement of data from Sram to dram by issuing requests to the Dwr sequencer.
S2d can receive requests from any of the processor's thirty-two dma channels. Once a command request has been detected, S2d, operating as a slave sequencer, fetches a dma descriptor from an Sram location dedicated to the requesting channel which includes the dram address, Sram address, checksum reset and request size. S2d then issues a request to the Dwr sequencer causing the transfer of data to the dram. The process repeats until the entire request has been satisfied at which time S2d writes ending status in to the Sram dma descriptor area and sets the channel done bit associated with that channel. S2d then monitors the dma channels for additional requests. FIG. 34 is an illustration showing the major blocks involved in the movement of data from Sram to dram.
Pci Slave Input Sequencer (Psi).
The Psi sequencer (See FIG. 35) acts as both a slave sequencer and a master sequencer. Servicing requests issued by a Pci master, the Psi sequencer manages movement of data from Pci bus to Sram and Pci bus to dram via Sram by issuing requests to the SramCtrl and Dwr sequencers.
Psi manages write requests to configuration space, expansion rom, dram, Sram and memory mapped registers. Psi separates these Pci bus operations in to two categories with different action taken for each. Dram accesses result in Psi generating write request to an Sram buffer followed with a write request to the Dwr sequencer. Subsequent write or read dram operations are retry terminated until the buffer has been emptied. An event notification is set for the processor allowing message passing to occur through dram space.
All other Pci write transactions result in Psi posting the write information including Pci address, Pci byte marks and Pci data to a reserved location in Sram, then setting an event flag which the event processor monitors. Subsequent writes or reads of configuration, expansion rom, Sram or registers are terminated with retry until the processor clears the event flag. This allows Mojave to keep pipelining levels to a minimum for the posted write and give the processor ample time to modify data for subsequent Pci read operations.
FIG. 35 depicts the sequence of events when Psi is the target of a Pci write operation. Note that events 4 through 7 occur only when the write operation targets the dram.
Pci Slave Output Sequencer (Pso).
The Pso sequencer (See FIG. 36) acts as both a slave sequencer and a master sequencer. Servicing requests issued by a Pci master, the Pso sequencer manages movement of data to Pci bus form Sram and to Pci bus from dram via Sram by issuing requests to the SramCtrl and Drd sequencers.
Pso manages read requests to configuration space, expansion rom, dram, Sram and memory mapped registers. Pso separates these Pci bus operations in to two categories with different action taken for each. Dram accesses result in Pso generating read request to the Drd sequencer followed with a read request to Sram buffer. Subsequent write or read dram operations are retry terminated until the buffer has been emptied.
All other Pci read transactions result in Pso posting the read request information including Pci address and Pci byte marks to a reserved location in Sram, then setting an event flag which the event processor monitors. Subsequent writes or reads of configuration, expansion rom, Sram or registers are terminated with retry until the processor clears the event flag. This allows Mojave to use a microcoded response mechanism to return data for the request. The processor decodes the request information, formulates or fetches the requested data and stores it in Sram then clears the event flag allowing Pso to fetch the data and return it on the Pci bus.
FIG. 36 depicts the sequence of events when Pso is the target of a Pci read operation.
Frame Receive Sequencer (RcvX).
The receive sequencer (RcvSeq)(See FIG. 37) analyzes and manages incoming packets, stores the result in dram buffers or sram buffers, then notifies the processor through the receive queue (RcvQ) mechanism. The process begins when a buffer descriptor is available at the output of the FreeQ (1). RcvSeq issues a request to the Qmg (2) which responds by supplying the buffer descriptor to RcvSeq (3). RcvSeq then waits for a receive packet (4). The Mac, network, transport and session information is analyzed as each byte is received (4) and stored in the assembly register (AssyReg). When sixteen bytes of information is available, RcvSeq requests a write of the data to the Sram (5). In normal mode, when sufficient data has been stored in the Sram based receive fifo, a Dram write request is issued to Dwr (8). The process continues until the entire packet has been received at which point RcvSeq stores the results of the packet analysis in the beginning of the receive buffer. Once the buffer and status have both been stored, RcvSeq issues a write-queue request to Qmg (12) using a QId based on the priority level of the incoming packet detected by RcvSeq. Qmg responds by storing a buffer descriptor (15) and, in normal mode, a status vector provided by RcvSeq (13). When QHashEn is set, RcvSeq will merge the CtxHash with the receive descriptor. The process then repeats. If RcvSeq detects the arrival of a packet before a free buffer is available, it ignores the packet and sets the PktMissed status bit for the next received packet.
FIG. 37 depicts the sequence of events for successful reception of a packet. FIG. 39 is a definition of the receive buffer. FIG. 40 is a definition of the receive buffer descriptor as stored on the RcvQ. FIG. 41 is a diagram that illustrates a receive vector.
Receive Priorities.
The receive sequencer (See FIG. 37) analyzes the vlan priorities of the incoming packets, and stores the receive descriptor in one of it's receive queues according to the value written to the PriLevels bits of the RcvCfg register as represented in FIG. 38. Rev. A of Mojave has a bug which limits receive queues to 0 and 1.
Frame Transmit Sequencer (XmtX).
The transmit sequencer (XmtSeq)(See FIG. 42) manages outgoing packets, using buffer descriptors retrieved from, in order of priority, the urgent descriptor register (XmtUrgDscr) followed by the transmit queues (XmtQ) priority 3 down to priority 0, then storing the descriptor for the freed buffer in the free buffer queue (FreeQ). The process begins when a buffer descriptor is available at, for example, the output of XmtQ2 (1). XmtSeq issues a request to the Qmg (2) which responds by supplying the buffer descriptor to XmtSeq (4). XmtSeq then issues a read request to the Drd (5) sequencer. Next, XmtSeq issues a read request to SramCtrl (6) then instructs the Mac (10) to begin frame transmission. Once the frame transmission has completed, XmtSeq stores the buffer descriptor on the FreeQ (12) thereby recycling the buffer. If XmtSeq detects a data-late condition or a collision, the packet is retransmitted automatically.
FIG. 42 depicts the sequence of events for successful transmission of a packet. FIG. 43 is a diagram of the transmit descriptor. FIG. 44 is a diagram of the merge descriptor. FIG. 45 is a diagram of the transmit beffer format. FIG. 46 is a diagram of the transmit vector.
Queue Manager (Qmg).
Mojave includes special hardware assist for the implementation of message and pointer queues. The hardware assist is called the queue manager (Qmg) (See FIG. 47) and manages the movement of queue entries between Cpu and Sram, between Xcv sequencers and Sram as well as between Sram and Dram. Queues comprise three distinct entities; the queue head (QHd), the queue tail (QTl) and the queue body (QBdy). QHd resides in 64 bytes of scratch ram and provides the area to which entries will be written (pushed). QTl resides in 64 bytes of scratch ram and contains queue locations from which entries will be read (popped). QBdy resides in dram and contains locations for expansion of the queue in order to minimize the Sram space requirements. The QBdy size depends upon the queue being accessed and the initialization parameters presented during queue initialization.
Qmg (See FIG. 47) accepts operation requests from both Cpu, XcvSeqs and DmaSeqs. Executing these operations at a frequency of 100 Mhz. Valid Cpu operations include initialize queue (InitQ), write queue (WrQ) and read queue (RdQ). Valid dma requests include read queue (RdQ), read body (RdBdy) and write body (WrBdy). Qmg working in unison with Q2d and D2q generate requests to the Dwr and Drd sequencers to control the movement of data between the QHd, QTl and QBdy.
There are a total of 32 queues. The first 8 are dedicated to a specific function as shown in FIG. 48.
FIG. 47 shows the major functions of Qmg. The arbiter selects the next operation to be performed. The dual-ported Sram holds the queue variables HdWrAddr, HdRdAddr, TlWrAddr, TlRdAddr, BdyWrAddr, BdyRdAddr and QSz. Qmg accepts an operation request, fetches the queue variables from the queue ram (Qram), modifies the variables based on the current state and the requested operation then updates the variables and issues a read or write request to the Sram controller. The Sram controller services the requests by writing the tail or reading the head and returning an acknowledge.
Dma Operations.
DMA operations are accomplished by seven dma sequencers (DmaSeq). Commands are sent to these sequencers via hardware queues. The queue Ids are fixed in hardware and are as shown in FIG. 49.
Microcode will initiate a DMA by writing a command to the appropriate queue. The DMA sequencer will read a command from the queue, and fetch the descriptor block from Sram. It will then do the DMA. At the end of the DMA, if the DMA chain bit is not set, the DMA sequencer will terminate the DMA.
For DMAs that complete without error, the DMA Context byte (bits 31:24 of the command) will be written to the termination queue indicated by bits 20:16 of the command. Each entry in the termination queue is 32 bits, but only the least significant 8 bits (7:0) are used and wriiten with the DMA Context.
For DMAs that complete with error, the termination queue will not be written. Instead a bit in the DMA Error Register will be set. This is a 32 bit register and the least significant 5 bits of the DMA context will be used to decide which bit should be written in the following manner:
DMA Error Register [1<<DMA command [28:24]]=1;
If the Dummy DMA bit is set, no DMA is performed but the DMA context is written directly to the DMA termination queue.
If the DMA chain bit is set and the DMA completes without error, the DMA descriptor block is updated, but no other termination information is written. If the DMA chain bit is set and the DMA completes with an error, the DMA descriptor block is updated, and the error is propogated to subsequent DMA commands until the sequencer finds one that does not have the chain bit, when the DMA Error Register will be written as above, without writing to the termination queue.
The format of the P2d or P2s descriptor is shown in FIG. 50.
The format of the S2p or D2p descriptor is shown in FIG. 51.
The format of the S2d, D2d or D2s descriptor is shown in FIG. 52.
The format of the ending status of any dma is as shown in FIG. 53.
FIG. 54 shows the major blocks of PCI logic and their relationships. The blocks of FIG. 54 are as follows:
Slave Dram Interface: This block controls the interface to Dram when Dram is being accessed directly by the host or by another PCI master.
Slave Sram Interface: This block controls the the access to Sram for PCI slave accesses to read Sram, or to read or write Dram.
Pci Configuration Registers: This block contains the configuration registers that control the PCI space.
DMA Master In: This block does PCI master transfers on behalf of the P2D and P2S DMA sequencers. There is synchronization logic to synchronize between the PCI bus and the SRAM which are being clcoked by different clocks. It has 256 bytes of buffering to minimize latencies caused by this synchronization.
DMA Master Out: This block does PCI master transfers on behalf of the D2P and S2P DMA sequencers. There is synchronization logic to synchronize between the PCI bus and the SRAM which are being clcoked by different clocks. It has 256 bytes of buffering to minimize latencies caused by this synchronization.
PCI Slave Interface: This block has the state machine for PCI slave accesses to Mojave, from the host or from another PCI master.
PCI Parity: This block generates and checks parity on the PCI bus.
PCI Master Interface: This block has the state machine for PCI master accesses to host memory or to another PCI slave, done on behalf of the DMA sequencers.

## Claims

1. A system, comprising:
(a) fast-path receive circuitry that is in control of a first plurality of TCP/IP connections, a first TCP/IP packet associated with one of the first plurality of TCP/IP connections being received onto the fast-path circuitry from a network, the fast-path receive circuitry comprising:
an SRAM that stores a control block (CB) for each TCP/IP connection of a first set of the first plurality of TCP/IP connections;
a DRAM that stores a CB for each TCP/IP connection of a second set of the first plurality of TCP/IP connections, the DRAM storing a CB associated with the first TCP/IP packet received onto the fast-path receive circuitry;
a content addressable memory (CAM); and
a first processor that executes a receive state machine, the first processor obtaining from the CAM information to determine whether the CB associated with the first TCP/IP packet is stored in the SRAM or is stored in the DRAM, the first processor using the information obtained from the CAM to access the CB;
wherein the fast-path receive circuitry uses a plurality of hash buckets to identify control blocks (CBs) associated with a plurality of incoming TCP/IP packets, some of the plurality of hash buckets being cached in the SRAM, others of the hash buckets being stored in DRAM; and

(b) a processor that executes a protocol processing stack, the protocol processing stack being in control of a second plurality of TCP/IP connections, wherein TCP/IP packets associated with the second plurality of TCP/IP connections are received onto the fast-path circuitry from the network, the protocol processing stack performing TCP protocol processing on the TCP/IP packets associated with the second plurality of TCP/IP connections, and wherein other TCP/IP packets associated with the first plurality of TCP/IP connections are received onto the fast-path circuitry from the network, the protocol stack performing substantially no TCP protocol processing on the other TCP/IP packets associated with the second plurality of TCP/IP connections.

2. The system of claim 1, wherein the first processor accesses the CB associated with the first TCP/IP packet by causing the CB associated with the first TCP/IP racket to be copied from the DRAM into the SRAM.

3. The system of claim 1, wherein the fast-path receive circuitry generates a hash for the first TCP/IP packet, and wherein the fast-path receive circuitry pushes the hash onto a queue, the first processor popping the queue and thereby obtaining the hash, the first processor then using the hash to identify the control block (CB) associated with the first TCP/IP packet.

4. The system of claim 1, wherein the SRAM includes a plurality of control block (CB) slots, and wherein the CAM contains a CAM entry for each of the CB slots in the SRAM.

5. The system of claim 1, wherein the control block (CB) associated with the first TCP/IP packet contains TCP state information.

6. The system of claim 1, wherein the control block (CB) associated with the first TCP/IP packet is a communication control block (CCB).

7. The system of claim 1, wherein the control block (CB) associated with the first TCP/IP packet is a transmit control block (TCB), the TCB comprising: TCP state information, a TCP source port address, a TCP destination port address, an P source address, and an P destination address.

8. The system of claim 1, wherein the fast-path receive circuitry further comprises:
a second processor that executes the receive state machine, the first processor and the second processor together performing TCP protocol processing and IP protocol processing on the first TCP/IP packet.

9. The system of claim 8, wherein one of the first and second processors performs initial processing on the first TCP/IP packet using the receive state machine and then stops processing the first TCP/IP packet and stores state information relating to a state of the receive state machine, and wherein the other the first and second processors retrieves the state information and uses the retrieved state information to perform subsequent processing on the first TCP/IP packet using the receive state machine.

10. The system of claim 1, wherein the first TCP/IP packet has an associated hash bucket, wherein if the associated hash bucket is stored in DRAM, then the associated hash bucket is copied into the SRAM, the associated hash bucket having a hash bucket entry, the first processor checking the hash bucket entry to determine whether TCP and IP fields of the hash bucket entry match TCP and IP fields of the first TCP/IP packet.

11. The system of claim 1, wherein the fast-path receive circuitry further comprises:
a plurality of lock bits, there being one lock bit for each of the first plurality of TCP/IP connections controlled by the fast-path receive circuitry, a lock bit indicating whether a control block (CB) associated with the lock bit has been locked by a processor context;
a lock table CAM; and
a lock table, wherein the lock table and the lock table CAM are used to identify a processor context that is waiting to gain control of the control block (CB) associated with the first TCP/IP racket.

12. The system of claim 11, wherein the lock table contains a plurality of entries, each entry identifying one of a plurality of processor contexts.

13. The system of claim 1, wherein each CB of the second set of the first plurality of TCP/IP connections is also stored in the SRAM.

14. The system of claim 1, further comprising a host CPU, the fast-path receive circuitry (a) and the processor (b) being part of a network interface device, the network interface being coupled to the host CPU.

15. The system of claim 1, wherein the fast-path receive circuitry (a) is part of a network interface device, and wherein the processor (b) is a host CPU, the network interface device being coupled to the host CPU.

16. A system, comprising:
a first processor that executes a protocol processing stack; and
fast-path receive circuitry that receives an incoming TCP/IP packet and performs substantially all TCP and IP protocol processing on the TCP/IP packet, the TCP/IP packet containing a header portion and a data portion, the data portion being transferred into a destination identified by the first processor, the data portion being transferred without the header portion being transferred into the destination and without the protocol processing stack doing any TCP protocol processing on the TCP/IP packet, the fast-path receive circuitry comprising:
an SRAM that stores a first plurality of control blocks (CB);
a DRAM that stores a second plurality of control blocks (CB);
a content addressable memory (CAM); and
a second processor that executes a receive state machine, the second processor using the CAM to determine whether a control block (CB) associated with the incoming TCP/IP packet is stored in the SRAM, wherein if the control block is not stored in the SRAM but rather is stored in the DRAM, then the second processor causes the control block (CB) associated with the incoming TCP/IP packet to be copied into the SRAM;
wherein the fast-path receive circuitry uses a plurality of hash buckets to identify control blocks (CBs) associated with incoming TCP/IP packets, some of the plurality of hash buckets being cached in the SRAM, others of the hash buckets being stored in DRAM.

17. The system of claim 16, wherein the incoming TCP/IP packet is associated with a TCP/IP connection, wherein control of the TCP/IP connection is passed from the first processor to the fast-path receive circuitry.

18. The system of claim 17, wherein control of the TCP/IP connection is passed to the fast-path receive circuitry by passing control of an associated control block (CB) to the fast-path receive circuitry.

19. A method, comprising:
receiving a TCP/IP packet onto a network interface device;
generating a hash from the TCP/IP packet and pushing the hash onto a queue, the queue being located on the network interface device;
popping the queue to retrieve the hash and using the hash to identify a hash bucket;
determining that the hash bucket identified by the hash is stored in a DRAM and copying the hash bucket from the DRAM and into an SRAM, the DRAM and the SRAM both being part of the network interface device;
searching a plurality of hash entries in the identified hash bucket and determining from one of the hash entries a control block number;
using a content addressable memory (CAM) to determine that a control block (CB) associated with the control block number is located in the DRAM, the CAM being part of the network interface device;
copying the control block (CB) from the DRAM and into the SRAM; and
using the control block (CB) to fast-path process the TCP/IP packet on the network interface device, the network interface device transferring a data portion of the TCP/IP packet into a destination, the destination having been identified by a processor, the processor executing a protocol processing stack, the network interface device transferring the data portion into the destination identified by the processor without the protocol processing stack of the processor performing any TCP protocol processing on the TCP/IP packet.

20. The method of claim 19, wherein the processor is a CPU of a host computer, the network interface device being coupled to the host computer, the destination being located in a memory of the host computer.

21. The method of claim 19, wherein the processor is a part of the network interface device.