# Patent

## Title
Gated diode nonvolatile memory operation

## Abstract

A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

## Background
REFERENCE TO RELATED APPLICATION
This application claims the benefit of U.S. Provisional Patent Application No. 60/866,583, filed on 20 Nov. 2006, by inventors Tien-Fan Ou, Wen-Jer Tsai, Erh-Kun Lai, Hsuan-Ling Kao and Yi Ying Liao entitled Gated Diode Nonvolatile Memory.


BACKGROUND
1. Field
The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge storage memory with a bias arrangement that reads the contents of the charge storage structure of the memory cell with great sensitivity.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Various memory cell structures based on charge trapping dielectric layers include structures known by the industry names PHINES, NROM, and SONOS, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As more net negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from, or adding positive charge to, the charge trapping layer.
Conventional memory cell structures rely on a transistor structure with source, drain, and gate. However, common transistor structures have drain and source diffusions that are laterally separated from each other by a self-aligned gate. This lateral separation is a factor that resists further miniaturization of nonvolatile memory.
Thus, a need exists for a nonvolatile memory cell that is open to further miniaturization and whose contents can be read with great sensitivity.
SUMMARY
One aspect of the technology is a method of operating a nonvolatile memory device integrated circuit, such as an integrated circuit comprising a charge storage structure, and one or more storage dielectric structures at least partly between the charge storage structure and a diode structure and at least partly between the charge storage structure and a source of gate voltage. The diode structure has a first node and a second node separated by a diffusion barrier junction. Various method embodiments include the following steps:

    
    
        applying a first bias arrangement to determine a charge storage state of the charge storage structure. The first node and the second node of the diode structure are at least partly adjacent to the one or more storage dielectric structures, and the diode structure has a cross-section in which the second node has opposite sides isolated from neighboring devices by isolation dielectric.
        measuring current flowing through at least the diffusion barrier junction separating the first node and the second node of the diode structure, in reverse bias, to determine the charge storage state of the charge storage structure.
    
    


The first bias arrangement causes a first voltage difference between the source of gate voltage and the second node, and a second voltage difference between the first node and the second node. In some embodiments, the first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for measuring the current flowing through at least the diffusion barrier junction to determine the charge storage state of the charge storage structure. The first voltage difference and the second voltage difference fail to change the charge storage state of the charge storage structure. In some embodiments, the first voltage difference is at least about 10 V between the gate and the second node, and the second voltage difference is more than about 2 V between the first node and the second node.
In some embodiments, any hot charge carriers generated during the first bias arrangement fail to change the charge storage state of the charge storage structure.
Some embodiments further include the steps of:

    
    
        applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure. Some example mechanisms are band-to-band hot hole tunneling, Fowler-Nordheim tunneling, hole movement between the charge storage structure and the diode structure, hole movement between the charge storage structure and the gate.
        applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure. Some example mechanisms are Fowler-Nordheim tunneling, band-to-band hot electron tunneling, electron movement between the charge storage structure and the diode structure, band-to-band hot electron tunneling, electron movement between the charge storage structure and the gate.
    
    


Some embodiments further include the step of programming the charge storage state of the charge storage structure to store one bit or multiple bits.
Another aspect of the technology is a method of operating an array of nonvolatile memory storage devices described herein. Various method embodiments comprise the steps of:

    
    
        applying a first bias arrangement to determine at least one charge storage state of one or more of the charge storage structures of the array, wherein the first node and the second node of one or more diode structures of the array are at least partly adjacent to the one or more storage dielectric structures, and the one or more diode structures have a cross-section in which the second node has opposite sides isolated from neighboring devices by isolation dielectric; and
        measuring current flowing through at least one of the diffusion barrier junctions separating the first node and the second node of the one or more diode structures, in reverse bias, to determine the charge storage state of the one or more charge storage structures.
    
    


Other embodiments cover variations discussed herein with respect to operating individual memory cells.
Yet another aspect of the technology is a method of operating an array of nonvolatile memory storage devices described herein. Various method embodiments comprise the steps of:
A further aspect of the technology is a method of operating an array of nonvolatile memory storage devices. The array comprises a plurality of diode columns each including a first node column and a second node column separated by a diffusion barrier junction. Opposite sides of the second node column are isolated from neighboring columns by isolation dielectric. A plurality of gate rows overlap the plurality of diode columns. A plurality of nonvolatile storage structures are each located at a particular intersection between a particular diode column of the plurality of diode columns and a particular gate row of the plurality of gate rows. Each nonvolatile storage structure of the plurality of nonvolatile storage structures includes a charge storage structure and one or more storage dielectric structures at least partly between the charge storage structure and the particular diode column, at least partly between the charge storage structure and the particular gate row, and at least partly adjacent to the first node column and the second node column of the particular diode column at the particular intersection. Various embodiments of the method include the steps of:

    
    
        applying a first bias arrangement to determine at least one charge storage state of one or more of the charge storage structures of the array. The first node column and the second node column of one or more diode columns of the array intersecting the one or more of the charge storage structures at one or more intersections are at least partly adjacent to the one or more storage dielectric structures at the one or more intersections. The one or more diode columns have cross-sections in which the second node column has opposite sides isolated from neighboring devices by isolation dielectric.
        measuring current flowing through at least one of the diffusion barrier junctions separating the first nodes and the second nodes of the one or more diode columns, in reverse bias, to determine at least one charge storage state of the one or more charge storage structures of the array.
    
    


In some embodiments, the first bias arrangement causes a first voltage difference between one or more gate rows of the plurality of gate rows and one or more second node columns of the array, and a second voltage difference between the first node and the second node of the array. The first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for the measuring, and the first voltage difference and the second voltage difference fail to change the charge storage state of the one or more charge storage structures at the one or more intersections.
In some embodiments the first bias arrangement induces at least a band-to-band current component through the one or more diode columns.
Further embodiments cover variations described herein.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified diagram of a gated diode nonvolatile memory cell.
FIGS. 2A, 2B, and 2C are simplified diagrams of a gated diode nonvolatile memory cell, showing various charge storage structures having different materials.
FIGS. 3A, 3B, 3C, and 3D are simplified diagrams of a gated diode nonvolatile memory cell, showing various examples of a diode structure, such as the pn diode and the Schottky diode.
FIGS. 4A and 4B are simplified diagrams of a gated diode nonvolatile memory cell, showing examples of a pn diode with a homojunction.
FIG. 5 is a simplified diagram of a gated diode nonvolatile memory cell, showing an example of a pn diode with a heterojunction.
FIGS. 6A and 6B are simplified diagrams of a gated diode nonvolatile memory cell operation performing electron tunnel injection.
FIGS. 7A and 7B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band hot electron injection.
FIGS. 8A and 8B are simplified diagrams of a gated diode nonvolatile memory cell operation performing hole tunnel injection.
FIGS. 9A and 9B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band hot hole injection.
FIGS. 10A and 10B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure.
FIGS. 11A and 11B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure, but with a different diode node arrangement than in FIGS. 10A and 10B.
FIGS. 12A and 12B are simplified diagrams of neighboring gated diode nonvolatile memory cells, with and without interconnected second nodes.
FIGS. 13A and 13B are simplified diagrams of an array of gated diode nonvolatile memory cells with interconnected second node columns, performing band-to-band sensing.
FIGS. 14A and 14B are simplified diagrams of an array of gated diode nonvolatile memory cells without interconnected second node columns, performing band-to-band sensing.
FIGS. 15A and 15B are simplified diagrams of an array of gated diode nonvolatile memory cells with interconnected second node columns, performing band-to-band sensing, where the doping arrangement of the diode structures is different from FIGS. 13A, 13B, 14A, and 14B.
FIGS. 16A and 16B are simplified diagrams of an array of gated diode nonvolatile memory cells without interconnected second node columns, performing band-to-band sensing, where the doping arrangement of the diode structures is different from FIGS. 13A, 13B, 14A, and 14B.
FIGS. 17A, 17B, and 17C are simplified diagrams of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which electron tunnel injection is performed on selected cells.
FIGS. 18A, 18B, and 18C are simplified diagrams of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band hot hole injection is performed on selected cells.
FIGS. 19A, 19B, and 19C are exploded view diagrams of multiple arrays of gated diode nonvolatile memory cells, with different interconnections of the word lines, first node columns, and second node columns, between different arrays.
FIG. 20 is a simplified diagram of an integrated circuit with an array of gated diode nonvolatile memory cells and control circuitry.
FIGS. 21A-21H illustrate a sample process flow for multiple arrays of gated diode nonvolatile memory cells.
FIGS. 22A and 22B are simplified diagrams of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band sensing is performed on selected cells.
FIGS. 23A-23H illustrate a sample process flow for an array of gated diode nonvolatile memory cells.
FIG. 24 is a perspective view of an array of gated diode nonvolatile memory cells as formed by the process of FIGS. 23A-23H.
FIG. 25 is similar to the simplified diagram in FIG. 1 of a gated diode nonvolatile memory cell, but adds a diffusion barrier junction to the diode structure.
FIGS. 26A, 26B, and 26C are similar to the simplified diagrams in FIGS. 2A, 2B, and 2C of a gated diode nonvolatile memory cell, showing various charge storage structures having different materials, but add a diffusion barrier junction to the diode structure.
FIGS. 27A, 27B, 27C, and 27D are similar to the simplified diagrams in FIGS. 3A, 3B, 3C, and 3D of a gated diode nonvolatile memory cell, showing various examples of a diode structure, such as the pn diode and the Schottky diode, but add a diffusion barrier junction to the diode structure.
FIGS. 28A and 28B are similar to the simplified diagrams in FIGS. 4A and 4B of a gated diode nonvolatile memory cell, showing examples of a pn diode with a homojunction, but add a diffusion barrier junction to the diode structure.
FIG. 29 is similar to the simplified diagram in FIG. 5 of a gated diode nonvolatile memory cell, showing an example of a pn diode with a heterojunction, but adds a diffusion barrier junction to the diode structure.
FIGS. 30A to 30F illustrate another sample process flow for an array of gated diode nonvolatile memory cells.
FIGS. 31A-31I illustrate a sample process flow for an array of gated diode nonvolatile memory cells with a diffusion barrier junction in the diode structures.
FIG. 32 is a perspective view of an array of gated diode nonvolatile memory cells with a diffusion barrier junction in the diode structures as formed by the process of FIGS. 31A-31H.
FIGS. 33A and 33B are similar to the simplified diagrams in FIGS. 6A and 6B of a gated diode nonvolatile memory cell operation performing electron tunnel injection, but add a diffusion barrier junction to the diode structure.
FIGS. 34A and 34B are similar to the simplified diagrams in FIGS. 7A and 7B of a gated diode nonvolatile memory cell operation performing band-to-band hot electron injection, but add a diffusion barrier junction to the diode structure.
FIGS. 35A and 35B are similar to the simplified diagrams in FIGS. 8A and 8B of a gated diode nonvolatile memory cell operation performing hole tunnel injection, but add a diffusion barrier junction to the diode structure.
FIGS. 36A and 36B are similar to the simplified diagrams in FIGS. 9A and 9B of a gated diode nonvolatile memory cell operation performing band-to-band hot hole injection, but add a diffusion barrier junction to the diode structure.
FIGS. 37A and 37B are similar to the simplified diagrams in FIGS. 10A and 10B of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure, but add a diffusion barrier junction to the diode structure.
FIGS. 38A and 38B are similar to the simplified diagrams in FIGS. 11A and 11B of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure, but add a diffusion barrier junction to the diode structure, and have a different diode node arrangement than in FIGS. 37A and 37B.
FIGS. 39A and 39B are similar to the simplified diagrams in FIGS. 12A and 12B of neighboring gated diode nonvolatile memory cells, with and without interconnected second nodes, but add a diffusion barrier junction to the diode structure.
FIGS. 40A and 40B are similar to the simplified diagrams in FIGS. 17A and 17B of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which electron tunnel injection is performed on selected cells, but add a diffusion barrier junction to the diode structure.
FIGS. 41A, 41B and 41C are similar to the simplified diagrams in FIGS. 18A, 18B, and 18C of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band hot hole injection is performed on selected cells, but add a diffusion barrier junction to the diode structure.
FIGS. 42A and 42B are similar to the simplified diagrams in FIGS. 22A and 22B of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band sensing is performed on selected cells, but add a diffusion barrier junction to the diode structure.
FIGS. 43A and 43B are graphs comparing the doping profiles of diode structures with and without a diffusion barrier junction.
FIGS. 44A and 44B are graphs comparing the doping profiles of diode structures with and without a diffusion barrier junction, under different thermal budget conditions.



DETAILED DESCRIPTION
FIG. 1 is a simplified diagram of a gated diode nonvolatile memory cell. Nodes 102 and 104 form a diode separated by a junction. A combined charge storage and dielectric structure 106 substantially surrounds the first diode node 102. The combined charge storage and dielectric structure 106 is also partly adjacent to the second diode node 104. In this cross-sectional view, dielectric 110 on either side of the second diode node 104 isolates the second diode node 104 from neighboring devices, such as other gated diode nonvolatile memory cells.
FIG. 25 is similar to the simplified diagram in FIG. 1 of a gated diode nonvolatile memory cell, but adds a diffusion barrier junction to the diode structure.
FIGS. 2A, 2B, and 2C are simplified diagrams of a gated diode nonvolatile memory cell, showing various charge storage structures having different materials. In FIG. 2A, a charge trapping material structure 202 locally stores charge, schematically shown here as positive charge on the portion of the charge trapping material near the diode junction. Oxide structures are between the charge trapping material structure 202 and the gate structure, and between the charge trapping material structure 202 and the diode structure. Representative dielectrics between the charge trapping material structure 202 and the gate structure include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al2O3. Representative between the charge trapping material structure 202 and the diode structure include silicon dioxide and silicon oxynitride having a thickness of about 2 to 10 nanometers, or other similar high dielectric constant materials.
Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al2O3, HfO2, and others.
In some embodiments, the gate structure comprises a material having a work function greater than the intrinsic work function of n-type silicon, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including for example greater than about 5 eV. Representative gate materials include p-type poly, TiN, Pt, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to Ru, Ir, Ni, and Co, metal alloys including but not limited to Ru—Ti and Ni-T, metal nitrides, and metal oxides including but not limited to RuO2. High work function gate materials result in higher injection barriers for electron tunneling than that of the typical n-type polysilicon gate. The injection barrier for n-type polysilicon gates with silicon dioxide as the outer dielectric is around 3.15 eV. Thus, embodiments of the present technology use materials for the gate and for the outer dielectric having an injection barrier higher than about 3.15 eV, such as higher than about 3.4 eV, and preferably higher than about 4 eV. For p-type polysilicon gates with silicon dioxide outer dielectrics, the injection barrier is about 4.25 eV, and the resulting threshold of a converged cell is reduced about 2 volts relative to a cell having an n-type polysilicon gate with a silicon dioxide outer dielectric.
FIG. 2B shows a gated diode nonvolatile memory cell resembling the gated diode nonvolatile memory cell of FIG. 2A, but with a floating gate 204, often made of polysilicon. FIG. 2C shows a gated diode nonvolatile memory cell resembling the nonvolatile memory cell of FIG. 2A, but with a nanoparticle charge storage structure 206.
Each charge storage structure can store one bit or multiple bits. For example, if each charge storage structure stores two bits, then there are four discrete levels of charge stored by the gated diode nonvolatile memory cell.
In some embodiments, programming refers to making more positive the net charge stored in the charge trapping structure, such as by the addition of holes to or the removal of electrons from the charge storage structure; and erasing refers to making more negative the net charge stored in the charge storage structure, such as by the removal of holes from or the addition of electrons to the charge trapping structure. However, in other embodiments programming refers to making the net charge stored in the charge storage structure more negative, and erasing refers to making the net charge stored in the charge storage structure more positive. Various charge movement mechanisms are used, such as band-to-band tunneling induced hot carrier injection, E-field induced tunneling, and direct tunneling from the substrate.
FIGS. 26A, 26B, and 26C are similar to the simplified diagrams in FIGS. 2A, 2B, and 2C of a gated diode nonvolatile memory cell, showing various charge storage structures having different materials, but add a diffusion barrier junction to the diode structure.
FIGS. 3A, 3B, 3C, and 3D are simplified diagrams of a gated diode nonvolatile memory cell, showing various examples of a diode structure, such as the pn diode and the Schottky diode. In FIGS. 3A and 3B, the diode structure is a pn diode. In FIG. 3A, the first node 302 substantially surrounded by the combined charge storage and dielectric structure is doped n-type, and the second node 304 is doped p-type. The gated diode nonvolatile memory cell of FIG. 3B interchanges the node materials of FIG. 3A, such that the first node 312 substantially surrounded by the combined charge storage and dielectric structure is doped p-ty pe, and the second node 314 is doped n-type. In FIGS. 3C and 3D, the diode structure is a Schottky diode. In FIG. 3C, the first node 322 substantially surrounded by the combined charge storage and dielectric structure is a metal material, and the second node 324 is a semiconductor material. The gated diode nonvolatile memory cell of FIG. 3D interchanges the node materials of FIG. 3C, such that the first node 332 substantially surrounded by the combined charge storage and dielectric structure is a semiconductor material, and the second node 334 is a metal material.
FIGS. 27A, 27B, 27C, and 27D are similar to the simplified diagrams in FIGS. 3A, 3B, 3C, and 3D of a gated diode nonvolatile memory cell, showing various examples of a diode structure, such as the pn diode and the Schottky diode, but add a diffusion barrier junction to the diode structure.
FIGS. 4A and 4B are simplified diagrams of a gated diode nonvolatile memory cell, showing examples of a pn diode with a homojunction. In FIG. 4A, both the first node 402 and the second 404 of the diode structure are silicon. In FIG. 4B, both the first node 412 and the second 414 of the diode structure are germanium. Because of the smaller bandgap of germanium compared to silicon, the gated diode nonvolatile memory cell tends to generate a greater band-to-band current with the configuration of FIG. 4B than with the configuration of FIG. 4A. Regardless of the material used in the homojunction diode structure, the diode structure can be single crystal or polycrystalline. A polycrystalline design results in higher memory cell density, due to the ability to deposit multiple layers of memory cells in the vertical direction.
FIGS. 28A and 28B are similar to the simplified diagrams in FIGS. 4A and 4B of a gated diode nonvolatile memory cell, showing examples of a pn diode with a homojunction, but add a diffusion barrier junction to the diode structure.
FIG. 5 is a simplified diagram of a gated diode nonvolatile memory cell, showing an example of a pn diode with a heterojunction. The first node 502 substantially surrounded by the combined charge storage and dielectric structure is germanium. The second node 504 is silicon. The first node 502 and the second node 504 are joined by a graded transition layer junction 506.
FIG. 29 is similar to the simplified diagram in FIG. 5 of a gated diode nonvolatile memory cell, showing an example of a pn diode with a heterojunction, but adds a diffusion barrier junction to the diode structure.
FIGS. 6A and 6B are simplified diagrams of a gated diode nonvolatile memory cell operation performing electron tunnel injection. In FIG. 6A, the electron tunnel injection mechanism moves electrons from the gate structure 608 biased at −10 V to the charge storage structure 606. The first diode node is biased at 10 V or is floating, and the second diode node 604 is biased at 10 V. In FIG. 6B, the electron tunnel injection mechanism moves electrons from the first diode node 602 biased at −10 V or is floating, to the charge storage structure 606. The gate structure 608 is biased at 10 V, and the second diode node 604 is biased at −10 V.
FIGS. 33A and 33B are similar to the simplified diagrams in FIGS. 6A and 6B of a gated diode nonvolatile memory cell operation performing electron tunnel injection, but add a diffusion barrier junction to the diode structure.
FIGS. 7A and 7B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band hot electron injection. In FIG. 7A, the band-to-band hot electron injection moves electrons from the diode structure to the charge storage structure 606. The n-type first diode node 602 biased at 0 V, the gate structure 608 is biased at 10 V, and holes of the resulting electron-hole pairs flow into the p+-type second node 604 biased at −5 V. In FIG. 7B, the band-to-band hot electron injection moves electrons from the diode structure to the charge storage structure 606. The n-type second diode node 604 biased at 0 V, the gate structure 608 is biased at 10 V, and holes of the resulting electron-hole pairs flow into the p+-type first node 602 is biased at −5 V.
FIGS. 34A and 34B are similar to the simplified diagrams in FIGS. 7A and 7B of a gated diode nonvolatile memory cell operation performing band-to-band hot electron injection, but add a diffusion barrier junction to the diode structure.
FIGS. 8A and 8B are simplified diagrams of a gated diode nonvolatile memory cell operation performing hole tunnel injection. In FIG. 8A, the hole tunnel injection mechanism moves holes from the gate structure 608 biased at 10 V to the charge storage structure 606. The first diode node is biased at −10 V or is floating, and the second diode node 604 is biased at −10 V. In FIG. 8B, the hole tunnel injection mechanism moves holes from the first diode node 602 biased at 10 V or is floating, to the charge storage structure 606. The gate structure 608 is biased at −10 V, and the second diode node 604 is biased at 10 V.
FIGS. 35A and 35B are similar to the simplified diagrams in FIGS. 8A and 8B of a gated diode nonvolatile memory cell operation performing hole tunnel injection, but add a diffusion barrier junction to the diode structure.
FIGS. 9A and 9B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band hot hole injection. In FIG. 9A, the band-to-band hot hole injection moves holes from the diode structure to the charge storage structure 606. The p-type first diode node 602 is biased at 0 V, the gate structure 608 is biased at −10 V, and electrons of the resulting electron-hole pairs flow into the n+-type second node 604 is biased at 5 V. In FIG. 9B, the band-to-band hot hole injection moves holes from the diode structure to the charge storage structure 606. The p-type second diode node 604 is biased at 0 V, the gate structure 608 is biased at −10 V, and electrons of the resulting electron-hole pairs flow into the n+-type first node 602 biased at 5 V.
Band-to-band currents flowing through the diode structure determine the charge storage state of the charge storage structure with great precision, due to combined vertical and lateral electrical fields. Larger vertical and lateral electrical fields give rise to larger band-to-band currents. A bias arrangement is applied to the various terminals, such that the energy bands bend sufficiently to cause band-to-band current in the diode structure, while keeping the potential difference between the diode nodes sufficiently low enough such that programming or erasing does not occur.
In example bias arrangements, the diode structure is reverse biased. Additionally, the voltage of the gate structure causes the energy bands to bend sufficiently such that band-to-band tunneling occurs through the diode structure. A high doping concentration in the one of the diode structure nodes, with the resulting high charge density of the space charge region, and the accompanying short length of the space charge region over which the voltage changes, contributes to the sharp energy band bending. Electrons in the valence band on one side of the diode structure junction tunnel through the forbidden gap to the conduction band on the other side of the diode structure junction and drift down the potential hill, deeper into the n-type diode structure node. Similarly, holes drift up the potential hill, away from either n-type diode structure node, and toward the p-type diode structure node.
The voltage of the gate structure controls the voltage of the portion of the diode structure by the dielectric structure which is between the diode structure and the charge storage structure. As the voltage of the gate structure becomes more negative, the voltage of the portion of the diode structure by this dielectric structure becomes more negative, resulting in deeper band bending in the diode structure. More band-to-band current flows, as a result of at least some combination of 1) an increasing overlap between occupied electron energy levels on one side of the bending energy bands, and unoccupied electron energy levels on the other side of bending energy bands, and 2) a narrower barrier width between the occupied electron energy levels and the unoccupied electron energy levels (Sze, Physics of Semiconductor Devices, 1981).
The net negative or net positive charge stored on the charge storage structure further affects the degree of band bending. In accordance with Gauss's Law, when a negative voltage is applied to the gate structure relative to the diode structure, a stronger electric field is experienced by portions of the diode structure which are near portions of the charge storage structure having relatively higher net negative charge. Similarly, when a positive voltage is applied to the gate structure relative to the diode structure, a stronger electric field is experienced by portions of the diode structure which are near portions of the charge storage structure having relatively higher net positive charge.
The different bias arrangements for reading, and bias arrangements for programming and erasing, show a careful balance. For reading, the potential difference between the diode structure terminals should not cause a substantial number of charge carriers to transit a dielectric to the charge storage structure and affect the charge storage state. In contrast, for programming and erasing, the potential difference between the diode structure terminals can be sufficient to cause a substantial number of carriers to transit a dielectric and affect the charge storage state by band-to-band hot carrier injection.
FIGS. 36A and 36B are similar to the simplified diagrams in FIGS. 9A and 9B of a gated diode nonvolatile memory cell operation performing band-to-band hot hole injection, but add a diffusion barrier junction to the diode structure.
FIGS. 10A and 10B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure. In FIGS. 10A and 10B, band-to-band sensing mechanism creates electron-hole pairs in the diode structure. Resulting electrons flow into the n+-type first diode node 602 biased at 2 V, and resulting holes flow into the p-type second diode node 604 biased at 0 V. The gate structure 608 is biased at −10 V. In FIG. 10A, the charge storage structure 606 stores relatively more negative net charge by the diode structure junction between the n+-type first diode node 602 and the p-type second diode node 604. In FIG. 10B, the charge storage structure 606 stores relatively more positive net charge by the diode structure junction between the n+-type first diode node 602 and the p-type second diode node 604. Greater band bending in the diode structure occurs in FIG. 10A than in FIG. 10B, and greater band-to-band sensing current flows in FIG. 10A than in FIG. 10B.
FIGS. 37A and 37B are similar to the simplified diagrams in FIGS. 10A and 10B of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure, but add a diffusion barrier junction to the diode structure.
FIGS. 11A and 11B are simplified diagrams of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure, but with a different diode node arrangement from FIGS. 10A and 10B. In particular, the first node 602 of the diode structure substantially surrounded by the combined charge storage and dielectric structure is p+-type, and the second node of the diode structure 604 is n-type. The band-to-band sensing mechanism creates electron-hole pairs in the diode structure. Resulting holes flow into the p+-type first diode node 602 biased at −2 V, and resulting electrons flow into the n-type second diode node 604 biased at 0 V. The gate structure 608 is biased at 10 V. In FIG. 11A, the charge storage structure 606 stores relatively more negative net charge by the diode structure junction between the p+-type first diode node 602 and the n-type second diode node 604. In FIG. 11B, the charge storage structure 606 stores a relatively more positive net charge by the diode structure junction between the p+-type first diode node 602 and the n-type second diode node 604. Greater band bending in the diode structure occurs in FIG. 11B than in FIG. 11A, and greater band-to-band sensing current flows in FIG. 11B than in FIG. 11A.
In other embodiments, the more heavily doped node is the second node of the diode structure, and the less heavily doped node is the first node of the diode structure substantially surrounded by the combined charge storage and dielectric structure.
FIGS. 38A and 38B are similar to the simplified diagrams in FIGS. 11A and 11B of a gated diode nonvolatile memory cell operation performing band-to-band sensing with different amounts of net positive or net negative charge characterizing the charge storage structure, but add a diffusion barrier junction to the diode structure, and have a different diode node arrangement than in FIGS. 37A and 37B.
FIGS. 12A and 12B are simplified diagrams of neighboring gated diode nonvolatile memory cells, with and without interconnected second nodes. In FIG. 12A, neighboring gated diode nonvolatile memory cells respectively have second nodes 1204 and 1205. Both second nodes 1204 and 1205 of the neighboring gated diode nonvolatile memory cells extend beyond the oxide which isolates the upper portions of the second nodes 1204 and 1205 from each other, and connect into a common node structure 1214. This common node structure is treated as a same bit line used by both neighboring gated diode nonvolatile memory cells. In FIG. 12B, both second nodes 1204 and 1205 of the neighboring gated diode nonvolatile memory cells do not extend beyond the oxide which isolates the second nodes 1204 and 1205 from each other. Each of the second nodes 1204 and 1205 is treated as a distinct bit line, and the two second nodes 1204 and 1205 are not treated as a same bit line.
FIGS. 39A and 39B are similar to the simplified diagrams in FIGS. 12A and 12B of neighboring gated diode nonvolatile memory cells, with and without interconnected second nodes, but add a diffusion barrier junction to the diode structure.
FIGS. 13A and 13B are simplified diagrams of an array of gated diode nonvolatile memory cells with interconnected second node columns, performing band-to-band sensing. The first node columns of the diode structures substantially surrounded by the combined charge storage and dielectric structures are n-type, and the second node columns of the diode structures are p-type. Neighboring second node columns of the diode structures extend beyond the oxide which isolates the upper portions of the second node columns from each other, and connect into a common bit line structure. In FIG. 13A, the first node columns of the diode structures are shown with bit line labels DL1 to DL6, the second node columns of the diode structures are shown with the bit line label CL, and the word lines are shown with word line labels WL1 to WL6. In FIG. 13B, voltages are applied to the diode columns and the word lines. The first node column DL3 is biased at 2 V, and the remaining first node columns are biased at 0 V. The second node columns are biased at 0 V. The word line WL5 is biased at −10 V, and the remaining word lines are biased at 0 V. A band-to-hand sensing operation is thereby performed on the gate diode memory cell at the intersection of word line WL5 and the first node column DL3. By measuring the current flowing through the first node column DL3 or the second node columns CL, the charge storage state of the charge storage structure of that gate diode memory cell is determined.
FIGS. 14A and 14B are simplified diagrams of an array of gated diode nonvolatile memory cells without interconnected second node columns, performing band-to-band sensing. Unlike the interconnected common bit line structure of the second node columns shown in FIGS. 13A and 13B, in FIGS. 14A and 14B neighboring second node columns of the diode structures are treated as distinct bit lines. In FIG. 14A, the second node columns of the diode structures are shown with bit line labels CL1 to CL6. In FIG. 14B, voltages are applied to the diode columns and the word lines. The first node column DL3 is biased at 2 V, and the remaining first node columns are biased at 0 V. The second node columns are biased at 0 V. The word line WL5 is biased at −10 V, and the remaining word lines are biased at 0 V. A band-to-band sensing operation is thereby performed on the gate diode memory cell at the intersection of word line WL5 and the first node column DL3/second node column CL3. By measuring the current flowing through the first node column DL3 or second node column CL3, the charge storage state of the charge storage structure of that gate diode memory cell is determined.
FIGS. 15A and 15B are simplified diagrams of an array of gated diode nonvolatile memory cells with interconnected second node columns, performing band-to-band sensing, where the doping arrangement of the diode structures is different from FIGS. 13A, 13B, 14A, and 14B. In FIGS. 15A and 15B, the first node columns of the diode structures substantially surrounded by the combined charge storage and dielectric structures are p-type, and the second node columns of the diode structures are n-type. Like FIGS. 13A and 13B, neighboring second node columns of the diode structures extend beyond the oxide which isolates the upper portions of the second node columns from each other, and connect into a common bit line structure. In FIG. 15A, the first node columns of the diode structures are shown with bit line labels DL1 to DL6, the second node columns of the diode structures are shown with the bit line label CL, and the word lines are shown with word line labels WL1 to WL6. In FIG. 15B, voltages are applied to the diode columns and the word lines. The first node column DL3 is biased at −2 V, and the remaining first node columns are biased at 0 V. The second node columns are biased at 0 V. The word line WL5 is biased at 10 V, and the remaining word lines are biased at 0 V. A band-to-band sensing operation is thereby performed on the gate diode memory cell at the intersection of word line WL5 and the first node column DL3. By measuring the current flowing through the first node column DL3 or the second node columns CL, the charge storage state of the charge storage structure of that gate diode memory cell is determined.
FIGS. 16A and 16B are simplified diagrams of an array of gated diode nonvolatile memory cells without interconnected node columns, performing band-to-band sensing, where the doping arrangement of the diode structures is like FIGS. 15A and 15B. Unlike the interconnected bit line structure of the second node columns shown in FIGS. 15A and 15B, in FIGS. 16A and 16B neighboring second node columns of the diode structures are treated as distinct bit lines. In FIG. 16A, the second node columns of the diode structures are shown with bit line labels CL1 to CL6. In FIG. 16B, voltages are applied to the diode columns and the word lines. The first node column DL3 is biased at −2 V, and the remaining first node columns are biased at 0 V. The second node columns are biased at 0 V. The word line WL5 is biased at 10 V, and the remaining word lines are biased at 0 V. A band-to-band sensing operation is thereby performed on the gate diode memory cell at the intersection of word line WL5 and the first node column DL3/second node column CL3. By measuring the current flowing through the first node column DL3 or second node column CL3, the charge storage state of the charge storage structure of that gate diode memory cell is determined.
The arrays of FIGS. 13A-16B have embodiments with and without diffusion barrier junctions.
FIGS. 17A, 17B, and 17C are simplified diagrams of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which electron tunnel injection is performed as in FIG. 6A, but on selected cells. In FIG. 17A, the electron tunnel injection mechanism moves electrons from the gate structure 608 biased at −10 V to the charge storage structures 606 and 607. The first diode nodes 602 and 603 are biased at 10 V or are floating, and the second diode nodes 604 and 605 are biased at 10 V. In FIG. 17B, the first diode node 602 is biased at 10 V or is floating, but the first diode node 603 is biased at −10 V. In FIG. 17C, the first diode nodes 602 and 603 are biased at 10 V or floating and 0V respectively, and the second diode nodes 604 and 605 are biased at 10 V and 0V respectively. The electron tunnel injection mechanism selectively moves electrons from the gate structure 608 biased at −10 V to the charge storage structure 606 but not to the charge storage structure 607. In other embodiments, the electron tunnel injection mechanism moves electrons from the first diode node to the charge storage structure as in FIG. 6B, but on selected cells. In other embodiments, the hole tunnel injection mechanism moves holes from the gate structure to the charge storage structure as in FIG. 8A, but on selected cells. In other embodiments, the hole tunnel injection mechanism moves holes from the first diode node to the charge storage structure as in FIG. 8B, but on selected cells.
FIGS. 40A and 40B are similar to the simplified diagrams in FIGS. 17A and 17B of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which electron tunnel injection is performed on selected cells, but add a diffusion barrier junction to the diode structure.
FIGS. 18A, 18B, and 18C are simplified diagrams of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band hot hole injection is performed as in FIG. 9B, but on selected cells. In FIG. 18A, the band-to-band hot hole injection mechanism moves holes from the diode structure to the charge storage structure 606. The p-type second diode nodes 604 and 605 are biased at 0 V, the gate structure 608 is biased at −10 V, and electrons of the resulting electron-hole pairs flow into the n+-type first nodes 602 and 603 biased at 5 V. In FIG. 18B, the first diode node 602 is biased at 5 V, but the first diode node 603 is biased at 0 V. The band-to-band hot hole injection mechanism selectively moves holes from the diode structure to the charge storage structure 606 but not to the charge storage structure 607. FIG. 18C also shows band-to-band hot hole injection being performed selectively on the diode structure formed by the first diode node 602 and the second diode node 604, but not on the diode structure formed by the first diode node 603 and the second diode node 605, as in FIG. 18B. However, in FIG. 18C, the first diode node 603 is biased at 5 V and the second diode node 605 is biased at 5 V. Because a sufficient reverse bias is still absent in the diode structure formed by the first diode node 603 and the second diode node 605, the band-to-band hot hole injection mechanism is still absent in this diode structure. In other embodiments, the band-to-band hot hole injection mechanism selectively moves holes from the diode structure with a p-type first diode node and a n+-type second diode node to the charge storage structure as in FIG. 9A, but on selected cells. In other embodiments, the band-to-band hot electron injection mechanism selectively moves electrons from the diode structure with a p+-type first diode node and an n-type second diode node to the charge storage structure as in FIG. 7B, but on selected cells. In other embodiments, the band-to-band hot electron injection mechanism selectively moves electrons from the diode structure with an n-type first diode node and a p+-type second diode node to the charge storage structure as in FIG. 7A, but on selected cells.
FIGS. 41A and 41B are similar to the simplified diagrams in FIGS. 18A, 18B, and 18C of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band hot hole injection is performed on selected cells, but add a diffusion barrier junction to the diode structure.
FIGS. 22A and 22B are simplified diagrams of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band sensing is performed as in FIGS. 10A and 10B, but on selected cells. In FIG. 22A, the band-to-band hot hole sensing mechanism creates electron-hole pairs in the diode structure formed by the n+-type first diode node 602 biased at 2 V and the p-type second diode node 604 biased at 0 V. Resulting electrons flow into the n+-type first diode node 602, and resulting holes flow into the p-type second diode node 604. This band-to-band sensing current indicates the amount of net positive or net negative charge characterizing the charge storage structure 606. The gate structure 608 is biased at −10 V. In the diode structure formed by the n+-type first diode node 603 biased at 0 V and the p-type second diode node 605 biased at 0 V, a band-to-band sensing current indicating the amount of charge characterizing the charge storage structure 607 does not flow, because a sufficient reverse bias is absent. FIG. 22B also shows band-to-band sensing being performed selectively on the diode structure formed by the first diode node 602 and the second diode node 604, but not on the diode structure formed by the first diode node 603 and the second diode node 605, as in FIG. 22A. However, in FIG. 22B, the first diode node 603 is biased at 2 V and the second diode node 605 is biased at 2 V. Because a sufficient reverse bias is still absent in the diode structure formed by the first diode node 603 and the second diode node 605, the band-to-band sensing mechanism is still absent. In other embodiments, the band-to-band sensing mechanism selectively flows in a diode structure with a p-type first diode node and a n+-type second diode node as in FIGS. 11A and 11B, but on selected cells.
FIGS. 42A and 42B are similar to the simplified diagrams in FIGS. 22A and 22B of neighboring gated diode nonvolatile memory cells without interconnected second nodes, in which band-to-band sensing is performed on selected cells, but add a diffusion barrier junction to the diode structure.
FIGS. 19A, 19B, and 19C are exploded view diagrams of multiple arrays of gated diode nonvolatile memory cells, with different interconnections of the word lines, first node columns, and second node columns, between different arrays. Each of the vertically displaced arrays is like the array shown in FIGS. 16A and 16B. Although the multiple arrays displaced vertically from one another by isolation oxide 1904 are part of the same integrated circuit, the multiple arrays are shown in exploded view to show the labels for all word lines and bit lines of the multiple arrays.
In FIG. 19A, the word lines of different arrays 1900 and 1902 are interconnected. The word lines of array 1900 and the word lines of array 1902 are both labeled WL1 to WL6. However, the first node columns and second node columns of different arrays are isolated from each other. The first node columns of array 1900 are labeled DL1 to DL6, and the first node columns of array 1902 are labeled DL7 to DL12. The second node columns of array 1900 are labeled CL1 to CL6, and the second node columns of array 1902 are labeled CL7 to CL12.
In FIG. 19B, the word lines of different arrays 1910 and 1912 are isolated from each other. The word lines of array 1910 are labeled WL1 to WL6, and the word lines of array 1912 are labeled WL7 to WL12. However, the first node columns and second node columns of the different arrays 1910 and 1912 are interconnected. The first node columns of array 1910 and array 1912 are both labeled DL1 to DL6, and the second node columns of array 1910 and array 1912 are both labeled CL1 to CL6.
In FIG. 19C, the word lines of different arrays 1920 and 1922, and the first node columns and second node columns of different arrays 1920 and 1922, are isolated from each other. The word lines of array 1920 are labeled WL1 to WL6, and the word lines of array 1922 are labeled WL7 to WL12. The first node columns of array 1920 are labeled DL1 to DL6, and the first node columns of array 1922 are labeled DL7 to DL12. The second node columns of array 1920 are labeled CL1 to CL6, and the second node columns of array 1922 are labeled CL7 to CL12.
In other embodiments, the multiple arrays have interconnected second node columns, such that a particular array of the multiple arrays has a common bit line structure for the second node columns of that array, or alternatively, for all of the arrays. In other embodiments, the first node columns are n-type and the second columns are p-type. The arrays of FIGS. 19A-C have embodiments with and without diffusion barrier junctions.
FIG. 20 is a simplified diagram of an integrated circuit with an array of gated diode nonvolatile memory cells and control circuitry. The integrated circuit 2050 includes a memory array 2000 implemented using gate diode nonvolatile memory cells, on a semiconductor substrate. The gated diode memory cells of array 2000 may be individual cells, interconnected in arrays, or interconnected in multiple arrays. A row decoder 2001 is coupled to a plurality of word lines 2002 arranged along rows in the memory array 2000. A column decoder 2003 is coupled to a plurality of bit lines 2004 arranged along columns in the memory array 2000. Addresses are supplied on bus 2005 to column decoder 2003 and row decoder 2001. Sense amplifiers and data-in structures in block 2006 are coupled to the column decoder 2003 via data bus 2007. Data is supplied via the data-in line 2011 from input/output ports on the integrated circuit 2050, or from other data sources internal or external to the integrated circuit 2050, to the data-in structures in block 2006. Data is supplied via the data-out line 2015 from the sense amplifiers in block 2006 to input/output ports on the integrated circuit 2050, or to other data destinations internal or external to the integrated circuit 2050. A bias arrangement state machine 2009 controls the application of bias arrangement supply voltages 2008, such as for the erase verify and program verify voltages, and the arrangements for programming, erasing, and reading the memory cells, such as with the band-to-band currents. The integrated circuit of FIG. 20 has embodiments with and without diffusion barrier junctions.
FIGS. 21A-21H illustrate a sample process flow for multiple arrays of gated diode nonvolatile memory cells. FIG. 21A shows a structure with a p-type polysilicon layer 2112 on an oxide layer 2104 on a silicon substrate 2102. In FIG. 21B, sacrificial oxide 2116 is formed and nitride 2118 is formed. Shallow trench isolation is performed, resulting in multiple p-type polysilicon structures 2113. In FIG. 21C, the sacrificial oxide 2116 and nitride 2118 are removed. The multiple p-type polysilicon structures 2113 are implanted, resulting in p-type second nodes 2114 and n+-type first nodes 2121 of the gated diode nonvolatile memory cells. In FIG. 21D, the combined charge storage and dielectric structure 2123 and gate polysilicon 2132 are formed, completing the first array of gated diode nonvolatile memory cells. In FIG. 21E, another layer of oxide 2104 and another layer of p-type polysilicon 2112 are formed. In FIGS. 21F-21H, the steps of FIGS. 21B-D are substantially repeated to form another array of gated diode nonvolatile memory cells that is displaced vertically from the first array.
FIGS. 23A-H illustrate a sample process flow for multiple arrays of gated diode nonvolatile memory cells. FIG. 23A shows a substrate 10 with a photoresist pattern 12 that defines shallow trenches to isolate neighboring devices from each other. The substrate may be either p-type or n-type. FIG. 23B shows the shallow trenches 14 etched in the substrate 10 between the photoresist pattern 12. The photoresist pattern 12 has been removed. FIG. 23C shows isolation oxide 16 filling the shallow trenches 14 to isolate neighboring devices from each other. FIG. 23D shows ion implantation 18. Ion implantation 18 with different ions creates deep well 8 in substrate 10, and well 6 in deep well 8. For example, if the substrate 10 is p-type, then deep well 8 is n-type and well 6 is p-type. Alternatively, if the substrate 10 is n-type, then deep well 8 is p-type and well 6 is n-type. For simplicity in the subsequent drawings, the combination of wells and substrate is not shown as it is understood that the devices may be formed in either a well or a substrate. FIG. 23E shows the diffusion bit lines 20 also formed by the ion implantation 18 between the isolation oxide 16. The diffusion bit lines 20 are implanted with a dopant having a charge type opposite to that of the well 6 (which alternatively may be a substrate 10). FIG. 23F shows the partial removal of the isolation oxide 16. Partial removal by dip back or etch back from the isolation oxide 16, results in shallower isolation oxide 22. The surface of the shallower isolation oxide 22 is lower than the pn junction between the diffusion bit lines 20 and the well 6. FIG. 23G shows the formation of the ONO film 30, having an upper oxide 24, a nitride 26, and a lower oxide 28. The nitride structure in other embodiments is a floating gate or nanocrystal. Because the surface of the shallower isolation oxide 22 is lower than the pn junction between the diffusion bit lines 20 and the well 6, the ONO film 30 controls the voltage at the pn junction between the diffusion bit lines 20 and the well 6. FIG. 23H shows the formation of word lines 32 that provide a gate voltage to the devices. An n+ or p+ polysilicon film is deposited and etched to form multiple word lines. The gate material can also be a metal gate, such as silicide, Ry, Mo, and W.
FIG. 24 is a perspective view of an array of gated diode nonvolatile memory cells as formed by the process of FIGS. 23A-23H.
FIGS. 30A to 30F illustrate another sample process flow for an array of gated diode nonvolatile memory cells.
FIG. 30A shows a p-type substrate 6 with n-type poly deposition 40 being performed. FIG. 30B shows the resulting n+ poly film 42 over the p-type substrate 6. FIG. 30C shows the subsequently formed mask layer, with a layer of pad oxide 44 over the n+ poly film 42 and a layer of SiN 46 over the pad oxide 44. Photoresist layer 48 over the layer of SiN 46 is part of the photolithography process to form trenches. FIG. 30D shows the shallow trenches anisotropically formed on the substrate 6. The n+ poly film 42 has been divided by the trenches into discrete first diode nodes, with corresponding second diode nodes being the portion of the neighboring substrate 6. Similarly, pad oxide 44 is divided into discrete pad oxides 52 and SiN 46 is divided into discrete SiN 54. Photoresist layer 48 is removed. In FIG. 30E, isolation oxide 56 fills the trenches, and isolates neighboring diode structures from each other. A chemical mechanical polishing process and SiN removal follow. FIG. 30F shows the partial removal of the isolation oxide, resulting in isolation oxide parts 22 which isolate neighboring diode structures from each other, by isolating parts of the neighboring second diode nodes from each other. The remainder of the process is similar to that shown in FIGS. 23G and 23H.
FIGS. 31A-31H illustrate a sample process flow for an array of gated diode nonvolatile memory cells with a diffusion barrier junction in the diode structures.
The process flow of FIGS. 31A-31H is similar to that of FIGS. 30A to 30F and FIGS. 23G and 23H, except that, prior to the formation of the n+ poly film 42 over the p-type substrate 6, an ultra thin film 58 is formed over the over the p-type substrate 6. Film 58 is in various embodiments an oxide, nitride, or oxynitride, with a thickness of about 10-20 Angstroms After the film 58 is divided into discrete sections, each discrete section is the diffusion barrier junction that helps to discourage the movement of dopants between the first and second diode nodes of each diode structure.
FIG. 32 is a perspective view of an array of gated diode nonvolatile memory cells with a diffusion barrier junction in the diode structures as formed by the process of FIGS. 31A-31H.
FIGS. 43A and 43B are graphs comparing the doping profiles of diode structures with and without a diffusion barrier junction.
FIG. 43A is graph showing the doping profiles of a diode structure with a diffusion barrier junction. Curves 4304 and 4306 respectively represent the doping profiles of p-type dopant boron and n-type dopant phosphorus. Curve 4302 represents the net doping profile of curves 4304 and 4306. The x-axis represents the vertical position in microns along the diode structure, such that the origin is the interface between the diffusion barrier junction and the second diode node, the positive x-axis direction goes deeper into the second diode node (and increasingly surrounded by isolation dielectric), and the negative x-axis direction goes deeper into the first diode node (and increasingly surrounded by charge storage structure and storage dielectric). The first diode node is n+ polysilicon doped 1020 cm−3.
FIG. 43B is graph showing the doping profiles of a diode structure similar to that of FIG. 43A, but without a diffusion barrier junction. Curves 4310 and 4312 respectively represent the doping profiles of p-type dopant boron and n-type dopant phosphorus. Curve 4308 represents the net doping profile of curves 4304 and 4306. The following table compares the p-type boron doping concentration, the n-type phosphorus doping concentration, and the net doping type, at a depth in the second diode node corresponding to an x-axis value of x=0.1 um. The table indicates that the diffusion barrier junction helps to discourage the movement of n-type dopants in the first diode node from moving into the second diode node.














FIG. 43B,



FIG. 43A, w/diffusion
w/o diffusion



barrier junction
barrier junction







p-type boron (cm−3)
6.58 × 1017
6.42 × 1017


n-type phosphorus (cm−3)
1.66 × 1017
1.47 × 1019


Net doping type of second
p-type
n-type


diode node









FIGS. 44A and 44B are graphs comparing the doping profiles of diode structures with and without a diffusion barrier junction, under different thermal budget conditions. In both FIGS. 44A and 44B, the diode structure has a 15 Angstrom thick diffusion barrier junction. The x-axis convention is the same as in FIGS. 43A and 43B. In FIG. 44A, curves 4402 and 4404 respectively represent the doping profiles of p-type dopant boron and n-type dopant phosphorus. In FIG. 44B, curves 4406 and 4408 respectively represent the doping profiles of p-type dopant boron and n-type dopant phosphorus. FIG. 44A corresponds to a relatively light thermal budget, with an ISSG (in situ steam generation) process at 900° C. for 21 seconds followed by an HTO (high temperature oxide) process at 900° C. for 30 minutes. FIG. 44B corresponds to a relatively heavy thermal budget, with a thermal process at 950° C. for 10 minutes followed by another thermal process at 1000° C. for 43.5 minutes. The respective doping profiles appear very similar between FIGS. 44A and 44B, despite the very different thermal budgets.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

## Claims

1. A method of operating a nonvolatile memory device integrated circuit comprising a charge storage structure, one or more storage dielectric structures at least partly between the charge storage structure and a diode structure and at least partly between the charge storage structure and a source of gate voltage, the diode structure having a first node and a second node separated by a diffusion barrier junction, the method comprising:
applying a first bias arrangement to determine a charge storage state of the charge storage structure, wherein the first node and the second node of the diode structure are at least partly adjacent to the one or more storage dielectric structures, and the diode structure has a cross-section in which the second node has opposite sides isolated from neighboring devices by isolation dielectric; and
measuring current flowing through at least the diffusion barrier junction separating the first node and the second node of the diode structure, in reverse bias, to determine the charge storage state of the charge storage structure.

2. The method of claim 1, wherein the first bias arrangement causes a first voltage difference between the source of gate voltage and the second node, and a second voltage difference between the first node and the second node, wherein the first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for said measuring, and the first voltage difference and the second voltage difference fail to change the charge storage state of the charge storage structure.

3. The method of claim 1, wherein the first bias arrangement causes a first voltage difference of at least about 10 V between the gate and the second node, and a second voltage difference more than about 2 V between the first node and the second node.

4. The method of claim 1, wherein the first bias arrangement induces at least a band-to-band current component through the diode structure.

5. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure.

6. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via band-to-band hot hole tunneling; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via Fowler-Nordheim tunneling.

7. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via Fowler-Nordheim tunneling; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via band-to-band hot electron tunneling.

8. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via band-to-band hot hole tunneling; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via electron movement between the charge storage structure and the diode structure.

9. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via hole movement between the charge storage structure and the diode structure; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via band-to-band hot electron tunneling.

10. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via band-to-band hot hole tunneling; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via electron movement between the charge storage structure and the gate.

11. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via hole movement between the charge storage structure and the gate; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via band-to-band hot electron tunneling.

12. the method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via Fowler-Nordheim tunneling; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via Fowler-Nordheim tunneling.

13. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via hole movement between the charge storage structure and the diode structure; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via electron movement between the charge storage structure and the diode structure.

14. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via hole movement between the charge storage structure and the diode structure; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via electron movement between the charge storage structure and the gate.

15. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via hole movement between the charge storage structure and the gate; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via electron movement between the charge storage structure and the diode structure.

16. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via hole movement between the charge storage structure and the gate; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via electron movement between the charge storage structure and the gate.

17. The method of claim 1, further comprising:
applying a second bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net positive charge in the charge storage structure via band-to-band hot hole tunneling; and
applying a third bias arrangement to adjust the charge storage state of the charge storage structure by increasing a net negative charge in the charge storage structure via band-to-band hot electron tunneling.

18. The method of claim 1, further comprising:
programming the charge storage state of the charge storage structure to store one bit.

19. The method of claim 1, further comprising:
programming the charge storage state of the charge storage structure to store multiple bits.

20. The method of claim 1, wherein any hot charge carriers generated during the first bias arrangement fail to change the charge storage state of the charge storage structure.

21. A method of operating an array of nonvolatile memory storage devices, each comprising a charge storage structure, one or more storage dielectric structures at least partly between the charge storage structure and a diode structure and at least partly between the charge storage structure and a source of gate voltage, the diode structure having a first node and a second node separated by a diffusion barrier junction, the method comprising:
applying a first bias arrangement to determine at least one charge storage state of one or more of the charge storage structures of the array, wherein the first node and the second node of one or more diode structures of the array are at least partly adjacent to the one or more storage dielectric structures, and the one or more diode structures have a cross-section in which the second node has opposite sides isolated from neighboring devices by isolation dielectric; and
measuring current flowing through at least one of the diffusion barrier junctions separating the first node and the second node of the one or more diode structures, in reverse bias, to determine the charge storage state of the one or more charge storage structures.

22. The method of claim 21, wherein the first bias arrangement causes a first voltage difference between the source of gate voltage and the second node, and a second voltage difference between the first node and the second node, wherein the first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for said measuring, and the first voltage difference and the second voltage difference fail to change the charge storage state.

23. The method of claim 21, wherein the first bias arrangement induces at least a band-to-band current component through the one or more diode structure.

24. A method of operating an array of nonvolatile memory storage devices comprising a plurality of diode columns each including a first node column and a second node column separated by a diffusion barrier junction wherein opposite sides of the second node column are isolated from neighboring columns by isolation dielectric, a plurality of gate rows overlapping the plurality of diode columns, a plurality of nonvolatile storage structures each located at a particular intersection between a particular diode column of the plurality of diode columns and a particular gate row of the plurality of gate rows, and each nonvolatile storage structure of the plurality of nonvolatile storage structures includes a charge storage structure and one or more storage dielectric structures at least partly between the charge storage structure and the particular diode column, at least partly between the charge storage structure and the particular gate row, and at least partly adjacent to the first node column and the second node column of the particular diode column at the particular intersection, the method comprising:
applying a first bias arrangement to determine at least one charge storage state of one or more of the charge storage structures of the array, wherein the first node column and the second node column of one or more diode columns of the array intersecting the one or more of the charge storage structures at one or more intersections are at least partly adjacent to the one or more storage dielectric structures at the one or more intersections, and the one or more diode columns have cross-sections in which the second node column has opposite sides isolated from neighboring devices by isolation dielectric; and
measuring current flowing through at least one of the diffusion barrier junctions separating the first nodes and the second nodes of the one or more diode columns, in reverse bias, to determine at least one charge storage state of the one or more charge storage structures of the array.

25. The method of claim 24, wherein the first bias arrangement causes a first voltage difference between one or more gate rows of the plurality of gate rows and one or more second node columns of the array, and a second voltage difference between the first node and the second node of the array, wherein the first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for said measuring, and the first voltage difference and the second voltage difference fail to change the charge storage state of the one or more charge storage structures at the one or more intersections.

26. The method of claim 24, wherein the first bias arrangement induces at least a band-to-band current component through the one or more diode columns.