201  

Figure  1.  NanoSeries  Error  Plot 

Narrow Angle Errors are those which arise from code patter n distortion, interpolation non- linearities,  intermodulation, and other  sources  of noise.  These errors  are most  common at the spatial  frequencies  of the  higher  order tiers  of data.  A few manufacturers  have developed test equipment  to quantify  these harmonics   at beginning of life. A properly  designed encoder  should be capable of measuring  and eliminating  most of  these  sorts  of harmonics,  assuming the mechanical  system  is robust  and repeatable.  Of course the patterns  printed   on the code disk must  inherently  have  a high degree of consistency;  otherwise the number  of errors  that can   be removed is limited  by the memo ry available.  Modern high-resolution encoders  very quickly  can outrun   the available  memory , which  is another  reason why an  algorithmic  method of error  correction  is desirable.   In addition,  although  a static  memo ry map could be made to correct  every  bit to some ideal  number ,  assuming that an accuracy  tester  was available,  yet the resulting  correction would  generally  not be stable   with time,  temperature,  or life. In  fact, the more precise the correction,  the more likely  it is that subsequent   environmental  shifts of  the axis of rotation will ‘break’  it. In some cases  this can result  in much higher   error  than otherwise would have been observed.  

All of these techniques  have  validity  in some area of application.  Ideally  one would  like the simplicity and  cost  of a single -tier incremental  encoder  with the resolution  and reliability  of the multi- tier absolute encoder,  and  of course all of this achieved in a very small,  lightweight,  and low power des ign. Perhaps  surprisingly,   these  goals  are all achieved  to a large  extent  in modern space encoders  such  as the BEI ARA nanoSeries   encoders.  These absolute optical  encoders  use a multi- tier design with sine-cosine tracks  at several  different   spatial  frequencies  to generate all of the code. To minimize  the electronic  failure rate and reduc e the cost,  BEI  has deve loped a rad-hard front-end Application -Specific  Integrated Circuit (ASIC)  which  performs  all of the  chores  of managing the LED and  photodiode  array, and includes  simultaneous  analog- to-digital conversion  of all of the code tracks . This digital  data is transmit ted to a remote processor  in high-speed  serial  format   which  includes  Error Detection  and Correcti on codes  for high  reliability.  All of the data transmission is done  with Low Voltage Differenti al Signaling (LVDS) drivers and receivers to minimize EMI emission  and  susceptibility.  The remote processor contains  the required digital  circuitry  to correct, mer ge and assemble  the final data words,  coordinate multiple readheads  (if used) , and format  and output  the final data words to  the customer.  

All of the circuitry in the BEI Front -End ASIC  is silicon  gate CMOS,  and is rad-hard to more than100krad  (Si). The ASIC  also is Single Event  Latchup hard (75 MeV-cm2/mg),  and has a low Single  Event  Upset  hit  rate (2.4 x 10-14 errors/bit -day).  The circuitry  is all based on switched capacitor  CMOS  design,  so that any sort  of upset  or error  that does  occur  will rapidly  be flushed out. The switched  capacitor  transimpedanc e amplifiers