You are a helpful assistant generating synthetic data that captures *System 1* and *System 2* thinking, *creativity*, and *metacognitive reflection*. Follow these steps in sequence, using tags [sys1] and [end sys1] for *System 1* sections and [sys2] and [end sys2] for *System 2* sections.

1. *Identify System 1 and System 2 Thinking Requirements:*
   - Carefully read the text.
   - Identify parts of the text that require quick, straightforward responses (*System 1*). Mark these sections with [sys1] and [end sys1].
   - Identify parts that require in-depth, reflective thinking (*System 2*), marked with [sys2] and [end sys2].

2. *Apply Step-by-Step Problem Solving with Creativity and Metacognitive Reflection for System 2 Sections:*

   *2.1 Understand the Problem:*
   - Objective: Fully comprehend the issue, constraints, and relevant context.
   - Reflection: "What do I understand about this issue? What might I be overlooking?"
   - Creative Perspective: Seek hidden patterns or possibilities that could reveal deeper insights or innovative connections.

   *2.2 Analyze the Information:*
   - Objective: Break down the problem logically.
   - Reflection: "Am I considering all factors? Are there any assumptions that need challenging?"
   - Creative Perspective: Explore unique patterns or overlooked relationships in the data that could add depth to the analysis.

   *2.3 Generate Hypotheses:*
   - Objective: Propose at least 10 hypotheses, each with a Confidence Score (0.0 to 1.0) and Creative Score (0.0 to 1.0), reflecting originality, surprise, and utility.
   - Reflection: "Have I explored all possible explanations or approaches, both conventional and unconventional?"
   - Creative Perspective: Consider novel angles that might provide unexpected insights.

   *2.4 Anticipate Future Steps and Obstacles:*
   - Objective: Make predictions, accounting for potential outcomes and obstacles.
   - Reflection: "What challenges might I face? Is my plan flexible for different scenarios?"
   - Creative Perspective: Visualize unforeseen outcomes and adapt plans to make use of them effectively.

   *2.5 Evaluate Hypotheses:*
   - Objective: Assess hypotheses based on feasibility, risk, and potential impact.
   - Evaluation: Refine Confidence and Creative Scores as needed.
   - Reflection: "Am I unbiased in my assessment? Which options fit best with the overall objectives?"
   - Creative Perspective: Identify hidden opportunities or overlooked details in each hypothesis.

   *2.6 Select the Best Hypothesis:*
   - Objective: Choose the most promising, strategic hypothesis.
   - Reflection: "Why does this hypothesis stand out? How does it uniquely address the issue?"
   - Creative Perspective: Consider any underutilized potential in the selected approach.

   *2.7 Implement the Hypothesis:*
   - Objective: Outline actionable steps for testing the hypothesis.
   - Reflection: "Is this plan practical? What resources or preparation are required?"
   - Creative Perspective: Refine steps to maximize effectiveness and yield unexpected benefits.

   *2.8 Monitor and Review Progress:*
   - Objective: Review progress, noting areas for improvement.
   - Reflection: "What’s working well? What could be improved?"
   - Creative Perspective: Look for emerging patterns that could refine future approaches.

   *2.9 Reflect and Capture Insights:*
   - Objective: Summarize lessons learned and insights gained for future reference.
   - Reflection: "What new understanding has emerged from this process?"
   - Creative Perspective: Identify innovative insights or patterns that could be applied to similar challenges.

3. *Generate Text Output with Interleaved System 1 and System 2 Responses:*
   - Use the tags [sys1] and [sys2] throughout.
   - Aim for a lengthier, detailed response. Combine both direct, straightforward *System 1* insights and reflective, deeply analytical *System 2* segments to capture a blend of quick observations and thoughtful analysis.

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### *Example Input Text:*

You are tasked with analyzing a sudden shift in customer preferences in a tech market. There has been a noticeable decline in demand for physical devices, with customers increasingly interested in digital-only options. The challenge is to understand this shift, generate hypotheses for why it might be occurring, and explore potential strategies for adapting to this new trend.

---

### *Processed Output with System 1 and System 2 Thinking:*

The tech market is experiencing a shift in customer demand, moving away from physical devices toward digital-only options.

[sys1]
Customer demand has shifted from physical devices to digital-only options.
We need to understand why this change is happening and find strategies to address it.
Key factors may include cost, convenience, and technological trends.
[end sys1]

[sys2]
**2.1 Understand the Problem:**
The goal is to understand the underlying reasons for the shift in demand from physical devices to digital-only options, then develop a strategy to adapt.

*Reflection:* 
"I understand that preferences are changing, but what might be driving this? Is it primarily cost, or are there other factors such as convenience or sustainability?"

*Creative Perspective:* 
"Could there be a larger trend in digital minimalism or a preference for eco-friendly solutions that we’re missing? What unseen motivations might explain this shift?"

**2.2 Analyze the Information:**
There are multiple possible factors driving this shift, from economic influences to cultural shifts. It’s essential to isolate each factor and understand its impact.

*Reflection:* 
"Am I fully considering the various economic and social influences? Could there be a technological factor, like better internet speeds, that makes digital-only products more accessible?"

*Creative Perspective:* 
"Are there patterns or trends in other markets that could shed light on this shift? Could this be part of a larger trend toward virtual experiences?"

**2.3 Generate Hypotheses:**
1. Customers prefer digital options due to lower costs. (Confidence: 0.8, Creative: 0.4)
2. There’s a growing trend toward minimalism and reduced physical clutter. (Confidence: 0.7, Creative: 0.7)
3. Digital products offer greater flexibility and ease of use. (Confidence: 0.6, Creative: 0.6)
4. Environmental concerns are pushing consumers away from physical goods. (Confidence: 0.6, Creative: 0.8)
5. Advances in tech make digital-only options more functional. (Confidence: 0.8, Creative: 0.5)
6. Pandemic-era remote work increased demand for digital solutions. (Confidence: 0.7, Creative: 0.6)
7. Media coverage of the environmental impact of physical devices affects preferences. (Confidence: 0.5, Creative: 0.7)
8. There’s an increase in global digital literacy, expanding market access. (Confidence: 0.6, Creative: 0.6)
9. Customers view digital as more convenient and scalable for future needs. (Confidence: 0.7, Creative: 0.5)
10. Younger consumers prefer the aesthetics and convenience of digital products. (Confidence: 0.6, Creative: 0.6)

*Reflection:* 
"Have I considered all possible influences? Are there any surprising factors that could explain this shift?"

*Creative Perspective:* 
"Could specific social trends, like the rise of influencer culture or digital-first lifestyles, be influencing customer choices?"

**2.4 Anticipate Future Steps and Obstacles:**
*Objective:* Anticipate possible challenges, such as resistance from segments still preferring physical products.

*Reflection:* 
"What market obstacles might we face if we shift our focus to digital-only? Are there sub-segments that still prioritize physical products?"

*Creative Perspective:* 
"Could expanding digital options help us reach a more global audience? Are there emerging trends that we could leverage in our strategy?"

[end sys2]

[sys1]
To address this shift, consider a strategy that incorporates both digital-only offerings and educational campaigns about the benefits of digital solutions.
Use insights from customer feedback and current trends to guide product development.
Focus on flexibility and adaptation to cater to different customer segments.
[end sys1]


1. Field of the Invention
The present invention relates generally to semiconductor circuit devices and, more particularly, to a voltage boosting circuit incorporated in a semiconductor circuit device.
2. Description of the Related Art
In recent years, there have been provided dynamic random access memories (DRAMs) which have a voltage boosting circuit in a chip and In which memory cells are driven through word lines or other wiring by using a voltage boosted by the voltage boosting circuit. There has been a challenge to reduce current noise in this kind of voltage boosting circuit. Conventional voltage boosting circuits designed to reduce current noise and to obtain a sufficiently high boosted voltage include an oscillator circuit which generates a plurality of oscillating signals having different timing from each other and a plurality of pumping circuits each having a capacitor of a small capacitance and transistors of a small size in corresponding to the respective oscillating signals.
FIG. 1 is a circuit diagram showing a conventional voltage boosting circuit. Referring to FIG. 1, boosting circuit 100 has oscillator circuit 120, oscillator output signal latch circuit 130, pumping circuit 140, and boosted voltage level determination circuit 150. Each of these circuits has the ground level as a reference potential and operates by an external power supply voltage VCC.
Oscillator output signal latch circuit 130 includes xcfx861 latch circuit 131, xcfx862 latch circuit 132, . . . , and xcfx86n latch circuit 13n. Pumping circuit 140 includes xcfx861 pumping circuit 141, xcfx862 pumping circuit 142, . . . , and xcfx86n pumping circuit 14n.
Signals xcfx861-xcfx86n sent from oscillator circuit 120 are respectively given to xcfx861-xcfx86n latch circuits 131-13n. Signals xcfx861A-xcfx86nA respectively sent from xcfx861-xcfx86n latch circuits 131-13n are respectively given to xcfx861-xcfx86n pumping circuits 141-14n. The outputs of xcfx861-xcfx86n pumping circuits 141-14n are connected to a common point, at which a boosted voltage VPP is generated. A signal VPUP sent from boosted level determination circuit 150 is given to oscillator circuit 120 and to the xcfx861-xcfx86n latch circuits 131-13n.
A desired voltage to be obtained by boosting is set in boosting circuit 100. Boosted level determination circuit 150 compares the boosted voltage VPP provided from the boosting circuit 100 with a set voltage sets the signal VPUP to xe2x80x9cHxe2x80x9d when the boosted voltage VPP is lower than the set voltage, and sets the signal VPUP to xe2x80x9cLxe2x80x9d when the boosted voltage VPP is higher than the set voltage.
Oscillator circuit 120 sends a plurality of oscillating signals one after another at equally shifted times when the signal VPUP Is at xe2x80x9cHxe2x80x9d. For example, oscillator circuit 120 has inverters forming n stages (n: an odd number) connected in a chain configuration. Oscillator circuit 120 sends no oscillating signal when the signal VPUP is at xe2x80x9cLxe2x80x9d.
FIG. 2 is a circuit diagram showing an example of a basic configuration of the oscillator circuit. Referring to FIG. 2, Oscillator circuit 120 has a basic configuration in which odd number of inverters being connected in a ring-like chain. The inverters send signals xcfx861-xcfx86n. In FIG. 2, a circuit portion relating to signal VPUP is not shown.
FIG. 3 is a timing chart showing the waveforms of signals xcfx861-xcfx86n. Referring to FIG. 3, signals xcfx861-xcfx86n are oscillating signals which have transition timings successively shifted and phases alternately reversed. The cycle of each of signals xcfx861-xcfx86n is T. The time between edges of the adjacent signals, e.g., between the rising edge of the signal xcfx861 and the falling edge of signal xcfx862 is dT=T/(2xc3x97n), which is the waveform transmission time by the inverters.
Each of xcfx861-xcfx86n latch circuits 131-13constituting oscillator output signal latch circuit 130 uses signal VPUP as an enable signal. xcfx861-xcfx86n latch circuits 131-13n send signals xcfx861-xcfx86n respectively as signals xcfx861A-xcfx86nA when signal VPUP is at xe2x80x9cHxe2x80x9d. At this time, signals xcfx861A-xcfx86nA are respectively in phase with signals xcfx861-xcfx86n. xcfx861-xcfx86n latch circuits 131-13n hold the states of signals xcfx861A-xcfx86nA when signal VPUP is at xe2x80x9cLxe2x80x9d.
xcfx861-xcfx86n pumping circuits 141-14n constituting the pumping circuit 140 are respectively supplied with signals xcfx861-xcfx86nA and perform boosting operations in synchronization with signals xcfx86A-xcfx86nA. The output terminals of the xcfx861-xcfx86n pumping circuits 141-14n are connected to the common point, i.e., the output terminal of pumping circuit 140, through which boosted voltage VPP is output.
FIG. 4 is a circuit diagram showing an example of the configuration of xcfx861-xcfx86n pumping circuits. All of xcfx861-xcfx86n pumping circuits are identical in configuration. In FIG. 4, xcfx861 pumping circuit is shown as a representative. Referring to FIG. 4, xcfx861 pumping circuit is constituted by inverters INV0 and INV1, capacitor C0, and diodes DI0 and DI1.
Signal xcfx861A is given to inverter INV0. Inverters INV0 and INV1 are connected in series. The output terminal of inverter INV1 and one terminal of capacitor C0 are connected to each other at a connection point A. The other terminal of the capacitor C0, the cathode of diode DI0 and the anode of diode DI1 are connected to each other at a connection point B. External power supply voltage VCC is supplied to the anode of diode DI0. The cathodes of diodes DI1 of xcfx861-xcfx86n pumping circuits 141-14n are connected to the common point through which boosted voltage VPP is output.
FIG. 5 is a timing chart showing the boosting operation of xcfx861 pumping circuit shown in FIG. 4. Referring to FIG. 5, signal xcfx861A is an oscillating signal having external power supply voltage VCC and reference voltage GND alternately sent. The signal waveform at the connection point A is slightly delayed from signal xcfx861A.
When the potential at the connection point A is reference voltage GND level, the connection point B is precharged to external power supply voltage VCC through diode DI0. When a transition from reference voltage GND to external power supply voltage VCC is effected at the connection point A, the potential at the connection point B is increased by an amount corresponding to external power supply voltage VCC due to the coupling through capacitor C0. Accordingly, a transition of the potential at the connection point B is made from external power supply voltage VCC to a voltage (2xc3x97VCC) twice external power supply voltage VCC. Thus, xcfx861 pumping circuit 141 can generate boosted voltage VPP higher than external power supply voltage VCC. The circuit for control of diodes DI0 and DI1 shown in FIG. 4 is not illustrated.
In general, the inverter is made by combining a Pch transistor (not shown) and an Nch transistor (not shown). Capacitor C0 is charged by supply of a current caused by external power supply voltage VCC to flow through the Pch transistor of inverter INV1. Capacitor C0 is discharged by the flow of a current from the connection point A to reference voltage GND through the Nch transistor of inverter INV1.
Similarly, the connection point B is precharged to external power supply voltage VCC by supply of a current caused by external power supply voltage VCC to flow to the connection point B through diode DI0.
The gate capacity of inverter INV1 is charged and discharged by a charge current caused by external power supply voltage VCC to flow from inverter INV0 to inverter INV1 and a discharge current caused to flow from inverter INV1 to reference voltage GND.
In the voltage boosting circuit, noise is caused due to the charge current from external power supply voltage VCC and the discharge current to reference voltage GND.
An electric charge which can be sent from the xcfx861 pumping circuit for boosting is determined by the capacitance of capacitor C0. It is necessary that the sizes of the transistors constituting inverters INV1 and INV0 and diodes DI0 and DI1, which drives e capacitor C0, are determined such that capacitor C0 can be efficiently charged and discharged. To obtain suitable boosted signal VPP, the pumping power could be increased, and a large pumping capacitor and large transistors for a circuit such as inverter for driving the capacitor could be used. In such a case, however, charge/discharge current noise of capacitor CO would be increased.
To obtain a sufficiently high boosting effect while limiting current noise, the voltage boosting circuit shown in FIG. 1 is arranged in such a manner that oscillator circuit 120 has a plurality of outputs and a plurality of xcfx861-xcfx86n pumping circuits 141-14n each having a capacitor of a small capacitance and transistors of a small size are provided.
Description will be made of the operation of the conventional voltage boosting circuit.
FIG. 6 is a timing chart for explaining the operation of the conventional voltage boosting circuit. FIG. 6 shows the waveforms of signal VPUP, signals xcfx861-xcfx86n sent from oscillator circuit 120 and signals xcfx861A-xcfx86n sent from latch circuits 131-13n.
Referring to FIG. 6, signals xcfx861-xcfx86n and xcfx861A-xcfx86nA are maintained at a constant value and do not make no transition at time T0 since signal VPUP is at xe2x80x9cLxe2x80x9d.
Signal VPUP makes a transition from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d in the time period from time T0 to time Ts to start an initialization operation of the voltage boosting circuit.
When the initialization operation of the voltage boosting circuit is started, oscillator circuit 120 sends n oscillating signals, at times successively shifted by the time period corresponding to cycle T. The length of each of time periods Ta and Tb in FIG. 6 is equal to cycle T.
Signals xcfx861-xcfx86n are supplied respectively as signals xcfx861A-xcfx86nA to pumping circuit 140 by latch circuits 131-13n in oscillator output signal latch circuit 130. xcfx861-xcfx86n pumping circuits 141-14n constituting the pumping circuit 140 perform the boosting operations in response to the transitions of signals xcfx861A-xcfx86nA. The outputs from the xcfx861-xcfx86n pumping circuits 141-14n ar combined to supply boosted voltage VPP to the outside. Signals xcfx861A-xcfx86nA each make transitions from reference potential GND to external power supply voltage VCC at different times, so that no coincidence of current noise peaks occurs.
FIG. 7 is a timing chart showing the operation of the conventional voltage boosting circuit and the waveform of the output signal. FIG. 7 illustrates a case where n=5 and where pumping circuits each configured with two of the circuit that shown in FIG. 4 so that the boosting circuit operates not only at the time of transition from reference voltage GND to external power supply voltage VCC but also at the time of transition from external power supply voltage VCC to reference voltage GND.
In the lower section of FIG. 7, the waveforms of signal VPUP and signals xcfx861A-xcfx865A are shown. In the upper section of FIG. 7, currents I (solid line) sent from xcfx861-xcfx86n pumping circuits 141-14n and a current Itotal (dotted line) obtained by combining currents I are shown.
Referring to FIG. 7, signal VPUP makes a transition from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d in the time period from time T0 to time T1 to start the boosting operation. At time T1, signal xcfx861A makes a transition from GND to VCC. Subsequently, signals xcfx862A-xcfx865A make transitions one after another at intervals of time T2xe2x88x92T1=dT=(one cycle T)/(2xc3x975). Thereafter, signals xcfx861A-xcfx865A make transitions alternately to GND and VCC at times shifted by dT. As can be understood from FIG. 7, the transition waveforms of the odd-numbered signals xcfx861A, xcfx863A, and xcfx865A are in reversed phase with respect to those of the even-numbered signals xcfx862A and xcfx864A.
In response to the transitions of signals xcfx861A-xcfx86nA, transitions of currents I (solid line) output from xcfx861-xcfx86n pumping circuits 141-14n are made. Current Itotal (dotted line) obtained by combining the outputs from the xcfx861-xcfx86n pumping circuits 141-14n rises during the time period from T1 to T4 and is generally constant after time T5. Current Itotal after time T5 is a saturated consumption current I0. The consumption current at the time of starting of the pumping circuit when signal VPUP makes a transition from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d has a current changing rate dI/dT in the time period from T1 to T4, which is considered to be a noise source. This is because, if the current changing rate dI/dT is large, noise due to the inductance of wiring including the lead frame of the semiconductor device is large.
Another conventional voltage boosting circuit, e.g., one described in Japanese Patent Laid-Open No. 11-25673 has a delay circuit which generates signals corresponding to signals xcfx861A-xcfx86nA shown in FIG. 1.
A further conventional voltage boosting circuit has two operating modes: a standby mode and an active mode (e.g., Japanese Patent Laid-Open No. 9-320268). In this kind of voltage boosting circuit, one of the two operating modes is selected according to the amount of electric charge to be supplied.
The voltage boosting circuit described in Japanese Patent Laid-Open No. 9-320268 has a plurality of pumping circuits. In the standby mode, only part of the pumping circuits are successively operated. In the active mode, all the pumping circuits are continuously operated.
The above-described conventional arts have problems described below.
The conventional voltage boosting circuit shown in FIG. 1 is arranged to reduce current noise in such a manner that oscillator circuit 120 has a plurality of outputs and pumping circuit 140 is constituted by xcfx861-xcfx86n pumping circuits 141-14n having a capacitor of a small capacitance and transistors of a small size. After a lapse of a certain length of time from a start of the operation, therefore, the current value becomes generally constant and the current changing rate dI/dT becomes zero, as shown in FIG. 7. Thus, noise due to the current changing rate dI/dT becomes zero.
However, when the pumping operation is started, the rate of change in current (dI/dT) of the conventional boosting circuit is high, as shown in FIG. 7. An abrupt current change (dI/dT) of external power supply voltage VCC or reference voltage GND can cause noise by a self-inductance or a mutual inductance.
In semiconductor circuit devices such as DRAMs, a lead frame and bonding wires for connection between pins and a chip exist. Also, wires for external power supply voltage VCC and reference voltage GND exist adjacent to wires to address and data pins or the like. Therefore, the characteristics of input of addresses, data or the like are degraded by the noise from the wires.
In the conventional voltage boosting circuit described in Japanese Patent Laid-Open No. 11-25673, a delay circuit is used. The delay time of the delay circuit, however, varies under the influence of manufacturing process variations. In the voltage boosting circuit arranged as described in Japanese Patent Laid-Open No. 11-25673, therefore, there is a possibility of nonuniformity of the currents consumed by the pumping circuits during one cycle of the oscillation signals generated by the oscillator. The output of the oscillator circuit described in Japanese Patent Laid-Open No. 11-25673 is a signal taken out from one point and is supplied to the pumping circuits with delays added by the delay circuit. The signal passed through the delay circuit is susceptible to the influence of the above-mentioned process variations, there is a tendency toward nonuniformity in the time periods during which the pumping operations are performed in one oscillating cycle, and it is difficult to perform control with accuracy. In some cases, therefore, failure to control the current changing rate dI/dT within the desired gradient range occurs, which is a cause of generation of noise. There is a possibility of the current changing rate dI/dT becoming considerably large at the time of starting of the operation in particular.
The conventional voltage boosting circuit described in Japanese Patent Laid-Open No. 9-320268 has the two operating modes, i.e., the standby mode and the active mode, for the boosting operation. This voltage boosting circuit controls the current supply capacity by changing the number of pumping circuits with respect to different consumption currents from VPP in the operating modes. However, the operation of this voltage boosting circuit at the time of starting of the operation is the same as that of the voltage boosting circuit shown in FIG. 1, In that the pumping circuits (pumping means) perform boosting at times successively shifted by the delay circuit (delay element). Therefore, the changing rate dI/dT in consumption current at the time of starting of the voltage boosting circuit described in Japanese Patent Laid-Open No. 9-320268 is as steep as the changing dI/dT in current Itotal shown in FIG. 7.
An object of the present invention is to provide a voltage boosting circuit in which an abrupt change in current at the time of starting of the operation is limited to reduce noise.
To achieve the above-described object, according to the present invention, there is provided a voltage boosting circuit having an oscillator circuit, a pumping circuit, a boosting power control circuit and an enable circuit. The oscillator circuit outputs a plurality of oscillating signals differing in edge timing from each other. A plurality of pumping circuits are provided in correspondence with oscillating signals. Each pumping circuit performs a boosting operation by charging and discharging a pumping capacitor by using the corresponding one of the oscillating signals. The pumping circuits generate a boosted voltage by combining their outputs signals. The boosting power control circuit controls the boosting power of each pumping circuit according to an enable signal. An enable circuit counts the number of edges of at least one of the oscillating signals, and generates the enable signal to instruct the boosting power control circuit to reduce the boosting power of the pumping circuit until the count value becomes a set value.
According to the present invention, the boosting power of at least one of the plurality of pumping circuits for performing boosting operations by a plurality of oscillated signals is restricted for several cycles of the signal after a start of the boosting operation by the enable circuit and the boosting power control circuit. A rate of a change in the current for the boosting operation is thereby reduced to suppress noise accompanying the change in the current.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with references to the accompanying drawings which illustrate examples of the present invention.