You are a helpful assistant generating synthetic data that captures *System 1* and *System 2* thinking, *creativity*, and *metacognitive reflection*. Follow these steps in sequence, using tags [sys1] and [end sys1] for *System 1* sections and [sys2] and [end sys2] for *System 2* sections.

1. *Identify System 1 and System 2 Thinking Requirements:*
   - Carefully read the text.
   - Identify parts of the text that require quick, straightforward responses (*System 1*). Mark these sections with [sys1] and [end sys1].
   - Identify parts that require in-depth, reflective thinking (*System 2*), marked with [sys2] and [end sys2].

2. *Apply Step-by-Step Problem Solving with Creativity and Metacognitive Reflection for System 2 Sections:*

   *2.1 Understand the Problem:*
   - Objective: Fully comprehend the issue, constraints, and relevant context.
   - Reflection: "What do I understand about this issue? What might I be overlooking?"
   - Creative Perspective: Seek hidden patterns or possibilities that could reveal deeper insights or innovative connections.

   *2.2 Analyze the Information:*
   - Objective: Break down the problem logically.
   - Reflection: "Am I considering all factors? Are there any assumptions that need challenging?"
   - Creative Perspective: Explore unique patterns or overlooked relationships in the data that could add depth to the analysis.

   *2.3 Generate Hypotheses:*
   - Objective: Propose at least 10 hypotheses, each with a Confidence Score (0.0 to 1.0) and Creative Score (0.0 to 1.0), reflecting originality, surprise, and utility.
   - Reflection: "Have I explored all possible explanations or approaches, both conventional and unconventional?"
   - Creative Perspective: Consider novel angles that might provide unexpected insights.

   *2.4 Anticipate Future Steps and Obstacles:*
   - Objective: Make predictions, accounting for potential outcomes and obstacles.
   - Reflection: "What challenges might I face? Is my plan flexible for different scenarios?"
   - Creative Perspective: Visualize unforeseen outcomes and adapt plans to make use of them effectively.

   *2.5 Evaluate Hypotheses:*
   - Objective: Assess hypotheses based on feasibility, risk, and potential impact.
   - Evaluation: Refine Confidence and Creative Scores as needed.
   - Reflection: "Am I unbiased in my assessment? Which options fit best with the overall objectives?"
   - Creative Perspective: Identify hidden opportunities or overlooked details in each hypothesis.

   *2.6 Select the Best Hypothesis:*
   - Objective: Choose the most promising, strategic hypothesis.
   - Reflection: "Why does this hypothesis stand out? How does it uniquely address the issue?"
   - Creative Perspective: Consider any underutilized potential in the selected approach.

   *2.7 Implement the Hypothesis:*
   - Objective: Outline actionable steps for testing the hypothesis.
   - Reflection: "Is this plan practical? What resources or preparation are required?"
   - Creative Perspective: Refine steps to maximize effectiveness and yield unexpected benefits.

   *2.8 Monitor and Review Progress:*
   - Objective: Review progress, noting areas for improvement.
   - Reflection: "What’s working well? What could be improved?"
   - Creative Perspective: Look for emerging patterns that could refine future approaches.

   *2.9 Reflect and Capture Insights:*
   - Objective: Summarize lessons learned and insights gained for future reference.
   - Reflection: "What new understanding has emerged from this process?"
   - Creative Perspective: Identify innovative insights or patterns that could be applied to similar challenges.

3. *Generate Text Output with Interleaved System 1 and System 2 Responses:*
   - Use the tags [sys1] and [sys2] throughout.
   - Aim for a lengthier, detailed response. Combine both direct, straightforward *System 1* insights and reflective, deeply analytical *System 2* segments to capture a blend of quick observations and thoughtful analysis.

---

### *Example Input Text:*

You are tasked with analyzing a sudden shift in customer preferences in a tech market. There has been a noticeable decline in demand for physical devices, with customers increasingly interested in digital-only options. The challenge is to understand this shift, generate hypotheses for why it might be occurring, and explore potential strategies for adapting to this new trend.

---

### *Processed Output with System 1 and System 2 Thinking:*

The tech market is experiencing a shift in customer demand, moving away from physical devices toward digital-only options.

[sys1]
Customer demand has shifted from physical devices to digital-only options.
We need to understand why this change is happening and find strategies to address it.
Key factors may include cost, convenience, and technological trends.
[end sys1]

[sys2]
**2.1 Understand the Problem:**
The goal is to understand the underlying reasons for the shift in demand from physical devices to digital-only options, then develop a strategy to adapt.

*Reflection:* 
"I understand that preferences are changing, but what might be driving this? Is it primarily cost, or are there other factors such as convenience or sustainability?"

*Creative Perspective:* 
"Could there be a larger trend in digital minimalism or a preference for eco-friendly solutions that we’re missing? What unseen motivations might explain this shift?"

**2.2 Analyze the Information:**
There are multiple possible factors driving this shift, from economic influences to cultural shifts. It’s essential to isolate each factor and understand its impact.

*Reflection:* 
"Am I fully considering the various economic and social influences? Could there be a technological factor, like better internet speeds, that makes digital-only products more accessible?"

*Creative Perspective:* 
"Are there patterns or trends in other markets that could shed light on this shift? Could this be part of a larger trend toward virtual experiences?"

**2.3 Generate Hypotheses:**
1. Customers prefer digital options due to lower costs. (Confidence: 0.8, Creative: 0.4)
2. There’s a growing trend toward minimalism and reduced physical clutter. (Confidence: 0.7, Creative: 0.7)
3. Digital products offer greater flexibility and ease of use. (Confidence: 0.6, Creative: 0.6)
4. Environmental concerns are pushing consumers away from physical goods. (Confidence: 0.6, Creative: 0.8)
5. Advances in tech make digital-only options more functional. (Confidence: 0.8, Creative: 0.5)
6. Pandemic-era remote work increased demand for digital solutions. (Confidence: 0.7, Creative: 0.6)
7. Media coverage of the environmental impact of physical devices affects preferences. (Confidence: 0.5, Creative: 0.7)
8. There’s an increase in global digital literacy, expanding market access. (Confidence: 0.6, Creative: 0.6)
9. Customers view digital as more convenient and scalable for future needs. (Confidence: 0.7, Creative: 0.5)
10. Younger consumers prefer the aesthetics and convenience of digital products. (Confidence: 0.6, Creative: 0.6)

*Reflection:* 
"Have I considered all possible influences? Are there any surprising factors that could explain this shift?"

*Creative Perspective:* 
"Could specific social trends, like the rise of influencer culture or digital-first lifestyles, be influencing customer choices?"

**2.4 Anticipate Future Steps and Obstacles:**
*Objective:* Anticipate possible challenges, such as resistance from segments still preferring physical products.

*Reflection:* 
"What market obstacles might we face if we shift our focus to digital-only? Are there sub-segments that still prioritize physical products?"

*Creative Perspective:* 
"Could expanding digital options help us reach a more global audience? Are there emerging trends that we could leverage in our strategy?"

[end sys2]

[sys1]
To address this shift, consider a strategy that incorporates both digital-only offerings and educational campaigns about the benefits of digital solutions.
Use insights from customer feedback and current trends to guide product development.
Focus on flexibility and adaptation to cater to different customer segments.
[end sys1]


/* $NoKeywords:$ */
/**
 * @file
 *
 * AMD Integrated Debug Option Backend Routines
 *
 * Contains AMD AGESA debug macros and library functions
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:      AGESA
 * @e sub-project:  IDS
 * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
 */
/*****************************************************************************
 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
 *       its contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ******************************************************************************
 */
/*----------------------------------------------------------------------------------------
 *                             M O D U L E S    U S E D
 *----------------------------------------------------------------------------------------
 */

#include "AGESA.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "IdsHt.h"
#include "amdlib.h"
#include "mm.h"
#include "mn.h"
#include "cpuRegisters.h"
#include "heapManager.h"
#include "cpuFamilyTranslation.h"
#include "GeneralServices.h"
#include "IdsLib.h"
#include "IdsNvToCmos.h"
#include "Filecode.h"
#ifdef __IDS_EXTENDED__
  #include IDS_EXT_INCLUDE (IdsInternalLib)
#endif
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)

#define FILECODE PROC_IDS_CONTROL_IDSCTRL_FILECODE

/*----------------------------------------------------------------------------
 *                            EXPORTED FUNCTIONS
 *
 *----------------------------------------------------------------------------
 */


extern CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[];


/**
 * IDS option hooking function dispatcher.
 *
 * This is the top level interface for IDS option Backend code.
 *
 * @param[in]     IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION
 * @param[in,out] DataPtr   Data pointer.
 * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 **/
IDS_STATUS
AmdIdsCtrlDispatcher (
  IN       AGESA_IDS_OPTION IdsOption,
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader
  )
{
  IDS_NV_ITEM *IdsNvPtr;
  IDS_STATUS   ReturnFlag;
  IDS_STATUS ExtendedFlag;

  IdsNvPtr  = NULL;
  ReturnFlag = IDS_SUCCESS;

  ASSERT (StdHeader != NULL);
  if (AmdGetIdsNvTable ((VOID **) &IdsNvPtr, StdHeader) != AGESA_SUCCESS) {
    IDS_HDT_CONSOLE (IDS_TRACE , "IDS initialize\n");
    AmdIdsCtrlInitialize (StdHeader);
    AmdGetIdsNvTable ((VOID **) &IdsNvPtr, StdHeader);
  }

  if (IdsNvPtr != NULL) {
    ReturnFlag = IdsParseFeatTbl (IdsOption, IdsContorlFeats, DataPtr, IdsNvPtr, StdHeader);
    ExtendedFlag = IDS_EXTENDED_HOOK (IdsOption, DataPtr, IdsNvPtr, StdHeader);
    if (ExtendedFlag != IDS_SUCCESS) {
      ReturnFlag = IDS_UNSUPPORTED;
    }
  }
  return ReturnFlag;
}

/**
 * Ids code for parse IDS feat table.
 *
 * Feat table in IDS is used to decribe the IDS support feat and its according family,handler.
 *
 * @param[in]     PIdsFeatTbl point to Ids Feat table
 * @param[in]     IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION
 * @param[in,out] DataPtr   Data pointer.
 * @param[in]     IdsNvPtr   Ids Nvram pointer.
 * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 **/
IDS_STATUS
IdsParseFeatTbl (
  IN       AGESA_IDS_OPTION IdsOption,
  IN       CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[],
  IN OUT   VOID *DataPtr,
  IN       IDS_NV_ITEM *IdsNvPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader
  )
{
  UINT16 i;
  AGESA_STATUS Tmpsts;
  CPU_LOGICAL_ID CpuLogicalId;
  BOOLEAN No_Check_Bsp;
  CONST IDS_FAMILY_FEAT_STRUCT *PIdsFeat;
  IDS_STATUS ReturnFlag;

  ReturnFlag = IDS_SUCCESS;

  for (i = 0; PIdsFeatTbl[i] != NULL; i++) {
    PIdsFeat = PIdsFeatTbl[i];
    //Does specified IdsOption reached
    if (PIdsFeat->IdsOption == IdsOption) {
      //check if bsp only
      if (PIdsFeat->IsBsp) {
        No_Check_Bsp = 0;
      } else {
        No_Check_Bsp = 1;
      }
      if (No_Check_Bsp || IsBsp (StdHeader, &Tmpsts)) {
        //Does Family Match required
        GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
        if ((CpuLogicalId.Family) & (PIdsFeat->CpuFamily)) {
          //Excute the code for specific Ids Feat
          IDS_HDT_CONSOLE (IDS_TRACE, "\tIDS Excute HookPoint [%x] Start\n", IdsOption);
          ReturnFlag = PIdsFeat->pf_idsoption (DataPtr, StdHeader, IdsNvPtr);
          IDS_HDT_CONSOLE (IDS_TRACE, "\tIDS Excute HookPoint [%x] End\n", IdsOption);
        }
      }
    }
  }
  return ReturnFlag;
}

/**
 *
 *  IDS Object Initialization
 *
 *  Initializer routine that will be invoked by the wrapper to initialize
 *  the data buffer in heap for the IDS object. It includes IDS control
 *  structure, IDS mem table and IDS GRA table.
 *
 *  @param[in,out] StdHeader    The Pointer of IDS Initial Parameter
 *
 *  @retval AGESA_SUCCESS       Success to init IDS Object.
 *  @retval AGESA_ERROR         Fail to init IDS Object.
 *
 **/

#ifdef IDS_HEAP_2STAGES
  #define IDS_HEAP_PERSIST_EARLY  HEAP_LOCAL_CACHE
  #define IDS_HEAP_ASSERTION_LATE
#else
  #define IDS_HEAP_PERSIST_EARLY  HEAP_SYSTEM_MEM
  #define IDS_HEAP_ASSERTION_LATE ASSERT(FALSE)
#endif

AGESA_STATUS
AmdIdsCtrlInitialize (
  IN OUT   AMD_CONFIG_PARAMS *StdHeader
  )
{
  AGESA_STATUS status;
  AGESA_STATUS IgnoreStatus;
  UINT16 NvTblSize;
  UINT16 i;
  IDS_NV_ITEM IdsNvTable[IDS_NUM_NV_ITEM];
  IDS_NV_ITEM *NvTable;
  IDS_NV_ITEM *NvPtr;
  IDS_CONTROL_STRUCT *IdsCtrlPtr;
  IDS_CALLOUT_STRUCT IdsCalloutData;
  ALLOCATE_HEAP_PARAMS AllocHeapParams;
  UINT16 MemTblSize;
  UINT8 HeapPersist;

  NvTblSize = 0;
  MemTblSize = 0;
  HeapPersist = HEAP_SYSTEM_MEM;
  //Heap status with HEAP_LOCAL_CACHE, will allocate heap with HEAP_LOCAL_CACHE
  //with HEAP_TEMP_MEM  HEAP_SYSTEM_MEM  HEAP_DO_NOT_EXIST_ANYMORE  HEAP_S3_RESUME
  // with allocate with HEAP_SYSTEM_MEM
  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
    MemTblSize = IDS_MAX_MEM_ITEMS;
    HeapPersist = IDS_HEAP_PERSIST_EARLY;
  } else if ((StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_YET) || (StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_ANYMORE)) {
    return AGESA_ERROR;
  } else {
    IDS_HEAP_ASSERTION_LATE;
  }

  IdsCalloutData.IdsNvPtr = IdsNvTable;
  IdsCalloutData.StdHeader = *StdHeader;
  IdsCalloutData.Reserved = FALSE;
//init IDS_CALLOUT_STRUCT before calling out, give NVITEM default value
  for (i = AGESA_IDS_EXT_ID_START; i < IDS_NUM_NV_ITEM; i++) {
    IdsNvTable[i].IdsNvId = i;
    IdsNvTable[i].IdsNvValue = AGESA_IDS_DFT_VAL;
  }

  AGESA_TESTPOINT (TpIfBeforeGetIdsData, StdHeader);
  if (AgesaGetIdsData (IDS_CALLOUT_INIT, &IdsCalloutData) == AGESA_SUCCESS) {
    IDS_HDT_CONSOLE (IDS_TRACE , "Get IDS options from CBS Done\n");
    NvTable = IdsCalloutData.IdsNvPtr;
    NvPtr = NvTable;
    while (NvPtr->IdsNvId != AGESA_IDS_NV_END) {
      IDS_HDT_CONSOLE (IDS_TRACE , "\tIDS_ID (%X) = %X\n", NvPtr->IdsNvId, NvPtr->IdsNvValue);
      NvTblSize  ++;
      NvPtr ++;
    }
    NvTblSize  ++;

    AllocHeapParams.RequestedBufferSize = sizeof (IDS_CONTROL_STRUCT);
    AllocHeapParams.RequestedBufferSize += NvTblSize  * sizeof (IDS_NV_ITEM);
    AllocHeapParams.RequestedBufferSize += MemTblSize * sizeof (MEM_TABLE_ALIAS);
    AllocHeapParams.RequestedBufferSize += IDS_EXTENDED_HEAP_SIZE;
    AllocHeapParams.BufferHandle = IDS_CONTROL_HANDLE;
    AllocHeapParams.Persist = HeapPersist;

    //
    // Allocate data buffer in heap
    //
    if (HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader) == AGESA_SUCCESS) {
      //
      // Initialize IDS Date Buffer
      //
      IdsCtrlPtr = (IDS_CONTROL_STRUCT *) AllocHeapParams.BufferPtr;
      IdsCtrlPtr->IgnoreIdsDefault = (BOOLEAN) IdsCalloutData.Reserved;
      IdsCtrlPtr->IdsHeapMemSize = AllocHeapParams.RequestedBufferSize;
      IdsCtrlPtr->IdsNvTableOffset = sizeof (IDS_CONTROL_STRUCT);
      IdsCtrlPtr->IdsMemTableOffset = IdsCtrlPtr->IdsNvTableOffset + NvTblSize  * sizeof (IDS_NV_ITEM);
      IdsCtrlPtr->IdsExtendOffset = IdsCtrlPtr->IdsMemTableOffset + MemTblSize * sizeof (MEM_TABLE_ALIAS);

      NvPtr = (IDS_NV_ITEM *) (AllocHeapParams.BufferPtr + IdsCtrlPtr->IdsNvTableOffset);
      for (i = 0; i < NvTblSize ; i++) {
        NvPtr->IdsNvId = NvTable->IdsNvId;
        NvPtr->IdsNvValue = NvTable->IdsNvValue;
        NvPtr ++;
        NvTable ++;
      }
      status = AGESA_SUCCESS;
    } else {
      status = AGESA_ERROR;
    }
  } else {
    if (!IsBsp (StdHeader, &IgnoreStatus)) {
      status = IDS_AP_GET_NV_FROM_CMOS (StdHeader);
    } else {
      IDS_HDT_CONSOLE (IDS_TRACE , "Get IDS options from CBS Fail\n");
      status = AGESA_ERROR;
    }
  }
  AGESA_TESTPOINT (TpIfAfterGetIdsData, StdHeader);

  return status;
}
/**
 *  IDS Backend Function for Target Pstate
 *
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubTargetPstate (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS tarpst;
  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;

  IDS_NV_READ_SKIP (tarpst, AGESA_IDS_NV_TARGET_PSTATE, IdsNvPtr, StdHeader) {
    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) tarpst, (BOOLEAN) FALSE, StdHeader);
  }
  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for HdtOut
 *
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubHdtOut (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS idsvalue;

//set HDTOUT En/Dis
  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_HDTOUT, IdsNvPtr, StdHeader) {
//if HDTOUT set to enable, set the corresponding DR2 flag to 0x99cc
    if (idsvalue == 1) {
      LibAmdWriteCpuReg (DR2_REG, 0x99cc);
    }
  }
  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for Power down mode
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubPowerDownCtrl (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  AMD_POST_PARAMS *PostParamsPtr;
  MEM_PARAMETER_STRUCT *RefPtr;
  IDS_STATUS idsvalue;
  MEM_DATA_STRUCT * memdataptr;

  PostParamsPtr = (AMD_POST_PARAMS *)DataPtr;
  memdataptr = PostParamsPtr->MemConfig.MemData;
  RefPtr = memdataptr->ParameterListPtr;

  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_MEMORY_POWER_DOWN, IdsNvPtr, StdHeader) {
    //if the idsvalue isn't auto do the override
    if (idsvalue < (IDS_STATUS)0x2) {
      RefPtr->EnablePowerDown = (BOOLEAN) idsvalue;
    }
  }
  return IDS_SUCCESS;
}

/**
 *  Backend Function for IDS Option Hook Point: IDS_UCODE
 *
 *  This function is used to disable UCode Installation if IDS Option disables ucode.
 *  The method is to force the number of total patches to ZERO.
 *
 *  @param[in,out]   DataPtr      The Pointer of Data to Override.
 *  @param[in,out]   StdHeader    The Pointer of AGESA Header.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubUCode (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS status;
  IDS_STATUS NvValue;
  UINT8 ** pUcodeptr;

  pUcodeptr = (UINT8 **) DataPtr;
  status = IDS_SUCCESS;
  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_UCODE, IdsNvPtr, StdHeader) {
    //Disabled
    if (NvValue == 0) {
      status = IDS_UNSUPPORTED;
    }
  }

  IDS_EXTENDED_CODE (
    IdsGetBvmUcodeBase (pUcodeptr, StdHeader);
  )

  return status;
}

/**
 *  IDS Backend Function for Post P-State
 *
 *  This function is used to set Post P-State which are CPU specifically.
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubPostPState (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  AMD_CPU_EARLY_PARAMS *PCpuEarlyParams;
  IDS_STATUS idsvalue;
  UINT8 curpstatesnum;

  PCpuEarlyParams = (AMD_CPU_EARLY_PARAMS *)DataPtr;
  curpstatesnum = IdsGetNumPstatesFamCommon (StdHeader);
  idsvalue = AmdIdsNvReader (AGESA_IDS_NV_POSTPSTATE, IdsNvPtr, StdHeader);

  if (idsvalue < (IDS_STATUS) (curpstatesnum + 3)) {
    switch (idsvalue) {
    case (IDS_STATUS) 0x0:
      // Auto
      break;
    case (IDS_STATUS) 0x1:
      // Maximum Performance
      PCpuEarlyParams->MemInitPState = 0;
      break;
    case (IDS_STATUS) 0x2:
      // Minimum Performance
      PCpuEarlyParams->MemInitPState = curpstatesnum - 1;
      break;
    default:
      PCpuEarlyParams->MemInitPState = (UINT8) (idsvalue - 3);
      break;
    }
  }
  return IDS_SUCCESS;
}



/**
 *  IDS Backend Function for Memory Mode Unganged
 *
 *  This function is used to override Memory Mode Unganged.
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubGangingMode (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS GangingMode;
  IDS_NV_READ_SKIP (GangingMode, AGESA_IDS_NV_DCT_GANGING_MODE, IdsNvPtr, StdHeader) {
    *((UINT8 *)DataPtr) = (UINT8) GangingMode;
  }
  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for Power Down Mode
 *
 *  This function is used to override Power Down Mode.
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubPowerDownMode (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS PowerDownMode;
  PowerDownMode = AmdIdsNvReader (AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, IdsNvPtr, StdHeader);
  if (PowerDownMode < (IDS_STATUS)0x2) {
    *((UINT8 *) DataPtr) = (UINT8)PowerDownMode;
  }
  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for Burst Length32
 *
 *  This function is used to override Burst Length32.
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubBurstLength32 (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS BurstLength32;
  BurstLength32 = AmdIdsNvReader (AGESA_IDS_NV_DRAM_BURST_LENGTH32, IdsNvPtr, StdHeader);
  if (BurstLength32 < (IDS_STATUS)0x2) {
    *((UINT8 *) DataPtr) = (UINT8)BurstLength32;
  }
  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for All Memory Clks Enable
 *
 *  This function is used to override All Memory Clks Enable
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubAllMemClkEn (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS AllMemClkEn;

  AllMemClkEn = AmdIdsNvReader (AGESA_IDS_NV_ALL_MEMCLKS , IdsNvPtr, StdHeader);
  if (AllMemClkEn < (IDS_STATUS)0x2) {
    *((UINT8 *) DataPtr) = (UINT8)AllMemClkEn;
  }

  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for Dll Shut Down
 *
 *  This function is used to override Dll Shut Down Option
 *
 *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
 *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 **/
IDS_STATUS
IdsSubDllShutDownSR (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  IDS_STATUS DllShutDownSR;
  IDS_NV_READ_SKIP (DllShutDownSR, AGESA_IDS_NV_DLL_SHUT_DOWN , IdsNvPtr, StdHeader) {
    *((UINT8 *) DataPtr) = (UINT8)DllShutDownSR;
  }
  return IDS_SUCCESS;
}

/**
 *  IDS Backend Function for HT Link Configuration
 *
 *  Provide the nv settings to the HT code in the form of a port override list.
 *  Create the list on the heap, so the HT code doesn't have to keep asking for it.
 *
 *  @param[out] Data         A reference to the HT Port Override List
 *  @param[in]  StdHeader    Header for library and services.
 *  @param[in] IdsNvPtr     The Pointer of NV Table.
 *
 *  @retval IDS_SUCCESS         Backend function is called successfully.
 *  @retval IDS_UNSUPPORTED     No Backend function is found.
 *
 */
IDS_STATUS
IdsSubHtLinkControl (
     OUT   VOID  *Data,
  IN       AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  ALLOCATE_HEAP_PARAMS AllocHeapParams;
  HTIDS_PORT_OVERRIDE_LIST   *ListReference;
  HTIDS_PORT_OVERRIDE_LIST   PortOverrideList;
  UINT32 HTlinkSocket;
  UINT32 HTlinkPort;
  UINT32 HTlinkFre;
  UINT32 HTlinkWidthIn;
  UINT32 HTlinkWidthOut;

  ASSERT (IdsNvPtr != NULL);
  ASSERT (Data != NULL);

  ListReference = Data;
  *ListReference = NULL;
  // Allocated the number of portlist override option sets supported (currently 2) plus 1 more for terminal.
  AllocHeapParams.RequestedBufferSize = (sizeof (HTIDS_PORT_OVERRIDE) * 3);
  AllocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
    PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST) AllocHeapParams.BufferPtr;
    LibAmdMemFill (PortOverrideList, HT_LIST_TERMINAL, AllocHeapParams.RequestedBufferSize, StdHeader);
    *ListReference = PortOverrideList;

    HTlinkSocket = AmdIdsNvReader (AGESA_IDS_NV_HTLINKSOCKET, IdsNvPtr, StdHeader);
    if (HTlinkSocket != IDS_UNSUPPORTED) {
      switch (HTlinkSocket) {
      case (UINT32) 0xE:
        HTlinkSocket = 0xFE;
        break;
      case (UINT32) 0xF:
        HTlinkSocket = 0xFF;
        break;
      default:
        break;
      }
      PortOverrideList->Socket = (UINT8) HTlinkSocket;
    }
    HTlinkPort = AmdIdsNvReader (AGESA_IDS_NV_HTLINKPORT, IdsNvPtr, StdHeader);
    if (HTlinkPort != IDS_UNSUPPORTED) {
      switch (HTlinkPort) {
      case (UINT32) 0xC:
        HTlinkPort = 0xFC;
        break;
      case (UINT32) 0xD:
        HTlinkPort = 0xFD;
        break;
      case (UINT32) 0xE:
        HTlinkPort = 0xFE;
        break;
      case (UINT32) 0xF:
        HTlinkPort = 0xFF;
        break;
      default:
        break;
      }
      PortOverrideList->Link = (UINT8) HTlinkPort;
    }
    HTlinkFre = AmdIdsNvReader (AGESA_IDS_NV_HTLINKFREQ, IdsNvPtr, StdHeader);
    if (HTlinkFre != IDS_UNSUPPORTED) {
      switch (HTlinkFre) {
      case (UINT32) 0x1F:
        HTlinkFre = 0xFF;
        break;
      default:
        break;
      }
      PortOverrideList->Frequency = (UINT8) HTlinkFre;
    }
    HTlinkWidthIn = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHIN , IdsNvPtr, StdHeader);
    if (HTlinkWidthIn != IDS_UNSUPPORTED) {
      switch (HTlinkWidthIn) {
      case (UINT32) 0x0:
        HTlinkWidthIn = 8;
        break;
      case (UINT32) 0x01:
        HTlinkWidthIn = 16;
        break;
      case (UINT32) 0x04:
        HTlinkWidthIn = 2;
        break;
      case (UINT32) 0x5:
        HTlinkWidthIn = 4;
        break;
      case (UINT32) 0x7:
        HTlinkWidthIn = 0xFF;
        break;
      default:
        break;
      }
      PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn;
    }
    HTlinkWidthOut = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHOUT, IdsNvPtr, StdHeader);
    if (HTlinkWidthOut != IDS_UNSUPPORTED) {
      switch (HTlinkWidthOut) {
      case (UINT32) 0x0:
        HTlinkWidthOut = 8;
        break;
      case (UINT32) 0x01:
        HTlinkWidthOut = 16;
        break;
      case (UINT32) 0x04:
        HTlinkWidthOut = 2;
        break;
      case (UINT32) 0x5:
        HTlinkWidthOut = 4;
        break;
      case (UINT32) 0x7:
        HTlinkWidthOut = 0xFF;
        break;
      default:
        break;
      }
      PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut;
    }
    if (PortOverrideList->Link == 0xFC) {
      // force both internal and external links
      // switch first PortOverride to force External
      HTlinkPort = 0xFE;  //Match external
      PortOverrideList->Link = (UINT8) HTlinkPort;

      // read all settings from first override list except Link
      HTlinkSocket = PortOverrideList->Socket;
      HTlinkPort = 0xFD;  //Match internal
      HTlinkFre = PortOverrideList->Frequency;
      HTlinkWidthIn = PortOverrideList->WidthIn;
      HTlinkWidthOut = PortOverrideList->WidthOut;

      // copy settings into second override list
      PortOverrideList++;

      PortOverrideList->Socket = (UINT8) HTlinkSocket;
      PortOverrideList->Link = (UINT8) HTlinkPort;
      PortOverrideList->Frequency = (UINT8) HTlinkFre;
      PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn;
      PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut;
    }
  }
  return IDS_SUCCESS;
}
/**
 *  IDS Backend Function for Select Platform Power Policy
 *
 *  Parameters:
 *  @param[in,out]   DataPtr  The Pointer of PLATFORM_CONFIGURATION.
 *  @param[in,out]   StdHeader        AMD standard header config param
 *  @param[in]     IdsNvPtr     The Pointer of NV Table.
 *
 * @retval      AGESA_SUCCESS     Always Succeeds.
 *
 */
IDS_STATUS
IdsSubPowerPolicyOverride (
  IN OUT   VOID *DataPtr,
  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
  IN       IDS_NV_ITEM *IdsNvPtr
  )
{
  PLATFORM_CONFIGURATION *PlatformConfig;
  IDS_STATUS NvValue;

  PlatformConfig = (PLATFORM_CONFIGURATION *)DataPtr;

  IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_POWER_POLICY, IdsNvPtr, StdHeader) {
    switch (NvValue) {
    case IDS_POWER_POLICY_PERFORMANCE:
      PlatformConfig->PlatformProfile.PlatformPowerPolicy = Performance;
      break;
    case IDS_POWER_POLICY_POWER:
      PlatformConfig->PlatformProfile.PlatformPowerPolicy = BatteryLife;
      break;
    case IDS_POWER_POLICY_AUTO:
      break;
    default:
      ASSERT (FALSE);
      break;
    }
  }

  return IDS_SUCCESS;
}