I have the following VHDL code - its for simulating an fsm, finite state machine. the code seems to behave fine, however when simulating i seem to have an issue with my output - the data out vector, which does not change value, and i want to be able to inspect its state at any given time. what could be a possible reason for that? LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
use STD.textio.all;

entity key_fsm_c is 
    port (clk: in std_logic;
     rst: in std_logic;
     left, right, up, down, center: in std_logic;
     data_out: out std_logic_vector(31 downto 0):= (others => '0');
     cntr_en: out std_logic;
     cntr_rst: out std_logic;
     cntr_load: out std_logic;
     edit_en_out: out std_logic
     );
end entity;

architecture Behavioral of key_fsm_c is
    type state_type is (idle, start, stop, reset, load, edit, inc_val, dec_val, inc_pos, dec_pos);
    signal c_state, n_state: state_type;
    
        -- Helper procedures for position and value increment and decrement operation
    
    procedure proc_dec_pos(old_pos: in integer;
                       position: out integer;
                       tmp: inout std_logic_vector;
                       act_num: out integer;
                       act_frag: out std_logic_vector) is
	begin
	    if old_pos >= 1 then
		position := old_pos - 1;
	    else
		position := 7;
	    end if;
	    act_frag := tmp(4*(position+1)-1 downto 4*position);
	    act_num := to_integer(unsigned(act_frag));
	end procedure;


    procedure proc_inc_pos(old_pos: in integer;
                       position: out integer;
                       tmp: inout std_logic_vector;
                       act_num: out integer;
                       act_frag: out std_logic_vector) is
    begin
        if old_pos <= 6 then
            position := old_pos + 1;
        else
            position := 0;
        end if;
        act_frag := tmp(4*(position+1)-1 downto 4*position);
        act_num := to_integer(unsigned(act_frag));
    end procedure;

    procedure proc_dec_val(old_num: in integer;
                       position: out integer;
                       tmp: inout std_logic_vector;
                       act_num: out integer;
                       act_frag: out std_logic_vector) is
    begin
        if old_num >= 1 then
            act_num := old_num - 1;
        else
            act_num := 9;
        end if;
        act_frag := std_logic_vector(to_unsigned(act_num, 4));
        tmp(4*(position+1)-1 downto 4*position) := act_frag;
    end procedure;

    procedure proc_inc_val(old_num: in integer;
                       position: out integer;
                       tmp: inout std_logic_vector;
                       act_num: out integer;
                       act_frag: out std_logic_vector) is
    begin
        if old_num <= 8 then
            act_num := old_num + 1;
        else 
            act_num := 0;
        end if;
        act_frag := std_logic_vector(to_unsigned(act_num, 4));
        tmp(4*(position+1)-1 downto 4*position) := act_frag;
    end procedure;
    
begin
    -- FSM state transition process
    proc_state_transition: process (rst, clk)
    begin
        if rst = '1' then
            c_state <= idle;
        elsif rising_edge(clk) then
            c_state <= n_state;
        end if;
    end process;

    -- FSM output logic process
    proc_output_logic: process (c_state, left, right, up, down, center)
        variable position: integer := 0;
        variable act_num: integer := 0;
        variable old_pos: integer := 0;
        variable old_num: integer := 0;
        variable is_begin: integer := 1;
        variable act_frag: std_logic_vector(3 downto 0);
        variable tmp: std_logic_vector(31 downto 0) := (others => '0');
        variable edit_pending: boolean := false;
    begin
        -- Initializing control signals
        cntr_en <= '0';
        cntr_rst <= '0';
        cntr_load <= '0';
        edit_en_out <= '0';

        case c_state is
            when idle =>
                n_state <= idle;
                if right='1' then 
                    n_state <= start;
                elsif left = '1' then 
                    n_state <= stop;
                elsif down = '1' then 
                    n_state <= reset;
                elsif up = '1' then 
                    n_state <= load;
                elsif center = '1' then
                    n_state <= edit;
                    edit_pending := true;
                end if;
            when start => 
                cntr_en <= '1';
                n_state <= idle;
            when stop => 
                cntr_en <= '0';
                n_state <= idle;
            when reset => 
                cntr_rst <= '1';
                n_state <= idle;
            when load =>
                cntr_load <= '1';
                edit_en_out <= '0';
                n_state <= idle;
            when edit =>
                n_state <= edit;
                edit_en_out <= '1';
                if right='1' and not edit_pending then 
                    n_state <= dec_pos;
                elsif left='1' and not edit_pending then 
                    n_state <= inc_pos;
                elsif down='1' and not edit_pending then 
                    n_state <= dec_val;
                elsif up='1' and not edit_pending then 
                    n_state <= inc_val;
                elsif center='1' and not edit_pending then 
                    n_state <= load;
                end if;
                edit_pending := false;
            when dec_pos =>
                proc_dec_pos(old_pos, position, tmp, act_num, act_frag);
                n_state <= edit;
            when inc_pos => 
                proc_inc_pos(old_pos, position, tmp, act_num, act_frag);
                n_state <= edit;
            when dec_val => 
                proc_dec_val(old_num, position, tmp, act_num, act_frag);
                n_state <= edit;
            when inc_val =>
                proc_inc_val(old_num, position, tmp, act_num, act_frag);
                n_state <= edit;
        end case;
        data_out <= tmp;
    end process;

end Behavioral;