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The present invention relates in general to logic circuitry, and in particular, to self-timed logic circuitry. Self-timed circuit techniques, once thought only as research-oriented projects, are quickly becoming mainstream in VLSI circuit applications. Requiring no clocks for operation, as does a traditional system, self-timed circuits operate asynchronously on the simple concept of demand. That is, a self-timed circuit operates only when asked to, generates the necessary outputs according to its own internal scheduling, and presents the results to the requester. Afterwards, the circuit xe2x80x9cgoes to sleepxe2x80x9d and awaits the next instruction/request. While asleep, no power is dissipated since no operation is taking place. This is contrary to traditional synchronous systems where even when a circuit is not needed, there is at least power dissipated by the clock circuitry running through the system. This idle power can be significantxe2x80x94studies show that clocking power is approximately 30% of the overall power on a given VLSI circuit/chip. Consequently, self-timed circuits have at least a power advantage over traditional methods. Self-timed circuits also have significant advantages over other techniques such as self-resetting. This approach requires no interaction between driving and receiving circuitry, creating scheduling and arrival time conflicts and complications. FIG. 1 shows an example of a self-timed logic circuit pipeline, or unit 100. Note in FIG. 1 that each block 101-104 labelled xe2x80x9cSelf-timed Logic Circuitxe2x80x9d can, itself, be a combination of self-timed circuits. The operation of such a self-timed system is straightforward and is presented briefly below. Note that this example is an extremely small system. Also, note that each sub-block 101-104 labelled in FIG. 1 as a xe2x80x9cSelf-Timed Logic Circuitxe2x80x9d may, itself, contain multiple self-timed circuit stages and, thus, may also contain operation internally as described below: The input source(s) indicates to the Self-Timed Logical Unit 100 by asserting the xe2x80x9crequestxe2x80x9d signal and enabling the xe2x80x9cdata inputsxe2x80x9d (a bus or multiple of bus signals). Note that the number of such sources is not limited to one, but is only shown as one in FIG. 1 for simplicity. The first (receiving) Self-Timed Logic Circuit xe2x80x9caxe2x80x9d 101 notes that a xe2x80x9crequestxe2x80x9d has been made and returns the xe2x80x9cacknowledgexe2x80x9d signal to the source(s). This signifies to the sources that the information on the xe2x80x9cdata inputsxe2x80x9d has been received. The logic (not shown) that drives the source signals (xe2x80x9cdata inputsxe2x80x9d) is now free to de-assert the xe2x80x9cdata inputsxe2x80x9d, do other operations, etc., since the Self-Timed Logical Circuit xe2x80x9caxe2x80x9d 101 has received the input information and has begun operating. Self-Timed Logic Circuit xe2x80x9caxe2x80x9d 101 operates on the xe2x80x9cdata inputsxe2x80x9d and produces a xe2x80x9cvalid output signalxe2x80x9d to Self-Timed Logic Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 along with xe2x80x9cdata output signalsxe2x80x9d. Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 receive the information and send xe2x80x9ccomplete outxe2x80x9d signals back to circuit xe2x80x9caxe2x80x9d 101 to signify capture of the incoming information. Circuit xe2x80x9caxe2x80x9d 101 is now free to de-assert the output information and, if necessary, receive further inputs from the logical unit input sources. Self-Timed Logic Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 operate