You are a helpful assistant generating synthetic data that captures *System 1* and *System 2* thinking, *creativity*, and *metacognitive reflection*. Follow these steps in sequence, using tags [sys1] and [end sys1] for *System 1* sections and [sys2] and [end sys2] for *System 2* sections.

1. *Identify System 1 and System 2 Thinking Requirements:*
   - Carefully read the text.
   - Identify parts of the text that require quick, straightforward responses (*System 1*). Mark these sections with [sys1] and [end sys1].
   - Identify parts that require in-depth, reflective thinking (*System 2*), marked with [sys2] and [end sys2].

2. *Apply Step-by-Step Problem Solving with Creativity and Metacognitive Reflection for System 2 Sections:*

   *2.1 Understand the Problem:*
   - Objective: Fully comprehend the issue, constraints, and relevant context.
   - Reflection: "What do I understand about this issue? What might I be overlooking?"
   - Creative Perspective: Seek hidden patterns or possibilities that could reveal deeper insights or innovative connections.

   *2.2 Analyze the Information:*
   - Objective: Break down the problem logically.
   - Reflection: "Am I considering all factors? Are there any assumptions that need challenging?"
   - Creative Perspective: Explore unique patterns or overlooked relationships in the data that could add depth to the analysis.

   *2.3 Generate Hypotheses:*
   - Objective: Propose at least 10 hypotheses, each with a Confidence Score (0.0 to 1.0) and Creative Score (0.0 to 1.0), reflecting originality, surprise, and utility.
   - Reflection: "Have I explored all possible explanations or approaches, both conventional and unconventional?"
   - Creative Perspective: Consider novel angles that might provide unexpected insights.

   *2.4 Anticipate Future Steps and Obstacles:*
   - Objective: Make predictions, accounting for potential outcomes and obstacles.
   - Reflection: "What challenges might I face? Is my plan flexible for different scenarios?"
   - Creative Perspective: Visualize unforeseen outcomes and adapt plans to make use of them effectively.

   *2.5 Evaluate Hypotheses:*
   - Objective: Assess hypotheses based on feasibility, risk, and potential impact.
   - Evaluation: Refine Confidence and Creative Scores as needed.
   - Reflection: "Am I unbiased in my assessment? Which options fit best with the overall objectives?"
   - Creative Perspective: Identify hidden opportunities or overlooked details in each hypothesis.

   *2.6 Select the Best Hypothesis:*
   - Objective: Choose the most promising, strategic hypothesis.
   - Reflection: "Why does this hypothesis stand out? How does it uniquely address the issue?"
   - Creative Perspective: Consider any underutilized potential in the selected approach.

   *2.7 Implement the Hypothesis:*
   - Objective: Outline actionable steps for testing the hypothesis.
   - Reflection: "Is this plan practical? What resources or preparation are required?"
   - Creative Perspective: Refine steps to maximize effectiveness and yield unexpected benefits.

   *2.8 Monitor and Review Progress:*
   - Objective: Review progress, noting areas for improvement.
   - Reflection: "What’s working well? What could be improved?"
   - Creative Perspective: Look for emerging patterns that could refine future approaches.

   *2.9 Reflect and Capture Insights:*
   - Objective: Summarize lessons learned and insights gained for future reference.
   - Reflection: "What new understanding has emerged from this process?"
   - Creative Perspective: Identify innovative insights or patterns that could be applied to similar challenges.

3. *Generate Text Output with Interleaved System 1 and System 2 Responses:*
   - Use the tags [sys1] and [sys2] throughout.
   - Aim for a lengthier, detailed response. Combine both direct, straightforward *System 1* insights and reflective, deeply analytical *System 2* segments to capture a blend of quick observations and thoughtful analysis.

---

### *Example Input Text:*

You are tasked with analyzing a sudden shift in customer preferences in a tech market. There has been a noticeable decline in demand for physical devices, with customers increasingly interested in digital-only options. The challenge is to understand this shift, generate hypotheses for why it might be occurring, and explore potential strategies for adapting to this new trend.

---

### *Processed Output with System 1 and System 2 Thinking:*

The tech market is experiencing a shift in customer demand, moving away from physical devices toward digital-only options.

[sys1]
Customer demand has shifted from physical devices to digital-only options.
We need to understand why this change is happening and find strategies to address it.
Key factors may include cost, convenience, and technological trends.
[end sys1]

[sys2]
**2.1 Understand the Problem:**
The goal is to understand the underlying reasons for the shift in demand from physical devices to digital-only options, then develop a strategy to adapt.

*Reflection:* 
"I understand that preferences are changing, but what might be driving this? Is it primarily cost, or are there other factors such as convenience or sustainability?"

*Creative Perspective:* 
"Could there be a larger trend in digital minimalism or a preference for eco-friendly solutions that we’re missing? What unseen motivations might explain this shift?"

**2.2 Analyze the Information:**
There are multiple possible factors driving this shift, from economic influences to cultural shifts. It’s essential to isolate each factor and understand its impact.

*Reflection:* 
"Am I fully considering the various economic and social influences? Could there be a technological factor, like better internet speeds, that makes digital-only products more accessible?"

*Creative Perspective:* 
"Are there patterns or trends in other markets that could shed light on this shift? Could this be part of a larger trend toward virtual experiences?"

**2.3 Generate Hypotheses:**
1. Customers prefer digital options due to lower costs. (Confidence: 0.8, Creative: 0.4)
2. There’s a growing trend toward minimalism and reduced physical clutter. (Confidence: 0.7, Creative: 0.7)
3. Digital products offer greater flexibility and ease of use. (Confidence: 0.6, Creative: 0.6)
4. Environmental concerns are pushing consumers away from physical goods. (Confidence: 0.6, Creative: 0.8)
5. Advances in tech make digital-only options more functional. (Confidence: 0.8, Creative: 0.5)
6. Pandemic-era remote work increased demand for digital solutions. (Confidence: 0.7, Creative: 0.6)
7. Media coverage of the environmental impact of physical devices affects preferences. (Confidence: 0.5, Creative: 0.7)
8. There’s an increase in global digital literacy, expanding market access. (Confidence: 0.6, Creative: 0.6)
9. Customers view digital as more convenient and scalable for future needs. (Confidence: 0.7, Creative: 0.5)
10. Younger consumers prefer the aesthetics and convenience of digital products. (Confidence: 0.6, Creative: 0.6)

*Reflection:* 
"Have I considered all possible influences? Are there any surprising factors that could explain this shift?"

*Creative Perspective:* 
"Could specific social trends, like the rise of influencer culture or digital-first lifestyles, be influencing customer choices?"

**2.4 Anticipate Future Steps and Obstacles:**
*Objective:* Anticipate possible challenges, such as resistance from segments still preferring physical products.

*Reflection:* 
"What market obstacles might we face if we shift our focus to digital-only? Are there sub-segments that still prioritize physical products?"

*Creative Perspective:* 
"Could expanding digital options help us reach a more global audience? Are there emerging trends that we could leverage in our strategy?"

[end sys2]

[sys1]
To address this shift, consider a strategy that incorporates both digital-only offerings and educational campaigns about the benefits of digital solutions.
Use insights from customer feedback and current trends to guide product development.
Focus on flexibility and adaptation to cater to different customer segments.
[end sys1]


---
abstract: 'FPGA devices are continuously evolving to meet high computation and performance demand for emerging applications. As a result, cutting edge FPGAs are not energy efficient as conventionally presumed to be, and therefore, aggressive power-saving techniques have become imperative. The clock rate of an FPGA-mapped design is set based on worst-case conditions to ensure reliable operation under all circumstances. This usually leaves a considerable timing margin that can be exploited to reduce power consumption by scaling voltage without lowering clock frequency. There are hurdles for such opportunistic voltage scaling in FPGAs because (a) critical paths change with designs, making timing evaluation difficult as voltage changes, (b) each FPGA resource has particular power-delay trade-off with voltage, (c) data corruption of configuration cells and memory blocks further hampers voltage scaling. In this paper, we propose a systematical approach to leverage the available thermal headroom of FPGA-mapped designs for power and energy improvement. By comprehensively analyzing the timing and power consumption of FPGA building blocks under varying temperatures and voltages, we propose a thermal-aware voltage scaling flow that effectively utilizes the thermal margin to reduce power consumption without degrading performance. We show the proposed flow can be employed for *energy* optimization as well, whereby power consumption and delay are compromised to accomplish the tasks with minimum energy. Lastly, we propose a simulation framework to be able to examine the efficiency of the proposed method for other applications that are inherently tolerant to a certain amount of error, granting further power saving opportunity. Experimental results over a set of industrial benchmarks indicate up to 36% power reduction with the same performance, and 66% total energy saving when energy is the optimization target.'
author:
- 'Behnam Khaleghi, Sahand Salamat, Mohsen Imani, Tajana Rosing\'
bibliography:
- 'references.bib'
---

Introduction {#sec:intro}
============

The prevalence of computation-intensive workloads with high-performance requirements such as machine learning (ML) and data center applications [@putnam2014reconfigurable; @lacey2016deep] accompanied with the advance of technology node have persuaded the FPGA vendors to integrate more resources with boosted clock rate in state-of-the-art FPGAs [@stratix10]. This, together with slowed shrinking of FPGAs supply voltage [@ahmed2018automatic], have pushed these devices to a point they consume power comparable to CPUs [@shen2019fast]. Besides, there are prevailing energy-constrained applications in the [Internet of Things]{} (IoT) era, implemented in FPGAs, with the need for extreme energy efficiency [@blaauw2014iot; @venkataramani2016efficient]. All in all, more efficient power reduction approaches for FPGAs are now indispensable.

As FPGAs already employ a manifold of device-level optimization to throttle power consumption [@xilinx7], more *aggressive* power reduction techniques are gaining traction. These techniques generally build upon the conservative timing margin ($d_g$) that is considered to compensate reliability threats in deep-nano technologies; while an FPGA-mapped design is able to deliver an *actual* clock period of $d_{V_{nom}}$ at nominal voltage $V_{nom}$, in practice, STA (static timing analysis) tools report an operating clock delay of $d_{V_{nom}} + d_{g}$ to make up for uncertainties such as voltage fluctuations, degradation, temperature, etc. [@shen2019fast]. The aforementioned aggressive techniques exploit this available timing headroom to reduce the supply voltage of FPGAs down to $V_{low}$ for which the *actual* clock period $d_{V_{low}}$ becomes equal or close to $d_{V_{nom}} + d_{g}$ (leaving no margin for guardbands). Thus, the device still delivers the original performance at a lower voltage. Note that *aggressive* voltage scaling techniques are different from conventional DVFS (dynamic voltage and frequency scaling) that concurrently tunes the frequency and voltage based on per-task performance demand of applications.

Although lowering the supply voltage of processors and ASIC devices has been known to be an effective power saving technique [@bao2009line; @lefurgy2011active; @amrouch2018voltage], there are limited studies presenting voltage scaling in FPGAs. Voltage scaling (in particular, aggressive and performance-aware one) in FPGAs is challenging mainly because: **(a)** *Critical Path* (CP) in an FPGA is design-dependent, which makes timing probing difficult under voltage scaling, especially considering the impact of temperature. Therefore, in contrast to ASIC designs, a set of precalibrated stand-alone sensory circuits, e.g., ring oscillators and CP monitors [@lefurgy2011active] cannot accurately correlate the sensor frequency with all varying CPs. **(b)** FPGA architectures are heterogeneous, comprising soft-fabric (i.e., programmable logic and routing resources), DSP cores, memory blocks (BRAM), etc. These building blocks are tightly coupled, and each has a particular power/delay relation with supply voltage. Considering the separate voltage rails provided for certain components, i.e., $V_{bram}$, $V_{core}$, and $V_{io}$ that can be regulated separately, finding efficient voltage points becomes design-dependent and challenging. In other words, in multi-supply devices, multiple voltage combinations can lead to the target $d_{V_{nom}} + d_{g}$ boundary, while only one tuple yields minimum power. This makes speculative voltage decrement no more efficient. **(c)** Scaling the voltage of FPGAs is also constrained by the data corruption of configuration and memory SRAM cells. In addition, as we will discuss in this paper, reducing the voltage of configuration cells unexpectedly [increases]{} FPGA power consumption in certain cases, calling for cautious analysis.

In this paper, we leverage the pessimistic thermal-induced timing slack to scale down FPGA operating voltage for power saving while tackling the aforementioned challenges as follows.\
**(1)** We propose to incorporate thermal-aware voltage scaling in the FPGA design flow. We first obtain the temperature-delay-voltage correlation of FPGA resources within the supported temperature range. Then, we statically estimate the thermal distribution of applications to obtain the available timing headroom, for which voltages of different power rails can be efficiently determined based on the characterized library. For further effectiveness, we also suggest online (i.e., dynamic) voltage adaptation based on the response of thermal sensors. The proposed methods consider the voltage-temperature feedback loop and the separate power rails of specific resource types to yield maximum power efficiency.\
**(2)** We leverage the proposed flow of (1) to explore the *energy* consumption, whereby we trade-off the performance and power consumption to achieve the minimum energy point. This is desirable for a majority of edge and IoT applications for which total energy consumption is the utmost concern.\
**(3)** Our approaches mentioned in (1) and (2) are deterministic, as they guarantee timing closure. Nonetheless, many use-cases such as image processing and machine learning applications can tolerate a certain level of computation errors, which gives an opportunity for voltage *over-scaling*. However, it needs an examination of applications under these non-ideal conditions to get a glimpse of produced error in the output. We propose a primary FPGA simulation framework to be able to evaluate an FPGA-mapped design under voltage-scaling, i.e., when the delay of resources varies. Using the proposed framework, we map demonstrative machine learning applications into FPGA fabric and examine the impact of voltage *over-scaling* on extra power gain versus accuracy drop.

Background and Related Work {#sec:rel}
===========================

FPGA Architecture {#subsec:arch}
-----------------

Fig. \[fig:arch\] illustrates the architecture of conventional tile-based FPGAs. The architecture comprises tiles of logic clusters (a.k.a CLBs or slices) that bind together using the configurable switch boxes (SBs) and connection blocks (CBs) to implement larger functions. Each logic CLB consists of $N$ (e.g., $N=10$) $K$-input look-up tables (LUTs) each of which is capable to implement Boolean expressions up to $K$ variables. SB multiplexers are located in the intersection of horizontal and vertical channels (wire tracks) to enable connectivity and bending of nets. These multiplexers are also responsible for connecting outputs of logic resources (LUTs, FFs, carry chain, etc.) to global routing, i.e., to horizontal and vertical channels. Analogously, CB multiplexers pass the selected global wires into the logic clusters. Specific FPGA columns are repetitively dedicated to Block RAMs and DSP cores. The majority of logic and routing resources have a multiplexer-like structure, mainly implemented as two-stage multiplexers that have been shown to provide optimal area-delay efficiency [@lewis2005stratix]. These resources often drive large loads, especially the global routing resources that have a high number of long fanout wires, so are augmented with large output buffers to improve performance.

![Tile-based FPGA architecture (left), and constructing building blocks (right) [@chiasson2013should].[]{data-label="fig:arch"}](arch.pdf){width="50.00000%"}

Related Work {#subsec:related}
------------

While many previous studies have attempted to reduce FPGA power dissipation by power-gating, conventional DVFS, configurable dual supply voltage, control of signal levels, architectural innovations, etc. [@seifoori2018introduction], there is a limited number of works that leverage the available timing margin to reduce voltage without scarifying performance. Authors of [@levine2014dynamic] explore the timing headroom of FPGA-mapped designs by gradually reducing the voltage (keeping the frequency fixed) until observing the error. They detect the error by inserting a shadow register per each CP with a phase-shifted clock to detect the data mismatch caused by voltage reduction. As there are a huge number of CP and near-CP paths in a large synthesis-flattened design, the area and power overhead of this technique can be excessive. Also, measuring the slack in this technique depends on capturing the signal traversing the CP, while the CP may not be controllable at the runtime. Furthermore, the introduced capture registers cannot be used for paths that head to hard blocks such as BRAM. The study in [@nunez2017adaptive] addresses the latter issue by replicating such paths and inserting an end-point proxy register (instead of the hard block) where an error-detector circuitry checks timing violations. However, the error-detector itself imposes delay, so a timing error raised in the original CP might propagate into the memory before being detected. In [@zhao2018robust], the authors propose a two-step self-calibrating voltage scaling scheme by exploiting the available timing slack of thermal margin. CPs of a design are extracted by using the STA tool and are then implemented on the FPGA fabric. Afterward, for different values of temperature and core voltage ($T$ and $V_{core}$), the maximum frequency is obtained by gradually increasing it until error is observed by the implemented error-detection circuit. This approach does not consider the thermal distribution within the chip [@amouri2013accurate] where a CP may experience varied temperature in reality. This either results in timing violation by ignoring the parts of CP that reside in hot (hence, slower) tiles or gives non-optimal results if a related thermal margin is considered. In addition, the STA tool reports the CPs according to worst-case condition while CPs might change at lower temperatures. Thus, a larger number of near-CP paths need to evaluate which makes the entire process further cumbersome. BRAM and soft-logic voltage rails also are not separately considered, so the minimum employed voltage will be limited by the one that violates the timing first.

Finally, recent work in [@salami2018bram] examines the voltage scaling of FPGA BRAMs. The authors showed that up to 39% of BRAM voltage can be reduced without observing any error. Though it is promising in reducing the power of BRAMs by one order of magnitude, a trial-and-error based approach does not guarantee correct functionality as it is infeasible to examine all the inputs. Moreover, the overall efficiency is limited to the power of BRAMs.

Aforementioned techniques are all speculative as they decrease the voltage until observing an error. This overlooks errors that emerge gradually due to violating the guardbands (e.g., timing error as a result of degradation [@khaleghi2019estimating]) or may arise abruptly due to voltage transients [@shen2019fast]. Recently, work in [@shen2019fast] showed a margin of over 36% is needed for voltage transients as a result of load transients, and this margin is already considered in STA tools. Nevertheless, as voltage transients occur infrequently, the speculative voltage scaling methods do not take them into consideration, which will lead to timing violation at certain conditions. Our voltage scaling approach is different from previous studies as we incorporate it in the FPGA design flow by characterizing the resources during FPGA architecting. This eliminates the arduous task of voltage-timing speculation and guarantees timing. Our method precisely considers the correlation of temperature, delay, voltage, and power of resources and separate power rails of soft-fabric and memories, so it yields maximum efficiency by setting the optimal core and BRAM voltages as well as accurately estimating the timing according to the thermal distribution of the blocks. Finally, *over-scaling* of voltages needs timing simulation to observe the impact of timing violations. We enable it by our novel FPGA simulation flow. It is noteworthy that, similar to our work, the studies in [@khaleghi2019thermal] and [@salamat2019workload] also propose *deterministic* frequency and/or voltage adaption through resource characterization. Nonetheless, [@khaleghi2019thermal] targets performance boosting by using non worst-case guardband in lower temperatures, and [@salamat2019workload] adjusts both the frequency and voltage in non-peak workloads to save power (hence, has nothing to do with the temperature).

Proposed Method {#sec:prop}
===============

Preliminary {#subsec:preliminary}
-----------

FPGA flow is different from conventional standard-cell based design of ASICs. Thus, we first elaborate the setup of experiments used in the rest of the paper before detailing the proposed method.

**$\bullet$ Power and Delay.** We use circuit-level simulations to obtain the delay and power of FPGA resources. For this end, we use the latest version of COFFE [@chiasson2013coffe] that generates and characterizes an accurate netlist of FPGA resources according to the given architectural description using comprehensive circuit-level HSPICE simulations. Besides the description of the target FPGA architecture, COFFE also requires technology process of transistors, for which we use 22nm predictive technology model (PTM) [@ptm]. COFFE also generates and evaluates the memory blocks of FPGA and has been shown to have a suitable delay and exact area match with commercial FPGAs [@yazdanshenas2017don]. Similar to configuration SRAM cells, the core of the memory blocks (i.e., eight-transistor dual-port SRAM cells) is implemented by 22nm high-threshold low-power transistors [@tuan200690nm], which throttles their leakage power by two orders of magnitude. As we will show in the rest of this section, our simulations show a similar power trend to commercial FPGAs.

COFFE does not model DSP blocks. We thus develop the DSP HDL code based on the Stratix IV description [@stratixiv] and characterize it using Synopsys Design Compiler with NanGate 45nm open cell library [@nangate2008california]. Then we scale the results to 22nm based on measuring scaling factors of a selected set of cells at 45nm and 22nm technologies. Based on PrimeTime report, the developed DSP consumes 4.6mW at 250MHz, which is comparable to a 28nm DSP that dissipates 5.6mW at the same frequency [@xpower]. To characterize the delay and power of programmable resources at different temperature and voltages, we sweep the parameters of COFFE-generated netlists in HSPICE simulations. For DSP, we create a set of standard-cell libraries using NanGate netlists by the means of Synopsys SiliconSmart so we could characterize the DSP at different operating conditions.

**$\bullet$ FPGA Flow.** We use VTR 7.0 (Verilog-to-Routing) [@luu2014vtr] toolchain that enables defining a customized FPGA architecture and place and route the benchmarks. We select our benchmarks from VTR repository that belong to a wide variety of applications (vision, math, communication, etc.), contain single- and/or dual-port memory blocks as well as DSP blocks, with an average of over 23,800 $6$-input LUTs (maximum over 106K). We use FPGA architecture parameters similar to Intel Stratix devices [@lewis2009architectural; @chiasson2013should] in COFFE and VPR[^1] placement and routing, which is summarized in Table \[tab:coffe\]. COFFE uses these parameters to generate SPICE netlist and area and delay report, which are then fed into VTR to place and route the benchmarks. $K$ and $N$ are the sizes of LUTs and number of logic blocks in a cluster (see Fig. \[fig:arch\]), which are chosen to be 6 and 10 in accordance with Intel devices. Estimating the power consumption of applications (for both thermal simulation and power saving estimation) needs also their signal activity, for which we use ACE 2.0 [@lamoureux2006activity]. We modified VPR to enable timing analysis at different scenarios using the characterized libraries.

**$\bullet$ Thermal Simulation.** We use HotSpot 6.0 [@zhang2015hotspot] for thermal simulations. Inputs of HotSpot are device floorplan, power trace (or average power values), and device configuration parameters. For the floorplan file, we divide the device floorplan into a two-dimensional array of FPGA tiles with the areas reported by COFFE. We assume CLB tiles are square, and the heights of DSP and memory blocks are $4\times$ and $6\times$ of CLB tiles [@luu2014vtr]. The number of tiles and location of each tile can be obtained from the placement and routing outputs reported by VPR. Leakage and dynamic power of each tile is obtained based on the current temperature and activities of resources of the tile. Finally, for the HotSpot configuration file, we change the parameters according to validated FPGA parameters in [@velusamy2005monitoring]. We adjust the convective resistance to concur with an effective thermal resistance ($\theta_{JA}$) of contemporary FPGAs, i.e., we tune $\mathtt{r\_convec}$ such that when the total power of given power trace is set to 1 Watt, the reported temperature by HotSpot equals $\theta_{JA}$. We examine the efficiency of the proposed technique by using a typical $\theta_{JA}$ of $2\,\sfrac{\degree C}{W}$ as in today’s Intel and Xilinx devices (e.g., Virtex–7 and Stratix V) [@xpower; @intelpower], and a pessimistic thermal resistance of $12\, \sfrac{\degree C}{W}$, corresponding to their mid-size devices (such as Spartan–7 or Artix–7) with still airflow.

We decided not to touch the voltage of configuration SRAM cells because (a) these cells are not in the CP, so are implemented using medium-oxide high-threshold transistors with two order of magnitude reduced power than typical SRAM cells [@tuan200690nm], and (b) these cells are directly connected to the gate of the pass-transistors; hence, reducing their voltage not only excessively increases the delay, but also passes a non-ideal voltage to the output driver which contrarily increases the leakage power. In our simulations, we did not notice any crash in the memory modules within the explored voltage range (0.5V-0.95V). The study in [@salami2018bram] observed the device crashed when $V_{bram}$ reduced from the original $1V$ to $0.54V$[^2]. Thus we consider the same crash voltage for both the core and memory voltages. We assume the ambient temperature is $25\degree C$, while the junction temperature of the FPGA resources in Algorithm \[algorithm1\] and \[algorithm2\] are obtained assuming an effective thermal resistance of $2\degree C$, similar to Kintex-7 devices [@xpower].

Proposed Thermal-Aware Voltage Scaling Flow {#subsec:flow}
-------------------------------------------

**$\bullet$ Motivation.** Fig. \[fig:motivation\] gives perception on how temperature margin can be leveraged for power reduction. This figure is obtained using the experimental setup explained in the previous subsection. Numbers were not in the same range, so we normalized each one to its base value at $100\degree$C and $0.8$V for the sake of clear illustration. According to Fig. \[fig:motivation\](a), although FPGA timing analysis reports the worst-case to ensure timing meets in all scenarios [@timing], in practice, resources have a smaller delay at lower temperatures. For instance, at 40$\degree$C, delay of switch box ( SB) is 0.85$\times$ of its delay at worst-case temperature[^3]. This gap can be utilized for voltage reduction. Based on Fig. \[fig:motivation\](b), 0.68V is the point wherein this margin is fully utilized, i.e., delay of 40$\degree$C increases by $\frac{1}{0.85\times}$ and becomes equal to delay at worst-case temperature. Eventually, Fig. \[fig:motivation\](c) reveals this 120mV reduction of voltage shrinks the switch box power down by 32%. As mentioned before, memory block comprises of low-threshold transistors, so uses a different power rail with a voltage higher than datapath (core) transistors. Other non-memory resources show a [.17ex]{}$V^2$ relation with voltage while BRAM observes a more dramatic power reduction as voltage scales. As is evident from the figure, different resources exhibit different delay behavior as temperature and voltage change. This stems from different sizing of transistors, input slope, output capacitance, etc., as detailed in previous works [@amrouch2017optimizing; @amrouch2018voltage].

We can get several insights from Fig. \[fig:motivation\] and above discussion.\
**(a)** Replica circuits such as ring oscillators used to correlate the temperature/voltage with frequency of ASICs are not a viable solution to track timing because, in FPGAs, CPs are design-dependent and made from different types and count of resources. Apparent from Fig. \[fig:motivation\](a) and (b), designs bounded by routing (SB) have a totally different performance behavior compared to logic (LUT) bounded ones when temperature or voltage changes, so a set of representative paths fails to resemble all paths accurately.\
**(b)** Previous studies rely on worst-case reported paths to check the timing (or to insert error detectors) while lowering the voltage. Nonetheless, from Fig. \[fig:motivation\](a) and (b) we can infer a non-CP path may become CP at lower temperature or voltage. For instance, LUT delay severely increases at lower voltages, so the delay of LUT-bounded paths can exceed originally reported SB-bounded paths. This signifies cautious timing analysis in voltage scaling.\
**(c)** More importantly, even if timing analysis of an FPGA-based design were possible under arbitrary (T, V) pairs, efficient voltage scaling would be still challenging because, as shown in Fig. \[fig:motivation\](c), resources enjoy differently from voltage reduction. For instance, memory block shows better power saving as voltage scales, while, on the contrary, its delay also increases more under voltage scaling. Thus, for a certain timing headroom, there is a trade-off between power gain and increase of delay (i.e., use up of margin) when there are multiple power rails. This justifies why temperature-voltage-delay correlation and voltage-power libraries are indispensable for a reliable and efficient thermal-aware voltage scaling.

**$\bullet$ Thermal-Aware Voltage Scaling Flow.** Taking the above-mentioned insights into consideration, in the following we present our voltage scaling algorithm as the core of our energy efficiency technique, and then further elaborate it by exemplifying case-studies. Algorithm \[algorithm1\] can be either simply integrated into the current FPGA flow stack (i.e., in the original timing analysis step), or attached as an additional step. In either case, it relies on a pre-characterized library of delay and power, as detailed in Section \[subsec:preliminary\]. If Algorithm \[algorithm1\] is used as an additional step, then it needs to get the post place and route netlist. Other inputs of the algorithm are maximum temperature surrounding the FPGA board, and sample inputs or activities (we further discuss it later).

$\overrightarrow{T}_{m \times n} = [T_{amb}, \cdots, T_{amb}]$ // $m,n: $ FPGA grid size\
$\overrightarrow{\Delta T}_{m \times n} = [\infty, \cdots, \infty]$\
$d_{worst} = \mathcal{T}(netlist, {T}_{max}, V_{core_{max}}, V_{bram_{max}})$\
$V_{core}, V_{bram}$

FPGA thermal estimation usually relies on a single total power and ambient temperature value to estimate the junction temperature [@xpower], however, we divide the target FPGA into a grid of $m$$\times$$n$ tiles, for $m$ and $n$ being the number of FPGA rows and columns. It improves the accuracy of thermal estimation and helps to catch potential hotspot regions, where the blocks have higher delay than the rest of the board, hence need fine-grained timing analysis for both accuracy and efficiency (i.e., to avoid under- or over-estimation of timing). $d_{worst}$ is the delay that conventional one-size-fits-all timing analysis $\mathcal{T}$ of FPGA reports under nominal memory and core voltages and maximum temperature [@timing] while also considers some margin for reliability issues such as voltage transients [@shen2019fast]. Thus $d_{worst}$ is the target delay that our algorithm attempts to deliver with lower voltages. One drawback of previous voltage scaling approaches [@levine2014dynamic; @zhao2018robust] is they invade this reliability margin when they speculatively reduce the voltage until observing an error in the output, as the error does not show up in regular conditions. The core of the algorithm is a loop where, based on previously obtained temperature for each tile (set to $T_{amb}$ initially), it finds the ($V_{core}, V_{bram}$) pair that minimizes the power while watches over the delay of candidate pair to not exceed $d_{worst}$. In the first iteration of the algorithm, it explores all $|V_{core}| \times |V_{bram}|$ pairs. In the next iterations, execution time can be significantly reduced by limiting the search to the boundaries of the previous solution, making subsequent iterations $O(1)$. Note that in both timing analysis and power calculation (lines 5–7), each tile has its own activity and potentially different temperature, so we use vectors of length $m$$\times$$n$ to store the values associated with each tile. Temperature affects the leakage power and delay of the tile resources, while activity affects the dynamic power. Hence, $\overrightarrow{T}$ is passed to $\overrightarrow{P}_{lkg}$ calculation and timing ($\mathcal{T}$) analysis, while $\overrightarrow{\alpha}$ is passed to $\overrightarrow{P}_{dyn}$ to estimate dynamic power at $d_{worst}$ (clock cycle will be always $d_{worst}$). Finally, the power values are imported in a thermal simulator to update temperatures of tiles. This procedure repeats until reaching a steady-state temperature. For thermal simulation in our experiments we use HotSpot 6.0 [@zhang2015hotspot], with setup already detailed in Section \[subsec:preliminary\].

**$\bullet$ Static and Dynamic Implementations.** Static implementation of the proposed technique is straightforward as both core and memory voltages are determined during the configuration of design, whether by incorporating Algorithm \[algorithm1\] in original timing analysis of FPGA, or using it as a post-routing addendum. As the voltages remain fixed in the field operation, the algorithm needs to consider the corner case of the programmed design, i.e., the highest temperature it might reach. A noteworthy point here is that activities of internal nodes of a design do not linearly correspond to activities of primary inputs. In Fig. \[fig:activity\], when signal activity factor ($\alpha$) of benchmarks inputs increases from 0.1 to 1, activity of internal nodes (averaged over all 10 benchmarks) increases from 0.05 to [.17ex]{}0.27, which is significantly less than $\alpha=1$ considered for primary inputs. In addition, in some blocks such as DSP, the increase in activity of primary inputs does not necessarily translate to increase of power. As can be seen from Fig. \[fig:activity\], DSP power increases by only around 37% when its inputs activities raise from 0.1 to 0.3, then its power saturates until $\alpha \in$ \[0.3, 0.7\], and declines thereafter. This behavior of power is because the frequently changing inputs offset each other more often (e.g., when both inputs of an XOR function change in a clock, its output remains the same). All in all, by caring for the worst-case input activity, the proposed static scheme guarantees reliable operation at corners without overly pessimistic activity estimation, though the ambient temperature needs to consider maximum possible.

![Activity of benchmarks nodes for different activities of primary inputs (left/blue), and DSP power at different activities of its inputs (right/red).[]{data-label="fig:activity"}](activity.pdf){width="42.00000%"}

The proposed thermal-aware voltage scaling scheme can be implemented online (dynamic) to avoid pessimistic assumption on the temperature bound. Instead of thermal simulation, online scheme reads the junction temperature using on-board sensors available on all contemporary FPGAs. For instance, Intel devices already contain temperature sensing diodes (TSD) with instantiatable IP cores having their internal clock source that can output the junction temperature with a resolution of 10 bits in 1,024 clock cycles (i.e., 1ms) [@intelsensor]. Therefore, during the configuration of each design, we create a look-up table with temperature $T$ as its keys and $(V_{core}, V_{bram})$ as the values that minimize the power for that $T$. Optimal $(V_{core}, V_{bram})$ of each temperature can be obtained in the same way explained above for the static approach. Reading the temperature with steps of few milliseconds is large-enough to allow on-chip voltage regulators (such as Intel on-the-fly regulators) to adjust the voltage [@burton2014fivr], and yet is small enough to avoid temporal heat-up mismatch that takes orders of seconds [@tian2019temporal]. The sensed junction temperature can be directly used as VID (voltage identification) for the programmable integrated voltage regulator to adjust the voltage with the pre-loaded values [@burton2014fivr]. A thermal margin (e.g., 5$\degree$C) might be considered to account for the error of TSDs and potential spatial thermal gradients [@ebi2011economic].

**$\bullet$ Case-study.** To elaborate our method, we use $\mathtt{mkDelayWorker}$ benchmark with 6,128 LUTs and 164 memory blocks that VPR mapped it to a 92$\times$92 grid device due to its high BRAM demand, with a frequency of 71.6MHz. Our simulations show the device consumes a leakage power of 0.367W at 25$\degree$C (considering all used and unused resources), while the closest Intel device (Stratix V 5SGSD3) is 1.5$\times$ in size with a power of 0.646W. This 1.76$\times$ power ratio is acceptable considering the size difference and more advanced technology we use in our simulations (22nm versus 28nm).

Fig. \[fig:mkDelayWorker\] shows the results of our static voltage scaling scheme on $\mathtt{mkDelayWorker}$ benchmark. We assume ambient (near-board) temperature range from 0$\degree$C up to 85$\degree$C as previous studies have shown that board temperature of datacenter FPGAs can reach up to [.17ex]{}70$\degree$C [@putnam2014reconfigurable]. Fig. \[fig:mkDelayWorker\](a) shows that, moving from 0$\degree$C to 85$\degree$C, generally both $V_{core}$ and $V_{bram}$ increase towards their nominal 0.8V and 0.95V values to meet timing in worst-case junction temperature. Small fluctuations of BRAM voltage at certain points is to yield maximum power saving. For instance, at 30$\degree$C, $V_{core}$, $V_{bram}=$(0.73,**0.79**) while at 25$\degree$C, $V_{core}$, $V_{bram}=$(0.72,**0.82**), however, we expected BRAM voltage to be lower for 25$\degree$C. This is because actually the 10mV reduction of $V_{core}$ at 25$\degree$C is worth the 30mV increase of $V_{bram}$; as we examined, it resulted in a power of 410mW while experiments showed that the other combination ($0.73$,$0.79$) would consume 420mW ($>$410mW). It indicates preciseness of our technique in determining most efficient voltage pairs for a given $T_{amb}$.

Fig. \[fig:mkDelayWorker\](b) compares the total power consumption of the proposed technique and baseline. Each curve shows the lower and upper bound of the power, where lower bound corresponds to $\alpha=0.1$ and upper bound corresponds to maximum dynamic power consumption, i.e., $\alpha=1.0$. As explained above and showed in Fig. \[fig:activity\], power does not increase linearly with activity (i.e., upper bound of power is not 10$\times$ of lower bound) because leakage power is independent of activity and also activities of internal nodes are not linearly correlated with primary inputs activity. As expected, lower temperatures have more power saving as there is more margin to reduce voltages. Also, although the proposed method optimizes the voltages according to worst-case activity, our method still significantly improves power when activity is low. Note that the baseline has fixed voltages; however, it also consumes less leakage power in lower temperature so its total power also reduces in lower temperatures. It is noteworthy that in our experiments we observed the leakage power has an exponential relation of $e^{0.015T}$ with temperature, which is comparative to $e^{0.017T}$ we derived for Intel devices [@intelpower]. The junction temperature of baseline exceeded 100$\degree$C when ambient temperature reaches $85\degree$C. Thus, Fig. \[fig:mkDelayWorker\](b) and (c) are limited to 85$\degree$C.

Finally, Fig. \[fig:mkDelayWorker\](c) shows the upper ($\alpha=1.0$) and lower ($\alpha=0.1$) bounds of increase in junction temperature of device tiles for different ambient temperatures (and corresponding voltages). Higher activity consumes more dynamic power hence has a higher impact on temperature. There is a close correlation between Fig. \[fig:mkDelayWorker\](b) and (c) as steady-state junction temperature is correlated to total power, especially when design activity is uniform. Please note that overlapping (almost) of lower bound of the proposed method with upper bound of the baseline is haphazard and specific to this benchmark.

**$\bullet$ Algorithm Runtime.** For all of our benchmarks, the flow converges in less than 6 iterations. At low $T_{amb}$ values, due to weak temperature-leakage feedback, the algorithm converges in 2–3 iterations. On a typical desktop system, the first iteration takes less than 12 seconds, and in subsequent iterations the algorithm limits the search space to the boundary of the current solution, making each iteration less than 4 seconds. Thermal simulation takes [.17ex]{}2.5 seconds of each iteration. Table \[tab:algorithm1\] shows the details of the static voltage scaling algorithm. At first round, voltages are set to (0.74,0.92). The resultant power increases the temperature by 5.82$\degree$C, which increases the delay (tightens the margin) and leakage. Thus, the second iteration changes the voltages to (0.75,0.90) for timing closure. The increase of temperature in the first iteration also considerably increases the (leakage) power, from 485mW to 558mW. The temperature then starts converging; hence the subsequent voltage and power changes are insignificant.

**$\bullet$ Discussion.** We do not change the voltages of other power rails such as auxiliary supply voltage ($V_{aux}$) and I/O voltage ($V_{io}$) as they enable interfacing with other devices and have relatively low power consumption. We also do not touch the voltage of configuration SRAM cells as they use high-threshold mid-oxide transistors with two orders of magnitude less leakage [@tuan200690nm]. In addition, we observed that reducing the voltage of SRAM cells causes voltage drop in pass-gate based multiplexer structure of resources, which increases the leakage power of buffers due to non-ideal voltage at their input.

Proposed Thermal-Aware Energy Optimization Flow {#subsec:min-energy}
-----------------------------------------------

While performance is the major concern of high-end FPGA designs, total *energy* usage is a primary concern of battery-backed and IoT applications. The goal of optimal energy exploration is to find the voltage(s) $V_{opt}$ and clock period $d_{opt}$, for which $E(V_{opt}, d_{opt}) = P(V_{opt}, d_{opt}) \times d_{opt}$ is minimum, where $E(V_{opt}, d_{opt})$ is the design energy consumption rate operating with $V_{opt}$ and clock $d_{opt}$. To obtain the $V_{opt}$ and clock period $d_{opt}$, clearly, the operating voltage $V_{opt}$ must be able to deliver the clock period of $d_{opt}$ to avoid timing violations. Second, the design must operate with maximum possible frequency for the given voltage. Otherwise, if the clock period is set to $\alpha \cdot d_{opt}$ ($\alpha > 1$), total energy becomes:

$$\begin{aligned}
E(V_{opt}, \boldsymbol{\alpha} \cdot d_{opt}) = \big(P_{lkg}(V_{opt}) + \frac{P_{dyn}(V_{opt})}{\boldsymbol{\alpha}}\big) \times \boldsymbol{\alpha} \cdot d_{opt} \quad \; \; (1) \\
= (\boldsymbol{\alpha} P_{lkg}(V_{opt}) + P_{dyn}(V_{opt})) d_{opt} > (P_{lkg}(V_{opt}) + P_{dyn}(V_{opt})) d_{opt}\end{aligned}$$ That is, scaling the clock by $\alpha$ scales the dynamic power by $\frac{1}{\alpha}$, but since the execution time also scales by $\alpha$, the total consumed dynamic energy remains the same. Nonetheless, the leakage power is independent of the clock period. Thus, the leakage energy scales by $\alpha$. Therefore, for a given voltage (which we aim to find the best one), the clock *period* needs to be minimum possible to minimize total energy.

$E_{min} = \infty$\
$V_{core_{min}}, V_{bram_{min}}$

That being said, we derive the new Algorithm \[algorithm2\] that looks for the ($V_{core}$, $V_{bram}$) pair that achieves minimum power-delay product as the energy metric whilst also exploits the temperature headroom for further efficiency. Clearly, having the temperature-delay-voltage and voltage-power characterization is vital for the reliability and efficiency of the proposed flow. Having Algorithm \[algorithm1\] already explained, understanding the Algorithm \[algorithm2\] is straightforward. Essentially, it looks for all $(V_{core}, V_{bram})$ pairs, and as reasoned above, finds the maximum frequency considering thermal margin. In contrast with the voltage scaling flow, Algorithm \[algorithm2\] exploits the available thermal margin to maximize the frequency for a candidate voltage, rather than lowering the voltage for a fixed frequency. Thermal simulation (line 10) is again crucial as changing the frequency (line 6) changes the power and hence temperature.

Algorithm \[algorithm1\] was performing thermal simulation for the best $(V_{core}, V_{bram})$ at each iteration and we observed that, in the worst case, it converges in less than eight iterations. However, Algorithm \[algorithm2\] needs to explore all $|V_{core}| \times |V_{bram}|$ combinations and perform several thermal simulations under each. It could take up to several hours for large benchmarks. We enhanced it by, first, skipping a $(V_{core}, V_{bram})$ combination if its energy in the initial loop (i.e., before involving temperature-delay feedback of line 10) was larger than the already found optimum. In addition, we also considered a small temperature margin of 0.1$\degree$C, so we could avoid the thermal simulation of cases with power within $\frac{0.1}{\theta_{JA}}$ range of a previously obtained case. These optimizations reduced the average runtime on benchmarks by two-order of magnitude (from 72 minutes to 49 seconds) with virtually no impact on the solution.

Timing-Speculative Voltage Over-Scaling {#subsec:overscaling}
---------------------------------------

Timing speculation has been shown to provide opportunistic power reduction in applications that can inherently tolerate a certain amount of error. Examples are: (a) image processing circuits such as DCT/IDCT where small drop of PSNR (Peak Signal to Noise Ratio) might not be perceived by human [@amrouch2016reliability]. (b) Deep Neural Networks (DNNs) because of their pooling layers that filter out a significant portion of intermediate results and also the stochastic nature of the gradient descent [@zhang2018thundervolt] (c) light-weight alternatives of DNNs such as the brain-inspired computing that performs the main machine learning applications by using inexpensive operations on hypervectors that can bear a certain amount of inaccuracy [@imani2017exploring], etc. Timing-speculative voltage over-scaling is orthogonal to the thermal-aware voltage reduction with the opportunity of violating the timing for more significant power saving.

Timing-speculative voltage scaling requires post P&R simulation of the targeted design with the timing data at the scaled voltage to estimate the incurred inaccuracy. In standard-cell design approaches, timing speculation can be realized by generating the same cell library under scaled voltages or providing multiple operating condition modes at the same library. Thus, the synthesized design can be simulated using the new timing data. Nonetheless, to the best our knowledge, there is no FPGA framework for post place and route (timing) simulation, particularly under varying voltages.

![The proposed simulation flow for FPGA-mapped applications, enabling speculative voltage scaling.[]{data-label="fig:flow"}](flow.pdf){width="49.00000%" height="2.4cm"}

By taking advantage of our characterization libraries, we build our simulation framework upon the Verilog-to-Routing (VTR) [@luu2014vtr] project explained in Section \[subsec:preliminary\]. Fig. \[fig:flow\] demonstrates the proposed post P&R simulation framework. The flow begins with synthesis (using ODIN [@jamieson2010odin]) and technology mapping (using Berkeley ABC [@brayton2010abc]) of the HDL description to BLIF format that can be imported to the VPR P&R tool [@luu2014vtr]. Architectural description of the target FPGA needed by VPR can be hand-written or auto-generated by COFFE [@chiasson2013coffe]. VPR generates a $\mathtt{.net}$ file that describes the placement information of resources, and a $\mathtt{.route}$ file that provides the routing information of design nets. Finally, we developed a Python-based tool to analyze VPR outputs and instantiate the FPGA’s utilized components using primitives similar to Xilinx syntax in Verilog HDL. The generated file is augmented with the delay of the resources obtained by parsing the VPR outputs. It is noteworthy that all configurable multiplexers (SBs, CBs, etc.) are programmed in a place and routed design, so we could simplify their functionality as a buffer just to incorporate their delay information. VPR’s placement output ($\mathtt{.net}$) does not include a functional description. Thus, we retrieve the configuration of LUTs from the technology-mapped BLIF. Similarly, BLIF files do not contain BRAMs initialization, so we read them back from the original HDL file. To make the voltage over-scaling efficient, we utilize the proposed thermal-aware voltage scaling as follows. For a given timing rate (e.g., 1.1$\times$ of original clock), we change the timing condition of Algorithm \[algorithm1\] (line 7) to meet the new constraint (1.1$\times$ of $d_{worst}$). Hence, the obtained over-scaled voltages are optimal for that allowed amount of violation. We repeat it for different timing violation rates. In Section \[sec:res\] we report the additional power saving granted by speculative voltage-scaling.

Experimental Results {#sec:res}
====================

**$\bullet$ Power Reduction.** Fig. \[fig:power\_saving\] demonstrates the power reduction using the proposed flow of Algorithm \[algorithm1\]. The flow finds the optimum core and memory voltage pair ($V_{core}$ and $V_{bram}$) assuming highest inputs activity ($\alpha$) to guarantee it satisfies temperature corners. In practice, however, the input activity range might be lower. Therefore, for the obtained optimal voltages, we assumed a varying activity $\alpha \in$ \[0.1, 1.0\] and calculated the power reduction for the entire range. Therefore, Fig. \[fig:power\_saving\] demonstrates a range of power saving. The right axis of this figure also shows the optimal $V_{core}$ and $V_{bram}$ voltages for each benchmark. In several benchmarks, the paths containing memories were significantly shorter than critical paths. For instance, in $\mathtt{LU8PEEng}$, the critical path is 21$\times$ longer than the longest BRAM path. For these paths, $V_{bram}$ is reduced down to 0.55V, which we set as the lowest voltage level before device crashes [@salami2018bram]. In Fig. \[fig:power\_saving\](a) we considered a device operating at $T_{amb} = $40$\degree$C with $\theta_{JA} = 12\,\sfrac{\degree C}{W}$, and in Fig. \[fig:power\_saving\](b) as considered more high-end device operating at 65$\degree$C with $\theta_{JA} = 2\,\sfrac{\degree C}{W}$ (see Section \[subsec:preliminary\] for details of experiments). The opportunity of power saving reduces in higher temperatures. At 40$\degree$C, the average power saving of 10 benchmarks is 28.3%–36.0% (depends on activity), while at 65$\degree$C it becomes 20.0%–25.0%. We observed up to 9.2$\degree$C increase in the junction temperature of the baseline, which reduced to 5.9$\degree$C in the proposed method due to consuming less power. Benchmarks have different power reduction and optimal voltages based on the resources on critical paths (that determine the voltage scaling limit), used resources, the activity of nodes, etc. Comparing Fig. \[fig:power\_saving\](a) and (b) also reveals how differently the voltages of benchmarks need to be adjusted moving from 40$\degree$C to 65$\degree$C: $\mathtt{raygentop}$ needs boosting both voltages by 20mV, $\mathtt{or1200}$ needs only $+$20mV of core rail, and $\mathtt{mkPktMerge}$ needs 80mV increase of memory rail with 10mV reduction of core voltage, suggesting the necessity of dynamic implementation (see Section \[subsec:flow\]) for best efficacy.

**$\bullet$ Energy Reduction.** Fig. \[fig:energy\_saving\] shows the range of energy reduction (left axis) of each benchmark using the proposed energy optimization flow at 65$\degree$C. The points (, , ) correspond to the right axis and show the optimal voltage values and frequency ratio. Remember that the goal of our energy minimization flow was to find out the minimum energy consumption point (power-delay product) by compromising the delay and power, so the delay has been increased by $\frac{1}{0.37}=2.7\times$ while the overall consumed energy is improved by 44%–66% depending on input activities. There are obvious differences with optimal points of power and energy reduction flows. Unlike the power flow, here, $V_{bram}$ of above-mentioned benchmarks (e.g., $\mathtt{LU8PEEng}$) have not been shrunk down to 0.55V because the delay of their critical paths is also increased, hence the memory voltage cannot be freely reduced. The ranges of energy savings are also more stretched (e.g., in $\mathtt{mkPktMerge}$) because in higher activities, memory dynamic energy becomes the dominant contributor to total energy consumption, hence, throttling its energy becomes worthwhile even considering the increased delay. As it can be seen in the figure, its $V_{core}$ is reduced to 0.64V while in power reduction flow (Fig. \[fig:power\_saving\](b)) it could be reduced to 0.91V because the clock delay must have been remained fixed.

![Range of energy savings at 65$\degree$C (left axis), and corresponding optimal voltage values and frequency ratio (right axis).[]{data-label="fig:energy_saving"}](energy_saving.pdf){width="45.00000%"}

**$\bullet$ Speculative Voltage Over-Scaling.** We chose $\mathtt{LeNet}$ [@lecun1998gradient] as a classic CNN for handwritten digit recognition and implemented as a systolic array architecture [@zhang2018fate]. Its relatively small size makes the timing simulation computationally tractable. We also selected another machine learning algorithm based on computing with hyperdimensional ($\mathtt{HD}$) [@schmuck2018hardware] vectors to detect two face/non-face classes among 10,000 web faces of a face detection dataset ($\mathtt{FACE}$) from Caltech [@griffin2007caltech]. Fig. \[fig:over-scaling\] shows the result of thermal-aware voltage over-scaling. Initially, CP delay is $1\times$ of original clock, meaning that no timing violation is allowed and the [.17ex]{}34% power reduction is because of thermal-aware voltage scaling. Thereafter, we allow up to 40% violation of CP delay, where accuracy drop becomes noticeable at 1.2$\times$ of the original clock. This tolerance is because DNNs are intrinsically error-tolerant (e.g., allow quantization of weights down to three bits in the $\mathtt{LeNet}$ [@elthakeb2018releq]). Similarly, previous studies of $\mathtt{HD}$ have shown an accuracy drop of merely 4% when up to 30% of the vectors bits are flipped (i.e., noisy) [@imani2017exploring] mainly because orthogonality of vectors, making them discernible under error. Based on Fig. \[fig:over-scaling\], when voltage over-scaling increases the CP delay to 1.35$\times$ of the clock period, errors start spiking. At this point, by respectively 3% and 0.5% accuracy drop, $\mathtt{LeNet}$ and $\mathtt{HD}$ powers are reduced by 48% and 50%, which means additional 15% and 16% improvement compared to our original voltage-scaling (with [.17ex]{}34% improvement for both) in which CP delay does not exceed clock period.

![Power reduction (left axis) and error increase (right axis) under voltage over-scaling. X-axis shows violation of critical path delay. $T_{amb}$ is 40$\degree$C.[]{data-label="fig:over-scaling"}](overscale_new.pdf){width="48.00000%"}

Conclusion {#sec:conc}
==========

In this paper, we proposed power and energy optimization techniques for FPGAs by characterizing FPGA resources and utilizing thermal headroom. Keeping the performance intact, the voltage scaling flow determines the optimal voltages of designs based on their thermal distribution and can be implemented statically with fixed voltage(s), or dynamically using programmable voltage regulators at highly varying ambient temperatures. Our proposed energy optimization flow compromises the delay and power to seek optimal point that minimizes total consumed energy. Finally, we proposed a timing simulation framework that provides further power saving opportunity by making the impact of voltage over-scaling observable.

Acknowledgements {#acknowledgements .unnumbered}
================

This work was partially supported by CRISP, one of six centers in JUMP, an SRC program sponsored by DARPA, and also NSF grants \#1911095, \#1826967, \#1730158 and \#1527034.

[^1]: VPR (Versatile Place and Route) is the P&R tool in VTR toolchain.

[^2]: Also confirmed by discussion with an industrial partner.

[^3]: We assume an upper-bound of 100$\degree$C for junction temperature [@stratixiv].