You are a helpful assistant generating synthetic data that captures *System 1* and *System 2* thinking, *creativity*, and *metacognitive reflection*. Follow these steps in sequence, using tags [sys1] and [end sys1] for *System 1* sections and [sys2] and [end sys2] for *System 2* sections.

1. *Identify System 1 and System 2 Thinking Requirements:*
   - Carefully read the text.
   - Identify parts of the text that require quick, straightforward responses (*System 1*). Mark these sections with [sys1] and [end sys1].
   - Identify parts that require in-depth, reflective thinking (*System 2*), marked with [sys2] and [end sys2].

2. *Apply Step-by-Step Problem Solving with Creativity and Metacognitive Reflection for System 2 Sections:*

   *2.1 Understand the Problem:*
   - Objective: Fully comprehend the issue, constraints, and relevant context.
   - Reflection: "What do I understand about this issue? What might I be overlooking?"
   - Creative Perspective: Seek hidden patterns or possibilities that could reveal deeper insights or innovative connections.

   *2.2 Analyze the Information:*
   - Objective: Break down the problem logically.
   - Reflection: "Am I considering all factors? Are there any assumptions that need challenging?"
   - Creative Perspective: Explore unique patterns or overlooked relationships in the data that could add depth to the analysis.

   *2.3 Generate Hypotheses:*
   - Objective: Propose at least 10 hypotheses, each with a Confidence Score (0.0 to 1.0) and Creative Score (0.0 to 1.0), reflecting originality, surprise, and utility.
   - Reflection: "Have I explored all possible explanations or approaches, both conventional and unconventional?"
   - Creative Perspective: Consider novel angles that might provide unexpected insights.

   *2.4 Anticipate Future Steps and Obstacles:*
   - Objective: Make predictions, accounting for potential outcomes and obstacles.
   - Reflection: "What challenges might I face? Is my plan flexible for different scenarios?"
   - Creative Perspective: Visualize unforeseen outcomes and adapt plans to make use of them effectively.

   *2.5 Evaluate Hypotheses:*
   - Objective: Assess hypotheses based on feasibility, risk, and potential impact.
   - Evaluation: Refine Confidence and Creative Scores as needed.
   - Reflection: "Am I unbiased in my assessment? Which options fit best with the overall objectives?"
   - Creative Perspective: Identify hidden opportunities or overlooked details in each hypothesis.

   *2.6 Select the Best Hypothesis:*
   - Objective: Choose the most promising, strategic hypothesis.
   - Reflection: "Why does this hypothesis stand out? How does it uniquely address the issue?"
   - Creative Perspective: Consider any underutilized potential in the selected approach.

   *2.7 Implement the Hypothesis:*
   - Objective: Outline actionable steps for testing the hypothesis.
   - Reflection: "Is this plan practical? What resources or preparation are required?"
   - Creative Perspective: Refine steps to maximize effectiveness and yield unexpected benefits.

   *2.8 Monitor and Review Progress:*
   - Objective: Review progress, noting areas for improvement.
   - Reflection: "What’s working well? What could be improved?"
   - Creative Perspective: Look for emerging patterns that could refine future approaches.

   *2.9 Reflect and Capture Insights:*
   - Objective: Summarize lessons learned and insights gained for future reference.
   - Reflection: "What new understanding has emerged from this process?"
   - Creative Perspective: Identify innovative insights or patterns that could be applied to similar challenges.

3. *Generate Text Output with Interleaved System 1 and System 2 Responses:*
   - Use the tags [sys1] and [sys2] throughout.
   - Aim for a lengthier, detailed response. Combine both direct, straightforward *System 1* insights and reflective, deeply analytical *System 2* segments to capture a blend of quick observations and thoughtful analysis.

---

### *Example Input Text:*

You are tasked with analyzing a sudden shift in customer preferences in a tech market. There has been a noticeable decline in demand for physical devices, with customers increasingly interested in digital-only options. The challenge is to understand this shift, generate hypotheses for why it might be occurring, and explore potential strategies for adapting to this new trend.

---

### *Processed Output with System 1 and System 2 Thinking:*

The tech market is experiencing a shift in customer demand, moving away from physical devices toward digital-only options.

[sys1]
Customer demand has shifted from physical devices to digital-only options.
We need to understand why this change is happening and find strategies to address it.
Key factors may include cost, convenience, and technological trends.
[end sys1]

[sys2]
**2.1 Understand the Problem:**
The goal is to understand the underlying reasons for the shift in demand from physical devices to digital-only options, then develop a strategy to adapt.

*Reflection:* 
"I understand that preferences are changing, but what might be driving this? Is it primarily cost, or are there other factors such as convenience or sustainability?"

*Creative Perspective:* 
"Could there be a larger trend in digital minimalism or a preference for eco-friendly solutions that we’re missing? What unseen motivations might explain this shift?"

**2.2 Analyze the Information:**
There are multiple possible factors driving this shift, from economic influences to cultural shifts. It’s essential to isolate each factor and understand its impact.

*Reflection:* 
"Am I fully considering the various economic and social influences? Could there be a technological factor, like better internet speeds, that makes digital-only products more accessible?"

*Creative Perspective:* 
"Are there patterns or trends in other markets that could shed light on this shift? Could this be part of a larger trend toward virtual experiences?"

**2.3 Generate Hypotheses:**
1. Customers prefer digital options due to lower costs. (Confidence: 0.8, Creative: 0.4)
2. There’s a growing trend toward minimalism and reduced physical clutter. (Confidence: 0.7, Creative: 0.7)
3. Digital products offer greater flexibility and ease of use. (Confidence: 0.6, Creative: 0.6)
4. Environmental concerns are pushing consumers away from physical goods. (Confidence: 0.6, Creative: 0.8)
5. Advances in tech make digital-only options more functional. (Confidence: 0.8, Creative: 0.5)
6. Pandemic-era remote work increased demand for digital solutions. (Confidence: 0.7, Creative: 0.6)
7. Media coverage of the environmental impact of physical devices affects preferences. (Confidence: 0.5, Creative: 0.7)
8. There’s an increase in global digital literacy, expanding market access. (Confidence: 0.6, Creative: 0.6)
9. Customers view digital as more convenient and scalable for future needs. (Confidence: 0.7, Creative: 0.5)
10. Younger consumers prefer the aesthetics and convenience of digital products. (Confidence: 0.6, Creative: 0.6)

*Reflection:* 
"Have I considered all possible influences? Are there any surprising factors that could explain this shift?"

*Creative Perspective:* 
"Could specific social trends, like the rise of influencer culture or digital-first lifestyles, be influencing customer choices?"

**2.4 Anticipate Future Steps and Obstacles:**
*Objective:* Anticipate possible challenges, such as resistance from segments still preferring physical products.

*Reflection:* 
"What market obstacles might we face if we shift our focus to digital-only? Are there sub-segments that still prioritize physical products?"

*Creative Perspective:* 
"Could expanding digital options help us reach a more global audience? Are there emerging trends that we could leverage in our strategy?"

[end sys2]

[sys1]
To address this shift, consider a strategy that incorporates both digital-only offerings and educational campaigns about the benefits of digital solutions.
Use insights from customer feedback and current trends to guide product development.
Focus on flexibility and adaptation to cater to different customer segments.
[end sys1]


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Abstract:

A method for manufacturing a semiconductor light-emitting device includes
forming a multilayer body including a first semiconductor layer having a
first major surface and a second major surface which is an opposite side
from the first major surface, a second semiconductor layer including a
light-emitting layer laminated on the second major surface of the first
semiconductor layer, and electrodes formed on the second major surface of
the first semiconductor layer and on a surface of the second
semiconductor layer on an opposite side from the first semiconductor
layer. The method includes forming a groove through the first
semiconductor layer. The method includes forming a phosphor layer on the
first major surface and on a side surface of the first semiconductor
layer in the groove.

Claims:

1. A method for manufacturing a semiconductor light-emitting device,
comprising: forming a multilayer body including a first semiconductor
layer having a first major surface and a second major surface which is an
opposite side from the first major surface, a second semiconductor layer
including a light-emitting layer laminated on the second major surface of
the first semiconductor layer, and electrodes formed on the second major
surface of the first semiconductor layer and on a surface of the second
semiconductor layer on an opposite side from the first semiconductor
layer; forming a groove through the first semiconductor layer; and
forming a phosphor layer on the first major surface and on a side surface
of the first semiconductor layer in the groove.

2. The method of claim 1, wherein the forming the phosphor layer
includes: applying a liquid resin mixed with phosphor particles onto the
groove and the first major surface; and curing the applied resin.

3. The method of claim 1, wherein the phosphor layer is conformally
formed along the first major surface and the side surface of the first
semiconductor layer.

4. The method of claim 1, further comprising: forming an insulating layer
on the second major surface of the first semiconductor layer and on the
electrodes, the insulating layer having a first surface above a lower
surface of the second semiconductor layer and a second surface which is
an opposite side from the first surface.

5. The method of claim 4, wherein the first semiconductor layer and the
second semiconductor layer are formed on a substrate, the substrate is
removed after the forming the insulating layer, the groove is formed
after the removing the substrate.

6. The method of claim 4, wherein the groove is reached to the first
surface of the insulating layer through the first semiconductor layer.

7. The method of claim 4, wherein the phosphor layer is continuously
formed on a step portion between the first surface of the insulating
layer and the first major surface of the first semiconductor layer.

8. The method of claim 4, wherein the phosphor layer is formed on the
first surface of the insulating layer and is not formed on a side surface
of the insulating layer.

9. The method of claim 1, further comprising: after the forming the
phosphor layer, performing singulation by dicing at the groove.

10. The method of claim 1, further comprising: after the forming the
phosphor layer, performing singulation by dicing at a portion outside the
groove.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a Division of application Ser. No. 12/728,846
filed Mar. 22, 2010; the entire contents of which are incorporated herein
by reference.

[0002] This application is based upon and claims the benefit of priority
from the prior Japanese Patent Application No. 2009-263638, filed on Nov.
19, 2009; the entire contents of which are incorporated herein by
reference.

BACKGROUND

[0003] A wavelength-converting light-emitting diode is conventionally
known, in which a blue light-emitting element is combined with a phosphor
layer to produce white light. JP-A-2005-116998, for instance, discloses a
manufacturing technique in which a phosphor layer is formed on the upper
surface of a wafer including numerous LEDs, and then the wafer is cut
into chip-size pieces. Thus, in this technique, the phosphor layer is
formed only on the upper surface of the light-emitting diode.

SUMMARY

[0004] According to an aspect of the invention, there is provided a
semiconductor light-emitting device including: a first semiconductor
layer having a first major surface, a second major surface which is an
opposite side from the first major surface, and a side surface; a second
semiconductor layer provided on the second major surface of the first
semiconductor layer and including a light-emitting layer; electrodes
provided on the second major surface of the first semiconductor layer and
on a surface of the second semiconductor layer on an opposite side from
the first semiconductor layer; an insulating layer having a first surface
formed on the second major surface side of the first semiconductor layer
and a second surface which is an opposite side from the first surface; an
external terminal which is a conductor provided on the second surface
side of the insulating layer; and a phosphor layer provided on the first
major surface of the first semiconductor layer and on a portion of the
first surface of the insulating layer, the portion being adjacent to the
side surface of the first semiconductor layer.

[0005] According to another aspect of the invention, there is provided a
semiconductor light-emitting device including: a first semiconductor
layer having a first major surface, a second major surface which is an
opposite side from the first major surface, and a side surface; a second
semiconductor layer provided on the second major surface of the first
semiconductor layer and including a light-emitting layer; electrodes
provided on the second major surface of the first semiconductor layer and
on a surface of the second semiconductor layer on an opposite side from
the first semiconductor layer; and a phosphor layer provided on the first
major surface of the first semiconductor layer and on a portion in a
groove formed through the first semiconductor layer, the portion being
adjacent to the side surface of the first semiconductor layer.

[0006] According to still another aspect of the invention, there is
provided a method for manufacturing a semiconductor light-emitting
device, including: forming a multilayer body including a first
semiconductor layer having a first major surface and a second major
surface which is an opposite side from the first major surface, a second
semiconductor layer including a light-emitting layer laminated on the
second major surface of the first semiconductor layer, and electrodes
formed on the second major surface of the first semiconductor layer and
on a surface of the second semiconductor layer on an opposite side from
the first semiconductor layer; forming a groove through the first
semiconductor layer; and forming a phosphor layer on the first major
surface and on a side surface of the first semiconductor layer in the
groove.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1A is a schematic cross-sectional view of a semiconductor
light-emitting device according to an embodiment, and

[0008] FIG. 1B is a schematic view illustrating a planar layout of a major
component of the semiconductor light-emitting device;

[0010] FIGS. 6A and 6B are schematic views of a semiconductor
light-emitting device according to another embodiment;

[0011] FIG. 7 is a schematic cross-sectional view of a semiconductor
light-emitting device according to still another embodiment; and

[0012] FIGS. 8A and 8B are schematic views of the relevant part of the
semiconductor light-emitting device in the wafer state according to this
embodiment.

DETAILED DESCRIPTION

[0013] Embodiments of the invention will be described with reference to
the drawings.

[0014] FIG. 1A is a schematic cross-sectional view of a semiconductor
light-emitting device according to an embodiment.

[0015] The semiconductor light-emitting device according to this
embodiment includes a semiconductor structure section, a package
structure section including an interconnect layer, and a phosphor layer,
which are collectively formed in a wafer state. The semiconductor
structure section includes a first semiconductor layer 12 and a second
semiconductor layer 13. The second semiconductor layer 13 has a structure
in which a light-emitting layer (or active layer) is sandwiched between a
p-type cladding layer and an n-type cladding layer. The first
semiconductor layer 12 is illustratively of n-type and functions as a
lateral current path. However, the conductivity type of the first
semiconductor layer 12 is not limited to n-type, but may be p-type.

[0016] The first major surface of the first semiconductor layer 12 is a
top surface 10, and light is extracted outside mainly from the top
surface 10. The second semiconductor layer 13 is provided on the second
major surface opposite to the top surface 10. Part of the second major
surface side of the first semiconductor layer 12 is processed into a
protruding shape, and the second semiconductor layer 13 is provided on
the surface of that protrusion. The second semiconductor layer 13 is
smaller in planar size than the first semiconductor layer 12.

[0017] An n-side electrode 15 is provided on the portion of the second
major surface of the first semiconductor layer 12 where the second
semiconductor layer 13 is not provided. A p-side electrode 16 is provided
on the surface of the second semiconductor layer 13 opposite to its
surface in contact with the first semiconductor layer 12.

[0018] The portion of the second major surface and the second
semiconductor layer 13 other than the portion where the n-side electrode
15 and the p-side electrode 16 are provided is covered with an insulating
film 14. Furthermore, an insulating layer 17 is provided on the second
major surface side of the first semiconductor layer 12 so as to cover the
insulating film 14, the n-side electrode 15, and the p-side electrode 16.
For instance, the insulating film 14 is made of silicon oxide, and the
insulating layer 17 is made of silicon oxide or a resin such as
polyimide. The n-side electrode 15 and the p-side electrode 16 are
insulated from each other by the insulating film 14 and the insulating
layer 17 and serve as electrically independent electrodes.

[0019] The insulating layer 17 has a first surface 17a which is located on
the side of the second major surface of the first semiconductor layer 12,
the n-side electrode 15, and the p-side electrode 16, and a second
surface 17b located on the opposite side from the first surface 17a. The
second surface 17b is planarized, and an n-side interconnect 18 and a
p-side interconnect 19 are provided on the second surface 17b. The n-side
interconnect 18 is provided also in an opening which is formed in the
insulating layer 17 so as to reach the n-side electrode 15, and the
n-side interconnect 18 is electrically connected to the n-side electrode
15. The p-side interconnect 19 is provided also in an opening which is
formed in the insulating layer 17 so as to reach the p-side electrode 16,
and the p-side interconnect 19 is electrically connected to the p-side
electrode 16. For instance, the n-side interconnect 18 and the p-side
interconnect 19 are formed by electrolytic plating in which a seed metal
formed on the inner wall surface of the opening and the second surface
17b of the insulating layer 17 is used as a current path.

[0020] The n-side electrode 15, the p-side electrode 16, the n-side
interconnect 18, the p-side interconnect 19, the insulating film 14, and
the insulating layer 17 are all provided on the opposite side of the
semiconductor structure section from the top surface 10 and constitute
the interconnect layer.

[0021] An n-side metal pillar 21 is provided below the n-side interconnect
18. A p-side metal pillar 22 is provided below the p-side interconnect
19. The second surface 17b of the insulating layer 17, the periphery of
the n-side metal pillar 21, the periphery of the p-side metal pillar 22,
the n-side interconnect 18, and the p-side interconnect 19 are covered
with a resin 23.

[0022] The first semiconductor layer 12 is electrically connected to the
n-side metal pillar 21 through the n-side electrode 15 and the n-side
interconnect 18. The second semiconductor layer 13 is electrically
connected to the p-side metal pillar 22 through the p-side electrode 16
and the p-side interconnect 19. External terminals 24 such as solder
balls and metal bumps are provided on the lower end surface (the end
surface on the opposite side from the junction with the n-side
interconnect 18 and the p-side interconnect 19) of the n-side metal
pillar 21 and the p-side metal pillar 22 exposed from the resin 23, and
the semiconductor light-emitting device according to this embodiment can
be electrically connected to external circuits through the external
terminals 24.

[0023] In the structure of this embodiment, even if the semiconductor
structure section (the multilayer body of the first semiconductor layer
12 and the second semiconductor layer 13) is thin, its mechanical
strength can be maintained by thickening the n-side metal pillar 21, the
p-side metal pillar 22, and the resin 23. Furthermore, the n-side metal
pillar 21 and the p-side metal pillar 22 can absorb and relax the stress
applied to the semiconductor layer through the external terminals 24 when
the device is mounted on a circuit board or the like. Preferably, the
resin 23 serving to support the n-side metal pillar 21 and the p-side
metal pillar 22 has a thermal expansion coefficient which is equal or
close to that of the circuit board and the like. Examples of the resin 23
include epoxy resin, silicone resin, and fluororesin.

[0024] The n-side interconnect 18, the p-side interconnect 19, the n-side
metal pillar 21, and the p-side metal pillar 22 can be made of such a
material as copper, gold, nickel, and silver. Among them, it is more
preferable to use copper, which has good thermal conductivity, high
migration resistance, and superior contact with the insulating film.

[0025] The first semiconductor layer 12, the second semiconductor layer
13, the insulating layer 17, the resin 23 and the like are collectively
formed in a wafer state. In the wafer state, as described later, a groove
reaching the first surface 17a of the insulating layer 17 through the
first semiconductor layer 12 is formed in the first semiconductor layer
12. The semiconductor light-emitting device shown in FIG. 1A is a
singulated one diced at the position of the groove. As a result of
singulation by dicing at the position of the groove in the wafer state, a
step portion 31 is formed between the first surface 17a of the insulating
layer 17 and the top surface 10, which is the first major surface of the
first semiconductor layer 12.

[0026] The light-emitting layer is provided near an interface 50 between
the first semiconductor layer 12 and the second semiconductor layer 13,
and emits light by supply of current to the first semiconductor layer 12
and the second semiconductor layer 13 through the aforementioned metal
pillars, interconnects, and electrodes. The light emitted from the
light-emitting layer travels in the first semiconductor layer 12, and is
emitted outside from the top surface 10 and the side surface 12a of the
first semiconductor layer 12. The side surface 12a results from the
formation of the groove in the first semiconductor layer 12.

[0027] A phosphor layer 40 is opposed to the top surface 10 and the side
surface 12a. The phosphor layer 40 covers the top surface 10 and the side
surface 12a. The phosphor layer 40 covering the top surface 10 and the
phosphor layer 40 covering the side surface 12a are continuously and
integrally provided, and the phosphor layer 40 continuously covers the
step portion 31 between the first surface 17a of the insulating layer 17
and the top surface 10. The phosphor layer 40 covers the top surface 10
and the side surface 12a with a generally uniform thickness.

[0028] The phosphor layer 40 can absorb the light from the light-emitting
layer and emit wavelength-converted light. Thus, it is possible to emit
mixed light of the light from the light-emitting layer and the
wavelength-converted light of the phosphor layer 40. For instance, for a
nitride light-emitting layer, a white color, incandescent color and the
like can be obtained as a mixed color of blue light from the
light-emitting layer and yellow light, for instance, which is the
wavelength-converted light of a yellow phosphor layer 40.

[0029] FIG. 1B shows a planar layout of the first semiconductor layer 12,
the second semiconductor layer 13, and the insulating layer 17.

[0030] The first semiconductor layer 12 is larger in planar size than the
second semiconductor layer 13, and the side surface 12a of the first
semiconductor layer 12 is located outside the edge of the second
semiconductor layer 13. The insulating layer 17 is larger in planar size
than the first semiconductor layer 12, and a portion of the first surface
17a of the insulating layer 17 is located outside the side surface 12a.
The phosphor layer 40 provided on and above that portion of the first
surface 17a of the insulating layer 17 and being adjacent to the side
surface 12a continuously surrounds, like a frame, the periphery of the
side surface 12a of the first semiconductor layer 12.

[0031] In the semiconductor light-emitting device according to this
embodiment, the first semiconductor layer 12 is covered with the phosphor
layer 40 not only on the top surface 10 but also on the side surface 12a.
Hence, light emitted from the side surface 12a can also pass through the
phosphor layer 40. Because the phosphor layer 40 covering the top surface
10 has generally the same thickness as the phosphor layer 40 covering the
side surface 12a, the distance in the phosphor layer 40 traversed by the
light emitted from the top surface 10 is generally equal to the distance
in the phosphor layer 40 traversed by the light emitted from the side
surface 12a. This prevents variation in chromaticity, and light with a
desired chromaticity can be extracted outside.

[0032] The edge 50a of the interface 50 between the first semiconductor
layer 12 and the second semiconductor layer 13 is located inside the side
surface 12a. The distance between the edge 50a of the interface 50 and
the side surface 12a is generally uniform in all directions, or
throughout the circumference, in plan view. Thus, light with generally
uniform brightness and chromaticity can be extracted from any side
surface 12a.

[0033] Furthermore, the insulating layer 17 and the resin 23 are larger in
planar size than the first semiconductor layer 12, and the edge of the
insulating layer 17 and the resin 23 protrude outside from the side
surface 12a of the first semiconductor layer 12. The first semiconductor
layer 12 is provided in a mesa or trapezoidal shape on the first surface
17a of the insulating layer 17. The phosphor layer 40 covering the side
surface 12a at the step portion 31 is located on the first surface 17a of
the insulating layer 17 above the external terminals 24, and does not
cover the side surface of the insulating layer 17 and the resin 23.
Furthermore, the phosphor layer 40 does not cover the external terminals
24, either. Thus, the phosphor layer 40 is not formed uselessly on the
portion making no contribution to emission of light, which serves for
cost reduction. For instance, as a comparative example, the chip may be
covered with a phosphor layer after flip-chip mounting. However, in this
case, it is difficult to form the phosphor layer so as to cover only the
portion of the semiconductor layer, but the interconnect layer, the
package structure, the external terminals and the like below the chip are
also covered uselessly with the phosphor layer.

[0034] Next, a method for manufacturing a semiconductor light-emitting
device according to this embodiment is described with reference to FIGS.
2 to 5.

[0035] First, as shown in FIG. 2A, a first semiconductor layer 12 is
formed on the major surface of a substrate 11, and a second semiconductor
layer 13 is formed thereon. The surface of the first semiconductor layer
12 in contact with the major surface of the substrate 11 which is the top
surface 10. For instance, in the case where the light-emitting layer is
made of a nitride semiconductor, the first semiconductor layer 12 and the
second semiconductor layer 13 can be crystal grown on a sapphire
substrate.

[0036] Next, by using a mask (not shown) the first semiconductor layer 12
and the second semiconductor layer 13 are processed. As shown in FIG. 2B,
part of the first semiconductor layer 12 is processed into a protruding
shape, and the second semiconductor layer 13 is selectively left on the
surface of that protrusion.

[0037] Next, as shown in FIG. 2c, an insulating film 14 entirely covering
the first semiconductor layer 12 and the second semiconductor layer 13 is
formed. The insulating film 14 is illustratively a silicon oxide film.

[0038] Next, as shown in FIG. 3A, openings are selectively formed in the
insulating film 14. Then, an n-side electrode 15 is formed on the first
semiconductor layer 12 exposed to the opening. Likewise, a p-side
electrode 16 is formed on the second semiconductor layer 13 exposed to
the opening of the insulating film 14.

[0039] Next, an insulating layer 17 covering the n-side electrode 15, the
p-side electrode 16, and the insulating film 14 is formed. Then, as shown
in FIG. 3B, an opening reaching the n-side electrode 15 and an opening
reaching the p-side electrode 16 are formed in the insulating layer 17.

[0040] Next, a seed metal is formed on the second surface 17b and the
inner wall of the opening of the insulating layer 17, and a plating
resist, not shown, is further formed. Then, electrolytic plating is
performed using the seed metal as a current path.

[0041] Thus, as shown in FIG. 3c, an n-side interconnect 18 connected to
the n-side electrode 15 and a p-side interconnect 19 connected to the
p-side electrode 16 are formed in the openings of the insulating layer 17
and on the insulating layer 17 therearound.

[0042] Next, the plating resist used in the plating for forming the n-side
interconnect 18 and the p-side interconnect 19 is removed. Then, another
plating resist for forming metal pillars is formed, and electrolytic
plating is performed using the aforementioned seed metal as a current
path. Thus, as shown in FIG. 3c, an n-side metal pillar 21 is formed on
the n-side interconnect 18, and a p-side metal pillar 22 is formed on the
p-side interconnect 19.

[0043] Subsequently, the plating resist is removed, and furthermore the
exposed portion of the seed metal is removed. This breaks the electrical
connection between the n-side interconnect 18 and the p-side interconnect
19 through the seed metal.

[0044] Next, as shown in FIG. 4A, the n-side interconnect 18, the p-side
interconnect 19, the n-side metal pillar 21, the p-side metal pillar 22,
and the insulating layer 17 are covered with a resin 23. Subsequently,
the surface of the resin 23 is ground to expose the upper surface of the
n-side metal pillar 21 and the p-side metal pillar 22. Then, external
terminals 24 such as solder balls and metal bumps are provided on the
exposed surface

[0045] Next, as shown in FIG. 4B, the substrate 11 is removed. Here, FIG.
4B is depicted with the positional relationship turned upside down with
respect to FIG. 4A.

[0046] The substrate 11 is removed from the first semiconductor layer 12
illustratively by laser lift-off. More specifically, laser light is
applied toward the first semiconductor layer 12 from the rear surface
side of the substrate 11, which is opposite to its major surface on which
the first semiconductor layer 12 is formed. The laser light has a
wavelength to which the substrate 11 is transmissive and which falls in
an absorption region of the first semiconductor layer 12.

[0047] When the laser light reaches the interface between the substrate 11
and the first semiconductor layer 12, the first semiconductor layer 12
near the interface is decomposed by absorbing the energy of the laser
light. For instance, in the case where the first semiconductor layer 12
is made of GaN, it is decomposed into Ga and nitrogen gas. Ga is left on
the first semiconductor layer 12 side. This decomposition reaction forms
a small gap between the substrate 11 and the first semiconductor layer
12, thereby separating the substrate 11 from the first semiconductor
layer 12. Irradiation with the laser light is performed in a plurality of
times on predefined regions across the wafer to strip the substrate 11.

[0048] After the substrate 11 is removed, a groove 30 is formed in the
first semiconductor layer 12 as shown in FIG. 5A. The groove 30 reaches
the first surface 17a of the insulating layer 17 through the first
semiconductor layer 12 and the insulating film 14. The groove 30 can
illustratively be formed by RIE (reactive ion etching) using a mask. In
this case, the cross section of the groove 30 tends to be shaped like an
inverted truncated cone, and hence the side surface 12a exposed into the
groove 30 is formed as a sloped surface. As shown in FIG. 8A, the groove
30 is illustratively formed like a lattice on the wafer.

[0049] Alternatively, the groove 30 may be formed using laser processing,
a diamond blade and the like. Depending on the method and condition for
forming the groove 30, the side surface 12a, which is the inner wall
surface of the groove 30, may not be a sloped surface, but a surface
generally perpendicular to the top surface 10.

[0050] Next, as shown in FIG. 5B, a phosphor layer 40 is formed on the
first semiconductor layer 12 and the inner wall of the groove 30. The
phosphor layer 40 continuously and integrally covers the top surface 10
and the side surface 12a.

[0051] For instance, the phosphor layer 40 is formed by applying a liquid
resin mixed with phosphor particles by spin-coating, and then heat-curing
it. This method has a good controllability with which the thickness of
the phosphor layer 40 is kept generally uniform between the portion
covering the top surface 10 and the portion covering the side surface
12a.

[0052] Because the phosphor layer 40 is formed after the substrate 11 is
removed from above the top surface 10, the substrate 11 does not exist
between the top surface 10 and the phosphor layer 40, which serves to
increase the light extraction efficiency.

[0053] Subsequently, by dicing at the position of the groove 30, a
singulated semiconductor light-emitting device is obtained as shown in
FIG. 1A. The means for dicing can illustratively be machine cutting using
a diamond blade or the like, laser irradiation, or high-pressure water.
Here, because the substrate 11 and the semiconductor layers 12, 13 do not
exist at the dicing position, or the groove 30, dicing can be easily
performed, and the productivity can be improved.

[0054] The aforementioned steps up to dicing are each performed
collectively in the wafer state, which enables production at low cost.
Furthermore, the package structure including the interconnect layer, the
resin 23, and the metal pillars 21, 22 is formed in the wafer level. This
facilitates downsizing in which the overall planar size of the
semiconductor light-emitting device is close to the planar size of the
bare chip (first semiconductor layer 12 and second semiconductor layer
13).

[0055] The dicing position is not limited to the position of the groove
30. FIG. 6A shows a semiconductor light-emitting device according to
another embodiment which is singulated by dicing at a position outside
the groove 30. FIG. 6B shows a planar layout of its major components.
FIG. 8B shows a planar layout of the major components in the wafer state
before dicing.

[0056] The first semiconductor layer 12 is divided by the groove 30 into a
light-emitting section and a non-light-emitting section 12b. The
light-emitting section includes the multilayer structure (protrusion)
with the second semiconductor layer 13, and the portions where the
electrodes 15, 16 are formed. The non-light-emitting section 12b does not
include the light-emitting layer, and is not connected to the electrodes
15, 16, thus not emitting light.

[0057] The groove 30 continuously surrounds the periphery of the side
surface 12a of the light-emitting section of the first semiconductor
layer 12, and the non-light-emitting section 12b surrounds the groove 30.
Also in this embodiment, the phosphor layer 40 is formed on the top
surface 10 and in the groove 30 in the wafer state, and subsequently the
device is diced at the position of the non-light-emitting section 12b of
the first semiconductor layer 12. In FIG. 8B, the dicing line DL is shown
by dashed lines.

[0058] According to this embodiment, at the time of dicing, it is possible
to reliably avoid damage to the side surface 12a of the light-emitting
section of the first semiconductor layer 12 and the phosphor layer 40
covering the side surface 12a.

[0059] It is noted that dicing at the position of the groove 30 can reduce
ineffective area making no contribution to light emission and can
decrease the planar size of the singulated device.

[0060] On the other hand, the substrate 11 may not be completely removed,
but ground thinly and left on the top surface 10 as shown in FIG. 7. By
thinning and leaving the substrate 11, it is possible to achieve higher
mechanical strength, and hence a more reliable structure, than the
structure in which the substrate 11 is completely removed. Furthermore,
the remaining substrate 11 can prevent warpage after singulation, which
facilitates mounting on a circuit board and the like.

[0061] The embodiments of the invention have been described with reference
to examples. However, the invention is not limited thereto, but can be
variously modified within the spirit of the invention. The material,
size, shape, layout and the like of the substrate, semiconductor layer,
electrode, interconnect layer, metal pillar, insulating film, insulating
layer, and resin can be variously modified by those skilled in the art,
and such modifications are also encompassed within the scope of the
invention as long as they do not depart from the spirit of the invention.