modify this code to accomodate the following:

1. use led 9 to display pulse(200ms)
2.Implement a 16-bit BCD decoder using shit-add 3 alorithm to display the input operands A&B, and the output of the operations
3. use hex 4 to hex0 to display the decimal equivalent of the 8-bit input operands and the 16-bit outputs
4. use sliding switcher 7 to 0 to represent the 8-bit opperands
5.use sliding switches 9 to 8
6 implement the following sequences based on the input states:

00 input 8bit operand A
01 input 8bit operand B
10 display C= A+B
11 display D= C<<4-b

Code:
module exam(
    input clk,
    input [7:0] switches,
    input [9:8] state_switches,
    output reg [6:0] hex0, hex1, hex2, hex3, hex4, hex5,
    output led9
);

    
    wire [7:0] operand_A, operand_B;
    wire [15:0] result;
    wire [6:0] hexA0, hexA1, hexA2, hexA3;
    wire [6:0] hexB0, hexB1, hexB2, hexB3;
    wire [6:0] hexC0, hexC1, hexC2, hexC3;
    wire [6:0] hexD0, hexD1, hexD2, hexD3;
	 wire [6:0] hexE0, hexE1, hexE2, hexE3;
    reg [7:0] A, B;
    reg [15:0] C, D;
    wire [1:0] state;
    reg clk_out;
    
    assign operand_A = switches;
    assign operand_B = switches;
    assign state = state_switches;

    
    reg [31:0] counter;
    initial counter = 0;
    always @(posedge clk) begin
        counter <= counter + 1;
        if (counter == 32'd10000000) begin
            clk_out <= 1;
            
        end else if (counter == 32'd20000000) begin
            clk_out <= 0;
				counter <= 0;
        end
    end
    
    assign led9 = clk_out;

    
    reg [8:0] add_result;
    always @(posedge clk_out) begin
        case(state)
            2'b00: begin // State 00: Display A
                A <= operand_A;
                C <= 0;
                D <= 0;
            end
            2'b01: begin // State 01: Display B
                B <= operand_B;
                C <= 0;
                D <= 0;
            end
            2'b10: begin // State 10: A + B
                add_result = A + B;
                C <= add_result[7:0];
                D <= 0;
            end
            2'b11: begin // State 11: (A + B) << A + B
                add_result = A + B;
                D <= (add_result << A) + B;
                C <= 0;
            end
        endcase
    end
    
    // BCD Decoder Instances for A, B, C, and D
    bcd_decoder bcd_A(.binary(A), .hex0(hexA0), .hex1(hexA1), .hex2(hexA2), .hex3(hexA3));
    bcd_decoder bcd_B(.binary(B), .hex0(hexB0), .hex1(hexB1), .hex2(hexB2), .hex3(hexB3));
    bcd_decoder bcd_C(.binary(C), .hex0(hexC0), .hex1(hexC1), .hex2(hexC2), .hex3(hexC3));
    bcd_decoder bcd_D(.binary(D), .hex0(hexD0), .hex1(hexD1), .hex2(hexD2), .hex3(hexD3));
	 

    // Output Multiplexing based on State
    always @(*) begin
        case(state)
            2'b00: begin
                hex0 = hexA0;
                hex1 = hexA1;
                hex2 = hexA2;
                hex3 = hexA3;
                hex4 = 7'b1111111; // Blank
                hex5 = 7'b1111111; // Blank
            end
            2'b01: begin
                hex0 = hexB0;
                hex1 = hexB1;
                hex2 = hexB2;
                hex3 = hexB3;
                hex4 = 7'b1111111; // Blank
                hex5 = 7'b1111111; // Blank
            end
            2'b10: begin
                hex0 = hexC0;
                hex1 = hexC1;
                hex2 = hexC2;
                hex3 = hexC3;
                hex4 = 7'b1111111; // Blank
                hex5 = 7'b1111111; // Blank
            end
            2'b11: begin
                hex0 = hexD0;
                hex1 = hexD1;
                hex2 = hexD2;
                hex3 = hexD3;
                hex4 = 7'b1111111; // Blank
                hex5 = 7'b1111111; // Blank
            end
        endcase
    end

endmodule

module bcd_decoder(binary, hex0, hex1, hex2, hex3);
    input [15:0] binary;
    output [6:0] hex0, hex1, hex2, hex3;
    reg [3:0] thousands, hundreds, tens, ones;
    integer i;

    always @(binary) begin
        thousands = 4'd0;
        hundreds = 4'd0;
        tens = 4'd0;
        ones = 4'd0;
        
        for (i = 15; i >= 0; i = i - 1) begin
            if (thousands >= 5)
                thousands = thousands + 3;
            if (hundreds >= 5)
                hundreds = hundreds + 3;
            if (tens >= 5)
                tens = tens + 3;
            if (ones >= 5)
                ones = ones + 3;

            thousands = thousands << 1;
            thousands[0] = hundreds[3];
            hundreds = hundreds << 1;
            hundreds[0] = tens[3];
            tens = tens << 1;
            tens[0] = ones[3];
            ones = ones << 1;
            ones[0] = binary[i];
        end
    end

    binary_to_segment u0(ones, hex0);
    binary_to_segment u1(tens, hex1);
    binary_to_segment u2(hundreds, hex2);
    binary_to_segment u3(thousands, hex3);
endmodule

module binary_to_segment(binary, seg);
    input [3:0] binary;
    output reg [6:0] seg;

    always @(binary) begin
        case (binary)
            4'b0000: seg = 7'b1000000; // 0
            4'b0001: seg = 7'b1111001; // 1
            4'b0010: seg = 7'b0100100; // 2
            4'b0011: seg = 7'b0110000; // 3
            4'b0100: seg = 7'b0011001; // 4
            4'b0101: seg = 7'b0010010; // 5
            4'b0110: seg = 7'b0000010; // 6
            4'b0111: seg = 7'b1111000; // 7
            4'b1000: seg = 7'b0000000; // 8
            4'b1001: seg = 7'b0010000; // 9
            default: seg = 7'b1111111; // Blank
        endcase
    end
endmodule