Massively improve disassembler logic 
instruction.rs:
use std::fmt;

// Define the registers
#[derive(Debug, Clone, Copy)]
pub enum Register {
    R0,
    R1,
    R2,
    R3,
    R4,
    R5,
    R6,
    R7,
    Unknown(u8),
}

impl fmt::Display for Register {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Register::R0 => write!(f, "R0"),
            Register::R1 => write!(f, "R1"),
            Register::R2 => write!(f, "R2"),
            Register::R3 => write!(f, "R3"),
            Register::R4 => write!(f, "R4"),
            Register::R5 => write!(f, "R5"),
            Register::R6 => write!(f, "R6"),
            Register::R7 => write!(f, "R7"),
            Register::Unknown(code) => write!(f, "R{}", code),
        }
    }
}

// Define operand types
#[derive(Debug, Clone)]
pub enum Operand {
    Register(Register),
    Immediate(u16),
    Address(u16),
}

impl fmt::Display for Operand {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Operand::Register(reg) => write!(f, "{}", reg),
            Operand::Immediate(val) => write!(f, "0x{:04X}", val),
            Operand::Address(addr) => write!(f, "0x{:04X}", addr),
        }
    }
}

// Define the instruction set
#[derive(Debug)]
pub enum Instruction {
    /// Format: LOAD Register, Immediate
    Load { register: Register, value: u16 },
    /// Format: ADD Register, Register
    Add { dest: Register, src: Register },
    /// Format: SUB Register, Register
    Sub { dest: Register, src: Register },
    /// Format: JMP Address
    Jmp { address: u16 },
    /// Format: CMP Register, Register
    Cmp { reg1: Register, reg2: Register },
    /// Format: JE Address
    Je { address: u16 },
    /// Format: JNE Address
    Jne { address: u16 },
    /// Format: PUSH Register
    Push { register: Register },
    /// Format: POP Register
    Pop { register: Register },
    /// Format: NOP
    Nop,
    /// Format: HALT
    Halt,
    /// Unknown or invalid instruction
    Unknown { opcode: u8, bytes: Vec<u8> },
}

impl fmt::Display for Instruction {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Instruction::Load { register, value } => {
                write!(f, "LOAD {}, {}", register, value)
            }
            Instruction::Add { dest, src } => {
                write!(f, "ADD {}, {}", dest, src)
            }
            Instruction::Sub { dest, src } => {
                write!(f, "SUB {}, {}", dest, src)
            }
            Instruction::Jmp { address } => {
                write!(f, "JMP {}", address)
            }
            Instruction::Cmp { reg1, reg2 } => {
                write!(f, "CMP {}, {}", reg1, reg2)
            }
            Instruction::Je { address } => {
                write!(f, "JE {}", address)
            }
            Instruction::Jne { address } => {
                write!(f, "JNE {}", address)
            }
            Instruction::Push { register } => {
                write!(f, "PUSH {}", register)
            }
            Instruction::Pop { register } => {
                write!(f, "POP {}", register)
            }
            Instruction::Nop => {
                write!(f, "NOP")
            }
            Instruction::Halt => {
                write!(f, "HALT")
            }
            Instruction::Unknown { opcode, bytes } => {
                write!(f, "UNKNOWN OPCODE 0x{:02X} {:?}", opcode, bytes)
            }
        }
    }
}

disassembler.rs:
use crate::instruction::{Instruction, Register};
use std::fmt;

// Define opcodes
const OPCODE_LOAD: u8 = 0x01;
const OPCODE_ADD: u8 = 0x02;
const OPCODE_SUB: u8 = 0x03;
const OPCODE_JMP: u8 = 0x04;
const OPCODE_CMP: u8 = 0x05;
const OPCODE_JE: u8 = 0x06;
const OPCODE_JNE: u8 = 0x07;
const OPCODE_PUSH: u8 = 0x08;
const OPCODE_POP: u8 = 0x09;
const OPCODE_NOP: u8 = 0x0A;
const OPCODE_HALT: u8 = 0x0B;

/// Represents a parsed instruction along with its address.
#[derive(Debug)]
pub struct ParsedInstruction {
    pub address: usize,
    pub instruction: Instruction,
}

/// Disassembles binary data into a vector of parsed instructions.
///
/// # Arguments
///
/// * `data` - A slice of bytes representing the binary code.
///
/// # Returns
///
/// * A vector of `ParsedInstruction` structs.
pub fn disassemble(data: &[u8]) -> Vec<ParsedInstruction> {
    let mut instructions = Vec::new();
    let mut pc = 0;

    while pc < data.len() {
        let address = pc;
        let opcode = data[pc];
        match opcode {
            OPCODE_LOAD => {
                if pc + 3 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let reg_code = data[pc + 1];
                let reg = decode_register(reg_code);
                let imm = ((data[pc + 2] as u16) << 8) | data[pc + 3] as u16;
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Load {
                        register: reg,
                        value: imm,
                    },
                });
                pc += 4;
            }
            OPCODE_ADD => {
                if pc + 2 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let dest_code = data[pc + 1];
                let src_code = data[pc + 2];
                let dest = decode_register(dest_code);
                let src = decode_register(src_code);
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Add { dest, src },
                });
                pc += 3;
            }
            OPCODE_SUB => {
                if pc + 2 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let dest_code = data[pc + 1];
                let src_code = data[pc + 2];
                let dest = decode_register(dest_code);
                let src = decode_register(src_code);
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Sub { dest, src },
                });
                pc += 3;
            }
            OPCODE_JMP => {
                if pc + 2 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let addr = ((data[pc + 1] as u16) << 8) | data[pc + 2] as u16;
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Jmp { address: addr },
                });
                pc += 3;
            }
            OPCODE_CMP => {
                if pc + 2 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let reg1_code = data[pc + 1];
                let reg2_code = data[pc + 2];
                let reg1 = decode_register(reg1_code);
                let reg2 = decode_register(reg2_code);
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Cmp { reg1, reg2 },
                });
                pc += 3;
            }
            OPCODE_JE => {
                if pc + 2 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let addr = ((data[pc + 1] as u16) << 8) | data[pc + 2] as u16;
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Je { address: addr },
                });
                pc += 3;
            }
            OPCODE_JNE => {
                if pc + 2 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let addr = ((data[pc + 1] as u16) << 8) | data[pc + 2] as u16;
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Jne { address: addr },
                });
                pc += 3;
            }
            OPCODE_PUSH => {
                if pc + 1 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let reg_code = data[pc + 1];
                let reg = decode_register(reg_code);
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Push { register: reg },
                });
                pc += 2;
            }
            OPCODE_POP => {
                if pc + 1 >= data.len() {
                    instructions.push(ParsedInstruction {
                        address,
                        instruction: Instruction::Unknown {
                            opcode,
                            bytes: data[pc..].to_vec(),
                        },
                    });
                    break;
                }
                let reg_code = data[pc + 1];
                let reg = decode_register(reg_code);
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Pop { register: reg },
                });
                pc += 2;
            }
            OPCODE_NOP => {
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Nop,
                });
                pc += 1;
            }
            OPCODE_HALT => {
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Halt,
                });
                pc += 1;
            }
            _ => {
                instructions.push(ParsedInstruction {
                    address,
                    instruction: Instruction::Unknown {
                        opcode,
                        bytes: vec![opcode],
                    },
                });
                pc += 1;
            }
        }
    }

    instructions
}

/// Decodes a register code into a `Register` enum.
///
/// # Arguments
///
/// * `code` - The register code as a `u8`.
///
/// # Returns
///
/// * A `Register` enum variant.
fn decode_register(code: u8) -> Register {
    match code {
        0x00 => Register::R0,
        0x01 => Register::R1,
        0x02 => Register::R2,
        0x03 => Register::R3,
        0x04 => Register::R4,
        0x05 => Register::R5,
        0x06 => Register::R6,
        0x07 => Register::R7,
        unknown => Register::Unknown(unknown),
    }
}