아래 영어를 한글로 번역해주세요.

Hello,
Welcome to this course ‘IC Design Process:

A Beginner's Overview to VLSI Technology’.

This course is presented by ‘Systemverilog
Academy’ . It is is an online platform to

learn Systemverilog hardware description language
for both design and verification coding.

Visit us at ‘systemverilog academy.com’
for in depth Systemverilog trainings in all

levels of expertness, beginner, intermediate
or advanced.

This is a beginner level course.

When anybody start learning a hardware description
language such as Systemverilog or VHDL, the

most common problem they could face is, in
‘connecting’ what they write in their

program to the actual ‘circuit’ that get
produced in the Silicon.

This is a course designed to simplify this
problem by connecting together the pieces

of information scattered throughout RTL design,
functional verification, synthesis, physical

design and manufacturing in VLSI technology.

This is not teaching any specific hardware
description language, or anything related

to coding in an HDL.

Course Overview:

As this course is teaching more theory than
coding practices, it is designed to ba a short

one and gives only the overview of every process.

The first session explains a short history
of ICs.

Second session refreshes few fundamentals
of digital circuits.

Third session describes the idea of Hardware
Description Language.

Fourth session gives the overview of every
steps involved in the design process of an

IC.

It is broadly classified as front-end and
back-end design processes.

Fifth session briefs the IC manufacturing
process and the final session summaries the

course.

History of ICs.

An Integrated Circuit or IC, is a device with
a large number of electronic circuits built

into a tiny plate of semiconductor material,
which will be usually Silicon.

An SOC or System On Chip is an ‘IC’ with
‘all components’ of a complete electronic

system built into a single Silicon plate.

Or simply, an SOC is a device with multiple
ICs built in a single chip.

Even though the actual Silicon in an IC is
a tiny metal peace, they could be built with,

up to several billions of transistors and
other electronic components in it.

As you know, there are two categories of electronic
circuits, analog and digital.

In the same manner, ICs can also be analog
or digital based on the number of operational

voltage levels in them.

Design process of analog and digital ICs are
‘not’ very similar, but the manufacturing

process for both of them are almost similar.

Usually HDLs are used to design digital ICs,
and this course is explaining the process

on the grounds of a digital IC.

Every digital circuit is made of ‘switches’
that ‘turn-on’ and ‘turn-off’ the

voltage.

Before the invention of BJT, the Bipolar Junction
Transistor, circuits were using vacuum tubes

as these digital switches.

You can imagine how bulky was, even a simple
laboratory circuit, that used vacuum tubes

instead of transistors!

With the invention of transistors in 1947
at Bell Laboratories, vacuum tubes were replaced

by these small Silicon devices, but still
the whole circuit was made of discrete transistors.

Eventually, the idea came up, that proposed
to build all transistors and other components

in a whole electronic circuit, into a ‘single’
Silicon piece, instead of manufactingthem

them separately and assembling.

This was nothing but what we call as an ‘Integrated’
Circuit and from there, the IC technology

evolution started and made it possible to
build up to billions of components into a

single wafer.

VLSI:

The first integrated circuits build only a
few devices in them, perhaps as many as ten

diodes, transistors, resistors and capacitors,
making it possible to fabricate, one or two

logic gates on a single IC.

This number started to increase slowly and
gone upto billion in 2008.

Based on the number of transistors made into
a single chip, the manufacturing technologies

were known by different names in the industry
like SSI or LSI.

Early in 1960s, hundreds of transistors were
built into a single chip and technology was

commonly known as SSI or Small Scale Integration.

It went up to thousands of transistors in
late 1960s which was known as Medium Scale

Integration, MSI.

In 70s, it increased to tens of thousands
of transistors and the technology was known

as Large Scale Integration or LSI.

Eventually, the number of transistors in a
single chip increased to hundreds of thousands

of transistors in 1980s, millions in late
90s and to billions in 2008.

Nowadays, irrespective of the number of transistors
in the chip, all IC manufacturing technologies

are called by the same name, VLSI or Very
Large Scale Integration.

Fundamentals of Digital circuits:

Before you start designing digital ICs, there
are few fundamentals of digital circuits that

need to be refreshed.

In digital circuits, all real world entities
, that is the ‘Data’, will be converted

to to binary numbers using mathematical formulas
as a ‘one’ can be represented with a positive

voltage and ‘zero’ with negative voltage.

The only requirement to process this binary
data in the circuit is to, switch-on and switch-off

the voltage in the circuit.

Thus we can say that ‘switches’ are the
basic building blocks of any digital circuit.

Normally, transistor and C-MOS devices are
used as these switches.

There are 2 types of Digital circuits, sequential
and combinational circuits.

A digital circuit whose output depends, not
only on the present value of its inputs, but

on the sequence of past inputs or the input
history, is called as a sequential circuit

.
On the other hand, a circuit whose output

is a pure function of, only its current inputs,
is called as a combinational circuit.

In simple words, a digital circuit with a
memory storage element in it will be a sequential

circuit and without memory will be a combinational
circuit.

One you have written the state of any digital
circuit and simplify it using the mathematical

formulas, there will be only two types of
components in it, which are, the ‘the logic

gates’ and ‘flip-flops’.

As you know, there are only seven logic gates
whose symbolic representation is shown here.

They are the and, or, x-or, not, nand, nor
& x-nor gates.

A Flip-Flop is the memory storage element
which can store a single bit input data in

it, for the duration of a clock signal.

All types of flip-flops, like D flops, JK
flops, latches etc, are again made of logic

gates.

As an example, this figure shows a D flip-flop
made using logic gates.

Thus we can say that, every digital circuit
is made of, only ‘logic gates’.

This breakdown will further go down into transistors,
as all logic gates can be made with only transistors.

Here is a diagram representing a nand gate
& nor gate using C-MOS transistors.

Thus, every digital circuit is made of gates
and flops, flops are made of gates, and all

gates are made using transistor.

This concludes that, every digital circuit
is made of, only with a large number of transistors.

To simply the design process, our aim is to
model the complex digital circuits in an abstract

way, which hides details of its transistor
level circuit diagram.

This is the whole purpose of using a Hardware
Description Language in IC design.

Hardware Description Language:

As you learned in the previous session, in
early 60s itself, the number of transistors

in a digital circuit have gone beyond the
point ,where it was possible to draw as a

transistor level circuit , and make a mask
for the fabrication process.

Thus it became essential to describe the circuit
behaviour in a high level manner, which is

independent of any library or technology that
is used in the manufacturing process of the

IC, and uses EDA tools to convert the written
‘program’ , to a mask diagram used in

the fabrication process.

This programming language is called as a ‘Hardware
Description Language’ or an ‘HDL’.

A few years ago, Verilog and VHDL were the
most common HDLs in the industry and nowadays,

Systemverilog , which is an extension of Verilog,
is the widely accepted language by most of

the semiconductor companies.

Verilog Language:

Verilog was developed by the company, Gateway
Design in 1984 which was later acquired by

Cadence Design Systems.

It gots its name from the words "verification"
and "logic" and became an IEEE standard in

1995 as ‘IEEE 1364’.

The Verilog HDL is now maintained by a non
profitable organization called Accellera.

System Verilog HDL:
Systemverilog is an extension of Verilog and

was developed by Accellera as a new standard.

It become an IEEE standard in 2005 which is
‘IEEE 1800-2005’.

Compare to verilog, Systemverilog added a
lot of features to support ‘functional verification’

of the IC.

Out of these, support for ‘Object Oriented
Programming‘ was a significant add-on which

helped it to become the most prefered HDL
in the industry, as it can be used for both

design as well as verification.

When you write a ‘design code’ in Verilog
and Systemverilog, they look almost the same.

But in case of a ‘test-bench’ or verification
code, Systemverilog is much more advanced

than Verilog.

IC Design & Manufacturing Process:

The process of making of an ICs can be broadly
classified into two, it need to designed first,

and manufactured next.

The design process is subdivided into front-end
and back-end process which consists of specification,

design, verification, synthesis and physical
design.

Each of these design and manufacturing process
contains many sub phases in them which are

explained in the coming sessions.

IC Design Process:

In this session, you will quickly go through
the complete design process of an IC.

The first step is to decide the functionality
of the IC.

Here the specification of the IC is written
and its microarchitecture is defined.

In the next phase, these specifications will
be programmed in a hardware description language

like Systemverilog.

This is called the RTL design phase of the
process and writing Systemverilog code is

often referred as the ‘RTL code’ where
RTL stands for ‘Register Transfer Layer’.

The next phase is functional verification.

Here the design is simulated using extra piece
of Systemverilog code called as the ‘Test-Bench’

or TB Code’.

The TestBench will use a ‘simulation EDA
tool’, to inject stimulus into the inputs

of the design and will check the correctness
of its outputs.

This will expose the issues or bugs in the
design which will be fixed in the RTL code.

These phases are repeated multiple times,
until the RTL code is bug free.

In the function verification phae, apart from
checking the correctness of the RTL, the quality

and completeness of the testing process will
also be ensured by using ‘coverage analysis’

techniques.

The RTL design and functional verification
phases are usually called as the “front

-end” phase of IC design process.

When the functionality of the IC or SOC is
very complex as in the case of a microprocessor,

Mobile CPU or Graphics Processor, it is impossible
completely to do any of the above phases,

which are , the specification definition,
RTL design and functional verification, by

one person or a group of people.

It is accomplished by subdividing the whole
IC into multiple ‘units’.

Here the whole IC or SOC will be split into
multiple clusters and clusters again into

units.

Each of these units will perform well defined
functions in their input-output boundaries.

The microarchitecture of each unit is defined
in the specification phase.

Aslo RTL design & functional verification
are performed in unit level boundaries.

Once the units are stabilized, that is when
are bug free, the functional verification

will be done at cluster level and SOC level
which will ideally expose all bugs in the

RTL those were hidden at unit level verification.

When the function verification is complete
at SOC or IC level, the front- end part of

design process is complete and will be send
for back end process.

IC Design- The back end process:

Once the verified RTL is ready, the HDL code
will be converted to digital circuits with

only logic gates and flip-flops.

This process is called as ‘synthesis’
and it is done by using EDA tools.

The output of synthesis will consist of list
of logic gates connect appropriately to perform

the designed functionality of the IC.

It is usually called as a ‘net-list’ and
it can be assumes as the circuit diagram of

the final IC, with only logic gates in it.

This gate level representation of the circuit
need to be converted to a geometric representation

of shapes which, when manufactured in the
corresponding layers of materials, will ensure

a circuit of transistors doing the intended
functionality.

This process is called as physical design.

In simple words, physical design is the process
of generating a ‘photo mask’, which can

be used in the fabrication process to produce
a transistor level circuit of the whole IC

in the Silicon.

The synthesis and the physical design phases
are commonly known as the ‘back- end’

phase of IC design process.

Physical design process:

There are many details in every phases of
physical design and here it is summarised

in a very abstract manner.

Synthesis is the process of converting the
HDL design code to a gate level representation

of the whole circuit, which is called as a
‘net-list’.

Next phase is floor planning.

Remember from the previous session that in
the front-end design phase, the whole IC will

be divided into subunits or blocks, to make
the process easier.

In the Floor planning phase, you will decide
which blocks or subunit will be made in, which

region of the metal in the final IC.

That is, here the whole area of the actual
silicon metal is assigned to major blocks

or units of the design.

This will also fix the position of input and
output pins of the IC.

Here is a representative floor plan of a design.

These rectangles could be major blocks of
your design or different IPs purchased for

this design.

Next phase is Placement which is a highly
complex and important phase in back end desing.In

simple words, it is the process of assigning
location to the ‘gates’ of the circuit

in the Silicon,while optimising a lot of power
and performance constraints.

It takes many iterative process to complete
this step.

Clock insertion phase.

Here, clock signal wiring is introduced into
the design, which are commonly known as ‘clock

trees’ . Clock signal need to driven to
every part of the circuit with the capability

of ‘gating the clock’ as and when needed.

Clock gating is a process of saving power,
by shutting down a part of the circuit when

it is not active for a small period of time.

The clock tree is a metal grid, which distributes
the clock signals from a common point to all

the elements that need clock, considering
the clock gating.

Till this point of physical design process,
you have decided the position of all blocks

in the IC, and the position of each logic
gate of the circuit in the Silicon as well.

Obviously, the next step is connect these
gates according to the circuit diagram which

is done in the routing phase.

Routing or ‘wire routing’ is the process
of connecting different components ‘placed’

in the circuit appropriately using metal wires.

To understand placing and routing phases in
the process, you can compare them to the same

steps in PCB design.

In the next phase is Design for manufacturability.

Here the design is modified where possible,
to make it as easy and efficient as possible,

to produce.

This is done by adding extra vias or adding
dummy metal, diffusion or poly layers wherever

possible while complying to the design rules
set by the foundry.

Last phase in physical design process is Tapeout
and mask generation.

After doing a lot of iterations in above steps
which at most care, the final the design data

will be ready and it need to be converted
into ‘photomasks’ in this phase.

The final photo mask will be generated and
sent to the manufacturing foundry to produce

the IC on Silicon.

This is called as ‘Tape-out’ as magnetic
tapes were used to write this photomask in

early days.

Nowadays, the final photomask will be delivered
in GDS-two format.

It is a binary file format representing planar
geometric shapes, text labels, and other information

about the layout, in a hierarchical form.

The data can be used to reconstruct all, or
part of the artwork, that to be used in sharing

layouts, or creating photomasks at the foundry.

All the steps in physical design are explained
in a very simplified manner here but remember,

in actual exercises, all of them are too complex,
costly and time consuming.

IC Manufacturing Process:

After physical design phase, which will generate
the photomask in GDS-two format, the next

step in to manufacture the IC in a foundry.

Again, there are a lot of steps involved in
the manufacturing process, from producing

the Silicon wafer from sand, till packing
and testing of final IC.

The most simplified description of IC manufacturing
process are given here.

Here, first you need to build transistors
on Silicon, then connect them according to

the circuit functionality and finally, pack
the IC into its case and test it.

Building a C-MOS not gate in Silicon:

The transistors used in modern ICs are Mos-Fets
(MOSFET).

They are of 2 types, P-MOS and N-MMOS transistors.

Here the first diagram shows how an NMOS and
PMOS transistors are manufactured into a p-type

substrate.

The N-MOS need two n-plus regios in the p-substrate
,and P-MOS need two p-plus regions in an n-well.

The second diagram show the circuit diagram
of a not gate made with a P-MOS and N-MOS

transistors.

The third diagram shows the cross-section
view of a not gate made in a p-type substrate.

If you compare the first and third diagram,
it shows the drain & source of both transistors

are connected together, to form a circuit
equivalent to the second diagram.

Note that, the gate, source & drain contacts
are ‘not’ normally in the same plane in

real devices, and this diagram is not to scale
as well.

To manufacture a complex digital circuit in
an IC, The same principle is applied as above.

That is, first the transistors are made into
the Silicon and then they are connected to

form the final circuit.

Thera are a lot of complex steps involved
in building all the transistors in Silicon,

which are not explained here.

You can imagine that,one you completed the
‘build-transistor’ phase, there will be

billions of transistors built itto silicon,
looking something similar to these diagrams.

Next you need to ‘connect’ the transistors
to form the final circuit.

Connecting transistors:

Inorder to connect the billions of transistors
according to the circuit diagram , just one

layer of connection will not be enough.

There will be multiple layer of connecting
wires, sitting on top of one another, seperated

by in insulating material.

Its cross-section view will look something
similar to this diagram.

It shows 5 layers of connection between transistors,
and there could be upto 9 connection layers

in a complex nowadays.

Here S-O-D or Spin-on Dielectrics is a coating
material that insulates between transistors

or between conducting metal wires.

These are the conducting metal connections,
and the other end of this metal will be connected

to some other transistor sitting in the IC.

This 3D diagems is an animation of connection
layers in a small part of IC.

Now you can imagine how comlex will be the
the complete connection diagram in a real

IC.

From these descriptions, it is clear that
you need two type of database to manufacture

and connect transistors.

First, the photo-mask to make billions of
transistors in Silicon, and second, the connection

information between these transistors over
multiple layers..

These two complex requirements are are solved
in the physical design process, and will be

available in the GDS-two formatted database.

Once the transistors and made and connected
to for the final circuit, it will be packed

in an insulating material with connections
made to external pins.

Different kind of testing will be done on
the wafer in between these processes, and

on the final IC at the end of production.

All these manufacturing process will take
from one to two months to complete and finally,

the IC will be packed as product and shipped
to the market.

What you have learned here is quick overview
of the whole IC manufacturing process and

there are a lot of complex procedures in each
and every phases of this process..

Also, there are few good Youtube videos that
shows there phases in a real IC foundries,

which I strongly recommended you to to watch,
even if you are not planning to learn more

about the manufacturing process.

Few of the selected Youtube video links are
given here for reference.

IC Design & Manufacturing Process Summary:

Here ia s quick summary of the complete process.

First the idea or functionality of the final
product is defined as specification.

This is coded in an HDL at different subunit
level.

Then the code will be verified at unit level,
cluster level and finally at SOC or IC level.

These phases are commonly known as ‘Front-End’
design process.

The final HDL code is converted to a gate
level circuit using ‘synthesising tools’

and will produce a GDS-two formatted photomask
that is used to manufacture the IC.

These are commonly called as the ‘Back-End’
design process.

Once the final photmask is ‘taped-out’,
it will be used to manufacture the IC in a

foundry.

After production, each IC will be validated
and finally shipped as a product to the market.

Summary:

Here is the summary of the course.

Every digital circuit is made of a large number
of transistors.

You will use a Hardware Description Language
to code behaviour of the IC and use EDA tools,

to convert this program into its equivalent
transistor circuit.

The coding phase is known as the front-end
design and other one as the back-end design.

Once the transistor circuit is ready, its
photo mask and connection layers will be generated,

and the circuit will be manufactured in Silicon.

In the manufacturing process, first transistors
are build into the IC using photmask and then

they are connected over different connection
layers, to form the final circuit.

This course was offered by ‘Systemverilog
Academy’ and here you reached the end of

the course.

‘Systemverilog Academy’ is an online learning
platform offering different courses in the

HDL.

This is the first ever course we published,
and there a number of others on the way over

the next few months.

These will teach Systemverilog for both design
and functional verification coding.

Apart from the online courses, we have also
designed more personalized practicing techniques

in Systemverilog, which will make you to ‘code-and-learn’
the programming language.

These will also be released soon at ‘systemverilogAcademy.com’
and remember, all of them are prepared by

experts from the industry who have extensive
work experience in SOC design and verification.

Please visit us at ‘SystemVerilogAcademy.com’
and subscribe to us.

We will keep you posted about the release
of new courses & practicing session, also,

you could get great offers and discounts as
well !

Thank you very much for enrolling this course
and we are really happy to see that you have

completed successfully!

We hope this was informative for you and would
really appreciate if you could leave your

honest feedback on this course.

Don’t forget to visit us at ‘SystemverilogAcademy.com’.

Thanks again & Happy learning.