摘要，SCI论文：{H}{igh}-energy and nuclear physics experiments, which are instrumental in examining the minute structure of matter, require the utilization of advanced particle accelerators. The High Intensity Heavy Ion Accelerator Facility (HIAF) in China, slated for completion in 2025, will provide critical support for these cutting-edge inquiries${^{[]}}$. As a national research facility, HIAF is dedicated to nuclear physics, atomic physics, heavy ion applications, and interdisciplinary research, establishing it as an indispensable research platform in the fields of high-energy and nuclear physics${^{[]}}$. In future operations, the HIAF is anticipated to fulfil experimental requirements involving up to 1 × 10${^{11}}$ ions per pulse and will accommodate multiple experimental terminals for an extensive array of particle and nuclear physics investigations${^{[]}}$. Given such significant beam densities and the diversity of experimental requirements, the implementation of an easily integrable, scalable, high-bandwidth, generic Data AcQuisition (DAQ) system is of pivotal importance.The deployment of sophisticated high-performance DAQ systems in significant international physics experiments like Mu3e, DUNE, and CMS. The Mu3e experiment employs multiple PCIe40 and DE5aNET boards, facilitating the high-bandwidth data processing essential for investigating rare muon decays${^{[]}}$. For the DUNE experiment, the DAQ framework utilizes the FELIX card${^{[]}}$, aligning with its needs for both scalability and robust data throughput. Likewise, for its phase 2 upgrade, the CMS experiment utilizes the DTH-400 to meet the demands of the CMS detectors for advanced data processing and enhanced transmission efficiency${^{[]}}$, ensuring efficient management, control of data collection, and synchronization.

The DAQ system developed for HIAF is inspired by the design philosophies of the aforementioned large-scale physics experimental DAQ systems, aiming to meet the varied experimental requirements at HIAF. Anchored by the new generation of the Common Data Acquisition Unit (new CDAU) board shown in Fig. 1, this system is capable of supporting data transmission bandwidths of up to 40 Gbps, and is characterized by its exceptional scalability and ease of integration. Embracing a standardized design methodology, the system substantially streamlines the development process, reduces design costs, and eases the maintenance of DAQ systems for experimental terminals conducted at HIAF.

\section{DAQ System Architecture}
The generic DAQ system, developed for the HIAF experiments, finalizes its system design based on the new CDAU board, as depicted in Fig. 2. The system, primarily consisting of the new CDAU board and a computer with the DAQ software, exhibits excellent compatibility and expandability. The connection between the new CDAU board and the computer is facilitated through a PCI Express (PCIe) slot, enabling efficient data transfer. Moreover, the DAQ software is responsible for performing tasks such as data reading, processing, and issuing configuration commands. 

\subsection{New CDAU}
Enhancements and optimizations have been implemented on the new CDAU, including advanced power management and the addition of the new LEMO connectors for convenient trigger inputs or outputs, in Fig. 1. Mirroring its predecessor, the new CDAU utilizes the Xilinx Kintex series FPGA as its central processing unit ${^{[]}}$. The new iteration of CDAU is engineered to interface directly with peripherals through the FPGA Mezzanine Card (FMC) and General-Purpose Input/Output (GPIO) ports, facilitating significant functional expansion. This includes the ability to connect with high-speed Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), and other expansion modules for direct data acquisition and control. During experiments, new CDAU can connect to up to eight front-end readout electronics, achieving a data transfer bandwidth of up to 80 Gbps. Upon entry via the optical fiber port, the data is temporarily stored in DDR3 Synchronous Dynamic Random-Access Memory (SDRAM). For experiments characterized by high instance rates, the  memory of the system capacity can be expanded to a dual-channel configuration using the onboard Small Outline Dual In-line Memory Module (SODIMM) slot. Upon software request, data cached within the system undergoes transmission to the computer through the PCIe 2.0 ×8 interface. Notably, the ability of the system to receive external trigger signals via the LEMO port plays a crucial role in minimizing the bandwidth consumed by uninteresting data, thereby significantly enhancing the efficiency of the system’s data transmission process.

\subsection{FPGA Logic Design}
As shown in Fig. 3, the logic structure of the FPGA is divided into three main sections: the Service Support Unit (SSU), the Data Unit (DU) and the PCIe Controller, by the design. The SSU is capable of delivering the necessary clock and reset signals each module requires, parsing and dispatching instructions from the host, and also encompasses capabilities for managing peripheral serial devices and gathering the operational statuses of all modules. Within the DU, data received via the GTX transceiver or the extension drivers is initially directed to the Trigger Selection module, where it is filtered based on an external trigger signal and simultaneously pre-packaged with the timestamp and the packet sequence number. Subsequently, the data is cached into off-chip DDR3 SDRAM by the Memory Controller; thereafter, it is extracted from the corresponding channel and repackaged by the Channel Selector module, in response to the directives of the DAQ software, with appended details such as the timestamp, channel number, and packet sequence number. Ultimately, the data is transmitted to the PCIe Controller, where, after a bus conversion (from the user bus to the AXI-Stream (AXI-S) bus), it is sent to the computer by the transceiver (TX/RX) engine.


As illustrated in Fig. 4, the PCIe Controller, developed with the Xilinx Integrated Block for PCIe Intellectual Property (IP) core, features an efficient application layer that includes a Transmission (TX) Engine, a Receive (RX) Engine, a Memory Manager, a Channel Controller, and a User Parser module, among others. The PCIe Controller has implemented four Direct Memory Access (DMA) bi-directional transmission channels to enhance data exchange capabilities. In the DMA write process, DMA operation commands are transmitted from the computer to the RX Engine utilizing Transaction Layer Packets (TLPs) via Programmed Input/Output (PIO). Subsequently, the RX Engine decodes these TLPs and forwards the interpreted instructions to the Memory Manager via the write request (WR REQ) bus. The Memory Manager, in turn, converts these instructions into DMA write commands (DMA\_WR\_CMD), dispatching them to the channel controller. To improve transmission efficiency, a Channel Sequencing Finite State Machine (CS\_FSM) aligns data and commands from all four channels based on the priority of the 4-channel data and then transmits this organized data set to the TX Engine. Following a specified instruction format, the TX Engine assembles the data and writes it to the memory of the computer. Contrasting with the DMA write process, the DMA read process sends the received DMA read commands (DMA\_RD\_CMD) to the computer by the TX engine. In the RX Engine, data is extracted by decoding the TLPs classified as Completion with Data (CplD) sent by the computer, and then forwarded to the subsequent module. Additionally, user commands are translated by the User Parser within the PCIe controller and sent to the SSU.

\subsection{DAQ Software Design}
The software for data acquisition integrated into the system adopts a design based on multithreading, incorporating three separate threads: Device Manager, PCIe Control (PCIe Ctrl), and Data Processing, as shown in Fig. 5. Firstly, the software employs the Device Manager thread to establish a connection with the PCIe endpoint (EP) device; subsequently, the PCIe Ctrl thread proceeds to configure the functionality of the EP device, primarily by employing PIO to relay target data to the Base Address Register (BAR), which in determines the number of DMA channels to be activated. In the course of the data acquisition phase, the DMA channel facilitates the conveyance of data from the endpoint device into the allocated memory space of the computer. Following this operation, the PCIe Ctrl thread proceeds to extract this data, permitting it to be archived directly or undergo real-time processing, contingent upon the selection of user. To guarantee compatibility with the intricate hardware and software architecture of the data acquisition system, the PCIe driver utilized by the software has undergone customization from its original version provided by Xilinx.

\section{Laboratory evaluation of the DAQ system}
In the laboratory, the high-performance data acquisition system was characterized to evaluate the performance of each transmission interface. In the evaluation of high-speed optical transmission interfaces, phenomena such as attenuation in optical fibers and the presence of external interferences have the potential to modify the signal integrity throughout the transmission process [89], which could consequently precipitate inaccuracies in the transmission of data. In the testing, the utilization of Integrated Bit Error Ratio Tester (IBERT) IP core [91], which is embedded within FPGA logic and comprises a pattern generator along with a pattern detector, facilitated the reception and analysis of data emitted by the generator to assess the occurrence of Bit Error Rate (BER). During the testing process, the speed of the optical link was set to 10 Gbps, and eight data loop paths were established between four SFP+ optical modules and one QSFP+ optical module, with the test running continuously for 48 hours and results recorded every hour. As depicted in Fig. 6, the transmission rate for each link consistently remained at 10 Gbps, exhibiting a remarkably low BER measured at 4 × 10${^{-16}}$.
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In this study, the PCIe interface serves as the sole conduit for data exchange between the new CDAU and the computer, playing a pivotal role in overall DAQ system performance. Consequently, Hence, an evaluation of the read and write transfer rates of the PCIe interface was conducted. The FPGA functioned as the initiator for both reading and writing tasks, with the instantaneous data transfer rate determined by performing read and write operations to the computer’s memory through DMA mode. This evaluation was performed continuously over a 48-hour period, with data recorded hourly, and the results are depicted in the Fig. 7. The results indicate stable write rates of 3420 MB/s and read rates of 3400 MB/s. After accounting for the coding and protocol overhead associated with the PCIe link, the effective rates approximated the theoretical throughput achievable with a PCIe 2.0 x8 link.

\section{Test with detector}
To further assess the performance of the DAQ system, an integrated test was carried out that included both the front-end (FE) detector and the DAQ system. The system setup, as shown in Fig. 8, main comprises a detector, FE electronics, and the DAQ system. The detector captures radiation signals and converts them into electrical signals. The FE electronics, which includes a preamplifier and a high-speed Analog-to-Digital Convert (ADC) module, is tasked with extracting, amplifying, and digitizing these signals. Subsequently, the new CDAU facilitates the transmission of the digitized data to the computer for further processing and analysis. In this test, the FE electronics is connected to the DAQ system through the FMC connector. To verify the integrity of all transmission paths, the new CDAU receives data from the FE electronics, routes it through a loopback via the optical transmission interface, then caches it in the DDR3, and ultimately forwards it to the computer.

Linear characterization was first performed on the ADC module of the FE electronics, employing a signal generator to produce 1 MHz exponential pulse signals with test signal amplitudes varying from -1.2 V to 1.2 V in increments of 0.1 V. The analysis of the recorded data revealed a linear correlation between the inputs and outputs. Using (1), the nonlinearity corresponding to each input value was calculated. The test results are presented in Fig. 9. Fig. 9(a) illustrates the linear function between the inputs and outputs, along with the noise level for each output point, reaching up to 1.5 mV. Fig. 9(b) displays the nonlinearity associated with each input value, with a maximum nonlinearity of 7.8 mV.


Subsequently, two detectors were employed to measure the ${^{137}}$Cs radiation source: cesium iodide (CsI) (with an avalanche photodiode (APD)) and lanthanum bromide (LaBr${_{3}}$) (with a photomultiplier tube (PMT)). Fig.10 displays the energy spectrum of ${^{137}}$Cs as measured by the CsI detector, highlighting the characteristic energy peak at 0.662 MeV with an energy resolution of 1.12 \%. Similarly, Fig. 11 displays the energy spectrum obtained by the LaBr${_{3}}$ detector, showing an energy resolution of 21.34 \%. Finally, cosmic rays were detected using a plastic scintillator (with a PMT), with the cosmic ray energy spectrum conforming to the Landau distribution, as depicted in Fig. 12. All these tests confirm that the data acquisition system is capable of stably acquiring experimental data.