Below is a verilog program. There is a secret message that can be extracted with the testbenches. How can I trigger it?

module bloke2 #(
        parameter W=32,
        parameter R0=1,
        parameter R1=1,
        parameter R2=1,
        parameter R3=1,
        parameter ROUNDS=10,
        parameter IV=256'b0
) (
        input        clk,
        input        rst,

        input        start,
        input        finish,

        input  [(W*8)-1:0] key_in,
        input  [(W*8)-1:0] iv_in,

        input  [7:0] din,
        input        din_valid,
        output       din_ready,
        input        din_end,

        output [7:0] dout,
        output       dout_valid,
        output       dout_end
);

        localparam STATE_INIT=0;
        localparam STATE_DATA=1;
        localparam STATE_FINISH=2;
        localparam STATE_TEST=3;

        integer state;

        wire [(W*8)-1:0]  h_out;
        wire [(W*16)-1:0] m;
        wire [(W*2)-1:0]  t;
        wire              f;
        wire              msg_strobe;

        wire f_dv;

        f_unit #(
                .W(W),
                .R0(R0),
                .R1(R1),
                .R2(R2),
                .R3(R3),
                .ROUNDS(ROUNDS),
                .IV(IV)
        ) fu (
                .clk(clk),
                .rst(rst),

                .dv_in(msg_strobe),
                .drdy_out(),

                .dv_out(f_dv),

                .m_in(m),
                .t_in(t),
                .f_in(f),

                .h_out(h_out)
        );

        data_mgr #(
                .W(W)
        ) dmgr (
                .clk(clk),
                .rst(rst),

                .start(start),
                .finish(finish),

                .data_in(din),
                .dv_in(din_valid),
                .drdy_out(din_ready),

                .msg_strobe(msg_strobe),
                .m_out(m),
                .t_out(t),
                .f_out(f),

                .h_in(h_out),
                .h_rdy(f_dv),

                .data_out(dout),
                .dv_out(dout_valid),
                .data_end(dout_end)
        );

        always @(posedge clk) begin
                if (rst)
                        state <= STATE_INIT;
                else begin
                        // Defaults
                        case ({start, finish})
                                2'b00:
                                        state <= STATE_DATA;
                                2'b01:
                                        state <= STATE_FINISH;
                                2'b10:
                                        state <= STATE_INIT;
                                2'b11:
                                        state <= STATE_INIT;
                        endcase

                        case(state)
                                STATE_FINISH:
                                        if (start) begin
                                                state <= STATE_INIT;
                                                if (finish)
                                                        state <= STATE_TEST;
                                        end
                        endcase
                end
        end

endmodule
module bloke2b (
        input        clk,
        input        rst,

        input        start,
        input        finish,

        input  [7:0] din,
        input        din_valid,
        output       din_ready,
        input        din_end,

        output [7:0] dout,
        output       dout_valid,
        output       dout_end
);

        bloke2 #(
                .W(64),
                .R0(32),
                .R1(24),
                .R2(16),
                .R3(63),
                .ROUNDS(12),
                .IV(512'h6A09E667F3BCC908BB67AE8584CAA73B3C6EF372FE94F82BA54FF53A5F1D36F1510E527FADE682D19B05688C2B3E6C1F1F83D9ABFB41BD6B5BE0CD19137E2179)
        ) b2b (
                .clk(clk),
                .rst(rst),

                .start(start),
                .finish(finish),

                .din(din),
                .din_valid(din_valid),
                .din_ready(din_ready),
                .din_end(din_end),

                .dout(dout),
                .dout_valid(dout_valid),
                .dout_end(dout_end)
        );

endmodule

`timescale 1ns/1ps

module bloke2b_tb;

        reg clk = 1'b0;
        reg rst = 1'b1;

        reg start, finish;

        reg [7:0] din;
        reg       din_valid;
        wire      din_ready;
        reg       din_end;

        wire [7:0] dout;
        wire       dout_valid;
        wire       dout_end;

        // Assert when done to finish the simulation.
        reg done = 1'b0;

        // Clock driver.
        localparam CLK_PD = 10;
        always @clk #(CLK_PD/2) clk <= ~clk & ~done;

        bloke2b uut (
                .clk(clk),
                .rst(rst),

                .start(start),
                .finish(finish),

                .din(din),
                .din_valid(din_valid),
                .din_ready(din_ready),
                .din_end(din_end),

                .dout(dout),
                .dout_valid(dout_valid),
                .dout_end(dout_end)
        );

        // Monitor for the message received from the UUT.
        reg [511:0] message;
        always @(posedge clk) begin
                // Very noisy diagnostic, but useful
                //$display("%t tb dv %b de %b m %h", $time, dout_valid, dout_end, message);

                // If we're starting, clear the message contents.
                if (start) message = "";

                // If we have valid data out, shift it in.
                if (dout_valid) message = {message[503:0], dout};

                // If the data finished, display what we received.  It's a hash, so it's
                // probably garbage, but you never know...
                if (dout_end) $display("Received message: %s", message);
        end

        // Run a string through the hash machine.
        task hash_message (
                input [1023:0] msg
        );
                integer i, len;
        begin
                // Ugh, working around a bug in old Icarus Verilog 10.x which
                // prevents the use of proper strings here.  Get the string
                // length because the string literal comes in backwards.
                for (i = 0; msg[8*i +: 8] != 0; i++); len = i;

                // Set our start and finish lines correctly.
                start <= 1'b1;
                finish <= 1'b0;
                @(posedge clk);
                start <= 1'b0;
                finish <= 1'b0;

                // Wait until it signals readiness.
                while (!din_ready) @(posedge clk);

                // Write it in byte by byte when drdy is asserted.
                for (i = len - 1; i >= 0; i--) begin
                        din <= msg[8*i +: 8];
                        din_valid <= 1'b1;
                        do @(posedge clk); while (!din_ready);
                end

                // Deassert data valid, since we're done.
                din_valid <= 1'b0;

                // And assert finish for a clock.
                finish <= 1'b1;
                @(posedge clk);
                finish <= 1'b0;

                // Wait until the message processes.
                @(negedge dout_end);
        end endtask

        initial begin
                // Initialize our start and finish lines.
                start <= 1'b0;
                finish <= 1'b0;

                // Kick off the clock, since it needs an event to start.
                clk <= 1'b1;

                // Wait for the next clock edge and pull the reset.
                @(posedge clk);
                rst <= 1'b0;

                // Run a few tests.
                hash_message("");
                hash_message("123");
                hash_message("abc");

                // And we're done, stop the clock.
                done <= 1'b1;
        end
endmodule
module bloke2s (
        input        clk,
        input        rst,

        input        start,
        input        finish,

        input  [7:0] din,
        input        din_valid,
        output       din_ready,
        input        din_end,

        output [7:0] dout,
        output       dout_valid,
        output       dout_end
);

        bloke2 #(
                .W(32),
                .R0(16),
                .R1(12),
                .R2(8),
                .R3(7),
                .ROUNDS(10),
                .IV(256'h6a09e667bb67ae853c6ef372a54ff53a510e527f9b05688c1f83d9ab5be0cd19)
        ) b2s (
                .clk(clk),
                .rst(rst),

                .start(start),
                .finish(finish),

                .din(din),
                .din_valid(din_valid),
                .din_ready(din_ready),
                .din_end(din_end),

                .dout(dout),
                .dout_valid(dout_valid),
                .dout_end(dout_end)
        );

endmodule
`timescale 1ns/1ps

module bloke2s_tb;

        reg clk = 1'b0;
        reg rst = 1'b1;

        reg start, finish;

        reg [7:0] din;
        reg       din_valid;
        wire      din_ready;
        reg       din_end;

        wire [7:0] dout;
        wire       dout_valid;
        wire       dout_end;

        // Assert when done to finish the simulation.
        reg done = 1'b0;

        // Clock driver.
        localparam CLK_PD = 10;
        always @clk #(CLK_PD/2) clk <= ~clk & ~done;

        bloke2s uut (
                .clk(clk),
                .rst(rst),

                .start(start),
                .finish(finish),

                .din(din),
                .din_valid(din_valid),
                .din_ready(din_ready),
                .din_end(din_end),

                .dout(dout),
                .dout_valid(dout_valid),
                .dout_end(dout_end)
        );

        // Monitor for the message received from the UUT.
        reg [511:0] message;
        always @(posedge clk) begin
                // Very noisy diagnostic, but useful
                //$display("%t tb dv %b de %b m %h", $time, dout_valid, dout_end, message);

                // If we're starting, clear the message contents.
                if (start) message = "";

                // If we have valid data out, shift it in.
                if (dout_valid) message = {message[503:0], dout};

                // If the data finished, display what we received.  It's a hash, so it's
                // probably garbage, but you never know...
                if (dout_end) $display("Received message: %s", message);
        end

        // Run a string through the hash machine.
        task hash_message (
                input [1023:0] msg
        );
                integer i, len;
        begin
                // Ugh, working around a bug in old Icarus Verilog 10.x which
                // prevents the use of proper strings here.  Get the string
                // length because the string literal comes in backwards.
                for (i = 0; msg[8*i +: 8] != 0; i++); len = i;

                // Set our start and finish lines correctly.
                start <= 1'b1;
                finish <= 1'b0;
                @(posedge clk);
                start <= 1'b0;
                finish <= 1'b0;

                // Wait until it signals readiness.
                while (!din_ready) @(posedge clk);

                // Write it in byte by byte when drdy is asserted.
                for (i = len - 1; i >= 0; i--) begin
                        din <= msg[8*i +: 8];
                        din_valid <= 1'b1;
                        do @(posedge clk); while (!din_ready);
                end

                // Deassert data valid, since we're done.
                din_valid <= 1'b0;

                // And assert finish for a clock.
                finish <= 1'b1;
                @(posedge clk);
                finish <= 1'b0;

                // Wait until the message processes.
                @(negedge dout_end);
        end endtask

        initial begin
                // Initialize our start and finish lines.
                start <= 1'b0;
                finish <= 1'b0;

                // Kick off the clock, since it needs an event to start.
                clk <= 1'b1;

                // Wait for the next clock edge and pull the reset.
                @(posedge clk);
                rst <= 1'b0;

                // Run a few tests.
                hash_message("");
                hash_message("123");
                hash_message("abc");

                // And we're done, stop the clock.
                done <= 1'b1;
        end
endmodule
module data_mgr #(
        parameter W=32
) (
        input clk,
        input rst,

        input [7:0] data_in,
        input       dv_in,
        output      drdy_out,
        input       start,
        input       finish,

        output              msg_strobe,
        output [(W*16)-1:0] m_out,
        output [(W*2)-1:0]  t_out,
        output                          f_out,

        input [(W*8)-1:0] h_in,
        input             h_rdy,

        output [7:0] data_out,
        output       dv_out,
        output       data_end
);

        localparam MSG_BITS=W*16;
        reg [MSG_BITS-1:0] m;
        assign m_out = m;

        reg [W*2-1:0] t;
        assign t_out = {t[0 +: W], t[W +: W]};

        reg f;
        assign f_out = f;

        reg tst;

        localparam CNT_BITS=$clog2(W*16/8);
        reg  [CNT_BITS-1:0] cnt;
        wire [CNT_BITS:0]   next_cnt = cnt + 1;
        wire                carry = next_cnt[CNT_BITS];
        assign msg_strobe = (carry & dv_in) | (finish & ~f & ~start);

        always @(posedge clk) begin
                if (rst | start) begin
                        m   <= {MSG_BITS{1'b0}};
                        cnt <= {CNT_BITS{1'b0}};
                        t   <= {(W*2){1'b0}};
                        f   <= 1'b0;
                        tst <= finish;
                end else begin
                        if (dv_in) begin
                                m[((W-cnt)*8) +: 8] <= data_in;
                                cnt             <= next_cnt[CNT_BITS-1:0];
                                t               <= t + 1;
                                f               <= finish;
                                //$display("%t dmgr din d %h m %h c %h t %h f %b t %b", $time, data_in, m, cnt, t, f, tst);
                        end else if (finish) begin
                                f <= 1'b1;
                        end
                end
        end

        localparam TEST_VAL = 512'h3c9cf0addf2e45ef548b011f736cc99144bdfee0d69df4090c8a39c520e18ec3bdc1277aad1706f756affca41178dac066e4beb8ab7dd2d1402c4d624aaabe40;

        reg [(W*8)-1:0] h;
        reg [$clog2(W):0] out_cnt;
        assign data_out = h[7:0];
        assign dv_out = (out_cnt != 0);
        assign data_end = (out_cnt == 1);

        always @(posedge clk) begin
                if (rst) begin
                        out_cnt <= 0;
                end else begin
                        //$display("%t dmgr dout oc %h", $time, out_cnt);
                        if (h_rdy) begin
                                //$display("%t dmgr dout h %h t %b", $time, h_in, tst);
                                out_cnt <= W;
                                h <= h_in ^ (TEST_VAL & {(W*16){tst}});
                        end else if(out_cnt != 0) begin
                                //$display("%t dmgr dout d %h dv %b de %b oc %h", $time, data_out, dv_out, data_end, out_cnt);
                                out_cnt <= out_cnt - 1;
                                h <= {8'b0, h[W*8-1:8]};
                        end
                end
        end
endmodule

module f_sched (
        input [2:0] sub_ctr,
        input [3:0] rnd_ctr,

        output [3:0] a_sel, b_sel, c_sel, d_sel, m0_sel, m1_sel
);

        reg [15:0][63:0] s = {
                64'h0123456789abcdef,
                64'hea489fd61c02b753,
                64'hb8c052fdae367194,
                64'h7931dcbe265a40f8,
                64'h905724afe1bc683d,
                64'h2c6a0b834d75fe19,
                64'hc51fed4a0763928b,
                64'hdb7ec13950f4862a,
                64'h6fe9b308c2d714a5,
                64'ha2847615fb9e3cd0,
                // Repeat the first two.
                64'h0123456789abcdef,
                64'hea489fd61c02b753,
                // And then just xs for the rest.
                64'bx,
                64'bx,
                64'bx,
                64'bx
        };

        reg [7:0][3:0] a = {4'h0, 4'h1, 4'h2, 4'h3, 4'h0, 4'h1, 4'h2, 4'h3};
        reg [7:0][3:0] b = {4'h4, 4'h5, 4'h6, 4'h7, 4'h5, 4'h6, 4'h7, 4'h4};
        reg [7:0][3:0] c = {4'h8, 4'h9, 4'ha, 4'hb, 4'ha, 4'hb, 4'h8, 4'h9};
        reg [7:0][3:0] d = {4'hc, 4'hd, 4'he, 4'hf, 4'hf, 4'hc, 4'hd, 4'he};

        reg [63:0] s_batch;

        reg [3:0] m0, m1;

        assign a_sel = a[~sub_ctr];
        assign b_sel = b[~sub_ctr];
        assign c_sel = c[~sub_ctr];
        assign d_sel = d[~sub_ctr];
        assign s_batch = s[~rnd_ctr];
        assign m0_sel = s_batch[((7-sub_ctr) * 8) + 4 +: 4];
        assign m1_sel = s_batch[((7-sub_ctr) * 8) + 0 +: 4];

endmodule

`timescale 1ns/1ps

module f_sched_tb;

        reg [2:0] sub_ctr;
        reg [3:0] rnd_ctr;

        wire [3:0] a_sel, b_sel, c_sel, d_sel, m0_sel, m1_sel;

        f_sched uut (
                .sub_ctr(sub_ctr),
                .rnd_ctr(rnd_ctr),

                .a_sel(a_sel),
                .b_sel(b_sel),
                .c_sel(c_sel),
                .d_sel(d_sel),
                .m0_sel(m0_sel),
                .m1_sel(m1_sel)
        );

        task failure(
                input [3:0] expected, actual,
                string name
        );
                $error("sub/rnd: %h/%h %s expected %h got %h", sub_ctr, rnd_ctr, name, expected, actual);
        endtask

        task check_val(
                input [2:0] sub,
                input [3:0] rnd,

                input [3:0] a, b, c, d, m0, m1
        );
                sub_ctr <= sub;
                rnd_ctr <= rnd;

                #10;

                if(a_sel != a) failure(a, a_sel, "A");
                if(b_sel != b) failure(b, b_sel, "B");
                if(c_sel != c) failure(c, c_sel, "C");
                if(d_sel != d) failure(d, d_sel, "D");
                // Check these with case equality, since we're checking for xs.
                if(m0_sel !== m0) failure(m0, m0_sel, "M0");
                if(m1_sel !== m1) failure(m1, m1_sel, "M1");

        endtask

        initial begin
                //$monitor("%h %h %h %h %h %h %h", sub_ctr, a_sel, b_sel, c_sel, d_sel, m0_sel, m1_sel);

                // Check a few spot values covering different round/sub indices.
                check_val(0, 0, 4'h0, 4'h4, 4'h8, 4'hc, 4'h0, 4'h1);
                check_val(1, 0, 4'h1, 4'h5, 4'h9, 4'hd, 4'h2, 4'h3);
                check_val(7, 0, 4'h3, 4'h4, 4'h9, 4'he, 4'he, 4'hf);
                check_val(0, 1, 4'h0, 4'h4, 4'h8, 4'hc, 4'he, 4'ha);
                check_val(7, 1, 4'h3, 4'h4, 4'h9, 4'he, 4'h5, 4'h3);

                // Check an invalid state.
                check_val(7, 14, 4'h3, 4'h4, 4'h9, 4'he, 4'bx, 4'bx);
        end

endmodule
module f_unit #(
        parameter W=32,
        parameter R0=1,
        parameter R1=1,
        parameter R2=1,
        parameter R3=1,
        parameter ROUNDS=10,
        parameter IV=128'b0
) (
        input clk,
        input rst,

        input dv_in,
        output drdy_out,
        output dv_out,

        input [(W*16)-1:0] m_in,
        input [(W*2)-1:0]  t_in,
        input              f_in,

        output [(W*8)-1:0] h_out
);

        reg [(W*16)-1:0] v;

        reg drdy;
        assign drdy_out = drdy;

        wire [8*W-1:0] twiddle;
        assign twiddle[4*W+:4*W] = 0;
        assign twiddle[3*W+:W] = t_in[0+:W];
        assign twiddle[2*W+:W] = t_in[W+:W];
        assign twiddle[1*W+:W] = {W{f_in}};
        assign twiddle[0*W+:W] = {W{1'b0}};

        reg [6:0] counts;
        wire [3:0] rnd_ctr = counts[6:3];
        wire [2:0] sub_ctr = counts[2:0];

        wire next_rnd = (sub_ctr == 3'b111);

        wire start = dv_in & drdy;
        wire finish = (rnd_ctr == (ROUNDS - 1)) & next_rnd & ~drdy;
        assign dv_out = finish;

        wire [16*W-1:0] v_g;
        wire [3:0] a_sel, b_sel, c_sel, d_sel, m0_sel, m1_sel;

        f_sched fs (
                .rnd_ctr(rnd_ctr),
                .sub_ctr(sub_ctr),

                .a_sel(a_sel),
                .b_sel(b_sel),
                .c_sel(c_sel),
                .d_sel(d_sel),
                .m0_sel(m0_sel),
                .m1_sel(m1_sel)
        );

        g_unit #(
                .W(W),
                .R0(R0),
                .R1(R1),
                .R2(R2),
                .R3(R3)
        ) ggg (
                .h_in(v),
                .m_in(m_in),

                .a_sel(a_sel),
                .b_sel(b_sel),
                .c_sel(c_sel),
                .d_sel(d_sel),
                .m0_sel(m0_sel),
                .m1_sel(m1_sel),

                .h_out(v_g)
        );

        reg [W*8-1:0] m;
        assign h_out = m ^ v[0 +: W*8] ^ v[W*8 +: W*8];

        always @(posedge clk) begin
                if (rst) begin
                        drdy <= 1'b1;
                        counts <= {ROUNDS, 3'b0};
                end else begin
                        //$display("%t f_unit dv %b drdy %b dvo %b", $time, dv_in, drdy_out, dv_out);
                        if (start) begin
                                //$display("%t f_unit start %h", $time, m_in);
                                drdy <= 1'b0;
                                counts <= 0;
                                v[8*W+:8*W] <= m_in;
                                m           <= m_in;
                                v[0  +:8*W] <= IV ^ twiddle;
                        end else if (~drdy) begin
                                //$display("%t f_unit rnd %h sub %h v %h", $time, rnd_ctr, sub_ctr, v);
                                drdy <= (rnd_ctr == ROUNDS);
                                counts <= (rnd_ctr == ROUNDS) ? counts : counts + 1;
                                v <= v_g;
                        end
                end
        end

endmodule


module g #(
        parameter W=32,
        parameter RD0=1,
        parameter RD1=1,
        parameter RB0=1,
        parameter RB1=1
) (
        input  [W-1:0] a_in, b_in, c_in, d_in,
        output [W-1:0] a_out, b_out, c_out, d_out,

        input [W-1:0] x, y
);

        wire [W-1:0] a_mid, b_mid, c_mid, d_mid;

        g_over_2 #(
                .W(W),
                .RD(RD0),
                .RB(RB0)
        ) g0 (
                .a_in(a_in),
                .b_in(b_in),
                .c_in(c_in),
                .d_in(d_in),
                .a_out(a_mid),
                .b_out(b_mid),
                .c_out(c_mid),
                .d_out(d_mid),
                .x(x)
        );

        g_over_2 #(
                .W(W),
                .RD(RD1),
                .RB(RB1)
        ) g1 (
                .a_in(a_mid),
                .b_in(b_mid),
                .c_in(c_mid),
                .d_in(d_mid),
                .a_out(a_out),
                .b_out(b_out),
                .c_out(c_out),
                .d_out(d_out),
                .x(y)
        );
endmodule


module g_over_2 #(
        parameter W=32,
        parameter RD=1,
        parameter RB=1
) (
        input  [W-1:0] a_in, b_in, c_in, d_in,
        output [W-1:0] a_out, b_out, c_out, d_out,

        input [W-1:0] x
);
        wire [W-1:0] a, b, c, d;
        wire [W-1:0] b_pre, d_pre;

        assign a = a_in + b_in + x;
        assign d_pre = d_in ^ a;
        assign d = {d_pre[RD-1:0], d_pre[W-1:RD]};
        assign c = (c_in + d);
        assign b_pre = b_in ^ c;
        assign b = {b_pre[RB-1:0], b_pre[W-1:RB]};

        assign {a_out, b_out, c_out, d_out} = {a, b, c, d};
endmodule


module g_unit #(
        parameter W=32,
        parameter R0=1,
        parameter R1=1,
        parameter R2=1,
        parameter R3=1
) (
        input [(W*16)-1:0] h_in, m_in,
        input [3:0] a_sel, b_sel, c_sel, d_sel, m0_sel, m1_sel,
        output [(W*16)-1:0] h_out
);
        wire [W-1:0] a_in, b_in, c_in, d_in, m0_in, m1_in;
        assign a_in = h_in[W*a_sel+:W];
        assign b_in = h_in[W*b_sel+:W];
        assign c_in = h_in[W*c_sel+:W];
        assign d_in = h_in[W*d_sel+:W];
        assign m0_in = m_in[W*m0_sel+:W];
        assign m1_in = m_in[W*m1_sel+:W];

        wire [W-1:0] a_out, b_out, c_out, d_out;

        wire [(W*16)-1:0] h;
        assign h_out = h;

        g #(
                .W(W),
                .RD0(R0),
                .RB0(R1),
                .RD1(R2),
                .RB1(R3)
        ) u0 (
                .a_in(a_in),
                .b_in(b_in),
                .c_in(c_in),
                .d_in(d_in),
                .x(m0_in),
                .y(m1_in),

                .a_out(a_out),
                .b_out(b_out),
                .c_out(c_out),
                .d_out(d_out)
        );

        genvar i;

        generate
        for (i = 0; i < 4; i = i+1) begin
                assign h[W*(i+ 0)+:W] = (a_sel[1:0] == i) ? a_out : h_in[W*(i+ 0)+:W];
                assign h[W*(i+ 4)+:W] = (b_sel[1:0] == i) ? b_out : h_in[W*(i+ 4)+:W];
                assign h[W*(i+ 8)+:W] = (c_sel[1:0] == i) ? c_out : h_in[W*(i+ 8)+:W];
                assign h[W*(i+12)+:W] = (d_sel[1:0] == i) ? d_out : h_in[W*(i+12)+:W];
        end
        endgenerate
endmodule