00:00:00 [AUDIO LOGO] Hello, and thank you for using the BQ769x2 family of battery monitors. This video will walk you through the basics of creating your schematic, help you to avoid common mistakes, and direct you to the best resources for any questions not directly answered in this video. Let’s start by taking a quick look at the BQ76952 product folder. Here, you will find a few important documents to keep handy while creating your schematic. The Data Sheet and Technical Reference Manual are essential.

00:00:29 There are multiple application notes I will be mentioning throughout the video highlighted here. You will find links for all of these documents in the video notes. Besides the technical documentation, there are other useful tools to be aware of as you develop your hardware and software. Under the Hardware development tab of the product folder, you can find the link to the evaluation module. Under the Software development tab, you’ll find the link to download the BQSTUDIO evaluation software and code examples.

00:00:54 These software tools are covered in detail in a different video. In the EVM product folders, the EVM design files are also available for download. These ZIP files not only include the design files for the EVM, but they also include design files for a simple two-layer reference design without all the extra features of the evaluation module, like jumpers and test points. Another resource that is extremely helpful are the TI reference designs. At the time of the making of this video, there is one TI reference design for a 16s battery pack.

00:01:23 But more are expected in the future, so check back for updates when starting a new design. TI reference designs include a design guide and all of the board design files to help speed up the design process. The first step in the schematic design is selecting the appropriate device number for your system needs. The BQ76952 and BQ76942 are very similar. The main difference is the number of cell input pins. The BQ76952 supports up to 16 cells, and the BQ76942 supports up to 10 cells. The standard BQ76952 and BQ76942 part numbers

00:02:00 are configured for I Squared C communications with CRC disabled. CRC requires an additional checksum in the communications to help ensure the data integrity. These devices can be modified by updating the device registers and programming the OTP. Please note that OTP programming must be done without the battery cells connected since the power to the device must be between 10 and 12 volts during programming. For more information, refer to the BQ769x2 Calibration and OTP Programming Guide, or check the OTP FAQ

00:02:31 link in the video notes. Many systems need a regulator enabled by default if the regulator is supplying power to the microcontroller. In this case, the BQ7695202 or the BQ7694202 may be a good fit since they come pre-configured with the Regulator 1 enabled and set to 3.3 volts. For systems that need SPI communication, the 03 or 04 versions of the device are usually the best fit. I recommend using the I Squared C versions in most cases, unless SPI is absolutely required, since they are the easiest to work with and offer

00:03:07 advantages such as block write and read transactions. OK, let’s go through the basic schematic connections, and I will point out things to watch out for along the way. Here, we are looking at the 16S76952 device. Let’s start with the connection for VSS. VSS will connect to the bottom of the lowest battery cell, which we commonly refer to as bat minus. This is the ground reference for the battery electronics. This is different from the negative terminal of the pack, which we will connect bat minus through a current sense resistor.

00:03:36 The REG18 pin is an output for the internal 1.8 volt regulator and needs a typical 2.2 microfarad capacitor. This pin should not be used to supply power to any external circuits. Pins 19 and 44 are no-connect pins, and these should be left floating or connected to VSS. The Data Sheet contains an unused pin section that gives instructions for any pins that are unused on the device. The BQ769x2 family has two LDO outputs, which can be programmed to different output voltages and can each supply up to 45 milliamps of current.

00:04:09 The REG1 and REG2 LDOs take their input from the REGIN pin, which should be approximately 5.5 volts. The default configuration of the device uses the internal pre-regulator. The device drives the base of an external NPN BJT to provide a 5.5-volt REGIN pin voltage. The collector of the BJT can be routed either to the battery stack voltage or to the common drain between the protection FETs used in series. On the EVM, it is connected to the common drain, which allows power to be pulled from the charger when

00:04:38 it is connected. The diode prevents reverse current flow from the BREG pin through the BJT base to collector in the event of a battery pack short circuit. If the pack voltage is low, a Schottky diode can be used. Otherwise, the standard diode is OK. Ensure that the BJT and resistors are selected to tolerate the peak power under maximum load expected on the REG1 and REG2 outputs. For example, if the stack voltage for 16 fully charged cells is 68 volts, the voltage across the BJT could be 62.5 volts.

00:05:10 If REG1 and REG2 are both driving the maximum current of 45 milliamps, this results in about 5.6 watts of power dissipated through the BJT. The resistors help to distribute the heat among multiple components, rather than all just through the BJT. A 1-microfarad capacitor should be connected from the NPN collector to VSS. The REGIN pin needs a 22-nanofarad typical capacitor. A large 10-meg resistor is recommended from BREG to VSS to avoid any unintended leakage current that may occur and shutdown mode.

00:05:42 Each LDO output being used needs a 1-microfarad capacitor to VSS. If REG1 or REG2 is not used, it can be left floating. If the REGIN voltage is available from another supply, such as an onboard DC-to-DC converter, BREG should be connected to REGIN. The internal pre-regulator should also be disabled in the REG0 config register. If the LDOs are not needed, then BREG and REGIN should be connected to VSS. REG1 and REG2 can be left floating, or they can be connected to VSS. Next, let’s look at the connections

00:06:14 for the cell voltage measurement pins, pins VC0 to VC16. Each of these pins has a cell input resistor and a cell input capacitor. These components filter noise for the cell input voltage measurement. The cell input resistor values can range from 20 ohms to 100 ohms, and the cell input capacitors can range from 0.1 microfarad to 1 microfarad, with a 0.22 microfarad typical recommended value. Shown here are the values used on the BQ76952 evaluation module. A longer RC time constant is beneficial for reducing

00:06:47 transients during a short circuit event. So using the typical 0.22 microfarad capacitor or higher is recommended when using a low resistor value. The resistor value determines the amount of balancing current when using the internal cell balancing feature. The cell balancing app node has detailed examples and considerations for determining the resistor size when using internal balancing. 100-ohm resistors are recommended if using external balancing transistors. Examples for different configurations

00:07:15 are also covered later in this video and in the cell balancing app node. Note that the cell input capacitors are all connected differentially. But the VC1 and VC0 capacitors both connect to VSS. This helps to prevent a very heavy load from pushing VC0 below VSS. Many designs do not use all of the cell inputs, so unused cell inputs can be shorted to reduce the cell count. In this example, we show how 13 cells can be connected. One important requirement to keep in mind is that not all cell inputs can be shorted.

00:07:45 In the Unused Pin section of the Data Sheet, it describes the requirement that battery cells must be connected between VC1 and VC0, between VC2 and VC1, and between the top two VC pins-- in this case, VC16 and VC15 for the BQ76952 device. All other VC pins can be shorted as needed to reduce the number of cells. If higher cell balancing current is needed, external FETs or BJTs can be used. The cell balancing application report goes into a more detailed discussion on this topic and contains examples for each case.

00:08:18 TI reference design TIDA-010208 uses external in-channel FETs for balancing, so it is also a good reference. One more important thing to consider is that VC0 has lower voltage tolerance specified in the Data Sheet than the other VC pins. The abs max range for this pin goes from 0.3 volts below VSS to 6 volts above VSS. The TI reference design uses two additional components to support the case, but the VC0 pin may be exposed to a voltage beyond this range when the cells are being connected. The 3.6-volt Zener diode is used to protect VC0 from exceeding

00:08:53 the positive voltage, and the shot key is used to protect from exceeding the negative voltage. Next, let’s take a look at the BAT and CP1 pins. The BAT pin is the primary power supply for the device. A series diode is recommended on the BAT pin along with a capacitor to VSS. If there is a short circuit condition in the pack, this will prevent the BAT pin from being pulled low as the stack voltage goes to zero. The device will still continue to operate long enough to detect the short circuit and disable the discharge FET,

00:09:21 drawing current from the capacitor. A standard diode can be used, or a Schottky diode may be needed for a lower voltage pack. The evaluation module and reference designs also use a 100-picofarad capacitor to filter noise on the BAT pin. The charge pump generates a voltage 11 volts above the BAT pin voltage. This is the voltage used by the charge and discharge FET driver pins to control the high-side FETs. The typical value in the data sheet for the charge pump capacitor is 470 nanofarads, but this value

00:09:50 can be adjusted up to a maximum of 2.2 microfarads, depending on the total capacitance that the charge and discharge pins will need to drive. Section 4 of the Multiple FETs Application Report has an in-depth discussion on how to select the charge pump capacitor value and the trade offs. If the charge and discharge high-side FET drivers are he used, the charge pump capacitor is not needed, and the CP1 pin can connect directly to the BAT pin. For this configuration, the charge pump should be disabled in the device registers.

00:10:20 See the FET Configuration section of the Technical Reference Manual for details. The SRP and SRN pins connect to a current sense resistor to enable current measurements and current base protections. The SRP pin connects to the battery ground side of the sense resistor. And the SRN pin connects to the PACK- terminal side of the sense resistor. An input filter is connected between the sense resistor and the device inputs. The resistance value of the sense resistor should be selected to maximize the range of the Coulomb

00:10:48 counter, but it also should consider the overcurrent and short circuit detection thresholds and allow some tolerance margin. The detailed Design Procedure section of the Data Sheet walks through a step-by-step example for choosing an optimal sense resistor for an application. Optional 0.1-microfarad filter capacitors can be added for additional noise filtering at each sense input to ground. All filter components should be placed as close as possible to the device, rather than close to the sense resistor,

00:11:16 and the traces from the sense resistor routed it in parallel to the filter circuit. A ground plane can also be included around the filter network to add additional noise immunity. If current sense is not used, the SRP and SRN pins should be connected directly to VSS. The device can support up to nine external thermistors on multifunction pens. The device includes an internal pull-up resistor to bias the thermistor during measurement. The internal pull-up resistor has two options which can set the pull-up resistor to either 18

00:11:46 kiloohms or 180 kiloohms. The 18-kiloohm option is intended for use with thermistors, such as the Simatic 103-AT, which has 10 kiloohms of resistance at room temperature. The 180-kiloohm option is intended for use with higher resistance thermistors, such as the Simatic 204AP-2, which has 200 kiloohms of resistance at room temperature. Many thermistors have longer wires which can allow EMI on temperature measurements. So a capacitor in parallel with each thermistor may be beneficial. 470 picofarads is a common value used on the reference design.

00:12:22 Too large of a value can affect the settling time when the thermistor Is periodically biased, resulting in measurement error. The data sheet recommends that when using an 18-K pull-up resistor with a thermistor, a capacitor less than 4 nanofarads is recommended. When using the 180-kiloohm pull-up resistor, the capacitor should be less than 400 picofarads. The TS2 pin is unique in that it is also the wake pin for the device. If shutdown mode will be used in an application, it is not recommended to connect the thermistor to the TS2 pin

00:12:53 because this will prevent the device from being able to enter shutdown mode and can get stuck in a soft shutdown state. See the TRM for more information about soft shutdown. In the software development phase of the project, it is important to pick optimal coefficients for the specific thermistor used on the hardware to use in the temperature calibration registers. There is a tool in the Design and Development section of the Product page that can be used for this. Next, let’s talk about the protection

00:13:19 FETs and the FUSE pin. If protection FETs are not used, the charge and discharge pins should be left unconnected. If the FUSE pin is not used, it should be tied to VSS, or it can be left unconnected. In the most common configuration, the charge and discharge FETs are connected in series, as shown in this image. The charge FET is disabled when certain protections trigger, such as an overvoltage or overcurrent during charge. By default, the BQ769x2 will also disable the charge FET when the device is in sleep mode to save power.

00:13:51 This behavior can be modified in the Register Settings. The discharge FET is disabled for protections, such as under voltage, over current and discharge, and short circuit. The BQ769x2 also includes a body diode protection feature that is enabled by default, which should be used for FETs operating in series. Here’s how body diode protection works. When the discharged FET is disabled and there is a charge current applied greater than the body diet threshold, the device will enable the discharge FET

00:14:20 temporarily while there’s charge current to prevent the discharge FET from being damaged. The same is true for the charge FET. When the charge FET is disabled, but a discharge current is detected above the body diode threshold, the charge FET will be enabled temporarily to prevent damage. When the device is put into shutdown mode, the charge and discharge pins are allowed to fall to VSS. But in this circuit, the Zener diode and the 10-megaohm resistor will hold these pin voltages at the battery voltage level.

00:14:48 The typical recommended 10-meg resistor results in a 1.1-microamp load when the charge pump is enabled. Using a smaller resistor value than 10 meg increases this load, which could pull down the charge pump voltage. Sections 7 and 8 of the Multiple FETs Application note discuss the charge and discharge driver in much more detail. Here, we also show the FET gate resistors used on the evaluation modules. Smaller resistor values can be used for faster turn off, but switching the FETs too fast can result in damage, especially with the transient response

00:15:19 of a short circuit event. On the discharge pin in this example, 10K is used for FET turn-on, while for the FET turn-off 1K in parallel with 10K is used, which results in close to 1K for faster turn-off. Two series capacitors are connected across the FETs for ESD protection, along with two series capacitors from the PACK+ to PACK- terminals. The point labeled CD is the Common Drain point between the two series FETs. On the evaluation module, this is used to power the REGIN circuit. This way, the circuit can pull current from the charger

00:15:50 when it is connected or pull current from the battery when the charger is not connected. The FUSE pin can be used to permanently disable a pack in the case of a permanent fail condition being detected. The typical output voltage is the FUSE pin is 7 volts, so this circuit divides the voltage down to control a FET, which controls a three-terminal fuse. The PACK and LD pins of the device are normally connected through 10 kiloohms of resistance to the PACK+ in this configuration. We will discuss these pins in more detail

00:16:17 later in this video. In this example, the same series FET configuration is used. But here, we have the high-side P-FETs with series resistors for pre-charging and pre-discharging. This example also includes a reverse charger protection circuit. First, let’s talk about the pre-charge and pre-discharge FETs. For a battery with cells that under voltage, charging can be done with reduced current with the series resistor until the battery reaches a programmable voltage level. Once this level is reached, the charge FET

00:16:44 is enabled for normal fast charging, and the pre-charge FET is disabled. The pre-discharge FET can be used to reduce inrush current when the load is initially powered. If the pre-discharge feature is enabled, then whenever the discharge FET is turned on to power the load, first, the pre-discharge FET will be enabled and then transition to turn on the discharge FET and turn off the pre-discharge FET. The pre-charge and pre-discharge FET drivers are limited in how much current they can sink when enabled,

00:17:11 so it is recommended to use 1-megaohm or larger resistances across the FET gate source. Many VMS systems have the requirement of being able to survive a reverse charge or connection. Here, we show the reverse charge of protection circuit used on the evaluation module, and a similar circuit is used in the TIDA-010208 reference design. There is a detailed discussion of this circuit in the Multiple FETs Application Report, so I will not discuss it in detail here. However, the idea of protecting against a reverse polarity

00:17:40 charge or connection does affect other parts of our schematic, which we will go over. We will show a couple more examples for FET configurations in which we will not go into great detail, but I first want to point out these important resources for different FET configurations. For the case where separate charge and discharge paths are needed, you will want to refer to the Parallel Paths Application Report, which includes example circuits and test results. For the very common case where multiple FETs are needed

00:18:05 in parallel to support higher current, the Multiple FETs Application Report is a very helpful document that includes the circuits and test results for many configurations. It also includes valuable discussions on reverse charger protection circuits, guidance for the optimal charge pump capacitor selection, and a more detailed look into the charge and discharge driver current paths. For applications where low-side FETs are required, the Low-Side FET Application Report covers multiple different options,

00:18:30 like using a FET driver IC or using discrete components. The TIDA-010208 Reference Design is a good example where multiple parallel FETs are used along with a pre-discharge FET. Here is an example circuit using separate charge and discharge paths from the Parallel Paths Application Report. Since body diode protection would not be needed for this configuration, the SFET bit and the FET options register should be set to 0 to disable this feature, which is normally enabled by default. Here is an example circuit using

00:19:00 a large number of parallel FETs for a higher current application from the Multiple FETs Application Report. Note the use of local turn-off loops that help speed up FET turn-off when a large number of FETs is used. Also note the use of small individual gate resistors in addition to the resistor on the common path. When multiple FETs are used in parallel, oscillation can occur. So small individual gate resistors or ferrite beads are often used to avoid oscillation. The TI reference design, TIDA-010208 uses ferrite beads

00:19:30 on the FET gates. The Multiple FETs Application note contains many more examples and discussions on this topic. Let’s look at the PACK and LD pin connections. On the left, we have the standard recommended connections as used on the evaluation module. The PACK and LD pin have multiple uses that I’ll summarize briefly. The LD pin is used for wake-up from shutdown, such as when a charger is attached, for low detection after a discharge current fall, for charger detection and deep sleep, to exit from pre-discharge mode, and it can also

00:20:01 be used to measure the voltage at the load. It is necessary to connect this pin to PACK+ if the high-side FET drivers are being used. This is because when the discharge FET is disabled, it will follow the LD pin voltage to avoid damaging the discharge FET, preventing the gate from being driven to zero while the source is still high. The PACK pin is used for voltage measurement on the PACK connector. The measured voltage on this pin is used in fuse drive decision. The measured voltage on this pin is

00:20:29 used to detect charger attach, which is then used for overcurrent and charge recovery. The voltage on this pin is used in waking up from sleep mode and also when delaying voltage-based shutdown. In a series FET configuration, these should normally connect through 10 kiloohms to PACK+. Two quarter-watt resistors are used on the evaluation module to spread the power dissipation for the event if a reverse charger is connected. High-voltage Schottky diodes are also used on the evaluation module but are not

00:21:00 populated for the reverse charger polarity situation. If high-side FETs are not used, the LD pin can still be connected in this way, or it can be connected to VSS. On the right side, we have a more complex example from the TI reference design TIDA-010208. This reference design accounts for an application where a high-voltage 120 volts may occur on the PACK+ connection due to regenerative charging. Here, two 75-volt Zener diodes, D41 and D43, are used to clamp the voltage on the LD and PACK pins

00:21:35 when the higher voltage is present to prevent from going over the absolute maximum allowed by the device. Schottky diodes D45 and D46 are to prevent the PACK and LD pins from going significantly negative in the case of a reverse charger to connection. Even though the recommended resistance for the PACK and LD pins as 10 kiloohms, larger resistors are used to account for the larger expected voltage. The measurements can be compensated using the Data Sheet RADC in LD and RADC in DV parameters. The diode D44 is used to bypass R138 so that LD can follow

00:22:11 the PACK+ voltage quickly when it is disabled due to an overcurrent or short circuit protection triggering. Let’s look at common digital pin connections to the microcontroller. The I Squared C bus is connected to a microcontroller with pull-up resistor to the bus voltage. This voltage can be the REG1 LDO output if it is being used to power the microcontroller, or it can connect to a different voltage trail. If the REG1 output is being used, it needs to be enabled by default. The BQ7695x02 may be the best part number

00:22:41 to use since it comes pre-configured with the REG1 enabled to 3.3 volts. The BQ769x2 does utilize clock stretching to slow down the bus as needed, so it is important to use a microcontroller that supports this feature. Refer to the I Squared C specification for more information on clock stretching. If SPI is required, one of the SPI versions of the device should be used, which comes pre-configured with REG1 enabled with the SPI output using the REG1 logic level. For the SPI configuration, the CFETOFF pin

00:23:09 is used for the SPI chip select. The HDQ pin is the SPI MOSI. The SDA pin is the SPI MISO. And the SCL pin is the SPI clock. Let’s look at the other digital control pins available on the device. RST_SHUT is a digital input that can be controlled by the microcontroller to put the device into shutdown mode. CFETOFF and DFETOFF can be used by the microcontroller to disable the charge and discharge FETs. DFETOFF can actually be configured to control both FETs together if needed. The ALERT pin is highly configurable.

00:23:42 It can be used to alert the microcontroller of many different events, such as when new measurements are ready, when a protection has triggered, when the device wakes up from sleep mode, when self-balancing is active. These are just a few examples. It can be configured as an open-drain pin or as a push-pull. The DCHG and DDSG pins can be used to communicate the state of the protection FETs to the microcontroller. These pins are digital outputs that reflect the state of the charge and discharge pin FET drivers.

00:24:11 As shown in the Low-Side FET Application Report, these pins can also be used with additional circuitry to control low-side FETs. While the BQ769x2 family does have several permanent failure features that can be configured to trigger a fuse, some applications require a separate individual IC for secondary protection to provide redundancy in a system. Here, we list a few of the common secondary protectors used with the BQ769x2 family. The BQ7718 is an over-voltage protector that can support up to five cells

00:24:40 but can be stacked, as shown in the image on the left. The BQ76952 and BQ76942 evaluation modules are example boards that use multiple BQ7718 secondary protectors along with the BQ769x2. The BQ77216 supports up to 16 cells and also offers under-voltage and temperature protections. The image on the right, which is from the TIDA-010208 reference design shows a block diagram of this configuration. Note that the BQ77216 has two output pins that are ordered together to activate the fuse. The BQ77207 is very similar to the BQ77216

00:25:17 and can be used for applications with seven cells or less. When using a secondary protector, it is important that separate input filters are used on the battery monitor and the secondary protector. You should not share the same input filter components, or it could cause issues. The BQ77216 and BQ77207 secondary protectors have two output pins, COUT and DOUT. When you use standalone, these can be used to control a charge and discharge FET instead of controlling a fuse. This image from the BQ77216 data sheet

00:25:46 shows a configuration where the BQ77216 and BQ76952 are both used together to control the charge and discharge FETs. Note that in this image, the COUT and DOUT signals must also control the CFETOFF and DFETOFF inputs to the BQ76952 to ensure that the charge driver goes low when COUT is disabling the charge FET or that the discharge driver goes low when the DOUT signal is disabling the discharge FET. There’s one important thing to be careful of in this configuration. The BQ77216 does not have the body diode protection feature

00:26:19 that we discussed earlier in this video, which is often important for FETs connected in series. And when the BQ769x2 CFETOFF and DFETOFF pins are used, the body diode protection feature is not available. So we generally recommend that the secondary protector only control a fuse. When separate charge and discharge paths are used, then this configuration may be more practical. Some systems need to be able to report accurate state of charge of a battery. While the BQ769x2 offers many features that

00:26:47 are helpful with gauging, like accurate cell voltage, PACK current, cell temperature measurements, and accumulated charge, this battery monitor does not report state of charge. So some applications use a top-of-stack gauge along with a battery monitor for this purpose. TI reference design TIDA-010030 uses the BQ34Z100-G1 top-of-stack gauge along with the BQ76940 battery monitor. Many users have used the idea from this example and have used the BQ34Z100-G1 gauge with the BQ769x2 battery monitor.

00:27:21 In this configuration, the microcontroller communicates with the gauge and the monitor separately. Both will connect to the sense resistor, and the gauge will measure the stack voltage through a divider circuit. Thanks for watching, and I hope this video has helped you get started on your battery pack design using the BQ769x2.

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