I'm trying to write a "Thesis title" using an idea like "In a heterogeneous edge computing system with a main core and an NPU, the main core performs different tasks while sharing the same memory. In this case, they share the same memory bandwidth. I am trying to design a system that decides how to perform quantization based on this memory bandwidth situation. For example, if the priority of the application executed by the main core is higher than the priority of the task performed by the NPU, the memory bandwidth is operated mainly around the main core, and the NPU lowers the quantization bits to reduce the memory bandwidth.". Please write an appropriate "Thesis title" by referring to the format below.

Abstract
Element-wise Partial Product Quantization for
Efficient Deep Learning Accelerators
To achieve efficient deep neural network (DNN) edge computing, model
inference must be performed quickly while reducing the memory requirements
and computation. To this end, deep-learning quantization algorithms and
dedicated accelerators have been actively studied. However, in previous studies,
algorithms and accelerators are not co-optimized, which means they require
complex high-precision operations when processed in accelerators, or
additional resources are needed to store intermediate computational results. To
address these problems, I propose a novel quantization algorithm called the
element-wise partial product quantization algorithm along with a co-optimized
accelerator design. I apply the quantization process directly to the elementwise
partial product results of the DNN parameters. Through this process, the
size of the intermediate values generated in the inference process is reduced,
allowing the accelerator to perform inference using fewer resources. All the
floating-point parameters of the quantization algorithm are fixed in the form of
a power of two so that the accelerator can efficiently process them. Through
hardware-to-software co-optimization, I can efficiently process model
inference using only integer and bit operations while saving 13.5%, 7.5%, and
15% on flip-flops, look-up tables, and inputs/outputs, respectively, with only a
3%–4% loss in accuracy.

Abstract
Binarized Neural Network with Parameterized Weight
Clipping and Quantization Gap Minimization for Online
Knowledge Distillation
As the applications for artificial intelligence are growing rapidly, numerous
network compression algorithms have been developed to restrict computing
resources such as smartphones, edge, and IoT devices. We explore different
approaches to addressing the challenges posed by the high hardware
requirements of artificial neural networks. One approach is the use of network
compression algorithms such as knowledge distillation (KD), which leverages
soft labels derived from a teacher model to a less parameterized model to
achieve high accuracy with reduced computational burden. In contrast to the
use of full precision parameters, binarized neural networks (BNNs) offer an
intriguing opportunity to facilitate aggressive compression at the expense of
drastically degraded accuracy. In this study, we propose two performance
improvements for online KD when a BNN is applied as a student network,
namely parameterized weight clipping (PWC) and quantization gap-aware
adaptive temperature scheduling. By aggregating both methodologies, we
achieved a top-1 test accuracy of 94.60% for the CIFAR-10 dataset and a
comparable result for the Tiny-ImageNet dataset. Another strategy to mitigate the substantial hardware demands of artificial
neural networks is to lighten full-precision neural network in training. In this
paper, we propose a discrete weight-aware optimizer that can compensate for
discrete parameter characteristics and initial unstable learning state by
introducing an efficient weight update rule for BNNs. We achieved a
comparable image classification accuracy to that of a BNN using an optimizer
for full-precision parameters on the ImageNet dataset while dramatically
reducing the time required for training. These studies contribute to the
ongoing research efforts to improve the performance and efficiency of
binarized neural networks, particularly in the context of edge device
computing and other resource-constrained environments.

Abstract
Value-aware weight compression for memory
efficient DNN network
In response to the growing complexity and size of Deep Neural Networks
(DNNs), this study introduces "value aware weight compression." The
technique addresses their impact on memory bandwidth and capacity in
resource-limited platforms such as edge devices. Designed to enhance DNN
model inference, this innovative approach effectively utilizes data value
information for quantization. It also takes advantage of the fact that weight
variations have a small impact on DNN inference. By integrating precisionfocused
quantization with established lossless compression methods, our
method aims to strike a balance between maintaining DNN model accuracy and
minimizing resource consumption. A detailed comparison with INT8 data format
quantization and advanced compression algorithms reveals our method's clear
superiority. Focusing on inference accuracy (top-1 accuracy) and compression
ratio, it achieves an average compression ratio of 5.84 and compresses data to
6 bits, while ensuring high inference accuracy with a small accuracy loss (within
a 1% threshold). In addition, Our method had similar levels of inference
accuracy and compression ratio to existing state-of-the-art compression
algorithm methods. This value-aware weight compression technique effectively
improves memory utilization on resource-constrained platforms, significantly
reducing bottleneck challenges in DNN inference.

Abstract
Cooperative Acceleration of CNN Inference in
Multicore Processors
Convolutional Neural Networks (CNN) demand high computational
capabilities, motivating researchers to leverage Processing-In-Memory (PIM)
technology to achieve significant performance improvements. However,
implementing complex arithmetic operations such as multiplication within
memory is a significant challenge in the PIM architecture.
To address this challenge, this paper proposes a PIM-enabled cache (PEC)
architecture that utilizes shifters for performing multiplication operations at a
low cost.
We also introduce a filter-wise hardware-friendly Power-of-Two (POT)
quantization scheme that quantizes
weights into power-of-two values for specific convolution filters to accelerate
convolution operations with the PEC. Our experimental results demonstrate that
the proposed PEC, together with the POT quantization, achieves 2.10x
performance improvement on average with an accuracy degradation of 0.781%