Create the complete code for a MIPS processor simulator based on the following specifications from a computer architecture assignment. The simulator should be able to:

Task 1: MIPS Compiler

Implement a MIPS compiler that reads MIPS assembly instructions and converts them into binary machine code (hardcoded).

The compiler should handle .data and .text sections, supporting memory allocation, and around 10 MIPS instructions including:

R-type instructions: add, sub, and, or, slt
I-type instructions: lw, beq, addi
J-type instructions: j
Steps for MIPS Compiler:

Read MIPS assembly instructions from a text file.
Parse each line of assembly code, identifying the type of instruction (R-type, I-type, J-type) and extracting registers and values.
Convert each instruction into the corresponding binary machine code (opcode, funct, registers, immediate values, etc.).
Output the binary code in a text file.
Example: For the assembly instruction add $t1, $t2, $t3, the compiler should output:

Copy code
000000 01010 01011 01001 00000 100000
Task 2: MIPS Execution

Simulate the execution of the binary MIPS instructions using a simulated processor that follows the standard MIPS datapath.
Simulation pipeline:
Instruction Fetch: Retrieve the next instruction from memory.
Instruction Decode: Decode the instruction and identify control signals.
Execution: Perform ALU operations (addition, subtraction, etc.).
Memory Access: For lw and sw, simulate memory read/write operations, including offset handling.
Write Back: Write the result back to the register file.
Requirements:
Create 32 MIPS registers and simulate memory (hardcoded).
Implement ALU operations like addition and subtraction.
Generate and apply control signals during the instruction cycle.
Simulate proper program counter (PC) updates, including branching behavior for beq.
Ensure proper reads and writes to registers and memory.
All components, including registers, ALU, control unit, and memory, should be hardcoded and modular.
Handle at least the following instructions:
R-type: add, sub, and, or, slt
I-type: lw, beq, addi
J-type: j
Task 3: Testing

Test the simulator with 5 MIPS programs in total, including 2 provided programs and 3 additional custom programs.
Analyze the results of these programs by printing the final state of the registers after execution.
Ensure that the programs are sufficiently complex to test the robustness of the simulator.
Additional Requirements:

The program should be written in either C, C++, or Python.
No external libraries should be used for register management, memory simulation, or instruction parsing—everything should be hardcoded.
Ensure proper formatting and modularity of code (e.g., separate functions for instruction decoding, execution, memory access, etc.).
Report Generation:

After executing the MIPS programs, generate a report including:
A brief description of the MIPS architecture simulated.
Challenges faced during implementation.
Detailed working of the simulator.
Results of the MIPS programs with explanations.
Contributions of each group member.
Ensure that the MIPS simulator is capable of handling the entire instruction pipeline, managing 32 registers, and properly simulating memory and control signals, while adhering to the MIPS instruction format. The simulator should output the state of registers and memory after executing each instruction."