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./run.synthesis 
Cleaning up the old directory
Creating a new directory
Synthesizing

                           Design Compiler Graphical 
                                 DC Ultra (TM)
                                  DFTMAX (TM)
                              Power Compiler (TM)
                                 DesignWare (R)
                                 DC Expert (TM)
                               Design Vision (TM)
                               HDL Compiler (TM)
                               VHDL Compiler (TM)
                                  DFT Compiler
                               Design Compiler(R)

              Version Q-2019.12-SP5-5 for linux64 - Mar 21, 2021 

                    Copyright (c) 1988 - 2021 Synopsys, Inc.
   This software and the associated documentation are proprietary to Synopsys,
 Inc. This software may only be used in accordance with the terms and conditions
 of a written license agreement with Synopsys, Inc. All other use, reproduction,
            or distribution of this software is strictly prohibited.
Initializing...
# ---------------------------------------
# Step 1: Specify libraries
# ---------------------------------------
set link_library [list /home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db ]
/home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db
set target_library [list /home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db ]
/home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db
# ---------------------------------------
# Step 2: Read designs
# ---------------------------------------
analyze -format sverilog $env(LAB_PATH)/RTL/DMAC_CFG.sv
Running PRESTO HDLC
Compiling source file /home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_CFG.sv
Presto compilation completed successfully.
Loading db file '/home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db'
Information: Using CCS timing libraries. (TIM-024)
1
analyze -format sverilog $env(LAB_PATH)/RTL/DMAC_ENGINE.sv
Running PRESTO HDLC
Compiling source file /home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_ENGINE.sv
Presto compilation completed successfully.
1
#analyze -format sverilog $env(LAB_PATH)/RTL/DMAC_FIFO.sv
analyze -format sverilog $env(LAB_PATH)/RTL/DMAC_TOP.sv
Running PRESTO HDLC
Compiling source file /home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_TOP.sv
Presto compilation completed successfully.
1
set design_name         DMAC_TOP
DMAC_TOP
elaborate $design_name
Loading db file '/INST/syn/Q-2019.12-SP5-5/libraries/syn/gtech.db'
Loading db file '/INST/syn/Q-2019.12-SP5-5/libraries/syn/standard.sldb'
  Loading link library 'saed32lvt_ss0p75v125c'
  Loading link library 'gtech'
Running PRESTO HDLC
Presto compilation completed successfully. (DMAC_TOP)
Elaborated 1 design.
Current design is now 'DMAC_TOP'.
Information: Building the design 'DMAC_CFG'. (HDL-193)

Statistics for case statements in always block at line 56 in file
	'/home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_CFG.sv'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            63            |     no/auto      |
===============================================

Statistics for case statements in always block at line 88 in file
	'/home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_CFG.sv'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            93            |    auto/auto     |
===============================================

Inferred memory devices in process
	in routine DMAC_CFG line 56 in file
		'/home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_CFG.sv'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    byte_len_reg     | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|    src_addr_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    dst_addr_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine DMAC_CFG line 88 in file
		'/home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_CFG.sv'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      rdata_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully. (DMAC_CFG)
Information: Building the design 'DMAC_ENGINE'. (HDL-193)

Statistics for case statements in always block at line 101 in file
	'/home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_ENGINE.sv'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           116            |     no/auto      |
===============================================
Warning:  /home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_ENGINE.sv:191: Net arvalid_o or a directly connected net may be driven by more than one process or block. (ELAB-405)

Inferred memory devices in process
	in routine DMAC_ENGINE line 80 in file
		'/home/SOC40/lab5/DMAC/SYN/..//RTL/DMAC_ENGINE.sv'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    data_buf_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      state_reg      | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
|    src_addr_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    dst_addr_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|       cnt_reg       | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully. (DMAC_ENGINE)
1
# connect all the library components and designs
link

  Linking design 'DMAC_TOP'
  Using the following designs and libraries:
  --------------------------------------------------------------------------
  saed32lvt_ss0p75v125c (library) /home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db

1
# renames multiply references designs so that each
# instance references a unique design
uniquify
1
# ---------------------------------------
# Step 3: Define design environments
# ---------------------------------------
#
# ---------------------------------------
# Step 4: Set design constraints
# ---------------------------------------
# ---------------------------------------
# Clock
# ---------------------------------------
set clk_name clk
clk
set clk_freq            200
200
# Reduce clock period to model wire delay (65% of original period)
set clk_period [expr 1000 / double($clk_freq)]
5.0
create_clock -period $clk_period $clk_name
1
set clk_uncertainty [expr $clk_period * 0.35]
1.75
set_clock_uncertainty -setup $clk_uncertainty $clk_name
1
# Set infinite drive strength
set_drive 0 $clk_name
1
set_ideal_network rst_n
1
# ---------------------------------------
# Input/Output
# ---------------------------------------
# Apply default timing constraints for modules
set_input_delay  1.3 [all_inputs]  -clock $clk_name
1
set_output_delay 1.3 [all_outputs] -clock $clk_name
1
# ---------------------------------------
# Area
# ---------------------------------------
# If max_area is set 0, DesignCompiler will minimize the design as small as possible
set_max_area 0 
1
# ---------------------------------------
# Step 5: Synthesize and optimzie the design
# ---------------------------------------
compile_ultra
Loading db file '/INST/syn/Q-2019.12-SP5-5/libraries/syn/dw_foundation.sldb'
Warning: DesignWare synthetic library dw_foundation.sldb is added to the synthetic_library in the current command. (UISN-40)
Information: Performing power optimization. (PWR-850)
Analyzing: "/home/ScalableArchiLab/SAED32_EDK/lib/stdcell_lvt/db_ccs/saed32lvt_ss0p75v125c.db"
Library analysis succeeded.
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | Q-2019.12-DWBB_201912.5 |     *     |
| Licensed DW Building Blocks        | Q-2019.12-DWBB_201912.5 |     *     |
============================================================================

Information: Sequential output inversion is enabled.  SVF file must be used for formal verification. (OPT-1208)

Information: There are 88 potential problems in your design. Please run 'check_design' for more information. (LINT-99)

  Simplifying Design 'DMAC_TOP'

Loaded alib file './alib-52/saed32lvt_ss0p75v125c.db.alib'
  Building model 'DW01_NAND2'
Information: Ungrouping hierarchy u_cfg before Pass 1 (OPT-776)
Information: Ungrouping hierarchy u_engine before Pass 1 (OPT-776)
Information: Ungrouping 2 of 3 hierarchies before Pass 1 (OPT-775)
Information: State dependent leakage is now switched from on to off.

  Beginning Pass 1 Mapping
  ------------------------
  Processing 'DMAC_TOP'
 Implement Synthetic for 'DMAC_TOP'.

  Updating timing information
Information: Updating design information... (UID-85)
Information: The library cell 'PMT3_LVT' in the library 'saed32lvt_ss0p75v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'PMT2_LVT' in the library 'saed32lvt_ss0p75v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'PMT1_LVT' in the library 'saed32lvt_ss0p75v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'NMT3_LVT' in the library 'saed32lvt_ss0p75v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'NMT2_LVT' in the library 'saed32lvt_ss0p75v125c' is not characterized for internal power. (PWR-536)
Information: The library cell 'NMT1_LVT' in the library 'saed32lvt_ss0p75v125c' is not characterized for internal power. (PWR-536)
Information: The target library(s) contains cell(s), other than black boxes, that are not characterized for internal power. (PWR-24)

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%

  Beginning Mapping Optimizations  (Ultra High effort)
  -------------------------------
  Mapping Optimization (Phase 1)
Information: Added key list 'DesignWare' to design 'DMAC_TOP'. (DDB-72)

                                  TOTAL                                                
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER  
  --------- --------- --------- --------- --------- ------------------------- ---------
    0:00:08    3750.1      1.86      55.8       0.0                           103300688.0000
    0:00:08    3723.5      4.66     301.5       0.0                           102701512.0000

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%

  Beginning Constant Register Removal
  -----------------------------------
    0:00:08    3723.5      4.66     301.5       0.0                           102701512.0000
    0:00:08    3723.5      4.66     301.5       0.0                           102701512.0000

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%

  Beginning Global Optimizations
  ------------------------------
  Numerical Synthesis (Phase 1)
  Numerical Synthesis (Phase 2)
  Global Optimization (Phase 1)
  Global Optimization (Phase 2)
  Global Optimization (Phase 3)
  Global Optimization (Phase 4)
  Global Optimization (Phase 5)
  Global Optimization (Phase 6)
  Global Optimization (Phase 7)
  Global Optimization (Phase 8)
  Global Optimization (Phase 9)
  Global Optimization (Phase 10)
  Global Optimization (Phase 11)
  Global Optimization (Phase 12)
  Global Optimization (Phase 13)
  Global Optimization (Phase 14)
  Global Optimization (Phase 15)
  Global Optimization (Phase 16)
  Global Optimization (Phase 17)
  Global Optimization (Phase 18)
  Global Optimization (Phase 19)
  Global Optimization (Phase 20)
  Global Optimization (Phase 21)
  Global Optimization (Phase 22)
  Global Optimization (Phase 23)
  Global Optimization (Phase 24)
  Global Optimization (Phase 25)
  Global Optimization (Phase 26)
  Global Optimization (Phase 27)
  Global Optimization (Phase 28)
  Global Optimization (Phase 29)
  Global Optimization (Phase 30)

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%

  Beginning Isolate Ports
  -----------------------

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%

  Beginning Delay Optimization
  ----------------------------
    0:00:09    3433.0      2.92     244.3       0.0                           92588640.0000
    0:00:11    3553.2      0.60      96.4       0.0                           96631552.0000
    0:00:11    3553.2      0.60      96.4       0.0                           96631552.0000
    0:00:11    3511.0      0.77      97.5       0.0                           95149328.0000

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%
    0:00:11    3511.0      0.77      97.5       0.0                           95149328.0000
    0:00:11    3511.0      0.77      97.5       0.0                           95149328.0000

  Beginning WLM Backend Optimization
  --------------------------------------
    0:00:12    3449.2      0.71      94.9       0.0                           93745360.0000
    0:00:12    3448.7      0.68      93.6       0.0                           93745360.0000
    0:00:12    3448.7      0.68      93.6       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:12    3425.1      0.68      93.2       0.0                           93745360.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:13    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:14    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:14    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:14    3428.1      0.59      89.0       0.0                           93818064.0000
    0:00:15    3535.4      0.28      31.2       0.0 u_cfg/byte_len_reg[13]/D  97358600.0000
    0:00:16    3567.2      0.19      21.3       0.0                           98506560.0000
    0:00:16    3567.7      0.19      20.8       0.0                           98528832.0000

Threshold voltage group cell usage:
>> saed32cell_lvt 100.00%


  Beginning Leakage Power Optimization  (max_leakage_power 0)
  ------------------------------------

                                  TOTAL                                                
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER  
  --------- --------- --------- --------- --------- ------------------------- ---------
    0:00:16    3567.7      0.19      20.8       0.0                           98528832.0000
  Global Optimization (Phase 31)
  Global Optimization (Phase 32)
  Global Optimization (Phase 33)
  Global Optimization (Phase 34)
  Global Optimization (Phase 35)
  Global Optimization (Phase 36)
  Global Optimization (Phase 37)
  Global Optimization (Phase 38)
  Global Optimization (Phase 39)
  Global Optimization (Phase 40)
  Global Optimization (Phase 41)
  Global Optimization (Phase 42)
  Global Optimization (Phase 43)
  Global Optimization (Phase 44)
  Global Optimization (Phase 45)
    0:00:17    3486.3      0.30      30.4       0.0                           95993832.0000
    0:00:17    3511.3      0.25      20.4       0.0                           96742224.0000
    0:00:17    3511.3      0.25      20.4       0.0                           96742224.0000
    0:00:17    3494.5      0.25      14.9       0.0                           96705136.0000
    0:00:17    3494.5      0.25      14.9       0.0                           96705136.0000
    0:00:17    3494.7      0.25      15.4       0.0                           96705136.0000
    0:00:17    3494.7      0.25      15.4       0.0                           96705136.0000
    0:00:17    3494.7      0.25      15.4       0.0                           96705136.0000
    0:00:17    3494.7      0.25      15.4       0.0                           96705136.0000
    0:00:18    3494.7      0.25      15.4       0.0                           96705136.0000
    0:00:18    3494.7      0.25      15.4       0.0                           96705136.0000
    0:00:19    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:19    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:19    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:19    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000

                                  TOTAL                                                
   ELAPSED            WORST NEG   SETUP    DESIGN                              LEAKAGE 
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT            POWER  
  --------- --------- --------- --------- --------- ------------------------- ---------
    0:00:20    3568.7      0.05       1.9       0.0                           99229448.0000
    0:00:20    3543.5      0.08       2.8       0.0                           98512768.0000
    0:00:21    3530.3      0.07       3.0       0.0                           97858400.0000
    0:00:21    3530.3      0.07       3.0       0.0                           97858400.0000
    0:00:21    3528.3      0.06       2.2       0.0                           97858400.0000
    0:00:21    3522.2      0.06       2.2       0.0                           97640280.0000
    0:00:21    3529.8      0.05       1.8       0.0                           97892536.0000
    0:00:21    3529.8      0.05       1.8       0.0                           97892536.0000
    0:00:21    3529.8      0.05       1.8       0.0                           97892536.0000
    0:00:21    3529.8      0.05       1.8       0.0                           97892536.0000
    0:00:21    3529.8      0.05       1.8       0.0                           97892536.0000
    0:00:22    3528.8      0.05       1.8       0.0                           97892536.0000


Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios 


  Optimization Complete
  ---------------------
Information: State dependent leakage is now switched from off to on.
Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)
1
#compile
# ---------------------------------------
# Step 6: Analyze and resolve design problems
# ---------------------------------------
check_design  > $design_name.check_design.rpt
report_constraint -all_violators -verbose -sig 10 > $design_name.all_viol.rpt
report_design                             > $design_name.design.rpt
report_area -physical -hierarchy          > $design_name.area.rpt
report_timing -nworst 10 -max_paths 10    > $design_name.timing.rpt
report_power -analysis_effort high        > $design_name.power.rpt
report_cell                               > $design_name.cell.rpt
report_qor                                > $design_name.qor.rpt
report_reference                          > $design_name.reference.rpt
report_resources                          > $design_name.resources.rpt
report_hierarchy -full                    > $design_name.hierarchy.rpt
report_threshold_voltage_group            > $design_name.vth.rpt
# ---------------------------------------
# Step 7: Save the design database
# ---------------------------------------
write -hierarchy -format verilog -output  $design_name.netlist.v
Writing verilog file '/home/SOC40/lab5/DMAC/SYN/OUTPUT/DMAC_TOP.netlist.v'.
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
1
write -hierarchy -format ddc     -output  $design_name.ddc
Writing ddc file 'DMAC_TOP.ddc'.
1
write_sdf -version 1.0                    $design_name.sdf
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
Information: Writing timing information to file '/home/SOC40/lab5/DMAC/SYN/OUTPUT/DMAC_TOP.sdf'. (WT-3)
1
write_sdc                                 $design_name.sdc
1
exit

Memory usage for this session 235 Mbytes.
Memory usage for this session including child processes 235 Mbytes.
CPU usage for this session 94 seconds ( 0.03 hours ).
Elapsed time for this session 96 seconds ( 0.03 hours ).

Thank you...
Synthesis Completed