`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/08/18 21:58:58
// Design Name: 
// Module Name: K7_ADC
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module K7_ADC(

    input   clk_single,//k25
    input   sysclk_n,//k28
    input   sysclk_p,//k29

    input   reset,//AK5  adc

//---------------ADC-----------------//
    input   Fclk_p,//ah6
    input   Fclk_n,//ah5
    input   Dclk_p,//ah4
    input   Dclk_n,//aj4

    output ADC_CLK_P,//af6
    output ADC_CLK_N,//ag5

    output  SEN,//ah7
    input   SDout,//aj7
    output  SData,//ag7
    output  Sclk,//af7

    output  Trig_TX,//AK8
    // output  RSV_DIG,//aj8
    // output  PDN_FAST,//ak6
    // output  PDN_GBL,//aj6

//    input   [7:0] ADCdata_p,  //ADC输入
//    input   [7:0] ADCdata_n
    input  [2:0]  ADCdata_p,  //ADC输入  ac2 ad2 ae1 ag2  d15p-ac5
    input  [2:0]  ADCdata_n
);

wire [10:0] outdata ;


//---------------CLK-----------------//
wire clkila;
wire clkadc;
wire clk200M;
clk_wiz_0 clk_u0
(
    // Clock out ports
 //   .clk200M(clk200M),     // output clk400M
    .clkadc(clkadc),     // output clk10M
 //   .clkila(clkila),     // output clk10M
    // Status and control signals
    .reset(reset), // input reset
    .locked(),       // output locked
    // Clock in ports
    .clk_in1_p(sysclk_p),    // input clk_in1_p
    .clk_in1_n(sysclk_n));   // input clk_in1_n

//---------------VIO-----------------//

//wire [5:0] cnt_delay_out;
//wire [23:0] write_reg_data;
//wire [5:0]  delay_cnt_in;
//wire    areset;
//wire    W_delay_rdy;
//wire de_reset;

//out 
wire [9:0] cnt_delay_out;
wire delay_locked;
//wire    W_delay_rdy;


//in
wire    areset;
wire [23:0] write_reg_data;
wire [9:0]  cnt_delay_in;
//wire  de_reset;
wire in_delay_reset;
wire [1:0] in_delay_data_ce;
wire [1:0] in_delay_data_inc;
wire [1:0] bitslip;
vio_0 vio (
  .clk(clk_single),                // input wire clk
  .probe_in0(delay_locked),    // input wire [0 : 0] probe_in0
  .probe_in1(cnt_delay_out),   
  
  .probe_out0(areset),  // output wire [0 : 0] probe_out0
  .probe_out1(write_reg_data),
  .probe_out2(bitslip),
  .probe_out3(cnt_delay_in),
  .probe_out4(in_delay_reset),
  .probe_out5(in_delay_data_ce),
  .probe_out6(in_delay_data_inc)
);


//---------------IOBUF-----------------// 
wire dclk_in;
wire fclk_in;
wire bitclk;
wire dclk_delayed;
wire dclk_delayed_divout;
// wire [1:0] data_delayed;
IBUFDS #(
    .DIFF_TERM("FALSE"),       // Differential Termination
    .IBUF_LOW_PWR("FALSE"),     // Low power="TRUE", Highest performance="FALSE" 
    .IOSTANDARD("LVDS")     // Specify the input I/O standard
) dclk (
    .O(dclk_in),  // Buffer output
    .I(Dclk_p),  // Diff_p buffer input (connect directly to top-level port)
    .IB(Dclk_n) // Diff_n buffer input (connect directly to top-level port)
);

IBUFDS #(
    .DIFF_TERM("FALSE"),       // Differential Termination
    .IBUF_LOW_PWR("FALSE"),     // Low power="TRUE", Highest performance="FALSE" 
    .IOSTANDARD("LVDS")     // Specify the input I/O standard
) fclk (
    .O(fclk_in),  // Buffer output
    .I(Fclk_p),  // Diff_p buffer input (connect directly to top-level port)
    .IB(Fclk_n) // Diff_n buffer input (connect directly to top-level port)
);

OBUFDS #(
  .IOSTANDARD("LVDS"), // Specify the output I/O standard
  .SLEW("FAST")           // Specify the output slew rate
) OBUFDS_inst (
  .O(ADC_CLK_P),     // Diff_p output (connect directly to top-level port)
  .OB(ADC_CLK_N),   // Diff_n output (connect directly to top-level port)
  .I(clkadc)      // Buffer input
);


////---------------IDELAY-----------------// 
//(* IODELAY_GROUP = "delay1" *) 

//IDELAYCTRL IDELAYCTRL_inst1 (
//    .RDY(W_delay_rdy),       // 1-bit output: Ready output
//    .REFCLK(clkadc), // 1-bit input: Reference clock input
//    .RST(de_reset)         // 1-bit input: Active high reset input
//);

//(* IODELAY_GROUP = "delay1" *
//IDELAYE2 #(
//    .CINVCTRL_SEL("FALSE"),         // Enable dynamic clock inversion (FALSE, TRUE)
//    .DELAY_SRC("IDATAIN"),          // Delay input (IDATAIN, DATAIN)
//    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
//    .IDELAY_TYPE("VAR_LOAD"),       // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
//    .IDELAY_VALUE(0),               // Input delay tap setting (0-31)
//    .PIPE_SEL("FALSE"),             // Select pipelined mode, FALSE, TRUE
//    .REFCLK_FREQUENCY(20.0),       // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
//    .SIGNAL_PATTERN("CLOCK")         // DATA, CLOCK input signal
//)
//IDELAYE2_inst1 (
//    .CNTVALUEOUT(cnt_delay_out),  // 5-bit output: Counter value output
//    .DATAOUT(dclk_delayed),       // 1-bit output: Delayed data output
//    .C(clkadc),              // 1-bit input: Clock input
//    .CE(1'b0),                 // 1-bit input: Active high enable increment/decrement input
//    .CINVCTRL(1'b0),           // 1-bit input: Dynamic clock inversion input
//    .CNTVALUEIN(delay_cnt_in),  // 5-bit input: Counter value input
//    .DATAIN(0),             // 1-bit input: Internal delay data input
//    .IDATAIN(dclk_in),              // 1-bit input: Data input from the I/O
//    .INC(1'b0),                // 1-bit input: Increment / Decrement tap delay input
//    .LD(1'b0),                 // 1-bit input: Load IDELAY_VALUE input
//    .LDPIPEEN(1'b0),           // 1-bit input: Enable PIPELINE register to load data input
//    .REGRST(1'b0)              // 1-bit input: Active-high reset tap-delay input
//);

wire dclk_out;
BUFIO dataclk (
    .O(dclk_out), // 1-bit output: Clock output (connect to I/O clock loads).
    .I(dclk_in)   // 1-bit input: Clock input (connect to an IBUF or BUFMR).
);


//wire fclk_out;
//BUFIO frameclk (
//    .O(fclk_out), // 1-bit output: Clock output (connect to I/O clock loads).
//    .I(fclk_in)   // 1-bit input: Clock input (connect to an IBUF or BUFMR).
//);

//BUFR #(
//    .BUFR_DIVIDE("5"),   // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" 
//    .SIM_DEVICE("7SERIES")// Must be set to "7SERIES" 
//)
//BUFR_inst (
//    .O(dclk_delayed_divout),   // 1-bit output: Clock output port
//    .CE(1'b1),      // 1-bit input: Active high, clock enable (Divided modes only)
//    .CLR(1'b0),     // 1-bit input: Active high, asynchronous clear (Divided modes only)
//    .I(dclk_delayed)   // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
//);


//---------------SPI-----------------// 
adc_spi adc_spi(
    .clk40M(clk_single),
    .Sclk(Sclk),
    .areset(areset),
    .SEN(SEN),
    .SData(SData),
    .SDout(SDout),
    .write_reg_data(write_reg_data)
);


(*keep="true"*) wire [19:0] ADC_data_1;
  selectio_wiz_0 
  instance_name
 (
   .data_in_from_pins_p(ADCdata_p[1:0]), // input [1:0] data_in_from_pins_p
   .data_in_from_pins_n(ADCdata_n[1:0]), // input [1:0] data_in_from_pins_n
   .data_in_to_device(ADC_data_1), // output [19:0] data_in_to_device
   .in_delay_reset(in_delay_reset), // input in_delay_reset                    
   .in_delay_data_ce(in_delay_data_ce), // input [1  :0] in_delay_data_ce      
   .in_delay_data_inc(in_delay_data_inc), // input [1  :0] in_delay_data_inc     
   .in_delay_tap_in(cnt_delay_in), // input [49:0] in_delay_tap_in          
   .in_delay_tap_out(cnt_delay_out), // output [49:0] in_delay_tap_out          
 
   .delay_locked(delay_locked), // output delay_locked                      
   .ref_clock(clkadc), // input ref_clock                         
   .bitslip(bitslip), // input bitslip                           
   .clk_in(dclk_out), // input clk_in                            
   .clk_div_in(fclk_in), // input clk_div_in                        
   .io_reset() // input io_reset
); 


(*keep="true"*) wire [9:0] indata = {ADC_data_1[19],ADC_data_1[17],ADC_data_1[15],ADC_data_1[13],ADC_data_1[11],ADC_data_1[9],ADC_data_1[7],ADC_data_1[5],ADC_data_1[3],ADC_data_1[1]};
(*keep="true"*) wire [9:0] indata2 = {ADC_data_1[18],ADC_data_1[16],ADC_data_1[14],ADC_data_1[12],ADC_data_1[10],ADC_data_1[8],ADC_data_1[6],ADC_data_1[4],ADC_data_1[2],ADC_data_1[0]};


wire [9:0] signed_data_1;
complement ch1(
    .data_in(indata),
    .data_out(signed_data_1)
);
wire [9:0] signed_data_2;
complement ch2(
    .data_in(indata2),
    .data_out(signed_data_2)
);




ila_0  ila_u (
    .clk(clkadc), // input wire clk	
//	.probe0(clkadc), // input wire [0:0]  probe0  

	.probe0(clkadc), // input wire [15:0]  probe2 
	.probe1(indata), // input wire [15:0]  probe3 
	.probe2(indata2),
	.probe3(fclk_in) // input wire [0:0]  probe4
//	.probe5(clkadc), // input wire [0:0]  probe5  bitclk
);

endmodule