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US011263018B2 ( 12 ) United States Patent ( 10 ) Patent No .: US 11,263,018 B2 Kwon et al . ( 45 ) Date of Patent : Mar. 1 , 2022 ( 54 ) VECTOR PROCESSOR AND CONTROL METHOD THEREFOR ( 71 ) Applicant : SAMSUNG ELECTRONICS CO . , LTD . , Suwon - si ( KR ) ( 52 ) U.S. CI . CPC G06F 9/3887 ( 2013.01 ) ; G06F 9/30032 ( 2013.01 ) ; G06F 9/30036 ( 2013.01 ) ; G06F 9/30105 ( 2013.01 ) ( 58 ) Field of Classification Search CPC G06F 9/3887 See application file for complete search history . ( 56 ) References Cited ( 72 ) Inventors : Ki - seok Kwon , Seoul ( KR ) ; Jae - un Park , Seoul ( KR ) ; Dong - kwan Suh , Yongin - si ( KR ) ; Kang - jin Yoon , Seoul ( KR ) U.S. PATENT DOCUMENTS ( 73 ) Assignee : SAMSUNG ELECTRONICS CO . , LTD . , Suwon - si ( KR ) 6,115,812 A * 7,467,288 B2 9/2000 Abdallah G06F 9/30014 708/520 12/2008 Glossner , III et al . ( * ) Notice : Subject to any disclaimer , the term of this ( Continued ) patent is extended or adjusted under 35 U.S.C. 154 ( b ) by 0 days . OTHER PUBLICATIONS ( 21 ) Appl . No .: 16 / 462,086 ( 22 ) PCT Filed : Oct. 23 , 2017 ( 86 ) PCT No .: PCT / KR2017 / 011725 $ 371 ( c ) ( 1 ) , ( 2 ) Date : May 17 , 2019 ( 87 ) PCT Pub . No .: WO2018 / 101607 PCT Pub . Date : Jun . 7 , 2018 International Search Report ( PCT / ISA / 210 ) , issued by International Searching Authority in International Application No. PCT / KR2017 / 011725 , dated Feb. 2 , 2018 . ( Continued ) Primary Examiner Michael J Metzger ( 74 ) Attorney , Agent , or Firm Sughrue Mion , PLLC ( 57 ) ABSTRACT A vector processor is disclosed . The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data ( SIMD ) lanes , storing each of a plurality of pieces of data , and respectively outputting input data to be used in a current cycle among the plurality of pieces of data , a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files , and performing shuffling such that the received plurality of pieces of input data respectively cor respond to the plurality of SIMD lanes and outputting the same ; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit . 13 Claims , 12 Drawing Sheets ( 65 ) Prior Publication Data US 2020/0272478 A1 Aug. 27 , 2020 ( 30 ) Foreign Application Priority Data Dec. 2 , 2016 ( KR ) 10-2016-0163399 ( 51 ) Int . Cl . G06F 9/38 G06F 9/30 ( 2018.01 ) ( 2018.01 ) 140 100 10-1 | 150 141 1 1 Register File Instruction 110-1 Decode Unit Address MUX Address Registers --142 To other lanes | I 2143 144 Shuffle Data Path From other lanes 1 Control -120-1 unit Configuration & Status Registers Execution Unit 130-1 1 1 US 11,263,018 B2 Page 2 ( 56 ) References Cited U.S. PATENT DOCUMENTS 8,190,854 B2 5/2012 Codrescu et al . 8,984,499 B2 3/2015 Uliel et al . 9,141,386 B2 9/2015 Wiedemeier et al . 9,189,237 B2 11/2015 Chen et al . 2006/0227966 A1 10/2006 Knowles 2008/0065863 A1 * 3/2008 Eichenberger G06F 9/30032 712/224 2009/0172358 A1 * 7/2009 Sperber GO6F 9/30109 712/208 2013/0275718 A1 * 10/2013 Ueda 06F 9/30032 712/204 2013/0318328 A1 11/2013 Ould - Ahmed - Vall et al . 2013/0339649 Al 12/2013 Hsu et al . 2014/0181477 Al 6/2014 Vadiya et al . 2015/0154008 A1 6/2015 Uliel et al . 2015/0356054 Al 12/2015 Barak et al . 2016/0188532 Al 6/2016 Ould - Ahmed - Vall et al . 2016/0202983 A1 * 7/2016 Lin G06F 9/3802 712/225 2017/0286112 A1 * 10/2017 Espasa G06F 9/30018 OTHER PUBLICATIONS Written Opinion ( PCT / ISA / 237 ) issued by the International Search ing Authority in International Application No. PCT / KR2017 / 011725 , dated Feb. 2 , 2018 . * cited by examiner U.S. Patent Mar. 1 , 2022 Sheet 1 of 12 US 11,263,018 B2 FIG . 1 100 < A PLURALITY OF REGISTER FILES 110 SHUFFLE UNIT * 120 EXECUTION UNIT 130 U.S. Patent Mar. 1 , 2022 Sheet 2 of 12 US 11,263,018 B2 FIG . 2 140 100 | 10-1 150 141 | | | 1 1 Register File Instruction 110-1 Decode Unit MUX | | 1 | Address 1 Address Registers -142 To other lanes 1 1 1 | | 1 ! From 1 -143 144 Shuffle other lanes Control Data Path 120-1 unit 1 1 1 Configuration 1 & Status Registers Execution Unit 130-1 | 1 1 1 1 U.S. Patent Mar. 1 , 2022 Sheet 3 of 12 US 11,263,018 B2 FIG . 3A TO T1 WO w1 W2 W3 W4 W5 w6 T8 W7 w8 U.S. Patent Mar. 1 , 2022 Sheet 4 of 12 US 11,263,018 B2 FIG . 3B TO T1 0.2 04 0.5 1.2 0.3 1.3 1.5 0.0 10 2.0 3,0 01 11 2.1 3,1 0,6 1,6 T8 2,6 3,6 0,7 1,7 2,7 3,7 2.2 2.3 3,3 2,4 3,4 2.5 3,2 3,5 0,0 0,1 1,0 1,1 0.2 1.2 0.3 0,4 1,3 1,4 0,5 1,5 0,6 1,6 0,7 1,7 FIG .3C U.S. Patent * = = = = Mar. 1 , 2022 = = = * * * = * ? * * * = = = Time 4 -waySIMD CORE(Lane 0,123) TO out(0,0 )=W0*in (0,0)*in (0,1)out 0,1=W0 WO out (0,3)=W0 *in(0,3 )out(0,2 )=W0*in (0,2) T1 out(0,0 )+=w1*in (0,1)out +=w1*in (0,2)out +=w1*in (0,3)out +=w1*in (0,4)T2 out(0,0 )+=W2*in (0,2)out 0,1+=W2 *in(0,3 )out0,2 +=W2*in (0,4)out 0,3+=W2 *in(0,5 ) | ) ( T3 out(0,0 )+=W3*in (1,0)out 0,1+=W3 *in(1,1 )out0,2 +=W3*in (1,2)out 0,3+=W3 *in(1,3 )T4 out(0,0 )+=W4*in (1,1)out 0,1+=W4 *in(1,2 )out0,2 +=W4*in (1,3)out 0,3+=W4 *in(1,4 )T5 out(0,0 )+=W5*in (1,2)out 0,1+=w5 *in(1,3 )out0,2 +=W5*in (1,4)out 0,3+=w5 *in(1,5 )T6 out(0,0 )+=W6*in (2,0)out 0,1+=W6 *in(2,1 )out0,2 +=W6*in (2,2)out 0,3+=W6 *in(2,3 )T7 out(0,0 )+=w7*in (2,1)out 0,1+=w7 *in(2,2 )out0,2 +=w7*in (2,3)out 0,3+=W7 *in(2,4 ) w8 T8 out(0,0 )+=W8*in (2,2)out 0,1+=W8 *in(2,3 )out0,2 +=W8*in (2,4)out 0,3+=W8 *in(2,5 ) out (0,5)=wo *in(0,5 )T9out( 0,4)=wo *in(0,4 )6W0*in (out0,6 )= WO * in(0,7) out(0,7 )=wo w1 T10 out(0,4 )+=w1*in (0,5)out +=w1*in (0,6)out +=W1*in (0,7)out +=w1*in (0,8)T11 out(0,4 )+=W2*in (0,6)out 0,5+=W2 *in(0,7 )out0,6 +=W2*in (0,8)out 0,7+=W2 *in(0,9 )T12 out(0,4 )+=w3*in (1,4)out 0,5+=W3 *in(1,5 )out0,6 +=W3*in (1,6)out 0,7+=w3 *in(1,7 )T13 out(0,4 )+=W4*in (1,5)out 0,5+=W4 *in(1,6 )out0,6 +=W4*in (1,7)out 0,7+=W4 *in(1,8 ) Sheet 5 of 12 * * * * * * = = = * = = = * = = - * * * = = = * * * = = * - US 11,263,018 B2 U.S. Patent Mar. 1 , 2022 Sheet 6 of 12 US 11,263,018 B2 FIG . 4A lane 0 lane 3 0,0 0,4 : lane 1 0,1 0,5 lane 2 0,2 0,6 0,3 0,7 : TO 0,0 0,1 0,2 0,3 U.S. Patent Mar. 1 , 2022 Sheet 7 of 12 US 11,263,018 B2 FIG . 4B lane 0 lane 3 0,0 0,4 lane 1 0,1 0,5 lane 2 0,2 0,6 0,3 0,7 : : T1 0,4 0,1 0,2 0,3 U.S. Patent Mar. 1 , 2022 Sheet 8 of 12 US 11,263,018 B2 FIG . 5A TO 0.0 0,1 0,2 0,3 0,0 0,1 0.2 0.3 U.S. Patent Mar. 1 , 2022 Sheet 9 of 12 US 11,263,018 B2 FIG . 5B T1 0,4 0,1 0,2 0,3 0,1 0,2 0,3 0.4 U.S. Patent Mar. 1 , 2022 Sheet 10 of 12 US 11,263,018 B2 FIG . 6 140 142 100 10-1 150 141 Register File H110-1 Bottom Address Instruction Decode Unit Right MUX Address Address To other lanes Diagonal Address Fromiother lanes 143 Shuffle Data Path -120-1 | | 1 Column Size Reg . Row Size Reg . Execution Unit 130-1 Control unit Pattern Reg . Row Index Reg . | F -144 1 | Column 1 Index Reg . U.S. Patent Mar. 1 , 2022 Sheet 11 of 12 US 11,263,018 B2 FIG . 7 Prep . vrû vr10 VIT vr12 RELATED ART PRESENT DISCLOSURE load $ vro # main image load $ vro # main image load Svr10 # right load $ vr10 # right load $ vr11 # bottom load $ vr11 # bottom load $ vr12 # bottom right load $ vr12 # bottom right 1st row load $ sr9 # filter weight sf_set2d $ vr11 , $ vr10 , mul $ vr15 , $ vro , $ sr9 $ vr12 , 3 , 3 , 1 , 1 load $ sr9 load $ sr9 # filter weight -hcat $ vrt , $ vro , $ vr10 , 1 sf_mul $ vr15 , $ vro , $ sr9 mac $ vr15 , $ vr1 , $ sr9 load Ssr9 load $ sr9 sf mac $ vr15 , $ vro , $ sr9 hcat $ vr2 , $ vro , $ vr10,2 load Ssr9 mac $ vr15 , $ vr2 , $ sr9 sf_mac $ vr15 , $ vro , $ sr9 } vr1 vro vr10 vr11 vr12 vr3 vr13 4 vro vr10 vr11 vr12 2nd row vcat $ vr13 , $ vr10 , $ vr12 , 1 load $ sr9 load $ sr9 sf_mac $ vr15 , $ vro , $ sr9 vcat $ vr3 , $ vro , $ vr11 , 1 load $ sr9 mac $ vr15 , $ vr3 , $ sr9 sf_mac $ vr15 , $ vro , $ sr9 load $ sr9 load $ sr9 hcat $ vr4 , $ vr3 , $ vr13 , 1 sf_mac $ vr15 , $ vro , $ sr9 mac $ vr15 , $ vr4 , $ sr9 load $ sr9 hcat $ vr5 , $ vr3 , $ vr13 , 2 mac $ vr15 , $ vr5 , $ sr9 3rd row vcat $ vr13 , $ vr10 , $ vr12 , 2 load $ sr9 load $ sr9 sf_mac $ vr15 , $ vro , $ sr9 vcat $ vr6 , $ vro , $ vr11 , 2 load Ssr9 mac $ vr15 , $ vr6 , $ sr9 sf_mac $ vr15 , $ vro , $ sr9 load $ sr9 load Ssr9 hcat $ vr7 , $ vr6 , $ vr13 , 1 sf_mac $ vr15 , $ vro , $ sr9 mac $ vr15 , $ vr7 , $ sr9 load $ sr9 hcat $ vr8 , $ vr6 , $ vr13 , 1 mac $ vr15 , $ vr8 , $ sr9 } U.S. Patent Mar. 1 , 2022 Sheet 12 of 12 US 11,263,018 B2 FIG . 8 START S810 STORE A PLURALITY OF DATA TO EACH OF THE PLURALITY OF REGISTER FILES PROVIDED IN EACH OF THE PLURALITY OF SIMD LANES AND OUTPUT INPUT DATA USED IN A CURRENT CYCLE FROM AMONG A PLURALITY OF DATA RESPECTIVELY 7 S820 BY SHUFFLE UNIT , RECEIVE A PLURALITY OF INPUT DATA OUTPUT FROM A PLURALITY OF REGISTER FILES AND OUTPUT THE RECEIVED INPUT DATA TO CORRESPOND TO EACH OF THE PLURALITY OF SIMD LANES BY PERFORMING SHUFFLING PERFORM PARALLEL OPERATION BY RECEIVING INPUT DATA OUTPUT FROM THE SHUFFLE UNIT S830 END D 10 a a a US 11,263,018 B2 1 2 VECTOR PROCESSOR AND CONTROL may be an address of input data which is used in a current METHOD THEREFOR cycle among the plurality of data stored in each register file . The shuffle control unit may transmit shuffle information TECHNICAL FIELD on the plurality of input data to the shuffle unit , and the 5 shuffle information may be information on input data to be This disclosure relates to a vector processor and a control outputted from each of the plurality of SIMD lanes . method therefor , and , more specifically , to a vector proces- The shuffle control unit may include an address multi sor for simultaneously processing several values with one plexer to provide reference register address for input data to instruction and a control method therefor . be used in a current cycle to each of the plurality of register files , and a control unit to control the address multiplexer . BACKGROUND ART The shuffle control unit may further include at least one address register to store reference register address of each of Single Instruction Multiple Data ( SIMD ) is one category the plurality of SIMD lanes , and the control unit may control of parallel operations for processing several data through one instruction . Specifically , the SIMD is a method in which is the address multiplexer to provide one of the plurality of a plurality of execution units apply the same or similar reference register addresses provided from the instruction operations to a plurality of data and simultaneously process decode unit and the at least one address register to a the operations . corresponding register file . In the related art , a plurality of data are stored in a vector The input instruction may include at least one of a type of register file , and data to be used in a current cycle , among the 20 operations to be processed by the execution unit , an opera plurality of data , is shuffled and stored in the vector register tion method , and information on an increment in a horizontal file again . In other words , the vector register file is addi direction and an increment in a vertical direction . tionally stored with separate data which shuffles a plurality The vector processor may further include a scalar register of data in addition to a plurality of data , and the step of file , and the execution unit may perform a parallel operation deleting after use is repeated . Accordingly , there is a prob- 25 of input data outputted from the shuffle unit using scalar data lem in that power consumption is huge . outputted from the scalar register file . Further , when performing shuffling of a plurality of data , According to an embodiment of the disclosure , a control there is a difference in the shuffling method for each cycle , method of a vector processor includes storing a plurality of so a separate instruction for performing shuffling for each data to each of a plurality of register files provided to each cycle is required . As a result , there is a problem that a 30 of SIMD lanes , and outputting input data to be used in a program code is lengthened . current cycle among the plurality of data , receiving a plu rality of input data outputted from the plurality of register DISCLOSURE files , and performing shuffling such that the received plu rality of input data respectively correspond to the plurality of Technical Problem 35 SIMD lanes and outputting the same , and receiving input data outputted from the shuffle unit and performing a The disclosure provides a vector processor for improving parallel operation on the input data . the processing speed of redundant operations and a control The outputting by performing shuffling may include method therefor . receiving a plurality of input data outputted from the plu 40 rality of register files by each of the plurality of multiplexers Technical Solution provided in each of the plurality of SIMDs in the shuffle unit , and outputting one input data corresponding to a lane According to an embodiment of the disclosure , a vector provided with the corresponding multiplexer among the process includes a plurality of register files , wherein each of received plurality of input data . the plurality of register files provided to each of single 45 The control method may further include controlling the instruction multiple data ( SIMD ) lanes , storing a plurality of plurality of register files and the shuffle unit by cycles based data , and outputting input data to be used in a current cycle on an input instruction . among the plurality of data , a shuffle unit for receiving a The controlling may include transmitting a reference plurality of input data outputted from the plurality of register register address of each of the plurality of SIMD lanes to files , and performing shuffling such that the received plu- 50 each of the plurality of register files , and the reference rality of input data respectively correspond to the plurality of register address may be an address of input data which is SIMD lanes and outputting the same , and an execution unit used in a current cycle among the plurality of data stored in for receiving input data outputted from the shuffle unit and each register file . performing a parallel operation on the input data . The controlling may include transmitting shuffle informa The shuffle unit may include a plurality of multiplexers 55 tion on the plurality of input data to the shuffle unit , and the provided in each of the plurality of SIMD lanes , and each of shuffle information may be information on input data to be the plurality of multiplexers may receive a plurality of input outputted from each of the plurality of SIMD lanes . data outputted from the plurality of register files , and output The controlling may include controlling an address mul one input data corresponding to a lane provided with the tiplexer to provide reference register address for input data corresponding multiplexer among the received plurality of 60 to be used in a current cycle to each of the plurality of input data . register files . The vector processor may further include a shuffle control The controlling may include storing reference register unit to control the plurality of register files and the shuffle address of each of the plurality of SIMD lanes , and control unit by cycles based on an input instruction . ling the address multiplexer to provide one of the plurality The shuffle control unit may transmit a reference register 65 of reference register addresses provided from the instruction address of each of the plurality of SIMD lanes to each of the decode unit and the at least one address register to a plurality of register files , and the reference register address corresponding register file . a 10 a US 11,263,018 B2 3 4 The input instruction may include at least one of a type of FIG . 1 is a block diagram illustrating a configuration of a operations to be processed by the execution unit , an opera- vector processor 100 according to an embodiment of the tion method , and information on an increment in a horizontal disclosure . direction and an increment in a vertical direction . As illustrated in FIG . 1 , the vector processor 100 includes The performing a parallel operation may include perform- 5 a plurality of register files 110 , a shuffle unit 120 , and an ing a parallel operation of input data outputted from the execution unit 130 . shuffle unit using scalar data outputted from the scalar register file . The vector processor 100 means a processor having According to an embodiment of the disclosure , a record instructions for processing a plurality of data called a vector . able medium storing a program to execute an operation For example , the vector processor 100 may process single method of a vector processor ,in which the operation method instruction multiple data ( SIMD ) instruction for vector pro includes storing a plurality of data to each of a plurality of cessing to process multiple data . Here , the SIMD means a register files provided to each of SIMD lanes , and respec- method for simultaneously computing several values with tively outputting input data to be used in a current cycle one instruction . among the plurality of data , receiving a plurality of input Each of the plurality of register files 110 may be provided data outputted from the plurality of register files by the 15 in each of a plurality of the SIMD lanes . In other words , each shuffle unit , and performing shuffling such that the received plurality of input data respectively correspond to the plu SIMD lane may have one register file . Here , the plurality of rality of SIMD lanes and outputting the same , and executing SIMD lanes may correspond to a parallel processing unit . In a parallel operation by receiving input data outputted from other words , the vector processor 100 may perform parallel the shuffle unit . 20 processing for as many as the number of the plurality of the SIMD lanes , to the maximum . Advantageous Effects The plurality of register files 110 may be composed of a plurality of scalar register files rather than a vector register As set forth above , according to the diverse embodiments file . The vector register file may have an architecture in of the disclosure , the vector processor may improve pro- 25 which a plurality of data are stored in one address , and the cessing speed and energy efficiency by performing shuffling scalar register file may have an architecture in which one of input data , and then performing an operation without data is stored in one address . In other words , the register re - storing address for outputting the data stored in the plurality of DESCRIPTION OF DRAWINGS register files 110 may include the SIMD lane information 30 and the address to which data of the scalar register file FIG . 1 is a block diagram illustrating a configuration of a corresponding to the SIMD lane is to be output . vector processor according to an embodiment of the disclo- Each of the plurality of register files 110 may store a plurality of ta , and output input data used in a current FIG . 2 is a block diagram specifically illustrating a cycle among the plurality of data . For example , one register configuration of the vector processor of FIG . 1 according to 35 file may store two data , and output input data used in a an embodiment of the disclosure . current cycle . The remaining register files may store two FIG . 3A is a view to describe an operation in a case where data in the same manner , and output input data used in a a filter is applied according to an embodiment of the current cycle . In other words , during one cycle , the number disclosure . of data which is outputted from the plurality of register files FIG . 3B is a view to describe an operation in a case where 40 110 may be equal to the number of the plurality of register a filter is applied according to an embodiment of the files 110 . disclosure . The embodiment of the disclosure is not limited thereto , FIG . 3C is a view to describe an operation in a case where and when the parallel processing unit is smaller than the a filter is applied according to an embodiment of the number of the plurality of register files 110 , the number of disclosure . 45 data outputted from the plurality of register files 110 during FIG . 4A is a view to describe n operation of a plurality of one cycle may be smaller than the number of the plurality of register files according to an embodiment of the disclosure . register files 110 . FIG . 4B is a view to describe n operation of a plurality of The shuffle unit 120 may be connected to the plurality of register files according to an embodiment of the disclosure . register files 110 , and receive a plurality of input data which FIG . 5A is a view to describe an operation of a shuffle unit 50 is outputted from the plurality of register files . In other according to an embodiment of the disclosure . words , the shuffle unit 120 may receive one input data for FIG . 5B is a view to describe an operation of a shuffle unit each SIMD lane . according to an embodiment of the disclosure . The shuffle unit 120 may perform shuffling and output a FIG . 6 is a view to describe a two - dimensional ( 2D ) plurality of received input data to correspond to each of the operation according to another embodiment of the disclo- 55 plurality of SIMD lanes . For example , the shuffle unit 120 may receive data a , data b , data c , and data d from the first FIG . 7 is a view to describe simplification of a program register file , the second register file , the third register file , code according to an embodiment of the disclosure . and the fourth register file , respectively . Here , each of the FIG . 8 is a flowchart to describe a control method of a first register file , the second register file , the third register vector processor according to an embodiment of the disclo- 60 file , and the fourth register file may be provided in the first SIMD lane , the second SIMD lane , the third SIMD lane , and the fourth SIMD lane . The shuffle unit 120 may perform BEST MODE shuffling and output the received data a , data b , data c , and data d to be processed in the second SIMD lane , the third Hereinbelow , diverse embodiments of the disclosure will 65 SIMD lane , the fourth SIMD lane , and the first SIMD lane , be described in a greater detail with reference to the attached respectively . The shuffling method may be predetermined or drawings . may be input by a user according to types of operations . sure . a 9 a a a sure . sure . a . 30 US 11,263,018 B2 5 6 The execution unit 130 may receive input data outputted input data without performing shuffling . For example , the from the shuffle unit 120 and perform parallel operations . first shuffle data path 120-1 may provide input data output The execution unit 130 may perform parallel processing for ted from the first register file 110-1 to the first execution unit a plurality of input data per cycle . 130-1 . Alternatively , the input data outputted from the first The execution unit 130 may perform four fundamental 5 register file 110-1 may be provided directly to the first arithmetic operations , logical operations , and the like . How execution unit 130-1 without passing through the first shuffle ever , the embodiment of the disclosure is not limited thereto , data path 120-1 . and the execution unit 130 may perform any other opera- The shuffle control unit 140 may control the plurality of tions . register files 110 and the shuffle unit 120 by each cycle based The execution unit 130 may include a plurality of execu- 10 on input instructions . Alternatively , the shuffle control unit tion units provided in each of the plurality of SIMD lanes . 140 may control the plurality of register files 110 and the Alternatively , the execution unit 130 may be implemented to shuffle unit 120 by each cycle based on the input instructions simultaneously process a plurality of operations as one hardware . and the current state . At this time , the shuffle control unit 140 FIG . 2 is a block diagram specifically illustrating a 15 may store the current state . Further , the shuffle control unit configuration of the vector processor 100 of FIG . 1 accord 140 may update the current state whenever one cycle ing to an embodiment of the disclosure . elapses . As shown in FIG . 2 , the vector processor 100 may include The shuffle control unit 140 may transfer the reference a first SIMD lane 10-1 among a plurality of the SIMD lanes , register addresses of each of the plurality of SIMD lanes to a shuffle control unit 140 , and an instruction decode unit 20 each of the plurality of register files 110. Here , the reference 150. In FIG . 2 , only the first SIMD lane 10-1 among a register address may be an address of input data used in the plurality of the SIMD lanes is illustrated for convenience of current cycle among a plurality of data stored in each description . The description of the configuration of FIG . 2 register file . which overlaps the configuration of FIG . 1 will be omitted . For example , the first register file 110-1 may store the data The first SIMD lane 10-1 may include a first register file 25 a at the register address RO and the data b at the register 110-1 , a first shuffle data path 120-1 , and an execution unit address R1 . In this state , when the shuffle control unit 140 130-1 . The first shuffle data path 120-1 may be a configu transmits the reference register address R1 of the first SIMD ration of the shuffle unit 120. That is , the shuffle unit 120 lane 10-1 to the first register file 110-1 , the first register file may include a plurality of shuffle data paths , and each shuffle 110-1 may output the data b of the register address R1 . The data path may be provided in each SIMD lane . shuffle control unit 140 may transmit the reference register The shuffle unit 120 may include a plurality of multiplex ers provided in each of the plurality of SIMD lanes . That is , address corresponding to the remaining register files . the first shuffle data path 120-1 may be implemented as a The shuffle control unit 140 may transmit shuffle infor multiplexer . Each of the plurality of multiplexers may mation for a plurality of input data to the shuffle unit 120 . receive a plurality of input data outputted from the plurality 35 That is , the shuffle control unit 140 may transmit the shuffle of register files 110 and output one input data corresponding information for a plurality of input data to the plurality of to a lane provided with the multiplexer , among the received shuffle data paths provided in the shuffle unit 120. Here , the plurality of input data . shuffle information may be information on the input data to For example , the first shuffle data path 120-1 may be be output in each of the plurality of SIMD lanes . implemented with a first multiplexer , the first multiplexer 40 For example , the shuffle control unit 140 may provide , to may receive not only input data outputted from the first the first multiplexer , information on the input port to which register file 110-1 , but also input data outputted from the the input data to be outputted from the current cycle is input , remaining register files provided in other SIMD lanes . That among the plurality of input data input to the plurality of is , the number of input ports of the multiplexer may be the input ports of the first multiplexer . The shuffle control unit same as the number of the plurality of SIMD lanes . 45 140 may also provide information corresponding to each of Also , a second shuffle data path ( not shown ) provided in the remaining multiplexers . a second SIMD lane ( not shown ) may be implemented with The shuffle control unit 140 may generate shuffle infor a second multiplexer , and the second multiplexer may mation for a plurality of input data based on at least one of receive not only the input data which is outputted from the an input instruction and a current state . As described above , second register file ( not shown ) , but also the input data 50 the plurality of register files 110 and the shuffle unit 120 may outputted from the remaining register files provided in other operate according to the control of the shuffle control unit SIMD lanes . 140. Hereinafter , the configuration of the shuffle control unit That is , each of the plurality of multiplexers may receive 140 will be described in further detail . a plurality of input data from the plurality of register files The shuffle control unit 140 may include an address 110. In addition , each register file 110 may provide input 55 multiplexer 141 , an address register 142 , a control unit 143 , data to not only a shuffle data path provided in a corre- and a configuration register 144 . sponding SIMD lane but also to a shuffle data path provided The address multiplexer 141 may provide a reference in another SIMD lane . register address for the input data to be used in the current The first shuffle data path 120-1 may provide input data cycle to each of the plurality of register files 110. Although outputted from the first register file 110-1 to an execution 60 FIG . 2 shows that there is one address multiplexer 141 , but unit provided in a SIMD lane other than the first SIMD lane the embodiment is not limited thereto . For example , the 10-1 . Also , the first shuffle data path 120-1 may provide one address multiplexer 141 may be implemented to be plural to of the plurality of input data outputted from the register file correspond to each of the plurality of register files 110 . other than the first register file 110-1 to the first execution At least one address register 142 may store a reference unit 130-1 . 65 register address of each of a plurality of SIMD lanes . At least However , the embodiment is not limited thereto , and the one address register 142 may receive and store a reference shuffle data path 120-1 may output a plurality of received register address from the instruction decode unit 150 . 9 US 11,263,018 B2 7 8 The control unit 143 may control the address multiplexer FIG . 3B , the processor may determine data of ( 0,0 ) pixel of 141 and the shuffle data path 120-1 . The method of control- the lower image of FIG . 3B by multiplying each of wo , ling the shuffle data path 120-1 has been described and will wl , ... , w8 by ( 0,0 ) , ( 0,1 ) , ( 0,2 ) , ( 1,0 ) , ( 1,1 ) , ( 1,2 ) , ( 2,0 ) , not be further described . ( 2,1 ) and ( 2,2 ) pixels of the upper image , and adding all the The control unit 143 may control the address multiplexer 5 multiplied values . 141 to provide one of a plurality of reference register The processor may determine the data of ( 0,1 ) pixel of the addresses provided from the instruction decode unit 150 and lower image of FIG . 3B by applying each of wo , wl , ... , the at least one address register 142 to the corresponding w8 to ( 0,1 ) , ( 0,2 ) , ( 0,3 ) , ( 1,1 ) , ( 1,2 ) , ( 1,3 ) , ( 2,1 ) , ( 2,2 ) , and register file . ( 2,3 ) pixels of the upper image of FIG . 3B . The processor The configuration register 144 may store the information 10 may repeat this process for all pixels and generate the lower included in the input instruction . Also , the configuration image of FIG . 3B . register 144 may store the current state . For example , the When performing a parallel operation , the vector proces configuration register 144 may include a counter for storing sor 100 multiplies wo by each of ( 0,0 ) , ( 0 , 1 ) , ( 0 , 2 ) , and ( 0 , the current state . 3 ) in the upper image . Specifically , multiplication operations The control unit 143 may control other units based on the 15 of wo by each of ( 0,0 ) , ( 0 , 1 ) , ( 0 , 2 ) , and ( 0 , 3 ) in the upper information stored in the configuration register 144. Here , image in each of the SIMD lanes may be performed . For the input instruction may include at least one of the type of example , a multiplication operation of wo by ( 0,0 ) of the operation to be processed by the execution unit 130 , the upper image may be performed in the first SIMD lane , a operation method , and information on an increment in the multiplication operation of w0 by ( 0 , 1 ) of the upper image horizontal and vertical directions . 20 may be performed in the second SIMD lane , a multiplication In addition , the vector processor 100 may further include operation of wo by ( 0 , 2 ) of the upper image may be an instruction memory ( not shown ) , an instruction fetch unit performed in the third SIMD lane , and a multiplication ( not shown ) , the instruction decode unit 150 , a scalar operation of wo by ( 0 , 3 ) of the upper image may be register file ( not shown ) , or the like . performed in the fourth SIMD lane . The above operations The instruction memory may store instructions . The 25 may be performed in the cycle of TO . instruction fetch unit may read instructions to be used in the Thereafter , a multiplication operation of wl by ( 0 , 1 ) of current cycle from the instruction memory based on the the upper image may be performed in the first SIMD lane , input instruction . The instruction decode unit 150 may and the multiplication result may be added to the multipli determine the type of instruction , the address of the input cation result of wo by ( 0 , 0 ) of the upper image . The same data of the instruction , and the like by decoding the fetched 30 operation may be performed in the remaining SIMD lanes . instructions . The above operation may be performed in the cycle of T1 . The scalar register file , provided separately from the In FIGS . 3A and 3B , data necessary for the TO , T1 and T8 plurality of register files , is a register file for storing scalar cycles are separately displayed . data . The plurality of register files are register files for That is , the vector processor 100 may perform parallel storing vector data . 35 operation by performing repeated multiplication and addi The execution unit 130 may perform parallel operation of tion operations for each SIMD lane . In FIG . 3C , operations the plurality of input data outputted from the shuffle unit 120 for each cycle are indicated by SIMD lanes , and the opera using the scalar data outputted from the scalar register file . tion of each configuration in the vector processor 100 will be That is , the scalar data outputted from the scalar register described in detail with reference to the following drawings . file may be transmitted to all of the plurality of execution 40 FIGS . 4A and 4B are views to describe n operation of a units included in the execution unit 130. The execution unit plurality of register files 110 according to an embodiment of may operate scalar data and input data input to each execu- the disclosure . tion unit . That is , a plurality of execution units may perform As shown in FIG . 4A , each of the plurality of register files parallel operation using one scalar data . 110 may store a plurality of data . Here , the plurality of data As described above , the execution unit 130 directly 45 may be the upper image of FIG . 3B . The oth register file ( lane receives the input data from the shuffle unit 120 , not from the 0 ) may store ( 0,0 ) and ( 0,4 ) , the first register file ( lane 1 ) plurality of register files 110 , and thus may improve the may store ( 0,1 ) and ( 0,5 ) , the second register file ( lane 2 ) processing speed and energy efficiency . Hereinafter , an may store ( 0,2 ) and ( 0,6 ) , and the third register file ( lane 3 ) example of the operation of the vector processor 100 will be may store ( 0,3 ) and ( 0 , 7 ) . described with reference to the drawings . In the TO cycle , the Oth register file may output ( 0,0 ) as FIGS . 3A to 3C are views to describe an operation in a input data , the first register file may output ( 0 , 1 ) as input case where a filter is applied according to an embodiment of data , the second register file may output ( 0 , 2 ) as the input the disclosure . data , and the third register file may output ( 0 , 3 ) as the input FIG . 3A shows an example of a filter that may be applied data . to an image . Although FIG . 3A illustrates a 3x3 matrix filter , 55 The plurality of register files 110 may determine the input it is not limited thereto and the filter may have any other data to be output by the reference register address provided type . Further , the art of the disclosure may be applied to all by the shuffle control unit 140. That is , the shuffle control the cases in which a parallel operation may be applied even unit 140 may provide a reference register address to each of if it is not a filter . a plurality of register files 110 for each cycle . For example , The vector processor 100 may apply a filter to the image 60 the shuffle control unit 140 may provide the reference as shown in FIG . 3B . In FIG . 3B , an upper image shows data register address RO to the Oth register file in the TO cycle , for each pixel of an image , and a lower image shows an provide the reference register address RO to the first register image to which a filter is applied . The filter may be stored file , provide the reference register address RO to the second in a scalar register file . register file , and provide the reference register address RO to For convenience of description , a case where a filter is 65 the third register file . applied without parallel operation will be described first . Then , as shown in FIG . 4B , in the T1 cycle , the Oth When the filter of FIG . 3A is applied to the upper image of register file may output ( 0 , 4 ) as input data , the first register 50 a . a 2 US 11,263,018 B2 9 10 file may output ( 0 , 1 ) as input data , the second register file FIG . 6 is a view to describe a two - dimensional ( 2D ) may output ( 0 , 2 ) as input data , and the third register file may operation according to another embodiment of the disclo output ( 0 , 3 ) as input data . sure . For example , if pixel data of ( 0 , 0 ) , ( 0 , 1 ) , ( 0 , 2 ) , and At this time , the shuffle control unit 140 may provide the ( 0,3 ) are operated during the TO cycle in the upper image of reference register address R1 to the oth register file in the Ti 5 FIG . 3B , when 2D operation is performed , the pixel data of cycle , the reference register address RO to the first register ( 0 , 0 ) , ( 0 , 1 ) , ( 1 , 0 ) , and ( 1 , 1 ) may be operated during the file , the reference register address RO to the second register TO cycle . The 2D calculation is a well - known art and is very file , and the reference register address RO to the third register similar to the description of FIG . 3B and will not be further file . described . FIGS . 4A and 4B illustrate that four parallel operations 10 As shown in FIG . 6 , at least one address register 142 may may be available as there are four SIMD lanes for conve include a bottom address , a right address , and a diagonal nience of description , but any other number of SIMD lane address . For example , the instruction decode unit may may be provided . In FIGS . 4A and 4B , it is described that data of ( 0,0 ) to provide a reference register address RO for referring to pixel ( 0,7 ) are stored in the plurality of register files 110 , but it is 15 data of ( 0 , 0 ) , ( 0 , 1 ) , ( 1 , 0 ) , and ( 1 , 1 ) to the address not limited thereto . For example , the plurality of register multiplexer 141. The at least one address register 142 may files 110 may store more data . provide bottom address R1 for referring to the pixel data of When the plurality of register files 110 store data of ( 0,0 ) ( 2,0 ) , ( 2 , 1 ) , ( 2 , 2 ) , and ( 2 , 3 ) right address R2 for referring to ( 0,7 ) , each of the reference register addresses may be to the pixel data of ( 0 , 2 ) , ( 0 , 3 ) , ( 1 , 2 ) , and ( 1 , 3 ) and composed of one bit . However , when the plurality of register 20 diagonal address R3 for referring to the pixel data of ( 2 , 2 ) , files 110 store more data , each of the reference register ( 2 , 3 ) , ( 3 , 2 ) , and ( 3 , 3 ) to the address multiplexer 141 . addresses may be composed of more bits . That is , the Meanwhile , the configuration register 144 may store the number of bits of the reference register address may be input data according to the instructions as shown below . determined by the size of the data stored in the plurality of [ Instruction 1 ] register files . 25 sf_set2d $ bottom , $ right , $ diagonal , num_row , num_col , Alternatively , if the number of bits of the reference row_stride , col_stride register address is predetermined , data stored in the plurality Here , $ bottom , Sright , and $ diagonal may be bottom of register files 110 may be determined based on the number address , right address , and diagonal address , respectively . of bits of the reference register as well . The num_row , and num_col may be the maximum value in FIGS . 5A and 5Bs are views to describe an operation of 30 the vertical direction and the maximum value in the hori a shuffle unit 120 according to an embodiment of the zontal direction , respectively . The row_stride and col_stride disclosure . may be a vertical increment or a horizontal increment , As illustrated in FIG . 5A the leftmost multiplexer may respectively . That is , the configuration register 144 may receive an input of the input data ( 0,0 ) , ( 0 , 1 ) , ( 0 , 2 ) , and ( 0 , receive the maximum value in the vertical direction , the 3 ) outputted from the plurality of register files 110 in the TO 35 maximum value in the horizontal direction , the vertical cycle . The leftmost multiplexer may output ( 0 , 0 ) as the increment ,and the horizontal increment as column size reg . , input data . The remaining multiplexers may be operating in row size reg . , row index reg . , and column index reg . , the similar manner . respectively . The pattern reg . may be input as the instruction At this time , the shuffle control unit 140 may provide itself and represents a reference pattern . information on data that each multiplexer has to output in 40 Here , the reference pattern represents a data access order . each cycle . For example , the shuffle control unit 140 may For example , the reference pattern may be one of 1D control the leftmost multiplexer to output the input data increase , 2D increase , and 2D zigzag . input through the first input port of the leftmost multiplexer The control unit 143 may receive an input of the above in the TO cycle . data and control the address multiplexer 141 and the shuffle Then , as illustrated in FIG . 5B , the leftmost multiplexer 45 data path 120-1 . may receive the input data ( 0 , 0 ) , ( 0 , 1 ) , ( 0 , 2 ) , and ( 0 , 3 ) Besides , a state update instruction after the multiplication outputted from the plurality of register files 110 in the Ti operation or multiply and add ( MAC ) operation may be cycle . The leftmost multiplexer may output ( 0 , 1 ) as input used , as shown below . data . The remaining multiplexers may be operating in the Instruction 2 ] similar manner . 50 sf_mul $ res , $ multiplicand , $ multiplier At this time , the shuffle control unit 140 may control the sf_mac $ acc , $ multiplicand , $ multiplier leftmost multiplexer to output the input data input through In instruction 2 , multiplicand may be an image , and the second input port of the leftmost multiplexer in the Ti multiplier may be a filter . Here , res may be the multiplication cycle . result of multiplicand and multiplier , and acc may be the That is , the shuffle unit 120 may be implemented with a 55 result of adding the result of multiplying multiplicand and plurality of multiplexers , and each multiplexer may receive multiplier to the previous value . a plurality of input data and output one of the input data . As described above , when instruction 1 and instruction 2 Through the above operation , the SIMD lane in which each are used , simplification of a program code is possible . of the plurality of input data is to be operated may be FIG . 7 is a view to describe simplification of a program changed . 60 code according to an embodiment of the disclosure . The shuffle unit 120 may receive and perform shuffling of The left side of FIG . 7 illustrates a program code accord a plurality of input data , and then provide the data to the ing to the related art and the right side of FIG . 7 illustrates execution unit 130 immediately . Accordingly , the power a program code according to this disclosure . consumption for storing the shuffled data in the register file According to the related art , data stored in a vector 110 again may be reduced , and the operation speed may be 65 register file is shuffled and then stored as a vector register file improved . In addition , the size of the hardware may be again . Accordingly , the program code according to the reduced as well . related art may include instructions for shuffling , such as a sure . 20 a US 11,263,018 B2 11 12 hcat and vcat . Also , data shuffling is required for every The input instruction may include at least one of a type of cycle , and accordingly , hcat or vcat may be necessary for operation to be processed by the execution unit , an operation every cycle . method , and information on the horizontal and vertical According to this disclosure , after the data stored in the increments . plurality of register files 110 is shuffled , operations may be 5 The step of performing parallel operation in step S830 performed immediately without storing the data in the may include performing parallel operation of input data plurality of register files 110. That is , there is no need for outputted from the shuffle unit using the scalar data output shuffling instructions such as hcat and veat , and only the ted from the scalar register file . sf_set2d instruction described above is necessary . That is , According to various embodiments of the disclosure as the initial input of the instruction sf_set2d is stored as the 10 described above , the vector processor may perform shuffling shuffling method , and the plurality of register files 110 may of the input data and then perform operation without re storing , thereby improving processing speed and energy perform shuffling for data necessary for each cycle and efficiency . provide the data . Meanwhile , the methods according to various embodi According to the disclosure , parallel operation may be 15 ments may be programmed and stored in various storage performed using sf_mul or sf_mac described above , without media . Accordingly , the methods according to various using hcat or vcat for each cycle . embodiments described above may be implemented in vari FIG . 8 is a flowchart to describe a control method of a ous types of electronic apparatuses that execute the storage vector processor according to an embodiment of the disclo- medium . Specifically , a non - transitory computer readable medium First , a plurality of data are stored in each of a plurality storing a program sequentially executing the control method of register files provided in each of a plurality of SIMD may be provided . lanes , and input data used for the current cycle among a The non - transitory computer readable medium is a plurality of data is output in step S810 . By the shuffle unit , medium that semi - permanently stores data and from which a plurality of input data outputted from the plurality of 25 data is readable by a device , but not a medium that stores register files may be received , and the received plurality of data for a short time , such as register , a cache , a memory , and input data may be shuffled and output to correspond to each the like . In detail , the aforementioned various applications or of the plurality of SIMD lanes in step S820 . Then , the input programs may be stored in the non - transitory computer data outputted from the shuffle unit may be received and a readable medium , for example , a compact disc ( CD ) , a parallel operation may be performed in step S830 . 30 digital versatile disc ( DVD ) , a hard disc , a Solid State Drive Here , the step of shuffling and outputting in step S820 ( SSD ) , a blu - ray disc , a universal serial bus ( USB ) , a may include receiving a plurality of input data outputted memory card , a read only memory ( ROM ) , and the like , and may be provided . from the plurality of register files by each of a plurality of multiplexers provided in each of the plurality of SIMD lanes 35 are merely exemplary and are not to be construed as limiting The foregoing exemplary embodiments and advantages in the shuffle unit , and outputting one input data correspond the present disclosure . The present teaching can be readily ing to the lane in which the corresponding multiplexer is applied to other types of apparatuses . Also , the description provided among the plurality of received input data . of the exemplary embodiments of the present disclosure is The method may further include controlling a plurality of intended to be illustrative , and not to limit the scope of the register files and a shuffle unit for each cycle based on an 40 claims , and many alternatives , modifications , and variations input instruction . At this time , the plurality of register files will be apparent to those skilled in the art . and the shuffle unit may be controlled for a specific cycle , The invention claimed is : and then the current state may be stored . That is , when one 1. A vector processor comprising : cycle is ended , the stored current state may be updated . a plurality of register files , wherein each of the plurality Here , the step of controlling may include transmitting the 45 of register files is provided to a corresponding lane of reference register address of each of the plurality of SIMD a plurality of single instruction multiple data ( SIMD ) lanes to each of the plurality of register files , and the lanes , stores a plurality of data , and outputs input data reference register address may be an address of input data to be used in a current cycle among the plurality of which is used for the current cycle among the plurality of data ; data stored in each register file . a shuffle unit for receiving a plurality of input data In addition , the step of controlling may include transmit outputted from the plurality of register files , performing ting the shuffle information for the plurality of input data to shuffling of the received plurality of input data such that the received plurality of input data respectively the shuffle unit , and the shuffle information may be infor correspond to the plurality of SIMD lanes , and output mation on the input data to be output in each of the plurality ting the shuffled plurality of input data , wherein a of SIMD lanes . number of the shuffled plurality of input data outputted The step of controlling may include controlling the by the shuffle unit is the same as a number of the address multiplexer to provide the reference register address plurality of input data received by the shuffle unit ; for the input data to be used in the current cycle to each of an execution unit for receiving the shuffled plurality of the plurality of register files . input data outputted from the shuffle unit and perform Here , the step of controlling may include storing the ing a parallel operation on the shuffled plurality of input reference register address of each of the plurality of SIMD data ; and lanes to at least one address register and controlling the a shuffle control unit for controlling the plurality of address multiplexer to provide one of the plurality of refer- register files and the shuffle unit based on an input ence register addresses provided from the instruction decode 65 instruction , unit and at least one address registers to a corresponding wherein the shuffle unit comprises a plurality of multi register file . plexers configured to receive the plurality of input data 50 55 60 20 25 US 11,263,018 B2 13 14 outputted from the plurality of register files and output ing , by the shuffle unit , shuffling of the received plu the shuffled plurality of input data , the plurality of input rality of input data such that the received plurality of data received by the plurality of multiplexers respec- input data respectively correspond to the plurality of tively correspond to the plurality of register files , and SIMD lanes , and outputting , by the shuffle unit , the each of the plurality of multiplexers is connected to at 5 shuffled plurality of input data , wherein a number of the least one register file from among the plurality of shuffled plurality of input data outputted from the register files and configured to receive input data from shuffle unit is the same as a number of the plurality of one of the at least one connected register file , input data received by the shuffle unit ; wherein the shuffle control unit comprises an address receiving the shuffled plurality of input data outputted multiplexer configured to provide a reference register 10 from the shuffle unit and performing a parallel opera address to each of the plurality of register files , and the shuffle control unit controls the plurality of register files tion on the shuffled plurality of input data ; and controlling , by a shuffle control unit , the plurality of to output the plurality of input data based on the reference register address , register files and the shuffle unit based on an input wherein the shuffle control unit includes a register for 15 instruction , storing a current state , generates shuffle information on wherein the shuffle unit comprises a plurality of multi the plurality of input data based on at least one of the plexers configured to receive the plurality of input data input instruction and the current state , transmits the outputted from the plurality of register files and output shuffle information to the shuffle unit , and updates the the shuffled plurality of input data , the plurality of input current state after the current cycle , data received by the plurality of multiplexers respec wherein the shuffle information is information on input tively correspond to the plurality of register files , each data to be outputted from each of the plurality of SIMD of the plurality of multiplexers is connected to at least lanes , and one register file from among the plurality of register wherein the shuffle control unit controls the plurality of files and configured to receive input data from one of multiplexers to output different data each other . the at least one connected register file , and the shuffle 2. The vector processor of claim 1 , wherein each of the control unit comprises an address multiplexer , plurality of multiplexers is connected to the plurality of wherein the controlling of the plurality of register files register files , receives the plurality of input data outputted and the shuffle unit comprises : from the plurality of register files and outputs one input data controlling the address multiplexer to provide a reference corresponding to a lane of the plurality of SIMD lanes 30 register address to each of the plurality of register files , provided with a corresponding multiplexer of the plurality of and multiplexers among the received plurality of input data . controlling the plurality of register files to output the 3. The vector processor of claim wherein the reference plurality of input data based on the reference register register address is an address of input data which is used in address , the current cycle among the plurality of data . wherein the shuffle control unit includes a register for 4. The vector processor of claim 1 , wherein the shuffle storing a current state , control unit further comprises : wherein the controlling of the plurality of register files a control unit to control the address multiplexer . and the shuffle unit comprises generating shuffle infor 5. The vector processor of claim 4 , wherein the shuffle mation on the plurality of input data based on at least control unit further comprises : one of the input instruction and the current state , at least one address register to store a reference register transmitting the shuffle information to the shuffle unit , address of each of the plurality of SIMD lanes , and and updating the current state after the current cycle , wherein the control unit controls the address multiplexer wherein the shuffle information is information on input to provide one of a plurality of reference register data to be outputted from each of the plurality of SIMD addresses provided from an instruction decode unit and 45 lanes , and the at least one address register to a corresponding wherein the shuffle control unit controls the plurality of register file . multiplexers to output different data each other . 6. The vector processor of claim 1 , wherein the input 9. The control method of claim 8 , wherein the receiving instruction comprises at least one of a type of operations to of the plurality of input data comprises receiving the plu be processed by the execution unit , an operation method , 50 rality of input data outputted from the plurality of register and information on an increment in a horizontal direction files by each of the plurality of multiplexers provided in the and an increment in a vertical direction . plurality of SIMD lanes in the shuffle unit , and the output 7. The vector processor of claim 1 , further comprising : ting of the shuffled plurality of input data comprises out a scalar register file , putting one input data corresponding to a lane of the wherein the execution unit performs the parallel operation 55 plurality of SIMD lanes provided with a corresponding of the shuffled plurality of input data outputted from the multiplexer of the plurality of multiplexers among the shuffle unit using scalar data outputted from the scalar received plurality of input data , each of the plurality of register file . multiplexers being connected to the plurality of register 8. A control method of a vector processor , the control files . method comprising : 10. The control method of claim 8 , wherein the reference storing a plurality of data to each of a plurality of register register address is an address of input data which is used in files that is provided to a corresponding lane of a the current cycle among the plurality of data . plurality of single instruction multiple data ( SIMD ) 11. The control method of claim 8 , wherein the controlling lanes , and outputting input data to be used in a current of the address multiplexer comprises controlling at least one cycle among the plurality of data ; 65 address register to store a reference register address of each receiving , by a shuffle unit , a plurality of input data of the plurality of SIMD lanes and controlling the address outputted from the plurality of register files , perform- multiplexer to provide one of a plurality of reference register 35 40 60 16 US 11,263,018 B2 15 addresses provided from an instruction decode unit and the at least one address register to a corresponding register file . 12. The control method of claim 8 , wherein the input instruction comprises at least one of a type of operations to be processed by an execution unit , an operation method , and 5 information on an increment in a horizontal direction and an increment in a vertical direction . 13. The control method of claim 8 , further comprising performing the parallel operation of the shuffled plurality of input data outputted from the shuffle unit using scalar data 10 outputted from a scalar register file .