touch가 될때마다 시리얼 통신으로 254를 전송하고 싶어. 그러나 지금은 처음 눌렀을때  3개의 254가 전송되고 그 뒤부터는 touch를 해도 전송되지 않아.
module motor_top(
  input clk,
  input i_Rx_Serial,
  input m_verification,
  input touch,
  output GPIO_1,
  output GPIO_2,
  output reg [6:0] led_direct,
  output reg [6:0] led_duty,
  output reg [6:0] led_time_10,
  output reg [6:0] led_time_1,
  output o_Tx_Serial
);
reg un_touch;
always @(posedge clk)
  un_touch <= ~touch;




reg [9:0] w_data;
uart_rx
#(.CLKS_PER_BIT(434)) rx
(
  .i_Clock(clk),
  .i_Rx_Serial(i_Rx_Serial),
  .o_Rx_DV(i_run), 
  .o_Rx_Byte(w_data) 
);

wire [7:0] dumy_data = 254;
pass_fsm core(       
    .clk(clk),
    .ii_run(i_run),  
    .o_tx_DV(data_valid)
    );



 reg ok;
    always @(*) begin
        if(un_touch==1 && data_valid==1) begin
            ok<=1;
        end
        else  begin
            ok<=0;
        end
    end


   uart_tx
  #(.CLKS_PER_BIT(434)) tx
  (
   .i_Clock(clk),
   .i_Tx_DV(ok),
   .i_Tx_Byte(dumy_data), // s_TX_DATA_BITS 일때 출력으로 나갈거
   .o_Tx_Serial(o_Tx_Serial) 
   );


reg [3:0] direction;
reg [3:0] dutynumber;
reg [3:0] timenumber;
reg [3:0] timenumber_10;
reg [3:0] timenumber_1;


always @(posedge clk) begin

  if(i_run==1 && w_data<8)
    dutynumber <= w_data;
  else if(i_run==1 && w_data==8)
    direction <= 0;
  else if(i_run==1 && w_data==9)
    direction <= 1;
  else if(i_run==1 && w_data==10)
    timenumber <=0;  
  else if(i_run==1 && w_data==11)
    timenumber <=5;
  else if(i_run==1 && w_data==12)
    timenumber <=10;
  else if(i_run==1 && w_data==13)
    timenumber <=15;

end

reg [5:0]time_s;
always @(clk) begin
    timenumber_10 <= time_s/10;
    timenumber_1 <= time_s%10;
end




led_dec for_accel(
  .led1_in(direction),
  .led1_out(led_direct)
);
led_dec for_direc(
  .led1_in(dutynumber),
  .led1_out(led_duty)
);

led_dec for_time10(
  .led1_in(timenumber_10),
  .led1_out(led_time_10)
);

led_dec for_time1(
  .led1_in(timenumber_1),
  .led1_out(led_time_1)
);




accelerator ins_accelerator(
  .clk(clk),
  .verification(m_verification),
  .direction_change(direction),
  .touch_sensor(un_touch),
  .duty_number(dutynumber),
  .time_number(timenumber),
  .outvalue1(GPIO_1),
  .outvalue2(GPIO_2),
  .s(time_s)
);

endmodule

module uart_tx
  #(parameter CLKS_PER_BIT = 0)
  (
   input       i_Clock,
   input       i_Tx_DV,
   input [7:0] i_Tx_Byte, /////처리된 입력
   //output      o_Tx_Active,
   output reg o_Tx_Serial
   //output      o_Tx_Done
   );

  localparam s_IDLE         = 3'b000;
  localparam s_TX_START_BIT = 3'b001;
  localparam s_TX_DATA_BITS = 3'b010;
  localparam s_TX_STOP_BIT  = 3'b011;
  localparam s_CLEANUP      = 3'b100;

  reg [2:0]    r_SM_Main     = 0;
  reg [15:0]    r_Clock_Count = 0;
  reg [2:0]    r_Bit_Index   = 0;
  reg [7:0]    r_Tx_Data     = 0;
 // reg          r_Tx_Done     = 0;
  //reg          r_Tx_Active   = 0;

  always @(posedge i_Clock)
    begin

      case (r_SM_Main)
        s_IDLE :
          begin
            o_Tx_Serial   <= 1'b1;         // Drive Line High for Idle
            //r_Tx_Done     <= 1'b0;
            r_Clock_Count <= 0;
            r_Bit_Index   <= 0;

            if (i_Tx_DV == 1'b1)
              begin
                //r_Tx_Active <= 1'b1;
                r_Tx_Data   <= i_Tx_Byte;
                r_SM_Main   <= s_TX_START_BIT;
              end
            else
              r_SM_Main <= s_IDLE;
          end // case: s_IDLE


        // Send out Start Bit. Start bit = 0
        s_TX_START_BIT :
          begin
            o_Tx_Serial <= 1'b0;

            // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
            if (r_Clock_Count < CLKS_PER_BIT-1'b1)
              begin
                r_Clock_Count <= r_Clock_Count + 1'b1;
                r_SM_Main     <= s_TX_START_BIT;
              end
            else
              begin
                r_Clock_Count <= 0;
                r_SM_Main     <= s_TX_DATA_BITS;
              end
          end // case: s_TX_START_BIT


        // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
        s_TX_DATA_BITS :
          begin
            o_Tx_Serial <= r_Tx_Data[r_Bit_Index];

            if (r_Clock_Count < CLKS_PER_BIT-1'b1)
              begin
                r_Clock_Count <= r_Clock_Count + 1'b1;
                r_SM_Main     <= s_TX_DATA_BITS;
              end
            else
              begin
                r_Clock_Count <= 0;

                // Check if we have sent out all bits
                if (r_Bit_Index < 7)
                  begin
                    r_Bit_Index <= r_Bit_Index + 1'b1;
                    r_SM_Main   <= s_TX_DATA_BITS;
                  end
                else
                  begin
                    r_Bit_Index <= 0;
                    r_SM_Main   <= s_TX_STOP_BIT;
                  end
              end
          end // case: s_TX_DATA_BITS


        // Send out Stop bit.  Stop bit = 1
       s_TX_STOP_BIT :
          begin
            o_Tx_Serial <= 1'b1;

            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
            
              
                //r_Tx_Done     <= 1'b1;
                r_Clock_Count <= 0;
                r_SM_Main     <= s_CLEANUP;
                //r_Tx_Active   <= 1'b0;
              
          end // case: s_Tx_STOP_BIT

        // Stay here 1 clock
        s_CLEANUP :
          begin
            //r_Tx_Done <= 1'b0;
            r_SM_Main <= s_IDLE;
          end


        default :
          r_SM_Main <= s_IDLE;

      endcase
    end

  //assign o_Tx_Active = r_Tx_Active;
  //assign o_Tx_Done   = r_Tx_Done;

endmodule
`timescale 1ns / 1ps

module pass_fsm(
        input               clk,
        input               rst_n,
        input              ii_run, 
        output reg         o_tx_DV
    );

localparam IDLE      = 2'b00;
localparam RUN       = 2'b01;
localparam DONE      = 2'b10;
localparam RUN_REAL  = 2'b11;

reg [1:0]                   state;
reg [7:0]                   r_data;
reg                         r_tx_DV;

//reg                         ena; //enable for core
wire                        run_done;

always@(posedge clk) begin
        case(state)
            IDLE: begin
					 if(ii_run) begin
                    state  <= RUN;
                    o_tx_DV <= 0;
                end
					 
                else begin
                    state <=IDLE;
                    o_tx_DV <= 0;
                end
            end

            RUN: begin
                state       <= DONE;
                o_tx_DV     <= 1;
					 
            end
				
				RUN_REAL:begin
						state       <= DONE;
						o_tx_DV     <= 1;
				end
            
            DONE: begin
                state           <= IDLE;
                o_tx_DV         <= 0;
                
            end

            default: begin
                state <= IDLE;
                o_tx_DV <= 0;
            end

        endcase
end

endmodule