Hi, I can't seem to place correctly the flip flops in this carry chain implementation on my artix 7 fpga. What is the problem?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;


library UNISIM;
use UNISIM.VComponents.all;

ENTITY carry_chain IS
    generic (
        STAGES:         integer := 200;             -- Num of used Carry4 stages (CAREFUL, NOT THE NUMBER OF SINGLE SUB-STAGES INSIDE THE SLICE)
        CONFIG:         string  := "CCCC";          -- Carry4 Output configuration (ex. CCCC - CSCC - NCCC) See paper for more info.
        Xoff:           integer := 0;               -- X Offset used to place the Carry4 in a specific location in the FPGA 
        Yoff:           integer := 0                -- Y Offset used to place the Carry4 in a specific location in the FPGA
    );
    port (
        clock:          in std_logic;
        hit:            in std_logic;                                       -- Input Signal to be propagated through the carry chain
        latched_output: out std_logic_vector(( STAGES * 4 )-1 downto 0);  -- the second -1 is used cause the chain is starting from the second slice
        valid:          out std_logic                                       -- This signal is asserted when the "hit" signal starts to flow
    );                                                                      -- though the carry chain
    
    attribute dont_touch : string;
    attribute dont_touch of carry_chain : entity is "true";

END carry_chain;

ARCHITECTURE Structural OF carry_chain IS

ATTRIBUTE RLOC:     string;
ATTRIBUTE LOC:      string;
ATTRIBUTE BEL:      string;

-- Signal that stores the output of the multiplexers. It is composed of (STAGES * 4) bits
-- cause every stage has 4 multiplexers (or XORs)
SIGNAL unreg_C:         std_logic_vector((STAGES * 4)-1 DOWNTO 0);  -- Stores the bits coming from the Carry4 MUXes
SIGNAL unreg_S:         std_logic_vector((STAGES * 4)-1 DOWNTO 0);  -- Stores the bits coming from the Carry4 XORs
SIGNAL carry_output:    std_logic_vector((STAGES * 4)-1 DOWNTO 0);  -- Input to be fed to the flipflops based on CONFIG

SIGNAL CLR:             std_logic   := '0';                     -- Reset signal sent from the first stage of the carry chain to the input stage
SIGNAL TRIG:            std_logic   := '0';                     -- Signal to be propagated through the chain

---- Function to get the CONFIG value for a given substage
--function get_config_value(config_string: string; index: integer) return character is
--begin
--    return config_string(index);
--end get_config_value;

ATTRIBUTE LOC of first_C4 : label is "X" & integer'image(Xoff) & "Y0";

BEGIN

-- First Carry4 instance
first_C4: carry4
port map (
    CYINIT => TRIG,
    CI => '0',
    DI => "0000",
    S => "1111",
    CO => unreg_C(3 downto 0),
    O => unreg_S(3 downto 0)
);

-- Cycle that generates the remaining carry chain elements
carry_delay_line: FOR i IN 1 TO (STAGES - 2) GENERATE
    ATTRIBUTE LOC of next_C4 : label is "X" & integer'image(Xoff) & "Y" & integer'image(i);
    BEGIN
    next_C4 : carry4
    port map(
        CYINIT => '0',
        CI     => unreg_C(4*i-1),
        DI     => "0000",
        S      => "1111",
        CO     => unreg_C(4*(i+1)-1 DOWNTO 4*i),
        O      => unreg_S(4*(i+1)-1 DOWNTO 4*i)
    );		 	
END GENERATE;

-- SETTING UP THE DESIRED CONFIGURATION (es. CCCC-CCCC...)
-- Loop through each bit of the chain
gen_carry_output: FOR i IN 0 TO ((STAGES * 4) - 1) GENERATE
    carry_output(i) <=
    -- REPEAT CONFIG for every 4 bit
    -- 'C' or 'c' means take bit from unreg_C
    unreg_C(i) WHEN CONFIG((i MOD 4) + 1) = 'C' OR CONFIG((i MOD 4) + 1) = 'c' ELSE
    -- 'S' or 's' means take bit from unreg_S
    unreg_S(i) WHEN CONFIG((i MOD 4) + 1) = 'S' OR CONFIG((i MOD 4) + 1) = 's' ELSE
    -- 'N' or 'n' means take 0
    '0';
END GENERATE;

-- =========================================================== INPUT STAGE ================================================================
input_stage:
BLOCK
    --ATTRIBUTE RLOC OF input_reg : LABEL IS "X0Y0";
BEGIN

    -- See paper for implementation details
    input_reg: FDRE
    GENERIC MAP(
        INIT    =>  '0'
    )
    PORT MAP(
        C       =>  hit,
        R       =>  CLR,
        D       =>  '1',
        Q       =>  TRIG,
        CE      =>  '1'
    );

END BLOCK;
-- =============================================================================================================================================
-- =======================================================FLIP FLOPS FOR FIRST SLICE ===========================================================
-- =============================================================================================================================================
--first_slice: BLOCK

--ATTRIBUTE LOC OF reg_1 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_1 : LABEL IS "AFF";  -- First flip-flop
--ATTRIBUTE LOC OF reg_2 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_2 : LABEL IS "A5FF"; -- Second flip-flop
--ATTRIBUTE LOC OF reg_3 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_3 : LABEL IS "BFF";  -- Third flip-flop
--ATTRIBUTE LOC OF reg_4 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_4 : LABEL IS "B5FF"; -- Fourth flip-flop
--ATTRIBUTE LOC OF reg_5 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_5 : LABEL IS "CFF";  -- Fifth flip-flop
--ATTRIBUTE LOC OF reg_6 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_6 : LABEL IS "C5FF"; -- Sixth flip-flop
--ATTRIBUTE LOC OF reg_7 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_7 : LABEL IS "DFF";  -- Seventh flip-flop
--ATTRIBUTE LOC OF reg_8 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + 1);
--ATTRIBUTE BEL OF reg_8 : LABEL IS "D5FF"; -- Eighth flip-flop

---- These signals connect the two flip-flops together in every substage (ex. from AFF to A5FF, BFF to B5FF...)
--SIGNAL aff_to_a5ff:     std_logic_vector(STAGES - 1 DOWNTO 0) := (others => '0');
--SIGNAL bff_to_b5ff:     std_logic_vector(STAGES - 1 DOWNTO 0) := (others => '0');   
--SIGNAL cff_to_c5ff:     std_logic_vector(STAGES - 1 DOWNTO 0) := (others => '0');
--SIGNAL dff_to_d5ff:     std_logic_vector(STAGES - 1 DOWNTO 0) := (others => '0');

--BEGIN

--    -- AFF FLIP-FLOP
--    reg_1: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => carry_output(0),                     -- Signal to be taken from MUXes or Xors Based on string CONFIG(0)
--        Q       => aff_to_a5ff(0),                      -- Signal to be sent to A5FF D
--        CE      => '1'                                  -- Clock Enable, always active                 
--    );
    
--    -- SET CLR
--    CLR <= aff_to_a5ff(0);
        
--    -- A5FF FLIP-FLOP
--    reg_2: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => aff_to_a5ff(0),
--        Q       => latched_output(0),
--        CE      => '1'
--    );
    
--    -- SET VALID
--    valid <= latched_output(0);
        
        
--    -----  Second SUBSTAGE (BFF and B5FF Flip Flops) ----------------------------------------------------------------------------------------------------
        
--    -- BFF FLIP-FLOP
--    reg_3: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => carry_output(1),        -- Signal to be taken from MUXes or Xors Based on string CONFIG(1)
--        Q       =>  bff_to_b5ff(0),                     -- Signal to be sent to B5FF
--        CE      => '1'
--    );
    
--    -- B5FF FLIP-FLOP
--    reg_4: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => bff_to_b5ff(0),                      -- Signal to be taken from BFF
--        Q       => latched_output(1),       -- Signal to be sent to latched output
--        CE      => '1'
--    );
    
----------Third SUBSTAGE (CFF and C5FF FLIP FLOPS) -------------------------------------------------------------------------------------------------

    
--    -- CFF FLIP-FLOP
--    reg_5: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => carry_output(2),        -- Signal to be taken from MUXes or Xors Based on string CONFIG(2)
--        Q       => cff_to_c5ff(0),                      -- Signal to be sent to C5FF
--        CE      => '1'
--    );
    
--    -- C5FF FLIP-FLOP
--    reg_6: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => cff_to_c5ff(0),                      -- Signal to be taken from CFF
--        Q       => latched_output(2),      -- Signal to be sent to latched output
--        CE      => '1'
--    );
    
    
-------- Fourth SUBSTAGE (DFF and D5FF FLIP FLOPS) ----------------------------------------------------------------------------------------------------
    
                         
--    -- DFF FLIP-FLOP
--    reg_7: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => carry_output(3),        -- Signal to be taken from MUXes or Xors Based on string CONFIG(3)
--        Q       => dff_to_d5ff(0),                      -- Signal to be sent to D5FF
--        CE      => '1'
--    );
    
--    -- D5FF FLIP-FLOP
--    reg_8: FDRE
--    GENERIC MAP(
--        INIT    => '0'
--    )
--    PORT MAP(
--        C       => clock,
--        R       => '0',
--        D       => dff_to_d5ff(0),                      -- Signal to be taken from DFF
--        Q       => latched_output(3),      -- Signal to be sent to latched output
--        CE      => '1'
--    );

--END BLOCK;

-- =========================================================================================================================================
-- ========================================================== FLIP FLOP STAGE ==============================================================
-- =========================================================================================================================================
-- Generate two flip-flops for every Substage of the Carry4 Cell (Except the first slice of the column, used for input stage
latches: FOR i IN 1 TO (STAGES - 2)
GENERATE

--ATTRIBUTE RLOC OF ff_stage : LABEL IS "X0Y" & integer'image(i);

BEGIN
    
ff_stage: BLOCK
    -- Given the input desiderd configuration (CCCC, CSCC, CNCC, etc. ):
    -- Generate 8 flip-flops for every stage
    ATTRIBUTE LOC OF reg_1 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_1 : LABEL IS "AFF";  -- First flip-flop
    ATTRIBUTE LOC OF reg_2 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_2 : LABEL IS "A5FF"; -- Second flip-flop
    ATTRIBUTE LOC OF reg_3 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_3 : LABEL IS "BFF";  -- Third flip-flop
    ATTRIBUTE LOC OF reg_4 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_4 : LABEL IS "B5FF"; -- Fourth flip-flop
    ATTRIBUTE LOC OF reg_5 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_5 : LABEL IS "CFF";  -- Fifth flip-flop
    ATTRIBUTE LOC OF reg_6 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_6 : LABEL IS "C5FF"; -- Sixth flip-flop
    ATTRIBUTE LOC OF reg_7 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_7 : LABEL IS "DFF";  -- Seventh flip-flop
    ATTRIBUTE LOC OF reg_8 : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff + (i + 1));
    ATTRIBUTE BEL OF reg_8 : LABEL IS "D5FF"; -- Eighth flip-flop
    
    SIGNAL aff_to_a5ff, bff_to_b5ff, cff_to_c5ff, dff_to_d5ff: std_logic;

    BEGIN
    ------ First SUBSTAGE (AFF and A5FF Flip Flops) -----------------------------------------------------------------------------------------------------  
                                                
    -- AFF FLIP-FLOP
    reg_1: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => carry_output( 4 * i),                -- Signal to be taken from MUXes or Xors Based on string CONFIG(0)
        Q       => aff_to_a5ff,                         -- Signal to be sent to A5FF D
        CE      => '1'                                  -- Clock Enable, always active                 
    );
        
    -- A5FF FLIP-FLOP
    reg_2: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => aff_to_a5ff,
        Q       => latched_output( 4 * i ),
        CE      => '1'
    );
         
    
-----  Second SUBSTAGE (BFF and B5FF Flip Flops) ----------------------------------------------------------------------------------------------------
        
    -- BFF FLIP-FLOP
    reg_3: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => carry_output(( 4 * i ) + 1 ),        -- Signal to be taken from MUXes or Xors Based on string CONFIG(1)
        Q       =>  bff_to_b5ff,                        -- Signal to be sent to B5FF
        CE      => '1'
    );
    
    -- B5FF FLIP-FLOP
    reg_4: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => bff_to_b5ff,                         -- Signal to be taken from BFF
        Q       => latched_output(( 4 * i ) + 1),       -- Signal to be sent to latched output
        CE      => '1'
    );
    
--------Third SUBSTAGE (CFF and C5FF FLIP FLOPS) -------------------------------------------------------------------------------------------------

    
    -- CFF FLIP-FLOP
    reg_5: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => carry_output(( 4 * i ) + 2 ),        -- Signal to be taken from MUXes or Xors Based on string CONFIG(2)
        Q       => cff_to_c5ff,                         -- Signal to be sent to C5FF
        CE      => '1'
    );
    
    -- C5FF FLIP-FLOP
    reg_6: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => cff_to_c5ff,                         -- Signal to be taken from CFF
        Q       => latched_output(( 4 * i ) + 2 ),      -- Signal to be sent to latched output
        CE      => '1'
    );
    
    
------ Fourth SUBSTAGE (DFF and D5FF FLIP FLOPS) ----------------------------------------------------------------------------------------------------
    
                         
    -- DFF FLIP-FLOP
    reg_7: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => carry_output(( 4 * i ) + 3 ),        -- Signal to be taken from MUXes or Xors Based on string CONFIG(3)
        Q       => dff_to_d5ff,                         -- Signal to be sent to D5FF
        CE      => '1'
    );
    
    -- D5FF FLIP-FLOP
    reg_8: FDRE
    GENERIC MAP(
        INIT    => '0'
    )
    PORT MAP(
        C       => clock,
        R       => '0',
        D       => dff_to_d5ff,                         -- Signal to be taken from DFF
        Q       => latched_output(( 4 * i ) + 3 ),      -- Signal to be sent to latched output
        CE      => '1'
    );

END BLOCK;
END GENERATE; 
-- ====================================================  END FLIP FLOP STAGE ===============================================================

-- Set CLR and valid signals
CLR <= latched_output(0);
valid <= latched_output(0);

END Structural;