i have the following vhdl code which implements a finite state machine. i am not very proud of it and i wonder what would it take to convert it to a synchronous state machine. LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
use STD.textio.all;

entity key_fsm_c is 
	port (clk: in std_logic;
	 rst: in std_logic; -- synch, high
	 left, right, up, down, center: in std_logic; -- keys
	 data_out: out std_logic_vector(31 downto 0):= (others => '0');
	 cntr_en: out std_logic;
	 cntr_rst: out std_logic;
	 cntr_load: out std_logic;
	 edit_en_out: out std_logic
	 );
end entity;

architecture Behavioral of key_fsm_c is
    type state_type is (idle, start, stop, reset, load, edit, inc_val, dec_val, inc_pos, dec_pos);
    signal c_state, n_state: state_type;
begin
    proc_fsm: process(c_state, left, right, up, down, center) 
	variable position: integer := 0;
	variable act_num: integer := 0;
	variable old_pos: integer := 0;
	variable old_num: integer := 0;
	variable is_begin: integer := 1;
	variable act_frag: std_logic_vector(3 downto 0);
	variable tmp: std_logic_vector(31 downto 0) := (others => '0');
	begin
		if (is_begin = 1) then
			cntr_en <= '0';
			is_begin := 0;
		end if;
		--cntr_en <= '0';
		case c_state is
		when idle =>
			n_state <= idle;
			cntr_rst <= '0';
			cntr_load <= '0';
			if right='1' then 
				n_state <= start;
			end if;
			if left = '1' then 
				n_state <= stop;
			end if;
			if down = '1' then 
				n_state <= reset;
			end if;
			if up = '1' then 
				n_state <= load;
			end if;
			if center = '1' then 
				n_state <= edit;
			end if;
		when start => 
			cntr_en <= '1';
			n_state <= idle;
		when stop => 
			cntr_en <= '0';
			n_state <= idle;
		when reset => 
			cntr_rst <= '1';
			n_state <= idle;
		when load =>
			cntr_load <= '1';
			edit_en_out <= '0';
			--data_out <= tmp;
			n_state <= idle;
		when edit =>
			old_pos := position;
			old_num := act_num;
			n_state <= edit;
			edit_en_out <= '1';
			if right = '1' then 
				n_state <= dec_pos;
			end if;
			if left = '1' then 
				n_state <= inc_pos;
			end if;
			if down = '1' then 
				n_state <= dec_val;
			end if;
			if up = '1' then 
				n_state <= inc_val;
			end if;
			if center = '1' then 
				n_state <= load;
			end if;
		when dec_pos => 
			if old_pos >= 1 then
				position := old_pos - 1;
			else
				position := 7;
			end if;
			act_frag := tmp(4*(position+1)-1 downto 4*position);
			act_num := to_integer(unsigned(act_frag));
			n_state <= edit;
		when inc_pos => 
			if old_pos <= 6 then
				position := old_pos + 1;
			else
				position := 0;
			end if;
			act_frag := tmp(4*(position+1)-1 downto 4*position);
			act_num := to_integer(unsigned(act_frag));
			n_state <= edit;
		when dec_val => 
			if old_num >= 1 then
				act_num := old_num - 1;
			else
				act_num := 9;
			end if;
			act_frag := std_logic_vector(to_unsigned(act_num, 4));
			tmp(4*(position+1)-1 downto 4*position) := act_frag;
			n_state <= edit;
		when inc_val =>
			if old_num <= 8 then
				act_num := old_num + 1;
			else 
				act_num := 0;
			end if;
			act_frag := std_logic_vector(to_unsigned(act_num, 4));
			tmp(4*(position+1)-1 downto 4*position) := act_frag;
			n_state <= edit;
		end case;
		data_out <= tmp;
    end process;
	
	proc_memory: process (clk, rst)
	begin
        if rst = '1' then 
            c_state <= idle;
        elsif rising_edge(clk) then
            c_state <= n_state;
        end if;
	end process;

end Behavioral;