fix the error in this code 
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity WashingMachineController0 is
    port (
        userProg : in STD_LOGIC_VECTOR(4 downto 0);
        clk_in : in STD_LOGIC;
        reset : in STD_LOGIC;
        start : in STD_LOGIC;
        sevseg_data : out STD_LOGIC_VECTOR(6 downto 0);
        sevseg_driver : out STD_LOGIC_VECTOR(7 downto 0);
        state : out STD_LOGIC_VECTOR(1 downto 0);
        clk_out : out STD_LOGIC
    );
end entity WashingMachineController0;

architecture Behavioral of WashingMachineController0 is
    constant COUNTER_MAX : integer := 9999;  -- Maximum counter value for display
    constant PROGRAMS : integer := 5;        -- Total number of programs
    constant WASH_CYCLES : integer := 4;     -- Number of wash cycles in each program
    constant SPIN_CYCLES : integer := 5;     -- Number of spin cycles in each program
    constant RINSE_CYCLES : integer := 2;    -- Number of rinse cycles in each program
    constant CLOCK_DIVIDER : integer := 500; -- Divide original clock frequency by 500

    type ProgramType is (COTTON, RAPID, SLOW, DRAIN, WHITE);
    signal program : ProgramType;

    signal counter : integer range 0 to COUNTER_MAX;
    signal zero : STD_LOGIC := '0';
    signal nextState : STD_LOGIC_VECTOR(1 downto 0);
    signal currentCycle : STD_LOGIC_VECTOR(1 downto 0);
    signal displayValue : STD_LOGIC_VECTOR(6 downto 0);
    signal displayDigit : STD_LOGIC_VECTOR(3 downto 0);
    signal displayDriver : STD_LOGIC_VECTOR(7 downto 0);

    signal clk_div_counter : integer range 0 to CLOCK_DIVIDER - 1;
    signal clk_out_internal : STD_LOGIC := '0';

begin

    -- Program selection logic
    process(userProg)
    begin
        case userProg is
            when "10000" =>
                program <= COTTON;
            when "01000" =>
                program <= RAPID;
            when "00100" =>
                program <= SLOW;
            when "00010" =>
                program <= DRAIN;
            when "00001" =>
                program <= WHITE;
            when others =>
                program <= COTTON;  -- Default program
        end case;
    end process;

    -- Clock divider process
    process (clk_in, reset)
    begin
        if reset = '1' then
            clk_div_counter <= 0;
            clk_out_internal <= '0';
            clk_out <= '0';
        elsif rising_edge(clk_in) then
            if clk_div_counter = CLOCK_DIVIDER - 1 then
                clk_div_counter <= 0;
                clk_out_internal <= not clk_out_internal;
            else
                clk_div_counter <= clk_div_counter + 1;
            end if;
        end if;
    end process;

    -- State transition logic
    process(clk_out_internal, reset)
    begin
        if reset = '1' then
            counter <= 0;
            zero <= '0';
            currentCycle <= "00";
            nextState <= "00";
        elsif rising_edge(clk_out_internal) then
            if start = '1' then
                counter <= COUNTER_MAX;
                zero <= '0';
                currentCycle <= "00";
                case program is
                    when COTTON =>
                        nextState <= "00";
                    when RAPID =>
                        nextState <= "00";
                    when SLOW =>
                        nextState <= "00";
                    when DRAIN =>
                        nextState <= "01";
                    when WHITE =>
                        nextState <= "00";
                    when others =>
                        nextState <= "00";
                end case;
            elsif zero = '1' then
                case currentCycle is
                    when "00" =>
                        nextState <= "01";
                    when "01" =>
                        nextState <= "10";
                    when "10" =>
                        nextState <= "11";
                    when "11" =>
                        nextState <= "11";
                    when others =>
                        nextState <= "11";
                end case;
            else
                nextState <= nextState;
            end if;
        end if;
    end process;

    -- Counter and zero logic
    process(counter, nextState)
    begin
        if counter = 0 then
            zero <= '1';
        else
            zero <= '0';
        end if;

        case nextState is
            when "00" =>
                if zero = '1' then
                    counter <= WASH_CYCLES - 1;
                else
                    counter <= counter - 1;
                end if;
            when "01" =>
                if zero = '1' then
                    counter <= SPIN_CYCLES - 1;
                else
                    counter <= counter - 1;
                end if;
            when "10" =>
                if zero = '1' then
                    counter <= RINSE_CYCLES - 1;
                else
                    counter <= counter - 1;
                end if;
            when "11" =>
                counter <= 0;
            when others =>
                counter <= 0;
        end case;
    end process;

    -- Display logic
    process(clk_out_internal, reset)
    begin
        if reset = '1' then
            displayDigit <= "0000";
            displayDriver <= "11111111";
        elsif rising_edge(clk_out_internal) then
            case displayDigit is
                when "0000" =>
                    displayValue <= "0011111"; -- Display 'C'
                when "0001" =>
                    displayValue <= "0110110"; -- Display 'O'
                when "0010" =>
                    displayValue <= "0111001"; -- Display 'T'
                when "0011" =>
                    displayValue <= "0100111"; -- Display 'T'
                when "0100" =>
                    displayValue <= "0111011"; -- Display 'O'
                when "0101" =>
                    case program is
                        when COTTON =>
                            displayValue <= "0011111"; -- Display 'C'
                        when RAPID =>
                            displayValue <= "0110110"; -- Display 'R'
                        when SLOW =>
                            displayValue <= "0111001"; -- Display 'S'
                        when DRAIN =>
                            displayValue <= "1011101"; -- Display 'D'
                        when WHITE =>
                            displayValue <= "1000110"; -- Display 'W'
                        when others =>
                            displayValue <= "0011111"; -- Default display 'C'
                    end case;
                when others =>
                    displayValue <= "0011111"; -- Default display 'C'
            end case;

            displayDigit <= std_logic_vector(unsigned(displayDigit) + 1);
            if displayDigit > "1001" then
                displayDigit <= "0000";
            end if;

            displayDriver <= std_logic_vector(not unsigned("0")) xor std_logic_vector('1' & not (2**to_integer(unsigned(displayDigit))));



        end if;
    end process;

    -- Output assignment
    sevseg_data <= displayValue;
    sevseg_driver <= displayDriver;
    state <= nextState;
    clk_out <= clk_out_internal;

end architecture Behavioral;