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PUBLICATIONS
2023

[ACML, Major] Seung Tae Lee, Jong Hwan Ko, and Seokin Hong, "Facto-CNN: Memory-Efficient CNN Training with Low-rank Tensor Factorization and Lossy Tensor Compression", The 15th Asian Conference on Machine Learning, İstanbul, Turkey, November 2023 (Acceptance Rate: 35%).

[ICCD, Major] Seongwook Kim, Gwangeun Byeon, Sihyung Kim, Hyungjin Kim, and Seokin Hong, "Conveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity", The 41st IEEE International Conference on Computer Design, Washington DC, USA, November 2023 (Acceptance Rate: 28%).

[PACT, Top-tier] Gwangeun Byeon, Seungtae Lee, Seongwook Kim, Yongjun Kim, Prashant J. Nair, and Seokin Hong, "SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs", The 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (Poster), Vienna, Austria, October 2023.

[ISOCC] Gwangeun Byeon, Seongwook Kim, and Seokin Hong, "Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers", The 20th International SoC Conference (ISOCC 2023), Jeju, Korea, October 2023.

[ITC-CSCC] Seongwook Kim, Yongjun Kim, Gwangeun Byeon, and Seokin Hong, "CAESAR: A CNN Accelerator Exploiting Sparsity And Redundancy Pattern", The 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jeju, Korea, June 2023.

[ITC-CSCC] Hyungjin Kim and Seokin Hong, "Why Address Translation Matter?: Analyzing Page Access Patterns in NAND Flash-based SSDs", The 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jeju, Korea, June 2023.

[ITC-CSCC] Joseph Woo, Seungtae Lee, Seongwook Kim, Gwangeun Byeon, and Seokin Hong, "In-Cache Processing with Power-of-Two Quantization for Fast CNN Inference on CPUs", The 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jeju, Korea, June 2023.

[DAC, Top-tier] Yongjun Kim, Seongwook Kim, Yujin Kim, Gwangeun Byeon, Prashant J. Nair, and Seokin Hong, "CRAN: A Computational Redundancy-aware Accelerator for Convolutional Neural Networks", 2023 Design Automation Conference (DAC'23) (Poster), San Francisco, California, USA, July 2023.

[SCIE] Awais Saeed, Ubaid U. Fayyaz, Ahsan Tahir, Seokin Hong and Tayyeb Mahmood, "On the Positional Single Error Correction and Double Error Detection in Racetrack Memories," in IEEE Access.

2022

[SCIE] Osang Kwon, Yongho Lee, and Seokin Hong, "Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation", accepted to IEEE Access, in IEEE Access, vol. 10, pp. 114552-114565, 2022.

[ICCE-ASIA] Osang Kwon, Yongho Lee, and Seokin Hong, "Virtual PTE Storage: Repurposing Last-level Cache to Accelerate Address Translation for Big Data Workloads", 2022 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), Yeosu, Korea, Republic of, 2022, pp. 1-5.

[SCIE] MinGu Kang, Sang Min Hyun, Tae Hee Han, Jungrae Kim, and Seokin Hong, "On-the-fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks", in IEEE Access, vol. 10, pp. 79730-79746, 2022.

[SCIE] Yongjun Kim, Yuze Chen, Yongho Lee, Limei Peng, and Seokin Hong, "Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches", in IEEE Access, vol. 10, pp. 29419-29431, 2022.

[DAC, Top-tier] Yongjun Kim, KwangEun Byun, and Seokin Hong, "Constructing Large Buffers with Heterogeneous STT-RAM Cells for DNN Accelerators", 2022 Design Automation Conference (DAC'22) (Poster), San Francisco, California, USA, July 2022.

[DAC, Top-tier] Yongho Lee, Osang Kwon, and Seokin Hong, "Don't Open Row: Rethinking Row Buffer Policy for Improving Performance of Non-Volatile Memories", 2022 Design Automation Conference (DAC'22), San Francisco, California, USA, July 2022.

[SCIE] Beomjun Kim, Yongtae Kim, Prashant Nair, and Seokin Hong, "Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches", Electronics 11, no. 2: 240.

2021

[SCIE] Mukhammed Garifulla, Juncheol Shin, Chanho Kim, Won Hwa Kim, Hye Jung Kim, Jaeil Kim, and Seokin Hong, "A Case Study of Quantizing Convolutional Neural Networks for Fast Disease Diagnosis on Portable Medical Devices", Sensors 22, no. 1: 219.

[SCIE] Jinkwon Kim, Seokin Hong, Jeongkyu Hong, and Soontae Kim, "CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems," in IEEE Transactions on Computers, vol. 70, no. 7, pp. 1132-1145, 1 July 2021.

[KCI] Yongho Lee, Osang Kwon, Kwangeun Byun, Yongjun Kim, and Seokin Hong, "Exploiting Hardware Events to Reduce Energy Consumption of HPC Systems", Journal of The Korea Society of Computer and Information, Volume 26 Issue 8, pp.1-11, 2021.

[ICEIC] Yuze Chen, and Seokin Hong, "Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches", Jeju, South Korea, January 31, 2021.

[Domestic Conference] Seungtae Lee, Junhyuk Park, and Seokin Hong "LSTM-based Data Prefetcher", in Proc. of Korea Software Congress (KSC), Dec 2021, Korea.

2020

[ICCD, Major] Beomjun Kim, Prashant J. Nair and Seokin Hong, "ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches," 2020 IEEE 38th International Conference on Computer Design (ICCD), Hartford, CT, USA, 2020.

[KCI] Seokin Hong, "Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches", Journal of the Korea Society of Computer and Information, Volume 25 Issue 3, pp.1-9, 2020.

[KCI] Seokin Hong, "Dynamic Rank Subsetting with Data Compression", Journal of the Korea Society of Computer and Information, Volume 25 Issue 4, pp.1-9, 2020.

2019

[MICRO, Top-tier] Seokin Hong, Bulent Abali, Alper Buyuktosunoglu, Michael Healy, and Prashant J. Nair, "Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads", IEEE/ACM International Symposium on Microarchitecture (MICRO'19), Columbus, OH, USA, 2019.

[SCIE] Wonyoung Lee, Mincheol Kang, Seokin Hong, Soontae Kim, "Inter-Page-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages", IEEE Transactions on Very Large Scale Integration Systems (TVLSI),  Volume: 27 , Issue 9, Sept. 2019, pp. 2033 - 2045.

[ASPLOS, Top-tier] Tian Jin and Seokin Hong, "Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '19), New York, NY, USA, 2019.

[Domestic Conference] Chanhui Seok, Seokin Hong, "Analyzing the Performance Overhead of Secure Memory", in Proc. of Korea Software Congress (KSC), Dec 2019, Korea.

[Domestic Conference] KwangEun Byun, Seokin Hong, "Performance Characterization of STAR RNA-seq aligner on Multi-core Processor", in Proc. of Korea Software Congress (KSC), Dec 2019, Korea.

2018

[MICRO, Top-tier] Seokin Hong, Prashant J. Nair, Bulent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, and Michael Healy, "Attache: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads", IEEE/ACM International Symposium on Microarchitecture (MICRO), Fukuoka, Japan, Oct., 2018.

2017

[MEMSYS] Michael Healy and Seokin Hong, "CramSim: Controller and Memory Simulator", International Symposium on Memory Systems(MEMSYS), Washington DC, USA, 2017.

[HPCA, Top-tier] Yebin Lee, Hyeonggyu Kim, Seokin Hong, and Soontae Kim, "Partial Row Activation for Low-Power DRAM System", IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, 2017.

2016

[SCI] Seokin Hong, Soontea Kim, "Designing A Resilient L1 Cache Architecture to Process Variation-induced Access-time Failures", IEEE Transactions on Computers, Volume 65, Number 10, Oct. 2016, pp. 2999-3012.

2015

[SCI] Seokin Hong, Soontea Kim, "A Low-cost Mechanism Exploiting Narrow-width Values for Tolerating Hard Faults in ALU", IEEE Transactions on Computers, Volume 64, Number 9, Sep. 2015, pp. 2433-2446.

[SCI] Tayyeb Mahmood, Seokin Hong, Soontae Kim, "Ensuring cache reliability and energy scaling at near-threshold voltage with Macho", IEEE Transactions on Computers, Volume 64, Number 6, Jun. 2015, pp. 1694-1706.

2014

[ICCD, Major] Seokin Hong, Jongmin Lee, Soontae Kim, "Ternary Cache: Three-valued MLC STT-RAM Caches", IEEE International Conference on Computer Design (ICCD), Seoul, Korea, Oct. 19-22, 2014.

2013

[DATE, Major] Seokin Hong, Soontae Kim, "AVICA: An Access-time Variation Insensitive L1 Cache Architecture", Design Automation and Test in Europe Conference (DATE), Grenoble, France, March 18-22, 2013.

[HPCA, Top-tier] Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee, "Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power", IEEE International Symposium on High Performance Computer Architecture (HPCA), Shenzhen, China, Feb., 2013.

[HPCA, Top-tier] Tayyeb Mahmood, Soontae Kim, Seokin Hong, "Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling", IEEE International Symposium on High Performance Computer Architecture(HPCA), Shenzhen, China, 2013.

2011

[MICRO, Top-tier] Soontae Kim, Jesung kim, Jongmin Lee, Seokin Hong, "Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits", IEEE/ACM International Symposium on Microarchitecture (MICRO), Brazil, Dec. 3-7, 2011.

[ISLPED, Major] Jongmin Lee, Seokin Hong, and Soontae Kim, "TLB Index-based Tagging for Cache Energy Reduction", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED),Fukuoka, Japan, Aug. 1-3, 2011. 

2010

[ICCD, Major] Seokin Hong and Soontae Kim, "Lizard: energy-efficient hard fault detection, diagnosis and isolation in the ALU", IEEE International Conference on Computer Design (ICCD), Amsterdam, Netherlands, Oct. 3-6, 2010. 

2009

[ISVLSI] Seokin Hong, Soontae Kim, "TEPS: Transient error protection utilizing sub-word parallelism", IEEE computer Society Annual International Symposium on VLSI (ISVLSI), Tampa, FL, USA, May 13-15, 2009.


SKKU COMPASS LAB
Department of Electrical and Computer Engineering, SKKU