标题：复杂SoC设计
复杂SoC设计（英文版)
丛书名： 经典原版书库 
作　　者： （美）罗恩 著
出 版 社： 机械工业出版社
出版时间： 2005-9-1 
版　　次： 1 
页　　数： 453 
开　　本： 16
印　　次： 1
纸　　张： 胶版纸
I S B N ： 9787111171935
包　　装： 平装
所属分类： 图书 >> 计算机/网络 >> 计算机理论 
定价：￥55.00
内容简介
本书利用Tensilica公司的Xtensa结构和TIE语言，系统地阐明了以处理器为核心进行设计的问题、机遇和挑战。Rowen介绍了一种全新的设计方法，然后介绍了其基本技术：处理器配置、扩展、硬件/软件协同生成、多处理器划分/通信等。
内容摘要
●为什么可扩展的处理器是必需的：当前设计方法有什么缺点。 
●将可扩展的处理器结构与传统的处理器及硬连线逻辑电路相比较。 
●延迟、吞吐率、并行功能的协调、硬件互连选择、设计复杂度的管理等问题。 
●针对嵌入式系统的多处理器SoC结构。 
●从软件和硬件开发者角度观察的任务设计。 
●先进的技术：实现复杂的状态机、任务-任务之间的同步、功率优化等。
作者简介
Chris Rowen博士 Tensilica公司 (在高产量系统中，该公司在使用专用微处理器的自动生成方面居于领先地位) 的总裁、CEO和创始人。他在斯坦福大学参与了RISC结构的最初研发工作，帮助创建了MIPS Computer Systems公司，并曾在Synopsys公司任Design Reuse Group (设计复用集团) 的副总裁和总经理。他拥有斯坦福大学的电气工程学博士学位。
图书目录
1. The Case for a New SOC Design Methodology
1.1 The Age of Megagate SOCs
1.2 The Fundamental Trends of SOC Design
1.3 What’s Wrong with Today’s Approach to SOC Design?
1.4 Preview: An Improved Design Methodology for SOC Design
1.5 Further Reading
2. SOC Design Today
2.1 Hardware System Structure
2.2 Software Structure
2.3 Current SOC DesignFlow
2.4 The Impact of Semiconductor Economics
2.5 Six Major Issues in SOC Design
2.6 Further Reading.
3. A New Look at SOC Design
3.1 Accelerating Processors for Traditional Software Tasks
3.2 Example: Tensilica Xtensa Processors for EEMBC Benchmarks
3.3 System Design with Multiple Processors
3.4 New Essentials of SOC Design Methodoloy
3.5 Addressing the Six Problems
3.6 Further Reading
4. System-Level Design of Complex SOCs 
4.1 Complex SOC System Architecture Opportunities
4.2 Major Decisions in Processor-Centric SOC Organization
4.3 Communication Design = Software Mode + Hardware　Interconnect
4.4 Hardware Interconnect Mechanisms
4.5 Performance-Driven Communication Design
4.6 The SOC Design Flow
4.7 Non-Processor Building Blocks in Complex SOC
4.8 Implications of Processor-Centric SOC Architecture
4.9 Further Reading
5. Configurable Processors: A Software View
5.1 Processor Hardware/Software Cogeneration
5.2 The Process of Instruction Definition and Application Tuning
5.3 The Basics of Instruction Extension
5.4 The Programmer’s Mode
5.5 Processor Performance Factors
5.6 Example: Tuning a Large Task
5.7 Memory-System Tuning
5.8 Long Instruction Words
5.9 Fully Automatic Instruction-Set Extension
5.10 Further Reading
6. Configurable Processors: A Hardware View
6.1 Application Acceleration: A Common Problem
6.2 Introduction to Pipelines and Processors
6.3 Hardware Blocks to Processors
6.4 Moving from Hardwired Engines to Processors
6.5 Designing the Processor Interface
6.6 A Short Example: ATM Packet Segmentation and Reassembly
6.7 Novel Roles for Processors in Hardware Replacement
6.8 Processors, Hardware Implementation, and Verification Flow
6.9 Progress in Hardware Abstraction
6.10 Further Reading
7. Advanced Topics in SOC Design
7.1 Pipelining for Processor Performance
7.2 Inside Processor Pipeline Stalls
7.3 Optimizing Processors to Match Hardware
7.4 Multiple Processor Debug and Trace
7.5 Issues in Memory Systems
7.6 Optimizing Power Dissipation in Extensible Processors
7.7 Essentials of TIE
7.8 Further Reading
8. The Future of SOC Design: The Sea of Processors
8.2 Why Is Software Programmability So Central?
8.3 Looking into the Future of SOC
8.4 Processor Scaling Model
8.5 Future Applications of Complex SOCs
8.6 The Future of the Complex SOC Design Process
8.7 The Future of the Industry
8.8 The Disruptive-Technology View
8.9 The Long View
8.10 Further Reading
Index