标题：边计年
著作
出版著作有《数字系统计算机辅助设计》、《数字系统设计自动化》、《超大规模集成电路计算机辅助设计技术》等。译著有《VHDL简明教程》、《数字逻辑与VHDL设计》、《嵌入式系统的描述与设计》等。
研究方向
计算机与超大规模集成电路计算机辅助设计(ICCAD)或称电子设计自动化(EDA)领域中，系统与行为级的设计方法和软件工具的研究。目前的研究重点是以片上系统SOC（System on a chip）为对象的软硬件协同设计与协同验证、体系结构与接口综合、与布图结合的高层次与逻辑综合，以及集成电路芯片物理设计算法的研究。目前的在研项目有：
1.国家自然科学基金重大计划面上项目（项目负责人）：多目标自适应粒度的系统级划分与接口综合算法研究；
2.国家自然科学基金重点项目(合作负责人)：SOC设计的关键技术研究及传导语音SOC系统实现；
3.国家自然科学基金重大计划面上项目（合作负责人）：面向SOC设计的高层次综合与布图规划结合技术研究；
4. 973项目（项目负责人）：延长摩尔定律的微处理芯片新原理、新结构与新方法研究：高效率的处理芯片的设计、验证与测试。
发表论文
Ming Zhu,Jinian Bian,Weimin Wu, “A Novel Collaborative Scheme of Simulation and Model Checking for Property Verification”，will appear in: Computers in Industry，SCI，EI2002
Cin-Ngai Sze，Wangning Long，Yu-Liang Wu，Jinian Bian，“Accelerating Logic Rewriting Using Implication Analysis”，In Japan：Transactions on Fundamentals of Electronics，Communications and Computer Sciences (IEICE)，E85-A(12)，2002.12，2725-2736，SCI 626XX，EI 03117394401，INSPEC 7553316
Wu Qiang，Bian Ji-Nian，Xue Hong-Xi，“Scheduling with Resource Allocation for Design Space Exploration in System-level Synthesis”(In English)，Journal of Software
¨    Weiwei Zheng, Weimin Wu, Jinian Bian, “RTL Satisfiability Solving and Property Checking Based on Linear Programming” (In Chinese), Journal of Computer Aided Design and Graphics. (郑伟伟，吴为民，边计年，“基于LP的RTL可满足性求解和性质检验”，计算机辅助设计与图形学学报)
ZHU Ming, BIAN Ji-Nian, Wu Wei-Min, “CoSAM: a Collaborative Verification System of Functional Simulation and Model Checking” (In Chinese) Computer Integrated Manufactory System. (朱 明，边计年，吴为民，“功能模拟与形式验证相结合的系统级协同验证系统CoSAM”，计算机集成制造系统（CIMS）)
2005
Haili Wang, Jinian Bian, Zhihui Xiong, Sikun Li, Jihua Chen, “Hierarchical communication model for interface synthesis in system-on-chip design” (In Chinese)，Journal of Computer-Aided Design and Computer Graphics，17（8），2005.8，1803-1808，EI 05359331579. (王海力，边计年，熊志辉，李思昆，陈吉华，“SoC接口综合的层次化通信模型”，计算机辅助设计与图形学学报，17（8），2005.8，1803-1808)
¨    Zhihui Xiong, Sikun Li, Jihua Chen, Haili Wang, Jinian Bian, “Co-design environment supporting platform-based system-on-chip design methodology”, (In Chinese), Journal of Computer-Aided Design and Computer Graphics，17(7)，2005.7，1401-1406，EI 05319278319. (熊志辉，李思昆，陈吉华，王海力，边计年，“支持平台设计方法的系统芯片协同设计环境”，计算机辅助设计与图形学学报，17(7)，2005.7，1401-1406)
¨    ZHU Ming, BIAN Jinian, WU Weimin, “Property classification for system verification on CDFG structure” (In Chinese)，Computer Engineering，31(10)，2005.5，48-50，EI 05249160987 (朱明，边计年，吴为民，“基于CDFG和OVL的系统验证性质分类”，计算机工程，31(10)，2005.5，48-50)
¨    赵康，边计年，吴强，薛宏熙，“C语言系统描述的HCDFG-II实现”，计算机工程与科学 27(4)，2005.4，80-83
¨    刘志鹏，边计年，王云峰，薛宏熙，“面向SOC系统设计的层次化CDFG的扩展”，计算机工程与科学 27(4)，2005.4，46-48，95
¨    Qiang Wu, Yunfeng Wang, Jinian Bian, Hongxi Xue, “Granularity transformations based on a new CDFG format for granularity selection in hardware-software partitioning” (In Chinese), Journal of Computer-Aided Design and Computer Graphics，17(3)，2005.3，387-393，EI 05169051874 (吴强，王云峰，边计年，薛宏熙: “软硬件划分中基于一种新的层次化控制数据流图的粒度变换”，计算机辅助设计与图形学学报,17(3)，2005.3，387-393)
2004
¨    Zhihui Xiong, Sikun Li, Jihua Chen, Haili Wang, Jinian Bian, “Hierarchical platform-based SoC system design method”，Acta Electronica Sinica，32(11)，2004.11，1813-1819，EI 05048806862(熊志辉，李思昆，陈吉华，王海力，边计年，“一种基于层次平台的SoC系统设计方法”, 电子学报, 32(11)，2004.11，1813-1819)
¨    “Multi-way hardware-software partitioning algorithm based on abstract architecture template” (In Chinese)，Journal of Computer Aided Design & Computer Graphics，16(11)，2004.11，1562-1567，EI 05038790248，INSPEC 8353409（吴强，边计年，薛宏熙，“ATMP: 基于抽象体系结构模板的多路软硬件划分算法”，计算机辅助设计与图形学学报，16(11)，2004.11，1562-1567）
¨    Yawen Niu, Qiang Wu, Jinian Bian, Hongxi Xue, “HCDFG-II - A representation of control/data flow graph for C language system specification”(In Chinese)，Journal of Computer Aided Design & Computer Graphics，16(11)，2004.11，1547-1552，EI 05028786279，INSPEC 8334598（牛亚文，边计年，吴强，薛宏熙， “HCDFG-II——面向C语言系统描述的控制/数据流图表示”，计算机辅助设计与图形学学报，16(11)，2004.11，1547-1552）
¨    Heng Hu，Hong-Xi Xue and Ji-nian Bian，“HSM2：A New Heuristic State Minimization Algorithm for Finite State Machine”(In English)，Journal of Computer Science and Technology (JCST)，19(5)，2004.9，729-733，SCI 857RY，EI 04428412745，INSPEC 8312012
2003
¨    聂江波，边计年，薛宏熙，吴为民，朱明，“基于模块的层次化模型判别”，微电子学与计算机 2003.12 64-67 
¨    曹秉超，边计年，“顺序蕴含图的状态编码方法”，计算机工程与应用 39(30)，2003.10 79-81 
¨    朱明，边计年，薛宏熙 软硬件协同验证系统平台间通讯设计，计算机工程与应用 39(27)，2003.9 122-124
2002
¨    朱明，边计年，薛宏熙，扩展的高层次行为描述内部模型，计算机工程与应用，38(16)，2002，204-206 
¨    赵建洲，朱明，边计年，薛宏熙 SOC系统中C到VHDL的转换，计算机工程与应用 38(16)，2002，12，188-190 
¨    刘建华，杨勋，边计年，薛宏熙，“嵌入系统中断控制器的设计”，计算机工程与应用 38(1)，2002，1，125-127 
2001
¨    杨勋，边计年，洪先龙，薛宏熙，“面向片上型系统软硬件协同验证平台的研制”，软件学报Journal of Software，12(增刊)，2001.6，202-207，EI 02036826714
¨    范轶平，贝劲松，边计年，薛宏熙，洪先龙，“一个有效的针对同步时序电路VHDL设计的模型判别器: VERIS”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics，13(6)，2001.6，485-489，EI 01336615796，INSPEC 6973523
2000
¨    边计年，“底层相关的VLSI高层次设计策略”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics，12(11)，2000.11，827-829，EI 00125456525，INSPEC 6799823
¨    朱明，边计年，薛宏熙，“利用变量序过滤算法减小多叉判决图规模”，微电子学 30(S0)，2000年增刊，2000.10，130-132
¨    许灵均，边计年，薛宏熙，“用局部等价替换技术改善时延性能”，微电子学 30(S0)，2000年增刊，2000.10，124-126
¨    卢峰，边计年，薛宏熙，“结合OBDD和电路结构的等价性验证算法”，微电子学 30(S0)，2000年增刊2000.10 121-123
¨    杨勋，薛宏熙，边计年，“微处理器模型CE及其验证方法”，微电子学 30(S0)，2000年增刊，2000.10，156-158
¨    徐正生，曹霆，边计年，薛宏熙，“时延驱动的多级逻辑综合研究”，计算机应用 2000年增刊，2000.9 168-170
¨    范轶平，贝劲松，边计年，薛宏熙，“符号模型判别系统的一种实用反例生成策略”，计算机应用 2000年增刊，2000.9，165-167，
¨    Long Wang-ning，Min Ying-hu，Bian Ji-nian，Yang Shi-yuan，Xue Hong-xi，“Efficient Heuristic Variable Ordering of OBDDs”，Tsinghua Science and Technology(清华大学学报英文版)，5(2)，2000.6. 221-226
¨    龙望宁，吴有亮，边计年，薛宏熙，“基于蕴涵树的冗余添加与删除技术”，计算机学报Chinese Journal of Computers， 23(4)，2000.4，356-362，EI 01015501585，INSPEC 6605609
¨    边计年，“布图驱动的逻辑综合技术”，中国学术期刊文摘(科技快报) 6(3)，2000.3， (0003K016)，387-388
1999
¨    曹霆，吴彦青，王刚，边计年，薛宏熙，“Windows中图形数据传输技术的实现”，电子技术与应用 25(10)，1999.10. 9-11
¨    王志明，边计年，龙望宁，薛宏熙，“基于二叉判决图的逻辑电路形式验证工具”，软件学报 10(增刊)，1999.6. 235-238 TP3-2
¨    贝劲松，边计年，薛宏熙，龙望宁，洪先龙，“SAS：形式验证中的OBDD变量排序算法”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics，11(5)，1999.9，412-416，EI 99114878831，INSPEC 006406117
¨    贝劲松，李洪星，边计年，薛宏熙，洪先龙，“形式验证中同步时序电路的VHDL描述到S2-FSM的转换”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics 11(3)，1999.5，196-199，EI 99084745239，INSPEC 006278840
1998
¨    贝劲松，李洪星，边计年，薛宏熙，“BDD在有限状态机验证中的应用”，微电子学与计算机 1998年增刊，1998.7 158-161
¨    赵方，郭芳，边计年，王刚，薛宏熙，“VHDL翻译型模拟器中函数功能的实现”微电子学与计算机 1998年增刊，1998.7，133-135
¨    边计年，“VITAL─设计ASIC模型的VHDL基准”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics，10(2)，1998.3. 161-166，EI 98064254897，INSPEC 006144280
¨    边计年，陈菁，“V2C++—— 一个用C++实现的VHDL 翻译型模拟器”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics，10(2)，1998.3. 167-172 EI 98064254898 INSPEC 006144281
1997
¨    边计年，卢峰，郭芳，“适应调试功能的VHDL模型及模拟算法”，计算机学报Chinese Journal of Computers，20(11)，1997.11，996-1002，EI 98034142626，INSPEC 005851162
1995
¨    边计年，移容树，“VHDL预定义算符的功能实现及其数据类型的相容性”，微电子学与计算机 1995年增刊[1995.7]，11-13
¨    边计年，郭芳，“VHDL层次化结构模型及其确立算法”，微电子学与计算机，1995 年增刊[1995.7] ，8-10
¨    苏明，薛宏熙，边计年，“VHDL集成设计环境”，微电子学与计算机，1995年增刊[1995.7]，1-3
1994
¨    王庆生，薛宏熙，边计年，“图文混合编辑器中VHDL源描述的自动生成”，计算机工程，1994年专刊[1994.6]
1991
¨    边计年，卢勤，吕昌，刘渝，连永君，“一个功能较强的交互式混合级逻辑模拟工具SIM”，计算机辅助设计与图形学学报Journal of Computer Aided Design & Computer Graphics，3(2)，1991.3，55-60
International Conferences
Accepted:
¨    Qiang Wu，Jinian Bian，Renfa Li，Yunfeng Wang，Haili Wang，Wei Wang，Wei Xie，“Extend Force-directed Scheduling for System-level Synthesis in Time-constrained System-on-Chip Design”，ICESS’05，Xi’an，2005.12.16-18，IEEE CS
¨    Yunfeng Wang，Jinian Bian，Xianlong Hong，Liu Yang，Qiang Zhou，Qiang Wu，“A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design”，ICESS’05，Xi’an，2005.12.16-18，LNCS，SCI
¨    Feng Lin，Haili Wang，JinianBian，“HW/SW Interface Synthesis based on Avalon Bus Specification for Nios-oriented SoC Design”，FPT’06，Singapore，2005.12.11-14
2005
¨    Zhipeng Liu, Jinian Bian, Jianfeng Huang, Yunfeng Wang, “Fast and Efficiently Binding of Functional Units For Low Power Design”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 94-97
¨    Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu, “SLCAO: An Effective System Level Communication Architectures Optimization Methodology for System-on-Chips”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 114-117
¨    Jianfeng Huang, Jinian Bian, Zhipeng Liu, Yunfeng Wang, “A Fast Algorithm for Power Optimization Using Multiple Voltages in Data Path Synthesis”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 902-905
¨    Shaohe Wu, Minchuan Chen, Weimin Wu, Jinian Bian, “RTL Property Checking Technology Based on ATPG and ILP”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 890-893
¨    Minchun Chen, Weimin Wu, Jinian Bian, “RTL Satisfiability Solving Using an ATPG based Approach”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 910-913
Tao Liu, Wei-Ming Wu, Yu-Liang Wu, Ji-Nian Bian, “Hexagon/Triangle Packing Using Improved Least Flexibility First Principle Algorithm”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 828-831
Zhuoyuan Li, Haixia Yan, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannal H. Yang, Vijay Pitchumani, “Design Tools for 3D Mixed Mode Placement”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 796-799
Bin Liu, Yici Cai, Qiang Zhou, Jinian Bian, Xianling Hong, “Decomposition for Power Gating Design Automation in Sequential Circuits”, 2005 6th International Conference on ASIC Proceedings, ASICON’05, Shanghai, 2005.10.17-20, 862-865
Weiwei Zheng，Weimin Wu，Jinian Bian，“Hierarchical Property Checking for RTL Circuits by LP-based Satisfiability Solving”，The 6th Workshop on RTL and High level Test Symposium，WRTLT’05，Harbin，2005.7. 213-218
Di Wang，Weimin Wu，Weiwei Zheng，Jinian Bian，“Model Checking of A DLX Microprocessor Design By Exploiting Modular Hierarchy”，The 6th Workshop on RTL and High level Test Symposium，WRTLT’05，Harbin，2005.7. 219-223
Yunfeng Wang，Jinian Bian，Xainlong Hong，“ A New Methodology of Integrating High Level Synthesis and Floorplanning for Nanometer Regime Design”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CD’05，Delft，Nederland，2005.5. 437-441，ISTP BCT62
Haili Wang，Jinian Bian，Qiang Wu，Yawen Niu，Kun Tong，“Integrated Hardware/Software Partitioning and Architecture Synthesis for Systems-on-Chip Design: An Incremental Design Methodology”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CD’05，Delft，Nederland，2005.5. 702-707，ISTP BCT62
Kun Tong，Jinian Bian，Haili Wang，“Piss: A Performance-Driven Interface，Synthesis System”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CD’05，Delft，Nederland，2005.5. 601-606，ISTP BCT62
Yawen Niu，Jinian Bian，Haili Wang，“CGEM: A Communication Graph Extraction Methodology Based on HCDFG for Channel Mapping in System Level Design”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CD’05，Delft，Nederland，2005.5. 696-701，ISTP BCT62
Liang Zhu，Haili Wang，Jinian Bian，“A Novel Method of Generating Transaction-level Model Based on Transformation Techniques”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CD’05，Delft，Nederland，2005.5. 768-773，ISTP BCT62
Rongjun Mu，Jinian Bian，Yu-liang Wu，Wai-Chung Tang，“Further Minimization of Bdds for LargeCircuits With Xor/Xnor Recognition”，Proceedings of International Conference on Computer Aided Industrial Design and Conceptual Design，CAID&CD’05，Delft，Nederland，2005.5. 551-555，ISTP BCT62
Wenjun Wang，Yunfeng Wang，Jinian Bian，“A Congestion Driven Re-Synthesis Method after floorplannig”，2005 (3st) International Conference on Communications，Circuits，and Systems and West Sino Exprositions Proceedings，ICCCAS’05，Hong Kong，2005.5. 1220-1224，ISTP BCZ13，INSPEC 8623662, IEEE xplore 
Jianfeng Huang，Jinian Bian，Zhipeng Liu，Yunfeng Wang，“Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing”，2005 (3st) International Conference on Communications，Circuits，and Systems and West Sino Exprositions Proceedings，ICCCAS’05，Hong Kong，2005.5. 1370-1374，ISTP BCZ13，INSPEC 8623694, IEEE xplore 
Haili Wang，Jinian Bian，Qiang Wu，Yunfeng Wang，“iTuCoMe: HCDFG-based Incremental Tuning HW/SW Codesign Methodology for Multi-level Exploration”，Procedings of The 9th International Conference on Computer Suppoted Cooperative Work in Design，CSCWD’05，Coventry，UK，2005.5. 978-983，ISTP BCO78，INSPEC 8588021，IEEE Xplore
Jianzhou Zhao，Jinian Bian，Weimin Wu，“Cooperation of SMV and Jeda for the Property Checking of Mixed Control and Data Intensive Designs”，Procedings of The 9th International Conference on Computer Suppoted Cooperative Work in Design，CSCWD’05，Coventry，UK，2005.5. 1024-1028，ISTP BCO78，INSPEC 8588029，IEEE Xplore
Yunfeng Wang，Jinian Bian，xianlong Hong，“Interconnect Delay Optimization via High Level Re-synthesis After Floorplanning”，International Symposium on Circuits and Systems，ISCAS’05，Cobe，Japan，2005.5. 5641-5644，ISTP BCZ06，IEEE xplore
Zhuoyuan Li，Xianlong Hong，Qiang Zhou，Yici Cai，Jinian Bian; Hannal Yang，Prashant Saxena，Vijay Pitchumani，“A Divide-and-Conquer 2.5-D Floorplanning Algorithm Based On Statistical Wirelength Estimation”， International Symposium on Circuits and Systems，ISCAS’05，Cobe，Japan，2005.5. 6230-6233，ISTP BCZ06，IEEE xplore
Qiang Wu，Jinian Bian，Hongxi Xue，“System-level Architectural Exploration Using Allocate-on-Demand Technique”，Proceedings of Asia and South-Pacific Design Automation Conference，ASP-DEC05，shanghai 2005.1，1296-1299，INSPEC 8487179，IEEE xplore
2004
Ming Zhu，Jinian Bian，Weimin Wu，“Optimization Techniques in a Functional Verification Platform for Embedded System”，The First International Conference on Embedded Software and System，ICESS04，Hangzhou，2004.12，480-486；Lecture Note in Computer Science (LNCS)，Vol. 3605 / 2005，DOI: 10.1007/11535409_79，2005.8. 542-548
Haili Wang，Jinian Bian，Yawen Niu，Kun Tong，Yunfeng Wang，，“CA-Ex: A Tuning-Incremental Methodology for Application-Specific Communication Architectures in Distributed Embedded Systems”，The First International Conference on Embedded Software and System，ICESS04，Hangzhou，2004.12. 7-14 Best Paper Award；Lecture Note in Computer Science (LNCS)，Vol. 3605 / 2005，DOI: 10.1007/11535409_79，2005.8. 74-80
Qiang Wu，Jinian Bian，Hongxi Xue，“A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design”，The First International Conference on Embedded Software and System，ICESS04，Hangzhou，2004.12. 124-130；Lecture Note in Computer Science (LNCS)，Vol. 3605 / 2005，DOI: 10.1007/11535409_79，2005.8. 150-157
Kun Tong，Haili Wang，Jinian Bian，“A Generic Interface Modeling Approach for SOC Design”，2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings，ICSICT’04，Beijing，2004.10. v.II，1400-1403 EI 05299218069，ISTP BBR18，INSPEC 8510606
Jianzhou Zhao，Jinian Bian，Weimin Wu，“PFGASAT-a Genetic SAT Solver Combining Partitioning and Fuzzy Strategies”，Proceedings of the 28th Annual International Computer Software and Applications Conference，COMPSAC 2004，Hong Kong，(28th) 2004.9，108-113，EI 05219121849，INSPEC 8303524，IEEE xplore，ACM lib
Weimin Wu，Ming Zhu，Jianzhou Zhao，Jinian Bian，“AL/RTL Co-Modeling And General Test Generation”，2004 International Conference on Communications，Circuits and Systems，ICCCAS2004 (2nd)，Chengdu 2004.6. 1329-1333，EI 05038790248，ISTP BBC53，000224820400291，INSPEC 8097931，IEEE xplore
Zhu Ming，Bian Jinian，Wu Weimin，“A Novel Collaborative Scheme of Simulation and Moddel Checking for Property Verification”，Proceedings of 8th International Conference on Computer Supported Cooperative Work in Design，CSCWD’04，Xiamen，(8th，Vol.II) 2004.5. 67-72 ISTP BAN11，000222931800020，INSPEC 8229343，IEEE xplore
2003
Ming Zhu，Jinian Bian，Weimin Wu，Hongxi Xue，“Property Classification for Hibrid Verification”，The 4th Workshop on RTL and High level Test Symposium，WRTLT’03，(2nd)，Xian 2003.11. 129-132
Jianzhou Zhao，Jinian Bian，Weimin Wu，“ACSAT: A SAT Solver via Solving TSP by ACO”，The 4th Workshop on RTL and High level Test Symposium，WRTLT’03，Xian 2003.11. 133-137
Weimin Wu，Di Wang，Weiwei Zheng，Jinian Bian，Ming Zhu，Jianzhou Zhao，“Safety Checking By Problem Solving”，The 4th Workshop on RTL and High level Test Symposium，WRTLT’03，Xian 2003.11. 151-156
Ming Zhu，Jinian Bian，Weimin Wu，Hongxi Xue，“Property Classification for Functional Verification based on CDFG”，Proceedings of the Twelfth Asian Test Symposium，ATS’03，(12th)，Xian 2003.11，503 ISTP BY38Z 000189157300092，INSPEC 7905635，IEEE xplore
¨    Haili Wang，Qiang Wu，Jinian Bian，Zhihui Xiong，Jihua Chen，Sikun Li，“A Novel Virtual-Real Component Synthesis Approach in SoC Design”，8th International Conference on CAD/Graphics，OCT 29-31，2003 CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS，PROCEEDINGS，CAD/Graphics’03，Macau 2003.10. 151-156，ISTP BAY65 000224243000023
Qiang Wu，Yunfeng Wang，Jinian Bian，Hongxi Xue，“Graph Transformations on CDFG for Granularity Selection in Hardware-Software Partitioning: Experiments and Analysis”，8th International Conference on CAD/Graphics，OCT 29-31，2003 CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS，PROCEEDINGS，CAD/Graphics’03，Macau 2003.10. 303-308，ISTP BAY65 000224243000046
Weimin Wu，Zhuoyuan Li，Hanbin Zhou，Xianlong Hong，Jinian Bian，“A Size-Balancing Approach to Mixed Mode Placement”，8th International Conference on CAD/Graphics，OCT 29-31，2003 CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS，PROCEEDINGS，CAD/Graphics’03，Macau 2003.10. 309-314，ISTP BAY65 000224243000047
Qiang Wu，Jinian Bian，Hongxi Xue，Yiping Fan，Weimin Wu，Xianlong Hong and Jun Gu，“Applying Search Space Smoothing Technique to Hardware/Software Partitioning”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON’03，Beijing 2003.10，85-88，ISTP BY56E 000189408900012，INSPEC 8015734，IEEE xplore
Hu Heng，Hongxi Xue，Jinian Bian，“A heuristic state assignment algorithm targeting area”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON’03，Beijing 2003.10. 93-96，ISTP BY56E 000189408900014，INSPEC 8015736，IEEE xplore，，ACM lib
Jinian Bian，Hongxi Xue，Zhengsheng Xu，Lingjun Xu，Yunfeng Wang，Yu-Liang Wu，“Local Logic Substitution Algorithm for Post-Layout Re-synthesis”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON’03，Beijing 2003.10. 136-139 ISTP BY56E 000189408900024，INSPEC 8015745，IEEE xplore
Wang Yunfeng，Bian Jinian，Wu Qiang，Hu Heng，“Reallocation and Rescheduling after Floor-planning for Timing Optimization”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON’03，Beijing 2003.10. 212-215 ISTP BY56E 000189408900042，INSPEC 8015761，IEEE xplore
Ming Zhu，Jinian Bian，Weimin Wu，Hongxi Xue，“Property-Classified Hybrid Verification based on CDFG”，Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON03，Beijing 2003.10. 233-237 ISTP BY56E 000189408900047，INSPEC 8015766，IEEE xplore
Jin Chen，Qiang Wu，Jinian Bian，Hongxi Xue，“SGA - A Self-adaptable granularity Approach for Hardware/Software Co-design”Proceedings of 2003 5th International Conference on ASIC. (IEEE Cat. No.03TH8690)，ASICON’03，Beijing 2003.10. 365-368 ISTP BY56E 000189408900079，INSPEC 8015794，IEEE xplore
Yang Xiao，Yufeng Wang，Jinian Bian，“Placement-Aware Retiming and Rescheduling in High-Level Synthesis”，CAID/CD’03，Hangzhou 2003.10. 556-561
Qiang Wu，Jinian Bian，Hongxi Xue，“A Unified Method for System Synthesis with Hardware and Software IP Cores in SoC Design”，CAID/CD’03，Hangzhou 2003.10. 802-807
Weimin Wu，Di Wang，Weiwei Zheng，Jinian Bian，Ming Zhu，“Property Checking Using RTL ATPG”，CAID/CD’03，Hangzhou 2003.10. 871-875
2002
Zhu Ming，Bian Jinian，Xue Hongxi，“Uniform Internal Model for Hybrid Language Description”，2002 International Conference on Communications，Circuits and Systems and West Sino Exposition Proceedings (Cat. No.02EX591)，ICCCAS’02，Chengdu 2002.6. 1322-1325 INSPEC 7691405，ISTP BY38Z 000189407400280，IEEE xplore
Qiang Wu，Yunfeng Wang，Jinian Bian，Weimin Wu，Hongxi Xue，“A Hierarchical CDFG as Intermediate Representation for Hardware/Software Codesign”2002 International Conference on Communications，Circuits and Systems and West Sino Exposition Proceedings (Cat. No.02EX591)，ICCCAS’02，Chengdu 2002.6. 1429-1432 INSPEC 7691428，ISTP BY38Z 000189407400303，IEEE xplore
2001
Xu Lingjun，Bian Jinian and Xue Hongxi，“Delay-driven Algorithm for Logic Re-synthesis after Placement”，CAID&CD’01，jinan，qingdao 2001.10. 647-651
Wang yunfeng，Lu Feng，Bian Jinian，Xue Hongxi，“，Merging High-Level Synthesis with Layout Design for SOC Design”，CAID&CD’01，jinan，qingdao 2001.10. 227-231
Lu Feng，Bian Jinian，Xue Hongxi，“EVBCS: New Equivalence Verification Algorithm Based on OBDD and Circuit Structure”，International Conference on ASIC，Proceedings，ASICON’01，Shanghai 2001. 10，190-193，EI 02126890572，ISTP  BU56Q 0001 76369900036，INSPEC 7260694，IEEE xplore
Yang Xun，Zhu Ming，Xue Hongxi，Bian Jinian，Hong Xianlong，“A Platform for System-on-a-chip Design Prototyping”，2001 4th International Conference on ASIC Proceedings，ASICON’01，Shanghai 2001. 10. 781-784，EI 02126890717，ISTP BU56Q 0001 76369900184，INSPEC 7260842，IEEE xplore
Liu Jianhua，Zhu Ming，Bian Jinian，Xue Hongxi，“A debug sub-system for embedded-system co-verification”，2001 4th International Conference on ASIC Proceedings，ASICON’01，Shanghai 2001.10.，777-780，EI 02126890716，ISTP BU56Q 0001 76369900183，INSPEC 7260841，IEEE xplore
2000 
Yang Xun，Xue Hongxi，Bian Jinian，“A Platform Supporting Hw/Sw System Coverification”，CAID&CD 2000，Hong Kong 2000.11. 533-536
Yiping Fan，Jinsong Bei，Jinian Bian，HongXi Xue，Xianlong Hong，Jun Gu，“VERIS: An Efficient Model Checker for Synchronous VHDL Designs”，WCC 2000 (icda 2000)  2000.8. 475-480;  Annual International Hardware Description Language Conference and Exhibition (HDLCON)，AUG，2000; System-On-Chip Methodologies & Design Languages 2001，97-107，ISTP BT43U 000173022800009
Jinian Bian，Hongxi Xue，Yanqing Wu，“OMDD - New Representation of Boolean Functions Oriented to Logic Synthesis”，Procedings Volume VII. Computer Science and Engineering: Part I. Programming-Techniques，SCI2000/ISAS2000，Orlando，Florida，USA  2000.7.
Xun Yang，Hongxi Xue，Jinian Bian，“The Integration of Simulation and Emulation for SOC HW/SW Coverification”，Procedings Volume VIII. Computer Science and Engineering: Part II  Geographical Information Systems，SCI2000/ISAS2000，Orlando，Florida，USA  2000.7.
Wangning Long，Yu-Liang Wu，Jinian Bian，“IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm”，Proceedings ASP-DAC 2000. Asia and South Pacific Design Automation Conference 2000 with EDA TechnoFair 2000. (Cat. No.00EX389)，ASP-DAC'00，Yokohama，Japan 2000.1. 415-421，INSPEC 6597039，IEEE xplore
1999
Wangning Long，Yu-Liang Wu，Jinian Bian，“On Implication-Tree Based Redundancy Addition and Removal Algorithm”，1999 IEEE International Symposium on Intelligent Signal Processing and Communication Systems. Signal Processing and Communications Beyond 2000，ISPACS'99，Phuket，Thailand 1999.12. 53-56 INSPEC 6662729，
Zhiming Wang，Jinian Bian，Hongxi Xue，“A Method of Formal Verification for Logic Circuits with ‘Don't Care’ Information”，Proceedings of The 6th International Conference On Computer Aided Design & Computer Graphics，CAD/Graphics'99，Shanghai 1999.12. 622-625 ISTP BQ56H 000088777900119
Bian Jinian，“Lower Level Dependent Design Methodology for High Level VLSI Design”，CAID&CD'99，Bangkok，Thailand 1999.11. 173-177
Xun Yang，Hongxi Xue，Jinian Bian，“Cycle-based Algorithm Used to Accelerate VHDL Simulation”，APCHDL'99，Fukuoka，Japan 1999.10. 17-21
Jinsong Bei，Hongxing Li，Jinian Bian，Hongxi Xue，Xianlong Hong，“FSM modeling of synchronous VHDL design for symbolic model checking”，Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)，ASP-DAC’99，Hong Kong，1999.1. 363-366，ISTP BM69S 000079494700090，INSPEC 6358324，IEEE xplore
1998
Jinsong Bei，Jinian Bian，HongXi Xue，Wangning Long，“A new heuristic algorithm for OBDD variable ordering”，ASICON’98，Beijing，1998.10. 354-357
Zhiming Wang，Wangnign Long，Jinian Bian，Hongxi Xue，“An OBDD based formal verification system”，ASICON’98，Beijing，1998.10. 366-369
1997
Fang Guo，Jinian Bian，Gang Wang，Hongxi Xue，“A process-based event driven method for compiled-code simulation”，5th International Conference on Computer-Aided Design and Computer Graphics，CAD/Graphics'97，Shenzhen 1997.12. 601-604 ISTP BK32T 000071822600126
Jinian Bian，Hongxi Xue，Ming Su. “VIDE: A visual VHDL integrated design environment”，Proceedings of the ASP-DAC '97. Asia and South Pacific Design Automation Conference 1997 (Cat. No.97TH8231)，ASP-DAC'97，Chiba，Japan 1997.1，383-386，EI 97073722182，ISTP BJ06S，INSPEC 5559025，IEEE xplore
1995
Bian Jinian，Lu Feng，Wan Bo，Su Ming，“A model and an algorithm for VHDL high-level and hierarchical simulation with debug function”，CAD/Graphics'95，Wuhan 1995.10. 1235-1240;   Proceedings of SPIE - The International Society for Optical Engineering，vol.2644 1996. 791-796，EI 96053164216，ISTP 1996 No.8，P67639，INSPEC 5276251
Bo Wan，Jinian Bian. “VHdbx: An X window system based high-level debugger for the VHDL simulation environment”，1995 4th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.95TH8143)，ICSICT'95，Beijing 1995.10. 358-360，EI 96063224075，ISTP 1996 P 67258，INSPEC 5340928
Qingsheng Wang，Hongxi Xue，Ming Su，Jinian Bian. “Behavioral description in visual VHDL and its implementation”，1995 4th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.95TH8143)，ICSICT'95，Beijing 1995.10. 361-363，EI 96063224076，ISTP 1996 No7，P67258，INSPEC 5340929，IEEE xplore
1991
Bian Jinian，Liu Yu. “Signal state and delay calculation in switch-level networks for mixed-level simulation”，China 1991 International Conference on Circuits and Systems. Conference Proceedings (Cat. No.91TH0387-1)，ICCAS'91，Shenzhen，1991.6. 917-920，EIM 9305-026040，EI 93030727787 ，INSPEC 4264542，IEEE xplore
学术职务
中国计算机学会 高级会员
中国计算机学会 计算机辅助设计与图形学专业委员会 副主任
中国计算机学会会刊《计算机辅助设计与图形学学报》副主编
著作和译作
1.       边计年等译：实用C语言FPGA设计，机械工业出版社，待出版
2.       边计年，薛宏熙 等译：用SpecC进行系统设计，清华大学出版社，待出版
3.       边计年，薛宏熙，苏  明，吴为民：数字系统设计自动化（第2版），清华大学出版社，2005.7.
4.       边计年，吴为民 等译：嵌入式系统的规范与设计，机械工业出版社，2005.7.  
5.       边计年，薛宏熙，吴  强 译：数字逻辑与VHDL设计，清华大学出版社，2005.1.
6.       边计年，薛宏熙 译：用VHDL设计电子线路，清华大学出版社，2000.8.      
7.       洪先龙，刘伟平，边计年 等著：超大规模集成电路计算机辅助设计技术，国防工业出版社，1998.6.  
8.       乔长阁，边计年，薛宏熙 译：VHDL简明教程，清华大学出版社，1997.10.       
9.       薛宏熙，边计年，苏  明：数字系统设计自动化，清华大学出版社，1996.10.
10.    吴文虎主编：中小学计算机知识词典，天津科技出版社，1994.9.（副主编）
11.    谭浩强主编：微型计算机实用手册，高等教育出版社，1993.4.（第二分册编委）
12.    薛宏熙，边计年，赵致格：数字系统计算机辅助设计，海洋出版社  1990.6.      
13.    吴文虎，边计年（执笔）：中学计算机教程(下册)，清华大学出版社       1987.
14.    唐泽圣，周嘉玉 等译：交互式计算机图形学基础，清华大学出版社       1986.11.