; LLVM IR from hoodoer/ENNEoS :: enneosEncoder/genotype.ll (ZN7CGenome13DuplicateLinkEii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.CGenome = type <{ i32, [4 x i8], %"class.std::vector", %"class.std::vector.0", ptr, i32, [4 x i8], double, double, double, i32, i32, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl" }
%"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl" = type { %"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl" }
%"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl" = type { %"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SLinkGene = type <{ i8, [3 x i8], i32, i32, i32, double, i8, [7 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN7CGenome13DuplicateLinkEii(ptr noundef nonnull align 8 dereferenceable(108) %0, i32 noundef %1, i32 noundef %2) #1 align 2 {
  %4 = alloca i1, align 1
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  %10 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %11

11:                                               ; preds = %38, %3
  %12 = load i32, ptr %8, align 4, !tbaa !9
  %13 = zext i32 %12 to i64
  %14 = getelementptr inbounds %class.CGenome, ptr %10, i32 0, i32 3
  %15 = call noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %14) #2
  %16 = icmp ult i64 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %11
  store i32 2, ptr %9, align 4
  br label %41

18:                                               ; preds = %11
  %19 = getelementptr inbounds %class.CGenome, ptr %10, i32 0, i32 3
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = zext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %21) #2
  %23 = getelementptr inbounds %struct.SLinkGene, ptr %22, i32 0, i32 3
  %24 = load i32, ptr %23, align 8, !tbaa !11
  %25 = load i32, ptr %6, align 4, !tbaa !9
  %26 = icmp eq i32 %24, %25
  br i1 %26, label %27, label %37

27:                                               ; preds = %18
  %28 = getelementptr inbounds %class.CGenome, ptr %10, i32 0, i32 3
  %29 = load i32, ptr %8, align 4, !tbaa !9
  %30 = zext i32 %29 to i64
  %31 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %30) #2
  %32 = getelementptr inbounds %struct.SLinkGene, ptr %31, i32 0, i32 4
  %33 = load i32, ptr %32, align 4, !tbaa !15
  %34 = load i32, ptr %7, align 4, !tbaa !9
  %35 = icmp eq i32 %33, %34
  br i1 %35, label %36, label %37

36:                                               ; preds = %27
  store i1 true, ptr %4, align 1
  store i32 1, ptr %9, align 4
  br label %41

37:                                               ; preds = %27, %18
  br label %38

38:                                               ; preds = %37
  %39 = load i32, ptr %8, align 4, !tbaa !9
  %40 = add i32 %39, 1
  store i32 %40, ptr %8, align 4, !tbaa !9
  br label %11, !llvm.loop !16

41:                                               ; preds = %36, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %42 = load i32, ptr %9, align 4
  switch i32 %42, label %46 [
    i32 2, label %43
    i32 1, label %44
  ]

43:                                               ; preds = %41
  store i1 false, ptr %4, align 1
  br label %44

44:                                               ; preds = %43, %41
  %45 = load i1, ptr %4, align 1
  ret i1 %45

46:                                               ; preds = %41
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"_ZTS9SLinkGene", !13, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !14, i64 16, !13, i64 24}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"double", !7, i64 0}
!15 = !{!12, !10, i64 12}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN7CGenome13DuplicateLinkEii(ptr noundef nonnull align 8 dereferenceable(108) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 32
  %5 = tail call noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #1
  %.not11.not = icmp eq i64 %5, 0
  br i1 %.not11.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %3, %16
  %6 = phi i64 [ %18, %16 ], [ 0, %3 ]
  %.0812 = phi i32 [ %17, %16 ], [ 0, %3 ]
  %7 = tail call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %6) #1
  %8 = getelementptr inbounds i8, ptr %7, i64 8
  %9 = load i32, ptr %8, align 8, !tbaa !5
  %10 = icmp eq i32 %9, %1
  br i1 %10, label %11, label %16

11:                                               ; preds = %.lr.ph
  %12 = tail call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %6) #1
  %13 = getelementptr inbounds i8, ptr %12, i64 12
  %14 = load i32, ptr %13, align 4, !tbaa !12
  %15 = icmp eq i32 %14, %2
  br i1 %15, label %._crit_edge, label %16

16:                                               ; preds = %.lr.ph, %11
  %17 = add i32 %.0812, 1
  %18 = zext i32 %17 to i64
  %19 = tail call noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #1
  %.not = icmp ugt i64 %19, %18
  br i1 %.not, label %.lr.ph, label %._crit_edge, !llvm.loop !13

._crit_edge:                                      ; preds = %16, %11, %3
  %.not.lcssa = phi i1 [ false, %3 ], [ true, %11 ], [ false, %16 ]
  ret i1 %.not.lcssa
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"_ZTS9SLinkGene", !7, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !11, i64 16, !7, i64 24}
!7 = !{!"bool", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"double", !8, i64 0}
!12 = !{!6, !10, i64 12}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass