; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library (PciCf8BitFieldRead32)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @SaveAndDisableInterrupts() #0

declare i32 @IoRead32(i64 noundef) #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @PciCf8BitFieldRead32(i64 noundef %0, i64 noundef %1, i64 noundef %2) #2 {
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i64 %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !5
  store i64 %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  br label %10

10:                                               ; preds = %3
  %11 = call zeroext i8 @DebugAssertEnabled()
  %12 = icmp ne i8 %11, 0
  br i1 %12, label %13, label %19

13:                                               ; preds = %10
  %14 = load i64, ptr %4, align 8, !tbaa !5
  %15 = and i64 %14, -268431613
  %16 = icmp eq i64 %15, 0
  br i1 %16, label %18, label %17

17:                                               ; preds = %13
  call void @DebugAssert(ptr noundef @.str, i64 noundef 1343, ptr noundef @.str.3)
  br label %18

18:                                               ; preds = %17, %13
  br label %19

19:                                               ; preds = %18, %10
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = call zeroext i8 @SaveAndDisableInterrupts()
  store i8 %22, ptr %7, align 1, !tbaa !9
  %23 = call i32 @IoRead32(i64 noundef 3320)
  store i32 %23, ptr %8, align 4, !tbaa !10
  %24 = load i64, ptr %4, align 8, !tbaa !5
  %25 = lshr i64 %24, 4
  %26 = and i64 %25, 16776960
  %27 = load i64, ptr %4, align 8, !tbaa !5
  %28 = and i64 %27, 252
  %29 = or i64 %26, %28
  %30 = or i64 %29, 2147483648
  %31 = trunc i64 %30 to i32
  %32 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %31)
  %33 = load i64, ptr %5, align 8, !tbaa !5
  %34 = load i64, ptr %6, align 8, !tbaa !5
  %35 = call i32 @IoBitFieldRead32(i64 noundef 3324, i64 noundef %33, i64 noundef %34)
  store i32 %35, ptr %9, align 4, !tbaa !10
  %36 = load i32, ptr %8, align 4, !tbaa !10
  %37 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %36)
  %38 = load i8, ptr %7, align 1, !tbaa !9
  %39 = call zeroext i8 @SetInterruptState(i8 noundef zeroext %38)
  %40 = load i32, ptr %9, align 4, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  ret i32 %40
}

declare i32 @IoBitFieldRead32(i64 noundef, i64 noundef, i64 noundef) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

declare zeroext i8 @SaveAndDisableInterrupts() local_unnamed_addr #0

declare i32 @IoRead32(i64 noundef) local_unnamed_addr #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @PciCf8BitFieldRead32(i64 noundef %0, i64 noundef %1, i64 noundef %2) local_unnamed_addr #1 {
  %4 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not = icmp eq i8 %4, 0
  %5 = and i64 %0, -268431613
  %6 = icmp eq i64 %5, 0
  %or.cond = or i1 %6, %.not
  br i1 %or.cond, label %8, label %7

7:                                                ; preds = %3
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 1343, ptr noundef nonnull @.str.3) #2
  br label %8

8:                                                ; preds = %7, %3
  %9 = tail call zeroext i8 @SaveAndDisableInterrupts() #2
  %10 = tail call i32 @IoRead32(i64 noundef 3320) #2
  %11 = lshr i64 %0, 4
  %12 = and i64 %11, 16776960
  %13 = and i64 %0, 252
  %14 = or disjoint i64 %12, %13
  %15 = trunc nuw nsw i64 %14 to i32
  %16 = or disjoint i32 %15, -2147483648
  %17 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %16) #2
  %18 = tail call i32 @IoBitFieldRead32(i64 noundef 3324, i64 noundef %1, i64 noundef %2) #2
  %19 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %10) #2
  %20 = tail call zeroext i8 @SetInterruptState(i8 noundef zeroext %9) #2
  ret i32 %18
}

declare i32 @IoBitFieldRead32(i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass