; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication/sc_semaphore.ll (ZN7sc_core12sc_semaphore4waitEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_semaphore" = type <{ %"class.sc_core::sc_semaphore_if", %"class.sc_core::sc_object", %"class.sc_core::sc_event", i32, [4 x i8] }>
%"class.sc_core::sc_semaphore_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.13", %"class.std::vector.13" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN7sc_core12sc_semaphore4waitEv(ptr noundef nonnull align 8 dereferenceable(284) %0) unnamed_addr #0 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  br label %4

4:                                                ; preds = %6, %1
  %5 = call noundef zeroext i1 @_ZNK7sc_core12sc_semaphore6in_useEv(ptr noundef nonnull align 8 dereferenceable(284) %3)
  br i1 %5, label %6, label %9

6:                                                ; preds = %4
  %7 = getelementptr inbounds %"class.sc_core::sc_semaphore", ptr %3, i32 0, i32 2
  %8 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  call void @_ZN7sc_core4waitERKNS_8sc_eventEPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(160) %7, ptr noundef %8)
  br label %4, !llvm.loop !9

9:                                                ; preds = %4
  %10 = getelementptr inbounds %"class.sc_core::sc_semaphore", ptr %3, i32 0, i32 3
  %11 = load i32, ptr %10, align 8, !tbaa !11
  %12 = add nsw i32 %11, -1
  store i32 %12, ptr %10, align 8, !tbaa !11
  ret i32 0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core12sc_semaphore6in_useEv(ptr noundef nonnull align 8 dereferenceable(284)) #1 align 2

declare void @_ZN7sc_core4waitERKNS_8sc_eventEPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(160), ptr noundef) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !28, i64 280}
!12 = !{!"_ZTSN7sc_core12sc_semaphoreE", !13, i64 0, !14, i64 8, !26, i64 120, !28, i64 280}
!13 = !{!"_ZTSN7sc_core15sc_semaphore_ifE"}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !6, i64 96, !6, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSN7sc_core8sc_eventE", !23, i64 0, !6, i64 32, !6, i64 40, !27, i64 48, !28, i64 52, !6, i64 56, !29, i64 64, !29, i64 88, !33, i64 112, !33, i64 136}
!27 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!28 = !{!"int", !7, i64 0}
!29 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN7sc_core12sc_semaphore4waitEv(ptr noundef nonnull align 8 dereferenceable(284) %0) unnamed_addr #0 align 2 {
  %2 = tail call noundef zeroext i1 @_ZNK7sc_core12sc_semaphore6in_useEv(ptr noundef nonnull align 8 dereferenceable(284) %0)
  br i1 %2, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %1
  %3 = getelementptr inbounds i8, ptr %0, i64 120
  br label %4

4:                                                ; preds = %.lr.ph, %4
  %5 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  tail call void @_ZN7sc_core4waitERKNS_8sc_eventEPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(160) %3, ptr noundef %5)
  %6 = tail call noundef zeroext i1 @_ZNK7sc_core12sc_semaphore6in_useEv(ptr noundef nonnull align 8 dereferenceable(284) %0)
  br i1 %6, label %4, label %._crit_edge, !llvm.loop !5

._crit_edge:                                      ; preds = %4, %1
  %7 = getelementptr inbounds i8, ptr %0, i64 280
  %8 = load i32, ptr %7, align 8, !tbaa !7
  %9 = add nsw i32 %8, -1
  store i32 %9, ptr %7, align 8, !tbaa !7
  ret i32 0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core12sc_semaphore6in_useEv(ptr noundef nonnull align 8 dereferenceable(284)) local_unnamed_addr #1 align 2

declare void @_ZN7sc_core4waitERKNS_8sc_eventEPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(160), ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !27, i64 280}
!8 = !{!"_ZTSN7sc_core12sc_semaphoreE", !9, i64 0, !10, i64 8, !25, i64 120, !27, i64 280}
!9 = !{!"_ZTSN7sc_core15sc_semaphore_ifE"}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !12, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!24 = !{!"long", !12, i64 0}
!25 = !{!"_ZTSN7sc_core8sc_eventE", !22, i64 0, !11, i64 32, !11, i64 40, !26, i64 48, !27, i64 52, !11, i64 56, !28, i64 64, !28, i64 88, !32, i64 112, !32, i64 136}
!26 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !12, i64 0}
!27 = !{!"int", !12, i64 0}
!28 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!32 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}


; Effective O3 passes: GlobalOptPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass