; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_export)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_export_registry" = type { i32, %"class.std::vector.18", ptr }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_export_base *, std::allocator<sc_core::sc_export_base *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_export_base *, std::allocator<sc_core::sc_export_base *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_export_base *, std::allocator<sc_core::sc_export_base *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_export_base *, std::allocator<sc_core::sc_export_base *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core31SC_ID_SC_EXPORT_NOT_REGISTERED_E = external constant [0 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core18sc_export_registry6removeEPNS_14sc_export_baseE(ptr noundef nonnull align 8 dereferenceable(40) %0, ptr noundef %1) #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  %7 = call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %6)
  %8 = icmp eq i32 %7, 0
  br i1 %8, label %9, label %10

9:                                                ; preds = %2
  br label %49

10:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %11 = call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %6)
  %12 = sub nsw i32 %11, 1
  store i32 %12, ptr %5, align 4, !tbaa !9
  br label %13

13:                                               ; preds = %26, %10
  %14 = load i32, ptr %5, align 4, !tbaa !9
  %15 = icmp sge i32 %14, 0
  br i1 %15, label %16, label %29

16:                                               ; preds = %13
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %"class.sc_core::sc_export_registry", ptr %6, i32 0, i32 1
  %19 = load i32, ptr %5, align 4, !tbaa !9
  %20 = sext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %20) #3
  %22 = load ptr, ptr %21, align 8, !tbaa !5
  %23 = icmp eq ptr %17, %22
  br i1 %23, label %24, label %25

24:                                               ; preds = %16
  br label %29

25:                                               ; preds = %16
  br label %26

26:                                               ; preds = %25
  %27 = load i32, ptr %5, align 4, !tbaa !9
  %28 = add nsw i32 %27, -1
  store i32 %28, ptr %5, align 4, !tbaa !9
  br label %13, !llvm.loop !11

29:                                               ; preds = %24, %13
  %30 = load i32, ptr %5, align 4, !tbaa !9
  %31 = icmp eq i32 %30, -1
  br i1 %31, label %32, label %34

32:                                               ; preds = %29
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZNK7sc_core14sc_export_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(112) %33, ptr noundef @_ZN7sc_core31SC_ID_SC_EXPORT_NOT_REGISTERED_E, ptr noundef null)
  br label %34

34:                                               ; preds = %32, %29
  %35 = getelementptr inbounds %"class.sc_core::sc_export_registry", ptr %6, i32 0, i32 1
  %36 = call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %6)
  %37 = sub nsw i32 %36, 1
  %38 = sext i32 %37 to i64
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef %38) #3
  %40 = load ptr, ptr %39, align 8, !tbaa !5
  %41 = getelementptr inbounds %"class.sc_core::sc_export_registry", ptr %6, i32 0, i32 1
  %42 = load i32, ptr %5, align 4, !tbaa !9
  %43 = sext i32 %42 to i64
  %44 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %43) #3
  store ptr %40, ptr %44, align 8, !tbaa !5
  %45 = getelementptr inbounds %"class.sc_core::sc_export_registry", ptr %6, i32 0, i32 1
  %46 = call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %6)
  %47 = sub nsw i32 %46, 1
  %48 = sext i32 %47 to i64
  call void @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef %48)
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %49

49:                                               ; preds = %34, %9
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core14sc_export_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(112), ptr noundef, ptr noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core31SC_ID_SC_EXPORT_NOT_REGISTERED_E = external constant [0 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core18sc_export_registry6removeEPNS_14sc_export_baseE(ptr noundef nonnull align 8 dereferenceable(40) %0, ptr noundef %1) local_unnamed_addr #0 align 2 {
  %3 = tail call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  %4 = icmp eq i32 %3, 0
  br i1 %4, label %30, label %5

5:                                                ; preds = %2
  %6 = tail call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  %8 = zext i32 %6 to i64
  br label %9

9:                                                ; preds = %13, %5
  %indvars.iv = phi i64 [ %10, %13 ], [ %8, %5 ]
  %10 = add nsw i64 %indvars.iv, -1
  %11 = trunc nuw i64 %indvars.iv to i32
  %12 = icmp sgt i32 %11, 0
  br i1 %12, label %13, label %17

13:                                               ; preds = %9
  %14 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %10) #2
  %15 = load ptr, ptr %14, align 8, !tbaa !5
  %16 = icmp eq ptr %15, %1
  br i1 %16, label %.thread, label %9, !llvm.loop !9

17:                                               ; preds = %9
  %18 = icmp eq i64 %indvars.iv, 0
  br i1 %18, label %19, label %.thread

19:                                               ; preds = %17
  tail call void @_ZNK7sc_core14sc_export_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(112) %1, ptr noundef nonnull @_ZN7sc_core31SC_ID_SC_EXPORT_NOT_REGISTERED_E, ptr noundef null)
  br label %.thread

.thread:                                          ; preds = %13, %19, %17
  %20 = tail call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  %21 = add nsw i32 %20, -1
  %22 = sext i32 %21 to i64
  %23 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %22) #2
  %24 = load ptr, ptr %23, align 8, !tbaa !5
  %sext = shl i64 %10, 32
  %25 = ashr exact i64 %sext, 32
  %26 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %25) #2
  store ptr %24, ptr %26, align 8, !tbaa !5
  %27 = tail call noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  %28 = add nsw i32 %27, -1
  %29 = sext i32 %28 to i64
  tail call void @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %29)
  br label %30

30:                                               ; preds = %2, %.thread
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core14sc_export_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(112), ptr noundef, ptr noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core18sc_export_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core14sc_export_baseESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass