; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int/sc_nbutils.ll (ZN5sc_dt8fsm_moveEcRiS0_S0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN5sc_dt15NB_DEFAULT_BASEE = external constant i32, align 4
@.str.12 = external hidden unnamed_addr constant [29 x i8], align 1
@.str.13 = external hidden unnamed_addr constant [93 x i8], align 1
@__PRETTY_FUNCTION__._ZN5sc_dt8fsm_moveEcRiS0_S0_ = external hidden unnamed_addr constant [75 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN5sc_dt8fsm_moveEcRiS0_S0_(i8 noundef signext %0, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 4 dereferenceable(4) %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  store i8 %0, ptr %6, align 1, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !8
  store ptr %2, ptr %8, align 8, !tbaa !8
  store ptr %3, ptr %9, align 8, !tbaa !8
  %10 = load ptr, ptr %9, align 8, !tbaa !8
  %11 = load i32, ptr %10, align 4, !tbaa !10
  switch i32 %11, label %57 [
    i32 0, label %12
    i32 1, label %29
    i32 2, label %48
    i32 3, label %71
  ]

12:                                               ; preds = %4
  %13 = load i8, ptr %6, align 1, !tbaa !5
  %14 = sext i8 %13 to i32
  switch i32 %14, label %24 [
    i32 48, label %15
    i32 43, label %18
    i32 45, label %21
  ]

15:                                               ; preds = %12
  %16 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 1, ptr %16, align 4, !tbaa !10
  %17 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 1, ptr %17, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %72

18:                                               ; preds = %12
  %19 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 1, ptr %19, align 4, !tbaa !10
  %20 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 2, ptr %20, align 4, !tbaa !10
  store i32 1, ptr %5, align 4
  br label %72

21:                                               ; preds = %12
  %22 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 -1, ptr %22, align 4, !tbaa !10
  %23 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 2, ptr %23, align 4, !tbaa !10
  store i32 1, ptr %5, align 4
  br label %72

24:                                               ; preds = %12
  %25 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 1, ptr %25, align 4, !tbaa !10
  %26 = load i32, ptr @_ZN5sc_dt15NB_DEFAULT_BASEE, align 4, !tbaa !10
  %27 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 %26, ptr %27, align 4, !tbaa !10
  %28 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %28, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %72

29:                                               ; preds = %4
  %30 = load i8, ptr %6, align 1, !tbaa !5
  %31 = sext i8 %30 to i32
  switch i32 %31, label %44 [
    i32 120, label %32
    i32 88, label %32
    i32 100, label %35
    i32 68, label %35
    i32 111, label %38
    i32 79, label %38
    i32 98, label %41
    i32 66, label %41
  ]

32:                                               ; preds = %29, %29
  %33 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 16, ptr %33, align 4, !tbaa !10
  %34 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %34, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %72

35:                                               ; preds = %29, %29
  %36 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 10, ptr %36, align 4, !tbaa !10
  %37 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %37, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %72

38:                                               ; preds = %29, %29
  %39 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 8, ptr %39, align 4, !tbaa !10
  %40 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %40, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %72

41:                                               ; preds = %29, %29
  %42 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 2, ptr %42, align 4, !tbaa !10
  %43 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %43, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %72

44:                                               ; preds = %29
  %45 = load i32, ptr @_ZN5sc_dt15NB_DEFAULT_BASEE, align 4, !tbaa !10
  %46 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 %45, ptr %46, align 4, !tbaa !10
  %47 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %47, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %72

48:                                               ; preds = %4
  %49 = load i8, ptr %6, align 1, !tbaa !5
  %50 = sext i8 %49 to i32
  switch i32 %50, label %53 [
    i32 48, label %51
  ]

51:                                               ; preds = %48
  %52 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 1, ptr %52, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %72

53:                                               ; preds = %48
  %54 = load i32, ptr @_ZN5sc_dt15NB_DEFAULT_BASEE, align 4, !tbaa !10
  %55 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 %54, ptr %55, align 4, !tbaa !10
  %56 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %56, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %72

57:                                               ; preds = %4
  %58 = load ptr, ptr %9, align 8, !tbaa !8
  %59 = load i32, ptr %58, align 4, !tbaa !10
  %60 = icmp sle i32 0, %59
  br i1 %60, label %61, label %65

61:                                               ; preds = %57
  %62 = load ptr, ptr %9, align 8, !tbaa !8
  %63 = load i32, ptr %62, align 4, !tbaa !10
  %64 = icmp sle i32 %63, 3
  br label %65

65:                                               ; preds = %61, %57
  %66 = phi i1 [ false, %57 ], [ %64, %61 ]
  br i1 %66, label %67, label %68

67:                                               ; preds = %65
  br label %70

68:                                               ; preds = %65
  call void @__assert_fail(ptr noundef @.str.12, ptr noundef @.str.13, i32 noundef 163, ptr noundef @__PRETTY_FUNCTION__._ZN5sc_dt8fsm_moveEcRiS0_S0_) #2
  unreachable

69:                                               ; No predecessors!
  br label %70

70:                                               ; preds = %69, %67
  br label %71

71:                                               ; preds = %70, %4
  store i32 0, ptr %5, align 4
  br label %72

72:                                               ; preds = %71, %53, %51, %44, %41, %38, %35, %32, %24, %21, %18, %15
  %73 = load i32, ptr %5, align 4
  ret i32 %73
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN5sc_dt15NB_DEFAULT_BASEE = external local_unnamed_addr constant i32, align 4
@.str.12 = external hidden unnamed_addr constant [29 x i8], align 1
@.str.13 = external hidden unnamed_addr constant [93 x i8], align 1
@__PRETTY_FUNCTION__._ZN5sc_dt8fsm_moveEcRiS0_S0_ = external hidden unnamed_addr constant [75 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef range(i32 0, 3) i32 @_ZN5sc_dt8fsm_moveEcRiS0_S0_(i8 noundef signext %0, ptr nocapture noundef nonnull writeonly align 4 dereferenceable(4) %1, ptr nocapture noundef nonnull writeonly align 4 dereferenceable(4) %2, ptr nocapture noundef nonnull align 4 dereferenceable(4) %3) local_unnamed_addr #0 {
  %5 = load i32, ptr %3, align 4, !tbaa !5
  switch i32 %5, label %.critedge [
    i32 0, label %6
    i32 1, label %12
    i32 2, label %19
    i32 3, label %22
  ]

6:                                                ; preds = %4
  switch i8 %0, label %10 [
    i8 48, label %7
    i8 43, label %8
    i8 45, label %9
  ]

7:                                                ; preds = %6
  store i32 1, ptr %2, align 4, !tbaa !5
  br label %.sink.split

8:                                                ; preds = %6
  store i32 1, ptr %2, align 4, !tbaa !5
  br label %.sink.split

9:                                                ; preds = %6
  store i32 -1, ptr %2, align 4, !tbaa !5
  br label %.sink.split

10:                                               ; preds = %6
  store i32 1, ptr %2, align 4, !tbaa !5
  %11 = load i32, ptr @_ZN5sc_dt15NB_DEFAULT_BASEE, align 4, !tbaa !5
  store i32 %11, ptr %1, align 4, !tbaa !5
  br label %.sink.split

12:                                               ; preds = %4
  switch i8 %0, label %17 [
    i8 120, label %13
    i8 88, label %13
    i8 100, label %14
    i8 68, label %14
    i8 111, label %15
    i8 79, label %15
    i8 98, label %16
    i8 66, label %16
  ]

13:                                               ; preds = %12, %12
  store i32 16, ptr %1, align 4, !tbaa !5
  br label %.sink.split

14:                                               ; preds = %12, %12
  store i32 10, ptr %1, align 4, !tbaa !5
  br label %.sink.split

15:                                               ; preds = %12, %12
  store i32 8, ptr %1, align 4, !tbaa !5
  br label %.sink.split

16:                                               ; preds = %12, %12
  store i32 2, ptr %1, align 4, !tbaa !5
  br label %.sink.split

17:                                               ; preds = %12
  %18 = load i32, ptr @_ZN5sc_dt15NB_DEFAULT_BASEE, align 4, !tbaa !5
  store i32 %18, ptr %1, align 4, !tbaa !5
  br label %.sink.split

19:                                               ; preds = %4
  %cond = icmp eq i8 %0, 48
  br i1 %cond, label %.sink.split, label %20

20:                                               ; preds = %19
  %21 = load i32, ptr @_ZN5sc_dt15NB_DEFAULT_BASEE, align 4, !tbaa !5
  store i32 %21, ptr %1, align 4, !tbaa !5
  br label %.sink.split

.critedge:                                        ; preds = %4
  tail call void @__assert_fail(ptr noundef nonnull @.str.12, ptr noundef nonnull @.str.13, i32 noundef 163, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN5sc_dt8fsm_moveEcRiS0_S0_) #2
  unreachable

.sink.split:                                      ; preds = %19, %7, %8, %9, %10, %13, %14, %15, %16, %17, %20
  %.sink = phi i32 [ 3, %20 ], [ 3, %17 ], [ 3, %16 ], [ 3, %15 ], [ 3, %14 ], [ 3, %13 ], [ 3, %10 ], [ 2, %9 ], [ 2, %8 ], [ 1, %7 ], [ 1, %19 ]
  %.0.ph = phi i32 [ 0, %20 ], [ 0, %17 ], [ 2, %16 ], [ 2, %15 ], [ 2, %14 ], [ 2, %13 ], [ 0, %10 ], [ 1, %9 ], [ 1, %8 ], [ 0, %7 ], [ 0, %19 ]
  store i32 %.sink, ptr %3, align 4, !tbaa !5
  br label %22

22:                                               ; preds = %.sink.split, %4
  %.0 = phi i32 [ 0, %4 ], [ %.0.ph, %.sink.split ]
  ret i32 %.0
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass