; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/synth/prime_flag (prime_numgen)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_bv" = type { %"class.sc_dt::sc_bv_base" }
%"class.sc_dt::sc_bv_base" = type { %"class.sc_dt::sc_proxy", i32, i32, ptr }
%"class.sc_dt::sc_proxy" = type { ptr }
%struct.prime_numgen = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZZN12prime_numgen5entryEvE2p2 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE2p3 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE2p5 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE2p7 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE3p11 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE3p13 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE3p17 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE3p19 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE3p23 = external hidden global i32, align 4
@_ZZN12prime_numgen5entryEvE3p29 = external hidden global i32, align 4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12prime_numgen5entryEv(ptr noundef nonnull align 8 dereferenceable(440) %0) #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca %"class.sc_dt::sc_bv", align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %9 = load ptr, ptr %2, align 8
  %10 = getelementptr inbounds %struct.prime_numgen, ptr %9, i32 0, i32 3
  %11 = load ptr, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  store i8 0, ptr %3, align 1, !tbaa !41
  %12 = load ptr, ptr %11, align 8, !tbaa !42
  %13 = getelementptr inbounds ptr, ptr %12, i64 14
  %14 = load ptr, ptr %13, align 8
  call void %14(ptr noundef nonnull align 8 dereferenceable(224) %11, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  br label %15

15:                                               ; preds = %228, %1
  %16 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %17 = icmp ne i32 %16, 0
  br i1 %17, label %18, label %67

18:                                               ; preds = %15
  %19 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %20 = icmp ne i32 %19, 0
  br i1 %20, label %67, label %21

21:                                               ; preds = %18
  %22 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %23 = icmp ne i32 %22, 0
  br i1 %23, label %67, label %24

24:                                               ; preds = %21
  %25 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %26 = icmp ne i32 %25, 0
  br i1 %26, label %67, label %27

27:                                               ; preds = %24
  %28 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %67, label %30

30:                                               ; preds = %27
  %31 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %32 = icmp ne i32 %31, 0
  br i1 %32, label %67, label %33

33:                                               ; preds = %30
  %34 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %35 = icmp ne i32 %34, 0
  br i1 %35, label %67, label %36

36:                                               ; preds = %33
  %37 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %38 = icmp ne i32 %37, 0
  br i1 %38, label %67, label %39

39:                                               ; preds = %36
  %40 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !44
  %41 = icmp ne i32 %40, 0
  br i1 %41, label %67, label %42

42:                                               ; preds = %39
  %43 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !44
  %44 = icmp ne i32 %43, 0
  br i1 %44, label %67, label %45

45:                                               ; preds = %42
  %46 = getelementptr inbounds %struct.prime_numgen, ptr %9, i32 0, i32 3
  %47 = load ptr, ptr %46, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #3
  store i8 1, ptr %4, align 1, !tbaa !41
  %48 = load ptr, ptr %47, align 8, !tbaa !42
  %49 = getelementptr inbounds ptr, ptr %48, i64 14
  %50 = load ptr, ptr %49, align 8
  call void %50(ptr noundef nonnull align 8 dereferenceable(224) %47, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #3
  %51 = getelementptr inbounds %struct.prime_numgen, ptr %9, i32 0, i32 4
  %52 = load ptr, ptr %51, align 8, !tbaa !45
  call void @llvm.lifetime.start.p0(i64 24, ptr %5) #3
  %53 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  call void @_ZN5sc_dt5sc_bvILi16EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24) %5, i32 noundef %53)
  %54 = load ptr, ptr %52, align 8, !tbaa !42
  %55 = getelementptr inbounds ptr, ptr %54, i64 9
  %56 = load ptr, ptr %55, align 8
  invoke void %56(ptr noundef nonnull align 8 dereferenceable(232) %52, ptr noundef nonnull align 8 dereferenceable(24) %5)
          to label %57 unwind label %63

57:                                               ; preds = %45
  call void @_ZN5sc_dt10sc_bv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  %58 = getelementptr inbounds %struct.prime_numgen, ptr %9, i32 0, i32 3
  %59 = load ptr, ptr %58, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  store i8 0, ptr %8, align 1, !tbaa !41
  %60 = load ptr, ptr %59, align 8, !tbaa !42
  %61 = getelementptr inbounds ptr, ptr %60, i64 14
  %62 = load ptr, ptr %61, align 8
  call void %62(ptr noundef nonnull align 8 dereferenceable(224) %59, ptr noundef nonnull align 1 dereferenceable(1) %8)
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  br label %67

63:                                               ; preds = %45
  %64 = landingpad { ptr, i32 }
          cleanup
  %65 = extractvalue { ptr, i32 } %64, 0
  store ptr %65, ptr %6, align 8
  %66 = extractvalue { ptr, i32 } %64, 1
  store i32 %66, ptr %7, align 4
  call void @_ZN5sc_dt10sc_bv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #3
  br label %229

67:                                               ; preds = %57, %42, %39, %36, %33, %30, %27, %24, %21, %18, %15
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  %68 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %69 = icmp ne i32 %68, 0
  br i1 %69, label %70, label %80

70:                                               ; preds = %67
  %71 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %72 = icmp ne i32 %71, 0
  br i1 %72, label %73, label %80

73:                                               ; preds = %70
  %74 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %75 = add i32 %74, -1
  store i32 %75, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %76 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %77 = add i32 %76, -1
  store i32 %77, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %78 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %79 = add i32 %78, 1
  store i32 %79, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  br label %228

80:                                               ; preds = %70, %67
  %81 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %82 = icmp ne i32 %81, 0
  br i1 %82, label %83, label %97

83:                                               ; preds = %80
  %84 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %85 = icmp ne i32 %84, 0
  br i1 %85, label %86, label %97

86:                                               ; preds = %83
  %87 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %88 = add i32 %87, -1
  store i32 %88, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %89 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %90 = add i32 %89, -1
  store i32 %90, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %91 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %92 = add i32 %91, 1
  store i32 %92, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %93 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %94 = add i32 %93, 1
  store i32 %94, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %95 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %96 = add i32 %95, 1
  store i32 %96, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  br label %227

97:                                               ; preds = %83, %80
  %98 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %99 = icmp ne i32 %98, 0
  br i1 %99, label %100, label %110

100:                                              ; preds = %97
  %101 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %102 = icmp ne i32 %101, 0
  br i1 %102, label %103, label %110

103:                                              ; preds = %100
  %104 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %105 = add i32 %104, -1
  store i32 %105, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %106 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %107 = add i32 %106, -1
  store i32 %107, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %108 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %109 = add i32 %108, 1
  store i32 %109, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  br label %226

110:                                              ; preds = %100, %97
  %111 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %112 = icmp ne i32 %111, 0
  br i1 %112, label %113, label %123

113:                                              ; preds = %110
  %114 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %115 = icmp ne i32 %114, 0
  br i1 %115, label %116, label %123

116:                                              ; preds = %113
  %117 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %118 = add i32 %117, -1
  store i32 %118, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %119 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %120 = add i32 %119, -1
  store i32 %120, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %121 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !44
  %122 = add i32 %121, 1
  store i32 %122, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !44
  br label %225

123:                                              ; preds = %113, %110
  %124 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %125 = icmp ne i32 %124, 0
  br i1 %125, label %126, label %136

126:                                              ; preds = %123
  %127 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %128 = icmp ne i32 %127, 0
  br i1 %128, label %129, label %136

129:                                              ; preds = %126
  %130 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %131 = add i32 %130, -1
  store i32 %131, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %132 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %133 = add i32 %132, -1
  store i32 %133, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %134 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !44
  %135 = add i32 %134, 1
  store i32 %135, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !44
  br label %224

136:                                              ; preds = %126, %123
  %137 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !44
  %138 = icmp ne i32 %137, 0
  br i1 %138, label %139, label %146

139:                                              ; preds = %136
  %140 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !44
  %141 = add i32 %140, -1
  store i32 %141, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !44
  %142 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %143 = add i32 %142, 1
  store i32 %143, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %144 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %145 = add i32 %144, 1
  store i32 %145, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  br label %223

146:                                              ; preds = %136
  %147 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !44
  %148 = icmp ne i32 %147, 0
  br i1 %148, label %149, label %156

149:                                              ; preds = %146
  %150 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !44
  %151 = add i32 %150, -1
  store i32 %151, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !44
  %152 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %153 = add i32 %152, 1
  store i32 %153, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %154 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %155 = add i32 %154, 1
  store i32 %155, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  br label %222

156:                                              ; preds = %146
  %157 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %158 = icmp ne i32 %157, 0
  br i1 %158, label %159, label %166

159:                                              ; preds = %156
  %160 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %161 = add i32 %160, -1
  store i32 %161, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !44
  %162 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %163 = add i32 %162, 1
  store i32 %163, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %164 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %165 = add i32 %164, 1
  store i32 %165, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  br label %221

166:                                              ; preds = %156
  %167 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  %168 = icmp ne i32 %167, 0
  br i1 %168, label %169, label %170

169:                                              ; preds = %166
  store i32 0, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !44
  br label %220

170:                                              ; preds = %166
  %171 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %172 = icmp ne i32 %171, 0
  br i1 %172, label %173, label %178

173:                                              ; preds = %170
  %174 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %175 = add i32 %174, -1
  store i32 %175, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %176 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %177 = add i32 %176, 1
  store i32 %177, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  br label %219

178:                                              ; preds = %170
  %179 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %180 = icmp ne i32 %179, 0
  br i1 %180, label %181, label %186

181:                                              ; preds = %178
  %182 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %183 = add i32 %182, -1
  store i32 %183, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %184 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  %185 = add i32 %184, 1
  store i32 %185, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !44
  br label %218

186:                                              ; preds = %178
  %187 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %188 = icmp ne i32 %187, 0
  br i1 %188, label %189, label %201

189:                                              ; preds = %186
  %190 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %191 = icmp ne i32 %190, 0
  br i1 %191, label %192, label %201

192:                                              ; preds = %189
  %193 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %194 = add i32 %193, -1
  store i32 %194, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %195 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %196 = add i32 %195, -1
  store i32 %196, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !44
  %197 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %198 = add i32 %197, 1
  store i32 %198, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %199 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %200 = add i32 %199, 1
  store i32 %200, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  br label %217

201:                                              ; preds = %189, %186
  %202 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %203 = icmp ne i32 %202, 0
  br i1 %203, label %204, label %211

204:                                              ; preds = %201
  %205 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %206 = add i32 %205, -1
  store i32 %206, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !44
  %207 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %208 = add i32 %207, 1
  store i32 %208, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !44
  %209 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %210 = add i32 %209, 1
  store i32 %210, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  br label %216

211:                                              ; preds = %201
  %212 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %213 = add i32 %212, 1
  store i32 %213, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !44
  %214 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  %215 = add i32 %214, 1
  store i32 %215, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !44
  br label %216

216:                                              ; preds = %211, %204
  br label %217

217:                                              ; preds = %216, %192
  br label %218

218:                                              ; preds = %217, %181
  br label %219

219:                                              ; preds = %218, %173
  br label %220

220:                                              ; preds = %219, %169
  br label %221

221:                                              ; preds = %220, %159
  br label %222

222:                                              ; preds = %221, %149
  br label %223

223:                                              ; preds = %222, %139
  br label %224

224:                                              ; preds = %223, %129
  br label %225

225:                                              ; preds = %224, %116
  br label %226

226:                                              ; preds = %225, %103
  br label %227

227:                                              ; preds = %226, %86
  br label %228

228:                                              ; preds = %227, %73
  br label %15, !llvm.loop !46

229:                                              ; preds = %63
  %230 = load ptr, ptr %6, align 8
  %231 = load i32, ptr %7, align 4
  %232 = insertvalue { ptr, i32 } poison, ptr %230, 0
  %233 = insertvalue { ptr, i32 } %232, i32 %231, 1
  resume { ptr, i32 } %233
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt5sc_bvILi16EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt10sc_bv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 424}
!10 = !{!"_ZTS12prime_numgen", !11, i64 0, !33, i64 232, !6, i64 416, !6, i64 424, !6, i64 432}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !24, i64 112, !25, i64 120, !27, i64 144, !29, i64 168, !31, i64 192, !6, i64 200, !32, i64 208, !6, i64 216, !6, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !6, i64 96, !6, i64 104}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !7, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!23 = !{!"long", !7, i64 0}
!24 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !26, i64 8, !6, i64 16}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !28, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !30, i64 8, !6, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!31 = !{!"bool", !7, i64 0}
!32 = !{!"int", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !6, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !6, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = !{!31, !31, i64 0}
!42 = !{!43, !43, i64 0}
!43 = !{!"vtable pointer", !8, i64 0}
!44 = !{!32, !32, i64 0}
!45 = !{!10, !6, i64 432}
!46 = distinct !{!46, !47}
!47 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_bv" = type { %"class.sc_dt::sc_bv_base" }
%"class.sc_dt::sc_bv_base" = type { %"class.sc_dt::sc_proxy", i32, i32, ptr }
%"class.sc_dt::sc_proxy" = type { ptr }

@_ZZN12prime_numgen5entryEvE2p2 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE2p3 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE2p5 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE2p7 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE3p11 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE3p13 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE3p17 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE3p19 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE3p23 = external hidden local_unnamed_addr global i32, align 4
@_ZZN12prime_numgen5entryEvE3p29 = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN12prime_numgen5entryEv(ptr noundef nonnull align 8 dereferenceable(440) %0) local_unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca %"class.sc_dt::sc_bv", align 8
  %5 = alloca i8, align 1
  %6 = getelementptr inbounds i8, ptr %0, i64 424
  %7 = load ptr, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #4
  store i8 0, ptr %2, align 1, !tbaa !40
  %8 = load ptr, ptr %7, align 8, !tbaa !41
  %9 = getelementptr inbounds i8, ptr %8, i64 112
  %10 = load ptr, ptr %9, align 8
  call void %10(ptr noundef nonnull align 8 dereferenceable(224) %7, ptr noundef nonnull align 1 dereferenceable(1) %2)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #4
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %11 = getelementptr inbounds i8, ptr %0, i64 432
  %.pre = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4
  %.pre41 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4
  %.pre42 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4
  br label %12

12:                                               ; preds = %.backedge, %1
  %13 = phi i32 [ %.pre42, %1 ], [ %.be, %.backedge ]
  %14 = phi i32 [ %.pre41, %1 ], [ %.be43, %.backedge ]
  %15 = phi i32 [ %.pre, %1 ], [ %.be44, %.backedge ]
  %16 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %17 = icmp eq i32 %16, 0
  %18 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4
  %19 = icmp ne i32 %18, 0
  %or.cond = select i1 %17, i1 true, i1 %19
  %20 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4
  %21 = icmp ne i32 %20, 0
  %or.cond3 = select i1 %or.cond, i1 true, i1 %21
  %22 = icmp ne i32 %15, 0
  %or.cond5 = select i1 %or.cond3, i1 true, i1 %22
  %23 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4
  %24 = icmp ne i32 %23, 0
  %or.cond7 = select i1 %or.cond5, i1 true, i1 %24
  %25 = icmp ne i32 %14, 0
  %or.cond9 = select i1 %or.cond7, i1 true, i1 %25
  %26 = icmp ne i32 %13, 0
  %or.cond11 = select i1 %or.cond9, i1 true, i1 %26
  %27 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4
  %28 = icmp ne i32 %27, 0
  %or.cond13 = select i1 %or.cond11, i1 true, i1 %28
  %29 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4
  %30 = icmp ne i32 %29, 0
  %or.cond15 = select i1 %or.cond13, i1 true, i1 %30
  %31 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4
  %32 = icmp ne i32 %31, 0
  %or.cond17 = select i1 %or.cond15, i1 true, i1 %32
  br i1 %or.cond17, label %50, label %33

33:                                               ; preds = %12
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #4
  store i8 1, ptr %3, align 1, !tbaa !40
  %35 = load ptr, ptr %34, align 8, !tbaa !41
  %36 = getelementptr inbounds i8, ptr %35, i64 112
  %37 = load ptr, ptr %36, align 8
  call void %37(ptr noundef nonnull align 8 dereferenceable(224) %34, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #4
  %38 = load ptr, ptr %11, align 8, !tbaa !44
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %4) #4
  %39 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  call void @_ZN5sc_dt5sc_bvILi16EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24) %4, i32 noundef %39)
  %40 = load ptr, ptr %38, align 8, !tbaa !41
  %41 = getelementptr inbounds i8, ptr %40, i64 72
  %42 = load ptr, ptr %41, align 8
  invoke void %42(ptr noundef nonnull align 8 dereferenceable(232) %38, ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %43 unwind label %48

43:                                               ; preds = %33
  call void @_ZN5sc_dt10sc_bv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %4) #4
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #4
  store i8 0, ptr %5, align 1, !tbaa !40
  %45 = load ptr, ptr %44, align 8, !tbaa !41
  %46 = getelementptr inbounds i8, ptr %45, i64 112
  %47 = load ptr, ptr %46, align 8
  call void %47(ptr noundef nonnull align 8 dereferenceable(224) %44, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #4
  br label %50

48:                                               ; preds = %33
  %49 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt10sc_bv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %4) #4
  resume { ptr, i32 } %49

50:                                               ; preds = %43, %12
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %51 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4
  %52 = icmp ne i32 %51, 0
  %53 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4
  %54 = icmp ne i32 %53, 0
  %or.cond19 = select i1 %52, i1 %54, i1 false
  br i1 %or.cond19, label %55, label %60

55:                                               ; preds = %50
  %56 = add i32 %51, -1
  store i32 %56, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !43
  %57 = add i32 %53, -1
  store i32 %57, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !43
  %58 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !43
  %59 = add i32 %58, 1
  store i32 %59, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !43
  br label %.backedge

60:                                               ; preds = %50
  %61 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !43
  %62 = icmp ne i32 %61, 0
  %63 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4
  %64 = icmp ne i32 %63, 0
  %or.cond21 = select i1 %62, i1 %64, i1 false
  br i1 %or.cond21, label %65, label %73

65:                                               ; preds = %60
  %66 = add i32 %61, -1
  store i32 %66, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !43
  %67 = add i32 %63, -1
  store i32 %67, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !43
  %68 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %69 = add i32 %68, 1
  store i32 %69, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %70 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %71 = add i32 %70, 1
  store i32 %71, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %72 = add i32 %53, 1
  store i32 %72, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !43
  br label %.backedge

.backedge:                                        ; preds = %65, %86, %101, %112, %119, %126, %136, %132, %123, %117, %107, %94, %76, %55
  %.be = phi i32 [ %67, %65 ], [ %63, %86 ], [ %63, %101 ], [ %63, %112 ], [ 0, %119 ], [ 0, %126 ], [ 0, %136 ], [ 0, %132 ], [ 0, %123 ], [ 0, %117 ], [ %63, %107 ], [ %63, %94 ], [ %78, %76 ], [ %59, %55 ]
  %.be43 = phi i32 [ %72, %65 ], [ %53, %86 ], [ %53, %101 ], [ %53, %112 ], [ %120, %119 ], [ 0, %126 ], [ 0, %136 ], [ 0, %132 ], [ 1, %123 ], [ %53, %117 ], [ %53, %107 ], [ %53, %94 ], [ %53, %76 ], [ %57, %55 ]
  %.be44 = phi i32 [ %51, %65 ], [ %51, %86 ], [ %103, %101 ], [ %114, %112 ], [ %51, %119 ], [ %128, %126 ], [ %51, %136 ], [ %51, %132 ], [ %51, %123 ], [ %51, %117 ], [ %51, %107 ], [ %51, %94 ], [ %51, %76 ], [ %56, %55 ]
  br label %12, !llvm.loop !45

73:                                               ; preds = %60
  %74 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %75 = icmp ne i32 %74, 0
  %or.cond23 = select i1 %75, i1 %64, i1 false
  br i1 %or.cond23, label %76, label %81

76:                                               ; preds = %73
  %77 = add i32 %74, -1
  store i32 %77, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %78 = add i32 %63, -1
  store i32 %78, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !43
  %79 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !43
  %80 = add i32 %79, 1
  store i32 %80, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !43
  br label %.backedge

81:                                               ; preds = %73
  %82 = load i32, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %83 = icmp ne i32 %82, 0
  %84 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4
  %85 = icmp ne i32 %84, 0
  %or.cond25 = select i1 %83, i1 %85, i1 false
  br i1 %or.cond25, label %86, label %91

86:                                               ; preds = %81
  %87 = add i32 %82, -1
  store i32 %87, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %88 = add i32 %84, -1
  store i32 %88, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !43
  %89 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !43
  %90 = add i32 %89, 1
  store i32 %90, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !43
  br label %.backedge

91:                                               ; preds = %81
  %92 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4
  %93 = icmp ne i32 %92, 0
  %or.cond27 = select i1 %75, i1 %93, i1 false
  br i1 %or.cond27, label %94, label %99

94:                                               ; preds = %91
  %95 = add i32 %74, -1
  store i32 %95, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %96 = add i32 %92, -1
  store i32 %96, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !43
  %97 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !43
  %98 = add i32 %97, 1
  store i32 %98, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !43
  br label %.backedge

99:                                               ; preds = %91
  %100 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !43
  %.not = icmp eq i32 %100, 0
  br i1 %.not, label %105, label %101

101:                                              ; preds = %99
  %102 = add i32 %100, -1
  store i32 %102, ptr @_ZZN12prime_numgen5entryEvE3p29, align 4, !tbaa !43
  %103 = add i32 %51, 1
  store i32 %103, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !43
  %104 = add i32 %92, 1
  store i32 %104, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !43
  br label %.backedge

105:                                              ; preds = %99
  %106 = load i32, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !43
  %.not40 = icmp eq i32 %106, 0
  br i1 %.not40, label %111, label %107

107:                                              ; preds = %105
  %108 = add i32 %106, -1
  store i32 %108, ptr @_ZZN12prime_numgen5entryEvE3p23, align 4, !tbaa !43
  %109 = add i32 %61, 1
  store i32 %109, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !43
  %110 = add i32 %84, 1
  store i32 %110, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !43
  br label %.backedge

111:                                              ; preds = %105
  br i1 %85, label %112, label %116

112:                                              ; preds = %111
  %113 = add i32 %84, -1
  store i32 %113, ptr @_ZZN12prime_numgen5entryEvE3p19, align 4, !tbaa !43
  %114 = add i32 %51, 1
  store i32 %114, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !43
  %115 = add i32 %92, 1
  store i32 %115, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !43
  br label %.backedge

116:                                              ; preds = %111
  br i1 %64, label %117, label %118

117:                                              ; preds = %116
  store i32 0, ptr @_ZZN12prime_numgen5entryEvE3p17, align 4, !tbaa !43
  br label %.backedge

118:                                              ; preds = %116
  br i1 %54, label %119, label %122

119:                                              ; preds = %118
  %120 = add i32 %53, -1
  store i32 %120, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !43
  %121 = add i32 %92, 1
  store i32 %121, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !43
  br label %.backedge

122:                                              ; preds = %118
  br i1 %93, label %123, label %125

123:                                              ; preds = %122
  %124 = add i32 %92, -1
  store i32 %124, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !43
  store i32 1, ptr @_ZZN12prime_numgen5entryEvE3p13, align 4, !tbaa !43
  br label %.backedge

125:                                              ; preds = %122
  %or.cond29 = and i1 %52, %83
  br i1 %or.cond29, label %126, label %131

126:                                              ; preds = %125
  %127 = add i32 %82, -1
  store i32 %127, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %128 = add i32 %51, -1
  store i32 %128, ptr @_ZZN12prime_numgen5entryEvE2p7, align 4, !tbaa !43
  %129 = add i32 %74, 1
  store i32 %129, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %130 = add i32 %61, 1
  store i32 %130, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !43
  br label %.backedge

131:                                              ; preds = %125
  br i1 %83, label %132, label %136

132:                                              ; preds = %131
  %133 = add i32 %82, -1
  store i32 %133, ptr @_ZZN12prime_numgen5entryEvE2p2, align 4, !tbaa !43
  %134 = add i32 %74, 1
  store i32 %134, ptr @_ZZN12prime_numgen5entryEvE2p3, align 4, !tbaa !43
  %135 = add i32 %61, 1
  store i32 %135, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !43
  br label %.backedge

136:                                              ; preds = %131
  %137 = add i32 %61, 1
  store i32 %137, ptr @_ZZN12prime_numgen5entryEvE2p5, align 4, !tbaa !43
  store i32 1, ptr @_ZZN12prime_numgen5entryEvE3p11, align 4, !tbaa !43
  br label %.backedge
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt5sc_bvILi16EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #2 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt10sc_bv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 424}
!6 = !{!"_ZTS12prime_numgen", !7, i64 0, !32, i64 232, !9, i64 416, !9, i64 424, !9, i64 432}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core5sc_inIbEE", !33, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!33 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !35, i64 0, !9, i64 120, !36, i64 128}
!35 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!36 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!40 = !{!30, !30, i64 0}
!41 = !{!42, !42, i64 0}
!42 = !{!"vtable pointer", !11, i64 0}
!43 = !{!31, !31, i64 0}
!44 = !{!6, !9, i64 432}
!45 = distinct !{!45, !46}
!46 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass