; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/utils (sc_hash)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_phash_base_iter" = type <{ ptr, ptr, ptr, ptr, i32, [4 x i8] }>
%"class.sc_core::sc_phash_base" = type { ptr, i32, i32, i32, i32, double, ptr, ptr, ptr }
%"class.sc_core::sc_phash_elem" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core18sc_phash_base_iter5resetEPNS_13sc_phash_baseE(ptr noundef nonnull align 8 dereferenceable(36) %0, ptr noundef %1) #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 0
  store ptr %8, ptr %9, align 8, !tbaa !9
  %10 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 4
  store i32 0, ptr %10, align 8, !tbaa !12
  %11 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 1
  store ptr null, ptr %11, align 8, !tbaa !13
  %12 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 2
  store ptr null, ptr %12, align 8, !tbaa !14
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  %13 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 4
  %14 = load i32, ptr %13, align 8, !tbaa !12
  store i32 %14, ptr %5, align 4, !tbaa !15
  br label %15

15:                                               ; preds = %55, %2
  %16 = load i32, ptr %5, align 4, !tbaa !15
  %17 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 0
  %18 = load ptr, ptr %17, align 8, !tbaa !9
  %19 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %18, i32 0, i32 1
  %20 = load i32, ptr %19, align 8, !tbaa !16
  %21 = icmp slt i32 %16, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %15
  store i32 2, ptr %6, align 4
  br label %58

23:                                               ; preds = %15
  %24 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 0
  %25 = load ptr, ptr %24, align 8, !tbaa !9
  %26 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %25, i32 0, i32 6
  %27 = load ptr, ptr %26, align 8, !tbaa !19
  %28 = load i32, ptr %5, align 4, !tbaa !15
  %29 = sext i32 %28 to i64
  %30 = getelementptr inbounds ptr, ptr %27, i64 %29
  %31 = load ptr, ptr %30, align 8, !tbaa !5
  %32 = icmp ne ptr %31, null
  br i1 %32, label %33, label %54

33:                                               ; preds = %23
  %34 = load i32, ptr %5, align 4, !tbaa !15
  %35 = add nsw i32 %34, 1
  %36 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 4
  store i32 %35, ptr %36, align 8, !tbaa !12
  %37 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !9
  %39 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %38, i32 0, i32 6
  %40 = load ptr, ptr %39, align 8, !tbaa !19
  %41 = load i32, ptr %5, align 4, !tbaa !15
  %42 = sext i32 %41 to i64
  %43 = getelementptr inbounds ptr, ptr %40, i64 %42
  %44 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 3
  store ptr %43, ptr %44, align 8, !tbaa !20
  %45 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 3
  %46 = load ptr, ptr %45, align 8, !tbaa !20
  %47 = load ptr, ptr %46, align 8, !tbaa !5
  %48 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 1
  store ptr %47, ptr %48, align 8, !tbaa !13
  %49 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 1
  %50 = load ptr, ptr %49, align 8, !tbaa !13
  %51 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %50, i32 0, i32 2
  %52 = load ptr, ptr %51, align 8, !tbaa !21
  %53 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %7, i32 0, i32 2
  store ptr %52, ptr %53, align 8, !tbaa !14
  store i32 2, ptr %6, align 4
  br label %58

54:                                               ; preds = %23
  br label %55

55:                                               ; preds = %54
  %56 = load i32, ptr %5, align 4, !tbaa !15
  %57 = add nsw i32 %56, 1
  store i32 %57, ptr %5, align 4, !tbaa !15
  br label %15, !llvm.loop !23

58:                                               ; preds = %33, %22
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  br label %59

59:                                               ; preds = %58
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTSN7sc_core18sc_phash_base_iterE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !11, i64 32}
!11 = !{!"int", !7, i64 0}
!12 = !{!10, !11, i64 32}
!13 = !{!10, !6, i64 8}
!14 = !{!10, !6, i64 16}
!15 = !{!11, !11, i64 0}
!16 = !{!17, !11, i64 8}
!17 = !{!"_ZTSN7sc_core13sc_phash_baseE", !6, i64 0, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !18, i64 24, !6, i64 32, !6, i64 40, !6, i64 48}
!18 = !{!"double", !7, i64 0}
!19 = !{!17, !6, i64 32}
!20 = !{!10, !6, i64 24}
!21 = !{!22, !6, i64 16}
!22 = !{!"_ZTSN7sc_core13sc_phash_elemE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable
define dso_local void @_ZN7sc_core18sc_phash_base_iter5resetEPNS_13sc_phash_baseE(ptr nocapture noundef nonnull writeonly align 8 dereferenceable(36) %0, ptr noundef %1) local_unnamed_addr #0 align 2 {
  store ptr %1, ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 32
  store i32 0, ptr %3, align 8, !tbaa !11
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = getelementptr inbounds i8, ptr %0, i64 16
  %6 = getelementptr inbounds i8, ptr %1, i64 8
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %4, i8 0, i64 16, i1 false)
  %7 = load i32, ptr %6, align 8, !tbaa !12
  %8 = icmp sgt i32 %7, 0
  br i1 %8, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %2
  %9 = getelementptr inbounds i8, ptr %1, i64 32
  %10 = load ptr, ptr %9, align 8, !tbaa !15
  %wide.trip.count = zext nneg i32 %7 to i64
  br label %11

11:                                               ; preds = %.lr.ph, %22
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %22 ]
  %12 = getelementptr inbounds ptr, ptr %10, i64 %indvars.iv
  %13 = load ptr, ptr %12, align 8, !tbaa !16
  %.not = icmp eq ptr %13, null
  br i1 %.not, label %22, label %14

14:                                               ; preds = %11
  %15 = getelementptr inbounds ptr, ptr %10, i64 %indvars.iv
  %16 = trunc nuw nsw i64 %indvars.iv to i32
  %17 = add nuw nsw i32 %16, 1
  store i32 %17, ptr %3, align 8, !tbaa !11
  %18 = getelementptr inbounds i8, ptr %0, i64 24
  store ptr %15, ptr %18, align 8, !tbaa !17
  %19 = load ptr, ptr %15, align 8, !tbaa !16
  store ptr %19, ptr %4, align 8, !tbaa !18
  %20 = getelementptr inbounds i8, ptr %19, i64 16
  %21 = load ptr, ptr %20, align 8, !tbaa !19
  store ptr %21, ptr %5, align 8, !tbaa !21
  br label %.loopexit

22:                                               ; preds = %11
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.loopexit, label %11, !llvm.loop !22

.loopexit:                                        ; preds = %22, %2, %14
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { mustprogress nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7sc_core18sc_phash_base_iterE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !10, i64 32}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!6, !10, i64 32}
!12 = !{!13, !10, i64 8}
!13 = !{!"_ZTSN7sc_core13sc_phash_baseE", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !14, i64 24, !7, i64 32, !7, i64 40, !7, i64 48}
!14 = !{!"double", !8, i64 0}
!15 = !{!13, !7, i64 32}
!16 = !{!7, !7, i64 0}
!17 = !{!6, !7, i64 24}
!18 = !{!6, !7, i64 8}
!19 = !{!20, !7, i64 16}
!20 = !{!"_ZTSN7sc_core13sc_phash_elemE", !7, i64 0, !7, i64 8, !7, i64 16}
!21 = !{!6, !7, i64 16}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass