; LLVM IR from gem5/gem5 :: ext/nomali/lib/gpucontrol.ll (ZN6NoMali10GPUControl8writeRegENS_7RegAddrEj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.NoMali::RegAddr" = type { i32 }
%"class.NoMali::GPUBlock" = type { ptr, ptr, %"class.NoMali::RegVector" }
%"class.NoMali::RegVector" = type { %"class.std::vector.0" }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6NoMali10GPUControl8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 %1, i32 noundef %2) unnamed_addr #3 align 2 {
  %4 = alloca %"struct.NoMali::RegAddr", align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca %"struct.NoMali::RegAddr", align 4
  %8 = alloca %"struct.NoMali::RegAddr", align 4
  %9 = alloca %"struct.NoMali::RegAddr", align 4
  %10 = alloca %"struct.NoMali::RegAddr", align 4
  %11 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  store i32 %1, ptr %11, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  %12 = load ptr, ptr %5, align 8
  %13 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  %14 = load i32, ptr %13, align 4, !tbaa !11
  switch i32 %14, label %53 [
    i32 32, label %15
    i32 36, label %15
    i32 40, label %15
    i32 44, label %15
    i32 48, label %19
    i32 384, label %24
    i32 388, label %24
    i32 400, label %24
    i32 404, label %24
    i32 416, label %24
    i32 420, label %24
    i32 432, label %24
    i32 436, label %24
    i32 448, label %42
    i32 452, label %42
    i32 464, label %42
    i32 468, label %42
    i32 480, label %42
    i32 484, label %42
    i32 496, label %42
    i32 500, label %42
  ]

15:                                               ; preds = %3, %3, %3, %3
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %7, ptr align 4 %4, i64 4, i1 false), !tbaa.struct !13
  %16 = load i32, ptr %6, align 4, !tbaa !9
  %17 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %7, i32 0, i32 0
  %18 = load i32, ptr %17, align 4
  call void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %12, i32 %18, i32 noundef %16)
  br label %54

19:                                               ; preds = %3
  %20 = load i32, ptr %6, align 4, !tbaa !9
  %21 = load ptr, ptr %12, align 8, !tbaa !14
  %22 = getelementptr inbounds ptr, ptr %21, i64 8
  %23 = load ptr, ptr %22, align 8
  call void %23(ptr noundef nonnull align 8 dereferenceable(56) %12, i32 noundef %20)
  br label %54

24:                                               ; preds = %3, %3, %3, %3, %3, %3, %3, %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  %25 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  %26 = load i32, ptr %25, align 4, !tbaa !11
  %27 = sub i32 %26, 384
  %28 = add i32 320, %27
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %8, i32 noundef %28)
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %29 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  %30 = load i32, ptr %29, align 4, !tbaa !11
  %31 = sub i32 %30, 384
  %32 = add i32 256, %31
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %9, i32 noundef %32)
  %33 = load i32, ptr %6, align 4, !tbaa !9
  %34 = getelementptr inbounds %"class.NoMali::GPUBlock", ptr %12, i32 0, i32 2
  %35 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24) %34, ptr noundef nonnull align 4 dereferenceable(4) %9)
  %36 = load i32, ptr %35, align 4, !tbaa !9
  %37 = and i32 %33, %36
  %38 = getelementptr inbounds %"class.NoMali::GPUBlock", ptr %12, i32 0, i32 2
  %39 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24) %38, ptr noundef nonnull align 4 dereferenceable(4) %8)
  %40 = load i32, ptr %39, align 4, !tbaa !9
  %41 = or i32 %40, %37
  store i32 %41, ptr %39, align 4, !tbaa !9
  call void @_ZN6NoMali11GPUBlockInt14raiseInterruptEj(ptr noundef nonnull align 8 dereferenceable(56) %12, i32 noundef 1536)
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  br label %54

42:                                               ; preds = %3, %3, %3, %3, %3, %3, %3, %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %43 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  %44 = load i32, ptr %43, align 4, !tbaa !11
  %45 = sub i32 %44, 448
  %46 = add i32 320, %45
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %10, i32 noundef %46)
  %47 = load i32, ptr %6, align 4, !tbaa !9
  %48 = xor i32 %47, -1
  %49 = getelementptr inbounds %"class.NoMali::GPUBlock", ptr %12, i32 0, i32 2
  %50 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24) %49, ptr noundef nonnull align 4 dereferenceable(4) %10)
  %51 = load i32, ptr %50, align 4, !tbaa !9
  %52 = and i32 %51, %48
  store i32 %52, ptr %50, align 4, !tbaa !9
  call void @_ZN6NoMali11GPUBlockInt14raiseInterruptEj(ptr noundef nonnull align 8 dereferenceable(56) %12, i32 noundef 1536)
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  br label %54

53:                                               ; preds = %3
  br label %54

54:                                               ; preds = %53, %42, %24, %19, %15
  ret void
}

declare void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56), i32, i32 noundef) unnamed_addr #4

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #3 align 2

declare void @_ZN6NoMali11GPUBlockInt14raiseInterruptEj(ptr noundef nonnull align 8 dereferenceable(56), i32 noundef) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTSN6NoMali7RegAddrE", !10, i64 0}
!13 = !{i64 0, i64 4, !9}
!14 = !{!15, !15, i64 0}
!15 = !{!"vtable pointer", !8, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.NoMali::RegAddr" = type { i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6NoMali10GPUControl8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 %1, i32 noundef %2) unnamed_addr #2 align 2 {
  %4 = alloca %"struct.NoMali::RegAddr", align 4
  %5 = alloca %"struct.NoMali::RegAddr", align 4
  %6 = alloca %"struct.NoMali::RegAddr", align 4
  switch i32 %1, label %29 [
    i32 32, label %7
    i32 36, label %7
    i32 40, label %7
    i32 44, label %7
    i32 48, label %8
    i32 384, label %12
    i32 388, label %12
    i32 400, label %12
    i32 404, label %12
    i32 416, label %12
    i32 420, label %12
    i32 432, label %12
    i32 436, label %12
    i32 448, label %22
    i32 452, label %22
    i32 464, label %22
    i32 468, label %22
    i32 480, label %22
    i32 484, label %22
    i32 496, label %22
    i32 500, label %22
  ]

7:                                                ; preds = %3, %3, %3, %3
  tail call void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 %1, i32 noundef %2)
  br label %29

8:                                                ; preds = %3
  %9 = load ptr, ptr %0, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %9, i64 64
  %11 = load ptr, ptr %10, align 8
  tail call void %11(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 noundef %2)
  br label %29

12:                                               ; preds = %3, %3, %3, %3, %3, %3, %3, %3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #4
  %13 = add nsw i32 %1, -64
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %4, i32 noundef %13)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #4
  %14 = add nsw i32 %1, -128
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %5, i32 noundef %14)
  %15 = getelementptr inbounds i8, ptr %0, i64 16
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24) %15, ptr noundef nonnull align 4 dereferenceable(4) %5)
  %17 = load i32, ptr %16, align 4, !tbaa !8
  %18 = and i32 %17, %2
  %19 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24) %15, ptr noundef nonnull align 4 dereferenceable(4) %4)
  %20 = load i32, ptr %19, align 4, !tbaa !8
  %21 = or i32 %20, %18
  store i32 %21, ptr %19, align 4, !tbaa !8
  call void @_ZN6NoMali11GPUBlockInt14raiseInterruptEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 noundef 1536)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #4
  br label %29

22:                                               ; preds = %3, %3, %3, %3, %3, %3, %3, %3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #4
  %23 = add nsw i32 %1, -128
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %6, i32 noundef %23)
  %24 = xor i32 %2, -1
  %25 = getelementptr inbounds i8, ptr %0, i64 16
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24) %25, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %27 = load i32, ptr %26, align 4, !tbaa !8
  %28 = and i32 %27, %24
  store i32 %28, ptr %26, align 4, !tbaa !8
  call void @_ZN6NoMali11GPUBlockInt14raiseInterruptEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 noundef 1536)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #4
  br label %29

29:                                               ; preds = %3, %22, %12, %8, %7
  ret void
}

declare void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56), i32, i32 noundef) unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN6NoMali9RegVectorixERKNS_7RegAddrE(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

declare void @_ZN6NoMali11GPUBlockInt14raiseInterruptEj(ptr noundef nonnull align 8 dereferenceable(56), i32 noundef) local_unnamed_addr #3

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass