; LLVM IR from gem5/gem5 :: ext/mcpat/cacti/decoder.ll (ZN12PredecBlkDrv16leakage_feedbackEd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }
%class.PredecBlkDrv = type { %class.Component, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double, double, double, double, [20 x double], [20 x double], [20 x double], [20 x double], double, double, %class.powerDef, %class.powerDef, ptr, ptr, i8, i32 }
%class.Component = type { %class.Area, %class.powerDef, %class.powerDef, double, double }
%class.Area = type { double, double, double }
%class.powerDef = type { %class.powerComponents, %class.powerComponents, %class.powerComponents }
%class.powerComponents = type { double, double, double, double, double }

@g_tp = external global %class.TechnologyParameter, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) #1

declare noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12PredecBlkDrv16leakage_feedbackEd(ptr noundef nonnull align 8 dereferenceable(1280) %0, double noundef %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca double, align 8
  %5 = alloca double, align 8
  %6 = alloca double, align 8
  %7 = alloca double, align 8
  %8 = alloca double, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store double %1, ptr %4, align 8, !tbaa !9
  %11 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  store double 0.000000e+00, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  store double 0.000000e+00, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store double 0.000000e+00, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  store double 0.000000e+00, ptr %8, align 8, !tbaa !9
  %12 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 1
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp ne i32 %13, 0
  br i1 %14, label %15, label %164

15:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !19
  br label %16

16:                                               ; preds = %55, %15
  %17 = load i32, ptr %9, align 4, !tbaa !19
  %18 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 3
  %19 = load i32, ptr %18, align 8, !tbaa !20
  %20 = icmp slt i32 %17, %19
  br i1 %20, label %22, label %21

21:                                               ; preds = %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %58

22:                                               ; preds = %16
  %23 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 16
  %24 = load i32, ptr %9, align 4, !tbaa !19
  %25 = sext i32 %24 to i64
  %26 = getelementptr inbounds [20 x double], ptr %23, i64 0, i64 %25
  %27 = load double, ptr %26, align 8, !tbaa !9
  %28 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 17
  %29 = load i32, ptr %9, align 4, !tbaa !19
  %30 = sext i32 %29 to i64
  %31 = getelementptr inbounds [20 x double], ptr %28, i64 0, i64 %30
  %32 = load double, ptr %31, align 8, !tbaa !9
  %33 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 26
  %34 = load i8, ptr %33, align 8, !tbaa !21, !range !22, !noundef !23
  %35 = trunc i8 %34 to i1
  %36 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %27, double noundef %32, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %35, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %37 = load double, ptr %5, align 8, !tbaa !9
  %38 = fadd double %37, %36
  store double %38, ptr %5, align 8, !tbaa !9
  %39 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 16
  %40 = load i32, ptr %9, align 4, !tbaa !19
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds [20 x double], ptr %39, i64 0, i64 %41
  %43 = load double, ptr %42, align 8, !tbaa !9
  %44 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 17
  %45 = load i32, ptr %9, align 4, !tbaa !19
  %46 = sext i32 %45 to i64
  %47 = getelementptr inbounds [20 x double], ptr %44, i64 0, i64 %46
  %48 = load double, ptr %47, align 8, !tbaa !9
  %49 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 26
  %50 = load i8, ptr %49, align 8, !tbaa !21, !range !22, !noundef !23
  %51 = trunc i8 %50 to i1
  %52 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %43, double noundef %48, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %51, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %53 = load double, ptr %7, align 8, !tbaa !9
  %54 = fadd double %53, %52
  store double %54, ptr %7, align 8, !tbaa !9
  br label %55

55:                                               ; preds = %22
  %56 = load i32, ptr %9, align 4, !tbaa !19
  %57 = add nsw i32 %56, 1
  store i32 %57, ptr %9, align 4, !tbaa !19
  br label %16, !llvm.loop !24

58:                                               ; preds = %21
  %59 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 6
  %60 = load i32, ptr %59, align 4, !tbaa !26
  %61 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 7
  %62 = load i32, ptr %61, align 8, !tbaa !27
  %63 = add nsw i32 %60, %62
  %64 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 8
  %65 = load i32, ptr %64, align 4, !tbaa !28
  %66 = add nsw i32 %63, %65
  %67 = sitofp i32 %66 to double
  %68 = load double, ptr %5, align 8, !tbaa !9
  %69 = fmul double %68, %67
  store double %69, ptr %5, align 8, !tbaa !9
  %70 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 6
  %71 = load i32, ptr %70, align 4, !tbaa !26
  %72 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 7
  %73 = load i32, ptr %72, align 8, !tbaa !27
  %74 = add nsw i32 %71, %73
  %75 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 8
  %76 = load i32, ptr %75, align 4, !tbaa !28
  %77 = add nsw i32 %74, %76
  %78 = sitofp i32 %77 to double
  %79 = load double, ptr %7, align 8, !tbaa !9
  %80 = fmul double %79, %78
  store double %80, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !19
  br label %81

81:                                               ; preds = %120, %58
  %82 = load i32, ptr %10, align 4, !tbaa !19
  %83 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 4
  %84 = load i32, ptr %83, align 4, !tbaa !29
  %85 = icmp slt i32 %82, %84
  br i1 %85, label %87, label %86

86:                                               ; preds = %81
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %123

87:                                               ; preds = %81
  %88 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 18
  %89 = load i32, ptr %10, align 4, !tbaa !19
  %90 = sext i32 %89 to i64
  %91 = getelementptr inbounds [20 x double], ptr %88, i64 0, i64 %90
  %92 = load double, ptr %91, align 8, !tbaa !9
  %93 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 19
  %94 = load i32, ptr %10, align 4, !tbaa !19
  %95 = sext i32 %94 to i64
  %96 = getelementptr inbounds [20 x double], ptr %93, i64 0, i64 %95
  %97 = load double, ptr %96, align 8, !tbaa !9
  %98 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 26
  %99 = load i8, ptr %98, align 8, !tbaa !21, !range !22, !noundef !23
  %100 = trunc i8 %99 to i1
  %101 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %92, double noundef %97, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %100, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %102 = load double, ptr %6, align 8, !tbaa !9
  %103 = fadd double %102, %101
  store double %103, ptr %6, align 8, !tbaa !9
  %104 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 18
  %105 = load i32, ptr %10, align 4, !tbaa !19
  %106 = sext i32 %105 to i64
  %107 = getelementptr inbounds [20 x double], ptr %104, i64 0, i64 %106
  %108 = load double, ptr %107, align 8, !tbaa !9
  %109 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 19
  %110 = load i32, ptr %10, align 4, !tbaa !19
  %111 = sext i32 %110 to i64
  %112 = getelementptr inbounds [20 x double], ptr %109, i64 0, i64 %111
  %113 = load double, ptr %112, align 8, !tbaa !9
  %114 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 26
  %115 = load i8, ptr %114, align 8, !tbaa !21, !range !22, !noundef !23
  %116 = trunc i8 %115 to i1
  %117 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %108, double noundef %113, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %116, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %118 = load double, ptr %8, align 8, !tbaa !9
  %119 = fadd double %118, %117
  store double %119, ptr %8, align 8, !tbaa !9
  br label %120

120:                                              ; preds = %87
  %121 = load i32, ptr %10, align 4, !tbaa !19
  %122 = add nsw i32 %121, 1
  store i32 %122, ptr %10, align 4, !tbaa !19
  br label %81, !llvm.loop !30

123:                                              ; preds = %86
  %124 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 9
  %125 = load i32, ptr %124, align 8, !tbaa !31
  %126 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 10
  %127 = load i32, ptr %126, align 4, !tbaa !32
  %128 = add nsw i32 %125, %127
  %129 = sitofp i32 %128 to double
  %130 = load double, ptr %6, align 8, !tbaa !9
  %131 = fmul double %130, %129
  store double %131, ptr %6, align 8, !tbaa !9
  %132 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 9
  %133 = load i32, ptr %132, align 8, !tbaa !31
  %134 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 10
  %135 = load i32, ptr %134, align 4, !tbaa !32
  %136 = add nsw i32 %133, %135
  %137 = sitofp i32 %136 to double
  %138 = load double, ptr %8, align 8, !tbaa !9
  %139 = fmul double %138, %137
  store double %139, ptr %8, align 8, !tbaa !9
  %140 = load double, ptr %5, align 8, !tbaa !9
  %141 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !33
  %142 = fmul double %140, %141
  %143 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 22
  %144 = getelementptr inbounds %class.powerDef, ptr %143, i32 0, i32 0
  %145 = getelementptr inbounds %class.powerComponents, ptr %144, i32 0, i32 1
  store double %142, ptr %145, align 8, !tbaa !40
  %146 = load double, ptr %6, align 8, !tbaa !9
  %147 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !33
  %148 = fmul double %146, %147
  %149 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 23
  %150 = getelementptr inbounds %class.powerDef, ptr %149, i32 0, i32 0
  %151 = getelementptr inbounds %class.powerComponents, ptr %150, i32 0, i32 1
  store double %148, ptr %151, align 8, !tbaa !41
  %152 = load double, ptr %7, align 8, !tbaa !9
  %153 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !33
  %154 = fmul double %152, %153
  %155 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 22
  %156 = getelementptr inbounds %class.powerDef, ptr %155, i32 0, i32 0
  %157 = getelementptr inbounds %class.powerComponents, ptr %156, i32 0, i32 2
  store double %154, ptr %157, align 8, !tbaa !42
  %158 = load double, ptr %8, align 8, !tbaa !9
  %159 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !33
  %160 = fmul double %158, %159
  %161 = getelementptr inbounds %class.PredecBlkDrv, ptr %11, i32 0, i32 23
  %162 = getelementptr inbounds %class.powerDef, ptr %161, i32 0, i32 0
  %163 = getelementptr inbounds %class.powerComponents, ptr %162, i32 0, i32 2
  store double %160, ptr %163, align 8, !tbaa !43
  br label %164

164:                                              ; preds = %123, %2
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !17, i64 280}
!12 = !{!"_ZTS12PredecBlkDrv", !13, i64 0, !17, i64 280, !17, i64 284, !17, i64 288, !17, i64 292, !17, i64 296, !17, i64 300, !17, i64 304, !17, i64 308, !17, i64 312, !17, i64 316, !17, i64 320, !10, i64 328, !10, i64 336, !10, i64 344, !10, i64 352, !7, i64 360, !7, i64 520, !7, i64 680, !7, i64 840, !10, i64 1000, !10, i64 1008, !15, i64 1016, !15, i64 1136, !6, i64 1256, !6, i64 1264, !18, i64 1272, !17, i64 1276}
!13 = !{!"_ZTS9Component", !14, i64 0, !15, i64 24, !15, i64 144, !10, i64 264, !10, i64 272}
!14 = !{!"_ZTS4Area", !10, i64 0, !10, i64 8, !10, i64 16}
!15 = !{!"_ZTS8powerDef", !16, i64 0, !16, i64 40, !16, i64 80}
!16 = !{!"_ZTS15powerComponents", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32}
!17 = !{!"int", !7, i64 0}
!18 = !{!"bool", !7, i64 0}
!19 = !{!17, !17, i64 0}
!20 = !{!12, !17, i64 288}
!21 = !{!12, !18, i64 1272}
!22 = !{i8 0, i8 2}
!23 = !{}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!12, !17, i64 300}
!27 = !{!12, !17, i64 304}
!28 = !{!12, !17, i64 308}
!29 = !{!12, !17, i64 292}
!30 = distinct !{!30, !25}
!31 = !{!12, !17, i64 312}
!32 = !{!12, !17, i64 316}
!33 = !{!34, !10, i64 936}
!34 = !{!"_ZTS19TechnologyParameter", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !10, i64 256, !10, i64 264, !10, i64 272, !10, i64 280, !10, i64 288, !10, i64 296, !10, i64 304, !10, i64 312, !10, i64 320, !10, i64 328, !10, i64 336, !10, i64 344, !35, i64 352, !36, i64 360, !36, i64 528, !36, i64 696, !36, i64 864, !36, i64 1032, !37, i64 1200, !37, i64 1264, !37, i64 1328, !38, i64 1392, !39, i64 1416, !39, i64 1464, !39, i64 1512}
!35 = !{!"long", !7, i64 0}
!36 = !{!"_ZTSN19TechnologyParameter10DeviceTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160}
!37 = !{!"_ZTSN19TechnologyParameter16InterconnectTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56}
!38 = !{!"_ZTSN19TechnologyParameter13ScalingFactorE", !10, i64 0, !10, i64 8, !10, i64 16}
!39 = !{!"_ZTSN19TechnologyParameter10MemoryTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40}
!40 = !{!12, !10, i64 1024}
!41 = !{!12, !10, i64 1144}
!42 = !{!12, !10, i64 1032}
!43 = !{!12, !10, i64 1152}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }

@g_tp = external local_unnamed_addr global %class.TechnologyParameter, align 8

declare noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) local_unnamed_addr #0

declare noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12PredecBlkDrv16leakage_feedbackEd(ptr nocapture noundef nonnull align 8 dereferenceable(1280) %0, double noundef %1) local_unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 280
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %86, label %.preheader

.preheader:                                       ; preds = %2
  %5 = getelementptr inbounds i8, ptr %0, i64 288
  %6 = load i32, ptr %5, align 8, !tbaa !17
  %7 = icmp sgt i32 %6, 0
  br i1 %7, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %.preheader
  %8 = getelementptr inbounds i8, ptr %0, i64 360
  %9 = getelementptr inbounds i8, ptr %0, i64 520
  %10 = getelementptr inbounds i8, ptr %0, i64 1272
  br label %30

._crit_edge:                                      ; preds = %30, %.preheader
  %11 = phi <2 x double> [ zeroinitializer, %.preheader ], [ %46, %30 ]
  %12 = getelementptr inbounds i8, ptr %0, i64 300
  %13 = load i32, ptr %12, align 4, !tbaa !18
  %14 = getelementptr inbounds i8, ptr %0, i64 304
  %15 = load i32, ptr %14, align 8, !tbaa !19
  %16 = add nsw i32 %15, %13
  %17 = getelementptr inbounds i8, ptr %0, i64 308
  %18 = load i32, ptr %17, align 4, !tbaa !20
  %19 = add nsw i32 %16, %18
  %20 = sitofp i32 %19 to double
  %21 = insertelement <2 x double> poison, double %20, i64 0
  %22 = shufflevector <2 x double> %21, <2 x double> poison, <2 x i32> zeroinitializer
  %23 = fmul <2 x double> %11, %22
  %24 = getelementptr inbounds i8, ptr %0, i64 292
  %25 = load i32, ptr %24, align 4, !tbaa !21
  %26 = icmp sgt i32 %25, 0
  br i1 %26, label %.lr.ph37, label %._crit_edge38

.lr.ph37:                                         ; preds = %._crit_edge
  %27 = getelementptr inbounds i8, ptr %0, i64 680
  %28 = getelementptr inbounds i8, ptr %0, i64 840
  %29 = getelementptr inbounds i8, ptr %0, i64 1272
  br label %66

30:                                               ; preds = %.lr.ph, %30
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %30 ]
  %31 = phi <2 x double> [ zeroinitializer, %.lr.ph ], [ %46, %30 ]
  %32 = getelementptr inbounds [20 x double], ptr %8, i64 0, i64 %indvars.iv
  %33 = load double, ptr %32, align 8, !tbaa !22
  %34 = getelementptr inbounds [20 x double], ptr %9, i64 0, i64 %indvars.iv
  %35 = load double, ptr %34, align 8, !tbaa !22
  %36 = load i8, ptr %10, align 8, !tbaa !23, !range !24, !noundef !25
  %37 = trunc nuw i8 %36 to i1
  %38 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %33, double noundef %35, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %37, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %39 = load double, ptr %32, align 8, !tbaa !22
  %40 = load double, ptr %34, align 8, !tbaa !22
  %41 = load i8, ptr %10, align 8, !tbaa !23, !range !24, !noundef !25
  %42 = trunc nuw i8 %41 to i1
  %43 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %39, double noundef %40, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %42, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %44 = insertelement <2 x double> poison, double %38, i64 0
  %45 = insertelement <2 x double> %44, double %43, i64 1
  %46 = fadd <2 x double> %31, %45
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %47 = load i32, ptr %5, align 8, !tbaa !17
  %48 = sext i32 %47 to i64
  %49 = icmp slt i64 %indvars.iv.next, %48
  br i1 %49, label %30, label %._crit_edge, !llvm.loop !26

._crit_edge38:                                    ; preds = %66, %._crit_edge
  %50 = phi <2 x double> [ zeroinitializer, %._crit_edge ], [ %82, %66 ]
  %51 = getelementptr inbounds i8, ptr %0, i64 312
  %52 = load i32, ptr %51, align 8, !tbaa !28
  %53 = getelementptr inbounds i8, ptr %0, i64 316
  %54 = load i32, ptr %53, align 4, !tbaa !29
  %55 = add nsw i32 %54, %52
  %56 = sitofp i32 %55 to double
  %57 = load <2 x double>, ptr getelementptr inbounds (i8, ptr @g_tp, i64 936), align 8
  %58 = getelementptr inbounds i8, ptr %0, i64 1024
  %59 = getelementptr inbounds i8, ptr %0, i64 1144
  %60 = shufflevector <2 x double> %57, <2 x double> poison, <2 x i32> zeroinitializer
  %61 = fmul <2 x double> %23, %60
  store <2 x double> %61, ptr %58, align 8, !tbaa !22
  %62 = insertelement <2 x double> poison, double %56, i64 0
  %63 = shufflevector <2 x double> %62, <2 x double> poison, <2 x i32> zeroinitializer
  %64 = fmul <2 x double> %50, %63
  %65 = fmul <2 x double> %60, %64
  store <2 x double> %65, ptr %59, align 8, !tbaa !22
  br label %86

66:                                               ; preds = %.lr.ph37, %66
  %indvars.iv45 = phi i64 [ 0, %.lr.ph37 ], [ %indvars.iv.next46, %66 ]
  %67 = phi <2 x double> [ zeroinitializer, %.lr.ph37 ], [ %82, %66 ]
  %68 = getelementptr inbounds [20 x double], ptr %27, i64 0, i64 %indvars.iv45
  %69 = load double, ptr %68, align 8, !tbaa !22
  %70 = getelementptr inbounds [20 x double], ptr %28, i64 0, i64 %indvars.iv45
  %71 = load double, ptr %70, align 8, !tbaa !22
  %72 = load i8, ptr %29, align 8, !tbaa !23, !range !24, !noundef !25
  %73 = trunc nuw i8 %72 to i1
  %74 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %69, double noundef %71, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %73, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %75 = load double, ptr %68, align 8, !tbaa !22
  %76 = load double, ptr %70, align 8, !tbaa !22
  %77 = load i8, ptr %29, align 8, !tbaa !23, !range !24, !noundef !25
  %78 = trunc nuw i8 %77 to i1
  %79 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %75, double noundef %76, i32 noundef 1, i32 noundef 2, i1 noundef zeroext %78, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %80 = insertelement <2 x double> poison, double %74, i64 0
  %81 = insertelement <2 x double> %80, double %79, i64 1
  %82 = fadd <2 x double> %67, %81
  %indvars.iv.next46 = add nuw nsw i64 %indvars.iv45, 1
  %83 = load i32, ptr %24, align 4, !tbaa !21
  %84 = sext i32 %83 to i64
  %85 = icmp slt i64 %indvars.iv.next46, %84
  br i1 %85, label %66, label %._crit_edge38, !llvm.loop !30

86:                                               ; preds = %._crit_edge38, %2
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 280}
!6 = !{!"_ZTS12PredecBlkDrv", !7, i64 0, !14, i64 280, !14, i64 284, !14, i64 288, !14, i64 292, !14, i64 296, !14, i64 300, !14, i64 304, !14, i64 308, !14, i64 312, !14, i64 316, !14, i64 320, !9, i64 328, !9, i64 336, !9, i64 344, !9, i64 352, !10, i64 360, !10, i64 520, !10, i64 680, !10, i64 840, !9, i64 1000, !9, i64 1008, !12, i64 1016, !12, i64 1136, !15, i64 1256, !15, i64 1264, !16, i64 1272, !14, i64 1276}
!7 = !{!"_ZTS9Component", !8, i64 0, !12, i64 24, !12, i64 144, !9, i64 264, !9, i64 272}
!8 = !{!"_ZTS4Area", !9, i64 0, !9, i64 8, !9, i64 16}
!9 = !{!"double", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTS8powerDef", !13, i64 0, !13, i64 40, !13, i64 80}
!13 = !{!"_ZTS15powerComponents", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32}
!14 = !{!"int", !10, i64 0}
!15 = !{!"any pointer", !10, i64 0}
!16 = !{!"bool", !10, i64 0}
!17 = !{!6, !14, i64 288}
!18 = !{!6, !14, i64 300}
!19 = !{!6, !14, i64 304}
!20 = !{!6, !14, i64 308}
!21 = !{!6, !14, i64 292}
!22 = !{!9, !9, i64 0}
!23 = !{!6, !16, i64 1272}
!24 = !{i8 0, i8 2}
!25 = !{}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!6, !14, i64 312}
!29 = !{!6, !14, i64 316}
!30 = distinct !{!30, !27}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass,VectorCombinePass