; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int/sc_signed.ll (ZN5sc_dt9sc_signed14set_packed_repEPj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32)) #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef, ptr noundef) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt9sc_signed16convert_2C_to_SMEv(ptr noundef nonnull align 8 dereferenceable(32)) #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt7bit_ordEi(i32 noundef) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt9digit_ordEi(i32 noundef) #4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt9sc_signed14set_packed_repEPj(ptr noundef nonnull align 8 dereferenceable(32) %0, ptr noundef %1) #3 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  %7 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %6, i32 0, i32 3
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %6, i32 0, i32 4
  %10 = load ptr, ptr %9, align 8, !tbaa !13
  call void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef %8, ptr noundef %10)
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  %11 = call noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32) %6)
  %12 = sub nsw i32 %11, 1
  store i32 %12, ptr %5, align 4, !tbaa !14
  br label %13

13:                                               ; preds = %55, %2
  %14 = load i32, ptr %5, align 4, !tbaa !14
  %15 = icmp sge i32 %14, 0
  br i1 %15, label %17, label %16

16:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  br label %58

17:                                               ; preds = %13
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = load i32, ptr %5, align 4, !tbaa !14
  %20 = sdiv i32 %19, 32
  %21 = sext i32 %20 to i64
  %22 = getelementptr inbounds i32, ptr %18, i64 %21
  %23 = load i32, ptr %22, align 4, !tbaa !14
  %24 = load i32, ptr %5, align 4, !tbaa !14
  %25 = srem i32 %24, 32
  %26 = call noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef %25)
  %27 = and i32 %23, %26
  %28 = icmp ne i32 %27, 0
  br i1 %28, label %29, label %41

29:                                               ; preds = %17
  %30 = load i32, ptr %5, align 4, !tbaa !14
  %31 = call noundef i32 @_ZN5sc_dt7bit_ordEi(i32 noundef %30)
  %32 = call noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef %31)
  %33 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %6, i32 0, i32 4
  %34 = load ptr, ptr %33, align 8, !tbaa !13
  %35 = load i32, ptr %5, align 4, !tbaa !14
  %36 = call noundef i32 @_ZN5sc_dt9digit_ordEi(i32 noundef %35)
  %37 = sext i32 %36 to i64
  %38 = getelementptr inbounds i32, ptr %34, i64 %37
  %39 = load i32, ptr %38, align 4, !tbaa !14
  %40 = or i32 %39, %32
  store i32 %40, ptr %38, align 4, !tbaa !14
  br label %54

41:                                               ; preds = %17
  %42 = load i32, ptr %5, align 4, !tbaa !14
  %43 = call noundef i32 @_ZN5sc_dt7bit_ordEi(i32 noundef %42)
  %44 = call noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef %43)
  %45 = xor i32 %44, -1
  %46 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %6, i32 0, i32 4
  %47 = load ptr, ptr %46, align 8, !tbaa !13
  %48 = load i32, ptr %5, align 4, !tbaa !14
  %49 = call noundef i32 @_ZN5sc_dt9digit_ordEi(i32 noundef %48)
  %50 = sext i32 %49 to i64
  %51 = getelementptr inbounds i32, ptr %47, i64 %50
  %52 = load i32, ptr %51, align 4, !tbaa !14
  %53 = and i32 %52, %45
  store i32 %53, ptr %51, align 4, !tbaa !14
  br label %54

54:                                               ; preds = %41, %29
  br label %55

55:                                               ; preds = %54
  %56 = load i32, ptr %5, align 4, !tbaa !14
  %57 = add nsw i32 %56, -1
  store i32 %57, ptr %5, align 4, !tbaa !14
  br label %13, !llvm.loop !15

58:                                               ; preds = %16
  call void @_ZN5sc_dt9sc_signed16convert_2C_to_SMEv(ptr noundef nonnull align 8 dereferenceable(32) %6)
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !12, i64 16}
!10 = !{!"_ZTSN5sc_dt9sc_signedE", !11, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !6, i64 24}
!11 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !6, i64 24}
!14 = !{!12, !12, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt9sc_signed16convert_2C_to_SMEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt7bit_ordEi(i32 noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt9digit_ordEi(i32 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt9sc_signed14set_packed_repEPj(ptr noundef nonnull align 8 dereferenceable(32) %0, ptr nocapture noundef readonly %1) local_unnamed_addr #2 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 16
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 24
  %6 = load ptr, ptr %5, align 8, !tbaa !12
  tail call void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef %4, ptr noundef %6)
  %7 = tail call noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32) %0)
  %8 = icmp sgt i32 %7, 0
  br i1 %8, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %33, %2
  tail call void @_ZN5sc_dt9sc_signed16convert_2C_to_SMEv(ptr noundef nonnull align 8 dereferenceable(32) %0)
  ret void

.lr.ph:                                           ; preds = %2, %33
  %.010.in = phi i32 [ %.010, %33 ], [ %7, %2 ]
  %.010 = add nsw i32 %.010.in, -1
  %9 = lshr i32 %.010, 5
  %10 = zext nneg i32 %9 to i64
  %11 = getelementptr inbounds i32, ptr %1, i64 %10
  %12 = load i32, ptr %11, align 4, !tbaa !13
  %13 = and i32 %.010, 31
  %14 = tail call noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef %13)
  %15 = and i32 %14, %12
  %.not = icmp eq i32 %15, 0
  %16 = tail call noundef i32 @_ZN5sc_dt7bit_ordEi(i32 noundef %.010)
  %17 = tail call noundef i32 @_ZN5sc_dt13one_and_zerosEi(i32 noundef %16)
  br i1 %.not, label %25, label %18

18:                                               ; preds = %.lr.ph
  %19 = load ptr, ptr %5, align 8, !tbaa !12
  %20 = tail call noundef i32 @_ZN5sc_dt9digit_ordEi(i32 noundef %.010)
  %21 = sext i32 %20 to i64
  %22 = getelementptr inbounds i32, ptr %19, i64 %21
  %23 = load i32, ptr %22, align 4, !tbaa !13
  %24 = or i32 %23, %17
  store i32 %24, ptr %22, align 4, !tbaa !13
  br label %33

25:                                               ; preds = %.lr.ph
  %26 = xor i32 %17, -1
  %27 = load ptr, ptr %5, align 8, !tbaa !12
  %28 = tail call noundef i32 @_ZN5sc_dt9digit_ordEi(i32 noundef %.010)
  %29 = sext i32 %28 to i64
  %30 = getelementptr inbounds i32, ptr %27, i64 %29
  %31 = load i32, ptr %30, align 4, !tbaa !13
  %32 = and i32 %31, %26
  store i32 %32, ptr %30, align 4, !tbaa !13
  br label %33

33:                                               ; preds = %18, %25
  %34 = icmp ugt i32 %.010.in, 1
  br i1 %34, label %.lr.ph, label %._crit_edge, !llvm.loop !14
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 16}
!6 = !{!"_ZTSN5sc_dt9sc_signedE", !7, i64 0, !8, i64 8, !8, i64 12, !8, i64 16, !11, i64 24}
!7 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"any pointer", !9, i64 0}
!12 = !{!6, !11, i64 24}
!13 = !{!8, !8, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass