; LLVM IR from gem5/gem5 :: ext/mcpat/cacti/decoder.ll (ZN9PredecBlk16leakage_feedbackEd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }
%class.PredecBlk = type <{ %class.Component, ptr, i8, [3 x i8], i32, double, double, i32, i32, i8, [3 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, [20 x double], [20 x double], [20 x double], [20 x double], [20 x double], [20 x double], double, double, %class.powerDef, %class.powerDef, %class.powerDef, i8, [7 x i8] }>
%class.Component = type { %class.Area, %class.powerDef, %class.powerDef, double, double }
%class.Area = type { double, double, double }
%class.powerDef = type { %class.powerComponents, %class.powerComponents, %class.powerComponents }
%class.powerComponents = type { double, double, double, double, double }

@g_tp = external global %class.TechnologyParameter, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) #1

declare noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9PredecBlk16leakage_feedbackEd(ptr noundef nonnull align 8 dereferenceable(1697) %0, double noundef %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca double, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca double, align 8
  %9 = alloca double, align 8
  %10 = alloca double, align 8
  %11 = alloca double, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca double, align 8
  %15 = alloca double, align 8
  %16 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store double %1, ptr %4, align 8, !tbaa !9
  %17 = load ptr, ptr %3, align 8
  %18 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 2
  %19 = load i8, ptr %18, align 8, !tbaa !11, !range !19, !noundef !20
  %20 = trunc i8 %19 to i1
  br i1 %20, label %21, label %333

21:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !21
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !21
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !21
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  store double 0.000000e+00, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  store double 0.000000e+00, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  %22 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 20
  %23 = getelementptr inbounds [20 x double], ptr %22, i64 0, i64 0
  %24 = load double, ptr %23, align 8, !tbaa !9
  %25 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 21
  %26 = getelementptr inbounds [20 x double], ptr %25, i64 0, i64 0
  %27 = load double, ptr %26, align 8, !tbaa !9
  %28 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %29 = load i8, ptr %28, align 8, !tbaa !22, !range !19, !noundef !20
  %30 = trunc i8 %29 to i1
  %31 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %24, double noundef %27, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %30, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %31, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %32 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 20
  %33 = getelementptr inbounds [20 x double], ptr %32, i64 0, i64 0
  %34 = load double, ptr %33, align 8, !tbaa !9
  %35 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 21
  %36 = getelementptr inbounds [20 x double], ptr %35, i64 0, i64 0
  %37 = load double, ptr %36, align 8, !tbaa !9
  %38 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %39 = load i8, ptr %38, align 8, !tbaa !22, !range !19, !noundef !20
  %40 = trunc i8 %39 to i1
  %41 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %34, double noundef %37, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %40, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %41, ptr %11, align 8, !tbaa !9
  %42 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 12
  %43 = load i32, ptr %42, align 8, !tbaa !23
  %44 = icmp ne i32 %43, 3
  br i1 %44, label %45, label %46

45:                                               ; preds = %21
  store double 0.000000e+00, ptr %8, align 8, !tbaa !9
  store double 0.000000e+00, ptr %9, align 8, !tbaa !9
  br label %61

46:                                               ; preds = %21
  %47 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 22
  %48 = getelementptr inbounds [20 x double], ptr %47, i64 0, i64 0
  %49 = load double, ptr %48, align 8, !tbaa !9
  %50 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 23
  %51 = getelementptr inbounds [20 x double], ptr %50, i64 0, i64 0
  %52 = load double, ptr %51, align 8, !tbaa !9
  %53 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %49, double noundef %52, i32 noundef 3, i32 noundef 3, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %53, ptr %8, align 8, !tbaa !9
  %54 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 22
  %55 = getelementptr inbounds [20 x double], ptr %54, i64 0, i64 0
  %56 = load double, ptr %55, align 8, !tbaa !9
  %57 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 23
  %58 = getelementptr inbounds [20 x double], ptr %57, i64 0, i64 0
  %59 = load double, ptr %58, align 8, !tbaa !9
  %60 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %56, double noundef %59, i32 noundef 3, i32 noundef 3, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %60, ptr %9, align 8, !tbaa !9
  br label %61

61:                                               ; preds = %46, %45
  %62 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 4
  %63 = load i32, ptr %62, align 4, !tbaa !24
  switch i32 %63, label %91 [
    i32 1, label %64
    i32 2, label %67
    i32 3, label %70
    i32 4, label %73
    i32 5, label %76
    i32 6, label %79
    i32 7, label %82
    i32 8, label %85
    i32 9, label %88
  ]

64:                                               ; preds = %61
  store i32 2, ptr %5, align 4, !tbaa !21
  store i32 0, ptr %7, align 4, !tbaa !21
  %65 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 1, ptr %65, align 8, !tbaa !25
  %66 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 0, ptr %66, align 4, !tbaa !26
  br label %92

67:                                               ; preds = %61
  store i32 4, ptr %5, align 4, !tbaa !21
  store i32 0, ptr %7, align 4, !tbaa !21
  %68 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 1, ptr %68, align 8, !tbaa !25
  %69 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 0, ptr %69, align 4, !tbaa !26
  br label %92

70:                                               ; preds = %61
  store i32 8, ptr %6, align 4, !tbaa !21
  store i32 0, ptr %7, align 4, !tbaa !21
  %71 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 0, ptr %71, align 8, !tbaa !25
  %72 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 1, ptr %72, align 4, !tbaa !26
  br label %92

73:                                               ; preds = %61
  store i32 8, ptr %5, align 4, !tbaa !21
  store i32 16, ptr %7, align 4, !tbaa !21
  %74 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 2, ptr %74, align 8, !tbaa !25
  %75 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 0, ptr %75, align 4, !tbaa !26
  br label %92

76:                                               ; preds = %61
  store i32 4, ptr %5, align 4, !tbaa !21
  store i32 8, ptr %6, align 4, !tbaa !21
  store i32 32, ptr %7, align 4, !tbaa !21
  %77 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 1, ptr %77, align 8, !tbaa !25
  %78 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 1, ptr %78, align 4, !tbaa !26
  br label %92

79:                                               ; preds = %61
  store i32 16, ptr %6, align 4, !tbaa !21
  store i32 64, ptr %7, align 4, !tbaa !21
  %80 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 0, ptr %80, align 8, !tbaa !25
  %81 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 2, ptr %81, align 4, !tbaa !26
  br label %92

82:                                               ; preds = %61
  store i32 8, ptr %5, align 4, !tbaa !21
  store i32 8, ptr %6, align 4, !tbaa !21
  store i32 128, ptr %7, align 4, !tbaa !21
  %83 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 2, ptr %83, align 8, !tbaa !25
  %84 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 1, ptr %84, align 4, !tbaa !26
  br label %92

85:                                               ; preds = %61
  store i32 4, ptr %5, align 4, !tbaa !21
  store i32 16, ptr %6, align 4, !tbaa !21
  store i32 256, ptr %7, align 4, !tbaa !21
  %86 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 2, ptr %86, align 8, !tbaa !25
  %87 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 2, ptr %87, align 4, !tbaa !26
  br label %92

88:                                               ; preds = %61
  store i32 24, ptr %6, align 4, !tbaa !21
  store i32 512, ptr %7, align 4, !tbaa !21
  %89 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 18
  store i32 0, ptr %89, align 8, !tbaa !25
  %90 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 19
  store i32 3, ptr %90, align 4, !tbaa !26
  br label %92

91:                                               ; preds = %61
  br label %92

92:                                               ; preds = %91, %88, %85, %82, %79, %76, %73, %70, %67, %64
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 1, ptr %12, align 4, !tbaa !21
  br label %93

93:                                               ; preds = %132, %92
  %94 = load i32, ptr %12, align 4, !tbaa !21
  %95 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 13
  %96 = load i32, ptr %95, align 4, !tbaa !27
  %97 = icmp slt i32 %94, %96
  br i1 %97, label %99, label %98

98:                                               ; preds = %93
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %135

99:                                               ; preds = %93
  %100 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 20
  %101 = load i32, ptr %12, align 4, !tbaa !21
  %102 = sext i32 %101 to i64
  %103 = getelementptr inbounds [20 x double], ptr %100, i64 0, i64 %102
  %104 = load double, ptr %103, align 8, !tbaa !9
  %105 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 21
  %106 = load i32, ptr %12, align 4, !tbaa !21
  %107 = sext i32 %106 to i64
  %108 = getelementptr inbounds [20 x double], ptr %105, i64 0, i64 %107
  %109 = load double, ptr %108, align 8, !tbaa !9
  %110 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %111 = load i8, ptr %110, align 8, !tbaa !22, !range !19, !noundef !20
  %112 = trunc i8 %111 to i1
  %113 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %104, double noundef %109, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %112, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %114 = load double, ptr %10, align 8, !tbaa !9
  %115 = fadd double %114, %113
  store double %115, ptr %10, align 8, !tbaa !9
  %116 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 20
  %117 = load i32, ptr %12, align 4, !tbaa !21
  %118 = sext i32 %117 to i64
  %119 = getelementptr inbounds [20 x double], ptr %116, i64 0, i64 %118
  %120 = load double, ptr %119, align 8, !tbaa !9
  %121 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 21
  %122 = load i32, ptr %12, align 4, !tbaa !21
  %123 = sext i32 %122 to i64
  %124 = getelementptr inbounds [20 x double], ptr %121, i64 0, i64 %123
  %125 = load double, ptr %124, align 8, !tbaa !9
  %126 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %127 = load i8, ptr %126, align 8, !tbaa !22, !range !19, !noundef !20
  %128 = trunc i8 %127 to i1
  %129 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %120, double noundef %125, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %128, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %130 = load double, ptr %11, align 8, !tbaa !9
  %131 = fadd double %130, %129
  store double %131, ptr %11, align 8, !tbaa !9
  br label %132

132:                                              ; preds = %99
  %133 = load i32, ptr %12, align 4, !tbaa !21
  %134 = add nsw i32 %133, 1
  store i32 %134, ptr %12, align 4, !tbaa !21
  br label %93, !llvm.loop !28

135:                                              ; preds = %98
  %136 = load i32, ptr %5, align 4, !tbaa !21
  %137 = sitofp i32 %136 to double
  %138 = load double, ptr %10, align 8, !tbaa !9
  %139 = fmul double %138, %137
  store double %139, ptr %10, align 8, !tbaa !9
  %140 = load i32, ptr %5, align 4, !tbaa !21
  %141 = sitofp i32 %140 to double
  %142 = load double, ptr %11, align 8, !tbaa !9
  %143 = fmul double %142, %141
  store double %143, ptr %11, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 1, ptr %13, align 4, !tbaa !21
  br label %144

144:                                              ; preds = %183, %135
  %145 = load i32, ptr %13, align 4, !tbaa !21
  %146 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 14
  %147 = load i32, ptr %146, align 8, !tbaa !30
  %148 = icmp slt i32 %145, %147
  br i1 %148, label %150, label %149

149:                                              ; preds = %144
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  br label %186

150:                                              ; preds = %144
  %151 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 22
  %152 = load i32, ptr %13, align 4, !tbaa !21
  %153 = sext i32 %152 to i64
  %154 = getelementptr inbounds [20 x double], ptr %151, i64 0, i64 %153
  %155 = load double, ptr %154, align 8, !tbaa !9
  %156 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 23
  %157 = load i32, ptr %13, align 4, !tbaa !21
  %158 = sext i32 %157 to i64
  %159 = getelementptr inbounds [20 x double], ptr %156, i64 0, i64 %158
  %160 = load double, ptr %159, align 8, !tbaa !9
  %161 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %162 = load i8, ptr %161, align 8, !tbaa !22, !range !19, !noundef !20
  %163 = trunc i8 %162 to i1
  %164 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %155, double noundef %160, i32 noundef 3, i32 noundef 3, i1 noundef zeroext %163, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %165 = load double, ptr %8, align 8, !tbaa !9
  %166 = fadd double %165, %164
  store double %166, ptr %8, align 8, !tbaa !9
  %167 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 22
  %168 = load i32, ptr %13, align 4, !tbaa !21
  %169 = sext i32 %168 to i64
  %170 = getelementptr inbounds [20 x double], ptr %167, i64 0, i64 %169
  %171 = load double, ptr %170, align 8, !tbaa !9
  %172 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 23
  %173 = load i32, ptr %13, align 4, !tbaa !21
  %174 = sext i32 %173 to i64
  %175 = getelementptr inbounds [20 x double], ptr %172, i64 0, i64 %174
  %176 = load double, ptr %175, align 8, !tbaa !9
  %177 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %178 = load i8, ptr %177, align 8, !tbaa !22, !range !19, !noundef !20
  %179 = trunc i8 %178 to i1
  %180 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %171, double noundef %176, i32 noundef 3, i32 noundef 3, i1 noundef zeroext %179, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %181 = load double, ptr %9, align 8, !tbaa !9
  %182 = fadd double %181, %180
  store double %182, ptr %9, align 8, !tbaa !9
  br label %183

183:                                              ; preds = %150
  %184 = load i32, ptr %13, align 4, !tbaa !21
  %185 = add nsw i32 %184, 1
  store i32 %185, ptr %13, align 4, !tbaa !21
  br label %144, !llvm.loop !31

186:                                              ; preds = %149
  %187 = load i32, ptr %6, align 4, !tbaa !21
  %188 = sitofp i32 %187 to double
  %189 = load double, ptr %8, align 8, !tbaa !9
  %190 = fmul double %189, %188
  store double %190, ptr %8, align 8, !tbaa !9
  %191 = load i32, ptr %6, align 4, !tbaa !21
  %192 = sitofp i32 %191 to double
  %193 = load double, ptr %9, align 8, !tbaa !9
  %194 = fmul double %193, %192
  store double %194, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  store double 0.000000e+00, ptr %14, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  store double 0.000000e+00, ptr %15, align 8, !tbaa !9
  %195 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 11
  %196 = load i32, ptr %195, align 4, !tbaa !32
  %197 = icmp eq i32 %196, 2
  br i1 %197, label %198, label %219

198:                                              ; preds = %186
  %199 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 24
  %200 = getelementptr inbounds [20 x double], ptr %199, i64 0, i64 0
  %201 = load double, ptr %200, align 8, !tbaa !9
  %202 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 25
  %203 = getelementptr inbounds [20 x double], ptr %202, i64 0, i64 0
  %204 = load double, ptr %203, align 8, !tbaa !9
  %205 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %206 = load i8, ptr %205, align 8, !tbaa !22, !range !19, !noundef !20
  %207 = trunc i8 %206 to i1
  %208 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %201, double noundef %204, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %207, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %208, ptr %14, align 8, !tbaa !9
  %209 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 24
  %210 = getelementptr inbounds [20 x double], ptr %209, i64 0, i64 0
  %211 = load double, ptr %210, align 8, !tbaa !9
  %212 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 25
  %213 = getelementptr inbounds [20 x double], ptr %212, i64 0, i64 0
  %214 = load double, ptr %213, align 8, !tbaa !9
  %215 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %216 = load i8, ptr %215, align 8, !tbaa !22, !range !19, !noundef !20
  %217 = trunc i8 %216 to i1
  %218 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %211, double noundef %214, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %217, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %218, ptr %15, align 8, !tbaa !9
  br label %245

219:                                              ; preds = %186
  %220 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 11
  %221 = load i32, ptr %220, align 4, !tbaa !32
  %222 = icmp eq i32 %221, 3
  br i1 %222, label %223, label %244

223:                                              ; preds = %219
  %224 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 24
  %225 = getelementptr inbounds [20 x double], ptr %224, i64 0, i64 0
  %226 = load double, ptr %225, align 8, !tbaa !9
  %227 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 25
  %228 = getelementptr inbounds [20 x double], ptr %227, i64 0, i64 0
  %229 = load double, ptr %228, align 8, !tbaa !9
  %230 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %231 = load i8, ptr %230, align 8, !tbaa !22, !range !19, !noundef !20
  %232 = trunc i8 %231 to i1
  %233 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %226, double noundef %229, i32 noundef 3, i32 noundef 3, i1 noundef zeroext %232, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %233, ptr %14, align 8, !tbaa !9
  %234 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 24
  %235 = getelementptr inbounds [20 x double], ptr %234, i64 0, i64 0
  %236 = load double, ptr %235, align 8, !tbaa !9
  %237 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 25
  %238 = getelementptr inbounds [20 x double], ptr %237, i64 0, i64 0
  %239 = load double, ptr %238, align 8, !tbaa !9
  %240 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %241 = load i8, ptr %240, align 8, !tbaa !22, !range !19, !noundef !20
  %242 = trunc i8 %241 to i1
  %243 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %236, double noundef %239, i32 noundef 3, i32 noundef 3, i1 noundef zeroext %242, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  store double %243, ptr %15, align 8, !tbaa !9
  br label %244

244:                                              ; preds = %223, %219
  br label %245

245:                                              ; preds = %244, %198
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #3
  store i32 1, ptr %16, align 4, !tbaa !21
  br label %246

246:                                              ; preds = %285, %245
  %247 = load i32, ptr %16, align 4, !tbaa !21
  %248 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 15
  %249 = load i32, ptr %248, align 4, !tbaa !33
  %250 = icmp slt i32 %247, %249
  br i1 %250, label %252, label %251

251:                                              ; preds = %246
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #3
  br label %288

252:                                              ; preds = %246
  %253 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 24
  %254 = load i32, ptr %16, align 4, !tbaa !21
  %255 = sext i32 %254 to i64
  %256 = getelementptr inbounds [20 x double], ptr %253, i64 0, i64 %255
  %257 = load double, ptr %256, align 8, !tbaa !9
  %258 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 25
  %259 = load i32, ptr %16, align 4, !tbaa !21
  %260 = sext i32 %259 to i64
  %261 = getelementptr inbounds [20 x double], ptr %258, i64 0, i64 %260
  %262 = load double, ptr %261, align 8, !tbaa !9
  %263 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %264 = load i8, ptr %263, align 8, !tbaa !22, !range !19, !noundef !20
  %265 = trunc i8 %264 to i1
  %266 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %257, double noundef %262, i32 noundef 2, i32 noundef 2, i1 noundef zeroext %265, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %267 = load double, ptr %14, align 8, !tbaa !9
  %268 = fadd double %267, %266
  store double %268, ptr %14, align 8, !tbaa !9
  %269 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 24
  %270 = load i32, ptr %16, align 4, !tbaa !21
  %271 = sext i32 %270 to i64
  %272 = getelementptr inbounds [20 x double], ptr %269, i64 0, i64 %271
  %273 = load double, ptr %272, align 8, !tbaa !9
  %274 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 25
  %275 = load i32, ptr %16, align 4, !tbaa !21
  %276 = sext i32 %275 to i64
  %277 = getelementptr inbounds [20 x double], ptr %274, i64 0, i64 %276
  %278 = load double, ptr %277, align 8, !tbaa !9
  %279 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 31
  %280 = load i8, ptr %279, align 8, !tbaa !22, !range !19, !noundef !20
  %281 = trunc i8 %280 to i1
  %282 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %273, double noundef %278, i32 noundef 2, i32 noundef 2, i1 noundef zeroext %281, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %283 = load double, ptr %15, align 8, !tbaa !9
  %284 = fadd double %283, %282
  store double %284, ptr %15, align 8, !tbaa !9
  br label %285

285:                                              ; preds = %252
  %286 = load i32, ptr %16, align 4, !tbaa !21
  %287 = add nsw i32 %286, 1
  store i32 %287, ptr %16, align 4, !tbaa !21
  br label %246, !llvm.loop !34

288:                                              ; preds = %251
  %289 = load i32, ptr %7, align 4, !tbaa !21
  %290 = sitofp i32 %289 to double
  %291 = load double, ptr %14, align 8, !tbaa !9
  %292 = fmul double %291, %290
  store double %292, ptr %14, align 8, !tbaa !9
  %293 = load i32, ptr %7, align 4, !tbaa !21
  %294 = sitofp i32 %293 to double
  %295 = load double, ptr %15, align 8, !tbaa !9
  %296 = fmul double %295, %294
  store double %296, ptr %15, align 8, !tbaa !9
  %297 = load double, ptr %10, align 8, !tbaa !9
  %298 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !35
  %299 = fmul double %297, %298
  %300 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 28
  %301 = getelementptr inbounds %class.powerDef, ptr %300, i32 0, i32 0
  %302 = getelementptr inbounds %class.powerComponents, ptr %301, i32 0, i32 1
  store double %299, ptr %302, align 8, !tbaa !42
  %303 = load double, ptr %8, align 8, !tbaa !9
  %304 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !35
  %305 = fmul double %303, %304
  %306 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 29
  %307 = getelementptr inbounds %class.powerDef, ptr %306, i32 0, i32 0
  %308 = getelementptr inbounds %class.powerComponents, ptr %307, i32 0, i32 1
  store double %305, ptr %308, align 8, !tbaa !43
  %309 = load double, ptr %14, align 8, !tbaa !9
  %310 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !35
  %311 = fmul double %309, %310
  %312 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 30
  %313 = getelementptr inbounds %class.powerDef, ptr %312, i32 0, i32 0
  %314 = getelementptr inbounds %class.powerComponents, ptr %313, i32 0, i32 1
  store double %311, ptr %314, align 8, !tbaa !44
  %315 = load double, ptr %11, align 8, !tbaa !9
  %316 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !35
  %317 = fmul double %315, %316
  %318 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 28
  %319 = getelementptr inbounds %class.powerDef, ptr %318, i32 0, i32 0
  %320 = getelementptr inbounds %class.powerComponents, ptr %319, i32 0, i32 2
  store double %317, ptr %320, align 8, !tbaa !45
  %321 = load double, ptr %9, align 8, !tbaa !9
  %322 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !35
  %323 = fmul double %321, %322
  %324 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 29
  %325 = getelementptr inbounds %class.powerDef, ptr %324, i32 0, i32 0
  %326 = getelementptr inbounds %class.powerComponents, ptr %325, i32 0, i32 2
  store double %323, ptr %326, align 8, !tbaa !46
  %327 = load double, ptr %15, align 8, !tbaa !9
  %328 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::DeviceType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 48), i32 0, i32 9), align 8, !tbaa !35
  %329 = fmul double %327, %328
  %330 = getelementptr inbounds %class.PredecBlk, ptr %17, i32 0, i32 30
  %331 = getelementptr inbounds %class.powerDef, ptr %330, i32 0, i32 0
  %332 = getelementptr inbounds %class.powerComponents, ptr %331, i32 0, i32 2
  store double %329, ptr %332, align 8, !tbaa !47
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %333

333:                                              ; preds = %288, %2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !17, i64 288}
!12 = !{!"_ZTS9PredecBlk", !13, i64 0, !6, i64 280, !17, i64 288, !18, i64 292, !10, i64 296, !10, i64 304, !18, i64 312, !18, i64 316, !17, i64 320, !18, i64 324, !18, i64 328, !18, i64 332, !18, i64 336, !18, i64 340, !18, i64 344, !18, i64 348, !18, i64 352, !18, i64 356, !7, i64 360, !7, i64 520, !7, i64 680, !7, i64 840, !7, i64 1000, !7, i64 1160, !10, i64 1320, !10, i64 1328, !15, i64 1336, !15, i64 1456, !15, i64 1576, !17, i64 1696}
!13 = !{!"_ZTS9Component", !14, i64 0, !15, i64 24, !15, i64 144, !10, i64 264, !10, i64 272}
!14 = !{!"_ZTS4Area", !10, i64 0, !10, i64 8, !10, i64 16}
!15 = !{!"_ZTS8powerDef", !16, i64 0, !16, i64 40, !16, i64 80}
!16 = !{!"_ZTS15powerComponents", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32}
!17 = !{!"bool", !7, i64 0}
!18 = !{!"int", !7, i64 0}
!19 = !{i8 0, i8 2}
!20 = !{}
!21 = !{!18, !18, i64 0}
!22 = !{!12, !17, i64 1696}
!23 = !{!12, !18, i64 328}
!24 = !{!12, !18, i64 292}
!25 = !{!12, !18, i64 352}
!26 = !{!12, !18, i64 356}
!27 = !{!12, !18, i64 332}
!28 = distinct !{!28, !29}
!29 = !{!"llvm.loop.mustprogress"}
!30 = !{!12, !18, i64 336}
!31 = distinct !{!31, !29}
!32 = !{!12, !18, i64 324}
!33 = !{!12, !18, i64 340}
!34 = distinct !{!34, !29}
!35 = !{!36, !10, i64 936}
!36 = !{!"_ZTS19TechnologyParameter", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !10, i64 256, !10, i64 264, !10, i64 272, !10, i64 280, !10, i64 288, !10, i64 296, !10, i64 304, !10, i64 312, !10, i64 320, !10, i64 328, !10, i64 336, !10, i64 344, !37, i64 352, !38, i64 360, !38, i64 528, !38, i64 696, !38, i64 864, !38, i64 1032, !39, i64 1200, !39, i64 1264, !39, i64 1328, !40, i64 1392, !41, i64 1416, !41, i64 1464, !41, i64 1512}
!37 = !{!"long", !7, i64 0}
!38 = !{!"_ZTSN19TechnologyParameter10DeviceTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160}
!39 = !{!"_ZTSN19TechnologyParameter16InterconnectTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56}
!40 = !{!"_ZTSN19TechnologyParameter13ScalingFactorE", !10, i64 0, !10, i64 8, !10, i64 16}
!41 = !{!"_ZTSN19TechnologyParameter10MemoryTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40}
!42 = !{!12, !10, i64 1344}
!43 = !{!12, !10, i64 1464}
!44 = !{!12, !10, i64 1584}
!45 = !{!12, !10, i64 1352}
!46 = !{!12, !10, i64 1472}
!47 = !{!12, !10, i64 1592}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }

@g_tp = external local_unnamed_addr global %class.TechnologyParameter, align 8
@switch.table._ZN9PredecBlk16leakage_feedbackEd = private unnamed_addr constant [9 x i32] [i32 1, i32 1, i32 0, i32 2, i32 1, i32 0, i32 2, i32 2, i32 0], align 4
@switch.table._ZN9PredecBlk16leakage_feedbackEd.1 = private unnamed_addr constant [9 x i32] [i32 0, i32 0, i32 1, i32 0, i32 1, i32 2, i32 1, i32 2, i32 3], align 4
@switch.table._ZN9PredecBlk16leakage_feedbackEd.2 = private unnamed_addr constant [9 x double] [double 2.000000e+00, double 4.000000e+00, double 0.000000e+00, double 8.000000e+00, double 4.000000e+00, double 0.000000e+00, double 8.000000e+00, double 4.000000e+00, double 0.000000e+00], align 8
@switch.table._ZN9PredecBlk16leakage_feedbackEd.3 = private unnamed_addr constant [9 x double] [double 0.000000e+00, double 0.000000e+00, double 8.000000e+00, double 0.000000e+00, double 8.000000e+00, double 1.600000e+01, double 8.000000e+00, double 1.600000e+01, double 2.400000e+01], align 8
@switch.table._ZN9PredecBlk16leakage_feedbackEd.4 = private unnamed_addr constant [9 x double] [double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 1.600000e+01, double 3.200000e+01, double 6.400000e+01, double 1.280000e+02, double 2.560000e+02, double 5.120000e+02], align 8

declare noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) local_unnamed_addr #0

declare noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9PredecBlk16leakage_feedbackEd(ptr nocapture noundef nonnull align 8 dereferenceable(1697) %0, double noundef %1) local_unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 288
  %4 = load i8, ptr %3, align 8, !tbaa !5, !range !17, !noundef !18
  %5 = trunc nuw i8 %4 to i1
  br i1 %5, label %6, label %159

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 360
  %8 = load double, ptr %7, align 8, !tbaa !19
  %9 = getelementptr inbounds i8, ptr %0, i64 520
  %10 = load double, ptr %9, align 8, !tbaa !19
  %11 = getelementptr inbounds i8, ptr %0, i64 1696
  %12 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %13 = trunc nuw i8 %12 to i1
  %14 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %8, double noundef %10, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %13, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %15 = load double, ptr %7, align 8, !tbaa !19
  %16 = load double, ptr %9, align 8, !tbaa !19
  %17 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %18 = trunc nuw i8 %17 to i1
  %19 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %15, double noundef %16, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %18, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %20 = getelementptr inbounds i8, ptr %0, i64 328
  %21 = load i32, ptr %20, align 8, !tbaa !21
  %.not = icmp eq i32 %21, 3
  br i1 %.not, label %22, label %33

22:                                               ; preds = %6
  %23 = getelementptr inbounds i8, ptr %0, i64 680
  %24 = load double, ptr %23, align 8, !tbaa !19
  %25 = getelementptr inbounds i8, ptr %0, i64 840
  %26 = load double, ptr %25, align 8, !tbaa !19
  %27 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %24, double noundef %26, i32 noundef 3, i32 noundef 3, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %28 = load double, ptr %23, align 8, !tbaa !19
  %29 = load double, ptr %25, align 8, !tbaa !19
  %30 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %28, double noundef %29, i32 noundef 3, i32 noundef 3, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %31 = insertelement <2 x double> poison, double %27, i64 0
  %32 = insertelement <2 x double> %31, double %30, i64 1
  br label %33

33:                                               ; preds = %6, %22
  %34 = phi <2 x double> [ %32, %22 ], [ zeroinitializer, %6 ]
  %35 = getelementptr inbounds i8, ptr %0, i64 292
  %36 = load i32, ptr %35, align 4, !tbaa !22
  %switch.tableidx = add i32 %36, -1
  %37 = icmp ult i32 %switch.tableidx, 9
  br i1 %37, label %switch.lookup, label %45

switch.lookup:                                    ; preds = %33
  %38 = zext nneg i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [9 x i32], ptr @switch.table._ZN9PredecBlk16leakage_feedbackEd, i64 0, i64 %38
  %switch.load = load i32, ptr %switch.gep, align 4
  %39 = zext nneg i32 %switch.tableidx to i64
  %switch.gep117 = getelementptr inbounds [9 x i32], ptr @switch.table._ZN9PredecBlk16leakage_feedbackEd.1, i64 0, i64 %39
  %switch.load118 = load i32, ptr %switch.gep117, align 4
  %40 = zext nneg i32 %switch.tableidx to i64
  %switch.gep119 = getelementptr inbounds [9 x double], ptr @switch.table._ZN9PredecBlk16leakage_feedbackEd.2, i64 0, i64 %40
  %switch.load120 = load double, ptr %switch.gep119, align 8
  %41 = zext nneg i32 %switch.tableidx to i64
  %switch.gep121 = getelementptr inbounds [9 x double], ptr @switch.table._ZN9PredecBlk16leakage_feedbackEd.3, i64 0, i64 %41
  %switch.load122 = load double, ptr %switch.gep121, align 8
  %42 = zext nneg i32 %switch.tableidx to i64
  %switch.gep123 = getelementptr inbounds [9 x double], ptr @switch.table._ZN9PredecBlk16leakage_feedbackEd.4, i64 0, i64 %42
  %switch.load124 = load double, ptr %switch.gep123, align 8
  %43 = getelementptr inbounds i8, ptr %0, i64 352
  store i32 %switch.load, ptr %43, align 8, !tbaa !23
  %44 = getelementptr inbounds i8, ptr %0, i64 356
  store i32 %switch.load118, ptr %44, align 4, !tbaa !24
  br label %45

45:                                               ; preds = %33, %switch.lookup
  %.055 = phi double [ 0.000000e+00, %33 ], [ %switch.load120, %switch.lookup ]
  %.054 = phi double [ 0.000000e+00, %33 ], [ %switch.load122, %switch.lookup ]
  %.053 = phi double [ 0.000000e+00, %33 ], [ %switch.load124, %switch.lookup ]
  %46 = getelementptr inbounds i8, ptr %0, i64 332
  %47 = load i32, ptr %46, align 4, !tbaa !25
  %48 = icmp sgt i32 %47, 1
  %49 = insertelement <2 x double> poison, double %14, i64 0
  %50 = insertelement <2 x double> %49, double %19, i64 1
  br i1 %48, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %45
  %51 = phi <2 x double> [ %50, %45 ], [ %75, %.lr.ph ]
  %52 = insertelement <2 x double> poison, double %.055, i64 0
  %53 = shufflevector <2 x double> %52, <2 x double> poison, <2 x i32> zeroinitializer
  %54 = fmul <2 x double> %53, %51
  %55 = getelementptr inbounds i8, ptr %0, i64 336
  %56 = load i32, ptr %55, align 8, !tbaa !26
  %57 = icmp sgt i32 %56, 1
  br i1 %57, label %.lr.ph65, label %._crit_edge66

.lr.ph65:                                         ; preds = %._crit_edge
  %58 = getelementptr inbounds i8, ptr %0, i64 680
  %59 = getelementptr inbounds i8, ptr %0, i64 840
  br label %86

.lr.ph:                                           ; preds = %45, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 1, %45 ]
  %60 = phi <2 x double> [ %75, %.lr.ph ], [ %50, %45 ]
  %61 = getelementptr inbounds [20 x double], ptr %7, i64 0, i64 %indvars.iv
  %62 = load double, ptr %61, align 8, !tbaa !19
  %63 = getelementptr inbounds [20 x double], ptr %9, i64 0, i64 %indvars.iv
  %64 = load double, ptr %63, align 8, !tbaa !19
  %65 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %66 = trunc nuw i8 %65 to i1
  %67 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %62, double noundef %64, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %66, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %68 = load double, ptr %61, align 8, !tbaa !19
  %69 = load double, ptr %63, align 8, !tbaa !19
  %70 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %71 = trunc nuw i8 %70 to i1
  %72 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %68, double noundef %69, i32 noundef 2, i32 noundef 3, i1 noundef zeroext %71, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %73 = insertelement <2 x double> poison, double %67, i64 0
  %74 = insertelement <2 x double> %73, double %72, i64 1
  %75 = fadd <2 x double> %60, %74
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %76 = load i32, ptr %46, align 4, !tbaa !25
  %77 = sext i32 %76 to i64
  %78 = icmp slt i64 %indvars.iv.next, %77
  br i1 %78, label %.lr.ph, label %._crit_edge, !llvm.loop !27

._crit_edge66:                                    ; preds = %86, %._crit_edge
  %79 = phi <2 x double> [ %34, %._crit_edge ], [ %102, %86 ]
  %80 = insertelement <2 x double> poison, double %.054, i64 0
  %81 = shufflevector <2 x double> %80, <2 x double> poison, <2 x i32> zeroinitializer
  %82 = fmul <2 x double> %81, %79
  %83 = getelementptr inbounds i8, ptr %0, i64 324
  %84 = load i32, ptr %83, align 4, !tbaa !29
  %85 = and i32 %84, -2
  %switch = icmp eq i32 %85, 2
  br i1 %switch, label %.sink.split97, label %120

86:                                               ; preds = %.lr.ph65, %86
  %indvars.iv83 = phi i64 [ 1, %.lr.ph65 ], [ %indvars.iv.next84, %86 ]
  %87 = phi <2 x double> [ %34, %.lr.ph65 ], [ %102, %86 ]
  %88 = getelementptr inbounds [20 x double], ptr %58, i64 0, i64 %indvars.iv83
  %89 = load double, ptr %88, align 8, !tbaa !19
  %90 = getelementptr inbounds [20 x double], ptr %59, i64 0, i64 %indvars.iv83
  %91 = load double, ptr %90, align 8, !tbaa !19
  %92 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %93 = trunc nuw i8 %92 to i1
  %94 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %89, double noundef %91, i32 noundef 3, i32 noundef 3, i1 noundef zeroext %93, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %95 = load double, ptr %88, align 8, !tbaa !19
  %96 = load double, ptr %90, align 8, !tbaa !19
  %97 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %98 = trunc nuw i8 %97 to i1
  %99 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %95, double noundef %96, i32 noundef 3, i32 noundef 3, i1 noundef zeroext %98, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %100 = insertelement <2 x double> poison, double %94, i64 0
  %101 = insertelement <2 x double> %100, double %99, i64 1
  %102 = fadd <2 x double> %87, %101
  %indvars.iv.next84 = add nuw nsw i64 %indvars.iv83, 1
  %103 = load i32, ptr %55, align 8, !tbaa !26
  %104 = sext i32 %103 to i64
  %105 = icmp slt i64 %indvars.iv.next84, %104
  br i1 %105, label %86, label %._crit_edge66, !llvm.loop !30

.sink.split97:                                    ; preds = %._crit_edge66
  %106 = getelementptr inbounds i8, ptr %0, i64 1000
  %107 = load double, ptr %106, align 8, !tbaa !19
  %108 = getelementptr inbounds i8, ptr %0, i64 1160
  %109 = load double, ptr %108, align 8, !tbaa !19
  %110 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %111 = trunc nuw i8 %110 to i1
  %112 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %107, double noundef %109, i32 noundef %84, i32 noundef 3, i1 noundef zeroext %111, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %113 = load double, ptr %106, align 8, !tbaa !19
  %114 = load double, ptr %108, align 8, !tbaa !19
  %115 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %116 = trunc nuw i8 %115 to i1
  %117 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %113, double noundef %114, i32 noundef %84, i32 noundef 3, i1 noundef zeroext %116, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %118 = insertelement <2 x double> poison, double %112, i64 0
  %119 = insertelement <2 x double> %118, double %117, i64 1
  br label %120

120:                                              ; preds = %._crit_edge66, %.sink.split97
  %121 = phi <2 x double> [ zeroinitializer, %._crit_edge66 ], [ %119, %.sink.split97 ]
  %122 = getelementptr inbounds i8, ptr %0, i64 340
  %123 = load i32, ptr %122, align 4, !tbaa !31
  %124 = icmp sgt i32 %123, 1
  br i1 %124, label %.lr.ph73, label %._crit_edge74

.lr.ph73:                                         ; preds = %120
  %125 = getelementptr inbounds i8, ptr %0, i64 1000
  %126 = getelementptr inbounds i8, ptr %0, i64 1160
  br label %139

._crit_edge74:                                    ; preds = %139, %120
  %127 = phi <2 x double> [ %121, %120 ], [ %155, %139 ]
  %128 = insertelement <2 x double> poison, double %.053, i64 0
  %129 = shufflevector <2 x double> %128, <2 x double> poison, <2 x i32> zeroinitializer
  %130 = fmul <2 x double> %129, %127
  %131 = load <2 x double>, ptr getelementptr inbounds (i8, ptr @g_tp, i64 936), align 8
  %132 = getelementptr inbounds i8, ptr %0, i64 1344
  %133 = getelementptr inbounds i8, ptr %0, i64 1464
  %134 = getelementptr inbounds i8, ptr %0, i64 1584
  %135 = shufflevector <2 x double> %131, <2 x double> poison, <2 x i32> zeroinitializer
  %136 = fmul <2 x double> %54, %135
  store <2 x double> %136, ptr %132, align 8, !tbaa !19
  %137 = fmul <2 x double> %82, %135
  store <2 x double> %137, ptr %133, align 8, !tbaa !19
  %138 = fmul <2 x double> %130, %135
  store <2 x double> %138, ptr %134, align 8, !tbaa !19
  br label %159

139:                                              ; preds = %.lr.ph73, %139
  %indvars.iv86 = phi i64 [ 1, %.lr.ph73 ], [ %indvars.iv.next87, %139 ]
  %140 = phi <2 x double> [ %121, %.lr.ph73 ], [ %155, %139 ]
  %141 = getelementptr inbounds [20 x double], ptr %125, i64 0, i64 %indvars.iv86
  %142 = load double, ptr %141, align 8, !tbaa !19
  %143 = getelementptr inbounds [20 x double], ptr %126, i64 0, i64 %indvars.iv86
  %144 = load double, ptr %143, align 8, !tbaa !19
  %145 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %146 = trunc nuw i8 %145 to i1
  %147 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %142, double noundef %144, i32 noundef 2, i32 noundef 2, i1 noundef zeroext %146, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %148 = load double, ptr %141, align 8, !tbaa !19
  %149 = load double, ptr %143, align 8, !tbaa !19
  %150 = load i8, ptr %11, align 8, !tbaa !20, !range !17, !noundef !18
  %151 = trunc nuw i8 %150 to i1
  %152 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %148, double noundef %149, i32 noundef 2, i32 noundef 2, i1 noundef zeroext %151, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %153 = insertelement <2 x double> poison, double %147, i64 0
  %154 = insertelement <2 x double> %153, double %152, i64 1
  %155 = fadd <2 x double> %140, %154
  %indvars.iv.next87 = add nuw nsw i64 %indvars.iv86, 1
  %156 = load i32, ptr %122, align 4, !tbaa !31
  %157 = sext i32 %156 to i64
  %158 = icmp slt i64 %indvars.iv.next87, %157
  br i1 %158, label %139, label %._crit_edge74, !llvm.loop !32

159:                                              ; preds = %._crit_edge74, %2
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !15, i64 288}
!6 = !{!"_ZTS9PredecBlk", !7, i64 0, !14, i64 280, !15, i64 288, !16, i64 292, !9, i64 296, !9, i64 304, !16, i64 312, !16, i64 316, !15, i64 320, !16, i64 324, !16, i64 328, !16, i64 332, !16, i64 336, !16, i64 340, !16, i64 344, !16, i64 348, !16, i64 352, !16, i64 356, !10, i64 360, !10, i64 520, !10, i64 680, !10, i64 840, !10, i64 1000, !10, i64 1160, !9, i64 1320, !9, i64 1328, !12, i64 1336, !12, i64 1456, !12, i64 1576, !15, i64 1696}
!7 = !{!"_ZTS9Component", !8, i64 0, !12, i64 24, !12, i64 144, !9, i64 264, !9, i64 272}
!8 = !{!"_ZTS4Area", !9, i64 0, !9, i64 8, !9, i64 16}
!9 = !{!"double", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTS8powerDef", !13, i64 0, !13, i64 40, !13, i64 80}
!13 = !{!"_ZTS15powerComponents", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32}
!14 = !{!"any pointer", !10, i64 0}
!15 = !{!"bool", !10, i64 0}
!16 = !{!"int", !10, i64 0}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = !{!9, !9, i64 0}
!20 = !{!6, !15, i64 1696}
!21 = !{!6, !16, i64 328}
!22 = !{!6, !16, i64 292}
!23 = !{!6, !16, i64 352}
!24 = !{!6, !16, i64 356}
!25 = !{!6, !16, i64 332}
!26 = !{!6, !16, i64 336}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = !{!6, !16, i64 324}
!30 = distinct !{!30, !28}
!31 = !{!6, !16, i64 340}
!32 = distinct !{!32, !28}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass,VectorCombinePass