; LLVM IR from gem5/gem5 :: ext/mcpat/cacti/wire.ll (ZN4Wire18delay_optimal_wireEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }
%class.Wire = type { %class.Component, i32, double, double, i32, double, double, double, double, double, i32, double, double, double, %"class.std::__cxx11::list", %class.Component, %class.Component, %class.Component, double, ptr }
%"class.std::__cxx11::list" = type { %"class.std::__cxx11::_List_base" }
%"class.std::__cxx11::_List_base" = type { %"struct.std::__cxx11::_List_base<Component, std::allocator<Component>>::_List_impl" }
%"struct.std::__cxx11::_List_base<Component, std::allocator<Component>>::_List_impl" = type { %"struct.std::__detail::_List_node_header" }
%"struct.std::__detail::_List_node_header" = type { %"struct.std::__detail::_List_node_base", i64 }
%"struct.std::__detail::_List_node_base" = type { ptr, ptr }
%class.Component = type { %class.Area, %class.powerDef, %class.powerDef, double, double }
%class.Area = type { double, double, double }
%class.powerDef = type { %class.powerComponents, %class.powerComponents, %class.powerComponents }
%class.powerComponents = type { double, double, double, double, double }

@g_tp = external global %class.TechnologyParameter, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Area8set_areaEd(ptr noundef nonnull align 8 dereferenceable(24), double noundef) #1 align 2

declare noundef double @_ZN9Component17compute_gate_areaEiiddd(ptr noundef nonnull align 8 dereferenceable(280), i32 noundef, i32 noundef, double noundef, double noundef, double noundef) #2

declare noundef double @_Z8drain_C_diiidbbb(double noundef, i32 noundef, i32 noundef, i32 noundef, double noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext) #2

declare noundef double @_Z6gate_Cddbbb(double noundef, double noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext) #2

declare noundef double @_Z7tr_R_ondiibbb(double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_ZN4Wire8wire_capEdb(ptr noundef nonnull align 8 dereferenceable(1264), double noundef, i1 noundef zeroext) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_ZN4Wire8wire_resEd(ptr noundef nonnull align 8 dereferenceable(1264), double noundef) #1 align 2

declare noundef double @_Z21pmos_to_nmos_sz_ratiobb(i1 noundef zeroext, i1 noundef zeroext) #2

; Function Attrs: nounwind
declare double @sqrt(double noundef) #4

declare noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) #2

declare noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Wire18delay_optimal_wireEv(ptr noundef nonnull align 8 dereferenceable(1264) %0) #5 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca double, align 8
  %4 = alloca double, align 8
  %5 = alloca double, align 8
  %6 = alloca double, align 8
  %7 = alloca double, align 8
  %8 = alloca double, align 8
  %9 = alloca double, align 8
  %10 = alloca double, align 8
  %11 = alloca double, align 8
  %12 = alloca double, align 8
  %13 = alloca double, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %14 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #6
  %15 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 7
  %16 = load double, ptr %15, align 8, !tbaa !9
  store double %16, ptr %3, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #6
  %17 = call noundef double @_Z21pmos_to_nmos_sz_ratiobb(i1 noundef zeroext false, i1 noundef zeroext false)
  store double %17, ptr %4, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #6
  store double 0.000000e+00, ptr %5, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #6
  store double 0.000000e+00, ptr %6, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #6
  store double 0.000000e+00, ptr %7, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #6
  %18 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %19 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 18
  %20 = load double, ptr %19, align 8, !tbaa !32
  %21 = fadd double %18, %20
  %22 = call noundef double @_Z6gate_Cddbbb(double noundef %21, double noundef 0.000000e+00, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  store double %22, ptr %8, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #6
  %23 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 18
  %24 = load double, ptr %23, align 8, !tbaa !32
  %25 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 39), align 8, !tbaa !33
  %26 = call noundef double @_Z8drain_C_diiidbbb(double noundef %24, i32 noundef 0, i32 noundef 1, i32 noundef 1, double noundef %25, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %27 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %28 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 39), align 8, !tbaa !33
  %29 = call noundef double @_Z8drain_C_diiidbbb(double noundef %27, i32 noundef 1, i32 noundef 1, i32 noundef 1, double noundef %28, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %30 = fadd double %26, %29
  store double %30, ptr %9, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #6
  %31 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %32 = call noundef double @_Z7tr_R_ondiibbb(double noundef %31, i32 noundef 1, i32 noundef 1, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %33 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 18
  %34 = load double, ptr %33, align 8, !tbaa !32
  %35 = call noundef double @_Z7tr_R_ondiibbb(double noundef %34, i32 noundef 0, i32 noundef 1, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %36 = fadd double %32, %35
  %37 = fdiv double %36, 2.000000e+00
  store double %37, ptr %10, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #6
  %38 = load double, ptr %3, align 8, !tbaa !25
  %39 = call noundef double @_ZN4Wire8wire_resEd(ptr noundef nonnull align 8 dereferenceable(1264) %14, double noundef %38)
  store double %39, ptr %11, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #6
  %40 = load double, ptr %3, align 8, !tbaa !25
  %41 = call noundef double @_ZN4Wire8wire_capEdb(ptr noundef nonnull align 8 dereferenceable(1264) %14, double noundef %40, i1 noundef zeroext false)
  store double %41, ptr %12, align 8, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #6
  %42 = load double, ptr %10, align 8, !tbaa !25
  %43 = load double, ptr %12, align 8, !tbaa !25
  %44 = fmul double %42, %43
  %45 = load double, ptr %11, align 8, !tbaa !25
  %46 = load double, ptr %8, align 8, !tbaa !25
  %47 = fmul double %45, %46
  %48 = fdiv double %44, %47
  %49 = call double @sqrt(double noundef %48) #6
  store double %49, ptr %13, align 8, !tbaa !25
  %50 = load double, ptr %10, align 8, !tbaa !25
  %51 = fmul double 2.000000e+00, %50
  %52 = load double, ptr %9, align 8, !tbaa !25
  %53 = load double, ptr %8, align 8, !tbaa !25
  %54 = fadd double %52, %53
  %55 = fmul double %51, %54
  %56 = load double, ptr %11, align 8, !tbaa !25
  %57 = load double, ptr %3, align 8, !tbaa !25
  %58 = fdiv double %56, %57
  %59 = load double, ptr %12, align 8, !tbaa !25
  %60 = load double, ptr %3, align 8, !tbaa !25
  %61 = fdiv double %59, %60
  %62 = fmul double %58, %61
  %63 = fdiv double %55, %62
  %64 = call double @sqrt(double noundef %63) #6
  %65 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  store double %64, ptr %65, align 8, !tbaa !34
  %66 = load double, ptr %13, align 8, !tbaa !25
  %67 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 5
  store double %66, ptr %67, align 8, !tbaa !35
  %68 = load double, ptr %13, align 8, !tbaa !25
  %69 = load double, ptr %8, align 8, !tbaa !25
  %70 = load double, ptr %9, align 8, !tbaa !25
  %71 = fadd double %69, %70
  %72 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %73 = load double, ptr %72, align 8, !tbaa !34
  %74 = load double, ptr %12, align 8, !tbaa !25
  %75 = load double, ptr %3, align 8, !tbaa !25
  %76 = fdiv double %74, %75
  %77 = fmul double %73, %76
  %78 = call double @llvm.fmuladd.f64(double %68, double %71, double %77)
  %79 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 19
  %80 = load ptr, ptr %79, align 8, !tbaa !36
  %81 = getelementptr inbounds %"class.TechnologyParameter::DeviceType", ptr %80, i32 0, i32 9
  %82 = load double, ptr %81, align 8, !tbaa !37
  %83 = fmul double %78, %82
  %84 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 19
  %85 = load ptr, ptr %84, align 8, !tbaa !36
  %86 = getelementptr inbounds %"class.TechnologyParameter::DeviceType", ptr %85, i32 0, i32 9
  %87 = load double, ptr %86, align 8, !tbaa !37
  %88 = fmul double %83, %87
  store double %88, ptr %5, align 8, !tbaa !25
  %89 = load double, ptr %10, align 8, !tbaa !25
  %90 = load double, ptr %8, align 8, !tbaa !25
  %91 = load double, ptr %9, align 8, !tbaa !25
  %92 = fadd double %90, %91
  %93 = load double, ptr %10, align 8, !tbaa !25
  %94 = load double, ptr %12, align 8, !tbaa !25
  %95 = fmul double %93, %94
  %96 = load double, ptr %3, align 8, !tbaa !25
  %97 = fdiv double %95, %96
  %98 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %99 = load double, ptr %98, align 8, !tbaa !34
  %100 = fmul double %97, %99
  %101 = load double, ptr %13, align 8, !tbaa !25
  %102 = fdiv double %100, %101
  %103 = call double @llvm.fmuladd.f64(double %89, double %92, double %102)
  %104 = load double, ptr %11, align 8, !tbaa !25
  %105 = load double, ptr %3, align 8, !tbaa !25
  %106 = fdiv double %104, %105
  %107 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %108 = load double, ptr %107, align 8, !tbaa !34
  %109 = fmul double %106, %108
  %110 = load double, ptr %8, align 8, !tbaa !25
  %111 = fmul double %109, %110
  %112 = load double, ptr %13, align 8, !tbaa !25
  %113 = call double @llvm.fmuladd.f64(double %111, double %112, double %103)
  %114 = load double, ptr %11, align 8, !tbaa !25
  %115 = load double, ptr %3, align 8, !tbaa !25
  %116 = fdiv double %114, %115
  %117 = fmul double 5.000000e-01, %116
  %118 = load double, ptr %12, align 8, !tbaa !25
  %119 = load double, ptr %3, align 8, !tbaa !25
  %120 = fdiv double %118, %119
  %121 = fmul double %117, %120
  %122 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %123 = load double, ptr %122, align 8, !tbaa !34
  %124 = fmul double %121, %123
  %125 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %126 = load double, ptr %125, align 8, !tbaa !34
  %127 = call double @llvm.fmuladd.f64(double %124, double %126, double %113)
  store double %127, ptr %7, align 8, !tbaa !25
  %128 = load double, ptr %7, align 8, !tbaa !25
  %129 = fmul double 6.930000e-01, %128
  %130 = load double, ptr %3, align 8, !tbaa !25
  %131 = fmul double %129, %130
  %132 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %133 = load double, ptr %132, align 8, !tbaa !34
  %134 = fdiv double %131, %133
  %135 = getelementptr inbounds %class.Component, ptr %14, i32 0, i32 3
  store double %134, ptr %135, align 8, !tbaa !38
  %136 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 19
  %137 = load ptr, ptr %136, align 8, !tbaa !36
  %138 = getelementptr inbounds %"class.TechnologyParameter::DeviceType", ptr %137, i32 0, i32 9
  %139 = load double, ptr %138, align 8, !tbaa !37
  %140 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %141 = fmul double %139, %140
  %142 = fmul double %141, 6.500000e-05
  %143 = fmul double %142, 1.098600e+00
  %144 = load double, ptr %13, align 8, !tbaa !25
  %145 = fmul double %143, %144
  %146 = load double, ptr %7, align 8, !tbaa !25
  %147 = fmul double %145, %146
  store double %147, ptr %6, align 8, !tbaa !25
  %148 = getelementptr inbounds %class.Component, ptr %14, i32 0, i32 0
  %149 = load double, ptr %3, align 8, !tbaa !25
  %150 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %151 = load double, ptr %150, align 8, !tbaa !34
  %152 = fdiv double %149, %151
  %153 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 18
  %154 = load double, ptr %153, align 8, !tbaa !32
  %155 = load double, ptr %13, align 8, !tbaa !25
  %156 = fmul double %154, %155
  %157 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %158 = load double, ptr %13, align 8, !tbaa !25
  %159 = fmul double %157, %158
  %160 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 39), align 8, !tbaa !33
  %161 = call noundef double @_ZN9Component17compute_gate_areaEiiddd(ptr noundef nonnull align 8 dereferenceable(280) %14, i32 noundef 0, i32 noundef 1, double noundef %156, double noundef %159, double noundef %160)
  %162 = fmul double %152, %161
  call void @_ZN4Area8set_areaEd(ptr noundef nonnull align 8 dereferenceable(24) %148, double noundef %162)
  %163 = load double, ptr %3, align 8, !tbaa !25
  %164 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %165 = load double, ptr %164, align 8, !tbaa !34
  %166 = fdiv double %163, %165
  %167 = load double, ptr %5, align 8, !tbaa !25
  %168 = load double, ptr %6, align 8, !tbaa !25
  %169 = fadd double %167, %168
  %170 = fmul double %166, %169
  %171 = getelementptr inbounds %class.Component, ptr %14, i32 0, i32 1
  %172 = getelementptr inbounds %class.powerDef, ptr %171, i32 0, i32 0
  %173 = getelementptr inbounds %class.powerComponents, ptr %172, i32 0, i32 0
  store double %170, ptr %173, align 8, !tbaa !39
  %174 = load double, ptr %3, align 8, !tbaa !25
  %175 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %176 = load double, ptr %175, align 8, !tbaa !34
  %177 = fdiv double %174, %176
  %178 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 19
  %179 = load ptr, ptr %178, align 8, !tbaa !36
  %180 = getelementptr inbounds %"class.TechnologyParameter::DeviceType", ptr %179, i32 0, i32 9
  %181 = load double, ptr %180, align 8, !tbaa !37
  %182 = fmul double %177, %181
  %183 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %184 = load double, ptr %13, align 8, !tbaa !25
  %185 = fmul double %183, %184
  %186 = load double, ptr %4, align 8, !tbaa !25
  %187 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %188 = fmul double %186, %187
  %189 = load double, ptr %13, align 8, !tbaa !25
  %190 = fmul double %188, %189
  %191 = call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %185, double noundef %190, i32 noundef 1, i32 noundef 2, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %192 = fmul double %182, %191
  %193 = getelementptr inbounds %class.Component, ptr %14, i32 0, i32 1
  %194 = getelementptr inbounds %class.powerDef, ptr %193, i32 0, i32 0
  %195 = getelementptr inbounds %class.powerComponents, ptr %194, i32 0, i32 1
  store double %192, ptr %195, align 8, !tbaa !40
  %196 = load double, ptr %3, align 8, !tbaa !25
  %197 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 6
  %198 = load double, ptr %197, align 8, !tbaa !34
  %199 = fdiv double %196, %198
  %200 = getelementptr inbounds %class.Wire, ptr %14, i32 0, i32 19
  %201 = load ptr, ptr %200, align 8, !tbaa !36
  %202 = getelementptr inbounds %"class.TechnologyParameter::DeviceType", ptr %201, i32 0, i32 9
  %203 = load double, ptr %202, align 8, !tbaa !37
  %204 = fmul double %199, %203
  %205 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %206 = load double, ptr %13, align 8, !tbaa !25
  %207 = fmul double %205, %206
  %208 = load double, ptr %4, align 8, !tbaa !25
  %209 = load double, ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 1), align 8, !tbaa !26
  %210 = fmul double %208, %209
  %211 = load double, ptr %13, align 8, !tbaa !25
  %212 = fmul double %210, %211
  %213 = call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %207, double noundef %212, i32 noundef 1, i32 noundef 2, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %214 = fmul double %204, %213
  %215 = getelementptr inbounds %class.Component, ptr %14, i32 0, i32 1
  %216 = getelementptr inbounds %class.powerDef, ptr %215, i32 0, i32 0
  %217 = getelementptr inbounds %class.powerComponents, ptr %216, i32 0, i32 2
  store double %214, ptr %217, align 8, !tbaa !41
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #6
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 328}
!10 = !{!"_ZTS4Wire", !11, i64 0, !16, i64 280, !13, i64 288, !13, i64 296, !17, i64 304, !13, i64 312, !13, i64 320, !13, i64 328, !13, i64 336, !13, i64 344, !18, i64 352, !13, i64 360, !13, i64 368, !13, i64 376, !19, i64 384, !11, i64 408, !11, i64 688, !11, i64 968, !13, i64 1248, !6, i64 1256}
!11 = !{!"_ZTS9Component", !12, i64 0, !14, i64 24, !14, i64 144, !13, i64 264, !13, i64 272}
!12 = !{!"_ZTS4Area", !13, i64 0, !13, i64 8, !13, i64 16}
!13 = !{!"double", !7, i64 0}
!14 = !{!"_ZTS8powerDef", !15, i64 0, !15, i64 40, !15, i64 80}
!15 = !{!"_ZTS15powerComponents", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32}
!16 = !{!"_ZTS9Wire_type", !7, i64 0}
!17 = !{!"_ZTS14Wire_placement", !7, i64 0}
!18 = !{!"int", !7, i64 0}
!19 = !{!"_ZTSNSt7__cxx114listI9ComponentSaIS1_EEE", !20, i64 0}
!20 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EEE", !21, i64 0}
!21 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EE10_List_implE", !22, i64 0}
!22 = !{!"_ZTSNSt8__detail17_List_node_headerE", !23, i64 0, !24, i64 16}
!23 = !{!"_ZTSNSt8__detail15_List_node_baseE", !6, i64 0, !6, i64 8}
!24 = !{!"long", !7, i64 0}
!25 = !{!13, !13, i64 0}
!26 = !{!27, !13, i64 8}
!27 = !{!"_ZTS19TechnologyParameter", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !13, i64 56, !13, i64 64, !13, i64 72, !13, i64 80, !13, i64 88, !13, i64 96, !13, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !13, i64 136, !13, i64 144, !13, i64 152, !13, i64 160, !13, i64 168, !13, i64 176, !13, i64 184, !13, i64 192, !13, i64 200, !13, i64 208, !13, i64 216, !13, i64 224, !13, i64 232, !13, i64 240, !13, i64 248, !13, i64 256, !13, i64 264, !13, i64 272, !13, i64 280, !13, i64 288, !13, i64 296, !13, i64 304, !13, i64 312, !13, i64 320, !13, i64 328, !13, i64 336, !13, i64 344, !24, i64 352, !28, i64 360, !28, i64 528, !28, i64 696, !28, i64 864, !28, i64 1032, !29, i64 1200, !29, i64 1264, !29, i64 1328, !30, i64 1392, !31, i64 1416, !31, i64 1464, !31, i64 1512}
!28 = !{!"_ZTSN19TechnologyParameter10DeviceTypeE", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !13, i64 56, !13, i64 64, !13, i64 72, !13, i64 80, !13, i64 88, !13, i64 96, !13, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !13, i64 136, !13, i64 144, !13, i64 152, !13, i64 160}
!29 = !{!"_ZTSN19TechnologyParameter16InterconnectTypeE", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !13, i64 56}
!30 = !{!"_ZTSN19TechnologyParameter13ScalingFactorE", !13, i64 0, !13, i64 8, !13, i64 16}
!31 = !{!"_ZTSN19TechnologyParameter10MemoryTypeE", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40}
!32 = !{!10, !13, i64 1248}
!33 = !{!27, !13, i64 312}
!34 = !{!10, !13, i64 320}
!35 = !{!10, !13, i64 312}
!36 = !{!10, !6, i64 1256}
!37 = !{!28, !13, i64 72}
!38 = !{!11, !13, i64 264}
!39 = !{!11, !13, i64 24}
!40 = !{!11, !13, i64 32}
!41 = !{!11, !13, i64 40}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }

@g_tp = external local_unnamed_addr global %class.TechnologyParameter, align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Area8set_areaEd(ptr noundef nonnull align 8 dereferenceable(24), double noundef) local_unnamed_addr #0 align 2

declare noundef double @_ZN9Component17compute_gate_areaEiiddd(ptr noundef nonnull align 8 dereferenceable(280), i32 noundef, i32 noundef, double noundef, double noundef, double noundef) local_unnamed_addr #1

declare noundef double @_Z8drain_C_diiidbbb(double noundef, i32 noundef, i32 noundef, i32 noundef, double noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext) local_unnamed_addr #1

declare noundef double @_Z6gate_Cddbbb(double noundef, double noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext) local_unnamed_addr #1

declare noundef double @_Z7tr_R_ondiibbb(double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_ZN4Wire8wire_capEdb(ptr noundef nonnull align 8 dereferenceable(1264), double noundef, i1 noundef zeroext) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_ZN4Wire8wire_resEd(ptr noundef nonnull align 8 dereferenceable(1264), double noundef) local_unnamed_addr #0 align 2

declare noundef double @_Z21pmos_to_nmos_sz_ratiobb(i1 noundef zeroext, i1 noundef zeroext) local_unnamed_addr #1

; Function Attrs: mustprogress nofree nounwind willreturn memory(write)
declare double @sqrt(double noundef) local_unnamed_addr #3

declare noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) local_unnamed_addr #1

declare noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef, double noundef, i32 noundef, i32 noundef, i1 noundef zeroext, i1 noundef zeroext, i1 noundef zeroext, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Wire18delay_optimal_wireEv(ptr noundef nonnull align 8 dereferenceable(1264) %0) local_unnamed_addr #4 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 328
  %3 = load double, ptr %2, align 8, !tbaa !5
  %4 = tail call noundef double @_Z21pmos_to_nmos_sz_ratiobb(i1 noundef zeroext false, i1 noundef zeroext false)
  %5 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 8), align 8, !tbaa !24
  %6 = getelementptr inbounds i8, ptr %0, i64 1248
  %7 = load double, ptr %6, align 8, !tbaa !30
  %8 = fadd double %5, %7
  %9 = tail call noundef double @_Z6gate_Cddbbb(double noundef %8, double noundef 0.000000e+00, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %10 = load double, ptr %6, align 8, !tbaa !30
  %11 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 312), align 8, !tbaa !31
  %12 = tail call noundef double @_Z8drain_C_diiidbbb(double noundef %10, i32 noundef 0, i32 noundef 1, i32 noundef 1, double noundef %11, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %13 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 8), align 8, !tbaa !24
  %14 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 312), align 8, !tbaa !31
  %15 = tail call noundef double @_Z8drain_C_diiidbbb(double noundef %13, i32 noundef 1, i32 noundef 1, i32 noundef 1, double noundef %14, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %16 = fadd double %12, %15
  %17 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 8), align 8, !tbaa !24
  %18 = tail call noundef double @_Z7tr_R_ondiibbb(double noundef %17, i32 noundef 1, i32 noundef 1, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %19 = load double, ptr %6, align 8, !tbaa !30
  %20 = tail call noundef double @_Z7tr_R_ondiibbb(double noundef %19, i32 noundef 0, i32 noundef 1, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false)
  %21 = fadd double %18, %20
  %22 = fmul double %21, 5.000000e-01
  %23 = tail call noundef double @_ZN4Wire8wire_resEd(ptr noundef nonnull align 8 dereferenceable(1264) %0, double noundef %3)
  %24 = tail call noundef double @_ZN4Wire8wire_capEdb(ptr noundef nonnull align 8 dereferenceable(1264) %0, double noundef %3, i1 noundef zeroext false)
  %25 = fmul double %22, %24
  %26 = fmul double %9, %23
  %27 = fdiv double %25, %26
  %28 = tail call double @sqrt(double noundef %27) #5
  %29 = fmul double %22, 2.000000e+00
  %30 = fadd double %9, %16
  %31 = fmul double %30, %29
  %32 = insertelement <2 x double> poison, double %23, i64 0
  %33 = insertelement <2 x double> %32, double %24, i64 1
  %34 = insertelement <2 x double> poison, double %3, i64 0
  %35 = shufflevector <2 x double> %34, <2 x double> poison, <2 x i32> zeroinitializer
  %36 = fdiv <2 x double> %33, %35
  %37 = extractelement <2 x double> %36, i64 0
  %38 = extractelement <2 x double> %36, i64 1
  %39 = fmul double %37, %38
  %40 = fdiv double %31, %39
  %41 = tail call double @sqrt(double noundef %40) #5
  %42 = getelementptr inbounds i8, ptr %0, i64 320
  store double %41, ptr %42, align 8, !tbaa !32
  %43 = getelementptr inbounds i8, ptr %0, i64 312
  store double %28, ptr %43, align 8, !tbaa !33
  %44 = fmul double %38, %41
  %45 = tail call double @llvm.fmuladd.f64(double %28, double %30, double %44)
  %46 = getelementptr inbounds i8, ptr %0, i64 1256
  %47 = load ptr, ptr %46, align 8, !tbaa !34
  %48 = getelementptr inbounds i8, ptr %47, i64 72
  %49 = load double, ptr %48, align 8, !tbaa !35
  %50 = fmul double %45, %49
  %51 = fmul double %49, %50
  %52 = fdiv double %25, %3
  %53 = fmul double %52, %41
  %54 = fdiv double %53, %28
  %55 = tail call double @llvm.fmuladd.f64(double %22, double %30, double %54)
  %56 = fmul double %37, %41
  %57 = fmul double %9, %56
  %58 = tail call double @llvm.fmuladd.f64(double %57, double %28, double %55)
  %59 = fmul double %37, 5.000000e-01
  %60 = fmul double %59, %38
  %61 = fmul double %60, %41
  %62 = tail call double @llvm.fmuladd.f64(double %61, double %41, double %58)
  %63 = fmul double %62, 6.930000e-01
  %64 = fmul double %3, %63
  %65 = fdiv double %64, %41
  %66 = getelementptr inbounds i8, ptr %0, i64 264
  store double %65, ptr %66, align 8, !tbaa !36
  %67 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 8), align 8, !tbaa !24
  %68 = fmul double %49, %67
  %69 = fmul double %68, 6.500000e-05
  %70 = fmul double %69, 1.098600e+00
  %71 = fmul double %28, %70
  %72 = fmul double %62, %71
  %73 = fdiv double %3, %41
  %74 = load double, ptr %6, align 8, !tbaa !30
  %75 = fmul double %28, %74
  %76 = fmul double %28, %67
  %77 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 312), align 8, !tbaa !31
  %78 = tail call noundef double @_ZN9Component17compute_gate_areaEiiddd(ptr noundef nonnull align 8 dereferenceable(280) %0, i32 noundef 0, i32 noundef 1, double noundef %75, double noundef %76, double noundef %77)
  %79 = fmul double %73, %78
  tail call void @_ZN4Area8set_areaEd(ptr noundef nonnull align 8 dereferenceable(24) %0, double noundef %79)
  %80 = load double, ptr %42, align 8, !tbaa !32
  %81 = fdiv double %3, %80
  %82 = fadd double %51, %72
  %83 = fmul double %81, %82
  %84 = getelementptr inbounds i8, ptr %0, i64 24
  store double %83, ptr %84, align 8, !tbaa !37
  %85 = load ptr, ptr %46, align 8, !tbaa !34
  %86 = getelementptr inbounds i8, ptr %85, i64 72
  %87 = load double, ptr %86, align 8, !tbaa !35
  %88 = fmul double %81, %87
  %89 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 8), align 8, !tbaa !24
  %90 = fmul double %28, %89
  %91 = fmul double %4, %89
  %92 = fmul double %28, %91
  %93 = tail call noundef double @_Z17cmos_Isub_leakageddi9Gate_typebbb17Half_net_topology(double noundef %90, double noundef %92, i32 noundef 1, i32 noundef 2, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %94 = fmul double %88, %93
  %95 = getelementptr inbounds i8, ptr %0, i64 32
  store double %94, ptr %95, align 8, !tbaa !38
  %96 = load double, ptr %42, align 8, !tbaa !32
  %97 = fdiv double %3, %96
  %98 = load ptr, ptr %46, align 8, !tbaa !34
  %99 = getelementptr inbounds i8, ptr %98, i64 72
  %100 = load double, ptr %99, align 8, !tbaa !35
  %101 = fmul double %97, %100
  %102 = load double, ptr getelementptr inbounds (i8, ptr @g_tp, i64 8), align 8, !tbaa !24
  %103 = fmul double %28, %102
  %104 = fmul double %4, %102
  %105 = fmul double %28, %104
  %106 = tail call noundef double @_Z15cmos_Ig_leakageddi9Gate_typebbb17Half_net_topology(double noundef %103, double noundef %105, i32 noundef 1, i32 noundef 2, i1 noundef zeroext false, i1 noundef zeroext false, i1 noundef zeroext false, i32 noundef 1)
  %107 = fmul double %101, %106
  %108 = getelementptr inbounds i8, ptr %0, i64 40
  store double %107, ptr %108, align 8, !tbaa !39
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { mustprogress nofree nounwind willreturn memory(write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 328}
!6 = !{!"_ZTS4Wire", !7, i64 0, !14, i64 280, !9, i64 288, !9, i64 296, !15, i64 304, !9, i64 312, !9, i64 320, !9, i64 328, !9, i64 336, !9, i64 344, !16, i64 352, !9, i64 360, !9, i64 368, !9, i64 376, !17, i64 384, !7, i64 408, !7, i64 688, !7, i64 968, !9, i64 1248, !22, i64 1256}
!7 = !{!"_ZTS9Component", !8, i64 0, !12, i64 24, !12, i64 144, !9, i64 264, !9, i64 272}
!8 = !{!"_ZTS4Area", !9, i64 0, !9, i64 8, !9, i64 16}
!9 = !{!"double", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTS8powerDef", !13, i64 0, !13, i64 40, !13, i64 80}
!13 = !{!"_ZTS15powerComponents", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32}
!14 = !{!"_ZTS9Wire_type", !10, i64 0}
!15 = !{!"_ZTS14Wire_placement", !10, i64 0}
!16 = !{!"int", !10, i64 0}
!17 = !{!"_ZTSNSt7__cxx114listI9ComponentSaIS1_EEE", !18, i64 0}
!18 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EEE", !19, i64 0}
!19 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EE10_List_implE", !20, i64 0}
!20 = !{!"_ZTSNSt8__detail17_List_node_headerE", !21, i64 0, !23, i64 16}
!21 = !{!"_ZTSNSt8__detail15_List_node_baseE", !22, i64 0, !22, i64 8}
!22 = !{!"any pointer", !10, i64 0}
!23 = !{!"long", !10, i64 0}
!24 = !{!25, !9, i64 8}
!25 = !{!"_ZTS19TechnologyParameter", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56, !9, i64 64, !9, i64 72, !9, i64 80, !9, i64 88, !9, i64 96, !9, i64 104, !9, i64 112, !9, i64 120, !9, i64 128, !9, i64 136, !9, i64 144, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176, !9, i64 184, !9, i64 192, !9, i64 200, !9, i64 208, !9, i64 216, !9, i64 224, !9, i64 232, !9, i64 240, !9, i64 248, !9, i64 256, !9, i64 264, !9, i64 272, !9, i64 280, !9, i64 288, !9, i64 296, !9, i64 304, !9, i64 312, !9, i64 320, !9, i64 328, !9, i64 336, !9, i64 344, !23, i64 352, !26, i64 360, !26, i64 528, !26, i64 696, !26, i64 864, !26, i64 1032, !27, i64 1200, !27, i64 1264, !27, i64 1328, !28, i64 1392, !29, i64 1416, !29, i64 1464, !29, i64 1512}
!26 = !{!"_ZTSN19TechnologyParameter10DeviceTypeE", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56, !9, i64 64, !9, i64 72, !9, i64 80, !9, i64 88, !9, i64 96, !9, i64 104, !9, i64 112, !9, i64 120, !9, i64 128, !9, i64 136, !9, i64 144, !9, i64 152, !9, i64 160}
!27 = !{!"_ZTSN19TechnologyParameter16InterconnectTypeE", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56}
!28 = !{!"_ZTSN19TechnologyParameter13ScalingFactorE", !9, i64 0, !9, i64 8, !9, i64 16}
!29 = !{!"_ZTSN19TechnologyParameter10MemoryTypeE", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !9, i64 40}
!30 = !{!6, !9, i64 1248}
!31 = !{!25, !9, i64 312}
!32 = !{!6, !9, i64 320}
!33 = !{!6, !9, i64 312}
!34 = !{!6, !22, i64 1256}
!35 = !{!26, !9, i64 72}
!36 = !{!7, !9, i64 264}
!37 = !{!7, !9, i64 24}
!38 = !{!7, !9, i64 32}
!39 = !{!7, !9, i64 40}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SLPVectorizerPass,SROAPass,TailCallElimPass