; LLVM IR from gem5/gem5 :: ext/mcpat/cacti/wire.ll (ZN4Wire8wire_resEd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }
%class.Wire = type { %class.Component, i32, double, double, i32, double, double, double, double, double, i32, double, double, double, %"class.std::__cxx11::list", %class.Component, %class.Component, %class.Component, double, ptr }
%"class.std::__cxx11::list" = type { %"class.std::__cxx11::_List_base" }
%"class.std::__cxx11::_List_base" = type { %"struct.std::__cxx11::_List_base<Component, std::allocator<Component>>::_List_impl" }
%"struct.std::__cxx11::_List_base<Component, std::allocator<Component>>::_List_impl" = type { %"struct.std::__detail::_List_node_header" }
%"struct.std::__detail::_List_node_header" = type { %"struct.std::__detail::_List_node_base", i64 }
%"struct.std::__detail::_List_node_base" = type { ptr, ptr }
%class.Component = type { %class.Area, %class.powerDef, %class.powerDef, double, double }
%class.Area = type { double, double, double }
%class.powerDef = type { %class.powerComponents, %class.powerComponents, %class.powerComponents }
%class.powerComponents = type { double, double, double, double, double }

@g_tp = external global %class.TechnologyParameter, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef double @_ZN4Wire8wire_resEd(ptr noundef nonnull align 8 dereferenceable(1264) %0, double noundef %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca double, align 8
  %5 = alloca double, align 8
  %6 = alloca double, align 8
  %7 = alloca double, align 8
  %8 = alloca double, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store double %1, ptr %4, align 8, !tbaa !9
  %9 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  store double 1.050000e+00, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store double 0.000000e+00, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  store double 0.000000e+00, ptr %8, align 8, !tbaa !9
  %10 = getelementptr inbounds %class.Wire, ptr %9, i32 0, i32 4
  %11 = load i32, ptr %10, align 8, !tbaa !11
  switch i32 %11, label %16 [
    i32 0, label %12
    i32 1, label %14
  ]

12:                                               ; preds = %2
  %13 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::InterconnectType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 52), i32 0, i32 5), align 8, !tbaa !26
  store double %13, ptr %5, align 8, !tbaa !9
  br label %18

14:                                               ; preds = %2
  %15 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::InterconnectType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 51), i32 0, i32 5), align 8, !tbaa !32
  store double %15, ptr %5, align 8, !tbaa !9
  br label %18

16:                                               ; preds = %2
  %17 = load double, ptr getelementptr inbounds (%"class.TechnologyParameter::InterconnectType", ptr getelementptr inbounds (%class.TechnologyParameter, ptr @g_tp, i32 0, i32 50), i32 0, i32 5), align 8, !tbaa !33
  store double %17, ptr %5, align 8, !tbaa !9
  br label %18

18:                                               ; preds = %16, %14, %12
  %19 = load double, ptr %6, align 8, !tbaa !9
  %20 = getelementptr inbounds %class.Wire, ptr %9, i32 0, i32 13
  %21 = load double, ptr %20, align 8, !tbaa !34
  %22 = fmul double %19, %21
  %23 = fmul double %22, 0x3EB0C6F7A0B5ED8D
  %24 = load double, ptr %4, align 8, !tbaa !9
  %25 = fmul double %23, %24
  %26 = load double, ptr %5, align 8, !tbaa !9
  %27 = getelementptr inbounds %class.Wire, ptr %9, i32 0, i32 3
  %28 = load double, ptr %27, align 8, !tbaa !35
  %29 = fmul double %26, %28
  %30 = getelementptr inbounds %class.Wire, ptr %9, i32 0, i32 11
  %31 = load double, ptr %30, align 8, !tbaa !36
  %32 = fdiv double %29, %31
  %33 = load double, ptr %7, align 8, !tbaa !9
  %34 = fsub double %32, %33
  %35 = load double, ptr %8, align 8, !tbaa !9
  %36 = fsub double %34, %35
  %37 = getelementptr inbounds %class.Wire, ptr %9, i32 0, i32 3
  %38 = load double, ptr %37, align 8, !tbaa !35
  %39 = load double, ptr %8, align 8, !tbaa !9
  %40 = call double @llvm.fmuladd.f64(double -2.000000e+00, double %39, double %38)
  %41 = fmul double %36, %40
  %42 = fdiv double %25, %41
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  ret double %42
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !18, i64 304}
!12 = !{!"_ZTS4Wire", !13, i64 0, !17, i64 280, !10, i64 288, !10, i64 296, !18, i64 304, !10, i64 312, !10, i64 320, !10, i64 328, !10, i64 336, !10, i64 344, !19, i64 352, !10, i64 360, !10, i64 368, !10, i64 376, !20, i64 384, !13, i64 408, !13, i64 688, !13, i64 968, !10, i64 1248, !6, i64 1256}
!13 = !{!"_ZTS9Component", !14, i64 0, !15, i64 24, !15, i64 144, !10, i64 264, !10, i64 272}
!14 = !{!"_ZTS4Area", !10, i64 0, !10, i64 8, !10, i64 16}
!15 = !{!"_ZTS8powerDef", !16, i64 0, !16, i64 40, !16, i64 80}
!16 = !{!"_ZTS15powerComponents", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32}
!17 = !{!"_ZTS9Wire_type", !7, i64 0}
!18 = !{!"_ZTS14Wire_placement", !7, i64 0}
!19 = !{!"int", !7, i64 0}
!20 = !{!"_ZTSNSt7__cxx114listI9ComponentSaIS1_EEE", !21, i64 0}
!21 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EEE", !22, i64 0}
!22 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EE10_List_implE", !23, i64 0}
!23 = !{!"_ZTSNSt8__detail17_List_node_headerE", !24, i64 0, !25, i64 16}
!24 = !{!"_ZTSNSt8__detail15_List_node_baseE", !6, i64 0, !6, i64 8}
!25 = !{!"long", !7, i64 0}
!26 = !{!27, !10, i64 1368}
!27 = !{!"_ZTS19TechnologyParameter", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !10, i64 256, !10, i64 264, !10, i64 272, !10, i64 280, !10, i64 288, !10, i64 296, !10, i64 304, !10, i64 312, !10, i64 320, !10, i64 328, !10, i64 336, !10, i64 344, !25, i64 352, !28, i64 360, !28, i64 528, !28, i64 696, !28, i64 864, !28, i64 1032, !29, i64 1200, !29, i64 1264, !29, i64 1328, !30, i64 1392, !31, i64 1416, !31, i64 1464, !31, i64 1512}
!28 = !{!"_ZTSN19TechnologyParameter10DeviceTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160}
!29 = !{!"_ZTSN19TechnologyParameter16InterconnectTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56}
!30 = !{!"_ZTSN19TechnologyParameter13ScalingFactorE", !10, i64 0, !10, i64 8, !10, i64 16}
!31 = !{!"_ZTSN19TechnologyParameter10MemoryTypeE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40}
!32 = !{!27, !10, i64 1304}
!33 = !{!27, !10, i64 1240}
!34 = !{!12, !10, i64 376}
!35 = !{!12, !10, i64 296}
!36 = !{!12, !10, i64 360}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TechnologyParameter = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::DeviceType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::InterconnectType", %"class.TechnologyParameter::ScalingFactor", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType", %"class.TechnologyParameter::MemoryType" }
%"class.TechnologyParameter::DeviceType" = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::InterconnectType" = type { double, double, double, double, double, double, double, double }
%"class.TechnologyParameter::ScalingFactor" = type { double, double, double }
%"class.TechnologyParameter::MemoryType" = type { double, double, double, double, double, double }

@g_tp = external local_unnamed_addr global %class.TechnologyParameter, align 8

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(read, inaccessiblemem: none) uwtable
define dso_local noundef double @_ZN4Wire8wire_resEd(ptr nocapture noundef nonnull readonly align 8 dereferenceable(1264) %0, double noundef %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 304
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %switch.selectcmp = icmp eq i32 %4, 1
  %switch.select = select i1 %switch.selectcmp, ptr getelementptr inbounds (i8, ptr @g_tp, i64 1304), ptr getelementptr inbounds (i8, ptr @g_tp, i64 1240)
  %switch.selectcmp7 = icmp eq i32 %4, 0
  %switch.select8 = select i1 %switch.selectcmp7, ptr getelementptr inbounds (i8, ptr @g_tp, i64 1368), ptr %switch.select
  %.0 = load double, ptr %switch.select8, align 8, !tbaa !24
  %5 = getelementptr inbounds i8, ptr %0, i64 376
  %6 = load double, ptr %5, align 8, !tbaa !25
  %7 = fmul double %6, 1.050000e+00
  %8 = fmul double %7, 0x3EB0C6F7A0B5ED8D
  %9 = fmul double %8, %1
  %10 = getelementptr inbounds i8, ptr %0, i64 296
  %11 = load double, ptr %10, align 8, !tbaa !26
  %12 = fmul double %.0, %11
  %13 = getelementptr inbounds i8, ptr %0, i64 360
  %14 = load double, ptr %13, align 8, !tbaa !27
  %15 = fdiv double %12, %14
  %16 = fmul double %11, %15
  %17 = fdiv double %9, %16
  ret double %17
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(read, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !15, i64 304}
!6 = !{!"_ZTS4Wire", !7, i64 0, !14, i64 280, !9, i64 288, !9, i64 296, !15, i64 304, !9, i64 312, !9, i64 320, !9, i64 328, !9, i64 336, !9, i64 344, !16, i64 352, !9, i64 360, !9, i64 368, !9, i64 376, !17, i64 384, !7, i64 408, !7, i64 688, !7, i64 968, !9, i64 1248, !22, i64 1256}
!7 = !{!"_ZTS9Component", !8, i64 0, !12, i64 24, !12, i64 144, !9, i64 264, !9, i64 272}
!8 = !{!"_ZTS4Area", !9, i64 0, !9, i64 8, !9, i64 16}
!9 = !{!"double", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTS8powerDef", !13, i64 0, !13, i64 40, !13, i64 80}
!13 = !{!"_ZTS15powerComponents", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32}
!14 = !{!"_ZTS9Wire_type", !10, i64 0}
!15 = !{!"_ZTS14Wire_placement", !10, i64 0}
!16 = !{!"int", !10, i64 0}
!17 = !{!"_ZTSNSt7__cxx114listI9ComponentSaIS1_EEE", !18, i64 0}
!18 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EEE", !19, i64 0}
!19 = !{!"_ZTSNSt7__cxx1110_List_baseI9ComponentSaIS1_EE10_List_implE", !20, i64 0}
!20 = !{!"_ZTSNSt8__detail17_List_node_headerE", !21, i64 0, !23, i64 16}
!21 = !{!"_ZTSNSt8__detail15_List_node_baseE", !22, i64 0, !22, i64 8}
!22 = !{!"any pointer", !10, i64 0}
!23 = !{!"long", !10, i64 0}
!24 = !{!9, !9, i64 0}
!25 = !{!6, !9, i64 376}
!26 = !{!6, !9, i64 296}
!27 = !{!6, !9, i64 360}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass