; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/fx (scfx_rep)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_bitref_r" = type <{ ptr, i32, [4 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_nanEv(ptr noundef nonnull align 8 dereferenceable(37)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_infEv(ptr noundef nonnull align 8 dereferenceable(37)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dt8scfx_rep3setEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37), i32 noundef, ptr noundef nonnull align 4 dereferenceable(28)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dt8scfx_rep5clearEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37), i32 noundef, ptr noundef nonnull align 4 dereferenceable(28)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt10sc_bv_base6lengthEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN5sc_dt8scfx_rep9set_sliceEiiRKNS_11scfx_paramsERKNS_10sc_bv_baseE(ptr noundef nonnull align 8 dereferenceable(37) %0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull align 4 dereferenceable(28) %3, ptr noundef nonnull align 8 dereferenceable(24) %4) #2 align 2 {
  %6 = alloca i1, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca %"class.sc_dt::sc_bitref_r", align 8
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store i32 %2, ptr %9, align 4, !tbaa !9
  store ptr %3, ptr %10, align 8, !tbaa !5
  store ptr %4, ptr %11, align 8, !tbaa !5
  %15 = load ptr, ptr %7, align 8
  %16 = call noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_nanEv(ptr noundef nonnull align 8 dereferenceable(37) %15)
  br i1 %16, label %19, label %17

17:                                               ; preds = %5
  %18 = call noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_infEv(ptr noundef nonnull align 8 dereferenceable(37) %15)
  br i1 %18, label %19, label %20

19:                                               ; preds = %17, %5
  store i1 false, ptr %6, align 1
  br label %55

20:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %21 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %21, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %51, %20
  %23 = load i32, ptr %13, align 4, !tbaa !9
  %24 = load ptr, ptr %11, align 8, !tbaa !5
  %25 = call noundef i32 @_ZNK5sc_dt10sc_bv_base6lengthEv(ptr noundef nonnull align 8 dereferenceable(24) %24)
  %26 = icmp slt i32 %23, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %22
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  br label %54

28:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 16, ptr %14) #4
  %29 = load ptr, ptr %11, align 8, !tbaa !5
  %30 = load i32, ptr %13, align 4, !tbaa !9
  call void @_ZNK5sc_dt8sc_proxyINS_10sc_bv_baseEEixEi(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_bitref_r") align 8 %14, ptr noundef nonnull align 8 dereferenceable(8) %29, i32 noundef %30)
  %31 = call noundef zeroext i1 @_ZNK5sc_dt11sc_bitref_rINS_10sc_bv_baseEE7to_boolEv(ptr noundef nonnull align 8 dereferenceable(12) %14)
  call void @llvm.lifetime.end.p0(i64 16, ptr %14) #4
  br i1 %31, label %32, label %36

32:                                               ; preds = %28
  %33 = load i32, ptr %12, align 4, !tbaa !9
  %34 = load ptr, ptr %10, align 8, !tbaa !5
  %35 = call noundef zeroext i1 @_ZN5sc_dt8scfx_rep3setEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37) %15, i32 noundef %33, ptr noundef nonnull align 4 dereferenceable(28) %34)
  br label %40

36:                                               ; preds = %28
  %37 = load i32, ptr %12, align 4, !tbaa !9
  %38 = load ptr, ptr %10, align 8, !tbaa !5
  %39 = call noundef zeroext i1 @_ZN5sc_dt8scfx_rep5clearEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37) %15, i32 noundef %37, ptr noundef nonnull align 4 dereferenceable(28) %38)
  br label %40

40:                                               ; preds = %36, %32
  %41 = load i32, ptr %8, align 4, !tbaa !9
  %42 = load i32, ptr %9, align 4, !tbaa !9
  %43 = icmp sge i32 %41, %42
  br i1 %43, label %44, label %47

44:                                               ; preds = %40
  %45 = load i32, ptr %12, align 4, !tbaa !9
  %46 = add nsw i32 %45, 1
  store i32 %46, ptr %12, align 4, !tbaa !9
  br label %50

47:                                               ; preds = %40
  %48 = load i32, ptr %12, align 4, !tbaa !9
  %49 = add nsw i32 %48, -1
  store i32 %49, ptr %12, align 4, !tbaa !9
  br label %50

50:                                               ; preds = %47, %44
  br label %51

51:                                               ; preds = %50
  %52 = load i32, ptr %13, align 4, !tbaa !9
  %53 = add nsw i32 %52, 1
  store i32 %53, ptr %13, align 4, !tbaa !9
  br label %22, !llvm.loop !11

54:                                               ; preds = %27
  store i1 true, ptr %6, align 1
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  br label %55

55:                                               ; preds = %54, %19
  %56 = load i1, ptr %6, align 1
  ret i1 %56
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK5sc_dt8sc_proxyINS_10sc_bv_baseEEixEi(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_bitref_r") align 8, ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK5sc_dt11sc_bitref_rINS_10sc_bv_baseEE7to_boolEv(ptr noundef nonnull align 8 dereferenceable(12)) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_bitref_r" = type <{ ptr, i32, [4 x i8] }>

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_nanEv(ptr noundef nonnull align 8 dereferenceable(37)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_infEv(ptr noundef nonnull align 8 dereferenceable(37)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dt8scfx_rep3setEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37), i32 noundef, ptr noundef nonnull align 4 dereferenceable(28)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dt8scfx_rep5clearEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37), i32 noundef, ptr noundef nonnull align 4 dereferenceable(28)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt10sc_bv_base6lengthEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN5sc_dt8scfx_rep9set_sliceEiiRKNS_11scfx_paramsERKNS_10sc_bv_baseE(ptr noundef nonnull align 8 dereferenceable(37) %0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull align 4 dereferenceable(28) %3, ptr noundef nonnull align 8 dereferenceable(24) %4) local_unnamed_addr #2 align 2 {
  %6 = alloca %"class.sc_dt::sc_bitref_r", align 8
  %7 = tail call noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_nanEv(ptr noundef nonnull align 8 dereferenceable(37) %0)
  br i1 %7, label %.loopexit, label %8

8:                                                ; preds = %5
  %9 = tail call noundef zeroext i1 @_ZNK5sc_dt8scfx_rep6is_infEv(ptr noundef nonnull align 8 dereferenceable(37) %0)
  br i1 %9, label %.loopexit, label %.preheader

.preheader:                                       ; preds = %8
  %10 = tail call noundef i32 @_ZNK5sc_dt10sc_bv_base6lengthEv(ptr noundef nonnull align 8 dereferenceable(24) %4)
  %11 = icmp sgt i32 %10, 0
  br i1 %11, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %.preheader
  %.not = icmp slt i32 %1, %2
  %.1.v = select i1 %.not, i32 -1, i32 1
  br label %12

12:                                               ; preds = %.lr.ph, %18
  %.018 = phi i32 [ 0, %.lr.ph ], [ %19, %18 ]
  %.01517 = phi i32 [ %2, %.lr.ph ], [ %.1, %18 ]
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #4
  call void @_ZNK5sc_dt8sc_proxyINS_10sc_bv_baseEEixEi(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_bitref_r") align 8 %6, ptr noundef nonnull align 8 dereferenceable(8) %4, i32 noundef %.018)
  %13 = call noundef zeroext i1 @_ZNK5sc_dt11sc_bitref_rINS_10sc_bv_baseEE7to_boolEv(ptr noundef nonnull align 8 dereferenceable(12) %6)
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #4
  br i1 %13, label %14, label %16

14:                                               ; preds = %12
  %15 = call noundef zeroext i1 @_ZN5sc_dt8scfx_rep3setEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37) %0, i32 noundef %.01517, ptr noundef nonnull align 4 dereferenceable(28) %3)
  br label %18

16:                                               ; preds = %12
  %17 = call noundef zeroext i1 @_ZN5sc_dt8scfx_rep5clearEiRKNS_11scfx_paramsE(ptr noundef nonnull align 8 dereferenceable(37) %0, i32 noundef %.01517, ptr noundef nonnull align 4 dereferenceable(28) %3)
  br label %18

18:                                               ; preds = %16, %14
  %.1 = add nsw i32 %.01517, %.1.v
  %19 = add nuw nsw i32 %.018, 1
  %20 = call noundef i32 @_ZNK5sc_dt10sc_bv_base6lengthEv(ptr noundef nonnull align 8 dereferenceable(24) %4)
  %21 = icmp slt i32 %19, %20
  br i1 %21, label %12, label %.loopexit, !llvm.loop !5

.loopexit:                                        ; preds = %18, %.preheader, %5, %8
  %.016 = phi i1 [ false, %8 ], [ false, %5 ], [ true, %.preheader ], [ true, %18 ]
  ret i1 %.016
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK5sc_dt8sc_proxyINS_10sc_bv_baseEEixEi(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_bitref_r") align 8, ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK5sc_dt11sc_bitref_rINS_10sc_bv_baseEE7to_boolEv(ptr noundef nonnull align 8 dereferenceable(12)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass