; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_prim_channel)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_prim_channel_registry" = type { ptr, i32, %"class.std::vector.18", ptr, ptr }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_prim_channel *, std::allocator<sc_core::sc_prim_channel *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_prim_channel *, std::allocator<sc_core::sc_prim_channel *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_prim_channel *, std::allocator<sc_core::sc_prim_channel *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_prim_channel *, std::allocator<sc_core::sc_prim_channel *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core15sc_prim_channel17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(128)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_prim_channelESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN7sc_core24sc_prim_channel_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(56) %0) #0 align 2 {
  %2 = alloca i1, align 1
  %3 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  %4 = load ptr, ptr %3, align 8
  %5 = call noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56) %4)
  %6 = getelementptr inbounds %"class.sc_core::sc_prim_channel_registry", ptr %4, i32 0, i32 1
  %7 = load i32, ptr %6, align 8, !tbaa !9
  %8 = icmp eq i32 %5, %7
  br i1 %8, label %9, label %10

9:                                                ; preds = %1
  store i1 true, ptr %2, align 1
  br label %28

10:                                               ; preds = %1
  br label %11

11:                                               ; preds = %23, %10
  %12 = getelementptr inbounds %"class.sc_core::sc_prim_channel_registry", ptr %4, i32 0, i32 1
  %13 = load i32, ptr %12, align 8, !tbaa !9
  %14 = call noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56) %4)
  %15 = icmp slt i32 %13, %14
  br i1 %15, label %16, label %27

16:                                               ; preds = %11
  %17 = getelementptr inbounds %"class.sc_core::sc_prim_channel_registry", ptr %4, i32 0, i32 2
  %18 = getelementptr inbounds %"class.sc_core::sc_prim_channel_registry", ptr %4, i32 0, i32 1
  %19 = load i32, ptr %18, align 8, !tbaa !9
  %20 = sext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_prim_channelESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %20) #2
  %22 = load ptr, ptr %21, align 8, !tbaa !5
  call void @_ZN7sc_core15sc_prim_channel17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(128) %22)
  br label %23

23:                                               ; preds = %16
  %24 = getelementptr inbounds %"class.sc_core::sc_prim_channel_registry", ptr %4, i32 0, i32 1
  %25 = load i32, ptr %24, align 8, !tbaa !9
  %26 = add nsw i32 %25, 1
  store i32 %26, ptr %24, align 8, !tbaa !9
  br label %11, !llvm.loop !16

27:                                               ; preds = %11
  store i1 false, ptr %2, align 1
  br label %28

28:                                               ; preds = %27, %9
  %29 = load i1, ptr %2, align 1
  ret i1 %29
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 8}
!10 = !{!"_ZTSN7sc_core24sc_prim_channel_registryE", !6, i64 0, !11, i64 8, !12, i64 16, !6, i64 40, !6, i64 48}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIPN7sc_core15sc_prim_channelESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_prim_channelESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_prim_channelESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_prim_channelESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core15sc_prim_channel17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(128)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_prim_channelESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN7sc_core24sc_prim_channel_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(56) %0) local_unnamed_addr #0 align 2 {
  %2 = tail call noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56) %0)
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %2, %4
  br i1 %5, label %.loopexit, label %.preheader

.preheader:                                       ; preds = %1
  %6 = tail call noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56) %0)
  %7 = icmp slt i32 %4, %6
  br i1 %7, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %.preheader
  %8 = getelementptr inbounds i8, ptr %0, i64 16
  br label %9

9:                                                ; preds = %.lr.ph, %9
  %10 = load i32, ptr %3, align 8, !tbaa !5
  %11 = sext i32 %10 to i64
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_prim_channelESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %11) #2
  %13 = load ptr, ptr %12, align 8, !tbaa !15
  tail call void @_ZN7sc_core15sc_prim_channel17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(128) %13)
  %14 = load i32, ptr %3, align 8, !tbaa !5
  %15 = add nsw i32 %14, 1
  store i32 %15, ptr %3, align 8, !tbaa !5
  %16 = tail call noundef i32 @_ZNK7sc_core24sc_prim_channel_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(56) %0)
  %17 = icmp slt i32 %15, %16
  br i1 %17, label %9, label %.loopexit, !llvm.loop !16

.loopexit:                                        ; preds = %9, %.preheader, %1
  ret i1 %5
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"_ZTSN7sc_core24sc_prim_channel_registryE", !7, i64 0, !10, i64 8, !11, i64 16, !7, i64 40, !7, i64 48}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"_ZTSSt6vectorIPN7sc_core15sc_prim_channelESaIS2_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_prim_channelESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_prim_channelESaIS2_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_prim_channelESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!15 = !{!7, !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass