; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_simcontext)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core12SC_ZERO_TIMEE = external global %"class.sc_core::sc_time", align 8
@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [1 x i8], align 1
@_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates = external hidden global i8, align 1
@_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates = external hidden global i64, align 8
@_ZN7sc_core34SC_ID_SIMULATION_START_AFTER_STOP_E = external constant [0 x i8], align 1
@_ZN7sc_core35SC_ID_SIMULATION_START_AFTER_ERROR_E = external constant [0 x i8], align 1
@_ZN7sc_core27SC_ID_NO_SC_START_ACTIVITY_E = external constant [0 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) #1 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext8simulateERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef nonnull align 8 dereferenceable(8)) #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #4

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core24sc_prim_channel_registry15pending_updatesEv(ptr noundef nonnull align 8 dereferenceable(56)) #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyE(ptr noundef nonnull align 8 dereferenceable(8) %0, i32 noundef %1) #3 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca %"class.sc_core::sc_time", align 8
  %7 = alloca %"class.sc_core::sc_time", align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca %"class.sc_core::sc_time", align 8
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #5
  call void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %6)
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  call void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %7)
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %14 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  store ptr %14, ptr %5, align 8, !tbaa !5
  %15 = call noundef i64 @_ZN7sc_core14sc_delta_countEv()
  store i64 %15, ptr %8, align 8, !tbaa !11
  %16 = load ptr, ptr %5, align 8, !tbaa !5
  %17 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %16, i32 0, i32 22
  %18 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull align 8 dereferenceable(8) %17)
  %19 = load i32, ptr %4, align 4, !tbaa !9
  %20 = icmp eq i32 %19, 1
  br i1 %20, label %21, label %26

21:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #5
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %22, i32 0, i32 22
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  call void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind writable sret(%"class.sc_core::sc_time") align 8 %10, ptr noundef nonnull align 8 dereferenceable(8) %23, ptr noundef nonnull align 8 dereferenceable(8) %24)
  %25 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 8 dereferenceable(8) %10)
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #5
  br label %26

26:                                               ; preds = %21, %2
  %27 = load atomic i8, ptr @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates acquire, align 8
  %28 = icmp eq i8 %27, 0
  br i1 %28, label %29, label %41, !prof !13

29:                                               ; preds = %26
  %30 = call i32 @__cxa_guard_acquire(ptr @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates) #5
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %41

32:                                               ; preds = %29
  %33 = load i64, ptr %8, align 8, !tbaa !11
  %34 = icmp eq i64 %33, 0
  br i1 %34, label %35, label %38

35:                                               ; preds = %32
  %36 = invoke noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
          to label %37 unwind label %50

37:                                               ; preds = %35
  br label %38

38:                                               ; preds = %37, %32
  %39 = phi i1 [ false, %32 ], [ %36, %37 ]
  %40 = zext i1 %39 to i8
  store i8 %40, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !14
  call void @__cxa_guard_release(ptr @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates) #5
  br label %41

41:                                               ; preds = %38, %29, %26
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %42)
  store i32 %43, ptr %9, align 4, !tbaa !16
  %44 = load i32, ptr %9, align 4, !tbaa !16
  %45 = icmp ne i32 %44, 0
  br i1 %45, label %46, label %59

46:                                               ; preds = %41
  %47 = load i32, ptr %9, align 4, !tbaa !16
  %48 = icmp eq i32 %47, 2
  br i1 %48, label %49, label %54

49:                                               ; preds = %46
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core34SC_ID_SIMULATION_START_AFTER_STOP_E, ptr noundef @.str.8, ptr noundef @.str.7, i32 noundef 1686)
  br label %54

50:                                               ; preds = %35
  %51 = landingpad { ptr, i32 }
          cleanup
  %52 = extractvalue { ptr, i32 } %51, 0
  store ptr %52, ptr %11, align 8
  %53 = extractvalue { ptr, i32 } %51, 1
  store i32 %53, ptr %12, align 4
  call void @__cxa_guard_abort(ptr @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  br label %103

54:                                               ; preds = %49, %46
  %55 = load i32, ptr %9, align 4, !tbaa !16
  %56 = icmp eq i32 %55, 1
  br i1 %56, label %57, label %58

57:                                               ; preds = %54
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core35SC_ID_SIMULATION_START_AFTER_ERROR_E, ptr noundef @.str.8, ptr noundef @.str.7, i32 noundef 1688)
  br label %58

58:                                               ; preds = %57, %54
  store i32 1, ptr %13, align 4
  br label %100

59:                                               ; preds = %41
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %60, i32 0, i32 4
  %62 = load ptr, ptr %61, align 8, !tbaa !18
  %63 = call noundef zeroext i1 @_ZNK7sc_core24sc_prim_channel_registry15pending_updatesEv(ptr noundef nonnull align 8 dereferenceable(56) %62)
  br i1 %63, label %64, label %65

64:                                               ; preds = %59
  store i8 1, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !14
  br label %65

65:                                               ; preds = %64, %59
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = load ptr, ptr %3, align 8, !tbaa !5
  call void @_ZN7sc_core13sc_simcontext8simulateERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344) %66, ptr noundef nonnull align 8 dereferenceable(8) %67)
  %68 = load ptr, ptr %5, align 8, !tbaa !5
  %69 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %68)
  store i32 %69, ptr %9, align 4, !tbaa !16
  %70 = load i32, ptr %4, align 4, !tbaa !9
  %71 = icmp eq i32 %70, 1
  br i1 %71, label %72, label %84

72:                                               ; preds = %65
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %73, i32 0, i32 28
  %75 = load i8, ptr %74, align 1, !tbaa !41, !range !42, !noundef !43
  %76 = trunc i8 %75 to i1
  br i1 %76, label %84, label %77

77:                                               ; preds = %72
  %78 = load i32, ptr %9, align 4, !tbaa !16
  %79 = icmp eq i32 %78, 0
  br i1 %79, label %80, label %84

80:                                               ; preds = %77
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %81, i32 0, i32 22
  %83 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %82, ptr noundef nonnull align 8 dereferenceable(8) %7)
  br label %84

84:                                               ; preds = %80, %77, %72, %65
  %85 = load i8, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !14, !range !42, !noundef !43
  %86 = trunc i8 %85 to i1
  br i1 %86, label %99, label %87

87:                                               ; preds = %84
  %88 = load i64, ptr %8, align 8, !tbaa !11
  %89 = call noundef i64 @_ZN7sc_core14sc_delta_countEv()
  %90 = icmp eq i64 %88, %89
  br i1 %90, label %91, label %99

91:                                               ; preds = %87
  %92 = load ptr, ptr %5, align 8, !tbaa !5
  %93 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %92, i32 0, i32 22
  %94 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %93, ptr noundef nonnull align 8 dereferenceable(8) %6)
  br i1 %94, label %95, label %99

95:                                               ; preds = %91
  %96 = load i32, ptr %9, align 4, !tbaa !16
  %97 = icmp eq i32 %96, 0
  br i1 %97, label %98, label %99

98:                                               ; preds = %95
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef @_ZN7sc_core27SC_ID_NO_SC_START_ACTIVITY_E, ptr noundef @.str.8, ptr noundef @.str.7, i32 noundef 1720)
  br label %99

99:                                               ; preds = %98, %95, %91, %87, %84
  store i8 0, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !14
  store i32 0, ptr %13, align 4
  br label %100

100:                                              ; preds = %99, %58
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  %101 = load i32, ptr %13, align 4
  switch i32 %101, label %108 [
    i32 0, label %102
    i32 1, label %102
  ]

102:                                              ; preds = %100, %100
  ret void

103:                                              ; preds = %50
  %104 = load ptr, ptr %11, align 8
  %105 = load i32, ptr %12, align 4
  %106 = insertvalue { ptr, i32 } poison, ptr %104, 0
  %107 = insertvalue { ptr, i32 } %106, i32 %105, 1
  resume { ptr, i32 } %107

108:                                              ; preds = %100
  unreachable
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i64 @_ZN7sc_core14sc_delta_countEv() #4

; Function Attrs: nounwind
declare i32 @__cxa_guard_acquire(ptr) #5

; Function Attrs: nounwind
declare void @__cxa_guard_abort(ptr) #5

; Function Attrs: nounwind
declare void @__cxa_guard_release(ptr) #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN7sc_core20sc_starvation_policyE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = !{!"branch_weights", i32 1, i32 1048575}
!14 = !{!15, !15, i64 0}
!15 = !{!"bool", !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"int", !7, i64 0}
!18 = !{!19, !6, i64 32}
!19 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !20, i64 64, !6, i64 80, !15, i64 88, !17, i64 92, !22, i64 96, !26, i64 120, !30, i64 144, !26, i64 168, !6, i64 192, !34, i64 200, !15, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !38, i64 256, !38, i64 264, !6, i64 272, !12, i64 280, !12, i64 288, !15, i64 296, !15, i64 297, !15, i64 298, !15, i64 299, !39, i64 300, !6, i64 304, !15, i64 312, !15, i64 313, !40, i64 316, !15, i64 320, !6, i64 328, !6, i64 336}
!20 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !21, i64 8}
!21 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSN7sc_core7sc_timeE", !12, i64 0}
!39 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!40 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!41 = !{!19, !15, i64 297}
!42 = !{i8 0, i8 2}
!43 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }

@_ZN7sc_core12SC_ZERO_TIMEE = external global %"class.sc_core::sc_time", align 8
@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [1 x i8], align 1
@_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates = external hidden local_unnamed_addr global i8, align 1
@_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates = external hidden global i64, align 8
@_ZN7sc_core34SC_ID_SIMULATION_START_AFTER_STOP_E = external constant [0 x i8], align 1
@_ZN7sc_core35SC_ID_SIMULATION_START_AFTER_ERROR_E = external constant [0 x i8], align 1
@_ZN7sc_core27SC_ID_NO_SC_START_ACTIVITY_E = external constant [0 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #1 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext8simulateERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #4

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core24sc_prim_channel_registry15pending_updatesEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyE(ptr noundef nonnull align 8 dereferenceable(8) %0, i32 noundef %1) local_unnamed_addr #3 personality ptr @__gxx_personality_v0 {
  %3 = alloca %"class.sc_core::sc_time", align 8
  %4 = alloca %"class.sc_core::sc_time", align 8
  %5 = alloca %"class.sc_core::sc_time", align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #6
  call void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %3)
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #6
  call void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %4)
  %6 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %7 = call noundef i64 @_ZN7sc_core14sc_delta_countEv()
  %8 = getelementptr inbounds i8, ptr %6, i64 256
  %9 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %10 = icmp eq i32 %1, 1
  br i1 %10, label %11, label %13

11:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #6
  call void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind nonnull writable sret(%"class.sc_core::sc_time") align 8 %5, ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %0)
  %12 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %4, ptr noundef nonnull align 8 dereferenceable(8) %5)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #6
  br label %13

13:                                               ; preds = %11, %2
  %14 = load atomic i8, ptr @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates acquire, align 8
  %15 = icmp eq i8 %14, 0
  br i1 %15, label %16, label %25, !prof !5

16:                                               ; preds = %13
  %17 = call i32 @__cxa_guard_acquire(ptr nonnull @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates) #6
  %.not22 = icmp eq i32 %17, 0
  br i1 %.not22, label %25, label %18

18:                                               ; preds = %16
  %19 = icmp eq i64 %7, 0
  br i1 %19, label %20, label %23

20:                                               ; preds = %18
  %21 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %4, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  %22 = zext i1 %21 to i8
  br label %23

23:                                               ; preds = %20, %18
  %24 = phi i8 [ 0, %18 ], [ %22, %20 ]
  store i8 %24, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !6
  call void @__cxa_guard_release(ptr nonnull @_ZGVZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates) #6
  br label %25

25:                                               ; preds = %23, %16, %13
  %26 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %6)
  switch i32 %26, label %54 [
    i32 0, label %29
    i32 2, label %27
    i32 1, label %28
  ]

27:                                               ; preds = %25
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core34SC_ID_SIMULATION_START_AFTER_STOP_E, ptr noundef nonnull @.str.8, ptr noundef nonnull @.str.7, i32 noundef 1686)
  br label %54

28:                                               ; preds = %25
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core35SC_ID_SIMULATION_START_AFTER_ERROR_E, ptr noundef nonnull @.str.8, ptr noundef nonnull @.str.7, i32 noundef 1688)
  br label %54

29:                                               ; preds = %25
  %30 = getelementptr inbounds i8, ptr %6, i64 32
  %31 = load ptr, ptr %30, align 8, !tbaa !10
  %32 = call noundef zeroext i1 @_ZNK7sc_core24sc_prim_channel_registry15pending_updatesEv(ptr noundef nonnull align 8 dereferenceable(56) %31)
  br i1 %32, label %33, label %34

33:                                               ; preds = %29
  store i8 1, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !6
  br label %34

34:                                               ; preds = %33, %29
  call void @_ZN7sc_core13sc_simcontext8simulateERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344) %6, ptr noundef nonnull align 8 dereferenceable(8) %0)
  %35 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %6)
  br i1 %10, label %36, label %43

36:                                               ; preds = %34
  %37 = getelementptr inbounds i8, ptr %6, i64 297
  %38 = load i8, ptr %37, align 1, !tbaa !36, !range !37, !noundef !38
  %39 = trunc nuw i8 %38 to i1
  %40 = icmp ne i32 %35, 0
  %or.cond.not = or i1 %40, %39
  br i1 %or.cond.not, label %43, label %41

41:                                               ; preds = %36
  %42 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %4)
  br label %43

43:                                               ; preds = %41, %36, %34
  %44 = load i8, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !6, !range !37, !noundef !38
  %45 = trunc nuw i8 %44 to i1
  br i1 %45, label %53, label %46

46:                                               ; preds = %43
  %47 = call noundef i64 @_ZN7sc_core14sc_delta_countEv()
  %48 = icmp eq i64 %7, %47
  br i1 %48, label %49, label %53

49:                                               ; preds = %46
  %50 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %3)
  %51 = icmp eq i32 %35, 0
  %or.cond3 = and i1 %51, %50
  br i1 %or.cond3, label %52, label %53

52:                                               ; preds = %49
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef nonnull @_ZN7sc_core27SC_ID_NO_SC_START_ACTIVITY_E, ptr noundef nonnull @.str.8, ptr noundef nonnull @.str.7, i32 noundef 1720)
  br label %53

53:                                               ; preds = %52, %49, %46, %43
  store i8 0, ptr @_ZZN7sc_core8sc_startERKNS_7sc_timeENS_20sc_starvation_policyEE29init_delta_or_pending_updates, align 1, !tbaa !6
  br label %54

54:                                               ; preds = %27, %28, %25, %53
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #6
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i64 @_ZN7sc_core14sc_delta_countEv() local_unnamed_addr #4

; Function Attrs: nofree nounwind
declare i32 @__cxa_guard_acquire(ptr) local_unnamed_addr #5

; Function Attrs: nofree nounwind
declare void @__cxa_guard_release(ptr) local_unnamed_addr #5

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nofree nounwind }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!"branch_weights", i32 1, i32 1048575}
!6 = !{!7, !7, i64 0}
!7 = !{!"bool", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!11, !12, i64 32}
!11 = !{!"_ZTSN7sc_core13sc_simcontextE", !12, i64 0, !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !13, i64 64, !12, i64 80, !7, i64 88, !15, i64 92, !16, i64 96, !20, i64 120, !24, i64 144, !20, i64 168, !12, i64 192, !28, i64 200, !7, i64 224, !12, i64 232, !12, i64 240, !12, i64 248, !32, i64 256, !32, i64 264, !12, i64 272, !33, i64 280, !33, i64 288, !7, i64 296, !7, i64 297, !7, i64 298, !7, i64 299, !34, i64 300, !12, i64 304, !7, i64 312, !7, i64 313, !35, i64 316, !7, i64 320, !12, i64 328, !12, i64 336}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !12, i64 0, !14, i64 8}
!14 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!15 = !{!"int", !8, i64 0}
!16 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!24 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!28 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!32 = !{!"_ZTSN7sc_core7sc_timeE", !33, i64 0}
!33 = !{!"long long", !8, i64 0}
!34 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!36 = !{!11, !7, i64 297}
!37 = !{i8 0, i8 2}
!38 = !{}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass