; LLVM IR from hoodoer/ENNEoS :: enneosEncoder (genotype)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.CGenome = type <{ i32, [4 x i8], %"class.std::vector", %"class.std::vector.0", ptr, i32, [4 x i8], double, double, double, i32, i32, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl" }
%"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl" = type { %"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl" }
%"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl" = type { %"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SNeuronGeneSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7CGenomeC2EiSt6vectorI11SNeuronGeneSaIS1_EES0_I9SLinkGeneSaIS4_EEii(ptr noundef nonnull align 8 dereferenceable(108) %0, i32 noundef %1, ptr noundef %2, ptr noundef %3, i32 noundef %4, i32 noundef %5) unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store ptr %2, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store i32 %4, ptr %11, align 4, !tbaa !9
  store i32 %5, ptr %12, align 4, !tbaa !9
  %15 = load ptr, ptr %7, align 8
  %16 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 0
  %17 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %17, ptr %16, align 8, !tbaa !11
  %18 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 2
  call void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %18, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %19 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 3
  invoke void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %19, ptr noundef nonnull align 8 dereferenceable(24) %3)
          to label %20 unwind label %29

20:                                               ; preds = %6
  %21 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 4
  store ptr null, ptr %21, align 8, !tbaa !22
  %22 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 7
  store double 0.000000e+00, ptr %22, align 8, !tbaa !23
  %23 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 8
  store double 0.000000e+00, ptr %23, align 8, !tbaa !24
  %24 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 9
  store double 0.000000e+00, ptr %24, align 8, !tbaa !25
  %25 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 10
  %26 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %26, ptr %25, align 8, !tbaa !26
  %27 = getelementptr inbounds %class.CGenome, ptr %15, i32 0, i32 11
  %28 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %28, ptr %27, align 4, !tbaa !27
  ret void

29:                                               ; preds = %6
  %30 = landingpad { ptr, i32 }
          cleanup
  %31 = extractvalue { ptr, i32 } %30, 0
  store ptr %31, ptr %13, align 8
  %32 = extractvalue { ptr, i32 } %30, 1
  store i32 %32, ptr %14, align 4
  call void @_ZNSt6vectorI11SNeuronGeneSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #2
  br label %33

33:                                               ; preds = %29
  %34 = load ptr, ptr %13, align 8
  %35 = load i32, ptr %14, align 4
  %36 = insertvalue { ptr, i32 } poison, ptr %34, 0
  %37 = insertvalue { ptr, i32 } %36, i32 %35, 1
  resume { ptr, i32 } %37
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTS7CGenome", !10, i64 0, !13, i64 8, !17, i64 32, !6, i64 56, !10, i64 64, !21, i64 72, !21, i64 80, !21, i64 88, !10, i64 96, !10, i64 100, !10, i64 104}
!13 = !{!"_ZTSSt6vectorI11SNeuronGeneSaIS0_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseI11SNeuronGeneSaIS0_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorI9SLinkGeneSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseI9SLinkGeneSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"double", !7, i64 0}
!22 = !{!12, !6, i64 56}
!23 = !{!12, !21, i64 72}
!24 = !{!12, !21, i64 80}
!25 = !{!12, !21, i64 88}
!26 = !{!12, !10, i64 96}
!27 = !{!12, !10, i64 100}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SNeuronGeneSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7CGenomeC2EiSt6vectorI11SNeuronGeneSaIS1_EES0_I9SLinkGeneSaIS4_EEii(ptr noundef nonnull align 8 dereferenceable(108) %0, i32 noundef %1, ptr noundef nonnull %2, ptr noundef %3, i32 noundef %4, i32 noundef %5) unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  store i32 %1, ptr %0, align 8, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  tail call void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %7, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %8 = getelementptr inbounds i8, ptr %0, i64 32
  invoke void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %8, ptr noundef nonnull align 8 dereferenceable(24) %3)
          to label %9 unwind label %14

9:                                                ; preds = %6
  %10 = getelementptr inbounds i8, ptr %0, i64 56
  store ptr null, ptr %10, align 8, !tbaa !20
  %11 = getelementptr inbounds i8, ptr %0, i64 72
  %12 = getelementptr inbounds i8, ptr %0, i64 96
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %11, i8 0, i64 24, i1 false)
  store i32 %4, ptr %12, align 8, !tbaa !21
  %13 = getelementptr inbounds i8, ptr %0, i64 100
  store i32 %5, ptr %13, align 4, !tbaa !22
  ret void

14:                                               ; preds = %6
  %15 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZNSt6vectorI11SNeuronGeneSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #3
  resume { ptr, i32 } %15
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS7CGenome", !7, i64 0, !10, i64 8, !15, i64 32, !14, i64 56, !7, i64 64, !19, i64 72, !19, i64 80, !19, i64 88, !7, i64 96, !7, i64 100, !7, i64 104}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorI11SNeuronGeneSaIS0_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseI11SNeuronGeneSaIS0_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"_ZTSSt6vectorI9SLinkGeneSaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseI9SLinkGeneSaIS0_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!19 = !{!"double", !8, i64 0}
!20 = !{!6, !14, i64 56}
!21 = !{!6, !7, i64 96}
!22 = !{!6, !7, i64 100}


; Effective O3 passes: EarlyCSEPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass