; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_time.ll (ZN7sc_core7sc_timeC2EdNS_12sc_time_unitE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector.0", ptr, %"class.std::vector.10", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.sc_core::sc_time_params" = type <{ double, i8, i8, [6 x i8], i64, i8, [7 x i8] }>

@_ZN7sc_coreL11time_valuesE = external hidden global [6 x double], align 16

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core7sc_timeC2EdNS_12sc_time_unitE(ptr noundef nonnull align 8 dereferenceable(8) %0, double noundef %1, i32 noundef %2) unnamed_addr #0 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca double, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca double, align 8
  %9 = alloca double, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store double %1, ptr %5, align 8, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !11
  %10 = load ptr, ptr %4, align 8
  %11 = getelementptr inbounds %"class.sc_core::sc_time", ptr %10, i32 0, i32 0
  store i64 0, ptr %11, align 8, !tbaa !13
  %12 = load double, ptr %5, align 8, !tbaa !9
  %13 = fcmp une double %12, 0.000000e+00
  br i1 %13, label %14, label %34

14:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %15 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %16 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %15, i32 0, i32 21
  %17 = load ptr, ptr %16, align 8, !tbaa !16
  store ptr %17, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %18 = load i32, ptr %6, align 4, !tbaa !11
  %19 = zext i32 %18 to i64
  %20 = getelementptr inbounds [6 x double], ptr @_ZN7sc_coreL11time_valuesE, i64 0, i64 %19
  %21 = load double, ptr %20, align 8, !tbaa !9
  %22 = load ptr, ptr %7, align 8, !tbaa !5
  %23 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %22, i32 0, i32 0
  %24 = load double, ptr %23, align 8, !tbaa !40
  %25 = fdiv double %21, %24
  store double %25, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %26 = load double, ptr %5, align 8, !tbaa !9
  %27 = load double, ptr %8, align 8, !tbaa !9
  %28 = call double @llvm.fmuladd.f64(double %26, double %27, double 5.000000e-01)
  store volatile double %28, ptr %9, align 8, !tbaa !9
  %29 = load volatile double, ptr %9, align 8, !tbaa !9
  %30 = fptosi double %29 to i64
  %31 = getelementptr inbounds %"class.sc_core::sc_time", ptr %10, i32 0, i32 0
  store i64 %30, ptr %31, align 8, !tbaa !13
  %32 = load ptr, ptr %7, align 8, !tbaa !5
  %33 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %32, i32 0, i32 2
  store i8 1, ptr %33, align 1, !tbaa !42
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %34

34:                                               ; preds = %14, %3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTSN7sc_core12sc_time_unitE", !7, i64 0}
!13 = !{!14, !15, i64 0}
!14 = !{!"_ZTSN7sc_core7sc_timeE", !15, i64 0}
!15 = !{!"long long", !7, i64 0}
!16 = !{!17, !6, i64 248}
!17 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !18, i64 64, !6, i64 80, !20, i64 88, !21, i64 92, !22, i64 96, !26, i64 120, !30, i64 144, !26, i64 168, !6, i64 192, !34, i64 200, !20, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !14, i64 256, !14, i64 264, !6, i64 272, !15, i64 280, !15, i64 288, !20, i64 296, !20, i64 297, !20, i64 298, !20, i64 299, !38, i64 300, !6, i64 304, !20, i64 312, !20, i64 313, !39, i64 316, !20, i64 320, !6, i64 328, !6, i64 336}
!18 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !19, i64 8}
!19 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"int", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!39 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!40 = !{!41, !10, i64 0}
!41 = !{!"_ZTSN7sc_core14sc_time_paramsE", !10, i64 0, !20, i64 8, !20, i64 9, !15, i64 16, !20, i64 24}
!42 = !{!41, !20, i64 9}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_coreL11time_valuesE = external hidden local_unnamed_addr global [6 x double], align 16

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core7sc_timeC2EdNS_12sc_time_unitE(ptr nocapture noundef nonnull writeonly align 8 dereferenceable(8) %0, double noundef %1, i32 noundef %2) unnamed_addr #0 align 2 {
  %4 = alloca double, align 8
  store i64 0, ptr %0, align 8, !tbaa !5
  %5 = fcmp une double %1, 0.000000e+00
  br i1 %5, label %6, label %18

6:                                                ; preds = %3
  %7 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %8 = getelementptr inbounds i8, ptr %7, i64 248
  %9 = load ptr, ptr %8, align 8, !tbaa !10
  %10 = zext i32 %2 to i64
  %11 = getelementptr inbounds [6 x double], ptr @_ZN7sc_coreL11time_valuesE, i64 0, i64 %10
  %12 = load double, ptr %11, align 8, !tbaa !35
  %13 = load double, ptr %9, align 8, !tbaa !37
  %14 = fdiv double %12, %13
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4)
  %15 = tail call double @llvm.fmuladd.f64(double %1, double %14, double 5.000000e-01)
  store volatile double %15, ptr %4, align 8, !tbaa !35
  %.0..0..0..0. = load volatile double, ptr %4, align 8, !tbaa !35
  %16 = fptosi double %.0..0..0..0. to i64
  store i64 %16, ptr %0, align 8, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %9, i64 9
  store i8 1, ptr %17, align 1, !tbaa !39
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4)
  br label %18

18:                                               ; preds = %6, %3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7sc_core7sc_timeE", !7, i64 0}
!7 = !{!"long long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!11, !12, i64 248}
!11 = !{!"_ZTSN7sc_core13sc_simcontextE", !12, i64 0, !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !13, i64 64, !12, i64 80, !15, i64 88, !16, i64 92, !17, i64 96, !21, i64 120, !25, i64 144, !21, i64 168, !12, i64 192, !29, i64 200, !15, i64 224, !12, i64 232, !12, i64 240, !12, i64 248, !6, i64 256, !6, i64 264, !12, i64 272, !7, i64 280, !7, i64 288, !15, i64 296, !15, i64 297, !15, i64 298, !15, i64 299, !33, i64 300, !12, i64 304, !15, i64 312, !15, i64 313, !34, i64 316, !15, i64 320, !12, i64 328, !12, i64 336}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !12, i64 0, !14, i64 8}
!14 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!15 = !{!"bool", !8, i64 0}
!16 = !{!"int", !8, i64 0}
!17 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!21 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!25 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!29 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!35 = !{!36, !36, i64 0}
!36 = !{!"double", !8, i64 0}
!37 = !{!38, !36, i64 0}
!38 = !{!"_ZTSN7sc_core14sc_time_paramsE", !36, i64 0, !15, i64 8, !15, i64 9, !7, i64 16, !15, i64 24}
!39 = !{!38, !15, i64 9}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,TailCallElimPass