; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_signal_ports)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_in.25" = type { %"class.sc_core::sc_port.26", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.26" = type { %"class.sc_core::sc_port_b.27" }
%"class.sc_core::sc_port_b.27" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.28" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.28" = type { %"struct.std::_Vector_base.29" }
%"struct.std::_Vector_base.29" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core15sc_trace_paramsD2Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZNK7sc_core5sc_inIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(184) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  %5 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %4, i32 0, i32 1
  %6 = load ptr, ptr %5, align 8, !tbaa !9
  %7 = icmp ne ptr %6, null
  br i1 %7, label %8, label %38

8:                                                ; preds = %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  %9 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %4, i32 0, i32 1
  %10 = load ptr, ptr %9, align 8, !tbaa !9
  %11 = call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #4
  %12 = sub i64 %11, 1
  %13 = trunc i64 %12 to i32
  store i32 %13, ptr %3, align 4, !tbaa !30
  br label %14

14:                                               ; preds = %28, %8
  %15 = load i32, ptr %3, align 4, !tbaa !30
  %16 = icmp sge i32 %15, 0
  br i1 %16, label %18, label %17

17:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  br label %31

18:                                               ; preds = %14
  %19 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %4, i32 0, i32 1
  %20 = load ptr, ptr %19, align 8, !tbaa !9
  %21 = load i32, ptr %3, align 4, !tbaa !30
  %22 = sext i32 %21 to i64
  %23 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %22) #4
  %24 = load ptr, ptr %23, align 8, !tbaa !5
  %25 = icmp eq ptr %24, null
  br i1 %25, label %27, label %26

26:                                               ; preds = %18
  call void @_ZN7sc_core15sc_trace_paramsD2Ev(ptr noundef nonnull align 8 dereferenceable(40) %24) #4
  call void @_ZdlPvm(ptr noundef %24, i64 noundef 40) #5
  br label %27

27:                                               ; preds = %26, %18
  br label %28

28:                                               ; preds = %27
  %29 = load i32, ptr %3, align 4, !tbaa !30
  %30 = add nsw i32 %29, -1
  store i32 %30, ptr %3, align 4, !tbaa !30
  br label %14, !llvm.loop !32

31:                                               ; preds = %17
  %32 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %4, i32 0, i32 1
  %33 = load ptr, ptr %32, align 8, !tbaa !9
  %34 = icmp eq ptr %33, null
  br i1 %34, label %36, label %35

35:                                               ; preds = %31
  call void @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %33) #4
  call void @_ZdlPvm(ptr noundef %33, i64 noundef 24) #5
  br label %36

36:                                               ; preds = %35, %31
  %37 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %4, i32 0, i32 1
  store ptr null, ptr %37, align 8, !tbaa !9
  br label %38

38:                                               ; preds = %36, %1
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 152}
!10 = !{!"_ZTSN7sc_core5sc_inIN5sc_dt8sc_logicEEE", !11, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!11 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !12, i64 0}
!12 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEEEE", !13, i64 0, !6, i64 120, !26, i64 128}
!13 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !6, i64 112}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !6, i64 96, !6, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!31, !31, i64 0}
!31 = !{!"int", !7, i64 0}
!32 = distinct !{!32, !33}
!33 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core15sc_trace_paramsD2Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZNK7sc_core5sc_inIN5sc_dt8sc_logicEE13remove_tracesEv(ptr nocapture noundef nonnull align 8 dereferenceable(184) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 152
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %20, label %4

4:                                                ; preds = %1
  %5 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #3
  %6 = trunc i64 %5 to i32
  %.06 = add i32 %6, -1
  %7 = icmp sgt i32 %.06, -1
  br i1 %7, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %4
  %8 = zext nneg i32 %.06 to i64
  br label %.lr.ph

._crit_edge:                                      ; preds = %16, %4
  %9 = load ptr, ptr %2, align 8, !tbaa !5
  %10 = icmp eq ptr %9, null
  br i1 %10, label %19, label %18

.lr.ph:                                           ; preds = %.lr.ph.preheader, %16
  %indvars.iv = phi i64 [ %8, %.lr.ph.preheader ], [ %indvars.iv.next, %16 ]
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %indvars.iv) #3
  %13 = load ptr, ptr %12, align 8, !tbaa !29
  %14 = icmp eq ptr %13, null
  br i1 %14, label %16, label %15

15:                                               ; preds = %.lr.ph
  tail call void @_ZN7sc_core15sc_trace_paramsD2Ev(ptr noundef nonnull align 8 dereferenceable(40) %13) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %13, i64 noundef 40) #4
  br label %16

16:                                               ; preds = %.lr.ph, %15
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %17 = icmp sgt i64 %indvars.iv, 0
  br i1 %17, label %.lr.ph, label %._crit_edge, !llvm.loop !30

18:                                               ; preds = %._crit_edge
  tail call void @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %9, i64 noundef 24) #4
  br label %19

19:                                               ; preds = %18, %._crit_edge
  store ptr null, ptr %2, align 8, !tbaa !5
  br label %20

20:                                               ; preds = %19, %1
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 152}
!6 = !{!"_ZTSN7sc_core5sc_inIN5sc_dt8sc_logicEEE", !7, i64 0, !11, i64 152, !11, i64 160, !11, i64 168, !11, i64 176}
!7 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !8, i64 0}
!8 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEEEE", !9, i64 0, !11, i64 120, !25, i64 128}
!9 = !{!"_ZTSN7sc_core12sc_port_baseE", !10, i64 0, !11, i64 112}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !12, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!24 = !{!"long", !12, i64 0}
!25 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!29 = !{!11, !11, i64 0}
!30 = distinct !{!30, !31}
!31 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass