; LLVM IR from beagleboard/librobotcontrol :: library/src (motor)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@channels = external hidden global i32, align 4
@dirA_chip = external hidden global [4 x i32], align 16
@dirA_pin = external hidden global [4 x i32], align 16
@dirB_chip = external hidden global [4 x i32], align 16
@dirB_pin = external hidden global [4 x i32], align 16
@pwmss = external hidden global [4 x i32], align 16
@pwmch = external hidden global [4 x i32], align 16
@stderr = external global ptr, align 8
@.str = external hidden unnamed_addr constant [62 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [62 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [53 x i8], align 1
@stby_state = external hidden global i32, align 4
@init_flag = external hidden global i32, align 4
@.str.3 = external hidden unnamed_addr constant [24 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [51 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @rc_motor_init_freq(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  %6 = call i32 @rc_model()
  %7 = icmp eq i32 %6, 8
  br i1 %7, label %8, label %9

8:                                                ; preds = %1
  store i32 2, ptr @channels, align 4, !tbaa !5
  br label %10

9:                                                ; preds = %1
  store i32 4, ptr @channels, align 4, !tbaa !5
  br label %10

10:                                               ; preds = %9, %8
  %11 = call i32 @rc_model()
  %12 = icmp eq i32 %11, 7
  br i1 %12, label %13, label %14

13:                                               ; preds = %10
  store i32 2, ptr @dirA_chip, align 16, !tbaa !5
  store i32 0, ptr @dirA_pin, align 16, !tbaa !5
  br label %15

14:                                               ; preds = %10
  store i32 1, ptr @dirA_chip, align 16, !tbaa !5
  store i32 28, ptr @dirA_pin, align 16, !tbaa !5
  br label %15

15:                                               ; preds = %14, %13
  store i32 0, ptr @dirB_chip, align 16, !tbaa !5
  store i32 31, ptr @dirB_pin, align 16, !tbaa !5
  store i32 1, ptr @pwmss, align 16, !tbaa !5
  store i32 65, ptr @pwmch, align 16, !tbaa !5
  %16 = call i32 @rc_model()
  %17 = icmp eq i32 %16, 8
  br i1 %17, label %18, label %19

18:                                               ; preds = %15
  store i32 0, ptr getelementptr inbounds ([4 x i32], ptr @dirA_chip, i64 0, i64 1), align 4, !tbaa !5
  store i32 26, ptr getelementptr inbounds ([4 x i32], ptr @dirA_pin, i64 0, i64 1), align 4, !tbaa !5
  br label %20

19:                                               ; preds = %15
  store i32 1, ptr getelementptr inbounds ([4 x i32], ptr @dirA_chip, i64 0, i64 1), align 4, !tbaa !5
  store i32 16, ptr getelementptr inbounds ([4 x i32], ptr @dirA_pin, i64 0, i64 1), align 4, !tbaa !5
  br label %20

20:                                               ; preds = %19, %18
  %21 = call i32 @rc_model()
  %22 = icmp eq i32 %21, 7
  br i1 %22, label %23, label %24

23:                                               ; preds = %20
  store i32 0, ptr getelementptr inbounds ([4 x i32], ptr @dirB_chip, i64 0, i64 1), align 4, !tbaa !5
  store i32 10, ptr getelementptr inbounds ([4 x i32], ptr @dirB_pin, i64 0, i64 1), align 4, !tbaa !5
  br label %30

24:                                               ; preds = %20
  %25 = call i32 @rc_model()
  %26 = icmp eq i32 %25, 8
  br i1 %26, label %27, label %28

27:                                               ; preds = %24
  store i32 1, ptr getelementptr inbounds ([4 x i32], ptr @dirB_chip, i64 0, i64 1), align 4, !tbaa !5
  store i32 27, ptr getelementptr inbounds ([4 x i32], ptr @dirB_pin, i64 0, i64 1), align 4, !tbaa !5
  br label %29

28:                                               ; preds = %24
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @dirB_chip, i64 0, i64 1), align 4, !tbaa !5
  store i32 17, ptr getelementptr inbounds ([4 x i32], ptr @dirB_pin, i64 0, i64 1), align 4, !tbaa !5
  br label %29

29:                                               ; preds = %28, %27
  br label %30

30:                                               ; preds = %29, %23
  %31 = call i32 @rc_model()
  %32 = icmp eq i32 %31, 8
  br i1 %32, label %33, label %34

33:                                               ; preds = %30
  store i32 0, ptr getelementptr inbounds ([4 x i32], ptr @pwmss, i64 0, i64 1), align 4, !tbaa !5
  store i32 65, ptr getelementptr inbounds ([4 x i32], ptr @pwmch, i64 0, i64 1), align 4, !tbaa !5
  br label %35

34:                                               ; preds = %30
  store i32 1, ptr getelementptr inbounds ([4 x i32], ptr @pwmss, i64 0, i64 1), align 4, !tbaa !5
  store i32 66, ptr getelementptr inbounds ([4 x i32], ptr @pwmch, i64 0, i64 1), align 4, !tbaa !5
  br label %35

35:                                               ; preds = %34, %33
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @dirA_chip, i64 0, i64 2), align 8, !tbaa !5
  store i32 9, ptr getelementptr inbounds ([4 x i32], ptr @dirA_pin, i64 0, i64 2), align 8, !tbaa !5
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @dirB_chip, i64 0, i64 2), align 8, !tbaa !5
  store i32 8, ptr getelementptr inbounds ([4 x i32], ptr @dirB_pin, i64 0, i64 2), align 8, !tbaa !5
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @pwmss, i64 0, i64 2), align 8, !tbaa !5
  store i32 65, ptr getelementptr inbounds ([4 x i32], ptr @pwmch, i64 0, i64 2), align 8, !tbaa !5
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @dirA_chip, i64 0, i64 3), align 4, !tbaa !5
  store i32 6, ptr getelementptr inbounds ([4 x i32], ptr @dirA_pin, i64 0, i64 3), align 4, !tbaa !5
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @dirB_chip, i64 0, i64 3), align 4, !tbaa !5
  store i32 7, ptr getelementptr inbounds ([4 x i32], ptr @dirB_pin, i64 0, i64 3), align 4, !tbaa !5
  store i32 2, ptr getelementptr inbounds ([4 x i32], ptr @pwmss, i64 0, i64 3), align 4, !tbaa !5
  store i32 66, ptr getelementptr inbounds ([4 x i32], ptr @pwmch, i64 0, i64 3), align 4, !tbaa !5
  %36 = load i32, ptr %3, align 4, !tbaa !5
  %37 = call i32 @rc_pwm_init(i32 noundef 0, i32 noundef %36)
  %38 = icmp ne i32 %37, 0
  %39 = xor i1 %38, true
  %40 = xor i1 %39, true
  %41 = zext i1 %40 to i32
  %42 = sext i32 %41 to i64
  %43 = call i64 @llvm.expect.i64(i64 %42, i64 0)
  %44 = icmp ne i64 %43, 0
  br i1 %44, label %45, label %48

45:                                               ; preds = %35
  %46 = load ptr, ptr @stderr, align 8, !tbaa !9
  %47 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %46, ptr noundef @.str) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

48:                                               ; preds = %35
  %49 = load i32, ptr %3, align 4, !tbaa !5
  %50 = call i32 @rc_pwm_init(i32 noundef 1, i32 noundef %49)
  %51 = icmp ne i32 %50, 0
  %52 = xor i1 %51, true
  %53 = xor i1 %52, true
  %54 = zext i1 %53 to i32
  %55 = sext i32 %54 to i64
  %56 = call i64 @llvm.expect.i64(i64 %55, i64 0)
  %57 = icmp ne i64 %56, 0
  br i1 %57, label %58, label %61

58:                                               ; preds = %48
  %59 = load ptr, ptr @stderr, align 8, !tbaa !9
  %60 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %59, ptr noundef @.str) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

61:                                               ; preds = %48
  %62 = load i32, ptr %3, align 4, !tbaa !5
  %63 = call i32 @rc_pwm_init(i32 noundef 2, i32 noundef %62)
  %64 = icmp ne i32 %63, 0
  %65 = xor i1 %64, true
  %66 = xor i1 %65, true
  %67 = zext i1 %66 to i32
  %68 = sext i32 %67 to i64
  %69 = call i64 @llvm.expect.i64(i64 %68, i64 0)
  %70 = icmp ne i64 %69, 0
  br i1 %70, label %71, label %74

71:                                               ; preds = %61
  %72 = load ptr, ptr @stderr, align 8, !tbaa !9
  %73 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %72, ptr noundef @.str.1) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

74:                                               ; preds = %61
  %75 = call i32 @rc_gpio_init(i32 noundef 0, i32 noundef 20, i32 noundef 2)
  %76 = icmp ne i32 %75, 0
  %77 = xor i1 %76, true
  %78 = xor i1 %77, true
  %79 = zext i1 %78 to i32
  %80 = sext i32 %79 to i64
  %81 = call i64 @llvm.expect.i64(i64 %80, i64 0)
  %82 = icmp ne i64 %81, 0
  br i1 %82, label %83, label %86

83:                                               ; preds = %74
  %84 = load ptr, ptr @stderr, align 8, !tbaa !9
  %85 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %84, ptr noundef @.str.2, i32 noundef 0, i32 noundef 20) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

86:                                               ; preds = %74
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %87

87:                                               ; preds = %148, %86
  %88 = load i32, ptr %4, align 4, !tbaa !5
  %89 = load i32, ptr @channels, align 4, !tbaa !5
  %90 = icmp slt i32 %88, %89
  br i1 %90, label %91, label %151

91:                                               ; preds = %87
  %92 = load i32, ptr %4, align 4, !tbaa !5
  %93 = sext i32 %92 to i64
  %94 = getelementptr inbounds [4 x i32], ptr @dirA_chip, i64 0, i64 %93
  %95 = load i32, ptr %94, align 4, !tbaa !5
  %96 = load i32, ptr %4, align 4, !tbaa !5
  %97 = sext i32 %96 to i64
  %98 = getelementptr inbounds [4 x i32], ptr @dirA_pin, i64 0, i64 %97
  %99 = load i32, ptr %98, align 4, !tbaa !5
  %100 = call i32 @rc_gpio_init(i32 noundef %95, i32 noundef %99, i32 noundef 2)
  %101 = icmp ne i32 %100, 0
  %102 = xor i1 %101, true
  %103 = xor i1 %102, true
  %104 = zext i1 %103 to i32
  %105 = sext i32 %104 to i64
  %106 = call i64 @llvm.expect.i64(i64 %105, i64 0)
  %107 = icmp ne i64 %106, 0
  br i1 %107, label %108, label %119

108:                                              ; preds = %91
  %109 = load ptr, ptr @stderr, align 8, !tbaa !9
  %110 = load i32, ptr %4, align 4, !tbaa !5
  %111 = sext i32 %110 to i64
  %112 = getelementptr inbounds [4 x i32], ptr @dirA_chip, i64 0, i64 %111
  %113 = load i32, ptr %112, align 4, !tbaa !5
  %114 = load i32, ptr %4, align 4, !tbaa !5
  %115 = sext i32 %114 to i64
  %116 = getelementptr inbounds [4 x i32], ptr @dirA_pin, i64 0, i64 %115
  %117 = load i32, ptr %116, align 4, !tbaa !5
  %118 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %109, ptr noundef @.str.2, i32 noundef %113, i32 noundef %117) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

119:                                              ; preds = %91
  %120 = load i32, ptr %4, align 4, !tbaa !5
  %121 = sext i32 %120 to i64
  %122 = getelementptr inbounds [4 x i32], ptr @dirB_chip, i64 0, i64 %121
  %123 = load i32, ptr %122, align 4, !tbaa !5
  %124 = load i32, ptr %4, align 4, !tbaa !5
  %125 = sext i32 %124 to i64
  %126 = getelementptr inbounds [4 x i32], ptr @dirB_pin, i64 0, i64 %125
  %127 = load i32, ptr %126, align 4, !tbaa !5
  %128 = call i32 @rc_gpio_init(i32 noundef %123, i32 noundef %127, i32 noundef 2)
  %129 = icmp ne i32 %128, 0
  %130 = xor i1 %129, true
  %131 = xor i1 %130, true
  %132 = zext i1 %131 to i32
  %133 = sext i32 %132 to i64
  %134 = call i64 @llvm.expect.i64(i64 %133, i64 0)
  %135 = icmp ne i64 %134, 0
  br i1 %135, label %136, label %147

136:                                              ; preds = %119
  %137 = load ptr, ptr @stderr, align 8, !tbaa !9
  %138 = load i32, ptr %4, align 4, !tbaa !5
  %139 = sext i32 %138 to i64
  %140 = getelementptr inbounds [4 x i32], ptr @dirB_chip, i64 0, i64 %139
  %141 = load i32, ptr %140, align 4, !tbaa !5
  %142 = load i32, ptr %4, align 4, !tbaa !5
  %143 = sext i32 %142 to i64
  %144 = getelementptr inbounds [4 x i32], ptr @dirB_pin, i64 0, i64 %143
  %145 = load i32, ptr %144, align 4, !tbaa !5
  %146 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %137, ptr noundef @.str.2, i32 noundef %141, i32 noundef %145) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

147:                                              ; preds = %119
  br label %148

148:                                              ; preds = %147
  %149 = load i32, ptr %4, align 4, !tbaa !5
  %150 = add nsw i32 %149, 1
  store i32 %150, ptr %4, align 4, !tbaa !5
  br label %87, !llvm.loop !11

151:                                              ; preds = %87
  store i32 0, ptr @stby_state, align 4, !tbaa !5
  store i32 1, ptr @init_flag, align 4, !tbaa !5
  %152 = call i32 @rc_motor_free_spin(i32 noundef 0)
  %153 = icmp ne i32 %152, 0
  %154 = xor i1 %153, true
  %155 = xor i1 %154, true
  %156 = zext i1 %155 to i32
  %157 = sext i32 %156 to i64
  %158 = call i64 @llvm.expect.i64(i64 %157, i64 0)
  %159 = icmp ne i64 %158, 0
  br i1 %159, label %160, label %163

160:                                              ; preds = %151
  %161 = load ptr, ptr @stderr, align 8, !tbaa !9
  %162 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %161, ptr noundef @.str.3) #5
  store i32 0, ptr @init_flag, align 4, !tbaa !5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

163:                                              ; preds = %151
  %164 = call i32 @rc_gpio_set_value(i32 noundef 0, i32 noundef 20, i32 noundef 1)
  %165 = icmp ne i32 %164, 0
  %166 = xor i1 %165, true
  %167 = xor i1 %166, true
  %168 = zext i1 %167 to i32
  %169 = sext i32 %168 to i64
  %170 = call i64 @llvm.expect.i64(i64 %169, i64 0)
  %171 = icmp ne i64 %170, 0
  br i1 %171, label %172, label %175

172:                                              ; preds = %163
  %173 = load ptr, ptr @stderr, align 8, !tbaa !9
  %174 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %173, ptr noundef @.str.4, i32 noundef 0, i32 noundef 20) #5
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

175:                                              ; preds = %163
  store i32 0, ptr @stby_state, align 4, !tbaa !5
  store i32 1, ptr @init_flag, align 4, !tbaa !5
  store i32 0, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %176

176:                                              ; preds = %175, %172, %160, %136, %108, %83, %71, %58, %45
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  %177 = load i32, ptr %2, align 4
  ret i32 %177
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @rc_model() #2

declare i32 @rc_pwm_init(i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare i64 @llvm.expect.i64(i64, i64) #3

; Function Attrs: nounwind
declare i32 @fprintf(ptr noundef, ptr noundef, ...) #4

declare i32 @rc_gpio_init(i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @rc_motor_free_spin(i32 noundef) #0

declare i32 @rc_gpio_set_value(i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(none) }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@channels = external hidden local_unnamed_addr global i32, align 4
@dirA_chip = external hidden local_unnamed_addr global [4 x i32], align 16
@dirA_pin = external hidden local_unnamed_addr global [4 x i32], align 16
@dirB_chip = external hidden local_unnamed_addr global [4 x i32], align 16
@dirB_pin = external hidden local_unnamed_addr global [4 x i32], align 16
@pwmss = external hidden local_unnamed_addr global [4 x i32], align 16
@pwmch = external hidden local_unnamed_addr global [4 x i32], align 16
@stderr = external local_unnamed_addr global ptr, align 8
@.str = external hidden unnamed_addr constant [62 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [62 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [53 x i8], align 1
@stby_state = external hidden local_unnamed_addr global i32, align 4
@init_flag = external hidden local_unnamed_addr global i32, align 4
@.str.3 = external hidden unnamed_addr constant [24 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [51 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 1) i32 @rc_motor_init_freq(i32 noundef %0) local_unnamed_addr #0 {
  %2 = tail call i32 @rc_model() #3
  %3 = icmp eq i32 %2, 8
  %. = select i1 %3, i32 2, i32 4
  store i32 %., ptr @channels, align 4, !tbaa !5
  %4 = tail call i32 @rc_model() #3
  %5 = icmp eq i32 %4, 7
  %storemerge16 = select i1 %5, i32 2, i32 1
  %storemerge15 = select i1 %5, i32 0, i32 28
  store i32 %storemerge16, ptr @dirA_chip, align 16, !tbaa !5
  store i32 %storemerge15, ptr @dirA_pin, align 16, !tbaa !5
  store i32 0, ptr @dirB_chip, align 16, !tbaa !5
  store i32 31, ptr @dirB_pin, align 16, !tbaa !5
  store i32 1, ptr @pwmss, align 16, !tbaa !5
  store i32 65, ptr @pwmch, align 16, !tbaa !5
  %6 = tail call i32 @rc_model() #3
  %7 = icmp ne i32 %6, 8
  %storemerge18 = zext i1 %7 to i32
  %storemerge17 = select i1 %7, i32 16, i32 26
  store i32 %storemerge18, ptr getelementptr inbounds (i8, ptr @dirA_chip, i64 4), align 4, !tbaa !5
  store i32 %storemerge17, ptr getelementptr inbounds (i8, ptr @dirA_pin, i64 4), align 4, !tbaa !5
  %8 = tail call i32 @rc_model() #3
  %9 = icmp eq i32 %8, 7
  br i1 %9, label %13, label %10

10:                                               ; preds = %1
  %11 = tail call i32 @rc_model() #3
  %12 = icmp eq i32 %11, 8
  %.55 = select i1 %12, i32 1, i32 2
  %.56 = select i1 %12, i32 27, i32 17
  br label %13

13:                                               ; preds = %10, %1
  %.sink54 = phi i32 [ 0, %1 ], [ %.55, %10 ]
  %.sink = phi i32 [ 10, %1 ], [ %.56, %10 ]
  store i32 %.sink54, ptr getelementptr inbounds (i8, ptr @dirB_chip, i64 4), align 4, !tbaa !5
  store i32 %.sink, ptr getelementptr inbounds (i8, ptr @dirB_pin, i64 4), align 4, !tbaa !5
  %14 = tail call i32 @rc_model() #3
  %15 = icmp ne i32 %14, 8
  %.28 = zext i1 %15 to i32
  %.29 = select i1 %15, i32 66, i32 65
  store i32 %.28, ptr getelementptr inbounds (i8, ptr @pwmss, i64 4), align 4, !tbaa !5
  store i32 %.29, ptr getelementptr inbounds (i8, ptr @pwmch, i64 4), align 4, !tbaa !5
  store i32 2, ptr getelementptr inbounds (i8, ptr @dirA_chip, i64 8), align 8, !tbaa !5
  store i32 9, ptr getelementptr inbounds (i8, ptr @dirA_pin, i64 8), align 8, !tbaa !5
  store i32 2, ptr getelementptr inbounds (i8, ptr @dirB_chip, i64 8), align 8, !tbaa !5
  store i32 8, ptr getelementptr inbounds (i8, ptr @dirB_pin, i64 8), align 8, !tbaa !5
  store i32 2, ptr getelementptr inbounds (i8, ptr @pwmss, i64 8), align 8, !tbaa !5
  store i32 65, ptr getelementptr inbounds (i8, ptr @pwmch, i64 8), align 8, !tbaa !5
  store i32 2, ptr getelementptr inbounds (i8, ptr @dirA_chip, i64 12), align 4, !tbaa !5
  store i32 6, ptr getelementptr inbounds (i8, ptr @dirA_pin, i64 12), align 4, !tbaa !5
  store i32 2, ptr getelementptr inbounds (i8, ptr @dirB_chip, i64 12), align 4, !tbaa !5
  store i32 7, ptr getelementptr inbounds (i8, ptr @dirB_pin, i64 12), align 4, !tbaa !5
  store i32 2, ptr getelementptr inbounds (i8, ptr @pwmss, i64 12), align 4, !tbaa !5
  store i32 66, ptr getelementptr inbounds (i8, ptr @pwmch, i64 12), align 4, !tbaa !5
  %16 = tail call i32 @rc_pwm_init(i32 noundef 0, i32 noundef %0) #3
  %.not = icmp eq i32 %16, 0
  br i1 %.not, label %20, label %17, !prof !9

17:                                               ; preds = %13
  %18 = load ptr, ptr @stderr, align 8, !tbaa !10
  %19 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %18, ptr noundef nonnull @.str) #4
  br label %76

20:                                               ; preds = %13
  %21 = tail call i32 @rc_pwm_init(i32 noundef 1, i32 noundef %0) #3
  %.not21 = icmp eq i32 %21, 0
  br i1 %.not21, label %25, label %22, !prof !9

22:                                               ; preds = %20
  %23 = load ptr, ptr @stderr, align 8, !tbaa !10
  %24 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %23, ptr noundef nonnull @.str) #4
  br label %76

25:                                               ; preds = %20
  %26 = tail call i32 @rc_pwm_init(i32 noundef 2, i32 noundef %0) #3
  %.not22 = icmp eq i32 %26, 0
  br i1 %.not22, label %30, label %27, !prof !9

27:                                               ; preds = %25
  %28 = load ptr, ptr @stderr, align 8, !tbaa !10
  %29 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %28, ptr noundef nonnull @.str.1) #4
  br label %76

30:                                               ; preds = %25
  %31 = tail call i32 @rc_gpio_init(i32 noundef 0, i32 noundef 20, i32 noundef 2) #3
  %.not23 = icmp eq i32 %31, 0
  br i1 %.not23, label %.preheader, label %34, !prof !9

.preheader:                                       ; preds = %30
  %32 = load i32, ptr @channels, align 4, !tbaa !5
  %33 = icmp sgt i32 %32, 0
  br i1 %33, label %.lr.ph, label %._crit_edge

34:                                               ; preds = %30
  %35 = load ptr, ptr @stderr, align 8, !tbaa !10
  %36 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %35, ptr noundef nonnull @.str.2, i32 noundef 0, i32 noundef 20) #4
  br label %76

37:                                               ; preds = %53
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %38 = load i32, ptr @channels, align 4, !tbaa !5
  %39 = sext i32 %38 to i64
  %40 = icmp slt i64 %indvars.iv.next, %39
  br i1 %40, label %.lr.ph, label %._crit_edge, !llvm.loop !12

.lr.ph:                                           ; preds = %.preheader, %37
  %indvars.iv = phi i64 [ %indvars.iv.next, %37 ], [ 0, %.preheader ]
  %41 = getelementptr inbounds [4 x i32], ptr @dirA_chip, i64 0, i64 %indvars.iv
  %42 = load i32, ptr %41, align 4, !tbaa !5
  %43 = getelementptr inbounds [4 x i32], ptr @dirA_pin, i64 0, i64 %indvars.iv
  %44 = load i32, ptr %43, align 4, !tbaa !5
  %45 = tail call i32 @rc_gpio_init(i32 noundef %42, i32 noundef %44, i32 noundef 2) #3
  %.not26 = icmp eq i32 %45, 0
  br i1 %.not26, label %53, label %46, !prof !9

46:                                               ; preds = %.lr.ph
  %47 = getelementptr inbounds [4 x i32], ptr @dirA_chip, i64 0, i64 %indvars.iv
  %48 = getelementptr inbounds [4 x i32], ptr @dirA_pin, i64 0, i64 %indvars.iv
  %49 = load ptr, ptr @stderr, align 8, !tbaa !10
  %50 = load i32, ptr %47, align 4, !tbaa !5
  %51 = load i32, ptr %48, align 4, !tbaa !5
  %52 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %49, ptr noundef nonnull @.str.2, i32 noundef %50, i32 noundef %51) #4
  br label %76

53:                                               ; preds = %.lr.ph
  %54 = getelementptr inbounds [4 x i32], ptr @dirB_chip, i64 0, i64 %indvars.iv
  %55 = load i32, ptr %54, align 4, !tbaa !5
  %56 = getelementptr inbounds [4 x i32], ptr @dirB_pin, i64 0, i64 %indvars.iv
  %57 = load i32, ptr %56, align 4, !tbaa !5
  %58 = tail call i32 @rc_gpio_init(i32 noundef %55, i32 noundef %57, i32 noundef 2) #3
  %.not27 = icmp eq i32 %58, 0
  br i1 %.not27, label %37, label %59, !prof !9

59:                                               ; preds = %53
  %60 = getelementptr inbounds [4 x i32], ptr @dirB_chip, i64 0, i64 %indvars.iv
  %61 = getelementptr inbounds [4 x i32], ptr @dirB_pin, i64 0, i64 %indvars.iv
  %62 = load ptr, ptr @stderr, align 8, !tbaa !10
  %63 = load i32, ptr %60, align 4, !tbaa !5
  %64 = load i32, ptr %61, align 4, !tbaa !5
  %65 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %62, ptr noundef nonnull @.str.2, i32 noundef %63, i32 noundef %64) #4
  br label %76

._crit_edge:                                      ; preds = %37, %.preheader
  store i32 0, ptr @stby_state, align 4, !tbaa !5
  store i32 1, ptr @init_flag, align 4, !tbaa !5
  %66 = tail call i32 @rc_motor_free_spin(i32 noundef 0)
  %.not24 = icmp eq i32 %66, 0
  br i1 %.not24, label %70, label %67, !prof !9

67:                                               ; preds = %._crit_edge
  %68 = load ptr, ptr @stderr, align 8, !tbaa !10
  %69 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %68, ptr noundef nonnull @.str.3) #4
  store i32 0, ptr @init_flag, align 4, !tbaa !5
  br label %76

70:                                               ; preds = %._crit_edge
  %71 = tail call i32 @rc_gpio_set_value(i32 noundef 0, i32 noundef 20, i32 noundef 1) #3
  %.not25 = icmp eq i32 %71, 0
  br i1 %.not25, label %75, label %72, !prof !9

72:                                               ; preds = %70
  %73 = load ptr, ptr @stderr, align 8, !tbaa !10
  %74 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef %73, ptr noundef nonnull @.str.4, i32 noundef 0, i32 noundef 20) #4
  br label %76

75:                                               ; preds = %70
  store i32 0, ptr @stby_state, align 4, !tbaa !5
  store i32 1, ptr @init_flag, align 4, !tbaa !5
  br label %76

76:                                               ; preds = %75, %72, %67, %59, %46, %34, %27, %22, %17
  %.014 = phi i32 [ -1, %17 ], [ -1, %22 ], [ -1, %27 ], [ -1, %34 ], [ -1, %46 ], [ -1, %59 ], [ -1, %67 ], [ -1, %72 ], [ 0, %75 ]
  ret i32 %.014
}

declare i32 @rc_model() local_unnamed_addr #1

declare i32 @rc_pwm_init(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nofree nounwind
declare noundef i32 @fprintf(ptr nocapture noundef, ptr nocapture noundef readonly, ...) local_unnamed_addr #2

declare i32 @rc_gpio_init(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @rc_motor_free_spin(i32 noundef) local_unnamed_addr #0

declare i32 @rc_gpio_set_value(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { cold nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"branch_weights", !"expected", i32 2000, i32 1}
!10 = !{!11, !11, i64 0}
!11 = !{!"any pointer", !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,LowerExpectIntrinsicPass,SROAPass,SimplifyCFGPass,TailCallElimPass