; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_time)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector.0", ptr, %"class.std::vector.10", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }
%"struct.sc_core::sc_time_params" = type <{ double, i8, i8, [6 x i8], i64, i8, [7 x i8] }>

@_ZN7sc_coreL11time_valuesE = external hidden global [6 x double], align 16
@_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E = external constant [0 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [83 x i8], align 1
@.str.9 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.10 = external hidden unnamed_addr constant [25 x i8], align 1
@.str.11 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.12 = external hidden unnamed_addr constant [18 x i8], align 1
@.str.13 = external hidden unnamed_addr constant [30 x i8], align 1
@_ZZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitEE22warn_default_time_unit = external hidden global i8, align 1
@.str.15 = external hidden unnamed_addr constant [46 x i8], align 1
@_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E = external constant [0 x i8], align 1
@.str.16 = external hidden unnamed_addr constant [35 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: nounwind
declare double @modf(double noundef, ptr noundef) #3

; Function Attrs: nounwind
declare double @log10(double noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) #4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitE(double noundef %0, i32 noundef %1) #5 {
  %3 = alloca double, align 8
  %4 = alloca i32, align 4
  %5 = alloca double, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca double, align 8
  store double %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %9 = load i8, ptr @_ZZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitEE22warn_default_time_unit, align 1, !tbaa !11, !range !13, !noundef !14
  %10 = trunc i8 %9 to i1
  br i1 %10, label %11, label %12

11:                                               ; preds = %2
  store i8 0, ptr @_ZZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitEE22warn_default_time_unit, align 1, !tbaa !11
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 0, ptr noundef @_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E, ptr noundef @.str.15, ptr noundef @.str.1, i32 noundef 354)
  br label %12

12:                                               ; preds = %11, %2
  %13 = load double, ptr %3, align 8, !tbaa !5
  %14 = fcmp olt double %13, 0.000000e+00
  br i1 %14, label %15, label %16

15:                                               ; preds = %12
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef @.str.9, ptr noundef @.str.1, i32 noundef 361)
  br label %16

16:                                               ; preds = %15, %12
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #6
  %17 = load double, ptr %3, align 8, !tbaa !5
  %18 = call double @log10(double noundef %17) #6
  %19 = call double @modf(double noundef %18, ptr noundef %5) #6
  %20 = fcmp une double %19, 0.000000e+00
  br i1 %20, label %21, label %22

21:                                               ; preds = %16
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef @.str.10, ptr noundef @.str.1, i32 noundef 368)
  br label %22

22:                                               ; preds = %21, %16
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #6
  %23 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  store ptr %23, ptr %6, align 8, !tbaa !15
  %24 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %25 = call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %24)
  br i1 %25, label %26, label %27

26:                                               ; preds = %22
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef @.str.11, ptr noundef @.str.1, i32 noundef 375)
  br label %27

27:                                               ; preds = %26, %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #6
  %28 = load ptr, ptr %6, align 8, !tbaa !15
  %29 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %28, i32 0, i32 21
  %30 = load ptr, ptr %29, align 8, !tbaa !17
  store ptr %30, ptr %7, align 8, !tbaa !15
  %31 = load ptr, ptr %7, align 8, !tbaa !15
  %32 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %31, i32 0, i32 2
  %33 = load i8, ptr %32, align 1, !tbaa !42, !range !13, !noundef !14
  %34 = trunc i8 %33 to i1
  br i1 %34, label %35, label %36

35:                                               ; preds = %27
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef @.str.13, ptr noundef @.str.1, i32 noundef 383)
  br label %36

36:                                               ; preds = %35, %27
  %37 = load ptr, ptr %7, align 8, !tbaa !15
  %38 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %37, i32 0, i32 5
  %39 = load i8, ptr %38, align 8, !tbaa !44, !range !13, !noundef !14
  %40 = trunc i8 %39 to i1
  br i1 %40, label %41, label %42

41:                                               ; preds = %36
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef @.str.12, ptr noundef @.str.1, i32 noundef 388)
  br label %42

42:                                               ; preds = %41, %36
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #6
  %43 = load double, ptr %3, align 8, !tbaa !5
  %44 = load i32, ptr %4, align 4, !tbaa !9
  %45 = zext i32 %44 to i64
  %46 = getelementptr inbounds [6 x double], ptr @_ZN7sc_coreL11time_valuesE, i64 0, i64 %45
  %47 = load double, ptr %46, align 8, !tbaa !5
  %48 = fmul double %43, %47
  %49 = load ptr, ptr %7, align 8, !tbaa !15
  %50 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %49, i32 0, i32 0
  %51 = load double, ptr %50, align 8, !tbaa !45
  %52 = fdiv double %48, %51
  store volatile double %52, ptr %8, align 8, !tbaa !5
  %53 = load volatile double, ptr %8, align 8, !tbaa !5
  %54 = fcmp olt double %53, 1.000000e+00
  br i1 %54, label %55, label %56

55:                                               ; preds = %42
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef @.str.16, ptr noundef @.str.1, i32 noundef 396)
  br label %56

56:                                               ; preds = %55, %42
  %57 = load volatile double, ptr %8, align 8, !tbaa !5
  %58 = fptosi double %57 to i64
  %59 = load ptr, ptr %7, align 8, !tbaa !15
  %60 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %59, i32 0, i32 4
  store i64 %58, ptr %60, align 8, !tbaa !46
  %61 = load ptr, ptr %7, align 8, !tbaa !15
  %62 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %61, i32 0, i32 5
  store i8 1, ptr %62, align 8, !tbaa !44
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #6
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN7sc_core12sc_time_unitE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!16, !16, i64 0}
!16 = !{!"any pointer", !7, i64 0}
!17 = !{!18, !16, i64 248}
!18 = !{!"_ZTSN7sc_core13sc_simcontextE", !16, i64 0, !16, i64 8, !16, i64 16, !16, i64 24, !16, i64 32, !16, i64 40, !16, i64 48, !16, i64 56, !19, i64 64, !16, i64 80, !12, i64 88, !21, i64 92, !22, i64 96, !26, i64 120, !30, i64 144, !26, i64 168, !16, i64 192, !34, i64 200, !12, i64 224, !16, i64 232, !16, i64 240, !16, i64 248, !38, i64 256, !38, i64 264, !16, i64 272, !39, i64 280, !39, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !40, i64 300, !16, i64 304, !12, i64 312, !12, i64 313, !41, i64 316, !12, i64 320, !16, i64 328, !16, i64 336}
!19 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !16, i64 0, !20, i64 8}
!20 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!21 = !{!"int", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!30 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!34 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!38 = !{!"_ZTSN7sc_core7sc_timeE", !39, i64 0}
!39 = !{!"long long", !7, i64 0}
!40 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!41 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!42 = !{!43, !12, i64 9}
!43 = !{!"_ZTSN7sc_core14sc_time_paramsE", !6, i64 0, !12, i64 8, !12, i64 9, !39, i64 16, !12, i64 24}
!44 = !{!43, !12, i64 24}
!45 = !{!43, !6, i64 0}
!46 = !{!43, !39, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_coreL11time_valuesE = external hidden local_unnamed_addr global [6 x double], align 16
@_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E = external constant [0 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [83 x i8], align 1
@.str.9 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.10 = external hidden unnamed_addr constant [25 x i8], align 1
@.str.11 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.12 = external hidden unnamed_addr constant [18 x i8], align 1
@.str.13 = external hidden unnamed_addr constant [30 x i8], align 1
@_ZZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitEE22warn_default_time_unit = external hidden local_unnamed_addr global i8, align 1
@.str.15 = external hidden unnamed_addr constant [46 x i8], align 1
@_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E = external constant [0 x i8], align 1
@.str.16 = external hidden unnamed_addr constant [35 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nofree nounwind willreturn memory(argmem: write)
declare double @modf(double noundef, ptr nocapture noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nofree nounwind willreturn memory(write)
declare double @log10(double noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) local_unnamed_addr #5

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitE(double noundef %0, i32 noundef %1) local_unnamed_addr #6 {
  %3 = alloca double, align 8
  %4 = alloca double, align 8
  %5 = load i8, ptr @_ZZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitEE22warn_default_time_unit, align 1, !tbaa !5, !range !9, !noundef !10
  %6 = trunc nuw i8 %5 to i1
  br i1 %6, label %7, label %8

7:                                                ; preds = %2
  store i8 0, ptr @_ZZN7sc_core24sc_set_default_time_unitEdNS_12sc_time_unitEE22warn_default_time_unit, align 1, !tbaa !5
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 0, ptr noundef nonnull @_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E, ptr noundef nonnull @.str.15, ptr noundef nonnull @.str.1, i32 noundef 354)
  br label %8

8:                                                ; preds = %7, %2
  %9 = fcmp olt double %0, 0.000000e+00
  br i1 %9, label %10, label %11

10:                                               ; preds = %8
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef nonnull @.str.9, ptr noundef nonnull @.str.1, i32 noundef 361)
  br label %11

11:                                               ; preds = %10, %8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #7
  %12 = tail call double @log10(double noundef %0) #7
  %13 = call double @modf(double noundef %12, ptr noundef nonnull %3) #7
  %14 = fcmp une double %13, 0.000000e+00
  br i1 %14, label %15, label %16

15:                                               ; preds = %11
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef nonnull @.str.10, ptr noundef nonnull @.str.1, i32 noundef 368)
  br label %16

16:                                               ; preds = %15, %11
  %17 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %18 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %19 = tail call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %18)
  br i1 %19, label %20, label %21

20:                                               ; preds = %16
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef nonnull @.str.11, ptr noundef nonnull @.str.1, i32 noundef 375)
  br label %21

21:                                               ; preds = %20, %16
  %22 = getelementptr inbounds i8, ptr %17, i64 248
  %23 = load ptr, ptr %22, align 8, !tbaa !11
  %24 = getelementptr inbounds i8, ptr %23, i64 9
  %25 = load i8, ptr %24, align 1, !tbaa !37, !range !9, !noundef !10
  %26 = trunc nuw i8 %25 to i1
  br i1 %26, label %27, label %28

27:                                               ; preds = %21
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef nonnull @.str.13, ptr noundef nonnull @.str.1, i32 noundef 383)
  br label %28

28:                                               ; preds = %27, %21
  %29 = getelementptr inbounds i8, ptr %23, i64 24
  %30 = load i8, ptr %29, align 8, !tbaa !40, !range !9, !noundef !10
  %31 = trunc nuw i8 %30 to i1
  br i1 %31, label %32, label %33

32:                                               ; preds = %28
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef nonnull @.str.12, ptr noundef nonnull @.str.1, i32 noundef 388)
  br label %33

33:                                               ; preds = %32, %28
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4)
  %34 = zext i32 %1 to i64
  %35 = getelementptr inbounds [6 x double], ptr @_ZN7sc_coreL11time_valuesE, i64 0, i64 %34
  %36 = load double, ptr %35, align 8, !tbaa !41
  %37 = fmul double %36, %0
  %38 = load double, ptr %23, align 8, !tbaa !42
  %39 = fdiv double %37, %38
  store volatile double %39, ptr %4, align 8, !tbaa !41
  %.0..0..0..0. = load volatile double, ptr %4, align 8, !tbaa !41
  %40 = fcmp olt double %.0..0..0..0., 1.000000e+00
  br i1 %40, label %41, label %42

41:                                               ; preds = %33
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core28SC_ID_SET_DEFAULT_TIME_UNIT_E, ptr noundef nonnull @.str.16, ptr noundef nonnull @.str.1, i32 noundef 396)
  br label %42

42:                                               ; preds = %41, %33
  %.0..0..0..0.1 = load volatile double, ptr %4, align 8, !tbaa !41
  %43 = fptosi double %.0..0..0..0.1 to i64
  %44 = getelementptr inbounds i8, ptr %23, i64 16
  store i64 %43, ptr %44, align 8, !tbaa !43
  store i8 1, ptr %29, align 8, !tbaa !40
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #7
  ret void
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nofree nounwind willreturn memory(argmem: write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nofree nounwind willreturn memory(write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = !{!12, !13, i64 248}
!12 = !{!"_ZTSN7sc_core13sc_simcontextE", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !13, i64 56, !14, i64 64, !13, i64 80, !6, i64 88, !16, i64 92, !17, i64 96, !21, i64 120, !25, i64 144, !21, i64 168, !13, i64 192, !29, i64 200, !6, i64 224, !13, i64 232, !13, i64 240, !13, i64 248, !33, i64 256, !33, i64 264, !13, i64 272, !34, i64 280, !34, i64 288, !6, i64 296, !6, i64 297, !6, i64 298, !6, i64 299, !35, i64 300, !13, i64 304, !6, i64 312, !6, i64 313, !36, i64 316, !6, i64 320, !13, i64 328, !13, i64 336}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !13, i64 0, !15, i64 8}
!15 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!16 = !{!"int", !7, i64 0}
!17 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!21 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!25 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!29 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!33 = !{!"_ZTSN7sc_core7sc_timeE", !34, i64 0}
!34 = !{!"long long", !7, i64 0}
!35 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!36 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!37 = !{!38, !6, i64 9}
!38 = !{!"_ZTSN7sc_core14sc_time_paramsE", !39, i64 0, !6, i64 8, !6, i64 9, !34, i64 16, !6, i64 24}
!39 = !{!"double", !7, i64 0}
!40 = !{!38, !6, i64 24}
!41 = !{!39, !39, i64 0}
!42 = !{!38, !39, i64 0}
!43 = !{!38, !34, i64 16}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass