; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/examples/aes/aes.ll (ZN11AES_Decrypt10MainThreadEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.AES_Decrypt = type { %struct.AES_Base, %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in.15", %"class.sc_core::sc_out", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_out.30", %"class.sc_core::sc_in", %"class.sc_core::sc_out", %"class.sc_dt::sc_uint.39", [11 x [4 x [4 x %"class.sc_dt::sc_uint"]]], [4 x [4 x %"class.sc_dt::sc_uint"]] }
%struct.AES_Base = type { %"class.sc_core::sc_module" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.2", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.2" = type { %"struct.std::_Vector_base.3" }
%"struct.std::_Vector_base.3" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in.15" = type { %"class.sc_core::sc_port.16", ptr, ptr }
%"class.sc_core::sc_port.16" = type { %"class.sc_core::sc_port_b.17" }
%"class.sc_core::sc_port_b.17" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.18" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.30" = type { %"class.sc_core::sc_inout.31" }
%"class.sc_core::sc_inout.31" = type { %"class.sc_core::sc_port.32", ptr, ptr, ptr }
%"class.sc_core::sc_port.32" = type { %"class.sc_core::sc_port_b.33" }
%"class.sc_core::sc_port_b.33" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.34" }
%"class.std::vector.34" = type { %"struct.std::_Vector_base.35" }
%"struct.std::_Vector_base.35" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_biguint<128>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.10" }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.23", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.23" = type { %"class.sc_core::sc_port_b.24" }
%"class.sc_core::sc_port_b.24" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.25" }
%"class.std::vector.25" = type { %"struct.std::_Vector_base.26" }
%"struct.std::_Vector_base.26" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_dt::sc_uint.39" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN8AES_Base8SchedKeyEPA4_N5sc_dt7sc_uintILi8EEEPA4_S3_(ptr noundef nonnull align 8 dereferenceable(232), ptr noundef, ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt5ResetEv(ptr noundef nonnull align 8 dereferenceable(6512)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt5InputEv(ptr noundef nonnull align 8 dereferenceable(6512)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt6OutputEv(ptr noundef nonnull align 8 dereferenceable(6512)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11AES_Decrypt10MainThreadEv(ptr noundef nonnull align 8 dereferenceable(6512) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  call void @_ZN11AES_Decrypt5ResetEv(ptr noundef nonnull align 8 dereferenceable(6512) %3)
  br label %4

4:                                                ; preds = %10, %1
  %5 = getelementptr inbounds %class.AES_Decrypt, ptr %3, i32 0, i32 2
  %6 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %5)
  %7 = load i8, ptr %6, align 1, !tbaa !9, !range !11, !noundef !12
  %8 = trunc i8 %7 to i1
  %9 = xor i1 %8, true
  br i1 %9, label %10, label %11

10:                                               ; preds = %4
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %3)
  br label %4, !llvm.loop !13

11:                                               ; preds = %4
  br label %12

12:                                               ; preds = %22, %11
  call void @_ZN11AES_Decrypt5InputEv(ptr noundef nonnull align 8 dereferenceable(6512) %3)
  %13 = getelementptr inbounds %class.AES_Decrypt, ptr %3, i32 0, i32 10
  %14 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %13)
  %15 = icmp eq i64 %14, 0
  br i1 %15, label %16, label %21

16:                                               ; preds = %12
  %17 = getelementptr inbounds %class.AES_Decrypt, ptr %3, i32 0, i32 12
  %18 = getelementptr inbounds [4 x [4 x %"class.sc_dt::sc_uint"]], ptr %17, i64 0, i64 0
  %19 = getelementptr inbounds %class.AES_Decrypt, ptr %3, i32 0, i32 11
  %20 = getelementptr inbounds [11 x [4 x [4 x %"class.sc_dt::sc_uint"]]], ptr %19, i64 0, i64 0
  call void @_ZN8AES_Base8SchedKeyEPA4_N5sc_dt7sc_uintILi8EEEPA4_S3_(ptr noundef nonnull align 8 dereferenceable(232) %3, ptr noundef %18, ptr noundef %20)
  call void @_ZN7sc_core9sc_module4waitEi(ptr noundef nonnull align 8 dereferenceable(232) %3, i32 noundef 3)
  br label %22

21:                                               ; preds = %12
  call void @_ZN11AES_Decrypt7DecryptEv(ptr noundef nonnull align 8 dereferenceable(6512) %3)
  call void @_ZN7sc_core9sc_module4waitEi(ptr noundef nonnull align 8 dereferenceable(232) %3, i32 noundef 12)
  call void @_ZN11AES_Decrypt6OutputEv(ptr noundef nonnull align 8 dereferenceable(6512) %3)
  br label %22

22:                                               ; preds = %21, %16
  br label %12, !llvm.loop !15
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEi(ptr noundef nonnull align 8 dereferenceable(232), i32 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt7DecryptEv(ptr noundef nonnull align 8 dereferenceable(6512)) #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN8AES_Base8SchedKeyEPA4_N5sc_dt7sc_uintILi8EEEPA4_S3_(ptr noundef nonnull align 8 dereferenceable(232), ptr noundef, ptr noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt5ResetEv(ptr noundef nonnull align 8 dereferenceable(6512)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt5InputEv(ptr noundef nonnull align 8 dereferenceable(6512)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt6OutputEv(ptr noundef nonnull align 8 dereferenceable(6512)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN11AES_Decrypt10MainThreadEv(ptr noundef nonnull align 8 dereferenceable(6512) %0) local_unnamed_addr #2 align 2 {
  tail call void @_ZN11AES_Decrypt5ResetEv(ptr noundef nonnull align 8 dereferenceable(6512) %0)
  %2 = getelementptr inbounds i8, ptr %0, i64 416
  %3 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %2)
  %4 = load i8, ptr %3, align 1, !tbaa !5, !range !9, !noundef !10
  %5 = trunc nuw i8 %4 to i1
  br i1 %5, label %.preheader, label %.lr.ph

.preheader:                                       ; preds = %.lr.ph, %1
  %6 = getelementptr inbounds i8, ptr %0, i64 1880
  %7 = getelementptr inbounds i8, ptr %0, i64 6128
  %8 = getelementptr inbounds i8, ptr %0, i64 1904
  br label %12

.lr.ph:                                           ; preds = %1, %.lr.ph
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %9 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %2)
  %10 = load i8, ptr %9, align 1, !tbaa !5, !range !9, !noundef !10
  %11 = trunc nuw i8 %10 to i1
  br i1 %11, label %.preheader, label %.lr.ph, !llvm.loop !11

12:                                               ; preds = %.backedge, %.preheader
  tail call void @_ZN11AES_Decrypt5InputEv(ptr noundef nonnull align 8 dereferenceable(6512) %0)
  %13 = tail call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %6)
  %14 = icmp eq i64 %13, 0
  br i1 %14, label %15, label %16

15:                                               ; preds = %12
  tail call void @_ZN8AES_Base8SchedKeyEPA4_N5sc_dt7sc_uintILi8EEEPA4_S3_(ptr noundef nonnull align 8 dereferenceable(232) %0, ptr noundef nonnull %7, ptr noundef nonnull %8)
  tail call void @_ZN7sc_core9sc_module4waitEi(ptr noundef nonnull align 8 dereferenceable(232) %0, i32 noundef 3)
  br label %.backedge

16:                                               ; preds = %12
  tail call void @_ZN11AES_Decrypt7DecryptEv(ptr noundef nonnull align 8 dereferenceable(6512) %0)
  tail call void @_ZN7sc_core9sc_module4waitEi(ptr noundef nonnull align 8 dereferenceable(232) %0, i32 noundef 12)
  tail call void @_ZN11AES_Decrypt6OutputEv(ptr noundef nonnull align 8 dereferenceable(6512) %0)
  br label %.backedge

.backedge:                                        ; preds = %16, %15
  br label %12, !llvm.loop !13
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEi(ptr noundef nonnull align 8 dereferenceable(232), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11AES_Decrypt7DecryptEv(ptr noundef nonnull align 8 dereferenceable(6512)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass