; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_signal_ports)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN7sc_core12sc_port_baseE = external constant ptr
@_ZTIN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE = external dso_local constant { ptr, ptr, ptr }, align 8
@_ZTIN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE = external dso_local constant { ptr, ptr, ptr }, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef nonnull align 8 dereferenceable(120)) #2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN7sc_core5sc_inIN5sc_dt8sc_logicEE5vbindERNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef nonnull align 8 dereferenceable(120) %1) unnamed_addr #3 align 2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  %9 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = icmp eq ptr %10, null
  br i1 %11, label %14, label %12

12:                                               ; preds = %2
  %13 = call ptr @__dynamic_cast(ptr %10, ptr @_ZTIN7sc_core12sc_port_baseE, ptr @_ZTIN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE, i64 0) #4
  br label %15

14:                                               ; preds = %2
  br label %15

15:                                               ; preds = %14, %12
  %16 = phi ptr [ %13, %12 ], [ null, %14 ]
  store ptr %16, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %21

19:                                               ; preds = %15
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120) %9, ptr noundef nonnull align 8 dereferenceable(120) %20)
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %35

21:                                               ; preds = %15
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = icmp eq ptr %22, null
  br i1 %23, label %26, label %24

24:                                               ; preds = %21
  %25 = call ptr @__dynamic_cast(ptr %22, ptr @_ZTIN7sc_core12sc_port_baseE, ptr @_ZTIN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE, i64 0) #4
  br label %27

26:                                               ; preds = %21
  br label %27

27:                                               ; preds = %26, %24
  %28 = phi ptr [ %25, %24 ], [ null, %26 ]
  store ptr %28, ptr %8, align 8, !tbaa !5
  %29 = load ptr, ptr %8, align 8, !tbaa !5
  %30 = icmp ne ptr %29, null
  br i1 %30, label %31, label %33

31:                                               ; preds = %27
  %32 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120) %9, ptr noundef nonnull align 8 dereferenceable(120) %32)
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %34

33:                                               ; preds = %27
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %34

34:                                               ; preds = %33, %31
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  br label %35

35:                                               ; preds = %34, %19
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  %36 = load i32, ptr %3, align 4
  ret i32 %36
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind willreturn memory(read) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN7sc_core12sc_port_baseE = external constant ptr
@_ZTIN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE = external dso_local constant { ptr, ptr, ptr }, align 8
@_ZTIN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE = external dso_local constant { ptr, ptr, ptr }, align 8

; Function Attrs: mustprogress nofree nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) local_unnamed_addr #0

declare void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef nonnull align 8 dereferenceable(120)) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local noundef range(i32 0, 3) i32 @_ZN7sc_core5sc_inIN5sc_dt8sc_logicEE5vbindERNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef nonnull align 8 dereferenceable(120) %1) unnamed_addr #2 align 2 {
  %3 = tail call ptr @__dynamic_cast(ptr nonnull %1, ptr nonnull @_ZTIN7sc_core12sc_port_baseE, ptr nonnull @_ZTIN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE, i64 0) #3
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %4, label %.sink.split

4:                                                ; preds = %2
  %5 = tail call ptr @__dynamic_cast(ptr nonnull %1, ptr nonnull @_ZTIN7sc_core12sc_port_baseE, ptr nonnull @_ZTIN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE, i64 0) #3
  %.not9 = icmp eq ptr %5, null
  br i1 %.not9, label %6, label %.sink.split

.sink.split:                                      ; preds = %4, %2
  %.sink = phi ptr [ %3, %2 ], [ %5, %4 ]
  tail call void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull align 8 dereferenceable(120) %.sink)
  br label %6

6:                                                ; preds = %.sink.split, %4
  %.1 = phi i32 [ 2, %4 ], [ 0, %.sink.split ]
  ret i32 %.1
}

attributes #0 = { mustprogress nofree nounwind willreturn memory(read) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass