; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/SourceLevelDebugPkg (XhcCreateTransferTrb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._URB = type <{ i64, i32, i32, i32, i64, i64, i8, i32 }>
%struct._USB3_DEBUG_PORT_INSTANCE = type <{ i8, i8, i8, i8, i64, i64, i64, i64, i64, %struct._TRANSFER_RING, %struct._TRANSFER_RING, %struct._EVENT_RING, %struct._URB, %struct._URB, i8, i64, i64, i64, i8 }>
%struct._TRANSFER_RING = type <{ i64, i32, i64, i64, i32 }>
%struct._EVENT_RING = type <{ i64, i64, i32, i64, i64, i32 }>
%struct._TRANSFER_TRB_NORMAL = type { i32, i32, i64 }

; Function Attrs: nounwind uwtable
declare dso_local i64 @XhcSyncTrsRing(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare i64 @RShiftU64(i64 noundef, i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i64 @XhcCreateTransferTrb(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  %7 = load ptr, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct._URB, ptr %7, i32 0, i32 7
  %9 = load i32, ptr %8, align 1, !tbaa !9
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %11, label %14

11:                                               ; preds = %2
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %12, i32 0, i32 10
  store ptr %13, ptr %5, align 8, !tbaa !5
  br label %17

14:                                               ; preds = %2
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %15, i32 0, i32 9
  store ptr %16, ptr %5, align 8, !tbaa !5
  br label %17

17:                                               ; preds = %14, %11
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = ptrtoint ptr %18 to i64
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct._URB, ptr %20, i32 0, i32 4
  store i64 %19, ptr %21, align 1, !tbaa !13
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = call i64 @XhcSyncTrsRing(ptr noundef %22, ptr noundef %23)
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct._TRANSFER_RING, ptr %25, i32 0, i32 2
  %27 = load i64, ptr %26, align 1, !tbaa !14
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct._URB, ptr %28, i32 0, i32 5
  store i64 %27, ptr %29, align 1, !tbaa !16
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct._TRANSFER_RING, ptr %30, i32 0, i32 2
  %32 = load i64, ptr %31, align 1, !tbaa !14
  %33 = inttoptr i64 %32 to ptr
  store ptr %33, ptr %6, align 8, !tbaa !5
  %34 = load ptr, ptr %4, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct._URB, ptr %34, i32 0, i32 0
  %36 = load i64, ptr %35, align 1, !tbaa !17
  %37 = and i64 %36, 4294967295
  %38 = trunc i64 %37 to i32
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %39, i32 0, i32 0
  store i32 %38, ptr %40, align 1, !tbaa !18
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct._URB, ptr %41, i32 0, i32 0
  %43 = load i64, ptr %42, align 1, !tbaa !17
  %44 = call i64 @RShiftU64(i64 noundef %43, i64 noundef 32)
  %45 = and i64 %44, 4294967295
  %46 = trunc i64 %45 to i32
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %47, i32 0, i32 1
  store i32 %46, ptr %48, align 1, !tbaa !18
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct._URB, ptr %49, i32 0, i32 1
  %51 = load i32, ptr %50, align 1, !tbaa !19
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %52, i32 0, i32 2
  %54 = zext i32 %51 to i64
  %55 = load i64, ptr %53, align 1
  %56 = and i64 %54, 131071
  %57 = and i64 %55, -131072
  %58 = or i64 %57, %56
  store i64 %58, ptr %53, align 1
  %59 = trunc i64 %56 to i32
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %60, i32 0, i32 2
  %62 = load i64, ptr %61, align 1
  %63 = and i64 %62, -4063233
  %64 = or i64 %63, 0
  store i64 %64, ptr %61, align 1
  %65 = load ptr, ptr %6, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %65, i32 0, i32 2
  %67 = load i64, ptr %66, align 1
  %68 = and i64 %67, -4290772993
  %69 = or i64 %68, 0
  store i64 %69, ptr %66, align 1
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %70, i32 0, i32 2
  %72 = load i64, ptr %71, align 1
  %73 = and i64 %72, -17179869185
  %74 = or i64 %73, 17179869184
  store i64 %74, ptr %71, align 1
  %75 = load ptr, ptr %6, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %75, i32 0, i32 2
  %77 = load i64, ptr %76, align 1
  %78 = and i64 %77, -137438953473
  %79 = or i64 %78, 137438953472
  store i64 %79, ptr %76, align 1
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %80, i32 0, i32 2
  %82 = load i64, ptr %81, align 1
  %83 = and i64 %82, -277076930199553
  %84 = or i64 %83, 4398046511104
  store i64 %84, ptr %81, align 1
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct._TRANSFER_RING, ptr %85, i32 0, i32 4
  %87 = load i32, ptr %86, align 1, !tbaa !20
  %88 = and i32 %87, 1
  %89 = load ptr, ptr %6, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct._TRANSFER_TRB_NORMAL, ptr %89, i32 0, i32 2
  %91 = zext i32 %88 to i64
  %92 = load i64, ptr %90, align 1
  %93 = and i64 %91, 1
  %94 = shl i64 %93, 32
  %95 = and i64 %92, -4294967297
  %96 = or i64 %95, %94
  store i64 %96, ptr %90, align 1
  %97 = trunc i64 %93 to i32
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  ret i64 0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 37}
!10 = !{!"_URB", !11, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !11, i64 20, !11, i64 28, !7, i64 36, !12, i64 37}
!11 = !{!"long long", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !11, i64 20}
!14 = !{!15, !11, i64 12}
!15 = !{!"_TRANSFER_RING", !11, i64 0, !12, i64 8, !11, i64 12, !11, i64 20, !12, i64 28}
!16 = !{!10, !11, i64 28}
!17 = !{!10, !11, i64 0}
!18 = !{!7, !7, i64 0}
!19 = !{!10, !12, i64 8}
!20 = !{!15, !12, i64 28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i64 @XhcSyncTrsRing(ptr noundef, ptr noundef) local_unnamed_addr #0

declare i64 @RShiftU64(i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local noundef i64 @XhcCreateTransferTrb(ptr noundef %0, ptr nocapture noundef %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %1, i64 37
  %4 = load i32, ptr %3, align 1, !tbaa !5
  %5 = icmp eq i32 %4, 0
  %.0.v = select i1 %5, i64 76, i64 44
  %.0 = getelementptr inbounds i8, ptr %0, i64 %.0.v
  %6 = ptrtoint ptr %.0 to i64
  %7 = getelementptr inbounds i8, ptr %1, i64 20
  store i64 %6, ptr %7, align 1, !tbaa !11
  %8 = tail call i64 @XhcSyncTrsRing(ptr noundef %0, ptr noundef nonnull %.0)
  %9 = getelementptr inbounds i8, ptr %.0, i64 12
  %10 = load i64, ptr %9, align 1, !tbaa !12
  %11 = getelementptr inbounds i8, ptr %1, i64 28
  store i64 %10, ptr %11, align 1, !tbaa !14
  %12 = inttoptr i64 %10 to ptr
  %13 = load i64, ptr %1, align 1, !tbaa !15
  %14 = trunc i64 %13 to i32
  store i32 %14, ptr %12, align 1, !tbaa !16
  %15 = load i64, ptr %1, align 1, !tbaa !15
  %16 = tail call i64 @RShiftU64(i64 noundef %15, i64 noundef 32) #2
  %17 = trunc i64 %16 to i32
  %18 = getelementptr inbounds i8, ptr %12, i64 4
  store i32 %17, ptr %18, align 1, !tbaa !16
  %19 = getelementptr inbounds i8, ptr %1, i64 8
  %20 = load i32, ptr %19, align 1, !tbaa !17
  %21 = getelementptr inbounds i8, ptr %12, i64 8
  %22 = load i64, ptr %21, align 1
  %23 = and i32 %20, 131071
  %24 = zext nneg i32 %23 to i64
  %25 = and i64 %22, -277235843989504
  %26 = or disjoint i64 %25, %24
  %27 = or disjoint i64 %26, 4552665333760
  store i64 %27, ptr %21, align 1
  %28 = getelementptr inbounds i8, ptr %.0, i64 28
  %29 = load i32, ptr %28, align 1, !tbaa !18
  %30 = and i32 %29, 1
  %31 = zext nneg i32 %30 to i64
  %32 = shl nuw nsw i64 %31, 32
  %33 = and i64 %27, -272687473491969
  %34 = or disjoint i64 %32, %33
  store i64 %34, ptr %21, align 1
  ret i64 0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 37}
!6 = !{!"_URB", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !7, i64 20, !7, i64 28, !8, i64 36, !10, i64 37}
!7 = !{!"long long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!6, !7, i64 20}
!12 = !{!13, !7, i64 12}
!13 = !{!"_TRANSFER_RING", !7, i64 0, !10, i64 8, !7, i64 12, !7, i64 20, !10, i64 28}
!14 = !{!6, !7, i64 28}
!15 = !{!6, !7, i64 0}
!16 = !{!8, !8, i64 0}
!17 = !{!6, !10, i64 8}
!18 = !{!13, !10, i64 28}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass