; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_simcontext)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_handle" = type { ptr }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #1

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext22create_cthread_processEPKcbMNS_15sc_process_hostEFvvEPS3_PKNS_16sc_spawn_optionsE(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_process_handle") align 8 %0, ptr noundef nonnull align 8 dereferenceable(344) %1, ptr noundef %2, i1 noundef zeroext %3, i64 %4, i64 %5, ptr noundef %6, ptr noundef %7) #3 align 2 personality ptr @__gxx_personality_v0 {
  %9 = alloca ptr, align 8
  %10 = alloca { i64, i64 }, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i8, align 1
  %14 = alloca { i64, i64 }, align 8
  %15 = alloca ptr, align 8
  %16 = alloca ptr, align 8
  %17 = alloca ptr, align 8
  %18 = alloca { i64, i64 }, align 8
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  store ptr %0, ptr %9, align 8
  %21 = getelementptr inbounds { i64, i64 }, ptr %10, i32 0, i32 0
  store i64 %4, ptr %21, align 8
  %22 = getelementptr inbounds { i64, i64 }, ptr %10, i32 0, i32 1
  store i64 %5, ptr %22, align 8
  %23 = load { i64, i64 }, ptr %10, align 8, !tbaa !5
  store ptr %1, ptr %11, align 8, !tbaa !8
  store ptr %2, ptr %12, align 8, !tbaa !8
  %24 = zext i1 %3 to i8
  store i8 %24, ptr %13, align 1, !tbaa !10
  store { i64, i64 } %23, ptr %14, align 8, !tbaa !5
  store ptr %6, ptr %15, align 8, !tbaa !8
  store ptr %7, ptr %16, align 8, !tbaa !8
  %25 = load ptr, ptr %11, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #6
  %26 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 408) #7
  %27 = load ptr, ptr %12, align 8, !tbaa !8
  %28 = load i8, ptr %13, align 1, !tbaa !10, !range !12, !noundef !13
  %29 = trunc i8 %28 to i1
  %30 = load { i64, i64 }, ptr %14, align 8, !tbaa !5
  %31 = load ptr, ptr %15, align 8, !tbaa !8
  %32 = load ptr, ptr %16, align 8, !tbaa !8
  store { i64, i64 } %30, ptr %18, align 8, !tbaa !5
  %33 = getelementptr inbounds { i64, i64 }, ptr %18, i32 0, i32 0
  %34 = load i64, ptr %33, align 8
  %35 = getelementptr inbounds { i64, i64 }, ptr %18, i32 0, i32 1
  %36 = load i64, ptr %35, align 8
  invoke void @_ZN7sc_core18sc_cthread_processC1EPKcbMNS_15sc_process_hostEFvvEPS3_PKNS_16sc_spawn_optionsE(ptr noundef nonnull align 8 dereferenceable(404) %26, ptr noundef %27, i1 noundef zeroext %29, i64 %34, i64 %36, ptr noundef %31, ptr noundef %32)
          to label %37 unwind label %46

37:                                               ; preds = %8
  store ptr %26, ptr %17, align 8, !tbaa !8
  %38 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %25, i32 0, i32 29
  %39 = load i8, ptr %38, align 2, !tbaa !14, !range !12, !noundef !13
  %40 = trunc i8 %39 to i1
  br i1 %40, label %41, label %50

41:                                               ; preds = %37
  %42 = load ptr, ptr %17, align 8, !tbaa !8
  %43 = load ptr, ptr %42, align 8, !tbaa !39
  %44 = getelementptr inbounds ptr, ptr %43, i64 24
  %45 = load ptr, ptr %44, align 8
  call void %45(ptr noundef nonnull align 8 dereferenceable(404) %42)
  br label %54

46:                                               ; preds = %8
  %47 = landingpad { ptr, i32 }
          cleanup
  %48 = extractvalue { ptr, i32 } %47, 0
  store ptr %48, ptr %19, align 8
  %49 = extractvalue { ptr, i32 } %47, 1
  store i32 %49, ptr %20, align 4
  call void @_ZdlPvm(ptr noundef %26, i64 noundef 408) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #6
  br label %56

50:                                               ; preds = %37
  %51 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %25, i32 0, i32 7
  %52 = load ptr, ptr %51, align 8, !tbaa !41
  %53 = load ptr, ptr %17, align 8, !tbaa !8
  call void @_ZN7sc_core16sc_process_table10push_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(16) %52, ptr noundef %53)
  br label %54

54:                                               ; preds = %50, %41
  %55 = load ptr, ptr %17, align 8, !tbaa !8
  call void @_ZN7sc_core17sc_process_handleC2EPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %55)
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #6
  ret void

56:                                               ; preds = %46
  %57 = load ptr, ptr %19, align 8
  %58 = load i32, ptr %20, align 4
  %59 = insertvalue { ptr, i32 } poison, ptr %57, 0
  %60 = insertvalue { ptr, i32 } %59, i32 %58, 1
  resume { ptr, i32 } %60
}

declare void @_ZN7sc_core18sc_cthread_processC1EPKcbMNS_15sc_process_hostEFvvEPS3_PKNS_16sc_spawn_optionsE(ptr noundef nonnull align 8 dereferenceable(404), ptr noundef, i1 noundef zeroext, i64, i64, ptr noundef, ptr noundef) unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core16sc_process_table10push_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef) #5 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core17sc_process_handleC2EPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) unnamed_addr #5 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"bool", !6, i64 0}
!12 = !{i8 0, i8 2}
!13 = !{}
!14 = !{!15, !11, i64 298}
!15 = !{!"_ZTSN7sc_core13sc_simcontextE", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56, !16, i64 64, !9, i64 80, !11, i64 88, !18, i64 92, !19, i64 96, !23, i64 120, !27, i64 144, !23, i64 168, !9, i64 192, !31, i64 200, !11, i64 224, !9, i64 232, !9, i64 240, !9, i64 248, !35, i64 256, !35, i64 264, !9, i64 272, !36, i64 280, !36, i64 288, !11, i64 296, !11, i64 297, !11, i64 298, !11, i64 299, !37, i64 300, !9, i64 304, !11, i64 312, !11, i64 313, !38, i64 316, !11, i64 320, !9, i64 328, !9, i64 336}
!16 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !9, i64 0, !17, i64 8}
!17 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !6, i64 0}
!18 = !{!"int", !6, i64 0}
!19 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!31 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!35 = !{!"_ZTSN7sc_core7sc_timeE", !36, i64 0}
!36 = !{!"long long", !6, i64 0}
!37 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !6, i64 0}
!38 = !{!"_ZTSN7sc_core9sc_statusE", !6, i64 0}
!39 = !{!40, !40, i64 0}
!40 = !{!"vtable pointer", !7, i64 0}
!41 = !{!15, !9, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_handle" = type { ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #0

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext22create_cthread_processEPKcbMNS_15sc_process_hostEFvvEPS3_PKNS_16sc_spawn_optionsE(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_process_handle") align 8 %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(344) %1, ptr noundef %2, i1 noundef zeroext %3, i64 %4, i64 %5, ptr noundef %6, ptr noundef %7) local_unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %9 = tail call noalias noundef nonnull dereferenceable(408) ptr @_Znwm(i64 noundef 408) #5
  invoke void @_ZN7sc_core18sc_cthread_processC1EPKcbMNS_15sc_process_hostEFvvEPS3_PKNS_16sc_spawn_optionsE(ptr noundef nonnull align 8 dereferenceable(404) %9, ptr noundef %2, i1 noundef zeroext %3, i64 %4, i64 %5, ptr noundef %6, ptr noundef %7)
          to label %10 unwind label %18

10:                                               ; preds = %8
  %11 = getelementptr inbounds i8, ptr %1, i64 298
  %12 = load i8, ptr %11, align 2, !tbaa !5, !range !34, !noundef !35
  %13 = trunc nuw i8 %12 to i1
  br i1 %13, label %14, label %20

14:                                               ; preds = %10
  %15 = load ptr, ptr %9, align 8, !tbaa !36
  %16 = getelementptr inbounds i8, ptr %15, i64 192
  %17 = load ptr, ptr %16, align 8
  tail call void %17(ptr noundef nonnull align 8 dereferenceable(404) %9)
  br label %23

18:                                               ; preds = %8
  %19 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %9, i64 noundef 408) #6
  resume { ptr, i32 } %19

20:                                               ; preds = %10
  %21 = getelementptr inbounds i8, ptr %1, i64 56
  %22 = load ptr, ptr %21, align 8, !tbaa !38
  tail call void @_ZN7sc_core16sc_process_table10push_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(16) %22, ptr noundef nonnull %9)
  br label %23

23:                                               ; preds = %20, %14
  tail call void @_ZN7sc_core17sc_process_handleC2EPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef nonnull %9)
  ret void
}

declare void @_ZN7sc_core18sc_cthread_processC1EPKcbMNS_15sc_process_hostEFvvEPS3_PKNS_16sc_spawn_optionsE(ptr noundef nonnull align 8 dereferenceable(404), ptr noundef, i1 noundef zeroext, i64, i64, ptr noundef, ptr noundef) unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core16sc_process_table10push_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef) local_unnamed_addr #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core17sc_process_handleC2EPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) unnamed_addr #4 align 2

attributes #0 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { builtin allocsize(0) }
attributes #6 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 298}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{i8 0, i8 2}
!35 = !{}
!36 = !{!37, !37, i64 0}
!37 = !{!"vtable pointer", !9, i64 0}
!38 = !{!6, !7, i64 56}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass