; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/gnats/pr213/pr213.ll (ZN3abc5entryEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.abc = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3abc5entryEv(ptr noundef nonnull align 8 dereferenceable(440) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  store i32 0, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %6

6:                                                ; preds = %37, %1
  %7 = load i32, ptr %3, align 4, !tbaa !9
  %8 = add nsw i32 %7, 1
  store i32 %8, ptr %3, align 4, !tbaa !9
  %9 = load i32, ptr %3, align 4, !tbaa !9
  %10 = icmp eq i32 %9, 5
  br i1 %10, label %11, label %12

11:                                               ; preds = %6
  br label %19

12:                                               ; preds = %6
  %13 = load i32, ptr %3, align 4, !tbaa !9
  %14 = icmp eq i32 %13, 7
  br i1 %14, label %15, label %16

15:                                               ; preds = %12
  br label %39

16:                                               ; preds = %12
  %17 = load i32, ptr %4, align 4, !tbaa !9
  %18 = add nsw i32 %17, 2
  store i32 %18, ptr %4, align 4, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %5)
  br label %19

19:                                               ; preds = %16, %11
  %20 = getelementptr inbounds %struct.abc, ptr %5, i32 0, i32 2
  %21 = load ptr, ptr %20, align 8, !tbaa !11
  %22 = load ptr, ptr %21, align 8, !tbaa !42
  %23 = getelementptr inbounds ptr, ptr %22, i64 7
  %24 = load ptr, ptr %23, align 8
  %25 = call noundef nonnull align 1 dereferenceable(1) ptr %24(ptr noundef nonnull align 8 dereferenceable(224) %21)
  %26 = load i8, ptr %25, align 1, !tbaa !44, !range !45, !noundef !46
  %27 = trunc i8 %26 to i1
  br i1 %27, label %28, label %37

28:                                               ; preds = %19
  %29 = getelementptr inbounds %struct.abc, ptr %5, i32 0, i32 3
  %30 = load ptr, ptr %29, align 8, !tbaa !47
  %31 = load ptr, ptr %30, align 8, !tbaa !42
  %32 = getelementptr inbounds ptr, ptr %31, i64 7
  %33 = load ptr, ptr %32, align 8
  %34 = call noundef nonnull align 1 dereferenceable(1) ptr %33(ptr noundef nonnull align 8 dereferenceable(224) %30)
  %35 = load i8, ptr %34, align 1, !tbaa !44, !range !45, !noundef !46
  %36 = trunc i8 %35 to i1
  br label %37

37:                                               ; preds = %28, %19
  %38 = phi i1 [ false, %19 ], [ %36, %28 ]
  br i1 %38, label %6, label %39, !llvm.loop !48

39:                                               ; preds = %37, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 416}
!12 = !{!"_ZTS3abc", !13, i64 0, !34, i64 232, !6, i64 416, !6, i64 424, !6, i64 432}
!13 = !{!"_ZTSN7sc_core9sc_moduleE", !14, i64 0, !26, i64 112, !27, i64 120, !29, i64 144, !31, i64 168, !33, i64 192, !6, i64 200, !10, i64 208, !6, i64 216, !6, i64 224}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !6, i64 96, !6, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !28, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !30, i64 8, !6, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !32, i64 8, !6, i64 16}
!32 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!33 = !{!"bool", !7, i64 0}
!34 = !{!"_ZTSN7sc_core5sc_inIbEE", !35, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!35 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !36, i64 0}
!36 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !37, i64 0, !6, i64 120, !38, i64 128}
!37 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !6, i64 112}
!38 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!43, !43, i64 0}
!43 = !{!"vtable pointer", !8, i64 0}
!44 = !{!33, !33, i64 0}
!45 = !{i8 0, i8 2}
!46 = !{}
!47 = !{!12, !6, i64 424}
!48 = distinct !{!48, !49}
!49 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3abc5entryEv(ptr noundef nonnull align 8 dereferenceable(440) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 416
  %3 = getelementptr inbounds i8, ptr %0, i64 424
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %4, align 8, !tbaa !40
  %6 = getelementptr inbounds i8, ptr %5, i64 56
  %7 = load ptr, ptr %6, align 8
  %8 = tail call noundef nonnull align 1 dereferenceable(1) ptr %7(ptr noundef nonnull align 8 dereferenceable(224) %4)
  %9 = load i8, ptr %8, align 1, !tbaa !42, !range !43, !noundef !44
  %10 = trunc nuw i8 %9 to i1
  br i1 %10, label %11, label %.critedge

11:                                               ; preds = %1
  %12 = load ptr, ptr %3, align 8, !tbaa !45
  %13 = load ptr, ptr %12, align 8, !tbaa !40
  %14 = getelementptr inbounds i8, ptr %13, i64 56
  %15 = load ptr, ptr %14, align 8
  %16 = tail call noundef nonnull align 1 dereferenceable(1) ptr %15(ptr noundef nonnull align 8 dereferenceable(224) %12)
  %17 = load i8, ptr %16, align 1, !tbaa !42, !range !43, !noundef !44
  %18 = trunc nuw i8 %17 to i1
  br i1 %18, label %19, label %.critedge, !llvm.loop !46

19:                                               ; preds = %11
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %20 = load ptr, ptr %2, align 8, !tbaa !5
  %21 = load ptr, ptr %20, align 8, !tbaa !40
  %22 = getelementptr inbounds i8, ptr %21, i64 56
  %23 = load ptr, ptr %22, align 8
  %24 = tail call noundef nonnull align 1 dereferenceable(1) ptr %23(ptr noundef nonnull align 8 dereferenceable(224) %20)
  %25 = load i8, ptr %24, align 1, !tbaa !42, !range !43, !noundef !44
  %26 = trunc nuw i8 %25 to i1
  br i1 %26, label %27, label %.critedge

27:                                               ; preds = %19
  %28 = load ptr, ptr %3, align 8, !tbaa !45
  %29 = load ptr, ptr %28, align 8, !tbaa !40
  %30 = getelementptr inbounds i8, ptr %29, i64 56
  %31 = load ptr, ptr %30, align 8
  %32 = tail call noundef nonnull align 1 dereferenceable(1) ptr %31(ptr noundef nonnull align 8 dereferenceable(224) %28)
  %33 = load i8, ptr %32, align 1, !tbaa !42, !range !43, !noundef !44
  %34 = trunc nuw i8 %33 to i1
  br i1 %34, label %35, label %.critedge, !llvm.loop !46

35:                                               ; preds = %27
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %36 = load ptr, ptr %2, align 8, !tbaa !5
  %37 = load ptr, ptr %36, align 8, !tbaa !40
  %38 = getelementptr inbounds i8, ptr %37, i64 56
  %39 = load ptr, ptr %38, align 8
  %40 = tail call noundef nonnull align 1 dereferenceable(1) ptr %39(ptr noundef nonnull align 8 dereferenceable(224) %36)
  %41 = load i8, ptr %40, align 1, !tbaa !42, !range !43, !noundef !44
  %42 = trunc nuw i8 %41 to i1
  br i1 %42, label %43, label %.critedge

43:                                               ; preds = %35
  %44 = load ptr, ptr %3, align 8, !tbaa !45
  %45 = load ptr, ptr %44, align 8, !tbaa !40
  %46 = getelementptr inbounds i8, ptr %45, i64 56
  %47 = load ptr, ptr %46, align 8
  %48 = tail call noundef nonnull align 1 dereferenceable(1) ptr %47(ptr noundef nonnull align 8 dereferenceable(224) %44)
  %49 = load i8, ptr %48, align 1, !tbaa !42, !range !43, !noundef !44
  %50 = trunc nuw i8 %49 to i1
  br i1 %50, label %51, label %.critedge, !llvm.loop !46

51:                                               ; preds = %43
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %52 = load ptr, ptr %2, align 8, !tbaa !5
  %53 = load ptr, ptr %52, align 8, !tbaa !40
  %54 = getelementptr inbounds i8, ptr %53, i64 56
  %55 = load ptr, ptr %54, align 8
  %56 = tail call noundef nonnull align 1 dereferenceable(1) ptr %55(ptr noundef nonnull align 8 dereferenceable(224) %52)
  %57 = load i8, ptr %56, align 1, !tbaa !42, !range !43, !noundef !44
  %58 = trunc nuw i8 %57 to i1
  br i1 %58, label %59, label %.critedge

59:                                               ; preds = %51
  %60 = load ptr, ptr %3, align 8, !tbaa !45
  %61 = load ptr, ptr %60, align 8, !tbaa !40
  %62 = getelementptr inbounds i8, ptr %61, i64 56
  %63 = load ptr, ptr %62, align 8
  %64 = tail call noundef nonnull align 1 dereferenceable(1) ptr %63(ptr noundef nonnull align 8 dereferenceable(224) %60)
  %65 = load i8, ptr %64, align 1, !tbaa !42, !range !43, !noundef !44
  %66 = trunc nuw i8 %65 to i1
  br i1 %66, label %67, label %.critedge, !llvm.loop !46

67:                                               ; preds = %59
  %68 = load ptr, ptr %2, align 8, !tbaa !5
  %69 = load ptr, ptr %68, align 8, !tbaa !40
  %70 = getelementptr inbounds i8, ptr %69, i64 56
  %71 = load ptr, ptr %70, align 8
  %72 = tail call noundef nonnull align 1 dereferenceable(1) ptr %71(ptr noundef nonnull align 8 dereferenceable(224) %68)
  %73 = load i8, ptr %72, align 1, !tbaa !42, !range !43, !noundef !44
  %74 = trunc nuw i8 %73 to i1
  br i1 %74, label %75, label %.critedge

75:                                               ; preds = %67
  %76 = load ptr, ptr %3, align 8, !tbaa !45
  %77 = load ptr, ptr %76, align 8, !tbaa !40
  %78 = getelementptr inbounds i8, ptr %77, i64 56
  %79 = load ptr, ptr %78, align 8
  %80 = tail call noundef nonnull align 1 dereferenceable(1) ptr %79(ptr noundef nonnull align 8 dereferenceable(224) %76)
  %81 = load i8, ptr %80, align 1, !tbaa !42, !range !43, !noundef !44
  %82 = trunc nuw i8 %81 to i1
  br i1 %82, label %83, label %.critedge, !llvm.loop !46

83:                                               ; preds = %75
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %84 = load ptr, ptr %2, align 8, !tbaa !5
  %85 = load ptr, ptr %84, align 8, !tbaa !40
  %86 = getelementptr inbounds i8, ptr %85, i64 56
  %87 = load ptr, ptr %86, align 8
  %88 = tail call noundef nonnull align 1 dereferenceable(1) ptr %87(ptr noundef nonnull align 8 dereferenceable(224) %84)
  %89 = load i8, ptr %88, align 1, !tbaa !42, !range !43, !noundef !44
  %90 = trunc nuw i8 %89 to i1
  br i1 %90, label %91, label %.critedge

91:                                               ; preds = %83
  %92 = load ptr, ptr %3, align 8, !tbaa !45
  %93 = load ptr, ptr %92, align 8, !tbaa !40
  %94 = getelementptr inbounds i8, ptr %93, i64 56
  %95 = load ptr, ptr %94, align 8
  %96 = tail call noundef nonnull align 1 dereferenceable(1) ptr %95(ptr noundef nonnull align 8 dereferenceable(224) %92)
  br label %.critedge

.critedge:                                        ; preds = %91, %83, %75, %67, %59, %51, %43, %35, %27, %19, %1, %11
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 416}
!6 = !{!"_ZTS3abc", !7, i64 0, !32, i64 232, !9, i64 416, !9, i64 424, !9, i64 432}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core5sc_inIbEE", !33, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!33 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !35, i64 0, !9, i64 120, !36, i64 128}
!35 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!36 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!40 = !{!41, !41, i64 0}
!41 = !{!"vtable pointer", !11, i64 0}
!42 = !{!30, !30, i64 0}
!43 = !{i8 0, i8 2}
!44 = !{}
!45 = !{!6, !9, i64 424}
!46 = distinct !{!46, !47}
!47 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: ADCEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass