; LLVM IR from gem5/gem5 :: ext/mcpat/core.ll (ZN10InstFetchUD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.InstFetchU = type <{ %class.McPATComponent, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %class.InputParameter, %class.CoreParameters, %class.CoreStatistics, %class.InstFetchParameters, [4 x i8], %class.InstFetchStatistics, double, double, double, i32, i8, [3 x i8] }>
%class.McPATComponent = type { ptr, %class.Component, ptr, %class.InputParameter, %"class.std::__cxx11::basic_string", double, %"class.std::vector", %class.McPATOutput, %class.statsDef, %class.statsDef, %class.powerDef, %class.powerDef }
%class.Component = type { %class.Area, %class.powerDef, %class.powerDef, double, double }
%class.Area = type { double, double, double }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<McPATComponent *, std::allocator<McPATComponent *>>::_Vector_impl" }
%"struct.std::_Vector_base<McPATComponent *, std::allocator<McPATComponent *>>::_Vector_impl" = type { %"struct.std::_Vector_base<McPATComponent *, std::allocator<McPATComponent *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<McPATComponent *, std::allocator<McPATComponent *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.McPATOutput = type { double, double, double, double, double, double }
%class.statsDef = type { %class.statsComponents, %class.statsComponents, %class.statsComponents, %class.statsComponents, %class.statsComponents, %class.statsComponents, %class.statsComponents }
%class.statsComponents = type { double, double, double }
%class.powerDef = type { %class.powerComponents, %class.powerComponents, %class.powerComponents }
%class.powerComponents = type { double, double, double, double, double }
%class.InputParameter = type { i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, i32, double, double, i32, i32, i32, i32, i32, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i8, i8, i32, i32, i8, double, double, i8, i32, i32, i8 }
%class.CoreParameters = type { i8, i8, i8, i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i8, i8, [4 x double], i32, i32, i32, i32, i32, i32, i32, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double, double, i32, double, double }
%class.CoreStatistics = type { double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double }
%class.InstFetchParameters = type { i32, i32, i32, i32, i32, i32, i32 }
%class.InstFetchStatistics = type { double, double }

@_ZTV10InstFetchU = external dso_local unnamed_addr constant { [6 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN10InstFetchUD2Ev(ptr noundef nonnull align 8 dereferenceable(2725) %0) unnamed_addr #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 32) ({ [6 x ptr] }, ptr @_ZTV10InstFetchU, i32 0, i32 0, i32 2), ptr %4, align 8, !tbaa !9
  %5 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 18
  %6 = load i8, ptr %5, align 4, !tbaa !11, !range !41, !noundef !42
  %7 = trunc i8 %6 to i1
  br i1 %7, label %9, label %8

8:                                                ; preds = %1
  store i32 1, ptr %3, align 4
  br label %92

9:                                                ; preds = %1
  %10 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 2
  %11 = load ptr, ptr %10, align 8, !tbaa !43
  %12 = icmp ne ptr %11, null
  br i1 %12, label %13, label %20

13:                                               ; preds = %9
  %14 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 2
  %15 = load ptr, ptr %14, align 8, !tbaa !43
  %16 = icmp eq ptr %15, null
  br i1 %16, label %18, label %17

17:                                               ; preds = %13
  call void @_ZN7ArraySTD1Ev(ptr noundef nonnull align 8 dereferenceable(10104) %15) #3
  call void @_ZdlPvm(ptr noundef %15, i64 noundef 10104) #4
  br label %18

18:                                               ; preds = %17, %13
  %19 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 2
  store ptr null, ptr %19, align 8, !tbaa !43
  br label %20

20:                                               ; preds = %18, %9
  %21 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 5
  %22 = load ptr, ptr %21, align 8, !tbaa !44
  %23 = icmp ne ptr %22, null
  br i1 %23, label %24, label %31

24:                                               ; preds = %20
  %25 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 5
  %26 = load ptr, ptr %25, align 8, !tbaa !44
  %27 = icmp eq ptr %26, null
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  call void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136) %26) #3
  call void @_ZdlPvm(ptr noundef %26, i64 noundef 10136) #4
  br label %29

29:                                               ; preds = %28, %24
  %30 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 5
  store ptr null, ptr %30, align 8, !tbaa !44
  br label %31

31:                                               ; preds = %29, %20
  %32 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 6
  %33 = load ptr, ptr %32, align 8, !tbaa !45
  %34 = icmp ne ptr %33, null
  br i1 %34, label %35, label %42

35:                                               ; preds = %31
  %36 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 6
  %37 = load ptr, ptr %36, align 8, !tbaa !45
  %38 = icmp eq ptr %37, null
  br i1 %38, label %40, label %39

39:                                               ; preds = %35
  call void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136) %37) #3
  call void @_ZdlPvm(ptr noundef %37, i64 noundef 10136) #4
  br label %40

40:                                               ; preds = %39, %35
  %41 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 6
  store ptr null, ptr %41, align 8, !tbaa !45
  br label %42

42:                                               ; preds = %40, %31
  %43 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 7
  %44 = load ptr, ptr %43, align 8, !tbaa !46
  %45 = icmp ne ptr %44, null
  br i1 %45, label %46, label %53

46:                                               ; preds = %42
  %47 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 7
  %48 = load ptr, ptr %47, align 8, !tbaa !46
  %49 = icmp eq ptr %48, null
  br i1 %49, label %51, label %50

50:                                               ; preds = %46
  call void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136) %48) #3
  call void @_ZdlPvm(ptr noundef %48, i64 noundef 10136) #4
  br label %51

51:                                               ; preds = %50, %46
  %52 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 7
  store ptr null, ptr %52, align 8, !tbaa !46
  br label %53

53:                                               ; preds = %51, %42
  %54 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 9
  %55 = getelementptr inbounds %class.CoreParameters, ptr %54, i32 0, i32 23
  %56 = load i32, ptr %55, align 8, !tbaa !47
  %57 = icmp sgt i32 %56, 0
  br i1 %57, label %58, label %81

58:                                               ; preds = %53
  %59 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 3
  %60 = load ptr, ptr %59, align 8, !tbaa !48
  %61 = icmp ne ptr %60, null
  br i1 %61, label %62, label %69

62:                                               ; preds = %58
  %63 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 3
  %64 = load ptr, ptr %63, align 8, !tbaa !48
  %65 = icmp eq ptr %64, null
  br i1 %65, label %67, label %66

66:                                               ; preds = %62
  call void @_ZN7ArraySTD1Ev(ptr noundef nonnull align 8 dereferenceable(10104) %64) #3
  call void @_ZdlPvm(ptr noundef %64, i64 noundef 10104) #4
  br label %67

67:                                               ; preds = %66, %62
  %68 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 3
  store ptr null, ptr %68, align 8, !tbaa !48
  br label %69

69:                                               ; preds = %67, %58
  %70 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 4
  %71 = load ptr, ptr %70, align 8, !tbaa !49
  %72 = icmp ne ptr %71, null
  br i1 %72, label %73, label %80

73:                                               ; preds = %69
  %74 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 4
  %75 = load ptr, ptr %74, align 8, !tbaa !49
  %76 = icmp eq ptr %75, null
  br i1 %76, label %78, label %77

77:                                               ; preds = %73
  call void @_ZN15BranchPredictorD1Ev(ptr noundef nonnull align 8 dereferenceable(2705) %75) #3
  call void @_ZdlPvm(ptr noundef %75, i64 noundef 2712) #4
  br label %78

78:                                               ; preds = %77, %73
  %79 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 4
  store ptr null, ptr %79, align 8, !tbaa !49
  br label %80

80:                                               ; preds = %78, %69
  br label %81

81:                                               ; preds = %80, %53
  %82 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 1
  %83 = load ptr, ptr %82, align 8, !tbaa !50
  %84 = icmp ne ptr %83, null
  br i1 %84, label %85, label %91

85:                                               ; preds = %81
  %86 = getelementptr inbounds %class.InstFetchU, ptr %4, i32 0, i32 1
  %87 = load ptr, ptr %86, align 8, !tbaa !50
  %88 = icmp eq ptr %87, null
  br i1 %88, label %90, label %89

89:                                               ; preds = %85
  call void @_ZN14McPATComponentD2Ev(ptr noundef nonnull align 8 dereferenceable(1784) %87) #3
  call void @_ZdlPvm(ptr noundef %87, i64 noundef 1784) #4
  br label %90

90:                                               ; preds = %89, %85
  br label %91

91:                                               ; preds = %90, %81
  store i32 0, ptr %3, align 4
  br label %92

92:                                               ; preds = %91, %8
  call void @_ZN14McPATComponentD2Ev(ptr noundef nonnull align 8 dereferenceable(1352) %4) #3
  %93 = load i32, ptr %3, align 4
  switch i32 %93, label %95 [
    i32 0, label %94
    i32 1, label %94
  ]

94:                                               ; preds = %92, %92
  ret void

95:                                               ; preds = %92
  unreachable
}

; Function Attrs: nounwind
declare void @_ZN7ArraySTD1Ev(ptr noundef nonnull align 8 dereferenceable(10104)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN14McPATComponentD2Ev(ptr noundef nonnull align 8 dereferenceable(1352)) unnamed_addr #2

declare void @_ZN15BranchPredictorD1Ev(ptr)

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !21, i64 2724}
!12 = !{!"_ZTS10InstFetchU", !13, i64 0, !6, i64 1352, !6, i64 1360, !6, i64 1368, !6, i64 1376, !6, i64 1384, !6, i64 1392, !6, i64 1400, !19, i64 1408, !33, i64 1776, !37, i64 2256, !38, i64 2648, !39, i64 2680, !16, i64 2696, !16, i64 2704, !16, i64 2712, !40, i64 2720, !21, i64 2724}
!13 = !{!"_ZTS14McPATComponent", !14, i64 8, !6, i64 288, !19, i64 296, !23, i64 664, !16, i64 696, !26, i64 704, !30, i64 728, !31, i64 776, !31, i64 944, !17, i64 1112, !17, i64 1232}
!14 = !{!"_ZTS9Component", !15, i64 0, !17, i64 24, !17, i64 144, !16, i64 264, !16, i64 272}
!15 = !{!"_ZTS4Area", !16, i64 0, !16, i64 8, !16, i64 16}
!16 = !{!"double", !7, i64 0}
!17 = !{!"_ZTS8powerDef", !18, i64 0, !18, i64 40, !18, i64 80}
!18 = !{!"_ZTS15powerComponents", !16, i64 0, !16, i64 8, !16, i64 16, !16, i64 24, !16, i64 32}
!19 = !{!"_ZTS14InputParameter", !20, i64 0, !20, i64 4, !20, i64 8, !20, i64 12, !20, i64 16, !21, i64 20, !20, i64 24, !20, i64 28, !20, i64 32, !20, i64 36, !20, i64 40, !20, i64 44, !16, i64 48, !16, i64 56, !20, i64 64, !20, i64 68, !20, i64 72, !20, i64 76, !20, i64 80, !21, i64 84, !21, i64 85, !21, i64 86, !21, i64 87, !21, i64 88, !20, i64 92, !20, i64 96, !20, i64 100, !20, i64 104, !20, i64 108, !20, i64 112, !20, i64 116, !20, i64 120, !20, i64 124, !20, i64 128, !20, i64 132, !20, i64 136, !20, i64 140, !20, i64 144, !20, i64 148, !22, i64 152, !20, i64 156, !21, i64 160, !20, i64 164, !20, i64 168, !20, i64 172, !20, i64 176, !20, i64 180, !20, i64 184, !20, i64 188, !21, i64 192, !20, i64 196, !20, i64 200, !20, i64 204, !20, i64 208, !20, i64 212, !20, i64 216, !20, i64 220, !20, i64 224, !20, i64 228, !20, i64 232, !20, i64 236, !20, i64 240, !20, i64 244, !20, i64 248, !20, i64 252, !20, i64 256, !20, i64 260, !20, i64 264, !20, i64 268, !20, i64 272, !20, i64 276, !20, i64 280, !20, i64 284, !20, i64 288, !20, i64 292, !20, i64 296, !21, i64 300, !20, i64 304, !20, i64 308, !20, i64 312, !21, i64 316, !21, i64 317, !20, i64 320, !20, i64 324, !21, i64 328, !16, i64 336, !16, i64 344, !21, i64 352, !20, i64 356, !20, i64 360, !21, i64 364}
!20 = !{!"int", !7, i64 0}
!21 = !{!"bool", !7, i64 0}
!22 = !{!"_ZTS9Wire_type", !7, i64 0}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSSt6vectorIP14McPATComponentSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIP14McPATComponentSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP14McPATComponentSaIS1_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP14McPATComponentSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTS11McPATOutput", !16, i64 0, !16, i64 8, !16, i64 16, !16, i64 24, !16, i64 32, !16, i64 40}
!31 = !{!"_ZTS8statsDef", !32, i64 0, !32, i64 24, !32, i64 48, !32, i64 72, !32, i64 96, !32, i64 120, !32, i64 144}
!32 = !{!"_ZTS15statsComponents", !16, i64 0, !16, i64 8, !16, i64 16}
!33 = !{!"_ZTS14CoreParameters", !21, i64 0, !21, i64 1, !21, i64 2, !34, i64 4, !35, i64 8, !36, i64 12, !16, i64 16, !20, i64 24, !20, i64 28, !20, i64 32, !20, i64 36, !20, i64 40, !20, i64 44, !20, i64 48, !20, i64 52, !20, i64 56, !20, i64 60, !20, i64 64, !20, i64 68, !20, i64 72, !20, i64 76, !20, i64 80, !20, i64 84, !20, i64 88, !20, i64 92, !20, i64 96, !20, i64 100, !20, i64 104, !20, i64 108, !20, i64 112, !20, i64 116, !20, i64 120, !20, i64 124, !20, i64 128, !20, i64 132, !20, i64 136, !20, i64 140, !20, i64 144, !20, i64 148, !16, i64 152, !20, i64 160, !20, i64 164, !20, i64 168, !20, i64 172, !21, i64 176, !21, i64 177, !7, i64 184, !20, i64 216, !20, i64 220, !20, i64 224, !20, i64 228, !20, i64 232, !20, i64 236, !20, i64 240, !16, i64 248, !16, i64 256, !20, i64 264, !20, i64 268, !20, i64 272, !20, i64 276, !20, i64 280, !20, i64 284, !20, i64 288, !20, i64 292, !20, i64 296, !20, i64 300, !20, i64 304, !20, i64 308, !20, i64 312, !20, i64 316, !20, i64 320, !20, i64 324, !20, i64 328, !20, i64 332, !20, i64 336, !20, i64 340, !20, i64 344, !20, i64 348, !20, i64 352, !20, i64 356, !20, i64 360, !20, i64 364, !20, i64 368, !20, i64 372, !20, i64 376, !20, i64 380, !20, i64 384, !20, i64 388, !20, i64 392, !20, i64 396, !20, i64 400, !20, i64 404, !20, i64 408, !20, i64 412, !20, i64 416, !20, i64 420, !22, i64 424, !22, i64 428, !20, i64 432, !16, i64 440, !16, i64 448, !20, i64 456, !16, i64 464, !16, i64 472}
!34 = !{!"_ZTS9Core_type", !7, i64 0}
!35 = !{!"_ZTS13Renaming_type", !7, i64 0}
!36 = !{!"_ZTS14Scheduler_type", !7, i64 0}
!37 = !{!"_ZTS14CoreStatistics", !16, i64 0, !16, i64 8, !16, i64 16, !16, i64 24, !16, i64 32, !16, i64 40, !16, i64 48, !16, i64 56, !16, i64 64, !16, i64 72, !16, i64 80, !16, i64 88, !16, i64 96, !16, i64 104, !16, i64 112, !16, i64 120, !16, i64 128, !16, i64 136, !16, i64 144, !16, i64 152, !16, i64 160, !16, i64 168, !16, i64 176, !16, i64 184, !16, i64 192, !16, i64 200, !16, i64 208, !16, i64 216, !16, i64 224, !16, i64 232, !16, i64 240, !16, i64 248, !16, i64 256, !16, i64 264, !16, i64 272, !16, i64 280, !16, i64 288, !16, i64 296, !16, i64 304, !16, i64 312, !16, i64 320, !16, i64 328, !16, i64 336, !16, i64 344, !16, i64 352, !16, i64 360, !16, i64 368, !16, i64 376, !16, i64 384}
!38 = !{!"_ZTS19InstFetchParameters", !20, i64 0, !20, i64 4, !20, i64 8, !20, i64 12, !20, i64 16, !20, i64 20, !20, i64 24}
!39 = !{!"_ZTS19InstFetchStatistics", !16, i64 0, !16, i64 8}
!40 = !{!"_ZTS12Cache_policy", !7, i64 0}
!41 = !{i8 0, i8 2}
!42 = !{}
!43 = !{!12, !6, i64 1360}
!44 = !{!12, !6, i64 1384}
!45 = !{!12, !6, i64 1392}
!46 = !{!12, !6, i64 1400}
!47 = !{!12, !20, i64 1864}
!48 = !{!12, !6, i64 1368}
!49 = !{!12, !6, i64 1376}
!50 = !{!12, !6, i64 1352}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV10InstFetchU = external dso_local unnamed_addr constant { [6 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN10InstFetchUD2Ev(ptr noundef nonnull align 8 dereferenceable(2725) %0) unnamed_addr #1 align 2 {
  store ptr getelementptr inbounds inrange(-16, 32) (i8, ptr @_ZTV10InstFetchU, i64 16), ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 2724
  %3 = load i8, ptr %2, align 4, !tbaa !8, !range !40, !noundef !41
  %4 = trunc nuw i8 %3 to i1
  br i1 %4, label %5, label %37

5:                                                ; preds = %1
  %6 = getelementptr inbounds i8, ptr %0, i64 1360
  %7 = load ptr, ptr %6, align 8, !tbaa !42
  %.not = icmp eq ptr %7, null
  br i1 %.not, label %9, label %8

8:                                                ; preds = %5
  tail call void @_ZN7ArraySTD1Ev(ptr noundef nonnull align 8 dereferenceable(10104) %7) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %7, i64 noundef 10104) #4
  store ptr null, ptr %6, align 8, !tbaa !42
  br label %9

9:                                                ; preds = %8, %5
  %10 = getelementptr inbounds i8, ptr %0, i64 1384
  %11 = load ptr, ptr %10, align 8, !tbaa !43
  %.not7 = icmp eq ptr %11, null
  br i1 %.not7, label %13, label %12

12:                                               ; preds = %9
  tail call void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136) %11) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %11, i64 noundef 10136) #4
  store ptr null, ptr %10, align 8, !tbaa !43
  br label %13

13:                                               ; preds = %12, %9
  %14 = getelementptr inbounds i8, ptr %0, i64 1392
  %15 = load ptr, ptr %14, align 8, !tbaa !44
  %.not8 = icmp eq ptr %15, null
  br i1 %.not8, label %17, label %16

16:                                               ; preds = %13
  tail call void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136) %15) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %15, i64 noundef 10136) #4
  store ptr null, ptr %14, align 8, !tbaa !44
  br label %17

17:                                               ; preds = %16, %13
  %18 = getelementptr inbounds i8, ptr %0, i64 1400
  %19 = load ptr, ptr %18, align 8, !tbaa !45
  %.not9 = icmp eq ptr %19, null
  br i1 %.not9, label %21, label %20

20:                                               ; preds = %17
  tail call void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136) %19) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %19, i64 noundef 10136) #4
  store ptr null, ptr %18, align 8, !tbaa !45
  br label %21

21:                                               ; preds = %20, %17
  %22 = getelementptr inbounds i8, ptr %0, i64 1864
  %23 = load i32, ptr %22, align 8, !tbaa !46
  %24 = icmp sgt i32 %23, 0
  br i1 %24, label %25, label %33

25:                                               ; preds = %21
  %26 = getelementptr inbounds i8, ptr %0, i64 1368
  %27 = load ptr, ptr %26, align 8, !tbaa !47
  %.not10 = icmp eq ptr %27, null
  br i1 %.not10, label %29, label %28

28:                                               ; preds = %25
  tail call void @_ZN7ArraySTD1Ev(ptr noundef nonnull align 8 dereferenceable(10104) %27) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %27, i64 noundef 10104) #4
  store ptr null, ptr %26, align 8, !tbaa !47
  br label %29

29:                                               ; preds = %28, %25
  %30 = getelementptr inbounds i8, ptr %0, i64 1376
  %31 = load ptr, ptr %30, align 8, !tbaa !48
  %.not11 = icmp eq ptr %31, null
  br i1 %.not11, label %33, label %32

32:                                               ; preds = %29
  tail call void @_ZN15BranchPredictorD1Ev(ptr noundef nonnull align 8 dereferenceable(2705) %31) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %31, i64 noundef 2712) #4
  store ptr null, ptr %30, align 8, !tbaa !48
  br label %33

33:                                               ; preds = %29, %32, %21
  %34 = getelementptr inbounds i8, ptr %0, i64 1352
  %35 = load ptr, ptr %34, align 8, !tbaa !49
  %.not12 = icmp eq ptr %35, null
  br i1 %.not12, label %37, label %36

36:                                               ; preds = %33
  tail call void @_ZN14McPATComponentD2Ev(ptr noundef nonnull align 8 dereferenceable(1784) %35) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %35, i64 noundef 1784) #4
  br label %37

37:                                               ; preds = %33, %36, %1
  tail call void @_ZN14McPATComponentD2Ev(ptr noundef nonnull align 8 dereferenceable(1352) %0) #3
  ret void
}

; Function Attrs: nounwind
declare void @_ZN7ArraySTD1Ev(ptr noundef nonnull align 8 dereferenceable(10104)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN18InstructionDecoderD1Ev(ptr noundef nonnull align 8 dereferenceable(10136)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN14McPATComponentD2Ev(ptr noundef nonnull align 8 dereferenceable(1352)) unnamed_addr #2

declare void @_ZN15BranchPredictorD1Ev(ptr) local_unnamed_addr

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !20, i64 2724}
!9 = !{!"_ZTS10InstFetchU", !10, i64 0, !17, i64 1352, !17, i64 1360, !17, i64 1368, !17, i64 1376, !17, i64 1384, !17, i64 1392, !17, i64 1400, !18, i64 1408, !32, i64 1776, !36, i64 2256, !37, i64 2648, !38, i64 2680, !13, i64 2696, !13, i64 2704, !13, i64 2712, !39, i64 2720, !20, i64 2724}
!10 = !{!"_ZTS14McPATComponent", !11, i64 8, !17, i64 288, !18, i64 296, !22, i64 664, !13, i64 696, !25, i64 704, !29, i64 728, !30, i64 776, !30, i64 944, !15, i64 1112, !15, i64 1232}
!11 = !{!"_ZTS9Component", !12, i64 0, !15, i64 24, !15, i64 144, !13, i64 264, !13, i64 272}
!12 = !{!"_ZTS4Area", !13, i64 0, !13, i64 8, !13, i64 16}
!13 = !{!"double", !14, i64 0}
!14 = !{!"omnipotent char", !7, i64 0}
!15 = !{!"_ZTS8powerDef", !16, i64 0, !16, i64 40, !16, i64 80}
!16 = !{!"_ZTS15powerComponents", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32}
!17 = !{!"any pointer", !14, i64 0}
!18 = !{!"_ZTS14InputParameter", !19, i64 0, !19, i64 4, !19, i64 8, !19, i64 12, !19, i64 16, !20, i64 20, !19, i64 24, !19, i64 28, !19, i64 32, !19, i64 36, !19, i64 40, !19, i64 44, !13, i64 48, !13, i64 56, !19, i64 64, !19, i64 68, !19, i64 72, !19, i64 76, !19, i64 80, !20, i64 84, !20, i64 85, !20, i64 86, !20, i64 87, !20, i64 88, !19, i64 92, !19, i64 96, !19, i64 100, !19, i64 104, !19, i64 108, !19, i64 112, !19, i64 116, !19, i64 120, !19, i64 124, !19, i64 128, !19, i64 132, !19, i64 136, !19, i64 140, !19, i64 144, !19, i64 148, !21, i64 152, !19, i64 156, !20, i64 160, !19, i64 164, !19, i64 168, !19, i64 172, !19, i64 176, !19, i64 180, !19, i64 184, !19, i64 188, !20, i64 192, !19, i64 196, !19, i64 200, !19, i64 204, !19, i64 208, !19, i64 212, !19, i64 216, !19, i64 220, !19, i64 224, !19, i64 228, !19, i64 232, !19, i64 236, !19, i64 240, !19, i64 244, !19, i64 248, !19, i64 252, !19, i64 256, !19, i64 260, !19, i64 264, !19, i64 268, !19, i64 272, !19, i64 276, !19, i64 280, !19, i64 284, !19, i64 288, !19, i64 292, !19, i64 296, !20, i64 300, !19, i64 304, !19, i64 308, !19, i64 312, !20, i64 316, !20, i64 317, !19, i64 320, !19, i64 324, !20, i64 328, !13, i64 336, !13, i64 344, !20, i64 352, !19, i64 356, !19, i64 360, !20, i64 364}
!19 = !{!"int", !14, i64 0}
!20 = !{!"bool", !14, i64 0}
!21 = !{!"_ZTS9Wire_type", !14, i64 0}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !14, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !17, i64 0}
!24 = !{!"long", !14, i64 0}
!25 = !{!"_ZTSSt6vectorIP14McPATComponentSaIS1_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIP14McPATComponentSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIP14McPATComponentSaIS1_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP14McPATComponentSaIS1_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!29 = !{!"_ZTS11McPATOutput", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40}
!30 = !{!"_ZTS8statsDef", !31, i64 0, !31, i64 24, !31, i64 48, !31, i64 72, !31, i64 96, !31, i64 120, !31, i64 144}
!31 = !{!"_ZTS15statsComponents", !13, i64 0, !13, i64 8, !13, i64 16}
!32 = !{!"_ZTS14CoreParameters", !20, i64 0, !20, i64 1, !20, i64 2, !33, i64 4, !34, i64 8, !35, i64 12, !13, i64 16, !19, i64 24, !19, i64 28, !19, i64 32, !19, i64 36, !19, i64 40, !19, i64 44, !19, i64 48, !19, i64 52, !19, i64 56, !19, i64 60, !19, i64 64, !19, i64 68, !19, i64 72, !19, i64 76, !19, i64 80, !19, i64 84, !19, i64 88, !19, i64 92, !19, i64 96, !19, i64 100, !19, i64 104, !19, i64 108, !19, i64 112, !19, i64 116, !19, i64 120, !19, i64 124, !19, i64 128, !19, i64 132, !19, i64 136, !19, i64 140, !19, i64 144, !19, i64 148, !13, i64 152, !19, i64 160, !19, i64 164, !19, i64 168, !19, i64 172, !20, i64 176, !20, i64 177, !14, i64 184, !19, i64 216, !19, i64 220, !19, i64 224, !19, i64 228, !19, i64 232, !19, i64 236, !19, i64 240, !13, i64 248, !13, i64 256, !19, i64 264, !19, i64 268, !19, i64 272, !19, i64 276, !19, i64 280, !19, i64 284, !19, i64 288, !19, i64 292, !19, i64 296, !19, i64 300, !19, i64 304, !19, i64 308, !19, i64 312, !19, i64 316, !19, i64 320, !19, i64 324, !19, i64 328, !19, i64 332, !19, i64 336, !19, i64 340, !19, i64 344, !19, i64 348, !19, i64 352, !19, i64 356, !19, i64 360, !19, i64 364, !19, i64 368, !19, i64 372, !19, i64 376, !19, i64 380, !19, i64 384, !19, i64 388, !19, i64 392, !19, i64 396, !19, i64 400, !19, i64 404, !19, i64 408, !19, i64 412, !19, i64 416, !19, i64 420, !21, i64 424, !21, i64 428, !19, i64 432, !13, i64 440, !13, i64 448, !19, i64 456, !13, i64 464, !13, i64 472}
!33 = !{!"_ZTS9Core_type", !14, i64 0}
!34 = !{!"_ZTS13Renaming_type", !14, i64 0}
!35 = !{!"_ZTS14Scheduler_type", !14, i64 0}
!36 = !{!"_ZTS14CoreStatistics", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !13, i64 56, !13, i64 64, !13, i64 72, !13, i64 80, !13, i64 88, !13, i64 96, !13, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !13, i64 136, !13, i64 144, !13, i64 152, !13, i64 160, !13, i64 168, !13, i64 176, !13, i64 184, !13, i64 192, !13, i64 200, !13, i64 208, !13, i64 216, !13, i64 224, !13, i64 232, !13, i64 240, !13, i64 248, !13, i64 256, !13, i64 264, !13, i64 272, !13, i64 280, !13, i64 288, !13, i64 296, !13, i64 304, !13, i64 312, !13, i64 320, !13, i64 328, !13, i64 336, !13, i64 344, !13, i64 352, !13, i64 360, !13, i64 368, !13, i64 376, !13, i64 384}
!37 = !{!"_ZTS19InstFetchParameters", !19, i64 0, !19, i64 4, !19, i64 8, !19, i64 12, !19, i64 16, !19, i64 20, !19, i64 24}
!38 = !{!"_ZTS19InstFetchStatistics", !13, i64 0, !13, i64 8}
!39 = !{!"_ZTS12Cache_policy", !14, i64 0}
!40 = !{i8 0, i8 2}
!41 = !{}
!42 = !{!9, !17, i64 1360}
!43 = !{!9, !17, i64 1384}
!44 = !{!9, !17, i64 1392}
!45 = !{!9, !17, i64 1400}
!46 = !{!9, !19, i64 1864}
!47 = !{!9, !17, i64 1368}
!48 = !{!9, !17, i64 1376}
!49 = !{!9, !17, i64 1352}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass