; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/gnats/pr-134/pr-134.ll (ZN4arst5entryEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xyz = type { i8, i8 }
%struct.arst = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4arst5entryEv(ptr noundef nonnull align 8 dereferenceable(432) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca [8 x %struct.xyz], align 16
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 16, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #2
  store i8 0, ptr %4, align 1, !tbaa !9
  br label %7

7:                                                ; preds = %21, %1
  %8 = load i8, ptr %4, align 1, !tbaa !9
  %9 = sext i8 %8 to i32
  %10 = icmp slt i32 %9, 8
  br i1 %10, label %12, label %11

11:                                               ; preds = %7
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #2
  br label %24

12:                                               ; preds = %7
  %13 = getelementptr inbounds %struct.arst, ptr %6, i32 0, i32 2
  %14 = load ptr, ptr %13, align 8, !tbaa !10
  %15 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %14)
  %16 = load i8, ptr %15, align 1, !tbaa !9
  %17 = load i8, ptr %4, align 1, !tbaa !9
  %18 = sext i8 %17 to i64
  %19 = getelementptr inbounds [8 x %struct.xyz], ptr %3, i64 0, i64 %18
  %20 = getelementptr inbounds %struct.xyz, ptr %19, i32 0, i32 0
  store i8 %16, ptr %20, align 2, !tbaa !42
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %21

21:                                               ; preds = %12
  %22 = load i8, ptr %4, align 1, !tbaa !9
  %23 = add i8 %22, 1
  store i8 %23, ptr %4, align 1, !tbaa !9
  br label %7, !llvm.loop !44

24:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %25

25:                                               ; preds = %38, %24
  %26 = load i8, ptr %5, align 1, !tbaa !9
  %27 = sext i8 %26 to i32
  %28 = icmp slt i32 %27, 8
  br i1 %28, label %30, label %29

29:                                               ; preds = %25
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  br label %41

30:                                               ; preds = %25
  %31 = load i8, ptr %5, align 1, !tbaa !9
  %32 = sext i8 %31 to i64
  %33 = getelementptr inbounds [8 x %struct.xyz], ptr %3, i64 0, i64 %32
  %34 = getelementptr inbounds %struct.xyz, ptr %33, i32 0, i32 0
  %35 = getelementptr inbounds %struct.arst, ptr %6, i32 0, i32 3
  %36 = load ptr, ptr %35, align 8, !tbaa !46
  %37 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %36, ptr noundef nonnull align 1 dereferenceable(1) %34)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %38

38:                                               ; preds = %30
  %39 = load i8, ptr %5, align 1, !tbaa !9
  %40 = add i8 %39, 1
  store i8 %40, ptr %5, align 1, !tbaa !9
  br label %25, !llvm.loop !47

41:                                               ; preds = %29
  call void @llvm.lifetime.end.p0(i64 16, ptr %3) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !6, i64 416}
!11 = !{!"_ZTS4arst", !12, i64 0, !34, i64 232, !6, i64 416, !6, i64 424}
!12 = !{!"_ZTSN7sc_core9sc_moduleE", !13, i64 0, !25, i64 112, !26, i64 120, !28, i64 144, !30, i64 168, !32, i64 192, !6, i64 200, !33, i64 208, !6, i64 216, !6, i64 224}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !6, i64 96, !6, i64 104}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !27, i64 8, !6, i64 16}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !29, i64 8, !6, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !31, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!32 = !{!"bool", !7, i64 0}
!33 = !{!"int", !7, i64 0}
!34 = !{!"_ZTSN7sc_core5sc_inIbEE", !35, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!35 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !36, i64 0}
!36 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !37, i64 0, !6, i64 120, !38, i64 128}
!37 = !{!"_ZTSN7sc_core12sc_port_baseE", !13, i64 0, !6, i64 112}
!38 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!43, !7, i64 0}
!43 = !{!"_ZTS3xyz", !7, i64 0, !7, i64 1}
!44 = distinct !{!44, !45}
!45 = !{!"llvm.loop.mustprogress"}
!46 = !{!11, !6, i64 424}
!47 = distinct !{!47, !45}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xyz = type { i8, i8 }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4arst5entryEv(ptr noundef nonnull align 8 dereferenceable(432) %0) local_unnamed_addr #0 align 2 {
.preheader:
  %1 = alloca [8 x %struct.xyz], align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %1) #2
  %2 = getelementptr inbounds i8, ptr %0, i64 416
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %4 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %3)
  %5 = load i8, ptr %4, align 1, !tbaa !40
  store i8 %5, ptr %1, align 16, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %6 = load ptr, ptr %2, align 8, !tbaa !5
  %7 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %6)
  %8 = load i8, ptr %7, align 1, !tbaa !40
  %9 = getelementptr inbounds i8, ptr %1, i64 2
  store i8 %8, ptr %9, align 2, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %10)
  %12 = load i8, ptr %11, align 1, !tbaa !40
  %13 = getelementptr inbounds i8, ptr %1, i64 4
  store i8 %12, ptr %13, align 4, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %14 = load ptr, ptr %2, align 8, !tbaa !5
  %15 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %14)
  %16 = load i8, ptr %15, align 1, !tbaa !40
  %17 = getelementptr inbounds i8, ptr %1, i64 6
  store i8 %16, ptr %17, align 2, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %18 = load ptr, ptr %2, align 8, !tbaa !5
  %19 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %18)
  %20 = load i8, ptr %19, align 1, !tbaa !40
  %21 = getelementptr inbounds i8, ptr %1, i64 8
  store i8 %20, ptr %21, align 8, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %22 = load ptr, ptr %2, align 8, !tbaa !5
  %23 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %22)
  %24 = load i8, ptr %23, align 1, !tbaa !40
  %25 = getelementptr inbounds i8, ptr %1, i64 10
  store i8 %24, ptr %25, align 2, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %26 = load ptr, ptr %2, align 8, !tbaa !5
  %27 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %26)
  %28 = load i8, ptr %27, align 1, !tbaa !40
  %29 = getelementptr inbounds i8, ptr %1, i64 12
  store i8 %28, ptr %29, align 4, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %30 = load ptr, ptr %2, align 8, !tbaa !5
  %31 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193) %30)
  %32 = load i8, ptr %31, align 1, !tbaa !40
  %33 = getelementptr inbounds i8, ptr %1, i64 14
  store i8 %32, ptr %33, align 2, !tbaa !41
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %34 = getelementptr inbounds i8, ptr %0, i64 424
  %35 = load ptr, ptr %34, align 8, !tbaa !43
  %36 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %35, ptr noundef nonnull align 1 dereferenceable(1) %1)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %37 = load ptr, ptr %34, align 8, !tbaa !43
  %38 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %37, ptr noundef nonnull align 1 dereferenceable(1) %9)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %39 = load ptr, ptr %34, align 8, !tbaa !43
  %40 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %39, ptr noundef nonnull align 1 dereferenceable(1) %13)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %41 = load ptr, ptr %34, align 8, !tbaa !43
  %42 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %41, ptr noundef nonnull align 1 dereferenceable(1) %17)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %43 = load ptr, ptr %34, align 8, !tbaa !43
  %44 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %43, ptr noundef nonnull align 1 dereferenceable(1) %21)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %45 = load ptr, ptr %34, align 8, !tbaa !43
  %46 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %45, ptr noundef nonnull align 1 dereferenceable(1) %25)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %47 = load ptr, ptr %34, align 8, !tbaa !43
  %48 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %47, ptr noundef nonnull align 1 dereferenceable(1) %29)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %49 = load ptr, ptr %34, align 8, !tbaa !43
  %50 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %49, ptr noundef nonnull align 1 dereferenceable(1) %33)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %1) #2
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEcvRKcEv(ptr noundef nonnull align 8 dereferenceable(193)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 416}
!6 = !{!"_ZTS4arst", !7, i64 0, !32, i64 232, !9, i64 416, !9, i64 424}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core5sc_inIbEE", !33, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!33 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !35, i64 0, !9, i64 120, !36, i64 128}
!35 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!36 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!40 = !{!10, !10, i64 0}
!41 = !{!42, !10, i64 0}
!42 = !{!"_ZTS3xyz", !10, i64 0, !10, i64 1}
!43 = !{!6, !9, i64 424}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass