; LLVM IR from hoodoer/ENNEoS :: enneosEncoder/genotype.ll (ZN7CGenomeC2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.CGenome = type <{ i32, [4 x i8], %"class.std::vector", %"class.std::vector.0", ptr, i32, [4 x i8], double, double, double, i32, i32, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl" }
%"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl" = type { %"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SNeuronGene, std::allocator<SNeuronGene>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl" }
%"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl" = type { %"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SLinkGene, std::allocator<SLinkGene>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7CGenomeC2Ev(ptr noundef nonnull align 8 dereferenceable(108) %0) unnamed_addr #0 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  %4 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 0
  store i32 0, ptr %4, align 8, !tbaa !9
  %5 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 2
  call void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #1
  %6 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 3
  call void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #1
  %7 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 4
  store ptr null, ptr %7, align 8, !tbaa !21
  %8 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 5
  store i32 -1, ptr %8, align 8, !tbaa !22
  %9 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 7
  store double 0.000000e+00, ptr %9, align 8, !tbaa !23
  %10 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 8
  store double 0.000000e+00, ptr %10, align 8, !tbaa !24
  %11 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 9
  store double 0.000000e+00, ptr %11, align 8, !tbaa !25
  %12 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 10
  store i32 0, ptr %12, align 8, !tbaa !26
  %13 = getelementptr inbounds %class.CGenome, ptr %3, i32 0, i32 11
  store i32 0, ptr %13, align 4, !tbaa !27
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS7CGenome", !11, i64 0, !12, i64 8, !16, i64 32, !6, i64 56, !11, i64 64, !20, i64 72, !20, i64 80, !20, i64 88, !11, i64 96, !11, i64 100, !11, i64 104}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorI11SNeuronGeneSaIS0_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseI11SNeuronGeneSaIS0_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!"_ZTSSt6vectorI9SLinkGeneSaIS0_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseI9SLinkGeneSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"double", !7, i64 0}
!21 = !{!10, !6, i64 56}
!22 = !{!10, !11, i64 64}
!23 = !{!10, !20, i64 72}
!24 = !{!10, !20, i64 80}
!25 = !{!10, !20, i64 88}
!26 = !{!10, !11, i64 96}
!27 = !{!10, !11, i64 100}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7CGenomeC2Ev(ptr noundef nonnull align 8 dereferenceable(108) %0) unnamed_addr #0 align 2 {
  store i32 0, ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 8
  tail call void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #2
  %3 = getelementptr inbounds i8, ptr %0, i64 32
  tail call void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %4 = getelementptr inbounds i8, ptr %0, i64 56
  store ptr null, ptr %4, align 8, !tbaa !20
  %5 = getelementptr inbounds i8, ptr %0, i64 64
  store i32 -1, ptr %5, align 8, !tbaa !21
  %6 = getelementptr inbounds i8, ptr %0, i64 72
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %6, i8 0, i64 32, i1 false)
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SNeuronGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI9SLinkGeneSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS7CGenome", !7, i64 0, !10, i64 8, !15, i64 32, !14, i64 56, !7, i64 64, !19, i64 72, !19, i64 80, !19, i64 88, !7, i64 96, !7, i64 100, !7, i64 104}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorI11SNeuronGeneSaIS0_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseI11SNeuronGeneSaIS0_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseI11SNeuronGeneSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"_ZTSSt6vectorI9SLinkGeneSaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseI9SLinkGeneSaIS0_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseI9SLinkGeneSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!19 = !{!"double", !8, i64 0}
!20 = !{!6, !14, i64 56}
!21 = !{!6, !7, i64 64}


; Effective O3 passes: EarlyCSEPass,InstCombinePass,MemCpyOptPass,SROAPass,TailCallElimPass