; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_signal_ports)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_inout.41" = type { %"class.sc_core::sc_port.34", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.34" = type { %"class.sc_core::sc_port_b.35" }
%"class.sc_core::sc_port_b.35" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.36" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.36" = type { %"struct.std::_Vector_base.37" }
%"struct.std::_Vector_base.37" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.sc_core::sc_trace_params" = type { ptr, %"class.std::__cxx11::basic_string" }

@_ZTIN7sc_core12sc_interfaceE = external constant ptr
@_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE = external dso_local constant { ptr, ptr, i32, i32, ptr, i64 }, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32)) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicdlEPvm(ptr noundef, i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNK7sc_core8sc_inoutIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(192)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE18end_of_elaborationEv(ptr noundef nonnull align 8 dereferenceable(192) %0) unnamed_addr #4 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8
  %7 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 1
  %8 = load ptr, ptr %7, align 8, !tbaa !9
  %9 = icmp ne ptr %8, null
  br i1 %9, label %10, label %19

10:                                               ; preds = %1
  %11 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 1
  %12 = load ptr, ptr %11, align 8, !tbaa !9
  call void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE5writeERKS2_(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 4 dereferenceable(4) %12)
  %13 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 1
  %14 = load ptr, ptr %13, align 8, !tbaa !9
  %15 = icmp eq ptr %14, null
  br i1 %15, label %17, label %16

16:                                               ; preds = %10
  call void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4) %14) #5
  call void @_ZN5sc_dt8sc_logicdlEPvm(ptr noundef %14, i64 noundef 4) #5
  br label %17

17:                                               ; preds = %16, %10
  %18 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 1
  store ptr null, ptr %18, align 8, !tbaa !9
  br label %19

19:                                               ; preds = %17, %1
  %20 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 2
  %21 = load ptr, ptr %20, align 8, !tbaa !30
  %22 = icmp ne ptr %21, null
  br i1 %22, label %23, label %63

23:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  store i32 0, ptr %3, align 4, !tbaa !31
  br label %24

24:                                               ; preds = %59, %23
  %25 = load i32, ptr %3, align 4, !tbaa !31
  %26 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 2
  %27 = load ptr, ptr %26, align 8, !tbaa !30
  %28 = call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %27) #5
  %29 = trunc i64 %28 to i32
  %30 = icmp slt i32 %25, %29
  br i1 %30, label %32, label %31

31:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  br label %62

32:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #5
  %33 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %6, i32 0, i32 2
  %34 = load ptr, ptr %33, align 8, !tbaa !30
  %35 = load i32, ptr %3, align 4, !tbaa !31
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36) #5
  %38 = load ptr, ptr %37, align 8, !tbaa !5
  store ptr %38, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  %39 = load ptr, ptr %6, align 8, !tbaa !33
  %40 = getelementptr inbounds ptr, ptr %39, i64 15
  %41 = load ptr, ptr %40, align 8
  %42 = call noundef ptr %41(ptr noundef nonnull align 8 dereferenceable(152) %6)
  %43 = icmp eq ptr %42, null
  br i1 %43, label %46, label %44

44:                                               ; preds = %32
  %45 = call ptr @__dynamic_cast(ptr %42, ptr @_ZTIN7sc_core12sc_interfaceE, ptr @_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE, i64 -1) #5
  br label %47

46:                                               ; preds = %32
  br label %47

47:                                               ; preds = %46, %44
  %48 = phi ptr [ %45, %44 ], [ null, %46 ]
  store ptr %48, ptr %5, align 8, !tbaa !5
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = getelementptr inbounds %"struct.sc_core::sc_trace_params", ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !35
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = load ptr, ptr %52, align 8, !tbaa !33
  %54 = getelementptr inbounds ptr, ptr %53, i64 7
  %55 = load ptr, ptr %54, align 8
  %56 = call noundef nonnull align 4 dereferenceable(4) ptr %55(ptr noundef nonnull align 8 dereferenceable(8) %52)
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = getelementptr inbounds %"struct.sc_core::sc_trace_params", ptr %57, i32 0, i32 1
  call void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef %51, ptr noundef nonnull align 4 dereferenceable(4) %56, ptr noundef nonnull align 8 dereferenceable(32) %58)
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #5
  br label %59

59:                                               ; preds = %47
  %60 = load i32, ptr %3, align 4, !tbaa !31
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %3, align 4, !tbaa !31
  br label %24, !llvm.loop !37

62:                                               ; preds = %31
  call void @_ZNK7sc_core8sc_inoutIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(192) %6)
  br label %63

63:                                               ; preds = %62, %19
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE5writeERKS2_(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 4 dereferenceable(4)) #4 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind willreturn memory(read) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 152}
!10 = !{!"_ZTSN7sc_core8sc_inoutIN5sc_dt8sc_logicEEE", !11, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176, !6, i64 184}
!11 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !12, i64 0}
!12 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEEEE", !13, i64 0, !6, i64 120, !26, i64 128}
!13 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !6, i64 112}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !6, i64 96, !6, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!10, !6, i64 160}
!31 = !{!32, !32, i64 0}
!32 = !{!"int", !7, i64 0}
!33 = !{!34, !34, i64 0}
!34 = !{!"vtable pointer", !8, i64 0}
!35 = !{!36, !6, i64 0}
!36 = !{!"_ZTSN7sc_core15sc_trace_paramsE", !6, i64 0, !23, i64 8}
!37 = distinct !{!37, !38}
!38 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN7sc_core12sc_interfaceE = external constant ptr
@_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE = external dso_local constant { ptr, ptr, i32, i32, ptr, i64 }, align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nofree nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) local_unnamed_addr #1

declare void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicdlEPvm(ptr noundef, i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNK7sc_core8sc_inoutIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(192)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE18end_of_elaborationEv(ptr noundef nonnull align 8 dereferenceable(192) %0) unnamed_addr #3 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 152
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %9, label %4

4:                                                ; preds = %1
  tail call void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE5writeERKS2_(ptr noundef nonnull align 8 dereferenceable(192) %0, ptr noundef nonnull align 4 dereferenceable(4) %3)
  %5 = load ptr, ptr %2, align 8, !tbaa !5
  %6 = icmp eq ptr %5, null
  br i1 %6, label %8, label %7

7:                                                ; preds = %4
  tail call void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4) %5) #5
  tail call void @_ZN5sc_dt8sc_logicdlEPvm(ptr noundef nonnull %5, i64 noundef 4) #5
  br label %8

8:                                                ; preds = %7, %4
  store ptr null, ptr %2, align 8, !tbaa !5
  br label %9

9:                                                ; preds = %8, %1
  %10 = getelementptr inbounds i8, ptr %0, i64 160
  %11 = load ptr, ptr %10, align 8, !tbaa !29
  %.not9 = icmp eq ptr %11, null
  br i1 %.not9, label %34, label %.preheader

.preheader:                                       ; preds = %9
  %12 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11) #5
  %13 = trunc i64 %12 to i32
  %14 = icmp sgt i32 %13, 0
  br i1 %14, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  tail call void @_ZNK7sc_core8sc_inoutIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(192) %0)
  br label %34

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.preheader ]
  %15 = load ptr, ptr %10, align 8, !tbaa !29
  %16 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %indvars.iv) #5
  %17 = load ptr, ptr %16, align 8, !tbaa !30
  %18 = load ptr, ptr %0, align 8, !tbaa !31
  %19 = getelementptr inbounds i8, ptr %18, i64 120
  %20 = load ptr, ptr %19, align 8
  %21 = tail call noundef ptr %20(ptr noundef nonnull align 8 dereferenceable(152) %0)
  %22 = icmp ne ptr %21, null
  tail call void @llvm.assume(i1 %22)
  %23 = tail call ptr @__dynamic_cast(ptr nonnull %21, ptr nonnull @_ZTIN7sc_core12sc_interfaceE, ptr nonnull @_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE, i64 -1) #5
  %24 = load ptr, ptr %17, align 8, !tbaa !33
  %25 = load ptr, ptr %23, align 8, !tbaa !31
  %26 = getelementptr inbounds i8, ptr %25, i64 56
  %27 = load ptr, ptr %26, align 8
  %28 = tail call noundef nonnull align 4 dereferenceable(4) ptr %27(ptr noundef nonnull align 8 dereferenceable(8) %23)
  %29 = getelementptr inbounds i8, ptr %17, i64 8
  tail call void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef %24, ptr noundef nonnull align 4 dereferenceable(4) %28, ptr noundef nonnull align 8 dereferenceable(32) %29)
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %30 = load ptr, ptr %10, align 8, !tbaa !29
  %31 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %30) #5
  %sext = shl i64 %31, 32
  %32 = ashr exact i64 %sext, 32
  %33 = icmp slt i64 %indvars.iv.next, %32
  br i1 %33, label %.lr.ph, label %._crit_edge, !llvm.loop !35

34:                                               ; preds = %._crit_edge, %9
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE5writeERKS2_(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
declare void @llvm.assume(i1 noundef) #4

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nofree nounwind willreturn memory(read) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 152}
!6 = !{!"_ZTSN7sc_core8sc_inoutIN5sc_dt8sc_logicEEE", !7, i64 0, !11, i64 152, !11, i64 160, !11, i64 168, !11, i64 176, !11, i64 184}
!7 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !8, i64 0}
!8 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEEEE", !9, i64 0, !11, i64 120, !25, i64 128}
!9 = !{!"_ZTSN7sc_core12sc_port_baseE", !10, i64 0, !11, i64 112}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !12, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!24 = !{!"long", !12, i64 0}
!25 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!29 = !{!6, !11, i64 160}
!30 = !{!11, !11, i64 0}
!31 = !{!32, !32, i64 0}
!32 = !{!"vtable pointer", !13, i64 0}
!33 = !{!34, !11, i64 0}
!34 = !{!"_ZTSN7sc_core15sc_trace_paramsE", !11, i64 0, !22, i64 8}
!35 = distinct !{!35, !36}
!36 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass