; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/utils/sc_hash.ll (ZN7sc_core13sc_phash_base18remove_by_contentsEPKv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_phash_base" = type { ptr, i32, i32, i32, i32, double, ptr, ptr, ptr }
%"class.sc_core::sc_phash_elem" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef, i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN7sc_core13sc_phash_base18remove_by_contentsEPKv(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef %1) #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %9 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store i32 0, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %10

10:                                               ; preds = %56, %2
  %11 = load i32, ptr %8, align 4, !tbaa !9
  %12 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %9, i32 0, i32 1
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp slt i32 %11, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %10
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  br label %59

16:                                               ; preds = %10
  %17 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %9, i32 0, i32 6
  %18 = load ptr, ptr %17, align 8, !tbaa !14
  %19 = load i32, ptr %8, align 4, !tbaa !9
  %20 = sext i32 %19 to i64
  %21 = getelementptr inbounds ptr, ptr %18, i64 %20
  store ptr %21, ptr %5, align 8, !tbaa !5
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = load ptr, ptr %22, align 8, !tbaa !5
  store ptr %23, ptr %6, align 8, !tbaa !5
  br label %24

24:                                               ; preds = %54, %16
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = icmp ne ptr %25, null
  br i1 %26, label %27, label %55

27:                                               ; preds = %24
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %28, i32 0, i32 1
  %30 = load ptr, ptr %29, align 8, !tbaa !15
  %31 = load ptr, ptr %4, align 8, !tbaa !5
  %32 = icmp ne ptr %30, %31
  br i1 %32, label %33, label %38

33:                                               ; preds = %27
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %34, i32 0, i32 2
  store ptr %35, ptr %5, align 8, !tbaa !5
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = load ptr, ptr %36, align 8, !tbaa !5
  store ptr %37, ptr %6, align 8, !tbaa !5
  br label %54

38:                                               ; preds = %27
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %39, i32 0, i32 2
  %41 = load ptr, ptr %40, align 8, !tbaa !17
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %41, ptr %42, align 8, !tbaa !5
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = icmp eq ptr %43, null
  br i1 %44, label %46, label %45

45:                                               ; preds = %38
  call void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %43) #2
  call void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef %43, i64 noundef 24) #2
  br label %46

46:                                               ; preds = %45, %38
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = load ptr, ptr %47, align 8, !tbaa !5
  store ptr %48, ptr %6, align 8, !tbaa !5
  %49 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %9, i32 0, i32 2
  %50 = load i32, ptr %49, align 4, !tbaa !18
  %51 = add nsw i32 %50, -1
  store i32 %51, ptr %49, align 4, !tbaa !18
  %52 = load i32, ptr %7, align 4, !tbaa !9
  %53 = add nsw i32 %52, 1
  store i32 %53, ptr %7, align 4, !tbaa !9
  br label %54

54:                                               ; preds = %46, %33
  br label %24, !llvm.loop !19

55:                                               ; preds = %24
  br label %56

56:                                               ; preds = %55
  %57 = load i32, ptr %8, align 4, !tbaa !9
  %58 = add nsw i32 %57, 1
  store i32 %58, ptr %8, align 4, !tbaa !9
  br label %10, !llvm.loop !21

59:                                               ; preds = %15
  %60 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #2
  ret i32 %60
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"_ZTSN7sc_core13sc_phash_baseE", !6, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !13, i64 24, !6, i64 32, !6, i64 40, !6, i64 48}
!13 = !{!"double", !7, i64 0}
!14 = !{!12, !6, i64 32}
!15 = !{!16, !6, i64 8}
!16 = !{!"_ZTSN7sc_core13sc_phash_elemE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!16, !6, i64 16}
!18 = !{!12, !10, i64 12}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = distinct !{!21, !20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef, i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN7sc_core13sc_phash_base18remove_by_contentsEPKv(ptr nocapture noundef nonnull align 8 dereferenceable(56) %0, ptr noundef readnone %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp sgt i32 %4, 0
  br i1 %5, label %.lr.ph28, label %._crit_edge29

.lr.ph28:                                         ; preds = %2
  %6 = getelementptr inbounds i8, ptr %0, i64 32
  %7 = getelementptr inbounds i8, ptr %0, i64 12
  br label %8

._crit_edge29:                                    ; preds = %._crit_edge, %2
  %.015.lcssa = phi i32 [ 0, %2 ], [ %.1.lcssa, %._crit_edge ]
  ret i32 %.015.lcssa

8:                                                ; preds = %.lr.ph28, %._crit_edge
  %9 = phi i32 [ %4, %.lr.ph28 ], [ %23, %._crit_edge ]
  %indvars.iv = phi i64 [ 0, %.lr.ph28 ], [ %indvars.iv.next, %._crit_edge ]
  %.01525 = phi i32 [ 0, %.lr.ph28 ], [ %.1.lcssa, %._crit_edge ]
  %10 = load ptr, ptr %6, align 8, !tbaa !12
  %11 = getelementptr inbounds ptr, ptr %10, i64 %indvars.iv
  %12 = load ptr, ptr %11, align 8, !tbaa !13
  %.not21 = icmp eq ptr %12, null
  br i1 %.not21, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %8, %22
  %.124 = phi i32 [ %.2, %22 ], [ %.01525, %8 ]
  %.01623 = phi ptr [ %.117, %22 ], [ %12, %8 ]
  %.01822 = phi ptr [ %.119, %22 ], [ %11, %8 ]
  %13 = getelementptr inbounds i8, ptr %.01623, i64 8
  %14 = load ptr, ptr %13, align 8, !tbaa !14
  %.not20 = icmp eq ptr %14, %1
  %15 = getelementptr inbounds i8, ptr %.01623, i64 16
  %16 = load ptr, ptr %15, align 8, !tbaa !13
  br i1 %.not20, label %17, label %22

17:                                               ; preds = %.lr.ph
  store ptr %16, ptr %.01822, align 8, !tbaa !13
  tail call void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %.01623) #1
  tail call void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef nonnull %.01623, i64 noundef 24) #1
  %18 = load ptr, ptr %.01822, align 8, !tbaa !13
  %19 = load i32, ptr %7, align 4, !tbaa !16
  %20 = add nsw i32 %19, -1
  store i32 %20, ptr %7, align 4, !tbaa !16
  %21 = add nsw i32 %.124, 1
  br label %22

22:                                               ; preds = %.lr.ph, %17
  %.119 = phi ptr [ %.01822, %17 ], [ %15, %.lr.ph ]
  %.117 = phi ptr [ %18, %17 ], [ %16, %.lr.ph ]
  %.2 = phi i32 [ %21, %17 ], [ %.124, %.lr.ph ]
  %.not = icmp eq ptr %.117, null
  br i1 %.not, label %._crit_edge.loopexit, label %.lr.ph, !llvm.loop !17

._crit_edge.loopexit:                             ; preds = %22
  %.pre = load i32, ptr %3, align 8, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %8
  %23 = phi i32 [ %9, %8 ], [ %.pre, %._crit_edge.loopexit ]
  %.1.lcssa = phi i32 [ %.01525, %8 ], [ %.2, %._crit_edge.loopexit ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %24 = sext i32 %23 to i64
  %25 = icmp slt i64 %indvars.iv.next, %24
  br i1 %25, label %8, label %._crit_edge29, !llvm.loop !19
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"_ZTSN7sc_core13sc_phash_baseE", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !11, i64 24, !7, i64 32, !7, i64 40, !7, i64 48}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"double", !8, i64 0}
!12 = !{!6, !7, i64 32}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !7, i64 8}
!15 = !{!"_ZTSN7sc_core13sc_phash_elemE", !7, i64 0, !7, i64 8, !7, i64 16}
!16 = !{!6, !10, i64 12}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass