; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_spawn_options.ll (ZN7sc_core16sc_spawn_optionsD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_spawn_options" = type { i8, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector.10", %"class.std::vector.15", i8, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_spawn_reset_base *, std::allocator<sc_core::sc_spawn_reset_base *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_spawn_reset_base *, std::allocator<sc_core::sc_spawn_reset_base *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_spawn_reset_base *, std::allocator<sc_core::sc_spawn_reset_base *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_spawn_reset_base *, std::allocator<sc_core::sc_spawn_reset_base *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<sc_core::sc_event_finder *, std::allocator<sc_core::sc_event_finder *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event_finder *, std::allocator<sc_core::sc_event_finder *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event_finder *, std::allocator<sc_core::sc_event_finder *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event_finder *, std::allocator<sc_core::sc_event_finder *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_interface *, std::allocator<sc_core::sc_interface *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_interface *, std::allocator<sc_core::sc_interface *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_interface *, std::allocator<sc_core::sc_interface *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_interface *, std::allocator<sc_core::sc_interface *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core16sc_spawn_optionsD2Ev(ptr noundef nonnull align 8 dereferenceable(136) %0) unnamed_addr #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #2
  %6 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 1
  %7 = call noundef i64 @_ZNKSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #2
  store i64 %7, ptr %3, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #2
  store i64 0, ptr %4, align 8, !tbaa !9
  br label %8

8:                                                ; preds = %24, %1
  %9 = load i64, ptr %4, align 8, !tbaa !9
  %10 = load i64, ptr %3, align 8, !tbaa !9
  %11 = icmp ult i64 %9, %10
  br i1 %11, label %13, label %12

12:                                               ; preds = %8
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #2
  br label %27

13:                                               ; preds = %8
  %14 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 1
  %15 = load i64, ptr %4, align 8, !tbaa !9
  %16 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %15) #2
  %17 = load ptr, ptr %16, align 8, !tbaa !5
  %18 = icmp eq ptr %17, null
  br i1 %18, label %23, label %19

19:                                               ; preds = %13
  %20 = load ptr, ptr %17, align 8, !tbaa !11
  %21 = getelementptr inbounds ptr, ptr %20, i64 1
  %22 = load ptr, ptr %21, align 8
  call void %22(ptr noundef nonnull align 8 dereferenceable(10) %17) #2
  br label %23

23:                                               ; preds = %19, %13
  br label %24

24:                                               ; preds = %23
  %25 = load i64, ptr %4, align 8, !tbaa !9
  %26 = add i64 %25, 1
  store i64 %26, ptr %4, align 8, !tbaa !9
  br label %8, !llvm.loop !13

27:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #2
  %28 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 5
  call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %28) #2
  %29 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 4
  call void @_ZNSt6vectorIPN7sc_core12sc_interfaceESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %29) #2
  %30 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 3
  call void @_ZNSt6vectorIPN7sc_core15sc_event_finderESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %30) #2
  %31 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 2
  call void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %31) #2
  %32 = getelementptr inbounds %"class.sc_core::sc_spawn_options", ptr %5, i32 0, i32 1
  call void @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %32) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_interfaceESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core15sc_event_finderESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"vtable pointer", !8, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core16sc_spawn_optionsD2Ev(ptr noundef nonnull align 8 dereferenceable(136) %0) unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 8
  %3 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #1
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %15, %1
  %4 = getelementptr inbounds i8, ptr %0, i64 104
  tail call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #1
  %5 = getelementptr inbounds i8, ptr %0, i64 80
  tail call void @_ZNSt6vectorIPN7sc_core12sc_interfaceESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #1
  %6 = getelementptr inbounds i8, ptr %0, i64 56
  tail call void @_ZNSt6vectorIPN7sc_core15sc_event_finderESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #1
  %7 = getelementptr inbounds i8, ptr %0, i64 32
  tail call void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #1
  tail call void @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #1
  ret void

.lr.ph:                                           ; preds = %1, %15
  %.05 = phi i64 [ %16, %15 ], [ 0, %1 ]
  %8 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %.05) #1
  %9 = load ptr, ptr %8, align 8, !tbaa !5
  %10 = icmp eq ptr %9, null
  br i1 %10, label %15, label %11

11:                                               ; preds = %.lr.ph
  %12 = load ptr, ptr %9, align 8, !tbaa !9
  %13 = getelementptr inbounds i8, ptr %12, i64 8
  %14 = load ptr, ptr %13, align 8
  tail call void %14(ptr noundef nonnull align 8 dereferenceable(10) %9) #1
  br label %15

15:                                               ; preds = %.lr.ph, %11
  %16 = add nuw i64 %.05, 1
  %exitcond.not = icmp eq i64 %16, %3
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !11
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_interfaceESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core15sc_event_finderESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core19sc_spawn_reset_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass