; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/if_transforms/loop_unrolling/test6 (test)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.test = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.13", ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4test5entryEv(ptr noundef nonnull align 8 dereferenceable(1328) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca [10 x i32], align 16
  store ptr %0, ptr %2, align 8, !tbaa !5
  %8 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 40, ptr %7) #2
  %9 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 3
  %10 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %9)
  %11 = load i32, ptr %10, align 4, !tbaa !9
  %12 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 1
  store i32 %11, ptr %12, align 4, !tbaa !9
  %13 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 0
  store i32 %11, ptr %13, align 16, !tbaa !9
  %14 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 4
  %15 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %14)
  %16 = load i32, ptr %15, align 4, !tbaa !9
  %17 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 3
  store i32 %16, ptr %17, align 4, !tbaa !9
  %18 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 2
  store i32 %16, ptr %18, align 8, !tbaa !9
  %19 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 5
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %19)
  %21 = load i32, ptr %20, align 4, !tbaa !9
  %22 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 5
  store i32 %21, ptr %22, align 4, !tbaa !9
  %23 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 4
  store i32 %21, ptr %23, align 16, !tbaa !9
  %24 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 6
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %24)
  %26 = load i32, ptr %25, align 4, !tbaa !9
  %27 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 7
  store i32 %26, ptr %27, align 4, !tbaa !9
  %28 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 6
  store i32 %26, ptr %28, align 8, !tbaa !9
  %29 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 7
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %29)
  %31 = load i32, ptr %30, align 4, !tbaa !9
  %32 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 9
  store i32 %31, ptr %32, align 4, !tbaa !9
  %33 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 8
  store i32 %31, ptr %33, align 16, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %34

34:                                               ; preds = %57, %1
  %35 = load i32, ptr %3, align 4, !tbaa !9
  %36 = icmp slt i32 %35, 2
  br i1 %36, label %37, label %60

37:                                               ; preds = %34
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %53, %37
  %39 = load i32, ptr %4, align 4, !tbaa !9
  %40 = icmp slt i32 %39, 3
  br i1 %40, label %41, label %56

41:                                               ; preds = %38
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %42

42:                                               ; preds = %49, %41
  %43 = load i32, ptr %5, align 4, !tbaa !9
  %44 = icmp slt i32 %43, 4
  br i1 %44, label %45, label %52

45:                                               ; preds = %42
  %46 = load i32, ptr %3, align 4, !tbaa !9
  %47 = sext i32 %46 to i64
  %48 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 %47
  store i32 5, ptr %48, align 4, !tbaa !9
  br label %49

49:                                               ; preds = %45
  %50 = load i32, ptr %5, align 4, !tbaa !9
  %51 = add nsw i32 %50, 1
  store i32 %51, ptr %5, align 4, !tbaa !9
  br label %42, !llvm.loop !11

52:                                               ; preds = %42
  br label %53

53:                                               ; preds = %52
  %54 = load i32, ptr %4, align 4, !tbaa !9
  %55 = add nsw i32 %54, 1
  store i32 %55, ptr %4, align 4, !tbaa !9
  br label %38, !llvm.loop !13

56:                                               ; preds = %38
  br label %57

57:                                               ; preds = %56
  %58 = load i32, ptr %3, align 4, !tbaa !9
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr %3, align 4, !tbaa !9
  br label %34, !llvm.loop !14

60:                                               ; preds = %34
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %61

61:                                               ; preds = %92, %60
  %62 = load i32, ptr %3, align 4, !tbaa !9
  %63 = icmp slt i32 %62, 2
  br i1 %63, label %64, label %95

64:                                               ; preds = %61
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %65

65:                                               ; preds = %88, %64
  %66 = load i32, ptr %4, align 4, !tbaa !9
  %67 = icmp slt i32 %66, 3
  br i1 %67, label %68, label %91

68:                                               ; preds = %65
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %69

69:                                               ; preds = %84, %68
  %70 = load i32, ptr %5, align 4, !tbaa !9
  %71 = icmp slt i32 %70, 4
  br i1 %71, label %72, label %87

72:                                               ; preds = %69
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %73

73:                                               ; preds = %80, %72
  %74 = load i32, ptr %6, align 4, !tbaa !9
  %75 = icmp slt i32 %74, 2
  br i1 %75, label %76, label %83

76:                                               ; preds = %73
  %77 = load i32, ptr %3, align 4, !tbaa !9
  %78 = sext i32 %77 to i64
  %79 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 %78
  store i32 6, ptr %79, align 4, !tbaa !9
  br label %80

80:                                               ; preds = %76
  %81 = load i32, ptr %6, align 4, !tbaa !9
  %82 = add nsw i32 %81, 1
  store i32 %82, ptr %6, align 4, !tbaa !9
  br label %73, !llvm.loop !15

83:                                               ; preds = %73
  br label %84

84:                                               ; preds = %83
  %85 = load i32, ptr %5, align 4, !tbaa !9
  %86 = add nsw i32 %85, 1
  store i32 %86, ptr %5, align 4, !tbaa !9
  br label %69, !llvm.loop !16

87:                                               ; preds = %69
  br label %88

88:                                               ; preds = %87
  %89 = load i32, ptr %4, align 4, !tbaa !9
  %90 = add nsw i32 %89, 1
  store i32 %90, ptr %4, align 4, !tbaa !9
  br label %65, !llvm.loop !17

91:                                               ; preds = %65
  br label %92

92:                                               ; preds = %91
  %93 = load i32, ptr %3, align 4, !tbaa !9
  %94 = add nsw i32 %93, 1
  store i32 %94, ptr %3, align 4, !tbaa !9
  br label %61, !llvm.loop !18

95:                                               ; preds = %61
  %96 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 0
  %97 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 11
  %98 = load ptr, ptr %97, align 8, !tbaa !19
  %99 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %98, ptr noundef nonnull align 4 dereferenceable(4) %96)
  %100 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 2
  %101 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 12
  %102 = load ptr, ptr %101, align 8, !tbaa !57
  %103 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %102, ptr noundef nonnull align 4 dereferenceable(4) %100)
  %104 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 4
  %105 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 13
  %106 = load ptr, ptr %105, align 8, !tbaa !58
  %107 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %106, ptr noundef nonnull align 4 dereferenceable(4) %104)
  %108 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 6
  %109 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 14
  %110 = load ptr, ptr %109, align 8, !tbaa !59
  %111 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %110, ptr noundef nonnull align 4 dereferenceable(4) %108)
  %112 = getelementptr inbounds [10 x i32], ptr %7, i64 0, i64 8
  %113 = getelementptr inbounds %struct.test, ptr %8, i32 0, i32 15
  %114 = load ptr, ptr %113, align 8, !tbaa !60
  %115 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %114, ptr noundef nonnull align 4 dereferenceable(4) %112)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  call void @llvm.lifetime.end.p0(i64 40, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}
!18 = distinct !{!18, !12}
!19 = !{!20, !6, i64 1288}
!20 = !{!"_ZTS4test", !21, i64 0, !42, i64 232, !6, i64 416, !50, i64 424, !50, i64 592, !50, i64 760, !50, i64 928, !50, i64 1096, !6, i64 1264, !6, i64 1272, !6, i64 1280, !6, i64 1288, !6, i64 1296, !6, i64 1304, !6, i64 1312, !6, i64 1320}
!21 = !{!"_ZTSN7sc_core9sc_moduleE", !22, i64 0, !34, i64 112, !35, i64 120, !37, i64 144, !39, i64 168, !41, i64 192, !6, i64 200, !10, i64 208, !6, i64 216, !6, i64 224}
!22 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !23, i64 16, !27, i64 40, !31, i64 64, !6, i64 96, !6, i64 104}
!23 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !32, i64 0, !33, i64 8, !7, i64 16}
!32 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!33 = !{!"long", !7, i64 0}
!34 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!35 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !36, i64 8, !6, i64 16}
!36 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!37 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !38, i64 8, !6, i64 16}
!38 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!39 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !40, i64 8, !6, i64 16}
!40 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!41 = !{!"bool", !7, i64 0}
!42 = !{!"_ZTSN7sc_core5sc_inIbEE", !43, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!43 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !44, i64 0}
!44 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !45, i64 0, !6, i64 120, !46, i64 128}
!45 = !{!"_ZTSN7sc_core12sc_port_baseE", !22, i64 0, !6, i64 112}
!46 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !47, i64 0}
!47 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !48, i64 0}
!48 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !49, i64 0}
!49 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!50 = !{!"_ZTSN7sc_core5sc_inIiEE", !51, i64 0, !6, i64 152, !6, i64 160}
!51 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIiEELi1ELNS_14sc_port_policyE0EEE", !52, i64 0}
!52 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIiEEEE", !45, i64 0, !6, i64 120, !53, i64 128}
!53 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !54, i64 0}
!54 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !55, i64 0}
!55 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE12_Vector_implE", !56, i64 0}
!56 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!57 = !{!20, !6, i64 1296}
!58 = !{!20, !6, i64 1304}
!59 = !{!20, !6, i64 1312}
!60 = !{!20, !6, i64 1320}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4test5entryEv(ptr noundef nonnull align 8 dereferenceable(1328) %0) local_unnamed_addr #0 align 2 {
.preheader25:
  %1 = alloca [10 x i32], align 16
  call void @llvm.lifetime.start.p0(i64 40, ptr nonnull %1) #2
  %2 = getelementptr inbounds i8, ptr %0, i64 424
  %3 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %2)
  %4 = getelementptr inbounds i8, ptr %1, i64 4
  %5 = getelementptr inbounds i8, ptr %0, i64 592
  %6 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %5)
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %1, i64 12
  store i32 %7, ptr %8, align 4, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %1, i64 8
  store i32 %7, ptr %9, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %0, i64 760
  %11 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %10)
  %12 = load i32, ptr %11, align 4, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %1, i64 20
  store i32 %12, ptr %13, align 4, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %1, i64 16
  store i32 %12, ptr %14, align 16, !tbaa !5
  %15 = getelementptr inbounds i8, ptr %0, i64 928
  %16 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %15)
  %17 = load i32, ptr %16, align 4, !tbaa !5
  %18 = getelementptr inbounds i8, ptr %1, i64 28
  store i32 %17, ptr %18, align 4, !tbaa !5
  %19 = getelementptr inbounds i8, ptr %1, i64 24
  store i32 %17, ptr %19, align 8, !tbaa !5
  %20 = getelementptr inbounds i8, ptr %0, i64 1096
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %20)
  %22 = load i32, ptr %21, align 4, !tbaa !5
  %23 = getelementptr inbounds i8, ptr %1, i64 36
  store i32 %22, ptr %23, align 4, !tbaa !5
  %24 = getelementptr inbounds i8, ptr %1, i64 32
  store i32 %22, ptr %24, align 16, !tbaa !5
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  store i32 6, ptr %1, align 16, !tbaa !5
  store i32 6, ptr %4, align 4, !tbaa !5
  %25 = getelementptr inbounds i8, ptr %0, i64 1288
  %26 = load ptr, ptr %25, align 8, !tbaa !9
  %27 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %26, ptr noundef nonnull align 4 dereferenceable(4) %1)
  %28 = getelementptr inbounds i8, ptr %0, i64 1296
  %29 = load ptr, ptr %28, align 8, !tbaa !48
  %30 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %29, ptr noundef nonnull align 4 dereferenceable(4) %9)
  %31 = getelementptr inbounds i8, ptr %0, i64 1304
  %32 = load ptr, ptr %31, align 8, !tbaa !49
  %33 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %32, ptr noundef nonnull align 4 dereferenceable(4) %14)
  %34 = getelementptr inbounds i8, ptr %0, i64 1312
  %35 = load ptr, ptr %34, align 8, !tbaa !50
  %36 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %35, ptr noundef nonnull align 4 dereferenceable(4) %19)
  %37 = getelementptr inbounds i8, ptr %0, i64 1320
  %38 = load ptr, ptr %37, align 8, !tbaa !51
  %39 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %38, ptr noundef nonnull align 4 dereferenceable(4) %24)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  call void @llvm.lifetime.end.p0(i64 40, ptr nonnull %1) #2
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 1288}
!10 = !{!"_ZTS4test", !11, i64 0, !33, i64 232, !13, i64 416, !41, i64 424, !41, i64 592, !41, i64 760, !41, i64 928, !41, i64 1096, !13, i64 1264, !13, i64 1272, !13, i64 1280, !13, i64 1288, !13, i64 1296, !13, i64 1304, !13, i64 1312, !13, i64 1320}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !25, i64 112, !26, i64 120, !28, i64 144, !30, i64 168, !32, i64 192, !13, i64 200, !6, i64 208, !13, i64 216, !13, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !13, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !13, i64 96, !13, i64 104}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveE", !13, i64 0, !27, i64 8, !13, i64 16}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !13, i64 0, !29, i64 8, !13, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !13, i64 0, !31, i64 8, !13, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!32 = !{!"bool", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !13, i64 152, !13, i64 160, !13, i64 168, !13, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !13, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !13, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!41 = !{!"_ZTSN7sc_core5sc_inIiEE", !42, i64 0, !13, i64 152, !13, i64 160}
!42 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIiEELi1ELNS_14sc_port_policyE0EEE", !43, i64 0}
!43 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIiEEEE", !36, i64 0, !13, i64 120, !44, i64 128}
!44 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !45, i64 0}
!45 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE12_Vector_implE", !47, i64 0}
!47 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!48 = !{!10, !13, i64 1296}
!49 = !{!10, !13, i64 1304}
!50 = !{!10, !13, i64 1312}
!51 = !{!10, !13, i64 1320}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass