; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication/sc_port.ll (ZN7sc_core12sc_port_base4bindERS0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector.5", %"class.std::vector.10", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.sc_core::sc_bind_info" = type { i32, i32, %"class.std::vector", i8, i32, i8, i8, %"class.std::vector.0", %"class.std::vector.0" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_bind_elem *, std::allocator<sc_core::sc_bind_elem *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_bind_elem *, std::allocator<sc_core::sc_bind_elem *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_bind_elem *, std::allocator<sc_core::sc_bind_elem *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_bind_elem *, std::allocator<sc_core::sc_bind_elem *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_bind_ef *, std::allocator<sc_core::sc_bind_ef *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_bind_ef *, std::allocator<sc_core::sc_bind_ef *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_bind_ef *, std::allocator<sc_core::sc_bind_ef *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_bind_ef *, std::allocator<sc_core::sc_bind_ef *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@_ZN7sc_core24SC_ID_BIND_PORT_TO_PORT_E = external constant [0 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [10 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef, ptr noundef) #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_bind_elemESaIS2_EE9push_backEOS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull align 8 dereferenceable(120) %1) #2 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  %9 = getelementptr inbounds %"class.sc_core::sc_port_base", ptr %8, i32 0, i32 1
  %10 = load ptr, ptr %9, align 8, !tbaa !9
  %11 = icmp eq ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %2
  call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %8, ptr noundef @_ZN7sc_core24SC_ID_BIND_PORT_TO_PORT_E, ptr noundef @.str.4)
  br label %13

13:                                               ; preds = %12, %2
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = icmp eq ptr %14, %8
  br i1 %15, label %16, label %17

16:                                               ; preds = %13
  call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %8, ptr noundef @_ZN7sc_core24SC_ID_BIND_PORT_TO_PORT_E, ptr noundef @.str.5)
  br label %17

17:                                               ; preds = %16, %13
  %18 = getelementptr inbounds %"class.sc_core::sc_port_base", ptr %8, i32 0, i32 1
  %19 = load ptr, ptr %18, align 8, !tbaa !9
  %20 = getelementptr inbounds %"struct.sc_core::sc_bind_info", ptr %19, i32 0, i32 2
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %21 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 16) #5
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  invoke void @_ZN7sc_core12sc_bind_elemC1EPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(16) %21, ptr noundef %22)
          to label %23 unwind label %31

23:                                               ; preds = %17
  store ptr %21, ptr %5, align 8, !tbaa !5
  call void @_ZNSt6vectorIPN7sc_core12sc_bind_elemESaIS2_EE9push_backEOS2_(ptr noundef nonnull align 8 dereferenceable(24) %20, ptr noundef nonnull align 8 dereferenceable(8) %5)
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  %24 = getelementptr inbounds %"class.sc_core::sc_port_base", ptr %8, i32 0, i32 1
  %25 = load ptr, ptr %24, align 8, !tbaa !9
  %26 = getelementptr inbounds %"struct.sc_core::sc_bind_info", ptr %25, i32 0, i32 3
  store i8 1, ptr %26, align 8, !tbaa !23
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = getelementptr inbounds %"class.sc_core::sc_port_base", ptr %27, i32 0, i32 1
  %29 = load ptr, ptr %28, align 8, !tbaa !9
  %30 = getelementptr inbounds %"struct.sc_core::sc_bind_info", ptr %29, i32 0, i32 5
  store i8 0, ptr %30, align 8, !tbaa !36
  ret void

31:                                               ; preds = %17
  %32 = landingpad { ptr, i32 }
          cleanup
  %33 = extractvalue { ptr, i32 } %32, 0
  store ptr %33, ptr %6, align 8
  %34 = extractvalue { ptr, i32 } %32, 1
  store i32 %34, ptr %7, align 4
  call void @_ZdlPvm(ptr noundef %21, i64 noundef 16) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  br label %35

35:                                               ; preds = %31
  %36 = load ptr, ptr %6, align 8
  %37 = load i32, ptr %7, align 4
  %38 = insertvalue { ptr, i32 } poison, ptr %36, 0
  %39 = insertvalue { ptr, i32 } %38, i32 %37, 1
  resume { ptr, i32 } %39
}

declare void @_ZN7sc_core12sc_bind_elemC1EPNS_12sc_port_baseE(ptr, ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin allocsize(0) }
attributes #6 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 112}
!10 = !{!"_ZTSN7sc_core12sc_port_baseE", !11, i64 0, !6, i64 112}
!11 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !6, i64 96, !6, i64 104}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !7, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!22 = !{!"long", !7, i64 0}
!23 = !{!24, !31, i64 32}
!24 = !{!"_ZTSN7sc_core12sc_bind_infoE", !25, i64 0, !26, i64 4, !27, i64 8, !31, i64 32, !25, i64 36, !31, i64 40, !31, i64 41, !32, i64 48, !32, i64 72}
!25 = !{!"int", !7, i64 0}
!26 = !{!"_ZTSN7sc_core14sc_port_policyE", !7, i64 0}
!27 = !{!"_ZTSSt6vectorIPN7sc_core12sc_bind_elemESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core12sc_bind_elemESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_bind_elemESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_bind_elemESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"bool", !7, i64 0}
!32 = !{!"_ZTSSt6vectorIPN7sc_core10sc_bind_efESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPN7sc_core10sc_bind_efESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core10sc_bind_efESaIS2_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core10sc_bind_efESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!36 = !{!24, !31, i64 40}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@_ZN7sc_core24SC_ID_BIND_PORT_TO_PORT_E = external constant [0 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [10 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef, ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_bind_elemESaIS2_EE9push_backEOS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_port_base4bindERS0_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull align 8 dereferenceable(120) %1) local_unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = getelementptr inbounds i8, ptr %0, i64 112
  %5 = load ptr, ptr %4, align 8, !tbaa !5
  %6 = icmp eq ptr %5, null
  br i1 %6, label %7, label %8

7:                                                ; preds = %2
  tail call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull @_ZN7sc_core24SC_ID_BIND_PORT_TO_PORT_E, ptr noundef nonnull @.str.4)
  br label %8

8:                                                ; preds = %7, %2
  %9 = icmp eq ptr %1, %0
  br i1 %9, label %10, label %11

10:                                               ; preds = %8
  tail call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull @_ZN7sc_core24SC_ID_BIND_PORT_TO_PORT_E, ptr noundef nonnull @.str.5)
  br label %11

11:                                               ; preds = %10, %8
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #4
  %13 = tail call noalias noundef nonnull dereferenceable(16) ptr @_Znwm(i64 noundef 16) #5
  invoke void @_ZN7sc_core12sc_bind_elemC1EPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(16) %13, ptr noundef nonnull %1)
          to label %14 unwind label %21

14:                                               ; preds = %11
  %15 = getelementptr inbounds i8, ptr %12, i64 8
  store ptr %13, ptr %3, align 8, !tbaa !22
  call void @_ZNSt6vectorIPN7sc_core12sc_bind_elemESaIS2_EE9push_backEOS2_(ptr noundef nonnull align 8 dereferenceable(24) %15, ptr noundef nonnull align 8 dereferenceable(8) %3)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #4
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %16, i64 32
  store i8 1, ptr %17, align 8, !tbaa !23
  %18 = getelementptr inbounds i8, ptr %1, i64 112
  %19 = load ptr, ptr %18, align 8, !tbaa !5
  %20 = getelementptr inbounds i8, ptr %19, i64 40
  store i8 0, ptr %20, align 8, !tbaa !36
  ret void

21:                                               ; preds = %11
  %22 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %13, i64 noundef 16) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #4
  resume { ptr, i32 } %22
}

declare void @_ZN7sc_core12sc_bind_elemC1EPNS_12sc_port_baseE(ptr, ptr) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin allocsize(0) }
attributes #6 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 112}
!6 = !{!"_ZTSN7sc_core12sc_port_baseE", !7, i64 0, !8, i64 112}
!7 = !{!"_ZTSN7sc_core9sc_objectE", !8, i64 8, !11, i64 16, !15, i64 40, !19, i64 64, !8, i64 96, !8, i64 104}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!15 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !21, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !8, i64 0}
!21 = !{!"long", !9, i64 0}
!22 = !{!8, !8, i64 0}
!23 = !{!24, !31, i64 32}
!24 = !{!"_ZTSN7sc_core12sc_bind_infoE", !25, i64 0, !26, i64 4, !27, i64 8, !31, i64 32, !25, i64 36, !31, i64 40, !31, i64 41, !32, i64 48, !32, i64 72}
!25 = !{!"int", !9, i64 0}
!26 = !{!"_ZTSN7sc_core14sc_port_policyE", !9, i64 0}
!27 = !{!"_ZTSSt6vectorIPN7sc_core12sc_bind_elemESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core12sc_bind_elemESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_bind_elemESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_bind_elemESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!31 = !{!"bool", !9, i64 0}
!32 = !{!"_ZTSSt6vectorIPN7sc_core10sc_bind_efESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPN7sc_core10sc_bind_efESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core10sc_bind_efESaIS2_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core10sc_bind_efESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!36 = !{!24, !31, i64 40}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass