; LLVM IR from JanaSabuj/cppdump :: SegmentTree.ll (Z6updatexxxxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@tree = external dso_local global %"class.std::vector", align 8
@arr = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6updatexxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4) #2 {
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  store i64 %0, ptr %6, align 8, !tbaa !5
  store i64 %1, ptr %7, align 8, !tbaa !5
  store i64 %2, ptr %8, align 8, !tbaa !5
  store i64 %3, ptr %9, align 8, !tbaa !5
  store i64 %4, ptr %10, align 8, !tbaa !5
  %12 = load i64, ptr %6, align 8, !tbaa !5
  %13 = load i64, ptr %7, align 8, !tbaa !5
  %14 = icmp eq i64 %12, %13
  br i1 %14, label %15, label %22

15:                                               ; preds = %5
  %16 = load i64, ptr %10, align 8, !tbaa !5
  %17 = load i64, ptr %9, align 8, !tbaa !5
  %18 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @arr, i64 noundef %17) #3
  store i64 %16, ptr %18, align 8, !tbaa !5
  %19 = load i64, ptr %10, align 8, !tbaa !5
  %20 = load i64, ptr %8, align 8, !tbaa !5
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %20) #3
  store i64 %19, ptr %21, align 8, !tbaa !5
  br label %59

22:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %23 = load i64, ptr %6, align 8, !tbaa !5
  %24 = load i64, ptr %7, align 8, !tbaa !5
  %25 = add nsw i64 %23, %24
  %26 = sdiv i64 %25, 2
  store i64 %26, ptr %11, align 8, !tbaa !5
  %27 = load i64, ptr %9, align 8, !tbaa !5
  %28 = load i64, ptr %11, align 8, !tbaa !5
  %29 = icmp sgt i64 %27, %28
  br i1 %29, label %30, label %39

30:                                               ; preds = %22
  %31 = load i64, ptr %11, align 8, !tbaa !5
  %32 = add nsw i64 %31, 1
  %33 = load i64, ptr %7, align 8, !tbaa !5
  %34 = load i64, ptr %8, align 8, !tbaa !5
  %35 = mul nsw i64 2, %34
  %36 = add nsw i64 %35, 1
  %37 = load i64, ptr %9, align 8, !tbaa !5
  %38 = load i64, ptr %10, align 8, !tbaa !5
  call void @_Z6updatexxxxx(i64 noundef %32, i64 noundef %33, i64 noundef %36, i64 noundef %37, i64 noundef %38)
  br label %46

39:                                               ; preds = %22
  %40 = load i64, ptr %6, align 8, !tbaa !5
  %41 = load i64, ptr %11, align 8, !tbaa !5
  %42 = load i64, ptr %8, align 8, !tbaa !5
  %43 = mul nsw i64 2, %42
  %44 = load i64, ptr %9, align 8, !tbaa !5
  %45 = load i64, ptr %10, align 8, !tbaa !5
  call void @_Z6updatexxxxx(i64 noundef %40, i64 noundef %41, i64 noundef %43, i64 noundef %44, i64 noundef %45)
  br label %46

46:                                               ; preds = %39, %30
  %47 = load i64, ptr %8, align 8, !tbaa !5
  %48 = mul nsw i64 2, %47
  %49 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %48) #3
  %50 = load i64, ptr %49, align 8, !tbaa !5
  %51 = load i64, ptr %8, align 8, !tbaa !5
  %52 = mul nsw i64 2, %51
  %53 = add nsw i64 %52, 1
  %54 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %53) #3
  %55 = load i64, ptr %54, align 8, !tbaa !5
  %56 = add nsw i64 %50, %55
  %57 = load i64, ptr %8, align 8, !tbaa !5
  %58 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %57) #3
  store i64 %56, ptr %58, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  br label %59

59:                                               ; preds = %46, %15
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@tree = external dso_local global %"class.std::vector", align 8
@arr = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6updatexxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4) local_unnamed_addr #0 {
  %6 = icmp eq i64 %0, %1
  br i1 %6, label %7, label %9

7:                                                ; preds = %5
  %8 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @arr, i64 noundef %3) #1
  store i64 %4, ptr %8, align 8, !tbaa !5
  br label %25

9:                                                ; preds = %5
  %10 = add nsw i64 %1, %0
  %11 = sdiv i64 %10, 2
  %12 = icmp slt i64 %11, %3
  br i1 %12, label %13, label %17

13:                                               ; preds = %9
  %14 = add nsw i64 %11, 1
  %15 = shl nsw i64 %2, 1
  %16 = or disjoint i64 %15, 1
  tail call void @_Z6updatexxxxx(i64 noundef %14, i64 noundef %1, i64 noundef %16, i64 noundef %3, i64 noundef %4)
  br label %19

17:                                               ; preds = %9
  %18 = shl nsw i64 %2, 1
  tail call void @_Z6updatexxxxx(i64 noundef %0, i64 noundef %11, i64 noundef %18, i64 noundef %3, i64 noundef %4)
  %.pre = or disjoint i64 %18, 1
  br label %19

19:                                               ; preds = %17, %13
  %.pre-phi27 = phi i64 [ %.pre, %17 ], [ %16, %13 ]
  %.pre-phi = phi i64 [ %18, %17 ], [ %15, %13 ]
  %20 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %.pre-phi) #1
  %21 = load i64, ptr %20, align 8, !tbaa !5
  %22 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %.pre-phi27) #1
  %23 = load i64, ptr %22, align 8, !tbaa !5
  %24 = add nsw i64 %23, %21
  br label %25

25:                                               ; preds = %19, %7
  %.sink = phi i64 [ %24, %19 ], [ %4, %7 ]
  %26 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %2) #1
  store i64 %.sink, ptr %26, align 8, !tbaa !5
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass