; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library (SerialPortInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@gUartBase = external dso_local global i16, align 2
@gBps = external dso_local global i64, align 8
@gData = external dso_local global i8, align 1
@gStop = external dso_local global i8, align 1
@gParity = external dso_local global i8, align 1
@gBreakSet = external dso_local global i8, align 1

; Function Attrs: nounwind uwtable
define dso_local i64 @SerialPortInitialize() #0 {
  %1 = alloca i64, align 8
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 8, ptr %1) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  %4 = load i8, ptr @gData, align 1, !tbaa !5
  %5 = zext i8 %4 to i32
  %6 = sub nsw i32 %5, 5
  %7 = trunc i32 %6 to i8
  store i8 %7, ptr %3, align 1, !tbaa !5
  %8 = load i64, ptr @gBps, align 8, !tbaa !8
  %9 = udiv i64 115200, %8
  store i64 %9, ptr %1, align 8, !tbaa !8
  %10 = load i8, ptr @gBreakSet, align 1, !tbaa !5
  %11 = zext i8 %10 to i32
  %12 = shl i32 %11, 6
  %13 = or i32 128, %12
  %14 = load i8, ptr @gParity, align 1, !tbaa !5
  %15 = zext i8 %14 to i32
  %16 = shl i32 %15, 3
  %17 = or i32 %13, %16
  %18 = load i8, ptr @gStop, align 1, !tbaa !5
  %19 = zext i8 %18 to i32
  %20 = shl i32 %19, 2
  %21 = or i32 %17, %20
  %22 = load i8, ptr %3, align 1, !tbaa !5
  %23 = zext i8 %22 to i32
  %24 = or i32 %21, %23
  %25 = trunc i32 %24 to i8
  store i8 %25, ptr %2, align 1, !tbaa !5
  %26 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %27 = zext i16 %26 to i32
  %28 = add nsw i32 %27, 3
  %29 = sext i32 %28 to i64
  %30 = load i8, ptr %2, align 1, !tbaa !5
  %31 = call zeroext i8 @IoWrite8(i64 noundef %29, i8 noundef zeroext %30)
  %32 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %33 = zext i16 %32 to i32
  %34 = add nsw i32 %33, 1
  %35 = sext i32 %34 to i64
  %36 = load i64, ptr %1, align 8, !tbaa !8
  %37 = lshr i64 %36, 8
  %38 = trunc i64 %37 to i8
  %39 = call zeroext i8 @IoWrite8(i64 noundef %35, i8 noundef zeroext %38)
  %40 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %41 = zext i16 %40 to i32
  %42 = add nsw i32 %41, 0
  %43 = sext i32 %42 to i64
  %44 = load i64, ptr %1, align 8, !tbaa !8
  %45 = and i64 %44, 255
  %46 = trunc i64 %45 to i8
  %47 = call zeroext i8 @IoWrite8(i64 noundef %43, i8 noundef zeroext %46)
  %48 = load i8, ptr @gBreakSet, align 1, !tbaa !5
  %49 = zext i8 %48 to i32
  %50 = shl i32 %49, 6
  %51 = or i32 -256, %50
  %52 = load i8, ptr @gParity, align 1, !tbaa !5
  %53 = zext i8 %52 to i32
  %54 = shl i32 %53, 3
  %55 = or i32 %51, %54
  %56 = load i8, ptr @gStop, align 1, !tbaa !5
  %57 = zext i8 %56 to i32
  %58 = shl i32 %57, 2
  %59 = or i32 %55, %58
  %60 = load i8, ptr %3, align 1, !tbaa !5
  %61 = zext i8 %60 to i32
  %62 = or i32 %59, %61
  %63 = trunc i32 %62 to i8
  store i8 %63, ptr %2, align 1, !tbaa !5
  %64 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %65 = zext i16 %64 to i32
  %66 = add nsw i32 %65, 3
  %67 = sext i32 %66 to i64
  %68 = load i8, ptr %2, align 1, !tbaa !5
  %69 = call zeroext i8 @IoWrite8(i64 noundef %67, i8 noundef zeroext %68)
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %2) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %1) #3
  ret i64 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @IoWrite8(i64 noundef, i8 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"long long", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@gUartBase = external dso_local local_unnamed_addr global i16, align 2
@gBps = external dso_local local_unnamed_addr global i64, align 8
@gData = external dso_local local_unnamed_addr global i8, align 1
@gStop = external dso_local local_unnamed_addr global i8, align 1
@gParity = external dso_local local_unnamed_addr global i8, align 1
@gBreakSet = external dso_local local_unnamed_addr global i8, align 1

; Function Attrs: nounwind uwtable
define dso_local noundef i64 @SerialPortInitialize() local_unnamed_addr #0 {
  %1 = load i8, ptr @gData, align 1, !tbaa !5
  %2 = add i8 %1, -5
  %3 = load i64, ptr @gBps, align 8, !tbaa !8
  %4 = udiv i64 115200, %3
  %5 = load i8, ptr @gBreakSet, align 1, !tbaa !5
  %6 = shl i8 %5, 6
  %7 = load i8, ptr @gParity, align 1, !tbaa !5
  %8 = shl i8 %7, 3
  %9 = load i8, ptr @gStop, align 1, !tbaa !5
  %10 = shl i8 %9, 2
  %11 = or i8 %6, %8
  %12 = or i8 %11, %10
  %13 = or i8 %12, %2
  %14 = or i8 %13, -128
  %15 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %16 = zext i16 %15 to i64
  %17 = add nuw nsw i64 %16, 3
  %18 = tail call zeroext i8 @IoWrite8(i64 noundef %17, i8 noundef zeroext %14) #2
  %19 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %20 = zext i16 %19 to i64
  %21 = add nuw nsw i64 %20, 1
  %22 = lshr i64 %4, 8
  %23 = trunc i64 %22 to i8
  %24 = tail call zeroext i8 @IoWrite8(i64 noundef %21, i8 noundef zeroext %23) #2
  %25 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %26 = zext i16 %25 to i64
  %27 = trunc i64 %4 to i8
  %28 = tail call zeroext i8 @IoWrite8(i64 noundef %26, i8 noundef zeroext %27) #2
  %29 = load i8, ptr @gBreakSet, align 1, !tbaa !5
  %30 = shl i8 %29, 6
  %31 = load i8, ptr @gParity, align 1, !tbaa !5
  %32 = shl i8 %31, 3
  %33 = load i8, ptr @gStop, align 1, !tbaa !5
  %34 = shl i8 %33, 2
  %35 = or i8 %30, %32
  %36 = or i8 %35, %34
  %37 = or i8 %36, %2
  %38 = load i16, ptr @gUartBase, align 2, !tbaa !10
  %39 = zext i16 %38 to i64
  %40 = add nuw nsw i64 %39, 3
  %41 = tail call zeroext i8 @IoWrite8(i64 noundef %40, i8 noundef zeroext %37) #2
  ret i64 0
}

declare zeroext i8 @IoWrite8(i64 noundef, i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"long long", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !6, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,TailCallElimPass