; LLVM IR from JanaSabuj/cppdump :: NQueen.ll (Z7isValidxxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@board = external dso_local global %"class.std::vector.0", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z7isValidxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2) #1 {
  %4 = alloca i1, align 1
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store i64 %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !5
  store i64 %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #2
  %14 = load i64, ptr %6, align 8, !tbaa !5
  %15 = sub nsw i64 %14, 1
  store i64 %15, ptr %8, align 8, !tbaa !5
  br label %16

16:                                               ; preds = %29, %3
  %17 = load i64, ptr %8, align 8, !tbaa !5
  %18 = icmp sge i64 %17, 0
  br i1 %18, label %20, label %19

19:                                               ; preds = %16
  store i32 2, ptr %9, align 4
  br label %32

20:                                               ; preds = %16
  %21 = load i64, ptr %8, align 8, !tbaa !5
  %22 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @board, i64 noundef %21) #2
  %23 = load i64, ptr %7, align 8, !tbaa !5
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %23) #2
  %25 = load i64, ptr %24, align 8, !tbaa !5
  %26 = icmp eq i64 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %20
  store i1 false, ptr %4, align 1
  store i32 1, ptr %9, align 4
  br label %32

28:                                               ; preds = %20
  br label %29

29:                                               ; preds = %28
  %30 = load i64, ptr %8, align 8, !tbaa !5
  %31 = add nsw i64 %30, -1
  store i64 %31, ptr %8, align 8, !tbaa !5
  br label %16, !llvm.loop !9

32:                                               ; preds = %27, %19
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #2
  %33 = load i32, ptr %9, align 4
  switch i32 %33, label %98 [
    i32 2, label %34
    i32 1, label %96
  ]

34:                                               ; preds = %32
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #2
  %35 = load i64, ptr %6, align 8, !tbaa !5
  %36 = sub nsw i64 %35, 1
  store i64 %36, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  %37 = load i64, ptr %7, align 8, !tbaa !5
  %38 = sub nsw i64 %37, 1
  store i64 %38, ptr %11, align 8, !tbaa !5
  br label %39

39:                                               ; preds = %57, %34
  %40 = load i64, ptr %10, align 8, !tbaa !5
  %41 = icmp sge i64 %40, 0
  br i1 %41, label %42, label %45

42:                                               ; preds = %39
  %43 = load i64, ptr %11, align 8, !tbaa !5
  %44 = icmp sge i64 %43, 0
  br label %45

45:                                               ; preds = %42, %39
  %46 = phi i1 [ false, %39 ], [ %44, %42 ]
  br i1 %46, label %48, label %47

47:                                               ; preds = %45
  store i32 5, ptr %9, align 4
  br label %62

48:                                               ; preds = %45
  %49 = load i64, ptr %10, align 8, !tbaa !5
  %50 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @board, i64 noundef %49) #2
  %51 = load i64, ptr %11, align 8, !tbaa !5
  %52 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %50, i64 noundef %51) #2
  %53 = load i64, ptr %52, align 8, !tbaa !5
  %54 = icmp eq i64 %53, 1
  br i1 %54, label %55, label %56

55:                                               ; preds = %48
  store i1 false, ptr %4, align 1
  store i32 1, ptr %9, align 4
  br label %62

56:                                               ; preds = %48
  br label %57

57:                                               ; preds = %56
  %58 = load i64, ptr %10, align 8, !tbaa !5
  %59 = add nsw i64 %58, -1
  store i64 %59, ptr %10, align 8, !tbaa !5
  %60 = load i64, ptr %11, align 8, !tbaa !5
  %61 = add nsw i64 %60, -1
  store i64 %61, ptr %11, align 8, !tbaa !5
  br label %39, !llvm.loop !11

62:                                               ; preds = %55, %47
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #2
  %63 = load i32, ptr %9, align 4
  switch i32 %63, label %98 [
    i32 5, label %64
    i32 1, label %96
  ]

64:                                               ; preds = %62
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #2
  %65 = load i64, ptr %6, align 8, !tbaa !5
  %66 = sub nsw i64 %65, 1
  store i64 %66, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #2
  %67 = load i64, ptr %7, align 8, !tbaa !5
  %68 = add nsw i64 %67, 1
  store i64 %68, ptr %13, align 8, !tbaa !5
  br label %69

69:                                               ; preds = %88, %64
  %70 = load i64, ptr %12, align 8, !tbaa !5
  %71 = icmp sge i64 %70, 0
  br i1 %71, label %72, label %76

72:                                               ; preds = %69
  %73 = load i64, ptr %13, align 8, !tbaa !5
  %74 = load i64, ptr %5, align 8, !tbaa !5
  %75 = icmp slt i64 %73, %74
  br label %76

76:                                               ; preds = %72, %69
  %77 = phi i1 [ false, %69 ], [ %75, %72 ]
  br i1 %77, label %79, label %78

78:                                               ; preds = %76
  store i32 8, ptr %9, align 4
  br label %93

79:                                               ; preds = %76
  %80 = load i64, ptr %12, align 8, !tbaa !5
  %81 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @board, i64 noundef %80) #2
  %82 = load i64, ptr %13, align 8, !tbaa !5
  %83 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef %82) #2
  %84 = load i64, ptr %83, align 8, !tbaa !5
  %85 = icmp eq i64 %84, 1
  br i1 %85, label %86, label %87

86:                                               ; preds = %79
  store i1 false, ptr %4, align 1
  store i32 1, ptr %9, align 4
  br label %93

87:                                               ; preds = %79
  br label %88

88:                                               ; preds = %87
  %89 = load i64, ptr %12, align 8, !tbaa !5
  %90 = add nsw i64 %89, -1
  store i64 %90, ptr %12, align 8, !tbaa !5
  %91 = load i64, ptr %13, align 8, !tbaa !5
  %92 = add nsw i64 %91, 1
  store i64 %92, ptr %13, align 8, !tbaa !5
  br label %69, !llvm.loop !12

93:                                               ; preds = %86, %78
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #2
  %94 = load i32, ptr %9, align 4
  switch i32 %94, label %98 [
    i32 8, label %95
    i32 1, label %96
  ]

95:                                               ; preds = %93
  store i1 true, ptr %4, align 1
  br label %96

96:                                               ; preds = %95, %93, %62, %32
  %97 = load i1, ptr %4, align 1
  ret i1 %97

98:                                               ; preds = %93, %62, %32
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@board = external dso_local global %"class.std::vector.0", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z7isValidxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2) local_unnamed_addr #0 {
  %4 = add nsw i64 %1, -1
  %5 = icmp sgt i64 %1, 0
  br i1 %5, label %.lr.ph, label %.thread

6:                                                ; preds = %.lr.ph
  %7 = add nsw i64 %.02949, -1
  %8 = icmp sgt i64 %.02949, 0
  br i1 %8, label %.lr.ph, label %.preheader46, !llvm.loop !5

.preheader46:                                     ; preds = %6
  %9 = icmp sgt i64 %2, 0
  %10 = and i1 %5, %9
  br i1 %10, label %.lr.ph53, label %.preheader

.lr.ph:                                           ; preds = %3, %6
  %.02949 = phi i64 [ %7, %6 ], [ %4, %3 ]
  %11 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @board, i64 noundef %.02949) #1
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %2) #1
  %13 = load i64, ptr %12, align 8, !tbaa !7
  %14 = icmp eq i64 %13, 1
  br i1 %14, label %.thread, label %6

15:                                               ; preds = %.lr.ph53
  %16 = add nsw i64 %.02751, -1
  %17 = icmp sgt i64 %.02751, 0
  %18 = icmp ugt i64 %.02652.in, 1
  %19 = select i1 %17, i1 %18, i1 false
  br i1 %19, label %.lr.ph53, label %.preheader, !llvm.loop !11

.preheader:                                       ; preds = %15, %.preheader46
  %.054 = add nsw i64 %2, 1
  %.not = icmp slt i64 %.054, %0
  br i1 %.not, label %.lr.ph59, label %.thread

.lr.ph53:                                         ; preds = %.preheader46, %15
  %.02652.in = phi i64 [ %.02652, %15 ], [ %2, %.preheader46 ]
  %.02751 = phi i64 [ %16, %15 ], [ %4, %.preheader46 ]
  %.02652 = add nsw i64 %.02652.in, -1
  %20 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @board, i64 noundef %.02751) #1
  %21 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %.02652) #1
  %22 = load i64, ptr %21, align 8, !tbaa !7
  %23 = icmp eq i64 %22, 1
  br i1 %23, label %.thread, label %15

24:                                               ; preds = %.lr.ph59
  %25 = add nsw i64 %.02556, -1
  %.0 = add nsw i64 %.057, 1
  %26 = icmp slt i64 %.02556, 1
  %27 = icmp sge i64 %.0, %0
  %.not45 = select i1 %26, i1 true, i1 %27
  br i1 %.not45, label %.thread, label %.lr.ph59, !llvm.loop !12

.lr.ph59:                                         ; preds = %.preheader, %24
  %.057 = phi i64 [ %.0, %24 ], [ %.054, %.preheader ]
  %.02556 = phi i64 [ %25, %24 ], [ %4, %.preheader ]
  %28 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @board, i64 noundef %.02556) #1
  %29 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %.057) #1
  %30 = load i64, ptr %29, align 8, !tbaa !7
  %.not68 = icmp ne i64 %30, 1
  br i1 %.not68, label %24, label %.thread

.thread:                                          ; preds = %.lr.ph, %.lr.ph53, %.lr.ph59, %24, %3, %.preheader
  %.3 = phi i1 [ true, %.preheader ], [ true, %3 ], [ %.not68, %24 ], [ %.not68, %.lr.ph59 ], [ false, %.lr.ph53 ], [ false, %.lr.ph ]
  ret i1 %.3
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"long long", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = distinct !{!11, !6}
!12 = distinct !{!12, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass