; LLVM IR from hoodoer/ENNEoS :: enneosEncoder (CInnovation)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SInnovation = type { i32, i32, i32, i32, i32, i32, double, double }
%struct.SNeuronGene = type { i32, i32, i8, double, double, double }
%class.CInnovation = type { %"class.std::vector.5", i32, i32 }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl" }
%"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl" = type { %"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SLinkGene = type <{ i8, [3 x i8], i32, i32, i32, double, i8, [7 x i8] }>

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11CInnovationC2ESt6vectorI9SLinkGeneSaIS1_EES0_I11SNeuronGeneSaIS4_EE(ptr noundef nonnull align 8 dereferenceable(32) %0, ptr noundef %1, ptr noundef %2) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca %struct.SInnovation, align 8
  %9 = alloca %struct.SNeuronGene, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca %struct.SInnovation, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %14 = load ptr, ptr %4, align 8
  %15 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 0
  call void @_ZNSt6vectorI11SInnovationSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #4
  %16 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 1
  store i32 0, ptr %16, align 8, !tbaa !9
  %17 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 2
  store i32 0, ptr %17, align 4, !tbaa !16
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 0, ptr %7, align 4, !tbaa !17
  br label %18

18:                                               ; preds = %37, %3
  %19 = load i32, ptr %7, align 4, !tbaa !17
  %20 = sext i32 %19 to i64
  %21 = call noundef i64 @_ZNKSt6vectorI11SNeuronGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %22 = icmp ult i64 %20, %21
  br i1 %22, label %24, label %23

23:                                               ; preds = %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %44

24:                                               ; preds = %18
  %25 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 0
  call void @llvm.lifetime.start.p0(i64 40, ptr %8) #4
  %26 = load i32, ptr %7, align 4, !tbaa !17
  %27 = sext i32 %26 to i64
  %28 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SNeuronGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %27) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %9, ptr align 8 %28, i64 40, i1 false), !tbaa.struct !18
  %29 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 2
  %30 = load i32, ptr %29, align 4, !tbaa !16
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %29, align 4, !tbaa !16
  %32 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 1
  %33 = load i32, ptr %32, align 8, !tbaa !9
  %34 = add nsw i32 %33, 1
  store i32 %34, ptr %32, align 8, !tbaa !9
  invoke void @_ZN11SInnovationC2E11SNeuronGeneii(ptr noundef nonnull align 8 dereferenceable(40) %8, ptr noundef byval(%struct.SNeuronGene) align 8 %9, i32 noundef %30, i32 noundef %33)
          to label %35 unwind label %40

35:                                               ; preds = %24
  invoke void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backEOS0_(ptr noundef nonnull align 8 dereferenceable(24) %25, ptr noundef nonnull align 8 dereferenceable(40) %8)
          to label %36 unwind label %40

36:                                               ; preds = %35
  call void @llvm.lifetime.end.p0(i64 40, ptr %8) #4
  br label %37

37:                                               ; preds = %36
  %38 = load i32, ptr %7, align 4, !tbaa !17
  %39 = add nsw i32 %38, 1
  store i32 %39, ptr %7, align 4, !tbaa !17
  br label %18, !llvm.loop !25

40:                                               ; preds = %35, %24
  %41 = landingpad { ptr, i32 }
          cleanup
  %42 = extractvalue { ptr, i32 } %41, 0
  store ptr %42, ptr %10, align 8
  %43 = extractvalue { ptr, i32 } %41, 1
  store i32 %43, ptr %11, align 4
  call void @llvm.lifetime.end.p0(i64 40, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %78

44:                                               ; preds = %23
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  store i32 0, ptr %12, align 4, !tbaa !17
  br label %45

45:                                               ; preds = %70, %44
  %46 = load i32, ptr %12, align 4, !tbaa !17
  %47 = sext i32 %46 to i64
  %48 = call noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #4
  %49 = icmp ult i64 %47, %48
  br i1 %49, label %51, label %50

50:                                               ; preds = %45
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  br label %77

51:                                               ; preds = %45
  call void @llvm.lifetime.start.p0(i64 40, ptr %13) #4
  %52 = load i32, ptr %12, align 4, !tbaa !17
  %53 = sext i32 %52 to i64
  %54 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %53) #4
  %55 = getelementptr inbounds %struct.SLinkGene, ptr %54, i32 0, i32 3
  %56 = load i32, ptr %55, align 8, !tbaa !27
  %57 = load i32, ptr %12, align 4, !tbaa !17
  %58 = sext i32 %57 to i64
  %59 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %58) #4
  %60 = getelementptr inbounds %struct.SLinkGene, ptr %59, i32 0, i32 4
  %61 = load i32, ptr %60, align 4, !tbaa !29
  %62 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 2
  %63 = load i32, ptr %62, align 4, !tbaa !16
  invoke void @_ZN11SInnovationC2Eii10innov_typei(ptr noundef nonnull align 8 dereferenceable(40) %13, i32 noundef %56, i32 noundef %61, i32 noundef 1, i32 noundef %63)
          to label %64 unwind label %73

64:                                               ; preds = %51
  %65 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 0
  invoke void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backERKS0_(ptr noundef nonnull align 8 dereferenceable(24) %65, ptr noundef nonnull align 8 dereferenceable(40) %13)
          to label %66 unwind label %73

66:                                               ; preds = %64
  %67 = getelementptr inbounds %class.CInnovation, ptr %14, i32 0, i32 2
  %68 = load i32, ptr %67, align 4, !tbaa !16
  %69 = add nsw i32 %68, 1
  store i32 %69, ptr %67, align 4, !tbaa !16
  call void @llvm.lifetime.end.p0(i64 40, ptr %13) #4
  br label %70

70:                                               ; preds = %66
  %71 = load i32, ptr %12, align 4, !tbaa !17
  %72 = add nsw i32 %71, 1
  store i32 %72, ptr %12, align 4, !tbaa !17
  br label %45, !llvm.loop !30

73:                                               ; preds = %64, %51
  %74 = landingpad { ptr, i32 }
          cleanup
  %75 = extractvalue { ptr, i32 } %74, 0
  store ptr %75, ptr %10, align 8
  %76 = extractvalue { ptr, i32 } %74, 1
  store i32 %76, ptr %11, align 4
  call void @llvm.lifetime.end.p0(i64 40, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  br label %78

77:                                               ; preds = %50
  ret void

78:                                               ; preds = %73, %40
  call void @_ZNSt6vectorI11SInnovationSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #4
  br label %79

79:                                               ; preds = %78
  %80 = load ptr, ptr %10, align 8
  %81 = load i32, ptr %11, align 4
  %82 = insertvalue { ptr, i32 } poison, ptr %80, 0
  %83 = insertvalue { ptr, i32 } %82, i32 %81, 1
  resume { ptr, i32 } %83
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI11SNeuronGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backEOS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(40)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SNeuronGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN11SInnovationC2E11SNeuronGeneii(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef byval(%struct.SNeuronGene) align 8, i32 noundef, i32 noundef) unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN11SInnovationC2Eii10innov_typei(ptr noundef nonnull align 8 dereferenceable(40), i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backERKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(40)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !15, i64 24}
!10 = !{!"_ZTS11CInnovation", !11, i64 0, !15, i64 24, !15, i64 28}
!11 = !{!"_ZTSSt6vectorI11SInnovationSaIS0_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseI11SInnovationSaIS0_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseI11SInnovationSaIS0_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseI11SInnovationSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!15 = !{!"int", !7, i64 0}
!16 = !{!10, !15, i64 28}
!17 = !{!15, !15, i64 0}
!18 = !{i64 0, i64 4, !17, i64 4, i64 4, !19, i64 8, i64 1, !21, i64 16, i64 8, !23, i64 24, i64 8, !23, i64 32, i64 8, !23}
!19 = !{!20, !20, i64 0}
!20 = !{!"_ZTS11neuron_type", !7, i64 0}
!21 = !{!22, !22, i64 0}
!22 = !{!"bool", !7, i64 0}
!23 = !{!24, !24, i64 0}
!24 = !{!"double", !7, i64 0}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = !{!28, !15, i64 8}
!28 = !{!"_ZTS9SLinkGene", !22, i64 0, !15, i64 4, !15, i64 8, !15, i64 12, !24, i64 16, !22, i64 24}
!29 = !{!28, !15, i64 12}
!30 = distinct !{!30, !26}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SInnovation = type { i32, i32, i32, i32, i32, i32, double, double }
%struct.SNeuronGene = type { i32, i32, i8, double, double, double }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11CInnovationC2ESt6vectorI9SLinkGeneSaIS1_EES0_I11SNeuronGeneSaIS4_EE(ptr noundef nonnull align 8 dereferenceable(32) %0, ptr noundef %1, ptr noundef %2) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca %struct.SInnovation, align 8
  %5 = alloca %struct.SNeuronGene, align 8
  %6 = alloca %struct.SInnovation, align 8
  tail call void @_ZNSt6vectorI11SInnovationSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  %7 = getelementptr inbounds i8, ptr %0, i64 24
  store i32 0, ptr %7, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %0, i64 28
  store i32 0, ptr %8, align 4, !tbaa !15
  %9 = tail call noundef i64 @_ZNKSt6vectorI11SNeuronGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %.not = icmp eq i64 %9, 0
  br i1 %.not, label %.preheader, label %.lr.ph

.preheader:                                       ; preds = %16, %3
  %10 = call noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #4
  %.not18 = icmp eq i64 %10, 0
  br i1 %.not18, label %._crit_edge, label %.lr.ph17

.lr.ph:                                           ; preds = %3, %16
  %indvars.iv = phi i64 [ %indvars.iv.next, %16 ], [ 0, %3 ]
  call void @llvm.lifetime.start.p0(i64 40, ptr nonnull %4) #4
  %11 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SNeuronGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv) #4
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(40) %5, ptr noundef nonnull align 8 dereferenceable(40) %11, i64 40, i1 false), !tbaa.struct !16
  %12 = load i32, ptr %8, align 4, !tbaa !15
  %13 = add nsw i32 %12, 1
  store i32 %13, ptr %8, align 4, !tbaa !15
  %14 = load i32, ptr %7, align 8, !tbaa !5
  %15 = add nsw i32 %14, 1
  store i32 %15, ptr %7, align 8, !tbaa !5
  call void @_ZN11SInnovationC2E11SNeuronGeneii(ptr noundef nonnull align 8 dereferenceable(40) %4, ptr noundef nonnull byval(%struct.SNeuronGene) align 8 %5, i32 noundef %12, i32 noundef %14)
  invoke void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backEOS0_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(40) %4)
          to label %16 unwind label %19

16:                                               ; preds = %.lr.ph
  call void @llvm.lifetime.end.p0(i64 40, ptr nonnull %4) #4
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %17 = call noundef i64 @_ZNKSt6vectorI11SNeuronGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %18 = icmp ugt i64 %17, %indvars.iv.next
  br i1 %18, label %.lr.ph, label %.preheader, !llvm.loop !24

19:                                               ; preds = %.lr.ph
  %20 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 40, ptr nonnull %4) #4
  br label %35

._crit_edge:                                      ; preds = %28, %.preheader
  ret void

.lr.ph17:                                         ; preds = %.preheader, %28
  %indvars.iv20 = phi i64 [ %indvars.iv.next21, %28 ], [ 0, %.preheader ]
  call void @llvm.lifetime.start.p0(i64 40, ptr nonnull %6) #4
  %21 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv20) #4
  %22 = getelementptr inbounds i8, ptr %21, i64 8
  %23 = load i32, ptr %22, align 8, !tbaa !26
  %24 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv20) #4
  %25 = getelementptr inbounds i8, ptr %24, i64 12
  %26 = load i32, ptr %25, align 4, !tbaa !28
  %27 = load i32, ptr %8, align 4, !tbaa !15
  call void @_ZN11SInnovationC2Eii10innov_typei(ptr noundef nonnull align 8 dereferenceable(40) %6, i32 noundef %23, i32 noundef %26, i32 noundef 1, i32 noundef %27)
  invoke void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backERKS0_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(40) %6)
          to label %28 unwind label %33

28:                                               ; preds = %.lr.ph17
  %29 = load i32, ptr %8, align 4, !tbaa !15
  %30 = add nsw i32 %29, 1
  store i32 %30, ptr %8, align 4, !tbaa !15
  call void @llvm.lifetime.end.p0(i64 40, ptr nonnull %6) #4
  %indvars.iv.next21 = add nuw nsw i64 %indvars.iv20, 1
  %31 = call noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #4
  %32 = icmp ugt i64 %31, %indvars.iv.next21
  br i1 %32, label %.lr.ph17, label %._crit_edge, !llvm.loop !29

33:                                               ; preds = %.lr.ph17
  %34 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 40, ptr nonnull %6) #4
  br label %35

35:                                               ; preds = %33, %19
  %.pn = phi { ptr, i32 } [ %20, %19 ], [ %34, %33 ]
  call void @_ZNSt6vectorI11SInnovationSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  resume { ptr, i32 } %.pn
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI11SNeuronGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backEOS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SNeuronGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN11SInnovationC2E11SNeuronGeneii(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef byval(%struct.SNeuronGene) align 8, i32 noundef, i32 noundef) unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI9SLinkGeneSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI9SLinkGeneSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN11SInnovationC2Eii10innov_typei(ptr noundef nonnull align 8 dereferenceable(40), i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EE9push_backERKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI11SInnovationSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 24}
!6 = !{!"_ZTS11CInnovation", !7, i64 0, !14, i64 24, !14, i64 28}
!7 = !{!"_ZTSSt6vectorI11SInnovationSaIS0_EE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseI11SInnovationSaIS0_EE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseI11SInnovationSaIS0_EE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseI11SInnovationSaIS0_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"int", !12, i64 0}
!15 = !{!6, !14, i64 28}
!16 = !{i64 0, i64 4, !17, i64 4, i64 4, !18, i64 8, i64 1, !20, i64 16, i64 8, !22, i64 24, i64 8, !22, i64 32, i64 8, !22}
!17 = !{!14, !14, i64 0}
!18 = !{!19, !19, i64 0}
!19 = !{!"_ZTS11neuron_type", !12, i64 0}
!20 = !{!21, !21, i64 0}
!21 = !{!"bool", !12, i64 0}
!22 = !{!23, !23, i64 0}
!23 = !{!"double", !12, i64 0}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!27, !14, i64 8}
!27 = !{!"_ZTS9SLinkGene", !21, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !23, i64 16, !21, i64 24}
!28 = !{!27, !14, i64 12}
!29 = distinct !{!29, !25}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass