; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_simcontext.ll (ZN7sc_core13sc_simcontext5cleanEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext5cleanEv(ptr noundef nonnull align 8 dereferenceable(344) %0) #2 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  %5 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 0
  %6 = load ptr, ptr %5, align 8, !tbaa !9
  %7 = icmp eq ptr %6, null
  br i1 %7, label %9, label %8

8:                                                ; preds = %1
  call void @_ZN7sc_core17sc_object_managerD1Ev(ptr noundef nonnull align 8 dereferenceable(105) %6) #6
  call void @_ZdlPvm(ptr noundef %6, i64 noundef 112) #7
  br label %9

9:                                                ; preds = %8, %1
  %10 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 1
  %11 = load ptr, ptr %10, align 8, !tbaa !35
  %12 = icmp eq ptr %11, null
  br i1 %12, label %14, label %13

13:                                               ; preds = %9
  call void @_ZN7sc_core18sc_module_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40) %11) #6
  call void @_ZdlPvm(ptr noundef %11, i64 noundef 40) #7
  br label %14

14:                                               ; preds = %13, %9
  %15 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 2
  %16 = load ptr, ptr %15, align 8, !tbaa !36
  %17 = icmp eq ptr %16, null
  br i1 %17, label %19, label %18

18:                                               ; preds = %14
  call void @_ZN7sc_core16sc_port_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40) %16) #6
  call void @_ZdlPvm(ptr noundef %16, i64 noundef 40) #7
  br label %19

19:                                               ; preds = %18, %14
  %20 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 3
  %21 = load ptr, ptr %20, align 8, !tbaa !37
  %22 = icmp eq ptr %21, null
  br i1 %22, label %24, label %23

23:                                               ; preds = %19
  call void @_ZN7sc_core18sc_export_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40) %21) #6
  call void @_ZdlPvm(ptr noundef %21, i64 noundef 40) #7
  br label %24

24:                                               ; preds = %23, %19
  %25 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 4
  %26 = load ptr, ptr %25, align 8, !tbaa !38
  %27 = icmp eq ptr %26, null
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  call void @_ZN7sc_core24sc_prim_channel_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(56) %26) #6
  call void @_ZdlPvm(ptr noundef %26, i64 noundef 56) #7
  br label %29

29:                                               ; preds = %28, %24
  %30 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 5
  %31 = load ptr, ptr %30, align 8, !tbaa !39
  %32 = icmp eq ptr %31, null
  br i1 %32, label %34, label %33

33:                                               ; preds = %29
  call void @_ZN7sc_core26sc_phase_callback_registryD1Ev(ptr noundef nonnull align 1 dereferenceable(1) %31) #6
  call void @_ZdlPvm(ptr noundef %31, i64 noundef 1) #7
  br label %34

34:                                               ; preds = %33, %29
  %35 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 6
  %36 = load ptr, ptr %35, align 8, !tbaa !40
  %37 = icmp eq ptr %36, null
  br i1 %37, label %39, label %38

38:                                               ; preds = %34
  call void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %36) #6
  call void @_ZdlPvm(ptr noundef %36, i64 noundef 8248) #7
  br label %39

39:                                               ; preds = %38, %34
  %40 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 7
  %41 = load ptr, ptr %40, align 8, !tbaa !41
  %42 = icmp eq ptr %41, null
  br i1 %42, label %44, label %43

43:                                               ; preds = %39
  call void @_ZN7sc_core16sc_process_tableD1Ev(ptr noundef nonnull align 8 dereferenceable(16) %41) #6
  call void @_ZdlPvm(ptr noundef %41, i64 noundef 16) #7
  br label %44

44:                                               ; preds = %43, %39
  %45 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 14
  call void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef 0)
  %46 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 15
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef 0)
  %47 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 16
  %48 = load ptr, ptr %47, align 8, !tbaa !42
  %49 = icmp eq ptr %48, null
  br i1 %49, label %51, label %50

50:                                               ; preds = %44
  call void @_ZN7sc_core11sc_ppq_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %48) #6
  call void @_ZdlPvm(ptr noundef %48, i64 noundef 24) #7
  br label %51

51:                                               ; preds = %50, %44
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #6
  %52 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 17
  %53 = call noundef i64 @_ZNKSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %52) #6
  %54 = sub i64 %53, 1
  %55 = trunc i64 %54 to i32
  store i32 %55, ptr %3, align 4, !tbaa !43
  br label %56

56:                                               ; preds = %72, %51
  %57 = load i32, ptr %3, align 4, !tbaa !43
  %58 = icmp sge i32 %57, 0
  br i1 %58, label %60, label %59

59:                                               ; preds = %56
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #6
  br label %75

60:                                               ; preds = %56
  %61 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 17
  %62 = load i32, ptr %3, align 4, !tbaa !43
  %63 = sext i32 %62 to i64
  %64 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %61, i64 noundef %63) #6
  %65 = load ptr, ptr %64, align 8, !tbaa !5
  %66 = icmp eq ptr %65, null
  br i1 %66, label %71, label %67

67:                                               ; preds = %60
  %68 = load ptr, ptr %65, align 8, !tbaa !44
  %69 = getelementptr inbounds ptr, ptr %68, i64 32
  %70 = load ptr, ptr %69, align 8
  call void %70(ptr noundef nonnull align 8 dereferenceable(8) %65) #6
  br label %71

71:                                               ; preds = %67, %60
  br label %72

72:                                               ; preds = %71
  %73 = load i32, ptr %3, align 4, !tbaa !43
  %74 = add nsw i32 %73, -1
  store i32 %74, ptr %3, align 4, !tbaa !43
  br label %56, !llvm.loop !46

75:                                               ; preds = %59
  %76 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 17
  call void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %76, i64 noundef 0)
  %77 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 19
  %78 = load ptr, ptr %77, align 8, !tbaa !48
  %79 = icmp eq ptr %78, null
  br i1 %79, label %81, label %80

80:                                               ; preds = %75
  call void @_ZN7sc_core11sc_runnableD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %78) #6
  call void @_ZdlPvm(ptr noundef %78, i64 noundef 48) #7
  br label %81

81:                                               ; preds = %80, %75
  %82 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 20
  %83 = load ptr, ptr %82, align 8, !tbaa !49
  %84 = icmp eq ptr %83, null
  br i1 %84, label %86, label %85

85:                                               ; preds = %81
  call void @_ZN7sc_core13sc_plist_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(16) %83) #6
  call void @_ZdlPvm(ptr noundef %83, i64 noundef 16) #7
  br label %86

86:                                               ; preds = %85, %81
  %87 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 21
  %88 = load ptr, ptr %87, align 8, !tbaa !50
  %89 = icmp eq ptr %88, null
  br i1 %89, label %91, label %90

90:                                               ; preds = %86
  call void @_ZN7sc_core14sc_time_paramsD1Ev(ptr noundef nonnull align 8 dereferenceable(25) %88) #6
  call void @_ZdlPvm(ptr noundef %88, i64 noundef 32) #7
  br label %91

91:                                               ; preds = %90, %86
  %92 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 37
  %93 = load ptr, ptr %92, align 8, !tbaa !51
  %94 = icmp eq ptr %93, null
  br i1 %94, label %99, label %95

95:                                               ; preds = %91
  %96 = load ptr, ptr %93, align 8, !tbaa !44
  %97 = getelementptr inbounds ptr, ptr %96, i64 1
  %98 = load ptr, ptr %97, align 8
  call void %98(ptr noundef nonnull align 8 dereferenceable(16) %93) #6
  br label %99

99:                                               ; preds = %95, %91
  %100 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %4, i32 0, i32 32
  %101 = load ptr, ptr %100, align 8, !tbaa !52
  %102 = icmp eq ptr %101, null
  br i1 %102, label %107, label %103

103:                                              ; preds = %99
  %104 = load ptr, ptr %101, align 8, !tbaa !44
  %105 = getelementptr inbounds ptr, ptr %104, i64 1
  %106 = load ptr, ptr %105, align 8
  call void %106(ptr noundef nonnull align 8 dereferenceable(80) %101) #6
  br label %107

107:                                              ; preds = %103, %99
  ret void
}

; Function Attrs: nounwind
declare void @_ZN7sc_core17sc_object_managerD1Ev(ptr noundef nonnull align 8 dereferenceable(105)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core18sc_module_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core16sc_port_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core18sc_export_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core24sc_prim_channel_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(56)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core26sc_phase_callback_registryD1Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_ppq_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core11sc_runnableD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #5 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core13sc_plist_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_time_paramsD1Ev(ptr noundef nonnull align 8 dereferenceable(25)) unnamed_addr #3

declare void @_ZN7sc_core16sc_process_tableD1Ev(ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !11, i64 64, !6, i64 80, !13, i64 88, !14, i64 92, !15, i64 96, !19, i64 120, !23, i64 144, !19, i64 168, !6, i64 192, !27, i64 200, !13, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !31, i64 256, !31, i64 264, !6, i64 272, !32, i64 280, !32, i64 288, !13, i64 296, !13, i64 297, !13, i64 298, !13, i64 299, !33, i64 300, !6, i64 304, !13, i64 312, !13, i64 313, !34, i64 316, !13, i64 320, !6, i64 328, !6, i64 336}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !12, i64 8}
!12 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core7sc_timeE", !32, i64 0}
!32 = !{!"long long", !7, i64 0}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!35 = !{!10, !6, i64 8}
!36 = !{!10, !6, i64 16}
!37 = !{!10, !6, i64 24}
!38 = !{!10, !6, i64 32}
!39 = !{!10, !6, i64 40}
!40 = !{!10, !6, i64 48}
!41 = !{!10, !6, i64 56}
!42 = !{!10, !6, i64 192}
!43 = !{!14, !14, i64 0}
!44 = !{!45, !45, i64 0}
!45 = !{!"vtable pointer", !8, i64 0}
!46 = distinct !{!46, !47}
!47 = !{!"llvm.loop.mustprogress"}
!48 = !{!10, !6, i64 232}
!49 = !{!10, !6, i64 240}
!50 = !{!10, !6, i64 248}
!51 = !{!10, !6, i64 328}
!52 = !{!10, !6, i64 304}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext5cleanEv(ptr noundef nonnull align 8 dereferenceable(344) %0) local_unnamed_addr #1 align 2 {
  %2 = load ptr, ptr %0, align 8, !tbaa !5
  %3 = icmp eq ptr %2, null
  br i1 %3, label %5, label %4

4:                                                ; preds = %1
  tail call void @_ZN7sc_core17sc_object_managerD1Ev(ptr noundef nonnull align 8 dereferenceable(105) %2) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %2, i64 noundef 112) #6
  br label %5

5:                                                ; preds = %4, %1
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = load ptr, ptr %6, align 8, !tbaa !34
  %8 = icmp eq ptr %7, null
  br i1 %8, label %10, label %9

9:                                                ; preds = %5
  tail call void @_ZN7sc_core18sc_module_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40) %7) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %7, i64 noundef 40) #6
  br label %10

10:                                               ; preds = %9, %5
  %11 = getelementptr inbounds i8, ptr %0, i64 16
  %12 = load ptr, ptr %11, align 8, !tbaa !35
  %13 = icmp eq ptr %12, null
  br i1 %13, label %15, label %14

14:                                               ; preds = %10
  tail call void @_ZN7sc_core16sc_port_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40) %12) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %12, i64 noundef 40) #6
  br label %15

15:                                               ; preds = %14, %10
  %16 = getelementptr inbounds i8, ptr %0, i64 24
  %17 = load ptr, ptr %16, align 8, !tbaa !36
  %18 = icmp eq ptr %17, null
  br i1 %18, label %20, label %19

19:                                               ; preds = %15
  tail call void @_ZN7sc_core18sc_export_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40) %17) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %17, i64 noundef 40) #6
  br label %20

20:                                               ; preds = %19, %15
  %21 = getelementptr inbounds i8, ptr %0, i64 32
  %22 = load ptr, ptr %21, align 8, !tbaa !37
  %23 = icmp eq ptr %22, null
  br i1 %23, label %25, label %24

24:                                               ; preds = %20
  tail call void @_ZN7sc_core24sc_prim_channel_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(56) %22) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %22, i64 noundef 56) #6
  br label %25

25:                                               ; preds = %24, %20
  %26 = getelementptr inbounds i8, ptr %0, i64 40
  %27 = load ptr, ptr %26, align 8, !tbaa !38
  %28 = icmp eq ptr %27, null
  br i1 %28, label %30, label %29

29:                                               ; preds = %25
  tail call void @_ZN7sc_core26sc_phase_callback_registryD1Ev(ptr noundef nonnull align 1 dereferenceable(1) %27) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %27, i64 noundef 1) #6
  br label %30

30:                                               ; preds = %29, %25
  %31 = getelementptr inbounds i8, ptr %0, i64 48
  %32 = load ptr, ptr %31, align 8, !tbaa !39
  %33 = icmp eq ptr %32, null
  br i1 %33, label %35, label %34

34:                                               ; preds = %30
  tail call void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %32) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %32, i64 noundef 8248) #6
  br label %35

35:                                               ; preds = %34, %30
  %36 = getelementptr inbounds i8, ptr %0, i64 56
  %37 = load ptr, ptr %36, align 8, !tbaa !40
  %38 = icmp eq ptr %37, null
  br i1 %38, label %40, label %39

39:                                               ; preds = %35
  tail call void @_ZN7sc_core16sc_process_tableD1Ev(ptr noundef nonnull align 8 dereferenceable(16) %37) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %37, i64 noundef 16) #6
  br label %40

40:                                               ; preds = %39, %35
  %41 = getelementptr inbounds i8, ptr %0, i64 144
  tail call void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef 0)
  %42 = getelementptr inbounds i8, ptr %0, i64 168
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef 0)
  %43 = getelementptr inbounds i8, ptr %0, i64 192
  %44 = load ptr, ptr %43, align 8, !tbaa !41
  %45 = icmp eq ptr %44, null
  br i1 %45, label %47, label %46

46:                                               ; preds = %40
  tail call void @_ZN7sc_core11sc_ppq_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %44) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %44, i64 noundef 24) #6
  br label %47

47:                                               ; preds = %46, %40
  %48 = getelementptr inbounds i8, ptr %0, i64 200
  %49 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %48) #5
  %50 = trunc i64 %49 to i32
  %.018 = add i32 %50, -1
  %51 = icmp sgt i32 %.018, -1
  br i1 %51, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %47
  %52 = zext nneg i32 %.018 to i64
  br label %.lr.ph

._crit_edge:                                      ; preds = %63, %47
  tail call void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef 0)
  %53 = getelementptr inbounds i8, ptr %0, i64 232
  %54 = load ptr, ptr %53, align 8, !tbaa !42
  %55 = icmp eq ptr %54, null
  br i1 %55, label %66, label %65

.lr.ph:                                           ; preds = %.lr.ph.preheader, %63
  %indvars.iv = phi i64 [ %52, %.lr.ph.preheader ], [ %indvars.iv.next, %63 ]
  %56 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %indvars.iv) #5
  %57 = load ptr, ptr %56, align 8, !tbaa !43
  %58 = icmp eq ptr %57, null
  br i1 %58, label %63, label %59

59:                                               ; preds = %.lr.ph
  %60 = load ptr, ptr %57, align 8, !tbaa !44
  %61 = getelementptr inbounds i8, ptr %60, i64 256
  %62 = load ptr, ptr %61, align 8
  tail call void %62(ptr noundef nonnull align 8 dereferenceable(8) %57) #5
  br label %63

63:                                               ; preds = %.lr.ph, %59
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %64 = icmp sgt i64 %indvars.iv, 0
  br i1 %64, label %.lr.ph, label %._crit_edge, !llvm.loop !46

65:                                               ; preds = %._crit_edge
  tail call void @_ZN7sc_core11sc_runnableD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %54) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %54, i64 noundef 48) #6
  br label %66

66:                                               ; preds = %65, %._crit_edge
  %67 = getelementptr inbounds i8, ptr %0, i64 240
  %68 = load ptr, ptr %67, align 8, !tbaa !48
  %69 = icmp eq ptr %68, null
  br i1 %69, label %71, label %70

70:                                               ; preds = %66
  tail call void @_ZN7sc_core13sc_plist_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(16) %68) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %68, i64 noundef 16) #6
  br label %71

71:                                               ; preds = %70, %66
  %72 = getelementptr inbounds i8, ptr %0, i64 248
  %73 = load ptr, ptr %72, align 8, !tbaa !49
  %74 = icmp eq ptr %73, null
  br i1 %74, label %76, label %75

75:                                               ; preds = %71
  tail call void @_ZN7sc_core14sc_time_paramsD1Ev(ptr noundef nonnull align 8 dereferenceable(25) %73) #5
  tail call void @_ZdlPvm(ptr noundef nonnull %73, i64 noundef 32) #6
  br label %76

76:                                               ; preds = %75, %71
  %77 = getelementptr inbounds i8, ptr %0, i64 328
  %78 = load ptr, ptr %77, align 8, !tbaa !50
  %79 = icmp eq ptr %78, null
  br i1 %79, label %84, label %80

80:                                               ; preds = %76
  %81 = load ptr, ptr %78, align 8, !tbaa !44
  %82 = getelementptr inbounds i8, ptr %81, i64 8
  %83 = load ptr, ptr %82, align 8
  tail call void %83(ptr noundef nonnull align 8 dereferenceable(16) %78) #5
  br label %84

84:                                               ; preds = %80, %76
  %85 = getelementptr inbounds i8, ptr %0, i64 304
  %86 = load ptr, ptr %85, align 8, !tbaa !51
  %87 = icmp eq ptr %86, null
  br i1 %87, label %92, label %88

88:                                               ; preds = %84
  %89 = load ptr, ptr %86, align 8, !tbaa !44
  %90 = getelementptr inbounds i8, ptr %89, i64 8
  %91 = load ptr, ptr %90, align 8
  tail call void %91(ptr noundef nonnull align 8 dereferenceable(80) %86) #5
  br label %92

92:                                               ; preds = %88, %84
  ret void
}

; Function Attrs: nounwind
declare void @_ZN7sc_core17sc_object_managerD1Ev(ptr noundef nonnull align 8 dereferenceable(105)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core18sc_module_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core16sc_port_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core18sc_export_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(40)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core24sc_prim_channel_registryD1Ev(ptr noundef nonnull align 8 dereferenceable(56)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core26sc_phase_callback_registryD1Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_ppq_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core11sc_runnableD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #4 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core13sc_plist_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_time_paramsD1Ev(ptr noundef nonnull align 8 dereferenceable(25)) unnamed_addr #2

declare void @_ZN7sc_core16sc_process_tableD1Ev(ptr) local_unnamed_addr

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{!6, !7, i64 8}
!35 = !{!6, !7, i64 16}
!36 = !{!6, !7, i64 24}
!37 = !{!6, !7, i64 32}
!38 = !{!6, !7, i64 40}
!39 = !{!6, !7, i64 48}
!40 = !{!6, !7, i64 56}
!41 = !{!6, !7, i64 192}
!42 = !{!6, !7, i64 232}
!43 = !{!7, !7, i64 0}
!44 = !{!45, !45, i64 0}
!45 = !{!"vtable pointer", !9, i64 0}
!46 = distinct !{!46, !47}
!47 = !{!"llvm.loop.mustprogress"}
!48 = !{!6, !7, i64 240}
!49 = !{!6, !7, i64 248}
!50 = !{!6, !7, i64 328}
!51 = !{!6, !7, i64 304}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass