; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_process.ll (ZN7sc_core12sc_process_b13reset_changedEbb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_b" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.18", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.23", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8, [3 x i8] }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core32sc_allow_process_control_cornersE = external global i8, align 1
@_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E = external constant [0 x i8], align 1
@.str.16 = external hidden unnamed_addr constant [49 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357), ptr noundef, ptr noundef) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_process_b13reset_changedEbb(ptr noundef nonnull align 8 dereferenceable(357) %0, i1 noundef zeroext %1, i1 noundef zeroext %2) #0 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  %7 = zext i1 %1 to i8
  store i8 %7, ptr %5, align 1, !tbaa !9
  %8 = zext i1 %2 to i8
  store i8 %8, ptr %6, align 1, !tbaa !9
  %9 = load ptr, ptr %4, align 8
  %10 = load i8, ptr @_ZN7sc_core32sc_allow_process_control_cornersE, align 1, !tbaa !9, !range !11, !noundef !12
  %11 = trunc i8 %10 to i1
  br i1 %11, label %21, label %12

12:                                               ; preds = %3
  %13 = load i8, ptr %5, align 1, !tbaa !9, !range !11, !noundef !12
  %14 = trunc i8 %13 to i1
  br i1 %14, label %21, label %15

15:                                               ; preds = %12
  %16 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 29
  %17 = load i32, ptr %16, align 8, !tbaa !13
  %18 = and i32 %17, 4
  %19 = icmp ne i32 %18, 0
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  call void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357) %9, ptr noundef @_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E, ptr noundef @.str.16)
  br label %21

21:                                               ; preds = %20, %15, %12, %3
  %22 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 29
  %23 = load i32, ptr %22, align 8, !tbaa !13
  %24 = and i32 %23, 8
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  br label %90

27:                                               ; preds = %21
  %28 = load i8, ptr %6, align 1, !tbaa !9, !range !11, !noundef !12
  %29 = trunc i8 %28 to i1
  br i1 %29, label %30, label %56

30:                                               ; preds = %27
  %31 = load i8, ptr %5, align 1, !tbaa !9, !range !11, !noundef !12
  %32 = trunc i8 %31 to i1
  br i1 %32, label %33, label %44

33:                                               ; preds = %30
  %34 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 4
  %35 = load i32, ptr %34, align 8, !tbaa !39
  %36 = add nsw i32 %35, 1
  store i32 %36, ptr %34, align 8, !tbaa !39
  %37 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %38 = call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %37)
  br i1 %38, label %39, label %43

39:                                               ; preds = %33
  %40 = load ptr, ptr %9, align 8, !tbaa !40
  %41 = getelementptr inbounds ptr, ptr %40, i64 22
  %42 = load ptr, ptr %41, align 8
  call void %42(ptr noundef nonnull align 8 dereferenceable(357) %9, i1 noundef zeroext true)
  br label %43

43:                                               ; preds = %39, %33
  br label %55

44:                                               ; preds = %30
  %45 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 5
  %46 = load i32, ptr %45, align 4, !tbaa !42
  %47 = add nsw i32 %46, 1
  store i32 %47, ptr %45, align 4, !tbaa !42
  %48 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %49 = call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %48)
  br i1 %49, label %50, label %54

50:                                               ; preds = %44
  %51 = load ptr, ptr %9, align 8, !tbaa !40
  %52 = getelementptr inbounds ptr, ptr %51, i64 22
  %53 = load ptr, ptr %52, align 8
  call void %53(ptr noundef nonnull align 8 dereferenceable(357) %9, i1 noundef zeroext false)
  br label %54

54:                                               ; preds = %50, %44
  br label %55

55:                                               ; preds = %54, %43
  br label %68

56:                                               ; preds = %27
  %57 = load i8, ptr %5, align 1, !tbaa !9, !range !11, !noundef !12
  %58 = trunc i8 %57 to i1
  br i1 %58, label %59, label %63

59:                                               ; preds = %56
  %60 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 4
  %61 = load i32, ptr %60, align 8, !tbaa !39
  %62 = add nsw i32 %61, -1
  store i32 %62, ptr %60, align 8, !tbaa !39
  br label %67

63:                                               ; preds = %56
  %64 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 5
  %65 = load i32, ptr %64, align 4, !tbaa !42
  %66 = add nsw i32 %65, -1
  store i32 %66, ptr %64, align 4, !tbaa !42
  br label %67

67:                                               ; preds = %63, %59
  br label %68

68:                                               ; preds = %67, %55
  %69 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 36
  %70 = load i32, ptr %69, align 8, !tbaa !43
  %71 = icmp eq i32 %70, 4
  br i1 %71, label %76, label %72

72:                                               ; preds = %68
  %73 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 36
  %74 = load i32, ptr %73, align 8, !tbaa !43
  %75 = icmp eq i32 %74, 3
  br i1 %75, label %76, label %90

76:                                               ; preds = %72, %68
  %77 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 4
  %78 = load i32, ptr %77, align 8, !tbaa !39
  %79 = icmp eq i32 %78, 0
  br i1 %79, label %80, label %90

80:                                               ; preds = %76
  %81 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 5
  %82 = load i32, ptr %81, align 4, !tbaa !42
  %83 = icmp eq i32 %82, 0
  br i1 %83, label %84, label %90

84:                                               ; preds = %80
  %85 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 32
  %86 = load i8, ptr %85, align 8, !tbaa !44, !range !11, !noundef !12
  %87 = trunc i8 %86 to i1
  br i1 %87, label %90, label %88

88:                                               ; preds = %84
  %89 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 36
  store i32 0, ptr %89, align 8, !tbaa !43
  br label %90

90:                                               ; preds = %88, %84, %80, %76, %72, %26
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!14, !27, i64 280}
!14 = !{!"_ZTSN7sc_core12sc_process_bE", !15, i64 0, !6, i64 112, !27, i64 120, !27, i64 124, !27, i64 128, !27, i64 132, !10, i64 136, !10, i64 137, !6, i64 144, !27, i64 152, !6, i64 160, !6, i64 168, !10, i64 176, !10, i64 177, !10, i64 178, !10, i64 179, !6, i64 184, !6, i64 192, !28, i64 200, !27, i64 204, !29, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !27, i64 280, !33, i64 288, !10, i64 312, !6, i64 320, !6, i64 328, !37, i64 336, !10, i64 340, !6, i64 344, !38, i64 352, !10, i64 356}
!15 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !16, i64 16, !20, i64 40, !24, i64 64, !6, i64 96, !6, i64 104}
!16 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !25, i64 0, !26, i64 8, !7, i64 16}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!26 = !{!"long", !7, i64 0}
!27 = !{!"int", !7, i64 0}
!28 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!29 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!38 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!39 = !{!14, !27, i64 128}
!40 = !{!41, !41, i64 0}
!41 = !{!"vtable pointer", !8, i64 0}
!42 = !{!14, !27, i64 132}
!43 = !{!14, !37, i64 336}
!44 = !{!14, !10, i64 312}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core32sc_allow_process_control_cornersE = external local_unnamed_addr global i8, align 1
@_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E = external constant [0 x i8], align 1
@.str.16 = external hidden unnamed_addr constant [49 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357), ptr noundef, ptr noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_process_b13reset_changedEbb(ptr noundef nonnull align 8 dereferenceable(357) %0, i1 noundef zeroext %1, i1 noundef zeroext %2) local_unnamed_addr #0 align 2 {
  %4 = load i8, ptr @_ZN7sc_core32sc_allow_process_control_cornersE, align 1, !tbaa !5, !range !9, !noundef !10
  %5 = trunc nuw i8 %4 to i1
  %brmerge = or i1 %5, %1
  br i1 %brmerge, label %11, label %6

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 280
  %8 = load i32, ptr %7, align 8, !tbaa !11
  %9 = and i32 %8, 4
  %.not = icmp eq i32 %9, 0
  br i1 %.not, label %11, label %10

10:                                               ; preds = %6
  tail call void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357) %0, ptr noundef nonnull @_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E, ptr noundef nonnull @.str.16)
  br label %11

11:                                               ; preds = %3, %10, %6
  %12 = getelementptr inbounds i8, ptr %0, i64 280
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = and i32 %13, 8
  %.not4 = icmp eq i32 %14, 0
  br i1 %.not4, label %15, label %61

15:                                               ; preds = %11
  br i1 %2, label %16, label %37

16:                                               ; preds = %15
  br i1 %1, label %17, label %27

17:                                               ; preds = %16
  %18 = getelementptr inbounds i8, ptr %0, i64 128
  %19 = load i32, ptr %18, align 8, !tbaa !38
  %20 = add nsw i32 %19, 1
  store i32 %20, ptr %18, align 8, !tbaa !38
  %21 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %22 = tail call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %21)
  br i1 %22, label %23, label %46

23:                                               ; preds = %17
  %24 = load ptr, ptr %0, align 8, !tbaa !39
  %25 = getelementptr inbounds i8, ptr %24, i64 176
  %26 = load ptr, ptr %25, align 8
  tail call void %26(ptr noundef nonnull align 8 dereferenceable(357) %0, i1 noundef zeroext true)
  br label %46

27:                                               ; preds = %16
  %28 = getelementptr inbounds i8, ptr %0, i64 132
  %29 = load i32, ptr %28, align 4, !tbaa !41
  %30 = add nsw i32 %29, 1
  store i32 %30, ptr %28, align 4, !tbaa !41
  %31 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %32 = tail call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %31)
  br i1 %32, label %33, label %46

33:                                               ; preds = %27
  %34 = load ptr, ptr %0, align 8, !tbaa !39
  %35 = getelementptr inbounds i8, ptr %34, i64 176
  %36 = load ptr, ptr %35, align 8
  tail call void %36(ptr noundef nonnull align 8 dereferenceable(357) %0, i1 noundef zeroext false)
  br label %46

37:                                               ; preds = %15
  br i1 %1, label %38, label %42

38:                                               ; preds = %37
  %39 = getelementptr inbounds i8, ptr %0, i64 128
  %40 = load i32, ptr %39, align 8, !tbaa !38
  %41 = add nsw i32 %40, -1
  store i32 %41, ptr %39, align 8, !tbaa !38
  br label %46

42:                                               ; preds = %37
  %43 = getelementptr inbounds i8, ptr %0, i64 132
  %44 = load i32, ptr %43, align 4, !tbaa !41
  %45 = add nsw i32 %44, -1
  store i32 %45, ptr %43, align 4, !tbaa !41
  br label %46

46:                                               ; preds = %38, %42, %23, %17, %33, %27
  %47 = getelementptr inbounds i8, ptr %0, i64 336
  %48 = load i32, ptr %47, align 8, !tbaa !42
  %.off = add i32 %48, -3
  %switch = icmp ult i32 %.off, 2
  br i1 %switch, label %49, label %61

49:                                               ; preds = %46
  %50 = getelementptr inbounds i8, ptr %0, i64 128
  %51 = load i32, ptr %50, align 8, !tbaa !38
  %52 = icmp eq i32 %51, 0
  %53 = getelementptr inbounds i8, ptr %0, i64 132
  %54 = load i32, ptr %53, align 4
  %55 = icmp eq i32 %54, 0
  %or.cond = select i1 %52, i1 %55, i1 false
  br i1 %or.cond, label %56, label %61

56:                                               ; preds = %49
  %57 = getelementptr inbounds i8, ptr %0, i64 312
  %58 = load i8, ptr %57, align 8, !tbaa !43, !range !9, !noundef !10
  %59 = trunc nuw i8 %58 to i1
  br i1 %59, label %61, label %60

60:                                               ; preds = %56
  store i32 0, ptr %47, align 8, !tbaa !42
  br label %61

61:                                               ; preds = %46, %11, %60, %56, %49
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = !{!12, !26, i64 280}
!12 = !{!"_ZTSN7sc_core12sc_process_bE", !13, i64 0, !14, i64 112, !26, i64 120, !26, i64 124, !26, i64 128, !26, i64 132, !6, i64 136, !6, i64 137, !14, i64 144, !26, i64 152, !14, i64 160, !14, i64 168, !6, i64 176, !6, i64 177, !6, i64 178, !6, i64 179, !14, i64 184, !14, i64 192, !27, i64 200, !26, i64 204, !28, i64 208, !14, i64 232, !14, i64 240, !14, i64 248, !14, i64 256, !7, i64 264, !26, i64 280, !32, i64 288, !6, i64 312, !14, i64 320, !14, i64 328, !36, i64 336, !6, i64 340, !14, i64 344, !37, i64 352, !6, i64 356}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !14, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !14, i64 96, !14, i64 104}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !14, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"int", !7, i64 0}
!27 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!28 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!32 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!36 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!37 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!38 = !{!12, !26, i64 128}
!39 = !{!40, !40, i64 0}
!40 = !{!"vtable pointer", !8, i64 0}
!41 = !{!12, !26, i64 132}
!42 = !{!12, !36, i64 336}
!43 = !{!12, !6, i64 312}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass