; LLVM IR from gem5/gem5 :: ext/nomali/lib/mmu.ll (ZN6NoMali3MMU8writeRegENS_7RegAddrEj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.NoMali::RegAddr" = type { i32 }
%"class.NoMali::MMU" = type { %"class.NoMali::GPUBlockInt", %"class.std::vector.0" }
%"class.NoMali::GPUBlockInt" = type { %"class.NoMali::GPUBlock", %"struct.NoMali::RegAddr", %"struct.NoMali::RegAddr", %"struct.NoMali::RegAddr", %"struct.NoMali::RegAddr" }
%"class.NoMali::GPUBlock" = type { ptr, ptr, %"class.NoMali::RegVector" }
%"class.NoMali::RegVector" = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<NoMali::AddrSpace, std::allocator<NoMali::AddrSpace>>::_Vector_impl" }
%"struct.std::_Vector_base<NoMali::AddrSpace, std::allocator<NoMali::AddrSpace>>::_Vector_impl" = type { %"struct.std::_Vector_base<NoMali::AddrSpace, std::allocator<NoMali::AddrSpace>>::_Vector_impl_data" }
%"struct.std::_Vector_base<NoMali::AddrSpace, std::allocator<NoMali::AddrSpace>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef zeroext i1 @_ZN6NoMaliL14isAddrSpaceRegERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali9AddrSpaceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i32 @_ZN6NoMaliL14getAddrSpaceNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) #1

; Function Attrs: inlinehint mustprogress uwtable
declare hidden i32 @_ZN6NoMaliL16getAddrSpaceAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6NoMali3MMU8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(80) %0, i32 %1, i32 noundef %2) unnamed_addr #5 align 2 {
  %4 = alloca %"struct.NoMali::RegAddr", align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca %"struct.NoMali::RegAddr", align 4
  %8 = alloca ptr, align 8
  %9 = alloca %"struct.NoMali::RegAddr", align 4
  %10 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  store i32 %1, ptr %10, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  %11 = load ptr, ptr %5, align 8
  %12 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  %13 = load i32, ptr %12, align 4, !tbaa !11
  switch i32 %13, label %18 [
    i32 0, label %14
    i32 4, label %14
    i32 8, label %14
    i32 12, label %14
  ]

14:                                               ; preds = %3, %3, %3, %3
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %7, ptr align 4 %4, i64 4, i1 false), !tbaa.struct !13
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %7, i32 0, i32 0
  %17 = load i32, ptr %16, align 4
  call void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %11, i32 %17, i32 noundef %15)
  br label %35

18:                                               ; preds = %3
  %19 = call noundef zeroext i1 @_ZN6NoMaliL14isAddrSpaceRegERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  br i1 %19, label %20, label %34

20:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #7
  %21 = getelementptr inbounds %"class.NoMali::MMU", ptr %11, i32 0, i32 1
  %22 = call noundef i32 @_ZN6NoMaliL14getAddrSpaceNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %23 = zext i32 %22 to i64
  %24 = call noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali9AddrSpaceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #7
  store ptr %24, ptr %8, align 8, !tbaa !5
  %25 = load ptr, ptr %8, align 8, !tbaa !5
  %26 = call i32 @_ZN6NoMaliL16getAddrSpaceAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %27 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %9, i32 0, i32 0
  store i32 %26, ptr %27, align 4
  %28 = load i32, ptr %6, align 4, !tbaa !9
  %29 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %9, i32 0, i32 0
  %30 = load i32, ptr %29, align 4
  %31 = load ptr, ptr %25, align 8, !tbaa !14
  %32 = getelementptr inbounds ptr, ptr %31, i64 4
  %33 = load ptr, ptr %32, align 8
  call void %33(ptr noundef nonnull align 8 dereferenceable(56) %25, i32 %30, i32 noundef %28)
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #7
  br label %34

34:                                               ; preds = %20, %18
  br label %35

35:                                               ; preds = %34, %14
  ret void
}

declare void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56), i32, i32 noundef) unnamed_addr #6

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTSN6NoMali7RegAddrE", !10, i64 0}
!13 = !{i64 0, i64 4, !9}
!14 = !{!15, !15, i64 0}
!15 = !{!"vtable pointer", !8, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.NoMali::RegAddr" = type { i32 }

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef zeroext i1 @_ZN6NoMaliL14isAddrSpaceRegERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali9AddrSpaceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i32 @_ZN6NoMaliL14getAddrSpaceNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress uwtable
declare hidden i32 @_ZN6NoMaliL16getAddrSpaceAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6NoMali3MMU8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(80) %0, i32 %1, i32 noundef %2) unnamed_addr #3 align 2 {
  %4 = alloca %"struct.NoMali::RegAddr", align 4
  store i32 %1, ptr %4, align 4
  %5 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  %switch = icmp ult i32 %5, 4
  br i1 %switch, label %6, label %7

6:                                                ; preds = %3
  tail call void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 %1, i32 noundef %2)
  br label %18

7:                                                ; preds = %3
  %8 = call noundef zeroext i1 @_ZN6NoMaliL14isAddrSpaceRegERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  br i1 %8, label %9, label %18

9:                                                ; preds = %7
  %10 = getelementptr inbounds i8, ptr %0, i64 56
  %11 = call noundef i32 @_ZN6NoMaliL14getAddrSpaceNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %12 = zext i32 %11 to i64
  %13 = call noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali9AddrSpaceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %12) #6
  %14 = call i32 @_ZN6NoMaliL16getAddrSpaceAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %15 = load ptr, ptr %13, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %15, i64 32
  %17 = load ptr, ptr %16, align 8
  call void %17(ptr noundef nonnull align 8 dereferenceable(56) %13, i32 %14, i32 noundef %2)
  br label %18

18:                                               ; preds = %7, %9, %6
  ret void
}

declare void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56), i32, i32 noundef) unnamed_addr #4

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #5

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass