; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int/sc_signed.ll (ZN5sc_dtcoERKNS_9sc_signedE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dt14check_for_zeroEiPKj(i32 noundef, ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef, ptr noundef, ptr noundef) #4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dtcoERKNS_9sc_signedE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_signed") align 8 %0, ptr noundef nonnull align 8 dereferenceable(32) %1) #5 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #7
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %10, i32 0, i32 1
  %12 = load i32, ptr %11, align 8, !tbaa !9
  store i32 %12, ptr %5, align 4, !tbaa !13
  %13 = load i32, ptr %5, align 4, !tbaa !13
  %14 = icmp eq i32 %13, 0
  br i1 %14, label %15, label %19

15:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #7
  store i32 1, ptr %6, align 4, !tbaa !13
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %16, i32 0, i32 2
  %18 = load i32, ptr %17, align 4, !tbaa !14
  call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef -1, i32 noundef %18, i32 noundef 1, ptr noundef %6, i1 noundef zeroext false)
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #7
  br label %55

19:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #7
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %20, i32 0, i32 3
  %22 = load i32, ptr %21, align 8, !tbaa !15
  store i32 %22, ptr %8, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #7
  %23 = load i32, ptr %8, align 4, !tbaa !13
  %24 = sext i32 %23 to i64
  %25 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %24, i64 4)
  %26 = extractvalue { i64, i1 } %25, 1
  %27 = extractvalue { i64, i1 } %25, 0
  %28 = select i1 %26, i64 -1, i64 %27
  %29 = call noalias noundef nonnull ptr @_Znam(i64 noundef %28) #8
  store ptr %29, ptr %9, align 8, !tbaa !5
  %30 = load i32, ptr %8, align 4, !tbaa !13
  %31 = load ptr, ptr %9, align 8, !tbaa !5
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %32, i32 0, i32 4
  %34 = load ptr, ptr %33, align 8, !tbaa !16
  call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %30, ptr noundef %31, ptr noundef %34)
  %35 = load i32, ptr %5, align 4, !tbaa !13
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %40

37:                                               ; preds = %19
  store i32 -1, ptr %5, align 4, !tbaa !13
  %38 = load i32, ptr %8, align 4, !tbaa !13
  %39 = load ptr, ptr %9, align 8, !tbaa !5
  call void @_ZN5sc_dt16vec_add_small_onEiPjj(i32 noundef %38, ptr noundef %39, i32 noundef 1)
  br label %48

40:                                               ; preds = %19
  store i32 1, ptr %5, align 4, !tbaa !13
  %41 = load i32, ptr %8, align 4, !tbaa !13
  %42 = load ptr, ptr %9, align 8, !tbaa !5
  call void @_ZN5sc_dt16vec_sub_small_onEiPjj(i32 noundef %41, ptr noundef %42, i32 noundef 1)
  %43 = load i32, ptr %8, align 4, !tbaa !13
  %44 = load ptr, ptr %9, align 8, !tbaa !5
  %45 = call noundef zeroext i1 @_ZN5sc_dt14check_for_zeroEiPKj(i32 noundef %43, ptr noundef %44)
  br i1 %45, label %46, label %47

46:                                               ; preds = %40
  store i32 0, ptr %5, align 4, !tbaa !13
  br label %47

47:                                               ; preds = %46, %40
  br label %48

48:                                               ; preds = %47, %37
  %49 = load i32, ptr %5, align 4, !tbaa !13
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %"class.sc_dt::sc_signed", ptr %50, i32 0, i32 2
  %52 = load i32, ptr %51, align 4, !tbaa !14
  %53 = load i32, ptr %8, align 4, !tbaa !13
  %54 = load ptr, ptr %9, align 8, !tbaa !5
  call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %49, i32 noundef %52, i32 noundef %53, ptr noundef %54, i1 noundef zeroext true)
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #7
  br label %55

55:                                               ; preds = %48, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #7
  ret void
}

declare void @_ZN5sc_dt16vec_add_small_onEiPjj(i32 noundef, ptr noundef, i32 noundef) #6

declare void @_ZN5sc_dt16vec_sub_small_onEiPjj(i32 noundef, ptr noundef, i32 noundef) #6

declare void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr, i32, i32, i32, ptr, i1)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !12, i64 8}
!10 = !{!"_ZTSN5sc_dt9sc_signedE", !11, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !6, i64 24}
!11 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!12 = !{!"int", !7, i64 0}
!13 = !{!12, !12, i64 0}
!14 = !{!10, !12, i64 12}
!15 = !{!10, !12, i64 16}
!16 = !{!10, !6, i64 24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dt14check_for_zeroEiPKj(i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dtcoERKNS_9sc_signedE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_signed") align 8 %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(32) %1) local_unnamed_addr #4 {
  %3 = alloca i32, align 4
  %4 = getelementptr inbounds i8, ptr %1, i64 8
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %7, label %10

7:                                                ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #6
  store i32 1, ptr %3, align 4, !tbaa !12
  %8 = getelementptr inbounds i8, ptr %1, i64 12
  %9 = load i32, ptr %8, align 4, !tbaa !13
  call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef -1, i32 noundef %9, i32 noundef 1, ptr noundef nonnull %3, i1 noundef zeroext false)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #6
  br label %27

10:                                               ; preds = %2
  %11 = getelementptr inbounds i8, ptr %1, i64 16
  %12 = load i32, ptr %11, align 8, !tbaa !14
  %13 = sext i32 %12 to i64
  %14 = icmp slt i32 %12, 0
  %15 = shl nsw i64 %13, 2
  %16 = select i1 %14, i64 -1, i64 %15
  %17 = tail call noalias noundef nonnull ptr @_Znam(i64 noundef %16) #7
  %18 = getelementptr inbounds i8, ptr %1, i64 24
  %19 = load ptr, ptr %18, align 8, !tbaa !15
  tail call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %12, ptr noundef nonnull %17, ptr noundef %19)
  %20 = icmp eq i32 %5, 1
  br i1 %20, label %21, label %22

21:                                               ; preds = %10
  tail call void @_ZN5sc_dt16vec_add_small_onEiPjj(i32 noundef %12, ptr noundef nonnull %17, i32 noundef 1)
  br label %24

22:                                               ; preds = %10
  tail call void @_ZN5sc_dt16vec_sub_small_onEiPjj(i32 noundef %12, ptr noundef nonnull %17, i32 noundef 1)
  %23 = tail call noundef zeroext i1 @_ZN5sc_dt14check_for_zeroEiPKj(i32 noundef %12, ptr noundef nonnull %17)
  %not. = xor i1 %23, true
  %spec.select = zext i1 %not. to i32
  br label %24

24:                                               ; preds = %22, %21
  %.0 = phi i32 [ -1, %21 ], [ %spec.select, %22 ]
  %25 = getelementptr inbounds i8, ptr %1, i64 12
  %26 = load i32, ptr %25, align 4, !tbaa !13
  tail call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %.0, i32 noundef %26, i32 noundef %12, ptr noundef nonnull %17, i1 noundef zeroext true)
  br label %27

27:                                               ; preds = %24, %7
  ret void
}

declare void @_ZN5sc_dt16vec_add_small_onEiPjj(i32 noundef, ptr noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN5sc_dt16vec_sub_small_onEiPjj(i32 noundef, ptr noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr, i32, i32, i32, ptr, i1) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 8}
!6 = !{!"_ZTSN5sc_dt9sc_signedE", !7, i64 0, !8, i64 8, !8, i64 12, !8, i64 16, !11, i64 24}
!7 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"any pointer", !9, i64 0}
!12 = !{!8, !8, i64 0}
!13 = !{!6, !8, i64 12}
!14 = !{!6, !8, i64 16}
!15 = !{!6, !11, i64 24}


; Effective O3 passes: GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass