; LLVM IR from gem5/gem5 :: ext/drampower/src/CommandAnalysis.ll (ZN4Data15CommandAnalysis15idle_pre_updateEll)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Data::CommandAnalysis" = type { %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", i64, %"class.std::vector", i64, i64, %"class.std::vector", i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, %"class.Data::MemorySpecification", i64, %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.13", %"class.std::vector.13", %"class.std::vector", i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i64, i64, %"class.std::vector", i64 }
%"class.Data::MemorySpecification" = type { ptr, %"class.std::__cxx11::basic_string", %"class.Data::MemoryType", [4 x i8], %"class.Data::MemArchitectureSpec", %"class.Data::MemTimingSpec", %"class.Data::MemPowerSpec", %"class.Data::Parametrisable" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.Data::MemoryType" = type { i32 }
%"class.Data::MemArchitectureSpec" = type <{ ptr, i64, i64, i64, i64, i64, i64, i64, i64, i8, i8, i8, [5 x i8], %"class.Data::Parametrisable" }>
%"class.Data::MemTimingSpec" = type { ptr, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, %"class.Data::Parametrisable" }
%"class.Data::MemPowerSpec" = type { ptr, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, %"class.Data::Parametrisable" }
%"class.Data::Parametrisable" = type { ptr, %"class.std::vector.3" }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIlERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Data15CommandAnalysis15idle_pre_updateEll(ptr noundef nonnull align 8 dereferenceable(1392) %0, i64 noundef %1, i64 noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  store i64 %2, ptr %6, align 8, !tbaa !9
  %9 = load ptr, ptr %4, align 8
  %10 = load i64, ptr %6, align 8, !tbaa !9
  %11 = icmp sgt i64 %10, 0
  br i1 %11, label %12, label %27

12:                                               ; preds = %3
  %13 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %9, i32 0, i32 31
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  %14 = load i64, ptr %5, align 8, !tbaa !9
  %15 = load i64, ptr %6, align 8, !tbaa !9
  %16 = sub nsw i64 %14, %15
  %17 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %9, i32 0, i32 30
  %18 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %17, i32 0, i32 5
  %19 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %18, i32 0, i32 17
  %20 = load i64, ptr %19, align 8, !tbaa !11
  %21 = sub nsw i64 %16, %20
  store i64 %21, ptr %7, align 8, !tbaa !9
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIlERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %13, ptr noundef nonnull align 8 dereferenceable(8) %7)
  %23 = load i64, ptr %22, align 8, !tbaa !9
  %24 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %9, i32 0, i32 10
  %25 = load i64, ptr %24, align 8, !tbaa !36
  %26 = add nsw i64 %25, %23
  store i64 %26, ptr %24, align 8, !tbaa !36
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  br label %41

27:                                               ; preds = %3
  %28 = load i64, ptr %6, align 8, !tbaa !9
  %29 = icmp eq i64 %28, 0
  br i1 %29, label %30, label %40

30:                                               ; preds = %27
  %31 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %9, i32 0, i32 31
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  %32 = load i64, ptr %5, align 8, !tbaa !9
  %33 = load i64, ptr %6, align 8, !tbaa !9
  %34 = sub nsw i64 %32, %33
  store i64 %34, ptr %8, align 8, !tbaa !9
  %35 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIlERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %31, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %36 = load i64, ptr %35, align 8, !tbaa !9
  %37 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %9, i32 0, i32 10
  %38 = load i64, ptr %37, align 8, !tbaa !36
  %39 = add nsw i64 %38, %36
  store i64 %39, ptr %37, align 8, !tbaa !36
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  br label %40

40:                                               ; preds = %30, %27
  br label %41

41:                                               ; preds = %40, %12
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 632}
!12 = !{!"_ZTSN4Data15CommandAnalysisE", !13, i64 0, !13, i64 24, !13, i64 48, !13, i64 72, !10, i64 96, !13, i64 104, !10, i64 128, !10, i64 136, !13, i64 144, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !10, i64 256, !10, i64 264, !10, i64 272, !10, i64 280, !10, i64 288, !10, i64 296, !10, i64 304, !10, i64 312, !10, i64 320, !10, i64 328, !17, i64 336, !10, i64 1104, !27, i64 1112, !27, i64 1136, !27, i64 1160, !31, i64 1184, !31, i64 1208, !13, i64 1232, !10, i64 1256, !10, i64 1264, !10, i64 1272, !10, i64 1280, !10, i64 1288, !10, i64 1296, !10, i64 1304, !10, i64 1312, !10, i64 1320, !10, i64 1328, !35, i64 1336, !10, i64 1344, !10, i64 1352, !13, i64 1360, !10, i64 1384}
!13 = !{!"_ZTSSt6vectorIlSaIlEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIlSaIlEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIlSaIlEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIlSaIlEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSN4Data19MemorySpecificationE", !18, i64 8, !20, i64 40, !22, i64 48, !24, i64 160, !26, i64 456}
!18 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !19, i64 0, !10, i64 8, !7, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!20 = !{!"_ZTSN4Data10MemoryTypeE", !21, i64 0}
!21 = !{!"_ZTSN4Data10MemoryType12MemoryType_tE", !7, i64 0}
!22 = !{!"_ZTSN4Data19MemArchitectureSpecE", !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !23, i64 72, !23, i64 73, !23, i64 74}
!23 = !{!"bool", !7, i64 0}
!24 = !{!"_ZTSN4Data13MemTimingSpecE", !25, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !25, i64 256}
!25 = !{!"double", !7, i64 0}
!26 = !{!"_ZTSN4Data12MemPowerSpecE", !25, i64 8, !25, i64 16, !25, i64 24, !25, i64 32, !25, i64 40, !25, i64 48, !25, i64 56, !25, i64 64, !25, i64 72, !25, i64 80, !25, i64 88, !25, i64 96, !25, i64 104, !25, i64 112, !25, i64 120, !25, i64 128, !25, i64 136, !25, i64 144, !25, i64 152, !25, i64 160, !25, i64 168, !25, i64 176, !25, i64 184, !25, i64 192, !25, i64 200, !25, i64 208, !25, i64 216, !25, i64 224, !25, i64 232, !25, i64 240}
!27 = !{!"_ZTSSt6vectorIN4Data10MemCommandESaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIN4Data10MemCommandESaIS1_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Data10MemCommandESaIS1_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIN4Data10MemCommandESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSSt6vectorIN4Data15CommandAnalysis9BankStateESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIN4Data15CommandAnalysis9BankStateESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIN4Data15CommandAnalysis9BankStateESaIS2_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIN4Data15CommandAnalysis9BankStateESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!35 = !{!"int", !7, i64 0}
!36 = !{!12, !10, i64 176}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIlERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Data15CommandAnalysis15idle_pre_updateEll(ptr noundef nonnull align 8 dereferenceable(1392) %0, i64 noundef %1, i64 noundef %2) local_unnamed_addr #2 align 2 {
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = icmp sgt i64 %2, 0
  br i1 %6, label %7, label %18

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 1104
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #3
  %9 = getelementptr inbounds i8, ptr %0, i64 632
  %10 = load i64, ptr %9, align 8, !tbaa !5
  %11 = add i64 %10, %2
  %12 = sub i64 %1, %11
  store i64 %12, ptr %4, align 8, !tbaa !34
  %13 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIlERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %14 = load i64, ptr %13, align 8, !tbaa !34
  %15 = getelementptr inbounds i8, ptr %0, i64 176
  %16 = load i64, ptr %15, align 8, !tbaa !35
  %17 = add nsw i64 %16, %14
  store i64 %17, ptr %15, align 8, !tbaa !35
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #3
  br label %27

18:                                               ; preds = %3
  %19 = icmp eq i64 %2, 0
  br i1 %19, label %20, label %27

20:                                               ; preds = %18
  %21 = getelementptr inbounds i8, ptr %0, i64 1104
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #3
  store i64 %1, ptr %5, align 8, !tbaa !34
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIlERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %21, ptr noundef nonnull align 8 dereferenceable(8) %5)
  %23 = load i64, ptr %22, align 8, !tbaa !34
  %24 = getelementptr inbounds i8, ptr %0, i64 176
  %25 = load i64, ptr %24, align 8, !tbaa !35
  %26 = add nsw i64 %25, %23
  store i64 %26, ptr %24, align 8, !tbaa !35
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #3
  br label %27

27:                                               ; preds = %18, %20, %7
  ret void
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 632}
!6 = !{!"_ZTSN4Data15CommandAnalysisE", !7, i64 0, !7, i64 24, !7, i64 48, !7, i64 72, !14, i64 96, !7, i64 104, !14, i64 128, !14, i64 136, !7, i64 144, !14, i64 168, !14, i64 176, !14, i64 184, !14, i64 192, !14, i64 200, !14, i64 208, !14, i64 216, !14, i64 224, !14, i64 232, !14, i64 240, !14, i64 248, !14, i64 256, !14, i64 264, !14, i64 272, !14, i64 280, !14, i64 288, !14, i64 296, !14, i64 304, !14, i64 312, !14, i64 320, !14, i64 328, !15, i64 336, !14, i64 1104, !25, i64 1112, !25, i64 1136, !25, i64 1160, !29, i64 1184, !29, i64 1208, !7, i64 1232, !14, i64 1256, !14, i64 1264, !14, i64 1272, !14, i64 1280, !14, i64 1288, !14, i64 1296, !14, i64 1304, !14, i64 1312, !14, i64 1320, !14, i64 1328, !33, i64 1336, !14, i64 1344, !14, i64 1352, !7, i64 1360, !14, i64 1384}
!7 = !{!"_ZTSSt6vectorIlSaIlEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIlSaIlEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIlSaIlEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIlSaIlEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"long", !12, i64 0}
!15 = !{!"_ZTSN4Data19MemorySpecificationE", !16, i64 8, !18, i64 40, !20, i64 48, !22, i64 160, !24, i64 456}
!16 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !17, i64 0, !14, i64 8, !12, i64 16}
!17 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!18 = !{!"_ZTSN4Data10MemoryTypeE", !19, i64 0}
!19 = !{!"_ZTSN4Data10MemoryType12MemoryType_tE", !12, i64 0}
!20 = !{!"_ZTSN4Data19MemArchitectureSpecE", !14, i64 8, !14, i64 16, !14, i64 24, !14, i64 32, !14, i64 40, !14, i64 48, !14, i64 56, !14, i64 64, !21, i64 72, !21, i64 73, !21, i64 74}
!21 = !{!"bool", !12, i64 0}
!22 = !{!"_ZTSN4Data13MemTimingSpecE", !23, i64 8, !14, i64 16, !14, i64 24, !14, i64 32, !14, i64 40, !14, i64 48, !14, i64 56, !14, i64 64, !14, i64 72, !14, i64 80, !14, i64 88, !14, i64 96, !14, i64 104, !14, i64 112, !14, i64 120, !14, i64 128, !14, i64 136, !14, i64 144, !14, i64 152, !14, i64 160, !14, i64 168, !14, i64 176, !14, i64 184, !14, i64 192, !14, i64 200, !14, i64 208, !14, i64 216, !14, i64 224, !14, i64 232, !14, i64 240, !14, i64 248, !23, i64 256}
!23 = !{!"double", !12, i64 0}
!24 = !{!"_ZTSN4Data12MemPowerSpecE", !23, i64 8, !23, i64 16, !23, i64 24, !23, i64 32, !23, i64 40, !23, i64 48, !23, i64 56, !23, i64 64, !23, i64 72, !23, i64 80, !23, i64 88, !23, i64 96, !23, i64 104, !23, i64 112, !23, i64 120, !23, i64 128, !23, i64 136, !23, i64 144, !23, i64 152, !23, i64 160, !23, i64 168, !23, i64 176, !23, i64 184, !23, i64 192, !23, i64 200, !23, i64 208, !23, i64 216, !23, i64 224, !23, i64 232, !23, i64 240}
!25 = !{!"_ZTSSt6vectorIN4Data10MemCommandESaIS1_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIN4Data10MemCommandESaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIN4Data10MemCommandESaIS1_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Data10MemCommandESaIS1_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!29 = !{!"_ZTSSt6vectorIN4Data15CommandAnalysis9BankStateESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIN4Data15CommandAnalysis9BankStateESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIN4Data15CommandAnalysis9BankStateESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIN4Data15CommandAnalysis9BankStateESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!33 = !{!"int", !12, i64 0}
!34 = !{!14, !14, i64 0}
!35 = !{!6, !14, i64 176}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass