; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/examples/datawidth_int_c (datawidth_int)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.datawidth = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9datawidth5entryEv(ptr noundef nonnull align 8 dereferenceable(448) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  br label %7

7:                                                ; preds = %18, %1
  br label %8

8:                                                ; preds = %7
  br label %9

9:                                                ; preds = %10, %8
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %10

10:                                               ; preds = %9
  %11 = getelementptr inbounds %struct.datawidth, ptr %6, i32 0, i32 4
  %12 = load ptr, ptr %11, align 8, !tbaa !9
  %13 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %12)
  %14 = load i8, ptr %13, align 1, !tbaa !41, !range !42, !noundef !43
  %15 = trunc i8 %14 to i1
  %16 = zext i1 %15 to i32
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %9, label %18, !llvm.loop !44

18:                                               ; preds = %10
  %19 = getelementptr inbounds %struct.datawidth, ptr %6, i32 0, i32 2
  %20 = load ptr, ptr %19, align 8, !tbaa !46
  %21 = load ptr, ptr %20, align 8, !tbaa !47
  %22 = getelementptr inbounds ptr, ptr %21, i64 5
  %23 = load ptr, ptr %22, align 8
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr %23(ptr noundef nonnull align 8 dereferenceable(196) %20)
  %25 = load i32, ptr %24, align 4, !tbaa !49
  store i32 %25, ptr %3, align 4, !tbaa !49
  %26 = getelementptr inbounds %struct.datawidth, ptr %6, i32 0, i32 3
  %27 = load ptr, ptr %26, align 8, !tbaa !50
  %28 = load ptr, ptr %27, align 8, !tbaa !47
  %29 = getelementptr inbounds ptr, ptr %28, i64 5
  %30 = load ptr, ptr %29, align 8
  %31 = call noundef nonnull align 4 dereferenceable(4) ptr %30(ptr noundef nonnull align 8 dereferenceable(196) %27)
  %32 = load i32, ptr %31, align 4, !tbaa !49
  store i32 %32, ptr %4, align 4, !tbaa !49
  %33 = load i32, ptr %3, align 4, !tbaa !49
  %34 = load i32, ptr %4, align 4, !tbaa !49
  %35 = add nsw i32 %33, %34
  store i32 %35, ptr %5, align 4, !tbaa !49
  %36 = getelementptr inbounds %struct.datawidth, ptr %6, i32 0, i32 5
  %37 = load ptr, ptr %36, align 8, !tbaa !51
  %38 = load ptr, ptr %37, align 8, !tbaa !47
  %39 = getelementptr inbounds ptr, ptr %38, i64 9
  %40 = load ptr, ptr %39, align 8
  call void %40(ptr noundef nonnull align 8 dereferenceable(196) %37, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %7, !llvm.loop !52
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 432}
!10 = !{!"_ZTS9datawidth", !11, i64 0, !33, i64 232, !6, i64 416, !6, i64 424, !6, i64 432, !6, i64 440}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !24, i64 112, !25, i64 120, !27, i64 144, !29, i64 168, !31, i64 192, !6, i64 200, !32, i64 208, !6, i64 216, !6, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !6, i64 96, !6, i64 104}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !7, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!23 = !{!"long", !7, i64 0}
!24 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !26, i64 8, !6, i64 16}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !28, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !30, i64 8, !6, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!31 = !{!"bool", !7, i64 0}
!32 = !{!"int", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !6, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !6, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = !{!31, !31, i64 0}
!42 = !{i8 0, i8 2}
!43 = !{}
!44 = distinct !{!44, !45}
!45 = !{!"llvm.loop.mustprogress"}
!46 = !{!10, !6, i64 416}
!47 = !{!48, !48, i64 0}
!48 = !{!"vtable pointer", !8, i64 0}
!49 = !{!32, !32, i64 0}
!50 = !{!10, !6, i64 424}
!51 = !{!10, !6, i64 440}
!52 = distinct !{!52, !45}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN9datawidth5entryEv(ptr noundef nonnull align 8 dereferenceable(448) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #3
  %3 = getelementptr inbounds i8, ptr %0, i64 432
  %4 = getelementptr inbounds i8, ptr %0, i64 416
  %5 = getelementptr inbounds i8, ptr %0, i64 424
  %6 = getelementptr inbounds i8, ptr %0, i64 440
  br label %7

7:                                                ; preds = %.backedge, %1
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %8)
  %10 = load i8, ptr %9, align 1, !tbaa !40, !range !41, !noundef !42
  %11 = icmp eq i8 %10, 0
  br i1 %11, label %.backedge, label %12

.backedge:                                        ; preds = %7, %12
  br label %7, !llvm.loop !43

12:                                               ; preds = %7
  %13 = load ptr, ptr %4, align 8, !tbaa !45
  %14 = load ptr, ptr %13, align 8, !tbaa !46
  %15 = getelementptr inbounds i8, ptr %14, i64 40
  %16 = load ptr, ptr %15, align 8
  %17 = call noundef nonnull align 4 dereferenceable(4) ptr %16(ptr noundef nonnull align 8 dereferenceable(196) %13)
  %18 = load i32, ptr %17, align 4, !tbaa !48
  %19 = load ptr, ptr %5, align 8, !tbaa !49
  %20 = load ptr, ptr %19, align 8, !tbaa !46
  %21 = getelementptr inbounds i8, ptr %20, i64 40
  %22 = load ptr, ptr %21, align 8
  %23 = call noundef nonnull align 4 dereferenceable(4) ptr %22(ptr noundef nonnull align 8 dereferenceable(196) %19)
  %24 = load i32, ptr %23, align 4, !tbaa !48
  %25 = add nsw i32 %24, %18
  store i32 %25, ptr %2, align 4, !tbaa !48
  %26 = load ptr, ptr %6, align 8, !tbaa !50
  %27 = load ptr, ptr %26, align 8, !tbaa !46
  %28 = getelementptr inbounds i8, ptr %27, i64 72
  %29 = load ptr, ptr %28, align 8
  call void %29(ptr noundef nonnull align 8 dereferenceable(196) %26, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  br label %.backedge
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 432}
!6 = !{!"_ZTS9datawidth", !7, i64 0, !32, i64 232, !9, i64 416, !9, i64 424, !9, i64 432, !9, i64 440}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core5sc_inIbEE", !33, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!33 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !35, i64 0, !9, i64 120, !36, i64 128}
!35 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!36 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!40 = !{!30, !30, i64 0}
!41 = !{i8 0, i8 2}
!42 = !{}
!43 = distinct !{!43, !44}
!44 = !{!"llvm.loop.mustprogress"}
!45 = !{!6, !9, i64 416}
!46 = !{!47, !47, i64 0}
!47 = !{!"vtable pointer", !11, i64 0}
!48 = !{!31, !31, i64 0}
!49 = !{!6, !9, i64 424}
!50 = !{!6, !9, i64 440}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass