; LLVM IR from luminousmen/ZUC :: ZUC.ll (Z14InitializationPhS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@LFSR_S = external dso_local global [16 x i32], align 16
@F_R1 = external dso_local global i32, align 4
@F_R2 = external dso_local global i32, align 4
@EK_d = external dso_local global [16 x i32], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z26LFSRWithInitializationModej(i32 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z16LFSRWithWorkModev() #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z17BitReorganizationv() #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z1Fv() #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z14InitializationPhS_(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %8

8:                                                ; preds = %38, %2
  %9 = load i32, ptr %6, align 4, !tbaa !9
  %10 = icmp slt i32 %9, 16
  br i1 %10, label %12, label %11

11:                                               ; preds = %8
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %41

12:                                               ; preds = %8
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = load i32, ptr %6, align 4, !tbaa !9
  %15 = sext i32 %14 to i64
  %16 = getelementptr inbounds i8, ptr %13, i64 %15
  %17 = load i8, ptr %16, align 1, !tbaa !11
  %18 = zext i8 %17 to i32
  %19 = or i32 0, %18
  %20 = shl i32 %19, 23
  %21 = load i32, ptr %6, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds [16 x i32], ptr @EK_d, i64 0, i64 %22
  %24 = load i32, ptr %23, align 4, !tbaa !9
  %25 = shl i32 %24, 8
  %26 = or i32 %20, %25
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = load i32, ptr %6, align 4, !tbaa !9
  %29 = sext i32 %28 to i64
  %30 = getelementptr inbounds i8, ptr %27, i64 %29
  %31 = load i8, ptr %30, align 1, !tbaa !11
  %32 = zext i8 %31 to i32
  %33 = or i32 0, %32
  %34 = or i32 %26, %33
  %35 = load i32, ptr %6, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds [16 x i32], ptr @LFSR_S, i64 0, i64 %36
  store i32 %34, ptr %37, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %12
  %39 = load i32, ptr %6, align 4, !tbaa !9
  %40 = add nsw i32 %39, 1
  store i32 %40, ptr %6, align 4, !tbaa !9
  br label %8, !llvm.loop !12

41:                                               ; preds = %11
  store i32 0, ptr @F_R1, align 4, !tbaa !9
  store i32 0, ptr @F_R2, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store i32 32, ptr %7, align 4, !tbaa !9
  br label %42

42:                                               ; preds = %45, %41
  %43 = load i32, ptr %7, align 4, !tbaa !9
  %44 = icmp ugt i32 %43, 0
  br i1 %44, label %45, label %51

45:                                               ; preds = %42
  call void @_Z17BitReorganizationv()
  %46 = call noundef i32 @_Z1Fv()
  store i32 %46, ptr %5, align 4, !tbaa !9
  %47 = load i32, ptr %5, align 4, !tbaa !9
  %48 = lshr i32 %47, 1
  call void @_Z26LFSRWithInitializationModej(i32 noundef %48)
  %49 = load i32, ptr %7, align 4, !tbaa !9
  %50 = add i32 %49, -1
  store i32 %50, ptr %7, align 4, !tbaa !9
  br label %42, !llvm.loop !14

51:                                               ; preds = %42
  call void @_Z17BitReorganizationv()
  %52 = call noundef i32 @_Z1Fv()
  call void @_Z16LFSRWithWorkModev()
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@LFSR_S = external dso_local local_unnamed_addr global [16 x i32], align 16
@F_R1 = external dso_local local_unnamed_addr global i32, align 4
@F_R2 = external dso_local local_unnamed_addr global i32, align 4
@EK_d = external dso_local local_unnamed_addr global [16 x i32], align 16

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z26LFSRWithInitializationModej(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z16LFSRWithWorkModev() local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z17BitReorganizationv() local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z1Fv() local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z14InitializationPhS_(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = load i8, ptr %0, align 1, !tbaa !5
  %4 = zext i8 %3 to i32
  %5 = shl nuw nsw i32 %4, 23
  %6 = load i32, ptr @EK_d, align 16, !tbaa !8
  %7 = shl i32 %6, 8
  %8 = or i32 %5, %7
  %9 = load i8, ptr %1, align 1, !tbaa !5
  %10 = zext i8 %9 to i32
  %11 = or disjoint i32 %8, %10
  store i32 %11, ptr @LFSR_S, align 16, !tbaa !8
  %12 = getelementptr inbounds i8, ptr %0, i64 1
  %13 = load i8, ptr %12, align 1, !tbaa !5
  %14 = zext i8 %13 to i32
  %15 = shl nuw nsw i32 %14, 23
  %16 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 4), align 4, !tbaa !8
  %17 = shl i32 %16, 8
  %18 = or i32 %15, %17
  %19 = getelementptr inbounds i8, ptr %1, i64 1
  %20 = load i8, ptr %19, align 1, !tbaa !5
  %21 = zext i8 %20 to i32
  %22 = or disjoint i32 %18, %21
  store i32 %22, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 4), align 4, !tbaa !8
  %23 = getelementptr inbounds i8, ptr %0, i64 2
  %24 = load i8, ptr %23, align 1, !tbaa !5
  %25 = zext i8 %24 to i32
  %26 = shl nuw nsw i32 %25, 23
  %27 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 8), align 8, !tbaa !8
  %28 = shl i32 %27, 8
  %29 = or i32 %26, %28
  %30 = getelementptr inbounds i8, ptr %1, i64 2
  %31 = load i8, ptr %30, align 1, !tbaa !5
  %32 = zext i8 %31 to i32
  %33 = or disjoint i32 %29, %32
  store i32 %33, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 8), align 8, !tbaa !8
  %34 = getelementptr inbounds i8, ptr %0, i64 3
  %35 = load i8, ptr %34, align 1, !tbaa !5
  %36 = zext i8 %35 to i32
  %37 = shl nuw nsw i32 %36, 23
  %38 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 12), align 4, !tbaa !8
  %39 = shl i32 %38, 8
  %40 = or i32 %37, %39
  %41 = getelementptr inbounds i8, ptr %1, i64 3
  %42 = load i8, ptr %41, align 1, !tbaa !5
  %43 = zext i8 %42 to i32
  %44 = or disjoint i32 %40, %43
  store i32 %44, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 12), align 4, !tbaa !8
  %45 = getelementptr inbounds i8, ptr %0, i64 4
  %46 = load i8, ptr %45, align 1, !tbaa !5
  %47 = zext i8 %46 to i32
  %48 = shl nuw nsw i32 %47, 23
  %49 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 16), align 16, !tbaa !8
  %50 = shl i32 %49, 8
  %51 = or i32 %48, %50
  %52 = getelementptr inbounds i8, ptr %1, i64 4
  %53 = load i8, ptr %52, align 1, !tbaa !5
  %54 = zext i8 %53 to i32
  %55 = or disjoint i32 %51, %54
  store i32 %55, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 16), align 16, !tbaa !8
  %56 = getelementptr inbounds i8, ptr %0, i64 5
  %57 = load i8, ptr %56, align 1, !tbaa !5
  %58 = zext i8 %57 to i32
  %59 = shl nuw nsw i32 %58, 23
  %60 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 20), align 4, !tbaa !8
  %61 = shl i32 %60, 8
  %62 = or i32 %59, %61
  %63 = getelementptr inbounds i8, ptr %1, i64 5
  %64 = load i8, ptr %63, align 1, !tbaa !5
  %65 = zext i8 %64 to i32
  %66 = or disjoint i32 %62, %65
  store i32 %66, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 20), align 4, !tbaa !8
  %67 = getelementptr inbounds i8, ptr %0, i64 6
  %68 = load i8, ptr %67, align 1, !tbaa !5
  %69 = zext i8 %68 to i32
  %70 = shl nuw nsw i32 %69, 23
  %71 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 24), align 8, !tbaa !8
  %72 = shl i32 %71, 8
  %73 = or i32 %70, %72
  %74 = getelementptr inbounds i8, ptr %1, i64 6
  %75 = load i8, ptr %74, align 1, !tbaa !5
  %76 = zext i8 %75 to i32
  %77 = or disjoint i32 %73, %76
  store i32 %77, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 24), align 8, !tbaa !8
  %78 = getelementptr inbounds i8, ptr %0, i64 7
  %79 = load i8, ptr %78, align 1, !tbaa !5
  %80 = zext i8 %79 to i32
  %81 = shl nuw nsw i32 %80, 23
  %82 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 28), align 4, !tbaa !8
  %83 = shl i32 %82, 8
  %84 = or i32 %81, %83
  %85 = getelementptr inbounds i8, ptr %1, i64 7
  %86 = load i8, ptr %85, align 1, !tbaa !5
  %87 = zext i8 %86 to i32
  %88 = or disjoint i32 %84, %87
  store i32 %88, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 28), align 4, !tbaa !8
  %89 = getelementptr inbounds i8, ptr %0, i64 8
  %90 = load i8, ptr %89, align 1, !tbaa !5
  %91 = zext i8 %90 to i32
  %92 = shl nuw nsw i32 %91, 23
  %93 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 32), align 16, !tbaa !8
  %94 = shl i32 %93, 8
  %95 = or i32 %92, %94
  %96 = getelementptr inbounds i8, ptr %1, i64 8
  %97 = load i8, ptr %96, align 1, !tbaa !5
  %98 = zext i8 %97 to i32
  %99 = or disjoint i32 %95, %98
  store i32 %99, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 32), align 16, !tbaa !8
  %100 = getelementptr inbounds i8, ptr %0, i64 9
  %101 = load i8, ptr %100, align 1, !tbaa !5
  %102 = zext i8 %101 to i32
  %103 = shl nuw nsw i32 %102, 23
  %104 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 36), align 4, !tbaa !8
  %105 = shl i32 %104, 8
  %106 = or i32 %103, %105
  %107 = getelementptr inbounds i8, ptr %1, i64 9
  %108 = load i8, ptr %107, align 1, !tbaa !5
  %109 = zext i8 %108 to i32
  %110 = or disjoint i32 %106, %109
  store i32 %110, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 36), align 4, !tbaa !8
  %111 = getelementptr inbounds i8, ptr %0, i64 10
  %112 = load i8, ptr %111, align 1, !tbaa !5
  %113 = zext i8 %112 to i32
  %114 = shl nuw nsw i32 %113, 23
  %115 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 40), align 8, !tbaa !8
  %116 = shl i32 %115, 8
  %117 = or i32 %114, %116
  %118 = getelementptr inbounds i8, ptr %1, i64 10
  %119 = load i8, ptr %118, align 1, !tbaa !5
  %120 = zext i8 %119 to i32
  %121 = or disjoint i32 %117, %120
  store i32 %121, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 40), align 8, !tbaa !8
  %122 = getelementptr inbounds i8, ptr %0, i64 11
  %123 = load i8, ptr %122, align 1, !tbaa !5
  %124 = zext i8 %123 to i32
  %125 = shl nuw nsw i32 %124, 23
  %126 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 44), align 4, !tbaa !8
  %127 = shl i32 %126, 8
  %128 = or i32 %125, %127
  %129 = getelementptr inbounds i8, ptr %1, i64 11
  %130 = load i8, ptr %129, align 1, !tbaa !5
  %131 = zext i8 %130 to i32
  %132 = or disjoint i32 %128, %131
  store i32 %132, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 44), align 4, !tbaa !8
  %133 = getelementptr inbounds i8, ptr %0, i64 12
  %134 = load i8, ptr %133, align 1, !tbaa !5
  %135 = zext i8 %134 to i32
  %136 = shl nuw nsw i32 %135, 23
  %137 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 48), align 16, !tbaa !8
  %138 = shl i32 %137, 8
  %139 = or i32 %136, %138
  %140 = getelementptr inbounds i8, ptr %1, i64 12
  %141 = load i8, ptr %140, align 1, !tbaa !5
  %142 = zext i8 %141 to i32
  %143 = or disjoint i32 %139, %142
  store i32 %143, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 48), align 16, !tbaa !8
  %144 = getelementptr inbounds i8, ptr %0, i64 13
  %145 = load i8, ptr %144, align 1, !tbaa !5
  %146 = zext i8 %145 to i32
  %147 = shl nuw nsw i32 %146, 23
  %148 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 52), align 4, !tbaa !8
  %149 = shl i32 %148, 8
  %150 = or i32 %147, %149
  %151 = getelementptr inbounds i8, ptr %1, i64 13
  %152 = load i8, ptr %151, align 1, !tbaa !5
  %153 = zext i8 %152 to i32
  %154 = or disjoint i32 %150, %153
  store i32 %154, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 52), align 4, !tbaa !8
  %155 = getelementptr inbounds i8, ptr %0, i64 14
  %156 = load i8, ptr %155, align 1, !tbaa !5
  %157 = zext i8 %156 to i32
  %158 = shl nuw nsw i32 %157, 23
  %159 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 56), align 8, !tbaa !8
  %160 = shl i32 %159, 8
  %161 = or i32 %158, %160
  %162 = getelementptr inbounds i8, ptr %1, i64 14
  %163 = load i8, ptr %162, align 1, !tbaa !5
  %164 = zext i8 %163 to i32
  %165 = or disjoint i32 %161, %164
  store i32 %165, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 56), align 8, !tbaa !8
  %166 = getelementptr inbounds i8, ptr %0, i64 15
  %167 = load i8, ptr %166, align 1, !tbaa !5
  %168 = zext i8 %167 to i32
  %169 = shl nuw nsw i32 %168, 23
  %170 = load i32, ptr getelementptr inbounds (i8, ptr @EK_d, i64 60), align 4, !tbaa !8
  %171 = shl i32 %170, 8
  %172 = or i32 %169, %171
  %173 = getelementptr inbounds i8, ptr %1, i64 15
  %174 = load i8, ptr %173, align 1, !tbaa !5
  %175 = zext i8 %174 to i32
  %176 = or disjoint i32 %172, %175
  store i32 %176, ptr getelementptr inbounds (i8, ptr @LFSR_S, i64 60), align 4, !tbaa !8
  store i32 0, ptr @F_R1, align 4, !tbaa !8
  store i32 0, ptr @F_R2, align 4, !tbaa !8
  tail call void @_Z17BitReorganizationv()
  %177 = tail call noundef i32 @_Z1Fv()
  %178 = lshr i32 %177, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %178)
  tail call void @_Z17BitReorganizationv()
  %179 = tail call noundef i32 @_Z1Fv()
  %180 = lshr i32 %179, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %180)
  tail call void @_Z17BitReorganizationv()
  %181 = tail call noundef i32 @_Z1Fv()
  %182 = lshr i32 %181, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %182)
  tail call void @_Z17BitReorganizationv()
  %183 = tail call noundef i32 @_Z1Fv()
  %184 = lshr i32 %183, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %184)
  tail call void @_Z17BitReorganizationv()
  %185 = tail call noundef i32 @_Z1Fv()
  %186 = lshr i32 %185, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %186)
  tail call void @_Z17BitReorganizationv()
  %187 = tail call noundef i32 @_Z1Fv()
  %188 = lshr i32 %187, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %188)
  tail call void @_Z17BitReorganizationv()
  %189 = tail call noundef i32 @_Z1Fv()
  %190 = lshr i32 %189, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %190)
  tail call void @_Z17BitReorganizationv()
  %191 = tail call noundef i32 @_Z1Fv()
  %192 = lshr i32 %191, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %192)
  tail call void @_Z17BitReorganizationv()
  %193 = tail call noundef i32 @_Z1Fv()
  %194 = lshr i32 %193, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %194)
  tail call void @_Z17BitReorganizationv()
  %195 = tail call noundef i32 @_Z1Fv()
  %196 = lshr i32 %195, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %196)
  tail call void @_Z17BitReorganizationv()
  %197 = tail call noundef i32 @_Z1Fv()
  %198 = lshr i32 %197, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %198)
  tail call void @_Z17BitReorganizationv()
  %199 = tail call noundef i32 @_Z1Fv()
  %200 = lshr i32 %199, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %200)
  tail call void @_Z17BitReorganizationv()
  %201 = tail call noundef i32 @_Z1Fv()
  %202 = lshr i32 %201, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %202)
  tail call void @_Z17BitReorganizationv()
  %203 = tail call noundef i32 @_Z1Fv()
  %204 = lshr i32 %203, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %204)
  tail call void @_Z17BitReorganizationv()
  %205 = tail call noundef i32 @_Z1Fv()
  %206 = lshr i32 %205, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %206)
  tail call void @_Z17BitReorganizationv()
  %207 = tail call noundef i32 @_Z1Fv()
  %208 = lshr i32 %207, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %208)
  tail call void @_Z17BitReorganizationv()
  %209 = tail call noundef i32 @_Z1Fv()
  %210 = lshr i32 %209, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %210)
  tail call void @_Z17BitReorganizationv()
  %211 = tail call noundef i32 @_Z1Fv()
  %212 = lshr i32 %211, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %212)
  tail call void @_Z17BitReorganizationv()
  %213 = tail call noundef i32 @_Z1Fv()
  %214 = lshr i32 %213, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %214)
  tail call void @_Z17BitReorganizationv()
  %215 = tail call noundef i32 @_Z1Fv()
  %216 = lshr i32 %215, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %216)
  tail call void @_Z17BitReorganizationv()
  %217 = tail call noundef i32 @_Z1Fv()
  %218 = lshr i32 %217, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %218)
  tail call void @_Z17BitReorganizationv()
  %219 = tail call noundef i32 @_Z1Fv()
  %220 = lshr i32 %219, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %220)
  tail call void @_Z17BitReorganizationv()
  %221 = tail call noundef i32 @_Z1Fv()
  %222 = lshr i32 %221, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %222)
  tail call void @_Z17BitReorganizationv()
  %223 = tail call noundef i32 @_Z1Fv()
  %224 = lshr i32 %223, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %224)
  tail call void @_Z17BitReorganizationv()
  %225 = tail call noundef i32 @_Z1Fv()
  %226 = lshr i32 %225, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %226)
  tail call void @_Z17BitReorganizationv()
  %227 = tail call noundef i32 @_Z1Fv()
  %228 = lshr i32 %227, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %228)
  tail call void @_Z17BitReorganizationv()
  %229 = tail call noundef i32 @_Z1Fv()
  %230 = lshr i32 %229, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %230)
  tail call void @_Z17BitReorganizationv()
  %231 = tail call noundef i32 @_Z1Fv()
  %232 = lshr i32 %231, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %232)
  tail call void @_Z17BitReorganizationv()
  %233 = tail call noundef i32 @_Z1Fv()
  %234 = lshr i32 %233, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %234)
  tail call void @_Z17BitReorganizationv()
  %235 = tail call noundef i32 @_Z1Fv()
  %236 = lshr i32 %235, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %236)
  tail call void @_Z17BitReorganizationv()
  %237 = tail call noundef i32 @_Z1Fv()
  %238 = lshr i32 %237, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %238)
  tail call void @_Z17BitReorganizationv()
  %239 = tail call noundef i32 @_Z1Fv()
  %240 = lshr i32 %239, 1
  tail call void @_Z26LFSRWithInitializationModej(i32 noundef %240)
  tail call void @_Z17BitReorganizationv()
  %241 = tail call noundef i32 @_Z1Fv()
  tail call void @_Z16LFSRWithWorkModev()
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass