; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/OptionRomPkg/Bus/Usb (Ax88772Crc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @Ax88772Crc(ptr noundef %0) #0 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  store i32 -1, ptr %5, align 4, !tbaa !9
  %8 = load ptr, ptr %2, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %8, i64 6
  store ptr %9, ptr %7, align 8, !tbaa !5
  br label %10

10:                                               ; preds = %42, %1
  %11 = load ptr, ptr %7, align 8, !tbaa !5
  %12 = load ptr, ptr %2, align 8, !tbaa !5
  %13 = icmp ugt ptr %11, %12
  br i1 %13, label %14, label %43

14:                                               ; preds = %10
  %15 = load ptr, ptr %2, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %15, i32 1
  store ptr %16, ptr %2, align 8, !tbaa !5
  %17 = load i8, ptr %15, align 1, !tbaa !11
  %18 = zext i8 %17 to i32
  store i32 %18, ptr %6, align 4, !tbaa !9
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %19

19:                                               ; preds = %39, %14
  %20 = load i32, ptr %3, align 4, !tbaa !9
  %21 = icmp ugt i32 8, %20
  br i1 %21, label %22, label %42

22:                                               ; preds = %19
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = ashr i32 %23, 31
  %25 = and i32 %24, 1
  %26 = load i32, ptr %6, align 4, !tbaa !9
  %27 = and i32 %26, 1
  %28 = xor i32 %25, %27
  store i32 %28, ptr %4, align 4, !tbaa !9
  %29 = load i32, ptr %5, align 4, !tbaa !9
  %30 = shl i32 %29, 1
  store i32 %30, ptr %5, align 4, !tbaa !9
  %31 = load i32, ptr %4, align 4, !tbaa !9
  %32 = icmp ne i32 0, %31
  br i1 %32, label %33, label %36

33:                                               ; preds = %22
  %34 = load i32, ptr %5, align 4, !tbaa !9
  %35 = xor i32 %34, 79764919
  store i32 %35, ptr %5, align 4, !tbaa !9
  br label %36

36:                                               ; preds = %33, %22
  %37 = load i32, ptr %6, align 4, !tbaa !9
  %38 = lshr i32 %37, 1
  store i32 %38, ptr %6, align 4, !tbaa !9
  br label %39

39:                                               ; preds = %36
  %40 = load i32, ptr %3, align 4, !tbaa !9
  %41 = add i32 %40, 1
  store i32 %41, ptr %3, align 4, !tbaa !9
  br label %19, !llvm.loop !12

42:                                               ; preds = %19
  br label %10, !llvm.loop !14

43:                                               ; preds = %10
  %44 = load i32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret i32 %44
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
define dso_local i32 @Ax88772Crc(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
  br label %.loopexit

.loopexit:                                        ; preds = %1, %.loopexit
  %.0.idx19 = phi i64 [ 0, %1 ], [ %.0.add, %.loopexit ]
  %.01318 = phi i32 [ -1, %1 ], [ %spec.select.7, %.loopexit ]
  %.0.ptr = getelementptr inbounds i8, ptr %0, i64 %.0.idx19
  %2 = load i8, ptr %.0.ptr, align 1, !tbaa !5
  %3 = zext i8 %2 to i32
  %4 = lshr i32 %.01318, 31
  %5 = and i32 %3, 1
  %6 = shl i32 %.01318, 1
  %.not = icmp eq i32 %4, %5
  %7 = xor i32 %6, 79764919
  %spec.select = select i1 %.not, i32 %6, i32 %7
  %8 = lshr i32 %3, 1
  %9 = lshr i32 %spec.select, 31
  %10 = and i32 %8, 1
  %11 = shl i32 %spec.select, 1
  %.not.1 = icmp eq i32 %9, %10
  %12 = xor i32 %11, 79764919
  %spec.select.1 = select i1 %.not.1, i32 %11, i32 %12
  %13 = lshr i32 %3, 2
  %14 = lshr i32 %spec.select.1, 31
  %15 = and i32 %13, 1
  %16 = shl i32 %spec.select.1, 1
  %.not.2 = icmp eq i32 %14, %15
  %17 = xor i32 %16, 79764919
  %spec.select.2 = select i1 %.not.2, i32 %16, i32 %17
  %18 = lshr i32 %3, 3
  %19 = lshr i32 %spec.select.2, 31
  %20 = and i32 %18, 1
  %21 = shl i32 %spec.select.2, 1
  %.not.3 = icmp eq i32 %19, %20
  %22 = xor i32 %21, 79764919
  %spec.select.3 = select i1 %.not.3, i32 %21, i32 %22
  %23 = lshr i32 %3, 4
  %24 = lshr i32 %spec.select.3, 31
  %25 = and i32 %23, 1
  %26 = shl i32 %spec.select.3, 1
  %.not.4 = icmp eq i32 %24, %25
  %27 = xor i32 %26, 79764919
  %spec.select.4 = select i1 %.not.4, i32 %26, i32 %27
  %28 = lshr i32 %3, 5
  %29 = lshr i32 %spec.select.4, 31
  %30 = and i32 %28, 1
  %31 = shl i32 %spec.select.4, 1
  %.not.5 = icmp eq i32 %29, %30
  %32 = xor i32 %31, 79764919
  %spec.select.5 = select i1 %.not.5, i32 %31, i32 %32
  %33 = lshr i32 %3, 6
  %34 = lshr i32 %spec.select.5, 31
  %35 = and i32 %33, 1
  %36 = shl i32 %spec.select.5, 1
  %.not.6 = icmp eq i32 %34, %35
  %37 = xor i32 %36, 79764919
  %spec.select.6 = select i1 %.not.6, i32 %36, i32 %37
  %38 = lshr i32 %3, 7
  %39 = lshr i32 %spec.select.6, 31
  %40 = shl i32 %spec.select.6, 1
  %.not.7 = icmp eq i32 %39, %38
  %41 = xor i32 %40, 79764919
  %spec.select.7 = select i1 %.not.7, i32 %40, i32 %41
  %.0.add = add nuw nsw i64 %.0.idx19, 1
  %exitcond.not = icmp eq i64 %.0.add, 6
  br i1 %exitcond.not, label %42, label %.loopexit, !llvm.loop !8

42:                                               ; preds = %.loopexit
  ret i32 %spec.select.7
}

attributes #0 = { nofree norecurse nosync nounwind memory(argmem: read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass