; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_time.ll (ZN7sc_core7sc_timeC2Eyb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector.0", ptr, %"class.std::vector.10", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.sc_core::sc_time_params" = type <{ double, i8, i8, [6 x i8], i64, i8, [7 x i8] }>

@_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E = external constant [0 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [83 x i8], align 1
@_ZZN7sc_core7sc_timeC1EybE16warn_constructor = external hidden global i8, align 1
@.str.2 = external hidden unnamed_addr constant [45 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef double @_ZN5sc_dt16uint64_to_doubleEy(i64 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core7sc_timeC2Eyb(ptr noundef nonnull align 8 dereferenceable(8) %0, i64 noundef %1, i1 noundef zeroext %2) unnamed_addr #4 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca double, align 8
  %9 = alloca double, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  %10 = zext i1 %2 to i8
  store i8 %10, ptr %6, align 1, !tbaa !11
  %11 = load ptr, ptr %4, align 8
  %12 = getelementptr inbounds %"class.sc_core::sc_time", ptr %11, i32 0, i32 0
  store i64 0, ptr %12, align 8, !tbaa !13
  %13 = load i8, ptr @_ZZN7sc_core7sc_timeC1EybE16warn_constructor, align 1, !tbaa !11, !range !15, !noundef !16
  %14 = trunc i8 %13 to i1
  br i1 %14, label %15, label %16

15:                                               ; preds = %3
  store i8 0, ptr @_ZZN7sc_core7sc_timeC1EybE16warn_constructor, align 1, !tbaa !11
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 0, ptr noundef @_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E, ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 143)
  br label %16

16:                                               ; preds = %15, %3
  %17 = load i64, ptr %5, align 8, !tbaa !9
  %18 = icmp ne i64 %17, 0
  br i1 %18, label %19, label %43

19:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  %20 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %21 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %20, i32 0, i32 21
  %22 = load ptr, ptr %21, align 8, !tbaa !17
  store ptr %22, ptr %7, align 8, !tbaa !5
  %23 = load i8, ptr %6, align 1, !tbaa !11, !range !15, !noundef !16
  %24 = trunc i8 %23 to i1
  br i1 %24, label %25, label %37

25:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %26 = load ptr, ptr %7, align 8, !tbaa !5
  %27 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %26, i32 0, i32 4
  %28 = load i64, ptr %27, align 8, !tbaa !40
  %29 = call noundef double @_ZN5sc_dt16uint64_to_doubleEy(i64 noundef %28)
  store double %29, ptr %8, align 8, !tbaa !43
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #5
  %30 = load i64, ptr %5, align 8, !tbaa !9
  %31 = call noundef double @_ZN5sc_dt16uint64_to_doubleEy(i64 noundef %30)
  %32 = load double, ptr %8, align 8, !tbaa !43
  %33 = call double @llvm.fmuladd.f64(double %31, double %32, double 5.000000e-01)
  store volatile double %33, ptr %9, align 8, !tbaa !43
  %34 = load volatile double, ptr %9, align 8, !tbaa !43
  %35 = fptosi double %34 to i64
  %36 = getelementptr inbounds %"class.sc_core::sc_time", ptr %11, i32 0, i32 0
  store i64 %35, ptr %36, align 8, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  br label %40

37:                                               ; preds = %19
  %38 = load i64, ptr %5, align 8, !tbaa !9
  %39 = getelementptr inbounds %"class.sc_core::sc_time", ptr %11, i32 0, i32 0
  store i64 %38, ptr %39, align 8, !tbaa !13
  br label %40

40:                                               ; preds = %37, %25
  %41 = load ptr, ptr %7, align 8, !tbaa !5
  %42 = getelementptr inbounds %"struct.sc_core::sc_time_params", ptr %41, i32 0, i32 2
  store i8 1, ptr %42, align 1, !tbaa !44
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %43

43:                                               ; preds = %40, %16
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{!14, !10, i64 0}
!14 = !{!"_ZTSN7sc_core7sc_timeE", !10, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = !{!18, !6, i64 248}
!18 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !19, i64 64, !6, i64 80, !12, i64 88, !21, i64 92, !22, i64 96, !26, i64 120, !30, i64 144, !26, i64 168, !6, i64 192, !34, i64 200, !12, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !14, i64 256, !14, i64 264, !6, i64 272, !10, i64 280, !10, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !38, i64 300, !6, i64 304, !12, i64 312, !12, i64 313, !39, i64 316, !12, i64 320, !6, i64 328, !6, i64 336}
!19 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !20, i64 8}
!20 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!21 = !{!"int", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!39 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!40 = !{!41, !10, i64 16}
!41 = !{!"_ZTSN7sc_core14sc_time_paramsE", !42, i64 0, !12, i64 8, !12, i64 9, !10, i64 16, !12, i64 24}
!42 = !{!"double", !7, i64 0}
!43 = !{!42, !42, i64 0}
!44 = !{!41, !12, i64 9}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E = external constant [0 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [83 x i8], align 1
@_ZZN7sc_core7sc_timeC1EybE16warn_constructor = external hidden local_unnamed_addr global i8, align 1
@.str.2 = external hidden unnamed_addr constant [45 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef double @_ZN5sc_dt16uint64_to_doubleEy(i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core7sc_timeC2Eyb(ptr nocapture noundef nonnull writeonly align 8 dereferenceable(8) %0, i64 noundef %1, i1 noundef zeroext %2) unnamed_addr #4 align 2 {
  %4 = alloca double, align 8
  store i64 0, ptr %0, align 8, !tbaa !5
  %5 = load i8, ptr @_ZZN7sc_core7sc_timeC1EybE16warn_constructor, align 1, !tbaa !10, !range !12, !noundef !13
  %6 = trunc nuw i8 %5 to i1
  br i1 %6, label %7, label %8

7:                                                ; preds = %3
  store i8 0, ptr @_ZZN7sc_core7sc_timeC1EybE16warn_constructor, align 1, !tbaa !10
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 0, ptr noundef nonnull @_ZN7sc_core28SC_ID_IEEE_1666_DEPRECATION_E, ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 143)
  br label %8

8:                                                ; preds = %7, %3
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %22, label %9

9:                                                ; preds = %8
  %10 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %11 = getelementptr inbounds i8, ptr %10, i64 248
  %12 = load ptr, ptr %11, align 8, !tbaa !14
  br i1 %2, label %13, label %20

13:                                               ; preds = %9
  %14 = getelementptr inbounds i8, ptr %12, i64 16
  %15 = load i64, ptr %14, align 8, !tbaa !38
  %16 = tail call noundef double @_ZN5sc_dt16uint64_to_doubleEy(i64 noundef %15)
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4)
  %17 = tail call noundef double @_ZN5sc_dt16uint64_to_doubleEy(i64 noundef %1)
  %18 = tail call double @llvm.fmuladd.f64(double %17, double %16, double 5.000000e-01)
  store volatile double %18, ptr %4, align 8, !tbaa !41
  %.0..0..0..0. = load volatile double, ptr %4, align 8, !tbaa !41
  %19 = fptosi double %.0..0..0..0. to i64
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4)
  br label %20

20:                                               ; preds = %9, %13
  %.sink = phi i64 [ %19, %13 ], [ %1, %9 ]
  store i64 %.sink, ptr %0, align 8
  %21 = getelementptr inbounds i8, ptr %12, i64 9
  store i8 1, ptr %21, align 1, !tbaa !42
  br label %22

22:                                               ; preds = %20, %8
  ret void
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7sc_core7sc_timeE", !7, i64 0}
!7 = !{!"long long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!11, !11, i64 0}
!11 = !{!"bool", !8, i64 0}
!12 = !{i8 0, i8 2}
!13 = !{}
!14 = !{!15, !16, i64 248}
!15 = !{!"_ZTSN7sc_core13sc_simcontextE", !16, i64 0, !16, i64 8, !16, i64 16, !16, i64 24, !16, i64 32, !16, i64 40, !16, i64 48, !16, i64 56, !17, i64 64, !16, i64 80, !11, i64 88, !19, i64 92, !20, i64 96, !24, i64 120, !28, i64 144, !24, i64 168, !16, i64 192, !32, i64 200, !11, i64 224, !16, i64 232, !16, i64 240, !16, i64 248, !6, i64 256, !6, i64 264, !16, i64 272, !7, i64 280, !7, i64 288, !11, i64 296, !11, i64 297, !11, i64 298, !11, i64 299, !36, i64 300, !16, i64 304, !11, i64 312, !11, i64 313, !37, i64 316, !11, i64 320, !16, i64 328, !16, i64 336}
!16 = !{!"any pointer", !8, i64 0}
!17 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !16, i64 0, !18, i64 8}
!18 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!19 = !{!"int", !8, i64 0}
!20 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!24 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!28 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!32 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!36 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!37 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!38 = !{!39, !7, i64 16}
!39 = !{!"_ZTSN7sc_core14sc_time_paramsE", !40, i64 0, !11, i64 8, !11, i64 9, !7, i64 16, !11, i64 24}
!40 = !{!"double", !8, i64 0}
!41 = !{!40, !40, i64 0}
!42 = !{!39, !11, i64 9}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MergedLoadStoreMotionPass,PostOrderFunctionAttrsPass,SROAPass,TailCallElimPass