; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/utils (sc_hash)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_phash_base" = type { ptr, i32, i32, i32, i32, double, ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_phash_baseC2EPviidbPFjPKvEPFiS3_S3_E(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, double noundef %4, i1 noundef zeroext %5, ptr noundef %6, ptr noundef %7) unnamed_addr #0 align 2 {
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca double, align 8
  %14 = alloca i8, align 1
  %15 = alloca ptr, align 8
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  store ptr %0, ptr %9, align 8, !tbaa !5
  store ptr %1, ptr %10, align 8, !tbaa !5
  store i32 %2, ptr %11, align 4, !tbaa !9
  store i32 %3, ptr %12, align 4, !tbaa !9
  store double %4, ptr %13, align 8, !tbaa !11
  %18 = zext i1 %5 to i8
  store i8 %18, ptr %14, align 1, !tbaa !13
  store ptr %6, ptr %15, align 8, !tbaa !5
  store ptr %7, ptr %16, align 8, !tbaa !5
  %19 = load ptr, ptr %9, align 8
  %20 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 0
  %21 = load ptr, ptr %10, align 8, !tbaa !5
  store ptr %21, ptr %20, align 8, !tbaa !15
  %22 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 1
  store i32 0, ptr %22, align 8, !tbaa !17
  %23 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 2
  store i32 0, ptr %23, align 4, !tbaa !18
  %24 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 3
  %25 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %25, ptr %24, align 8, !tbaa !19
  %26 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 4
  %27 = load i8, ptr %14, align 1, !tbaa !13, !range !20, !noundef !21
  %28 = trunc i8 %27 to i1
  %29 = zext i1 %28 to i32
  store i32 %29, ptr %26, align 4, !tbaa !22
  %30 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 5
  %31 = load double, ptr %13, align 8, !tbaa !11
  store double %31, ptr %30, align 8, !tbaa !23
  %32 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 6
  store ptr null, ptr %32, align 8, !tbaa !24
  %33 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 7
  %34 = load ptr, ptr %15, align 8, !tbaa !5
  store ptr %34, ptr %33, align 8, !tbaa !25
  %35 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 8
  %36 = load ptr, ptr %16, align 8, !tbaa !5
  store ptr %36, ptr %35, align 8, !tbaa !26
  %37 = load i32, ptr %11, align 4, !tbaa !9
  %38 = icmp sle i32 %37, 0
  br i1 %38, label %39, label %40

39:                                               ; preds = %8
  store i32 11, ptr %11, align 4, !tbaa !9
  br label %48

40:                                               ; preds = %8
  %41 = load i32, ptr %11, align 4, !tbaa !9
  %42 = srem i32 %41, 2
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %47

44:                                               ; preds = %40
  %45 = load i32, ptr %11, align 4, !tbaa !9
  %46 = add nsw i32 %45, 1
  store i32 %46, ptr %11, align 4, !tbaa !9
  br label %47

47:                                               ; preds = %44, %40
  br label %48

48:                                               ; preds = %47, %39
  %49 = load i32, ptr %11, align 4, !tbaa !9
  %50 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 1
  store i32 %49, ptr %50, align 8, !tbaa !17
  %51 = load i32, ptr %11, align 4, !tbaa !9
  %52 = sext i32 %51 to i64
  %53 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %52, i64 8)
  %54 = extractvalue { i64, i1 } %53, 1
  %55 = extractvalue { i64, i1 } %53, 0
  %56 = select i1 %54, i64 -1, i64 %55
  %57 = call noalias noundef nonnull ptr @_Znam(i64 noundef %56) #4
  %58 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 6
  store ptr %57, ptr %58, align 8, !tbaa !24
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #5
  store i32 0, ptr %17, align 4, !tbaa !9
  br label %59

59:                                               ; preds = %70, %48
  %60 = load i32, ptr %17, align 4, !tbaa !9
  %61 = load i32, ptr %11, align 4, !tbaa !9
  %62 = icmp slt i32 %60, %61
  br i1 %62, label %64, label %63

63:                                               ; preds = %59
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #5
  br label %73

64:                                               ; preds = %59
  %65 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %19, i32 0, i32 6
  %66 = load ptr, ptr %65, align 8, !tbaa !24
  %67 = load i32, ptr %17, align 4, !tbaa !9
  %68 = sext i32 %67 to i64
  %69 = getelementptr inbounds ptr, ptr %66, i64 %68
  store ptr null, ptr %69, align 8, !tbaa !5
  br label %70

70:                                               ; preds = %64
  %71 = load i32, ptr %17, align 4, !tbaa !9
  %72 = add nsw i32 %71, 1
  store i32 %72, ptr %17, align 4, !tbaa !9
  br label %59, !llvm.loop !27

73:                                               ; preds = %63
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #1

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { builtin allocsize(0) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"double", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{!16, !6, i64 0}
!16 = !{!"_ZTSN7sc_core13sc_phash_baseE", !6, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !12, i64 24, !6, i64 32, !6, i64 40, !6, i64 48}
!17 = !{!16, !10, i64 8}
!18 = !{!16, !10, i64 12}
!19 = !{!16, !10, i64 16}
!20 = !{i8 0, i8 2}
!21 = !{}
!22 = !{!16, !10, i64 20}
!23 = !{!16, !12, i64 24}
!24 = !{!16, !6, i64 32}
!25 = !{!16, !6, i64 40}
!26 = !{!16, !6, i64 48}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_phash_baseC2EPviidbPFjPKvEPFiS3_S3_E(ptr nocapture noundef nonnull align 8 dereferenceable(56) %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, double noundef %4, i1 noundef zeroext %5, ptr noundef %6, ptr noundef %7) unnamed_addr #0 align 2 {
  store ptr %1, ptr %0, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %0, i64 8
  %10 = getelementptr inbounds i8, ptr %0, i64 12
  store i32 0, ptr %10, align 4, !tbaa !12
  %11 = getelementptr inbounds i8, ptr %0, i64 16
  store i32 %3, ptr %11, align 8, !tbaa !13
  %12 = getelementptr inbounds i8, ptr %0, i64 20
  %13 = zext i1 %5 to i32
  store i32 %13, ptr %12, align 4, !tbaa !14
  %14 = getelementptr inbounds i8, ptr %0, i64 24
  store double %4, ptr %14, align 8, !tbaa !15
  %15 = getelementptr inbounds i8, ptr %0, i64 32
  store ptr null, ptr %15, align 8, !tbaa !16
  %16 = getelementptr inbounds i8, ptr %0, i64 40
  store ptr %6, ptr %16, align 8, !tbaa !17
  %17 = getelementptr inbounds i8, ptr %0, i64 48
  store ptr %7, ptr %17, align 8, !tbaa !18
  %18 = icmp slt i32 %2, 1
  %spec.select = or i32 %2, 1
  %.015 = select i1 %18, i32 11, i32 %spec.select
  store i32 %.015, ptr %9, align 8, !tbaa !19
  %19 = zext i32 %.015 to i64
  %20 = shl nuw nsw i64 %19, 3
  %21 = tail call noalias noundef nonnull ptr @_Znam(i64 noundef %20) #2
  store ptr %21, ptr %15, align 8, !tbaa !16
  %22 = icmp sgt i32 %.015, 0
  br i1 %22, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %8
  %xtraiter = and i64 %19, 3
  %23 = icmp ult i32 %.015, 4
  br i1 %23, label %.lr.ph.epil.preheader, label %.lr.ph.preheader.new

.lr.ph.preheader.new:                             ; preds = %.lr.ph.preheader
  %unroll_iter = and i64 %19, 2147483644
  br label %.lr.ph

.lr.ph.epil.preheader:                            ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv.unr = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next.3, %.lr.ph ]
  br label %.lr.ph.epil

.lr.ph.epil:                                      ; preds = %.lr.ph.epil, %.lr.ph.epil.preheader
  %indvars.iv.epil = phi i64 [ %indvars.iv.next.epil, %.lr.ph.epil ], [ %indvars.iv.unr, %.lr.ph.epil.preheader ]
  %epil.iter = phi i64 [ %epil.iter.next, %.lr.ph.epil ], [ 0, %.lr.ph.epil.preheader ]
  %24 = load ptr, ptr %15, align 8, !tbaa !16
  %25 = getelementptr inbounds ptr, ptr %24, i64 %indvars.iv.epil
  store ptr null, ptr %25, align 8, !tbaa !20
  %indvars.iv.next.epil = add nuw nsw i64 %indvars.iv.epil, 1
  %epil.iter.next = add i64 %epil.iter, 1
  %epil.iter.cmp.not = icmp eq i64 %epil.iter.next, %xtraiter
  br i1 %epil.iter.cmp.not, label %._crit_edge, label %.lr.ph.epil, !llvm.loop !21

._crit_edge:                                      ; preds = %.lr.ph.epil, %8
  ret void

.lr.ph:                                           ; preds = %.lr.ph, %.lr.ph.preheader.new
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader.new ], [ %indvars.iv.next.3, %.lr.ph ]
  %niter = phi i64 [ 0, %.lr.ph.preheader.new ], [ %niter.next.3, %.lr.ph ]
  %26 = load ptr, ptr %15, align 8, !tbaa !16
  %27 = getelementptr inbounds ptr, ptr %26, i64 %indvars.iv
  store ptr null, ptr %27, align 8, !tbaa !20
  %indvars.iv.next = or disjoint i64 %indvars.iv, 1
  %28 = load ptr, ptr %15, align 8, !tbaa !16
  %29 = getelementptr inbounds ptr, ptr %28, i64 %indvars.iv.next
  store ptr null, ptr %29, align 8, !tbaa !20
  %indvars.iv.next.1 = or disjoint i64 %indvars.iv, 2
  %30 = load ptr, ptr %15, align 8, !tbaa !16
  %31 = getelementptr inbounds ptr, ptr %30, i64 %indvars.iv.next.1
  store ptr null, ptr %31, align 8, !tbaa !20
  %indvars.iv.next.2 = or disjoint i64 %indvars.iv, 3
  %32 = load ptr, ptr %15, align 8, !tbaa !16
  %33 = getelementptr inbounds ptr, ptr %32, i64 %indvars.iv.next.2
  store ptr null, ptr %33, align 8, !tbaa !20
  %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
  %niter.next.3 = add i64 %niter, 4
  %niter.ncmp.3 = icmp eq i64 %niter.next.3, %unroll_iter
  br i1 %niter.ncmp.3, label %.lr.ph.epil.preheader, label %.lr.ph, !llvm.loop !23
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7sc_core13sc_phash_baseE", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !11, i64 24, !7, i64 32, !7, i64 40, !7, i64 48}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"double", !8, i64 0}
!12 = !{!6, !10, i64 12}
!13 = !{!6, !10, i64 16}
!14 = !{!6, !10, i64 20}
!15 = !{!6, !11, i64 24}
!16 = !{!6, !7, i64 32}
!17 = !{!6, !7, i64 40}
!18 = !{!6, !7, i64 48}
!19 = !{!6, !10, i64 8}
!20 = !{!7, !7, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.unroll.disable"}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass