; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo (cycle_model)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.operand = type { i32, i32 }
%struct.cycle_model = type <{ %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [65536 x i32], [65536 x i32], [2048 x i32], i32, [8 x i32], [4 x i8], ptr, i32, i32, i32, [4 x i8] }>
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.stack_el = type { i32, ptr }

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str.10 = external hidden unnamed_addr constant [118 x i8], align 1
@.str.12 = external hidden unnamed_addr constant [26 x i8], align 1
@.str.14 = external hidden unnamed_addr constant [27 x i8], align 1
@.str.15 = external hidden unnamed_addr constant [39 x i8], align 1
@.str.16 = external hidden unnamed_addr constant [27 x i8], align 1
@.str.17 = external hidden unnamed_addr constant [27 x i8], align 1
@.str.19 = external hidden unnamed_addr constant [27 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN11cycle_model11fetch_instrEi(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN11cycle_model10write_dataEii(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef, i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN11cycle_model10write_backEP7operandi(ptr noundef nonnull align 8 dereferenceable(533052) %0, ptr noundef %1, i32 noundef %2) #2 align 2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  %12 = load ptr, ptr %5, align 8
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.operand, ptr %13, i32 0, i32 0
  %15 = load i32, ptr %14, align 4, !tbaa !11
  switch i32 %15, label %171 [
    i32 1, label %16
    i32 2, label %21
    i32 3, label %49
    i32 4, label %79
    i32 5, label %136
  ]

16:                                               ; preds = %3
  %17 = load i32, ptr %7, align 4, !tbaa !9
  %18 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 17
  store i32 %17, ptr %18, align 8, !tbaa !14
  %19 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 17
  %20 = load i32, ptr %19, align 8, !tbaa !14
  store i32 %20, ptr %4, align 4
  br label %172

21:                                               ; preds = %3
  %22 = load ptr, ptr %6, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.operand, ptr %22, i32 0, i32 1
  %24 = load i32, ptr %23, align 4, !tbaa !45
  %25 = icmp slt i32 %24, 8
  br i1 %25, label %26, label %32

26:                                               ; preds = %21
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.operand, ptr %27, i32 0, i32 1
  %29 = load i32, ptr %28, align 4, !tbaa !45
  %30 = icmp sge i32 %29, 0
  br i1 %30, label %31, label %32

31:                                               ; preds = %26
  br label %33

32:                                               ; preds = %26, %21
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.12, ptr noundef @.str.10, i32 noundef 1465)
  br label %33

33:                                               ; preds = %32, %31
  %34 = phi i32 [ 0, %31 ], [ 0, %32 ]
  %35 = load i32, ptr %7, align 4, !tbaa !9
  %36 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %37 = load ptr, ptr %6, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.operand, ptr %37, i32 0, i32 1
  %39 = load i32, ptr %38, align 4, !tbaa !45
  %40 = sext i32 %39 to i64
  %41 = getelementptr inbounds [8 x i32], ptr %36, i64 0, i64 %40
  store i32 %35, ptr %41, align 4, !tbaa !9
  %42 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.operand, ptr %43, i32 0, i32 1
  %45 = load i32, ptr %44, align 4, !tbaa !45
  %46 = sext i32 %45 to i64
  %47 = getelementptr inbounds [8 x i32], ptr %42, i64 0, i64 %46
  %48 = load i32, ptr %47, align 4, !tbaa !9
  store i32 %48, ptr %4, align 4
  br label %172

49:                                               ; preds = %3
  %50 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 20
  %51 = load ptr, ptr %50, align 8, !tbaa !46
  %52 = getelementptr inbounds %struct.stack_el, ptr %51, i32 0, i32 0
  %53 = load i32, ptr %52, align 8, !tbaa !47
  %54 = add nsw i32 %53, 1
  store i32 %54, ptr %52, align 8, !tbaa !47
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %55 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 20
  %56 = load ptr, ptr %55, align 8, !tbaa !46
  %57 = getelementptr inbounds %struct.stack_el, ptr %56, i32 0, i32 0
  %58 = load i32, ptr %57, align 8, !tbaa !47
  %59 = call noundef i32 @_ZN11cycle_model11fetch_instrEi(ptr noundef nonnull align 8 dereferenceable(533052) %12, i32 noundef %58)
  store i32 %59, ptr %8, align 4, !tbaa !9
  %60 = load i32, ptr %8, align 4, !tbaa !9
  %61 = icmp slt i32 %60, 2048
  br i1 %61, label %62, label %66

62:                                               ; preds = %49
  %63 = load i32, ptr %8, align 4, !tbaa !9
  %64 = icmp sge i32 %63, 0
  br i1 %64, label %65, label %66

65:                                               ; preds = %62
  br label %67

66:                                               ; preds = %62, %49
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.19, ptr noundef @.str.10, i32 noundef 1477)
  br label %67

67:                                               ; preds = %66, %65
  %68 = phi i32 [ 0, %65 ], [ 0, %66 ]
  %69 = load i32, ptr %7, align 4, !tbaa !9
  %70 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 16
  %71 = load i32, ptr %8, align 4, !tbaa !9
  %72 = sext i32 %71 to i64
  %73 = getelementptr inbounds [2048 x i32], ptr %70, i64 0, i64 %72
  store i32 %69, ptr %73, align 4, !tbaa !9
  %74 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 16
  %75 = load i32, ptr %8, align 4, !tbaa !9
  %76 = sext i32 %75 to i64
  %77 = getelementptr inbounds [2048 x i32], ptr %74, i64 0, i64 %76
  %78 = load i32, ptr %77, align 4, !tbaa !9
  store i32 %78, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %172

79:                                               ; preds = %3
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.operand, ptr %80, i32 0, i32 1
  %82 = load i32, ptr %81, align 4, !tbaa !45
  %83 = icmp eq i32 %82, 0
  br i1 %83, label %89, label %84

84:                                               ; preds = %79
  %85 = load ptr, ptr %6, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.operand, ptr %85, i32 0, i32 1
  %87 = load i32, ptr %86, align 4, !tbaa !45
  %88 = icmp eq i32 %87, 1
  br i1 %88, label %89, label %90

89:                                               ; preds = %84, %79
  br label %91

90:                                               ; preds = %84
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.14, ptr noundef @.str.10, i32 noundef 1483)
  br label %91

91:                                               ; preds = %90, %89
  %92 = phi i32 [ 0, %89 ], [ 0, %90 ]
  %93 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %94 = load ptr, ptr %6, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.operand, ptr %94, i32 0, i32 1
  %96 = load i32, ptr %95, align 4, !tbaa !45
  %97 = sext i32 %96 to i64
  %98 = getelementptr inbounds [8 x i32], ptr %93, i64 0, i64 %97
  %99 = load i32, ptr %98, align 4, !tbaa !9
  %100 = icmp slt i32 %99, 2048
  br i1 %100, label %101, label %111

101:                                              ; preds = %91
  %102 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %103 = load ptr, ptr %6, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.operand, ptr %103, i32 0, i32 1
  %105 = load i32, ptr %104, align 4, !tbaa !45
  %106 = sext i32 %105 to i64
  %107 = getelementptr inbounds [8 x i32], ptr %102, i64 0, i64 %106
  %108 = load i32, ptr %107, align 4, !tbaa !9
  %109 = icmp sge i32 %108, 0
  br i1 %109, label %110, label %111

110:                                              ; preds = %101
  br label %112

111:                                              ; preds = %101, %91
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.15, ptr noundef @.str.10, i32 noundef 1484)
  br label %112

112:                                              ; preds = %111, %110
  %113 = phi i32 [ 0, %110 ], [ 0, %111 ]
  %114 = load i32, ptr %7, align 4, !tbaa !9
  %115 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 16
  %116 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %117 = load ptr, ptr %6, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.operand, ptr %117, i32 0, i32 1
  %119 = load i32, ptr %118, align 4, !tbaa !45
  %120 = sext i32 %119 to i64
  %121 = getelementptr inbounds [8 x i32], ptr %116, i64 0, i64 %120
  %122 = load i32, ptr %121, align 4, !tbaa !9
  %123 = sext i32 %122 to i64
  %124 = getelementptr inbounds [2048 x i32], ptr %115, i64 0, i64 %123
  store i32 %114, ptr %124, align 4, !tbaa !9
  %125 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 16
  %126 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %127 = load ptr, ptr %6, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.operand, ptr %127, i32 0, i32 1
  %129 = load i32, ptr %128, align 4, !tbaa !45
  %130 = sext i32 %129 to i64
  %131 = getelementptr inbounds [8 x i32], ptr %126, i64 0, i64 %130
  %132 = load i32, ptr %131, align 4, !tbaa !9
  %133 = sext i32 %132 to i64
  %134 = getelementptr inbounds [2048 x i32], ptr %125, i64 0, i64 %133
  %135 = load i32, ptr %134, align 4, !tbaa !9
  store i32 %135, ptr %4, align 4
  br label %172

136:                                              ; preds = %3
  %137 = load ptr, ptr %6, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.operand, ptr %137, i32 0, i32 1
  %139 = load i32, ptr %138, align 4, !tbaa !45
  %140 = icmp eq i32 %139, 1
  br i1 %140, label %146, label %141

141:                                              ; preds = %136
  %142 = load ptr, ptr %6, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.operand, ptr %142, i32 0, i32 1
  %144 = load i32, ptr %143, align 4, !tbaa !45
  %145 = icmp eq i32 %144, 0
  br i1 %145, label %146, label %147

146:                                              ; preds = %141, %136
  br label %148

147:                                              ; preds = %141
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.16, ptr noundef @.str.10, i32 noundef 1490)
  br label %148

148:                                              ; preds = %147, %146
  %149 = phi i32 [ 0, %146 ], [ 0, %147 ]
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %150 = getelementptr inbounds %struct.cycle_model, ptr %12, i32 0, i32 18
  %151 = load ptr, ptr %6, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.operand, ptr %151, i32 0, i32 1
  %153 = load i32, ptr %152, align 4, !tbaa !45
  %154 = sext i32 %153 to i64
  %155 = getelementptr inbounds [8 x i32], ptr %150, i64 0, i64 %154
  %156 = load i32, ptr %155, align 4, !tbaa !9
  store i32 %156, ptr %9, align 4, !tbaa !9
  %157 = load i32, ptr %9, align 4, !tbaa !9
  %158 = icmp slt i32 %157, 65536
  br i1 %158, label %159, label %163

159:                                              ; preds = %148
  %160 = load i32, ptr %9, align 4, !tbaa !9
  %161 = icmp sge i32 %160, 0
  br i1 %161, label %162, label %163

162:                                              ; preds = %159
  br label %164

163:                                              ; preds = %159, %148
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.17, ptr noundef @.str.10, i32 noundef 1492)
  br label %164

164:                                              ; preds = %163, %162
  %165 = phi i32 [ 0, %162 ], [ 0, %163 ]
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %166 = load i32, ptr %7, align 4, !tbaa !9
  store i32 %166, ptr %10, align 4, !tbaa !9
  %167 = load i32, ptr %9, align 4, !tbaa !9
  %168 = load i32, ptr %10, align 4, !tbaa !9
  %169 = call noundef i32 @_ZN11cycle_model10write_dataEii(ptr noundef nonnull align 8 dereferenceable(533052) %12, i32 noundef %167, i32 noundef %168)
  store i32 %169, ptr %11, align 4, !tbaa !9
  %170 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %170, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %172

171:                                              ; preds = %3
  store i32 -1, ptr %4, align 4
  br label %172

172:                                              ; preds = %171, %164, %112, %67, %33, %16
  %173 = load i32, ptr %4, align 4
  ret i32 %173
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !13, i64 0}
!12 = !{!"_ZTS7operand", !13, i64 0, !10, i64 4}
!13 = !{!"_ZTS7op_type", !7, i64 0}
!14 = !{!15, !10, i64 532992}
!15 = !{!"_ZTS11cycle_model", !16, i64 0, !37, i64 232, !6, i64 416, !6, i64 424, !6, i64 432, !6, i64 440, !6, i64 448, !6, i64 456, !6, i64 464, !6, i64 472, !6, i64 480, !6, i64 488, !6, i64 496, !6, i64 504, !7, i64 512, !7, i64 262656, !7, i64 524800, !10, i64 532992, !7, i64 532996, !6, i64 533032, !10, i64 533040, !10, i64 533044, !10, i64 533048}
!16 = !{!"_ZTSN7sc_core9sc_moduleE", !17, i64 0, !29, i64 112, !30, i64 120, !32, i64 144, !34, i64 168, !36, i64 192, !6, i64 200, !10, i64 208, !6, i64 216, !6, i64 224}
!17 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !18, i64 16, !22, i64 40, !26, i64 64, !6, i64 96, !6, i64 104}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !27, i64 0, !28, i64 8, !7, i64 16}
!27 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!28 = !{!"long", !7, i64 0}
!29 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!30 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !31, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!32 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !33, i64 8, !6, i64 16}
!33 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!34 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !35, i64 8, !6, i64 16}
!35 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!36 = !{!"bool", !7, i64 0}
!37 = !{!"_ZTSN7sc_core5sc_inIbEE", !38, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!38 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !39, i64 0}
!39 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !40, i64 0, !6, i64 120, !41, i64 128}
!40 = !{!"_ZTSN7sc_core12sc_port_baseE", !17, i64 0, !6, i64 112}
!41 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!45 = !{!12, !10, i64 4}
!46 = !{!15, !6, i64 533032}
!47 = !{!48, !10, i64 0}
!48 = !{!"_ZTS8stack_el", !10, i64 0, !6, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str.10 = external hidden unnamed_addr constant [118 x i8], align 1
@.str.12 = external hidden unnamed_addr constant [26 x i8], align 1
@.str.14 = external hidden unnamed_addr constant [27 x i8], align 1
@.str.15 = external hidden unnamed_addr constant [39 x i8], align 1
@.str.16 = external hidden unnamed_addr constant [27 x i8], align 1
@.str.17 = external hidden unnamed_addr constant [27 x i8], align 1
@.str.19 = external hidden unnamed_addr constant [27 x i8], align 1

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN11cycle_model11fetch_instrEi(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN11cycle_model10write_dataEii(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef, i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN11cycle_model10write_backEP7operandi(ptr noundef nonnull align 8 dereferenceable(533052) %0, ptr nocapture noundef readonly %1, i32 noundef %2) local_unnamed_addr #1 align 2 {
  %4 = load i32, ptr %1, align 4, !tbaa !5
  switch i32 %4, label %67 [
    i32 1, label %5
    i32 2, label %7
    i32 3, label %20
    i32 4, label %31
    i32 5, label %54
  ]

5:                                                ; preds = %3
  %6 = getelementptr inbounds i8, ptr %0, i64 532992
  store i32 %2, ptr %6, align 8, !tbaa !11
  br label %67

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %1, i64 4
  %9 = load i32, ptr %8, align 4, !tbaa !43
  %or.cond36 = icmp ult i32 %9, 8
  br i1 %or.cond36, label %11, label %10

10:                                               ; preds = %7
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.12, ptr noundef nonnull @.str.10, i32 noundef 1465)
  %.pre43 = load i32, ptr %8, align 4, !tbaa !43
  br label %11

11:                                               ; preds = %7, %10
  %12 = phi i32 [ %9, %7 ], [ %.pre43, %10 ]
  %13 = getelementptr inbounds i8, ptr %0, i64 532996
  %14 = sext i32 %12 to i64
  %15 = getelementptr inbounds [8 x i32], ptr %13, i64 0, i64 %14
  store i32 %2, ptr %15, align 4, !tbaa !44
  %16 = load i32, ptr %8, align 4, !tbaa !43
  %17 = sext i32 %16 to i64
  %18 = getelementptr inbounds [8 x i32], ptr %13, i64 0, i64 %17
  %19 = load i32, ptr %18, align 4, !tbaa !44
  br label %67

20:                                               ; preds = %3
  %21 = getelementptr inbounds i8, ptr %0, i64 533032
  %22 = load ptr, ptr %21, align 8, !tbaa !45
  %23 = load i32, ptr %22, align 8, !tbaa !46
  %24 = add nsw i32 %23, 1
  store i32 %24, ptr %22, align 8, !tbaa !46
  %25 = tail call noundef i32 @_ZN11cycle_model11fetch_instrEi(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef %24)
  %or.cond = icmp ult i32 %25, 2048
  br i1 %or.cond, label %27, label %26

26:                                               ; preds = %20
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.19, ptr noundef nonnull @.str.10, i32 noundef 1477)
  br label %27

27:                                               ; preds = %20, %26
  %28 = getelementptr inbounds i8, ptr %0, i64 524800
  %29 = sext i32 %25 to i64
  %30 = getelementptr inbounds [2048 x i32], ptr %28, i64 0, i64 %29
  store i32 %2, ptr %30, align 4, !tbaa !44
  br label %67

31:                                               ; preds = %3
  %32 = getelementptr inbounds i8, ptr %1, i64 4
  %33 = load i32, ptr %32, align 4, !tbaa !43
  %switch = icmp ult i32 %33, 2
  br i1 %switch, label %35, label %34

34:                                               ; preds = %31
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.14, ptr noundef nonnull @.str.10, i32 noundef 1483)
  %.pre39 = load i32, ptr %32, align 4, !tbaa !43
  br label %35

35:                                               ; preds = %31, %34
  %36 = phi i32 [ %33, %31 ], [ %.pre39, %34 ]
  %37 = getelementptr inbounds i8, ptr %0, i64 532996
  %38 = sext i32 %36 to i64
  %39 = getelementptr inbounds [8 x i32], ptr %37, i64 0, i64 %38
  %40 = load i32, ptr %39, align 4, !tbaa !44
  %or.cond37 = icmp ult i32 %40, 2048
  br i1 %or.cond37, label %42, label %41

41:                                               ; preds = %35
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.15, ptr noundef nonnull @.str.10, i32 noundef 1484)
  %.pre40 = load i32, ptr %32, align 4, !tbaa !43
  %.phi.trans.insert = sext i32 %.pre40 to i64
  %.phi.trans.insert41 = getelementptr inbounds [8 x i32], ptr %37, i64 0, i64 %.phi.trans.insert
  %.pre42 = load i32, ptr %.phi.trans.insert41, align 4, !tbaa !44
  br label %42

42:                                               ; preds = %35, %41
  %43 = phi i32 [ %40, %35 ], [ %.pre42, %41 ]
  %44 = getelementptr inbounds i8, ptr %0, i64 524800
  %45 = sext i32 %43 to i64
  %46 = getelementptr inbounds [2048 x i32], ptr %44, i64 0, i64 %45
  store i32 %2, ptr %46, align 4, !tbaa !44
  %47 = load i32, ptr %32, align 4, !tbaa !43
  %48 = sext i32 %47 to i64
  %49 = getelementptr inbounds [8 x i32], ptr %37, i64 0, i64 %48
  %50 = load i32, ptr %49, align 4, !tbaa !44
  %51 = sext i32 %50 to i64
  %52 = getelementptr inbounds [2048 x i32], ptr %44, i64 0, i64 %51
  %53 = load i32, ptr %52, align 4, !tbaa !44
  br label %67

54:                                               ; preds = %3
  %55 = getelementptr inbounds i8, ptr %1, i64 4
  %56 = load i32, ptr %55, align 4, !tbaa !43
  %switch38 = icmp ult i32 %56, 2
  br i1 %switch38, label %58, label %57

57:                                               ; preds = %54
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.16, ptr noundef nonnull @.str.10, i32 noundef 1490)
  %.pre = load i32, ptr %55, align 4, !tbaa !43
  br label %58

58:                                               ; preds = %54, %57
  %59 = phi i32 [ %56, %54 ], [ %.pre, %57 ]
  %60 = getelementptr inbounds i8, ptr %0, i64 532996
  %61 = sext i32 %59 to i64
  %62 = getelementptr inbounds [8 x i32], ptr %60, i64 0, i64 %61
  %63 = load i32, ptr %62, align 4, !tbaa !44
  %or.cond3 = icmp ult i32 %63, 65536
  br i1 %or.cond3, label %65, label %64

64:                                               ; preds = %58
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.17, ptr noundef nonnull @.str.10, i32 noundef 1492)
  br label %65

65:                                               ; preds = %58, %64
  %66 = tail call noundef i32 @_ZN11cycle_model10write_dataEii(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef %63, i32 noundef %2)
  br label %67

67:                                               ; preds = %3, %65, %42, %27, %11, %5
  %.0 = phi i32 [ %66, %65 ], [ %53, %42 ], [ %2, %27 ], [ %19, %11 ], [ %2, %5 ], [ -1, %3 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS7operand", !7, i64 0, !10, i64 4}
!7 = !{!"_ZTS7op_type", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!12, !10, i64 532992}
!12 = !{!"_ZTS11cycle_model", !13, i64 0, !35, i64 232, !15, i64 416, !15, i64 424, !15, i64 432, !15, i64 440, !15, i64 448, !15, i64 456, !15, i64 464, !15, i64 472, !15, i64 480, !15, i64 488, !15, i64 496, !15, i64 504, !8, i64 512, !8, i64 262656, !8, i64 524800, !10, i64 532992, !8, i64 532996, !15, i64 533032, !10, i64 533040, !10, i64 533044, !10, i64 533048}
!13 = !{!"_ZTSN7sc_core9sc_moduleE", !14, i64 0, !27, i64 112, !28, i64 120, !30, i64 144, !32, i64 168, !34, i64 192, !15, i64 200, !10, i64 208, !15, i64 216, !15, i64 224}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !15, i64 8, !16, i64 16, !20, i64 40, !24, i64 64, !15, i64 96, !15, i64 104}
!15 = !{!"any pointer", !8, i64 0}
!16 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !25, i64 0, !26, i64 8, !8, i64 16}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !15, i64 0}
!26 = !{!"long", !8, i64 0}
!27 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!28 = !{!"_ZTSN7sc_core12sc_sensitiveE", !15, i64 0, !29, i64 8, !15, i64 16}
!29 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !8, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !15, i64 0, !31, i64 8, !15, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !8, i64 0}
!32 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !15, i64 0, !33, i64 8, !15, i64 16}
!33 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !8, i64 0}
!34 = !{!"bool", !8, i64 0}
!35 = !{!"_ZTSN7sc_core5sc_inIbEE", !36, i64 0, !15, i64 152, !15, i64 160, !15, i64 168, !15, i64 176}
!36 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !37, i64 0}
!37 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !38, i64 0, !15, i64 120, !39, i64 128}
!38 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !15, i64 112}
!39 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !42, i64 0}
!42 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!43 = !{!6, !10, i64 4}
!44 = !{!10, !10, i64 0}
!45 = !{!12, !15, i64 533032}
!46 = !{!47, !10, i64 0}
!47 = !{!"_ZTS8stack_el", !10, i64 0, !15, i64 8}


; Effective O3 passes: BDCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass