; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/sim_tests/biquad/biquad1/biquad.ll (ZN6biquad5entryEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.biquad = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in", %"class.sc_core::sc_out", i32, [4 x float], [5 x float] }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6biquad5entryEv(ptr noundef nonnull align 8 dereferenceable(984) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca float, align 4
  %4 = alloca float, align 4
  %5 = alloca float, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %7 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  %8 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 3
  %9 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %8)
  %10 = load i8, ptr %9, align 1, !tbaa !9, !range !11, !noundef !12
  %11 = trunc i8 %10 to i1
  %12 = zext i1 %11 to i32
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %14, label %24

14:                                               ; preds = %1
  %15 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %16 = getelementptr inbounds [4 x float], ptr %15, i64 0, i64 3
  store float 0.000000e+00, ptr %16, align 4, !tbaa !13
  %17 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %18 = getelementptr inbounds [4 x float], ptr %17, i64 0, i64 2
  store float 0.000000e+00, ptr %18, align 4, !tbaa !13
  %19 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %20 = getelementptr inbounds [4 x float], ptr %19, i64 0, i64 1
  store float 0.000000e+00, ptr %20, align 4, !tbaa !13
  %21 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %22 = getelementptr inbounds [4 x float], ptr %21, i64 0, i64 0
  store float 0.000000e+00, ptr %22, align 4, !tbaa !13
  %23 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store float 0.000000e+00, ptr %5, align 4, !tbaa !13
  call void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176) %23, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  br label %24

24:                                               ; preds = %14, %1
  br label %25

25:                                               ; preds = %56, %24
  br label %26

26:                                               ; preds = %25
  %27 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 2
  %28 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168) %27)
  %29 = load float, ptr %28, align 4, !tbaa !13
  store float %29, ptr %4, align 4, !tbaa !13
  %30 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 7
  %31 = getelementptr inbounds [5 x float], ptr %30, i64 0, i64 0
  %32 = load float, ptr %31, align 4, !tbaa !13
  %33 = load float, ptr %4, align 4, !tbaa !13
  %34 = fmul float %32, %33
  store float %34, ptr %3, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !15
  br label %35

35:                                               ; preds = %53, %26
  %36 = load i32, ptr %6, align 4, !tbaa !15
  %37 = icmp slt i32 %36, 4
  br i1 %37, label %39, label %38

38:                                               ; preds = %35
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %56

39:                                               ; preds = %35
  %40 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 7
  %41 = load i32, ptr %6, align 4, !tbaa !15
  %42 = add nsw i32 %41, 1
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds [5 x float], ptr %40, i64 0, i64 %43
  %45 = load float, ptr %44, align 4, !tbaa !13
  %46 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %47 = load i32, ptr %6, align 4, !tbaa !15
  %48 = sext i32 %47 to i64
  %49 = getelementptr inbounds [4 x float], ptr %46, i64 0, i64 %48
  %50 = load float, ptr %49, align 4, !tbaa !13
  %51 = load float, ptr %3, align 4, !tbaa !13
  %52 = call float @llvm.fmuladd.f32(float %45, float %50, float %51)
  store float %52, ptr %3, align 4, !tbaa !13
  br label %53

53:                                               ; preds = %39
  %54 = load i32, ptr %6, align 4, !tbaa !15
  %55 = add nsw i32 %54, 1
  store i32 %55, ptr %6, align 4, !tbaa !15
  br label %35, !llvm.loop !17

56:                                               ; preds = %38
  %57 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %58 = getelementptr inbounds [4 x float], ptr %57, i64 0, i64 0
  %59 = load float, ptr %58, align 4, !tbaa !13
  %60 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %61 = getelementptr inbounds [4 x float], ptr %60, i64 0, i64 1
  store float %59, ptr %61, align 4, !tbaa !13
  %62 = load float, ptr %4, align 4, !tbaa !13
  %63 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %64 = getelementptr inbounds [4 x float], ptr %63, i64 0, i64 0
  store float %62, ptr %64, align 4, !tbaa !13
  %65 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %66 = getelementptr inbounds [4 x float], ptr %65, i64 0, i64 2
  %67 = load float, ptr %66, align 4, !tbaa !13
  %68 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %69 = getelementptr inbounds [4 x float], ptr %68, i64 0, i64 3
  store float %67, ptr %69, align 4, !tbaa !13
  %70 = load float, ptr %3, align 4, !tbaa !13
  %71 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 6
  %72 = getelementptr inbounds [4 x float], ptr %71, i64 0, i64 2
  store float %70, ptr %72, align 4, !tbaa !13
  %73 = getelementptr inbounds %struct.biquad, ptr %7, i32 0, i32 4
  call void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176) %73, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  br label %25, !llvm.loop !19
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!14, !14, i64 0}
!14 = !{!"float", !7, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"int", !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN6biquad5entryEv(ptr noundef nonnull align 8 dereferenceable(984) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca float, align 4
  %3 = alloca float, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #5
  %4 = getelementptr inbounds i8, ptr %0, i64 584
  %5 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %4)
  %6 = load i8, ptr %5, align 1, !tbaa !5, !range !9, !noundef !10
  %7 = trunc nuw i8 %6 to i1
  br i1 %7, label %8, label %11

8:                                                ; preds = %1
  %9 = getelementptr inbounds i8, ptr %0, i64 948
  %10 = getelementptr inbounds i8, ptr %0, i64 768
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) %9, i8 0, i64 16, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #5
  store float 0.000000e+00, ptr %3, align 4, !tbaa !11
  call void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176) %10, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #5
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  br label %11

11:                                               ; preds = %8, %1
  %12 = getelementptr inbounds i8, ptr %0, i64 416
  %13 = getelementptr inbounds i8, ptr %0, i64 964
  %14 = getelementptr inbounds i8, ptr %0, i64 948
  %15 = getelementptr inbounds i8, ptr %0, i64 952
  %16 = getelementptr inbounds i8, ptr %0, i64 956
  %17 = getelementptr inbounds i8, ptr %0, i64 960
  %18 = getelementptr inbounds i8, ptr %0, i64 768
  %19 = getelementptr inbounds i8, ptr %0, i64 968
  %20 = getelementptr inbounds i8, ptr %0, i64 972
  %21 = getelementptr inbounds i8, ptr %0, i64 952
  %22 = getelementptr inbounds i8, ptr %0, i64 976
  %23 = getelementptr inbounds i8, ptr %0, i64 956
  %24 = getelementptr inbounds i8, ptr %0, i64 980
  %25 = getelementptr inbounds i8, ptr %0, i64 960
  br label %26

26:                                               ; preds = %26, %11
  %27 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168) %12)
  %28 = load float, ptr %27, align 4, !tbaa !11
  %29 = load float, ptr %13, align 4, !tbaa !11
  %30 = fmul float %28, %29
  %31 = load float, ptr %19, align 8, !tbaa !11
  %32 = load float, ptr %14, align 4, !tbaa !11
  %33 = call float @llvm.fmuladd.f32(float %31, float %32, float %30)
  %34 = load float, ptr %20, align 4, !tbaa !11
  %35 = load float, ptr %21, align 8, !tbaa !11
  %36 = call float @llvm.fmuladd.f32(float %34, float %35, float %33)
  %37 = load float, ptr %22, align 8, !tbaa !11
  %38 = load float, ptr %23, align 4, !tbaa !11
  %39 = call float @llvm.fmuladd.f32(float %37, float %38, float %36)
  %40 = load float, ptr %24, align 4, !tbaa !11
  %41 = load float, ptr %25, align 8, !tbaa !11
  %42 = call float @llvm.fmuladd.f32(float %40, float %41, float %39)
  store float %42, ptr %2, align 4, !tbaa !11
  store float %32, ptr %15, align 8, !tbaa !11
  store float %28, ptr %14, align 4, !tbaa !11
  store float %38, ptr %17, align 8, !tbaa !11
  store float %42, ptr %16, align 4, !tbaa !11
  call void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176) %18, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  br label %26, !llvm.loop !13
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #4

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = !{!12, !12, i64 0}
!12 = !{!"float", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,LoopRotatePass,MemCpyOptPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass