; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Universal (MD5Final)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._MD5_CTX = type { i64, i64, [4 x i32], [64 x i8], i64 }

@Md5HashPadding = external dso_local constant <{ i8, [127 x i8] }>, align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare ptr @CopyMem(ptr noundef, ptr noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @MD5UpdateBlock(ptr noundef, ptr noundef, i64 noundef) #2

declare ptr @ZeroMem(ptr noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i64 @MD5Final(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i64, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct._MD5_CTX, ptr %8, i32 0, i32 0
  %10 = load i64, ptr %9, align 8, !tbaa !9
  %11 = icmp eq i64 %10, -9223372036854775788
  br i1 %11, label %12, label %20

12:                                               ; preds = %2
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct._MD5_CTX, ptr %14, i32 0, i32 2
  %16 = getelementptr inbounds [4 x i32], ptr %15, i64 0, i64 0
  %17 = call ptr @CopyMem(ptr noundef %13, ptr noundef %16, i64 noundef 16)
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = call ptr @ZeroMem(ptr noundef %18, i64 noundef 104)
  store i64 0, ptr %3, align 8
  store i32 1, ptr %7, align 4
  br label %64

20:                                               ; preds = %2
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct._MD5_CTX, ptr %21, i32 0, i32 0
  %23 = load i64, ptr %22, align 8, !tbaa !9
  %24 = icmp slt i64 %23, 0
  br i1 %24, label %25, label %29

25:                                               ; preds = %20
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct._MD5_CTX, ptr %26, i32 0, i32 0
  %28 = load i64, ptr %27, align 8, !tbaa !9
  store i64 %28, ptr %3, align 8
  store i32 1, ptr %7, align 4
  br label %64

29:                                               ; preds = %20
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct._MD5_CTX, ptr %30, i32 0, i32 4
  %32 = load i64, ptr %31, align 8, !tbaa !12
  %33 = icmp uge i64 %32, 56
  %34 = zext i1 %33 to i64
  %35 = select i1 %33, i32 120, i32 56
  %36 = sext i32 %35 to i64
  store i64 %36, ptr %6, align 8, !tbaa !13
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct._MD5_CTX, ptr %37, i32 0, i32 4
  %39 = load i64, ptr %38, align 8, !tbaa !12
  %40 = load i64, ptr %6, align 8, !tbaa !13
  %41 = sub i64 %40, %39
  store i64 %41, ptr %6, align 8, !tbaa !13
  %42 = load ptr, ptr %4, align 8, !tbaa !5
  %43 = load i64, ptr %6, align 8, !tbaa !13
  call void @MD5UpdateBlock(ptr noundef %42, ptr noundef @Md5HashPadding, i64 noundef %43)
  %44 = load ptr, ptr %4, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct._MD5_CTX, ptr %44, i32 0, i32 1
  %46 = load i64, ptr %45, align 8, !tbaa !14
  %47 = call i64 @LShiftU64(i64 noundef %46, i64 noundef 3)
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct._MD5_CTX, ptr %48, i32 0, i32 1
  store i64 %47, ptr %49, align 8, !tbaa !14
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct._MD5_CTX, ptr %51, i32 0, i32 1
  call void @MD5UpdateBlock(ptr noundef %50, ptr noundef %52, i64 noundef 8)
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct._MD5_CTX, ptr %53, i32 0, i32 3
  %55 = getelementptr inbounds [64 x i8], ptr %54, i64 0, i64 0
  %56 = call ptr @ZeroMem(ptr noundef %55, i64 noundef 64)
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct._MD5_CTX, ptr %57, i32 0, i32 1
  store i64 0, ptr %58, align 8, !tbaa !14
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct._MD5_CTX, ptr %59, i32 0, i32 0
  store i64 -9223372036854775788, ptr %60, align 8, !tbaa !9
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  %62 = load ptr, ptr %5, align 8, !tbaa !5
  %63 = call i64 @MD5Final(ptr noundef %61, ptr noundef %62)
  store i64 %63, ptr %3, align 8
  store i32 1, ptr %7, align 4
  br label %64

64:                                               ; preds = %29, %25, %12
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  %65 = load i64, ptr %3, align 8
  ret i64 %65
}

declare i64 @LShiftU64(i64 noundef, i64 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_MD5_CTX", !11, i64 0, !11, i64 8, !7, i64 16, !7, i64 32, !11, i64 96}
!11 = !{!"long long", !7, i64 0}
!12 = !{!10, !11, i64 96}
!13 = !{!11, !11, i64 0}
!14 = !{!10, !11, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Md5HashPadding = external dso_local constant <{ i8, [127 x i8] }>, align 16

declare ptr @CopyMem(ptr noundef, ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @MD5UpdateBlock(ptr noundef, ptr noundef, i64 noundef) local_unnamed_addr #1

declare ptr @ZeroMem(ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i64 -9223372036854775787, -9223372036854775788) i64 @MD5Final(ptr noundef %0, ptr noundef %1) local_unnamed_addr #1 {
  %3 = load i64, ptr %0, align 8, !tbaa !5
  %4 = icmp eq i64 %3, -9223372036854775788
  br i1 %4, label %tailrecurse._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %5 = icmp slt i64 %3, 0
  br i1 %5, label %.loopexit, label %tailrecurse

tailrecurse._crit_edge:                           ; preds = %tailrecurse, %2
  %6 = getelementptr inbounds i8, ptr %0, i64 16
  %7 = tail call ptr @CopyMem(ptr noundef %1, ptr noundef nonnull %6, i64 noundef 16) #2
  %8 = tail call ptr @ZeroMem(ptr noundef nonnull %0, i64 noundef 104) #2
  br label %.loopexit

tailrecurse:                                      ; preds = %.lr.ph
  %9 = getelementptr inbounds i8, ptr %0, i64 32
  %10 = getelementptr inbounds i8, ptr %0, i64 8
  %11 = getelementptr inbounds i8, ptr %0, i64 96
  %12 = load i64, ptr %11, align 8, !tbaa !10
  %.inv = icmp ult i64 %12, 56
  %13 = select i1 %.inv, i64 56, i64 120
  %14 = sub i64 %13, %12
  tail call void @MD5UpdateBlock(ptr noundef nonnull %0, ptr noundef nonnull @Md5HashPadding, i64 noundef %14)
  %15 = load i64, ptr %10, align 8, !tbaa !11
  %16 = tail call i64 @LShiftU64(i64 noundef %15, i64 noundef 3) #2
  store i64 %16, ptr %10, align 8, !tbaa !11
  tail call void @MD5UpdateBlock(ptr noundef nonnull %0, ptr noundef nonnull %10, i64 noundef 8)
  %17 = tail call ptr @ZeroMem(ptr noundef nonnull %9, i64 noundef 64) #2
  store i64 0, ptr %10, align 8, !tbaa !11
  store i64 -9223372036854775788, ptr %0, align 8, !tbaa !5
  br label %tailrecurse._crit_edge

.loopexit:                                        ; preds = %.lr.ph, %tailrecurse._crit_edge
  %.0 = phi i64 [ 0, %tailrecurse._crit_edge ], [ %3, %.lr.ph ]
  ret i64 %.0
}

declare i64 @LShiftU64(i64 noundef, i64 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_MD5_CTX", !7, i64 0, !7, i64 8, !8, i64 16, !8, i64 32, !7, i64 96}
!7 = !{!"long long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 96}
!11 = !{!6, !7, i64 8}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass