; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_signal_ports)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_in.25" = type { %"class.sc_core::sc_port.26", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.26" = type { %"class.sc_core::sc_port_b.27" }
%"class.sc_core::sc_port_b.27" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.28" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.28" = type { %"struct.std::_Vector_base.29" }
%"struct.std::_Vector_base.29" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_logic> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.sc_core::sc_trace_params" = type { ptr, %"class.std::__cxx11::basic_string" }

@_ZTIN7sc_core12sc_interfaceE = external constant ptr
@_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE = external dso_local constant { ptr, ptr, i32, i32, ptr, i64 }, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core5sc_inIN5sc_dt8sc_logicEE18end_of_elaborationEv(ptr noundef nonnull align 8 dereferenceable(184) %0) unnamed_addr #3 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8
  %7 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %6, i32 0, i32 1
  %8 = load ptr, ptr %7, align 8, !tbaa !9
  %9 = icmp ne ptr %8, null
  br i1 %9, label %10, label %50

10:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  store i32 0, ptr %3, align 4, !tbaa !30
  br label %11

11:                                               ; preds = %46, %10
  %12 = load i32, ptr %3, align 4, !tbaa !30
  %13 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %6, i32 0, i32 1
  %14 = load ptr, ptr %13, align 8, !tbaa !9
  %15 = call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %14) #5
  %16 = trunc i64 %15 to i32
  %17 = icmp slt i32 %12, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %11
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  br label %49

19:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #5
  %20 = getelementptr inbounds %"class.sc_core::sc_in.25", ptr %6, i32 0, i32 1
  %21 = load ptr, ptr %20, align 8, !tbaa !9
  %22 = load i32, ptr %3, align 4, !tbaa !30
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #5
  %25 = load ptr, ptr %24, align 8, !tbaa !5
  store ptr %25, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  %26 = load ptr, ptr %6, align 8, !tbaa !32
  %27 = getelementptr inbounds ptr, ptr %26, i64 15
  %28 = load ptr, ptr %27, align 8
  %29 = call noundef ptr %28(ptr noundef nonnull align 8 dereferenceable(152) %6)
  %30 = icmp eq ptr %29, null
  br i1 %30, label %33, label %31

31:                                               ; preds = %19
  %32 = call ptr @__dynamic_cast(ptr %29, ptr @_ZTIN7sc_core12sc_interfaceE, ptr @_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE, i64 -1) #5
  br label %34

33:                                               ; preds = %19
  br label %34

34:                                               ; preds = %33, %31
  %35 = phi ptr [ %32, %31 ], [ null, %33 ]
  store ptr %35, ptr %5, align 8, !tbaa !5
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = getelementptr inbounds %"struct.sc_core::sc_trace_params", ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !34
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = load ptr, ptr %39, align 8, !tbaa !32
  %41 = getelementptr inbounds ptr, ptr %40, i64 7
  %42 = load ptr, ptr %41, align 8
  %43 = call noundef nonnull align 4 dereferenceable(4) ptr %42(ptr noundef nonnull align 8 dereferenceable(8) %39)
  %44 = load ptr, ptr %4, align 8, !tbaa !5
  %45 = getelementptr inbounds %"struct.sc_core::sc_trace_params", ptr %44, i32 0, i32 1
  call void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef %38, ptr noundef nonnull align 4 dereferenceable(4) %43, ptr noundef nonnull align 8 dereferenceable(32) %45)
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #5
  br label %46

46:                                               ; preds = %34
  %47 = load i32, ptr %3, align 4, !tbaa !30
  %48 = add nsw i32 %47, 1
  store i32 %48, ptr %3, align 4, !tbaa !30
  br label %11, !llvm.loop !36

49:                                               ; preds = %18
  call void @_ZNK7sc_core5sc_inIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(184) %6)
  br label %50

50:                                               ; preds = %49, %1
  ret void
}

declare void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32)) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNK7sc_core5sc_inIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(184)) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind willreturn memory(read) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 152}
!10 = !{!"_ZTSN7sc_core5sc_inIN5sc_dt8sc_logicEEE", !11, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!11 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !12, i64 0}
!12 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEEEE", !13, i64 0, !6, i64 120, !26, i64 128}
!13 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !6, i64 112}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !6, i64 96, !6, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!31, !31, i64 0}
!31 = !{!"int", !7, i64 0}
!32 = !{!33, !33, i64 0}
!33 = !{!"vtable pointer", !8, i64 0}
!34 = !{!35, !6, i64 0}
!35 = !{!"_ZTSN7sc_core15sc_trace_paramsE", !6, i64 0, !23, i64 8}
!36 = distinct !{!36, !37}
!37 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN7sc_core12sc_interfaceE = external constant ptr
@_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE = external dso_local constant { ptr, ptr, i32, i32, ptr, i64 }, align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nofree nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core5sc_inIN5sc_dt8sc_logicEE18end_of_elaborationEv(ptr noundef nonnull align 8 dereferenceable(184) %0) unnamed_addr #2 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 152
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %26, label %.preheader

.preheader:                                       ; preds = %1
  %4 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  %5 = trunc i64 %4 to i32
  %6 = icmp sgt i32 %5, 0
  br i1 %6, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  tail call void @_ZNK7sc_core5sc_inIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(184) %0)
  br label %26

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.preheader ]
  %7 = load ptr, ptr %2, align 8, !tbaa !5
  %8 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %indvars.iv) #5
  %9 = load ptr, ptr %8, align 8, !tbaa !29
  %10 = load ptr, ptr %0, align 8, !tbaa !30
  %11 = getelementptr inbounds i8, ptr %10, i64 120
  %12 = load ptr, ptr %11, align 8
  %13 = tail call noundef ptr %12(ptr noundef nonnull align 8 dereferenceable(152) %0)
  %14 = icmp ne ptr %13, null
  tail call void @llvm.assume(i1 %14)
  %15 = tail call ptr @__dynamic_cast(ptr nonnull %13, ptr nonnull @_ZTIN7sc_core12sc_interfaceE, ptr nonnull @_ZTIN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEE, i64 -1) #5
  %16 = load ptr, ptr %9, align 8, !tbaa !32
  %17 = load ptr, ptr %15, align 8, !tbaa !30
  %18 = getelementptr inbounds i8, ptr %17, i64 56
  %19 = load ptr, ptr %18, align 8
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr %19(ptr noundef nonnull align 8 dereferenceable(8) %15)
  %21 = getelementptr inbounds i8, ptr %9, i64 8
  tail call void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef %16, ptr noundef nonnull align 4 dereferenceable(4) %20, ptr noundef nonnull align 8 dereferenceable(32) %21)
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %22 = load ptr, ptr %2, align 8, !tbaa !5
  %23 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core15sc_trace_paramsESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %22) #5
  %sext = shl i64 %23, 32
  %24 = ashr exact i64 %sext, 32
  %25 = icmp slt i64 %indvars.iv.next, %24
  br i1 %25, label %.lr.ph, label %._crit_edge, !llvm.loop !34

26:                                               ; preds = %._crit_edge, %1
  ret void
}

declare void @_ZN7sc_core8sc_traceEPNS_13sc_trace_fileERKN5sc_dt8sc_logicERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE(ptr noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNK7sc_core5sc_inIN5sc_dt8sc_logicEE13remove_tracesEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
declare void @llvm.assume(i1 noundef) #4

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nofree nounwind willreturn memory(read) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 152}
!6 = !{!"_ZTSN7sc_core5sc_inIN5sc_dt8sc_logicEEE", !7, i64 0, !11, i64 152, !11, i64 160, !11, i64 168, !11, i64 176}
!7 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !8, i64 0}
!8 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIN5sc_dt8sc_logicEEEEE", !9, i64 0, !11, i64 120, !25, i64 128}
!9 = !{!"_ZTSN7sc_core12sc_port_baseE", !10, i64 0, !11, i64 112}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !12, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!24 = !{!"long", !12, i64 0}
!25 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!29 = !{!11, !11, i64 0}
!30 = !{!31, !31, i64 0}
!31 = !{!"vtable pointer", !13, i64 0}
!32 = !{!33, !11, i64 0}
!33 = !{!"_ZTSN7sc_core15sc_trace_paramsE", !11, i64 0, !22, i64 8}
!34 = distinct !{!34, !35}
!35 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass