; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_simcontext)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core12SC_ZERO_TIMEE = external global %"class.sc_core::sc_time", align 8
@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1
@_ZN7sc_core31SC_ID_SIMULATION_TIME_OVERFLOW_E = external constant [0 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [1 x i8], align 1
@_ZN7sc_core31SC_ID_NEGATIVE_SIMULATION_TIME_E = external constant [0 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNK7sc_core14sc_event_timed11notify_timeEv(ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344)) #3 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #4

declare void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160)) #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext10initializeEb(ptr noundef nonnull align 8 dereferenceable(344), i1 noundef zeroext) #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext8simulateERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr noundef nonnull align 8 dereferenceable(8) %1) #3 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %"class.sc_core::sc_time", align 8
  %6 = alloca i32, align 4
  %7 = alloca %"class.sc_core::sc_time", align 8
  %8 = alloca %"class.sc_core::sc_time", align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %11 = load ptr, ptr %3, align 8
  call void @_ZN7sc_core13sc_simcontext10initializeEb(ptr noundef nonnull align 8 dereferenceable(344) %11, i1 noundef zeroext true)
  %12 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %11)
  %13 = icmp ne i32 %12, 0
  br i1 %13, label %14, label %15

14:                                               ; preds = %2
  br label %146

15:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #6
  %16 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core11sc_max_timeEv()
  %17 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  call void @_ZN7sc_coremiERKNS_7sc_timeES2_(ptr dead_on_unwind writable sret(%"class.sc_core::sc_time") align 8 %5, ptr noundef nonnull align 8 dereferenceable(8) %16, ptr noundef nonnull align 8 dereferenceable(8) %17)
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %18, ptr noundef nonnull align 8 dereferenceable(8) %5)
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core31SC_ID_SIMULATION_TIME_OVERFLOW_E, ptr noundef @.str.8, ptr noundef @.str.7, i32 noundef 903)
  store i32 1, ptr %6, align 4
  br label %144

21:                                               ; preds = %15
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %22, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  br i1 %23, label %24, label %25

24:                                               ; preds = %21
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core31SC_ID_NEGATIVE_SIMULATION_TIME_E, ptr noundef @.str.8, ptr noundef @.str.7, i32 noundef 908)
  br label %25

25:                                               ; preds = %24, %21
  br label %26

26:                                               ; preds = %25
  %27 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 33
  store i8 1, ptr %27, align 8, !tbaa !9
  %28 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 28
  store i8 0, ptr %28, align 1, !tbaa !35
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #6
  %29 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind writable sret(%"class.sc_core::sc_time") align 8 %7, ptr noundef nonnull align 8 dereferenceable(8) %29, ptr noundef nonnull align 8 dereferenceable(8) %30)
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #6
  call void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %8)
  %31 = load ptr, ptr %4, align 8, !tbaa !5
  %32 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %31, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  br i1 %32, label %33, label %51

33:                                               ; preds = %26
  %34 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 33
  store i8 1, ptr %34, align 8, !tbaa !9
  call void @_ZN7sc_core13sc_simcontext6crunchEb(ptr noundef nonnull align 8 dereferenceable(344) %11, i1 noundef zeroext true)
  %35 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 32
  %36 = load ptr, ptr %35, align 8, !tbaa !36
  %37 = icmp ne ptr %36, null
  br i1 %37, label %38, label %40

38:                                               ; preds = %33
  %39 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 33
  store i8 0, ptr %39, align 8, !tbaa !9
  store i32 1, ptr %6, align 4
  br label %143

40:                                               ; preds = %33
  %41 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 18
  %42 = load i8, ptr %41, align 8, !tbaa !37, !range !38, !noundef !39
  %43 = trunc i8 %42 to i1
  br i1 %43, label %44, label %45

44:                                               ; preds = %40
  call void @_ZN7sc_core13sc_simcontext11trace_cycleEb(ptr noundef nonnull align 8 dereferenceable(344) %11, i1 noundef zeroext false)
  br label %45

45:                                               ; preds = %44, %40
  %46 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 27
  %47 = load i8, ptr %46, align 8, !tbaa !40, !range !38, !noundef !39
  %48 = trunc i8 %47 to i1
  br i1 %48, label %49, label %50

49:                                               ; preds = %45
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %11)
  store i32 1, ptr %6, align 4
  br label %143

50:                                               ; preds = %45
  br label %140

51:                                               ; preds = %26
  br label %52

52:                                               ; preds = %125, %51
  call void @_ZN7sc_core13sc_simcontext6crunchEb(ptr noundef nonnull align 8 dereferenceable(344) %11, i1 noundef zeroext false)
  %53 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 32
  %54 = load ptr, ptr %53, align 8, !tbaa !36
  %55 = icmp ne ptr %54, null
  br i1 %55, label %56, label %58

56:                                               ; preds = %52
  %57 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 33
  store i8 0, ptr %57, align 8, !tbaa !9
  store i32 1, ptr %6, align 4
  br label %143

58:                                               ; preds = %52
  %59 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 18
  %60 = load i8, ptr %59, align 8, !tbaa !37, !range !38, !noundef !39
  %61 = trunc i8 %60 to i1
  br i1 %61, label %62, label %63

62:                                               ; preds = %58
  call void @_ZN7sc_core13sc_simcontext11trace_cycleEb(ptr noundef nonnull align 8 dereferenceable(344) %11, i1 noundef zeroext false)
  br label %63

63:                                               ; preds = %62, %58
  %64 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 27
  %65 = load i8, ptr %64, align 8, !tbaa !40, !range !38, !noundef !39
  %66 = trunc i8 %65 to i1
  br i1 %66, label %67, label %68

67:                                               ; preds = %63
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %11)
  store i32 1, ptr %6, align 4
  br label %143

68:                                               ; preds = %63
  %69 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 28
  %70 = load i8, ptr %69, align 1, !tbaa !35, !range !38, !noundef !39
  %71 = trunc i8 %70 to i1
  br i1 %71, label %72, label %73

72:                                               ; preds = %68
  br label %140

73:                                               ; preds = %68
  %74 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  %75 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %74)
  br label %76

76:                                               ; preds = %120, %73
  %77 = call noundef zeroext i1 @_ZNK7sc_core13sc_simcontext9next_timeERNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344) %11, ptr noundef nonnull align 8 dereferenceable(8) %8)
  br i1 %77, label %78, label %80

78:                                               ; preds = %76
  %79 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %7)
  br i1 %79, label %80, label %81

80:                                               ; preds = %78, %76
  br label %128

81:                                               ; preds = %78
  %82 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  %83 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %82)
  br i1 %83, label %84, label %90

84:                                               ; preds = %81
  %85 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  %86 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %85, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %87 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 25
  %88 = load i64, ptr %87, align 8, !tbaa !41
  %89 = add i64 %88, 1
  store i64 %89, ptr %87, align 8, !tbaa !41
  br label %90

90:                                               ; preds = %84, %81
  br label %91

91:                                               ; preds = %117, %90
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #6
  %92 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 16
  %93 = load ptr, ptr %92, align 8, !tbaa !42
  %94 = call noundef ptr @_ZN7sc_core6sc_ppqIPNS_14sc_event_timedEE11extract_topEv(ptr noundef nonnull align 8 dereferenceable(24) %93)
  store ptr %94, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #6
  %95 = load ptr, ptr %9, align 8, !tbaa !5
  %96 = call noundef ptr @_ZNK7sc_core14sc_event_timed5eventEv(ptr noundef nonnull align 8 dereferenceable(16) %95)
  store ptr %96, ptr %10, align 8, !tbaa !5
  %97 = load ptr, ptr %9, align 8, !tbaa !5
  %98 = icmp eq ptr %97, null
  br i1 %98, label %100, label %99

99:                                               ; preds = %91
  call void @_ZN7sc_core14sc_event_timedD2Ev(ptr noundef nonnull align 8 dereferenceable(16) %97) #6
  call void @_ZN7sc_core14sc_event_timeddlEPvm(ptr noundef %97, i64 noundef 16) #6
  br label %100

100:                                              ; preds = %99, %91
  %101 = load ptr, ptr %10, align 8, !tbaa !5
  %102 = icmp ne ptr %101, null
  br i1 %102, label %103, label %105

103:                                              ; preds = %100
  %104 = load ptr, ptr %10, align 8, !tbaa !5
  call void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160) %104)
  br label %105

105:                                              ; preds = %103, %100
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #6
  br label %106

106:                                              ; preds = %105
  %107 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 16
  %108 = load ptr, ptr %107, align 8, !tbaa !42
  %109 = call noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %108)
  %110 = icmp ne i32 %109, 0
  br i1 %110, label %111, label %117

111:                                              ; preds = %106
  %112 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 16
  %113 = load ptr, ptr %112, align 8, !tbaa !42
  %114 = call noundef ptr @_ZNK7sc_core6sc_ppqIPNS_14sc_event_timedEE3topEv(ptr noundef nonnull align 8 dereferenceable(24) %113)
  %115 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNK7sc_core14sc_event_timed11notify_timeEv(ptr noundef nonnull align 8 dereferenceable(16) %114)
  %116 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %115, ptr noundef nonnull align 8 dereferenceable(8) %8)
  br label %117

117:                                              ; preds = %111, %106
  %118 = phi i1 [ false, %106 ], [ %116, %111 ]
  br i1 %118, label %91, label %119, !llvm.loop !43

119:                                              ; preds = %117
  br label %120

120:                                              ; preds = %119
  %121 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 19
  %122 = load ptr, ptr %121, align 8, !tbaa !45
  %123 = call noundef zeroext i1 @_ZNK7sc_core11sc_runnable8is_emptyEv(ptr noundef nonnull align 8 dereferenceable(48) %122)
  br i1 %123, label %76, label %124, !llvm.loop !46

124:                                              ; preds = %120
  br label %125

125:                                              ; preds = %124
  %126 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %7)
  br i1 %126, label %52, label %127, !llvm.loop !47

127:                                              ; preds = %125
  br label %128

128:                                              ; preds = %127, %80
  %129 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  %130 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %129)
  br i1 %130, label %131, label %139

131:                                              ; preds = %128
  %132 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeleERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %7)
  br i1 %132, label %133, label %139

133:                                              ; preds = %131
  %134 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 22
  %135 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %134, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %136 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 25
  %137 = load i64, ptr %136, align 8, !tbaa !41
  %138 = add i64 %137, 1
  store i64 %138, ptr %136, align 8, !tbaa !41
  br label %139

139:                                              ; preds = %133, %131, %128
  br label %140

140:                                              ; preds = %139, %72, %50
  %141 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 31
  store i32 1, ptr %141, align 4, !tbaa !48
  %142 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 33
  store i8 0, ptr %142, align 8, !tbaa !9
  store i32 0, ptr %6, align 4
  br label %143

143:                                              ; preds = %140, %67, %56, %49, %38
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #6
  br label %144

144:                                              ; preds = %143, %20
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #6
  %145 = load i32, ptr %6, align 4
  switch i32 %145, label %147 [
    i32 0, label %146
    i32 1, label %146
  ]

146:                                              ; preds = %144, %144, %14
  ret void

147:                                              ; preds = %144
  unreachable
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coremiERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #5

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core11sc_max_timeEv() #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext6crunchEb(ptr noundef nonnull align 8 dereferenceable(344), i1 noundef zeroext) #5 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext11trace_cycleEb(ptr noundef nonnull align 8 dereferenceable(344), i1 noundef zeroext) #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core13sc_simcontext9next_timeERNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef nonnull align 8 dereferenceable(8)) #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core6sc_ppqIPNS_14sc_event_timedEE11extract_topEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core14sc_event_timed5eventEv(ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core14sc_event_timedD2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core14sc_event_timeddlEPvm(ptr noundef, i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZNK7sc_core6sc_ppqIPNS_14sc_event_timedEE3topEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core11sc_runnable8is_emptyEv(ptr noundef nonnull align 8 dereferenceable(48)) #5 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeleERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 312}
!10 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !11, i64 64, !6, i64 80, !13, i64 88, !14, i64 92, !15, i64 96, !19, i64 120, !23, i64 144, !19, i64 168, !6, i64 192, !27, i64 200, !13, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !31, i64 256, !31, i64 264, !6, i64 272, !32, i64 280, !32, i64 288, !13, i64 296, !13, i64 297, !13, i64 298, !13, i64 299, !33, i64 300, !6, i64 304, !13, i64 312, !13, i64 313, !34, i64 316, !13, i64 320, !6, i64 328, !6, i64 336}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !12, i64 8}
!12 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core7sc_timeE", !32, i64 0}
!32 = !{!"long long", !7, i64 0}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!35 = !{!10, !13, i64 297}
!36 = !{!10, !6, i64 304}
!37 = !{!10, !13, i64 224}
!38 = !{i8 0, i8 2}
!39 = !{}
!40 = !{!10, !13, i64 296}
!41 = !{!10, !32, i64 280}
!42 = !{!10, !6, i64 192}
!43 = distinct !{!43, !44}
!44 = !{!"llvm.loop.mustprogress"}
!45 = !{!10, !6, i64 232}
!46 = distinct !{!46, !44}
!47 = distinct !{!47, !44}
!48 = !{!10, !33, i64 300}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }

@_ZN7sc_core12SC_ZERO_TIMEE = external global %"class.sc_core::sc_time", align 8
@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1
@_ZN7sc_core31SC_ID_SIMULATION_TIME_OVERFLOW_E = external constant [0 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [1 x i8], align 1
@_ZN7sc_core31SC_ID_NEGATIVE_SIMULATION_TIME_E = external constant [0 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNK7sc_core14sc_event_timed11notify_timeEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #3 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #4

declare void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160)) local_unnamed_addr #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext10initializeEb(ptr noundef nonnull align 8 dereferenceable(344), i1 noundef zeroext) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext8simulateERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr noundef nonnull align 8 dereferenceable(8) %1) local_unnamed_addr #3 align 2 {
  %3 = alloca %"class.sc_core::sc_time", align 8
  %4 = alloca %"class.sc_core::sc_time", align 8
  %5 = alloca %"class.sc_core::sc_time", align 8
  tail call void @_ZN7sc_core13sc_simcontext10initializeEb(ptr noundef nonnull align 8 dereferenceable(344) %0, i1 noundef zeroext true)
  %6 = tail call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  %.not = icmp eq i32 %6, 0
  br i1 %.not, label %7, label %92

7:                                                ; preds = %2
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #6
  %8 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core11sc_max_timeEv()
  %9 = getelementptr inbounds i8, ptr %0, i64 256
  call void @_ZN7sc_coremiERKNS_7sc_timeES2_(ptr dead_on_unwind nonnull writable sret(%"class.sc_core::sc_time") align 8 %3, ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %9)
  %10 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) %3)
  br i1 %10, label %11, label %12

11:                                               ; preds = %7
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core31SC_ID_SIMULATION_TIME_OVERFLOW_E, ptr noundef nonnull @.str.8, ptr noundef nonnull @.str.7, i32 noundef 903)
  br label %91

12:                                               ; preds = %7
  %13 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  br i1 %13, label %14, label %15

14:                                               ; preds = %12
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core31SC_ID_NEGATIVE_SIMULATION_TIME_E, ptr noundef nonnull @.str.8, ptr noundef nonnull @.str.7, i32 noundef 908)
  br label %15

15:                                               ; preds = %12, %14
  %16 = getelementptr inbounds i8, ptr %0, i64 312
  store i8 1, ptr %16, align 8, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %0, i64 297
  store i8 0, ptr %17, align 1, !tbaa !34
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #6
  call void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind nonnull writable sret(%"class.sc_core::sc_time") align 8 %4, ptr noundef nonnull align 8 dereferenceable(8) %9, ptr noundef nonnull align 8 dereferenceable(8) %1)
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #6
  call void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %5)
  %18 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  br i1 %18, label %25, label %.preheader

.preheader:                                       ; preds = %15
  %19 = getelementptr inbounds i8, ptr %0, i64 304
  %20 = getelementptr inbounds i8, ptr %0, i64 224
  %21 = getelementptr inbounds i8, ptr %0, i64 296
  %22 = getelementptr inbounds i8, ptr %0, i64 280
  %23 = getelementptr inbounds i8, ptr %0, i64 192
  %24 = getelementptr inbounds i8, ptr %0, i64 232
  br label %39

25:                                               ; preds = %15
  store i8 1, ptr %16, align 8, !tbaa !5
  call void @_ZN7sc_core13sc_simcontext6crunchEb(ptr noundef nonnull align 8 dereferenceable(344) %0, i1 noundef zeroext true)
  %26 = getelementptr inbounds i8, ptr %0, i64 304
  %27 = load ptr, ptr %26, align 8, !tbaa !35
  %.not12 = icmp eq ptr %27, null
  br i1 %.not12, label %29, label %28

28:                                               ; preds = %25
  store i8 0, ptr %16, align 8, !tbaa !5
  br label %90

29:                                               ; preds = %25
  %30 = getelementptr inbounds i8, ptr %0, i64 224
  %31 = load i8, ptr %30, align 8, !tbaa !36, !range !37, !noundef !38
  %32 = trunc nuw i8 %31 to i1
  br i1 %32, label %33, label %34

33:                                               ; preds = %29
  call void @_ZN7sc_core13sc_simcontext11trace_cycleEb(ptr noundef nonnull align 8 dereferenceable(344) %0, i1 noundef zeroext false)
  br label %34

34:                                               ; preds = %33, %29
  %35 = getelementptr inbounds i8, ptr %0, i64 296
  %36 = load i8, ptr %35, align 8, !tbaa !39, !range !37, !noundef !38
  %37 = trunc nuw i8 %36 to i1
  br i1 %37, label %38, label %.loopexit13

38:                                               ; preds = %34
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  br label %90

39:                                               ; preds = %.preheader, %80
  call void @_ZN7sc_core13sc_simcontext6crunchEb(ptr noundef nonnull align 8 dereferenceable(344) %0, i1 noundef zeroext false)
  %40 = load ptr, ptr %19, align 8, !tbaa !35
  %.not9 = icmp eq ptr %40, null
  br i1 %.not9, label %42, label %41

41:                                               ; preds = %39
  store i8 0, ptr %16, align 8, !tbaa !5
  br label %90

42:                                               ; preds = %39
  %43 = load i8, ptr %20, align 8, !tbaa !36, !range !37, !noundef !38
  %44 = trunc nuw i8 %43 to i1
  br i1 %44, label %45, label %46

45:                                               ; preds = %42
  call void @_ZN7sc_core13sc_simcontext11trace_cycleEb(ptr noundef nonnull align 8 dereferenceable(344) %0, i1 noundef zeroext false)
  br label %46

46:                                               ; preds = %45, %42
  %47 = load i8, ptr %21, align 8, !tbaa !39, !range !37, !noundef !38
  %48 = trunc nuw i8 %47 to i1
  br i1 %48, label %49, label %50

49:                                               ; preds = %46
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  br label %90

50:                                               ; preds = %46
  %51 = load i8, ptr %17, align 1, !tbaa !34, !range !37, !noundef !38
  %52 = trunc nuw i8 %51 to i1
  br i1 %52, label %.loopexit13, label %53

53:                                               ; preds = %50
  %54 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %9)
  br label %55

55:                                               ; preds = %.critedge, %53
  %56 = call noundef zeroext i1 @_ZNK7sc_core13sc_simcontext9next_timeERNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr noundef nonnull align 8 dereferenceable(8) %5)
  br i1 %56, label %57, label %.loopexit

57:                                               ; preds = %55
  %58 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %4)
  br i1 %58, label %.loopexit, label %59

59:                                               ; preds = %57
  %60 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %9)
  br i1 %60, label %61, label %.preheader18

61:                                               ; preds = %59
  %62 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %9, ptr noundef nonnull align 8 dereferenceable(8) %5)
  %63 = load i64, ptr %22, align 8, !tbaa !40
  %64 = add i64 %63, 1
  store i64 %64, ptr %22, align 8, !tbaa !40
  br label %.preheader18

.preheader18:                                     ; preds = %61, %59
  br label %65

65:                                               ; preds = %.preheader18, %73
  %66 = load ptr, ptr %23, align 8, !tbaa !41
  %67 = call noundef ptr @_ZN7sc_core6sc_ppqIPNS_14sc_event_timedEE11extract_topEv(ptr noundef nonnull align 8 dereferenceable(24) %66)
  %68 = call noundef ptr @_ZNK7sc_core14sc_event_timed5eventEv(ptr noundef nonnull align 8 dereferenceable(16) %67)
  call void @_ZN7sc_core14sc_event_timedD2Ev(ptr noundef nonnull align 8 dereferenceable(16) %67) #6
  call void @_ZN7sc_core14sc_event_timeddlEPvm(ptr noundef nonnull %67, i64 noundef 16) #6
  %.not10 = icmp eq ptr %68, null
  br i1 %.not10, label %70, label %69

69:                                               ; preds = %65
  call void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160) %68)
  br label %70

70:                                               ; preds = %69, %65
  %71 = load ptr, ptr %23, align 8, !tbaa !41
  %72 = call noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %71)
  %.not11 = icmp eq i32 %72, 0
  br i1 %.not11, label %.critedge, label %73

73:                                               ; preds = %70
  %74 = load ptr, ptr %23, align 8, !tbaa !41
  %75 = call noundef ptr @_ZNK7sc_core6sc_ppqIPNS_14sc_event_timedEE3topEv(ptr noundef nonnull align 8 dereferenceable(24) %74)
  %76 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNK7sc_core14sc_event_timed11notify_timeEv(ptr noundef nonnull align 8 dereferenceable(16) %75)
  %77 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %76, ptr noundef nonnull align 8 dereferenceable(8) %5)
  br i1 %77, label %65, label %.critedge, !llvm.loop !42

.critedge:                                        ; preds = %70, %73
  %78 = load ptr, ptr %24, align 8, !tbaa !44
  %79 = call noundef zeroext i1 @_ZNK7sc_core11sc_runnable8is_emptyEv(ptr noundef nonnull align 8 dereferenceable(48) %78)
  br i1 %79, label %55, label %80, !llvm.loop !45

80:                                               ; preds = %.critedge
  %81 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %4)
  br i1 %81, label %39, label %.loopexit, !llvm.loop !46

.loopexit:                                        ; preds = %80, %55, %57
  %82 = call noundef zeroext i1 @_ZNK7sc_core7sc_timegtERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %9)
  br i1 %82, label %83, label %.loopexit13

83:                                               ; preds = %.loopexit
  %84 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeleERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %4)
  br i1 %84, label %85, label %.loopexit13

85:                                               ; preds = %83
  %86 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core7sc_timeaSERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %9, ptr noundef nonnull align 8 dereferenceable(8) %5)
  %87 = load i64, ptr %22, align 8, !tbaa !40
  %88 = add i64 %87, 1
  store i64 %88, ptr %22, align 8, !tbaa !40
  br label %.loopexit13

.loopexit13:                                      ; preds = %50, %.loopexit, %83, %85, %34
  %89 = getelementptr inbounds i8, ptr %0, i64 300
  store i32 1, ptr %89, align 4, !tbaa !47
  store i8 0, ptr %16, align 8, !tbaa !5
  br label %90

90:                                               ; preds = %.loopexit13, %49, %41, %38, %28
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #6
  br label %91

91:                                               ; preds = %90, %11
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #6
  br label %92

92:                                               ; preds = %2, %91
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coremiERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core11sc_max_timeEv() local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core7sc_timeC2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeeqERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext6crunchEb(ptr noundef nonnull align 8 dereferenceable(344), i1 noundef zeroext) local_unnamed_addr #5 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext11trace_cycleEb(ptr noundef nonnull align 8 dereferenceable(344), i1 noundef zeroext) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core13sc_simcontext9next_timeERNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core6sc_ppqIPNS_14sc_event_timedEE11extract_topEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core14sc_event_timed5eventEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core14sc_event_timedD2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core14sc_event_timeddlEPvm(ptr noundef, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZNK7sc_core6sc_ppqIPNS_14sc_event_timedEE3topEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core11sc_runnable8is_emptyEv(ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #5 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeleERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 312}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{!6, !12, i64 297}
!35 = !{!6, !7, i64 304}
!36 = !{!6, !12, i64 224}
!37 = !{i8 0, i8 2}
!38 = !{}
!39 = !{!6, !12, i64 296}
!40 = !{!6, !31, i64 280}
!41 = !{!6, !7, i64 192}
!42 = distinct !{!42, !43}
!43 = !{!"llvm.loop.mustprogress"}
!44 = !{!6, !7, i64 232}
!45 = distinct !{!45, !43}
!46 = distinct !{!46, !43}
!47 = !{!6, !32, i64 300}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass