; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_process.ll (ZN7sc_core12sc_process_bD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_b" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.18", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.23", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8, [3 x i8] }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTVN7sc_core12sc_process_bE = external dso_local unnamed_addr constant { [26 x ptr] }, align 8

; Function Attrs: nounwind
declare void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160)) unnamed_addr #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112)) unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core12sc_process_bD2Ev(ptr noundef nonnull align 8 dereferenceable(357) %0) unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 192) ({ [26 x ptr] }, ptr @_ZTVN7sc_core12sc_process_bE, i32 0, i32 0, i32 2), ptr %3, align 8, !tbaa !9
  %4 = load ptr, ptr %3, align 8, !tbaa !9
  %5 = getelementptr inbounds ptr, ptr %4, i64 14
  %6 = load ptr, ptr %5, align 8
  invoke void %6(ptr noundef nonnull align 8 dereferenceable(112) %3)
          to label %7 unwind label %64

7:                                                ; preds = %1
  %8 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 14
  %9 = load i8, ptr %8, align 8, !tbaa !11, !range !38, !noundef !39
  %10 = trunc i8 %9 to i1
  br i1 %10, label %11, label %20

11:                                               ; preds = %7
  %12 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 27
  %13 = load ptr, ptr %12, align 8, !tbaa !40
  %14 = icmp eq ptr %13, null
  br i1 %14, label %19, label %15

15:                                               ; preds = %11
  %16 = load ptr, ptr %13, align 8, !tbaa !9
  %17 = getelementptr inbounds ptr, ptr %16, i64 1
  %18 = load ptr, ptr %17, align 8
  call void %18(ptr noundef nonnull align 8 dereferenceable(8) %13) #4
  br label %19

19:                                               ; preds = %15, %11
  br label %20

20:                                               ; preds = %19, %7
  %21 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 19
  %22 = load ptr, ptr %21, align 8, !tbaa !41
  %23 = icmp eq ptr %22, null
  br i1 %23, label %28, label %24

24:                                               ; preds = %20
  %25 = load ptr, ptr %22, align 8, !tbaa !9
  %26 = getelementptr inbounds ptr, ptr %25, i64 1
  %27 = load ptr, ptr %26, align 8
  call void %27(ptr noundef nonnull align 8 dereferenceable(80) %22) #4
  br label %28

28:                                               ; preds = %24, %20
  %29 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 20
  %30 = load ptr, ptr %29, align 8, !tbaa !42
  %31 = icmp eq ptr %30, null
  br i1 %31, label %33, label %32

32:                                               ; preds = %28
  call void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %30) #4
  call void @_ZdlPvm(ptr noundef %30, i64 noundef 8248) #5
  br label %33

33:                                               ; preds = %32, %28
  %34 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 24
  %35 = load ptr, ptr %34, align 8, !tbaa !43
  %36 = icmp eq ptr %35, null
  br i1 %36, label %38, label %37

37:                                               ; preds = %33
  call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %35) #4
  call void @_ZdlPvm(ptr noundef %35, i64 noundef 160) #5
  br label %38

38:                                               ; preds = %37, %33
  %39 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 25
  %40 = load ptr, ptr %39, align 8, !tbaa !44
  %41 = icmp eq ptr %40, null
  br i1 %41, label %43, label %42

42:                                               ; preds = %38
  call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %40) #4
  call void @_ZdlPvm(ptr noundef %40, i64 noundef 160) #5
  br label %43

43:                                               ; preds = %42, %38
  %44 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 34
  %45 = load ptr, ptr %44, align 8, !tbaa !45
  %46 = icmp eq ptr %45, null
  br i1 %46, label %48, label %47

47:                                               ; preds = %43
  call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %45) #4
  call void @_ZdlPvm(ptr noundef %45, i64 noundef 160) #5
  br label %48

48:                                               ; preds = %47, %43
  %49 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 35
  %50 = load ptr, ptr %49, align 8, !tbaa !46
  %51 = icmp eq ptr %50, null
  br i1 %51, label %56, label %52

52:                                               ; preds = %48
  %53 = load ptr, ptr %50, align 8, !tbaa !9
  %54 = getelementptr inbounds ptr, ptr %53, i64 3
  %55 = load ptr, ptr %54, align 8
  call void %55(ptr noundef nonnull align 8 dereferenceable(8) %50) #4
  br label %56

56:                                               ; preds = %52, %48
  %57 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 39
  %58 = load ptr, ptr %57, align 8, !tbaa !47
  %59 = icmp eq ptr %58, null
  br i1 %59, label %61, label %60

60:                                               ; preds = %56
  call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %58) #4
  call void @_ZdlPvm(ptr noundef %58, i64 noundef 160) #5
  br label %61

61:                                               ; preds = %60, %56
  %62 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 31
  call void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %62) #4
  %63 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %3, i32 0, i32 23
  call void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %63) #4
  call void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112) %3) #4
  ret void

64:                                               ; preds = %1
  %65 = landingpad { ptr, i32 }
          catch ptr null
  %66 = extractvalue { ptr, i32 } %65, 0
  call void @__clang_call_terminate(ptr %66) #6
  unreachable
}

; Function Attrs: noinline noreturn nounwind uwtable
declare hidden void @__clang_call_terminate(ptr noundef) #3

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #0

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noinline noreturn nounwind uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !26, i64 176}
!12 = !{!"_ZTSN7sc_core12sc_process_bE", !13, i64 0, !6, i64 112, !25, i64 120, !25, i64 124, !25, i64 128, !25, i64 132, !26, i64 136, !26, i64 137, !6, i64 144, !25, i64 152, !6, i64 160, !6, i64 168, !26, i64 176, !26, i64 177, !26, i64 178, !26, i64 179, !6, i64 184, !6, i64 192, !27, i64 200, !25, i64 204, !28, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !25, i64 280, !32, i64 288, !26, i64 312, !6, i64 320, !6, i64 328, !36, i64 336, !26, i64 340, !6, i64 344, !37, i64 352, !26, i64 356}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !6, i64 96, !6, i64 104}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"int", !7, i64 0}
!26 = !{!"bool", !7, i64 0}
!27 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!28 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!36 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!37 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!38 = !{i8 0, i8 2}
!39 = !{}
!40 = !{!12, !6, i64 256}
!41 = !{!12, !6, i64 184}
!42 = !{!12, !6, i64 192}
!43 = !{!12, !6, i64 232}
!44 = !{!12, !6, i64 240}
!45 = !{!12, !6, i64 320}
!46 = !{!12, !6, i64 328}
!47 = !{!12, !6, i64 344}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN7sc_core12sc_process_bE = external dso_local unnamed_addr constant { [26 x ptr] }, align 8

; Function Attrs: nounwind
declare void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160)) unnamed_addr #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112)) unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core12sc_process_bD2Ev(ptr noundef nonnull align 8 dereferenceable(357) %0) unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  store ptr getelementptr inbounds inrange(-16, 192) (i8, ptr @_ZTVN7sc_core12sc_process_bE, i64 16), ptr %0, align 8, !tbaa !5
  %2 = load ptr, ptr getelementptr inbounds inrange(-128, 80) (i8, ptr @_ZTVN7sc_core12sc_process_bE, i64 128), align 8
  invoke void %2(ptr noundef nonnull align 8 dereferenceable(112) %0)
          to label %3 unwind label %59

3:                                                ; preds = %1
  %4 = getelementptr inbounds i8, ptr %0, i64 176
  %5 = load i8, ptr %4, align 8, !tbaa !8, !range !37, !noundef !38
  %6 = trunc nuw i8 %5 to i1
  br i1 %6, label %7, label %15

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 256
  %9 = load ptr, ptr %8, align 8, !tbaa !39
  %10 = icmp eq ptr %9, null
  br i1 %10, label %15, label %11

11:                                               ; preds = %7
  %12 = load ptr, ptr %9, align 8, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %12, i64 8
  %14 = load ptr, ptr %13, align 8
  tail call void %14(ptr noundef nonnull align 8 dereferenceable(8) %9) #4
  br label %15

15:                                               ; preds = %7, %11, %3
  %16 = getelementptr inbounds i8, ptr %0, i64 184
  %17 = load ptr, ptr %16, align 8, !tbaa !40
  %18 = icmp eq ptr %17, null
  br i1 %18, label %23, label %19

19:                                               ; preds = %15
  %20 = load ptr, ptr %17, align 8, !tbaa !5
  %21 = getelementptr inbounds i8, ptr %20, i64 8
  %22 = load ptr, ptr %21, align 8
  tail call void %22(ptr noundef nonnull align 8 dereferenceable(80) %17) #4
  br label %23

23:                                               ; preds = %19, %15
  %24 = getelementptr inbounds i8, ptr %0, i64 192
  %25 = load ptr, ptr %24, align 8, !tbaa !41
  %26 = icmp eq ptr %25, null
  br i1 %26, label %28, label %27

27:                                               ; preds = %23
  tail call void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %25) #4
  tail call void @_ZdlPvm(ptr noundef nonnull %25, i64 noundef 8248) #5
  br label %28

28:                                               ; preds = %27, %23
  %29 = getelementptr inbounds i8, ptr %0, i64 232
  %30 = load ptr, ptr %29, align 8, !tbaa !42
  %31 = icmp eq ptr %30, null
  br i1 %31, label %33, label %32

32:                                               ; preds = %28
  tail call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %30) #4
  tail call void @_ZdlPvm(ptr noundef nonnull %30, i64 noundef 160) #5
  br label %33

33:                                               ; preds = %32, %28
  %34 = getelementptr inbounds i8, ptr %0, i64 240
  %35 = load ptr, ptr %34, align 8, !tbaa !43
  %36 = icmp eq ptr %35, null
  br i1 %36, label %38, label %37

37:                                               ; preds = %33
  tail call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %35) #4
  tail call void @_ZdlPvm(ptr noundef nonnull %35, i64 noundef 160) #5
  br label %38

38:                                               ; preds = %37, %33
  %39 = getelementptr inbounds i8, ptr %0, i64 320
  %40 = load ptr, ptr %39, align 8, !tbaa !44
  %41 = icmp eq ptr %40, null
  br i1 %41, label %43, label %42

42:                                               ; preds = %38
  tail call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %40) #4
  tail call void @_ZdlPvm(ptr noundef nonnull %40, i64 noundef 160) #5
  br label %43

43:                                               ; preds = %42, %38
  %44 = getelementptr inbounds i8, ptr %0, i64 328
  %45 = load ptr, ptr %44, align 8, !tbaa !45
  %46 = icmp eq ptr %45, null
  br i1 %46, label %51, label %47

47:                                               ; preds = %43
  %48 = load ptr, ptr %45, align 8, !tbaa !5
  %49 = getelementptr inbounds i8, ptr %48, i64 24
  %50 = load ptr, ptr %49, align 8
  tail call void %50(ptr noundef nonnull align 8 dereferenceable(8) %45) #4
  br label %51

51:                                               ; preds = %47, %43
  %52 = getelementptr inbounds i8, ptr %0, i64 344
  %53 = load ptr, ptr %52, align 8, !tbaa !46
  %54 = icmp eq ptr %53, null
  br i1 %54, label %56, label %55

55:                                               ; preds = %51
  tail call void @_ZN7sc_core8sc_eventD1Ev(ptr noundef nonnull align 8 dereferenceable(160) %53) #4
  tail call void @_ZdlPvm(ptr noundef nonnull %53, i64 noundef 160) #5
  br label %56

56:                                               ; preds = %55, %51
  %57 = getelementptr inbounds i8, ptr %0, i64 288
  tail call void @_ZNSt6vectorIPKN7sc_core8sc_eventESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %57) #4
  %58 = getelementptr inbounds i8, ptr %0, i64 208
  tail call void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %58) #4
  tail call void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112) %0) #4
  ret void

59:                                               ; preds = %1
  %60 = landingpad { ptr, i32 }
          catch ptr null
  %61 = extractvalue { ptr, i32 } %60, 0
  tail call void @__clang_call_terminate(ptr %61) #6
  unreachable
}

; Function Attrs: noinline noreturn nounwind uwtable
declare hidden void @__clang_call_terminate(ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #0

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noinline noreturn nounwind uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !25, i64 176}
!9 = !{!"_ZTSN7sc_core12sc_process_bE", !10, i64 0, !11, i64 112, !24, i64 120, !24, i64 124, !24, i64 128, !24, i64 132, !25, i64 136, !25, i64 137, !11, i64 144, !24, i64 152, !11, i64 160, !11, i64 168, !25, i64 176, !25, i64 177, !25, i64 178, !25, i64 179, !11, i64 184, !11, i64 192, !26, i64 200, !24, i64 204, !27, i64 208, !11, i64 232, !11, i64 240, !11, i64 248, !11, i64 256, !12, i64 264, !24, i64 280, !31, i64 288, !25, i64 312, !11, i64 320, !11, i64 328, !35, i64 336, !25, i64 340, !11, i64 344, !36, i64 352, !25, i64 356}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !12, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!23 = !{!"long", !12, i64 0}
!24 = !{!"int", !12, i64 0}
!25 = !{!"bool", !12, i64 0}
!26 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !12, i64 0}
!27 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!31 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!35 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !12, i64 0}
!36 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !12, i64 0}
!37 = !{i8 0, i8 2}
!38 = !{}
!39 = !{!9, !11, i64 256}
!40 = !{!9, !11, i64 184}
!41 = !{!9, !11, i64 192}
!42 = !{!9, !11, i64 232}
!43 = !{!9, !11, i64 240}
!44 = !{!9, !11, i64 320}
!45 = !{!9, !11, i64 328}
!46 = !{!9, !11, i64 344}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass