; LLVM IR from gem5/gem5 :: src/arch/sparc/asi.ll (ZN4gem58SparcISA9asiIsTwinENS0_3ASIE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN4gem58SparcISA9asiIsTwinENS0_3ASIE(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  %3 = load i32, ptr %2, align 4, !tbaa !5
  %4 = icmp sge i32 %3, 34
  br i1 %4, label %5, label %11

5:                                                ; preds = %1
  %6 = load i32, ptr %2, align 4, !tbaa !5
  %7 = icmp sle i32 %6, 39
  br i1 %7, label %8, label %11

8:                                                ; preds = %5
  %9 = load i32, ptr %2, align 4, !tbaa !5
  %10 = icmp ne i32 %9, 37
  br i1 %10, label %32, label %11

11:                                               ; preds = %8, %5, %1
  %12 = load i32, ptr %2, align 4, !tbaa !5
  %13 = icmp sge i32 %12, 42
  br i1 %13, label %14, label %20

14:                                               ; preds = %11
  %15 = load i32, ptr %2, align 4, !tbaa !5
  %16 = icmp sle i32 %15, 47
  br i1 %16, label %17, label %20

17:                                               ; preds = %14
  %18 = load i32, ptr %2, align 4, !tbaa !5
  %19 = icmp ne i32 %18, 45
  br i1 %19, label %32, label %20

20:                                               ; preds = %17, %14, %11
  %21 = load i32, ptr %2, align 4, !tbaa !5
  %22 = icmp eq i32 %21, 226
  br i1 %22, label %32, label %23

23:                                               ; preds = %20
  %24 = load i32, ptr %2, align 4, !tbaa !5
  %25 = icmp eq i32 %24, 227
  br i1 %25, label %32, label %26

26:                                               ; preds = %23
  %27 = load i32, ptr %2, align 4, !tbaa !5
  %28 = icmp eq i32 %27, 234
  br i1 %28, label %32, label %29

29:                                               ; preds = %26
  %30 = load i32, ptr %2, align 4, !tbaa !5
  %31 = icmp eq i32 %30, 235
  br label %32

32:                                               ; preds = %29, %26, %23, %20, %17, %8
  %33 = phi i1 [ true, %26 ], [ true, %23 ], [ true, %20 ], [ true, %17 ], [ true, %8 ], [ %31, %29 ]
  ret i1 %33
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"_ZTSN4gem58SparcISA3ASIE", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local noundef zeroext i1 @_ZN4gem58SparcISA9asiIsTwinENS0_3ASIE(i32 noundef %0) local_unnamed_addr #0 {
  %2 = add i32 %0, -34
  %or.cond = icmp ult i32 %2, 6
  %3 = icmp ne i32 %0, 37
  %or.cond3 = and i1 %3, %or.cond
  br i1 %or.cond3, label %8, label %4

4:                                                ; preds = %1
  %5 = add i32 %0, -42
  %or.cond5 = icmp ult i32 %5, 6
  %6 = icmp ne i32 %0, 45
  %or.cond7 = and i1 %6, %or.cond5
  br i1 %or.cond7, label %8, label %switch.early.test

switch.early.test:                                ; preds = %4
  %7 = add i32 %0, -226
  %switch.and = and i32 %7, -10
  %switch.selectcmp = icmp eq i32 %switch.and, 0
  br label %8

8:                                                ; preds = %switch.early.test, %4, %1
  %9 = phi i1 [ true, %1 ], [ true, %4 ], [ %switch.selectcmp, %switch.early.test ]
  ret i1 %9
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass