; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library (PciCf8Write16)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @SaveAndDisableInterrupts() #0

declare i32 @IoRead32(i64 noundef) #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @PciCf8Write16(i64 noundef %0, i16 noundef zeroext %1) #2 {
  %3 = alloca i64, align 8
  %4 = alloca i16, align 2
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i16, align 2
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i16 %1, ptr %4, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #3
  br label %8

8:                                                ; preds = %2
  %9 = call zeroext i8 @DebugAssertEnabled()
  %10 = icmp ne i8 %9, 0
  br i1 %10, label %11, label %17

11:                                               ; preds = %8
  %12 = load i64, ptr %3, align 8, !tbaa !5
  %13 = and i64 %12, -268431615
  %14 = icmp eq i64 %13, 0
  br i1 %14, label %16, label %15

15:                                               ; preds = %11
  call void @DebugAssert(ptr noundef @.str, i64 noundef 652, ptr noundef @.str.2)
  br label %16

16:                                               ; preds = %15, %11
  br label %17

17:                                               ; preds = %16, %8
  br label %18

18:                                               ; preds = %17
  br label %19

19:                                               ; preds = %18
  %20 = call zeroext i8 @SaveAndDisableInterrupts()
  store i8 %20, ptr %5, align 1, !tbaa !11
  %21 = call i32 @IoRead32(i64 noundef 3320)
  store i32 %21, ptr %6, align 4, !tbaa !12
  %22 = load i64, ptr %3, align 8, !tbaa !5
  %23 = lshr i64 %22, 4
  %24 = and i64 %23, 16776960
  %25 = load i64, ptr %3, align 8, !tbaa !5
  %26 = and i64 %25, 252
  %27 = or i64 %24, %26
  %28 = or i64 %27, 2147483648
  %29 = trunc i64 %28 to i32
  %30 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %29)
  %31 = load i64, ptr %3, align 8, !tbaa !5
  %32 = and i64 %31, 2
  %33 = trunc i64 %32 to i16
  %34 = zext i16 %33 to i32
  %35 = add nsw i32 3324, %34
  %36 = sext i32 %35 to i64
  %37 = load i16, ptr %4, align 2, !tbaa !9
  %38 = call zeroext i16 @IoWrite16(i64 noundef %36, i16 noundef zeroext %37)
  store i16 %38, ptr %7, align 2, !tbaa !9
  %39 = load i32, ptr %6, align 4, !tbaa !12
  %40 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %39)
  %41 = load i8, ptr %5, align 1, !tbaa !11
  %42 = call zeroext i8 @SetInterruptState(i8 noundef zeroext %41)
  %43 = load i16, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  ret i16 %43
}

declare zeroext i16 @IoWrite16(i64 noundef, i16 noundef zeroext) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

declare zeroext i8 @SaveAndDisableInterrupts() local_unnamed_addr #0

declare i32 @IoRead32(i64 noundef) local_unnamed_addr #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @PciCf8Write16(i64 noundef %0, i16 noundef zeroext %1) local_unnamed_addr #1 {
  %3 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not = icmp eq i8 %3, 0
  %4 = and i64 %0, -268431615
  %5 = icmp eq i64 %4, 0
  %or.cond = or i1 %5, %.not
  br i1 %or.cond, label %7, label %6

6:                                                ; preds = %2
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 652, ptr noundef nonnull @.str.2) #2
  br label %7

7:                                                ; preds = %6, %2
  %8 = tail call zeroext i8 @SaveAndDisableInterrupts() #2
  %9 = tail call i32 @IoRead32(i64 noundef 3320) #2
  %10 = lshr i64 %0, 4
  %11 = and i64 %10, 16776960
  %12 = and i64 %0, 252
  %13 = or disjoint i64 %11, %12
  %14 = trunc nuw nsw i64 %13 to i32
  %15 = or disjoint i32 %14, -2147483648
  %16 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %15) #2
  %17 = and i64 %0, 2
  %18 = or disjoint i64 %17, 3324
  %19 = tail call zeroext i16 @IoWrite16(i64 noundef %18, i16 noundef zeroext %1) #2
  %20 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %9) #2
  %21 = tail call zeroext i8 @SetInterruptState(i8 noundef zeroext %8) #2
  ret i16 %19
}

declare zeroext i16 @IoWrite16(i64 noundef, i16 noundef zeroext) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass