; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int (sc_signed)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_dt::sc_length_param" = type { i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef, ptr noundef) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt15sc_length_paramC2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt15sc_length_param3lenEv(ptr noundef nonnull align 4 dereferenceable(4)) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt17div_signed_friendEiiiPKjiiS1_(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_signed") align 8 %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, ptr noundef %7) #3 {
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  %18 = alloca %"class.sc_dt::sc_length_param", align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca ptr, align 8
  %22 = alloca i32, align 4
  store ptr %0, ptr %9, align 8
  store i32 %1, ptr %10, align 4, !tbaa !5
  store i32 %2, ptr %11, align 4, !tbaa !5
  store i32 %3, ptr %12, align 4, !tbaa !5
  store ptr %4, ptr %13, align 8, !tbaa !9
  store i32 %5, ptr %14, align 4, !tbaa !5
  store i32 %6, ptr %15, align 4, !tbaa !5
  store ptr %7, ptr %16, align 8, !tbaa !9
  %23 = load i32, ptr %12, align 4, !tbaa !5
  %24 = load ptr, ptr %13, align 8, !tbaa !9
  %25 = call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %23, ptr noundef %24)
  store i32 %25, ptr %12, align 4, !tbaa !5
  %26 = load i32, ptr %15, align 4, !tbaa !5
  %27 = load ptr, ptr %16, align 8, !tbaa !9
  %28 = call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %26, ptr noundef %27)
  store i32 %28, ptr %15, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #7
  %29 = load i32, ptr %12, align 4, !tbaa !5
  %30 = load ptr, ptr %13, align 8, !tbaa !9
  %31 = load i32, ptr %15, align 4, !tbaa !5
  %32 = load ptr, ptr %16, align 8, !tbaa !9
  %33 = call noundef i32 @_ZN5sc_dt7vec_cmpEiPKjiS1_(i32 noundef %29, ptr noundef %30, i32 noundef %31, ptr noundef %32)
  store i32 %33, ptr %17, align 4, !tbaa !5
  %34 = load i32, ptr %17, align 4, !tbaa !5
  %35 = icmp slt i32 %34, 0
  br i1 %35, label %36, label %38

36:                                               ; preds = %8
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #7
  call void @_ZN5sc_dt15sc_length_paramC2Ev(ptr noundef nonnull align 4 dereferenceable(4) %18)
  %37 = call noundef i32 @_ZNK5sc_dt15sc_length_param3lenEv(ptr noundef nonnull align 4 dereferenceable(4) %18)
  call void @_ZN5sc_dt9sc_signedC1Ei(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %37)
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #7
  store i32 1, ptr %19, align 4
  br label %107

38:                                               ; preds = %8
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #7
  %39 = call noundef i32 @_ZN5sc_dt6sc_maxIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %12, ptr noundef nonnull align 4 dereferenceable(4) %15)
  %40 = add nsw i32 %39, 1
  store i32 %40, ptr %20, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %21) #7
  %41 = load i32, ptr %20, align 4, !tbaa !5
  %42 = sext i32 %41 to i64
  %43 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %42, i64 4)
  %44 = extractvalue { i64, i1 } %43, 1
  %45 = extractvalue { i64, i1 } %43, 0
  %46 = select i1 %44, i64 -1, i64 %45
  %47 = call noalias noundef nonnull ptr @_Znam(i64 noundef %46) #8
  store ptr %47, ptr %21, align 8, !tbaa !9
  %48 = load i32, ptr %20, align 4, !tbaa !5
  %49 = load ptr, ptr %21, align 8, !tbaa !9
  call void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef %48, ptr noundef %49)
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #7
  %50 = load ptr, ptr %16, align 8, !tbaa !9
  %51 = load i32, ptr %50, align 4, !tbaa !5
  store i32 %51, ptr %22, align 4, !tbaa !5
  %52 = load i32, ptr %17, align 4, !tbaa !5
  %53 = icmp eq i32 %52, 0
  br i1 %53, label %54, label %57

54:                                               ; preds = %38
  %55 = load ptr, ptr %21, align 8, !tbaa !9
  %56 = getelementptr inbounds i32, ptr %55, i64 0
  store i32 1, ptr %56, align 4, !tbaa !5
  br label %101

57:                                               ; preds = %38
  %58 = load i32, ptr %15, align 4, !tbaa !5
  %59 = icmp eq i32 %58, 1
  br i1 %59, label %60, label %67

60:                                               ; preds = %57
  %61 = load i32, ptr %22, align 4, !tbaa !5
  %62 = icmp eq i32 %61, 1
  br i1 %62, label %63, label %67

63:                                               ; preds = %60
  %64 = load i32, ptr %12, align 4, !tbaa !5
  %65 = load ptr, ptr %21, align 8, !tbaa !9
  %66 = load ptr, ptr %13, align 8, !tbaa !9
  call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %64, ptr noundef %65, ptr noundef %66)
  br label %100

67:                                               ; preds = %60, %57
  %68 = load i32, ptr %15, align 4, !tbaa !5
  %69 = icmp eq i32 %68, 1
  br i1 %69, label %70, label %80

70:                                               ; preds = %67
  %71 = load i32, ptr %12, align 4, !tbaa !5
  %72 = icmp eq i32 %71, 1
  br i1 %72, label %73, label %80

73:                                               ; preds = %70
  %74 = load ptr, ptr %13, align 8, !tbaa !9
  %75 = load i32, ptr %74, align 4, !tbaa !5
  %76 = load i32, ptr %22, align 4, !tbaa !5
  %77 = udiv i32 %75, %76
  %78 = load ptr, ptr %21, align 8, !tbaa !9
  %79 = getelementptr inbounds i32, ptr %78, i64 0
  store i32 %77, ptr %79, align 4, !tbaa !5
  br label %99

80:                                               ; preds = %70, %67
  %81 = load i32, ptr %15, align 4, !tbaa !5
  %82 = icmp eq i32 %81, 1
  br i1 %82, label %83, label %92

83:                                               ; preds = %80
  %84 = load i32, ptr %22, align 4, !tbaa !5
  %85 = zext i32 %84 to i64
  %86 = icmp ult i64 %85, 32768
  br i1 %86, label %87, label %92

87:                                               ; preds = %83
  %88 = load i32, ptr %12, align 4, !tbaa !5
  %89 = load ptr, ptr %13, align 8, !tbaa !9
  %90 = load i32, ptr %22, align 4, !tbaa !5
  %91 = load ptr, ptr %21, align 8, !tbaa !9
  call void @_ZN5sc_dt13vec_div_smallEiPKjjPj(i32 noundef %88, ptr noundef %89, i32 noundef %90, ptr noundef %91)
  br label %98

92:                                               ; preds = %83, %80
  %93 = load i32, ptr %12, align 4, !tbaa !5
  %94 = load ptr, ptr %13, align 8, !tbaa !9
  %95 = load i32, ptr %15, align 4, !tbaa !5
  %96 = load ptr, ptr %16, align 8, !tbaa !9
  %97 = load ptr, ptr %21, align 8, !tbaa !9
  call void @_ZN5sc_dt13vec_div_largeEiPKjiS1_Pj(i32 noundef %93, ptr noundef %94, i32 noundef %95, ptr noundef %96, ptr noundef %97)
  br label %98

98:                                               ; preds = %92, %87
  br label %99

99:                                               ; preds = %98, %73
  br label %100

100:                                              ; preds = %99, %63
  br label %101

101:                                              ; preds = %100, %54
  %102 = load i32, ptr %10, align 4, !tbaa !5
  %103 = call noundef i32 @_ZN5sc_dt6sc_maxIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %11, ptr noundef nonnull align 4 dereferenceable(4) %14)
  %104 = load i32, ptr %20, align 4, !tbaa !5
  %105 = sub nsw i32 %104, 1
  %106 = load ptr, ptr %21, align 8, !tbaa !9
  call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %102, i32 noundef %103, i32 noundef %105, ptr noundef %106, i1 noundef zeroext true)
  store i32 1, ptr %19, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %21) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #7
  br label %107

107:                                              ; preds = %101, %36
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #7
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef, ptr noundef) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt6sc_maxIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #4

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt7vec_cmpEiPKjiS1_(i32 noundef, ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef, ptr noundef, ptr noundef) #2

declare void @_ZN5sc_dt13vec_div_smallEiPKjjPj(i32 noundef, ptr noundef, i32 noundef, ptr noundef) #6

declare void @_ZN5sc_dt13vec_div_largeEiPKjiS1_Pj(i32 noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) #6

declare void @_ZN5sc_dt9sc_signedC1Ei(ptr, i32)

declare void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr, i32, i32, i32, ptr, i1)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_dt::sc_length_param" = type { i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt15sc_length_paramC2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt15sc_length_param3lenEv(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt17div_signed_friendEiiiPKjiiS1_(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_signed") align 8 %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, ptr noundef %7) local_unnamed_addr #3 {
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca %"class.sc_dt::sc_length_param", align 4
  store i32 %2, ptr %9, align 4, !tbaa !5
  store i32 %5, ptr %11, align 4, !tbaa !5
  %14 = tail call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %3, ptr noundef %4)
  store i32 %14, ptr %10, align 4, !tbaa !5
  %15 = tail call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %6, ptr noundef %7)
  store i32 %15, ptr %12, align 4, !tbaa !5
  %16 = tail call noundef i32 @_ZN5sc_dt7vec_cmpEiPKjiS1_(i32 noundef %14, ptr noundef %4, i32 noundef %15, ptr noundef %7)
  %17 = icmp slt i32 %16, 0
  br i1 %17, label %18, label %20

18:                                               ; preds = %8
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %13) #6
  call void @_ZN5sc_dt15sc_length_paramC2Ev(ptr noundef nonnull align 4 dereferenceable(4) %13)
  %19 = call noundef i32 @_ZNK5sc_dt15sc_length_param3lenEv(ptr noundef nonnull align 4 dereferenceable(4) %13)
  call void @_ZN5sc_dt9sc_signedC1Ei(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %19)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %13) #6
  br label %48

20:                                               ; preds = %8
  %21 = call noundef i32 @_ZN5sc_dt6sc_maxIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %10, ptr noundef nonnull align 4 dereferenceable(4) %12)
  %22 = add nsw i32 %21, 1
  %23 = zext nneg i32 %22 to i64
  %24 = icmp slt i32 %21, -1
  %25 = shl nuw nsw i64 %23, 2
  %26 = select i1 %24, i64 -1, i64 %25
  %27 = call noalias noundef nonnull ptr @_Znam(i64 noundef %26) #7
  call void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef %22, ptr noundef nonnull %27)
  %28 = load i32, ptr %7, align 4, !tbaa !5
  %29 = icmp eq i32 %16, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %20
  store i32 1, ptr %27, align 4, !tbaa !5
  br label %46

31:                                               ; preds = %20
  %32 = load i32, ptr %12, align 4, !tbaa !5
  %33 = icmp eq i32 %32, 1
  %34 = icmp eq i32 %28, 1
  %or.cond = select i1 %33, i1 %34, i1 false
  %35 = load i32, ptr %10, align 4
  br i1 %or.cond, label %36, label %37

36:                                               ; preds = %31
  call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %35, ptr noundef nonnull %27, ptr noundef %4)
  br label %46

37:                                               ; preds = %31
  %38 = icmp eq i32 %35, 1
  %or.cond3 = select i1 %33, i1 %38, i1 false
  br i1 %or.cond3, label %39, label %42

39:                                               ; preds = %37
  %40 = load i32, ptr %4, align 4, !tbaa !5
  %41 = udiv i32 %40, %28
  store i32 %41, ptr %27, align 4, !tbaa !5
  br label %46

42:                                               ; preds = %37
  %43 = icmp ult i32 %28, 32768
  %or.cond6 = select i1 %33, i1 %43, i1 false
  br i1 %or.cond6, label %44, label %45

44:                                               ; preds = %42
  call void @_ZN5sc_dt13vec_div_smallEiPKjjPj(i32 noundef %35, ptr noundef %4, i32 noundef %28, ptr noundef nonnull %27)
  br label %46

45:                                               ; preds = %42
  call void @_ZN5sc_dt13vec_div_largeEiPKjiS1_Pj(i32 noundef %35, ptr noundef %4, i32 noundef %32, ptr noundef nonnull %7, ptr noundef nonnull %27)
  br label %46

46:                                               ; preds = %36, %44, %45, %39, %30
  %47 = call noundef i32 @_ZN5sc_dt6sc_maxIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %9, ptr noundef nonnull align 4 dereferenceable(4) %11)
  call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %1, i32 noundef %47, i32 noundef %21, ptr noundef nonnull %27, i1 noundef zeroext true)
  br label %48

48:                                               ; preds = %46, %18
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt6sc_maxIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt7vec_cmpEiPKjiS1_(i32 noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @_ZN5sc_dt13vec_div_smallEiPKjjPj(i32 noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #5

declare void @_ZN5sc_dt13vec_div_largeEiPKjiS1_Pj(i32 noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #5

declare void @_ZN5sc_dt9sc_signedC1Ei(ptr, i32) local_unnamed_addr

declare void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr, i32, i32, i32, ptr, i1) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass