; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/sim_tests/biquad/biquad1 (main)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_signal" = type <{ %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, float, [4 x i8], i64, float, [4 x i8] }>
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }
%"class.sc_core::sc_signal.8" = type { %"class.sc_core::sc_signal_inout_if.9", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if.9" = type { %"class.sc_core::sc_signal_in_if.10", %"class.sc_core::sc_signal_write_if.11" }
%"class.sc_core::sc_signal_in_if.10" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if.11" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_clock" = type { %"class.sc_core::sc_signal.8", %"class.sc_core::sc_time", double, %"class.sc_core::sc_time", i8, %"class.sc_core::sc_time", %"class.sc_core::sc_time", %"class.sc_core::sc_event", %"class.sc_core::sc_event" }
%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.12", %"class.std::vector.12", %"class.std::vector.17", %"class.std::vector.17" }
%"class.std::vector.12" = type { %"struct.std::_Vector_base.13" }
%"struct.std::_Vector_base.13" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.17" = type { %"struct.std::_Vector_base.18" }
%"struct.std::_Vector_base.18" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.biquad = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.27", %"class.sc_core::sc_in", %"class.sc_core::sc_out", i32, [4 x float], [5 x float] }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in.27" = type { %"class.sc_core::sc_port.28", ptr, ptr }
%"class.sc_core::sc_port.28" = type { %"class.sc_core::sc_port_b.29" }
%"class.sc_core::sc_port_b.29" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.30" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.30" = type { %"struct.std::_Vector_base.31" }
%"struct.std::_Vector_base.31" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.22" }
%"class.std::vector.22" = type { %"struct.std::_Vector_base.23" }
%"struct.std::_Vector_base.23" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.35", ptr, ptr, ptr }
%"class.sc_core::sc_port.35" = type { %"class.sc_core::sc_port_b.36" }
%"class.sc_core::sc_port_b.36" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.37" }
%"class.std::vector.37" = type { %"struct.std::_Vector_base.38" }
%"struct.std::_Vector_base.38" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>
%struct.testbench = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.27", %"class.sc_core::sc_out.42", %"class.sc_core::sc_out" }
%"class.sc_core::sc_out.42" = type { %"class.sc_core::sc_inout.43" }
%"class.sc_core::sc_inout.43" = type { %"class.sc_core::sc_port.44", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.44" = type { %"class.sc_core::sc_port_b.45" }
%"class.sc_core::sc_port_b.45" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.46" }
%"class.std::vector.46" = type { %"struct.std::_Vector_base.47" }
%"struct.std::_Vector_base.47" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@signal_freq = external dso_local global float, align 4
@.str = external hidden unnamed_addr constant [6 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [8 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [3 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local i32 @sc_main(i32 noundef %0, ptr noundef %1) #0 personality ptr @__gxx_personality_v0 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca %"class.sc_core::sc_signal", align 8
  %6 = alloca %"class.sc_core::sc_signal", align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca %"class.sc_core::sc_signal.8", align 8
  %10 = alloca float, align 4
  %11 = alloca float, align 4
  %12 = alloca i8, align 1
  %13 = alloca %"class.sc_core::sc_clock", align 8
  %14 = alloca %struct.biquad, align 8
  %15 = alloca %"class.sc_core::sc_module_name", align 8
  %16 = alloca %struct.testbench, align 8
  %17 = alloca %"class.sc_core::sc_module_name", align 8
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 200, ptr %5) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196) %5)
  call void @llvm.lifetime.start.p0(i64 200, ptr %6) #8
  invoke void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196) %6)
          to label %20 unwind label %38

20:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 224, ptr %9) #8
  invoke void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(224) %9)
          to label %21 unwind label %42

21:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #8
  store float 0.000000e+00, ptr %10, align 4, !tbaa !11
  %22 = invoke noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %5, ptr noundef nonnull align 4 dereferenceable(4) %10)
          to label %23 unwind label %46

23:                                               ; preds = %21
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #8
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #8
  store float 0.000000e+00, ptr %11, align 4, !tbaa !11
  %24 = invoke noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %6, ptr noundef nonnull align 4 dereferenceable(4) %11)
          to label %25 unwind label %50

25:                                               ; preds = %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #8
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #8
  store i8 0, ptr %12, align 1, !tbaa !13
  %26 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %9, ptr noundef nonnull align 1 dereferenceable(1) %12)
          to label %27 unwind label %54

27:                                               ; preds = %25
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #8
  call void @llvm.lifetime.start.p0(i64 592, ptr %13) #8
  invoke void @_ZN7sc_core8sc_clockC1EPKcdNS_12sc_time_unitEd(ptr noundef nonnull align 8 dereferenceable(592) %13, ptr noundef @.str, double noundef 1.000000e+01, i32 noundef 2, double noundef 5.000000e-01)
          to label %28 unwind label %58

28:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 984, ptr %14) #8
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %15, ptr noundef @.str.2)
          to label %29 unwind label %62

29:                                               ; preds = %28
  invoke void @_ZN6biquadC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(984) %14, ptr noundef %15, ptr noundef nonnull align 8 dereferenceable(592) %13, ptr noundef nonnull align 8 dereferenceable(196) %5, ptr noundef nonnull align 8 dereferenceable(224) %9, ptr noundef nonnull align 8 dereferenceable(196) %6)
          to label %30 unwind label %66

30:                                               ; preds = %29
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %15) #8
  call void @llvm.lifetime.start.p0(i64 952, ptr %16) #8
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %17, ptr noundef @.str.3)
          to label %31 unwind label %70

31:                                               ; preds = %30
  invoke void @_ZN9testbenchC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(952) %16, ptr noundef %17, ptr noundef nonnull align 8 dereferenceable(592) %13, ptr noundef nonnull align 8 dereferenceable(196) %6, ptr noundef nonnull align 8 dereferenceable(224) %9, ptr noundef nonnull align 8 dereferenceable(196) %5)
          to label %32 unwind label %74

32:                                               ; preds = %31
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %17) #8
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #8
  store i32 10000, ptr %18, align 4, !tbaa !5
  store float 1.000000e+05, ptr @signal_freq, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #8
  store i32 1, ptr %19, align 4, !tbaa !5
  br label %33

33:                                               ; preds = %106, %32
  %34 = load i32, ptr %19, align 4, !tbaa !5
  %35 = load i32, ptr %3, align 4, !tbaa !5
  %36 = icmp slt i32 %34, %35
  br i1 %36, label %78, label %37

37:                                               ; preds = %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #8
  br label %109

38:                                               ; preds = %2
  %39 = landingpad { ptr, i32 }
          cleanup
  %40 = extractvalue { ptr, i32 } %39, 0
  store ptr %40, ptr %7, align 8
  %41 = extractvalue { ptr, i32 } %39, 1
  store i32 %41, ptr %8, align 4
  br label %121

42:                                               ; preds = %20
  %43 = landingpad { ptr, i32 }
          cleanup
  %44 = extractvalue { ptr, i32 } %43, 0
  store ptr %44, ptr %7, align 8
  %45 = extractvalue { ptr, i32 } %43, 1
  store i32 %45, ptr %8, align 4
  br label %120

46:                                               ; preds = %21
  %47 = landingpad { ptr, i32 }
          cleanup
  %48 = extractvalue { ptr, i32 } %47, 0
  store ptr %48, ptr %7, align 8
  %49 = extractvalue { ptr, i32 } %47, 1
  store i32 %49, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #8
  br label %119

50:                                               ; preds = %23
  %51 = landingpad { ptr, i32 }
          cleanup
  %52 = extractvalue { ptr, i32 } %51, 0
  store ptr %52, ptr %7, align 8
  %53 = extractvalue { ptr, i32 } %51, 1
  store i32 %53, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #8
  br label %119

54:                                               ; preds = %25
  %55 = landingpad { ptr, i32 }
          cleanup
  %56 = extractvalue { ptr, i32 } %55, 0
  store ptr %56, ptr %7, align 8
  %57 = extractvalue { ptr, i32 } %55, 1
  store i32 %57, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #8
  br label %119

58:                                               ; preds = %27
  %59 = landingpad { ptr, i32 }
          cleanup
  %60 = extractvalue { ptr, i32 } %59, 0
  store ptr %60, ptr %7, align 8
  %61 = extractvalue { ptr, i32 } %59, 1
  store i32 %61, ptr %8, align 4
  br label %118

62:                                               ; preds = %28
  %63 = landingpad { ptr, i32 }
          cleanup
  %64 = extractvalue { ptr, i32 } %63, 0
  store ptr %64, ptr %7, align 8
  %65 = extractvalue { ptr, i32 } %63, 1
  store i32 %65, ptr %8, align 4
  br label %117

66:                                               ; preds = %29
  %67 = landingpad { ptr, i32 }
          cleanup
  %68 = extractvalue { ptr, i32 } %67, 0
  store ptr %68, ptr %7, align 8
  %69 = extractvalue { ptr, i32 } %67, 1
  store i32 %69, ptr %8, align 4
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %15) #8
  br label %117

70:                                               ; preds = %30
  %71 = landingpad { ptr, i32 }
          cleanup
  %72 = extractvalue { ptr, i32 } %71, 0
  store ptr %72, ptr %7, align 8
  %73 = extractvalue { ptr, i32 } %71, 1
  store i32 %73, ptr %8, align 4
  br label %116

74:                                               ; preds = %31
  %75 = landingpad { ptr, i32 }
          cleanup
  %76 = extractvalue { ptr, i32 } %75, 0
  store ptr %76, ptr %7, align 8
  %77 = extractvalue { ptr, i32 } %75, 1
  store i32 %77, ptr %8, align 4
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %17) #8
  br label %116

78:                                               ; preds = %33
  %79 = load ptr, ptr %4, align 8, !tbaa !9
  %80 = load i32, ptr %19, align 4, !tbaa !5
  %81 = sext i32 %80 to i64
  %82 = getelementptr inbounds ptr, ptr %79, i64 %81
  %83 = load ptr, ptr %82, align 8, !tbaa !9
  %84 = getelementptr inbounds i8, ptr %83, i64 0
  %85 = load i8, ptr %84, align 1, !tbaa !15
  %86 = sext i8 %85 to i32
  %87 = icmp eq i32 %86, 45
  br i1 %87, label %88, label %99

88:                                               ; preds = %78
  %89 = load ptr, ptr %4, align 8, !tbaa !9
  %90 = load i32, ptr %19, align 4, !tbaa !5
  %91 = add nsw i32 %90, 1
  %92 = sext i32 %91 to i64
  %93 = getelementptr inbounds ptr, ptr %89, i64 %92
  %94 = load ptr, ptr %93, align 8, !tbaa !9
  %95 = call double @atof(ptr noundef %94) #9
  %96 = fptrunc double %95 to float
  store float %96, ptr @signal_freq, align 4, !tbaa !11
  %97 = load i32, ptr %19, align 4, !tbaa !5
  %98 = add nsw i32 %97, 1
  store i32 %98, ptr %19, align 4, !tbaa !5
  br label %106

99:                                               ; preds = %78
  %100 = load ptr, ptr %4, align 8, !tbaa !9
  %101 = load i32, ptr %19, align 4, !tbaa !5
  %102 = sext i32 %101 to i64
  %103 = getelementptr inbounds ptr, ptr %100, i64 %102
  %104 = load ptr, ptr %103, align 8, !tbaa !9
  %105 = call i32 @atoi(ptr noundef %104) #9
  store i32 %105, ptr %18, align 4, !tbaa !5
  br label %106

106:                                              ; preds = %99, %88
  %107 = load i32, ptr %19, align 4, !tbaa !5
  %108 = add nsw i32 %107, 1
  store i32 %108, ptr %19, align 4, !tbaa !5
  br label %33, !llvm.loop !16

109:                                              ; preds = %37
  %110 = load i32, ptr %18, align 4, !tbaa !5
  invoke void @_ZN7sc_core8sc_startEiNS_12sc_time_unitENS_20sc_starvation_policyE(i32 noundef %110, i32 noundef 2, i32 noundef 1)
          to label %111 unwind label %112

111:                                              ; preds = %109
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #8
  call void @_ZN9testbenchD2Ev(ptr noundef nonnull align 8 dereferenceable(952) %16) #8
  call void @llvm.lifetime.end.p0(i64 952, ptr %16) #8
  call void @_ZN6biquadD2Ev(ptr noundef nonnull align 8 dereferenceable(984) %14) #8
  call void @llvm.lifetime.end.p0(i64 984, ptr %14) #8
  call void @_ZN7sc_core8sc_clockD1Ev(ptr noundef nonnull align 8 dereferenceable(592) %13) #8
  call void @llvm.lifetime.end.p0(i64 592, ptr %13) #8
  call void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(224) %9) #8
  call void @llvm.lifetime.end.p0(i64 224, ptr %9) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %6) #8
  call void @llvm.lifetime.end.p0(i64 200, ptr %6) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %5) #8
  call void @llvm.lifetime.end.p0(i64 200, ptr %5) #8
  ret i32 0

112:                                              ; preds = %109
  %113 = landingpad { ptr, i32 }
          cleanup
  %114 = extractvalue { ptr, i32 } %113, 0
  store ptr %114, ptr %7, align 8
  %115 = extractvalue { ptr, i32 } %113, 1
  store i32 %115, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #8
  call void @_ZN9testbenchD2Ev(ptr noundef nonnull align 8 dereferenceable(952) %16) #8
  br label %116

116:                                              ; preds = %112, %74, %70
  call void @llvm.lifetime.end.p0(i64 952, ptr %16) #8
  call void @_ZN6biquadD2Ev(ptr noundef nonnull align 8 dereferenceable(984) %14) #8
  br label %117

117:                                              ; preds = %116, %66, %62
  call void @llvm.lifetime.end.p0(i64 984, ptr %14) #8
  call void @_ZN7sc_core8sc_clockD1Ev(ptr noundef nonnull align 8 dereferenceable(592) %13) #8
  br label %118

118:                                              ; preds = %117, %58
  call void @llvm.lifetime.end.p0(i64 592, ptr %13) #8
  br label %119

119:                                              ; preds = %118, %54, %50, %46
  call void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(224) %9) #8
  br label %120

120:                                              ; preds = %119, %42
  call void @llvm.lifetime.end.p0(i64 224, ptr %9) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %6) #8
  br label %121

121:                                              ; preds = %120, %38
  call void @llvm.lifetime.end.p0(i64 200, ptr %6) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %5) #8
  call void @llvm.lifetime.end.p0(i64 200, ptr %5) #8
  br label %122

122:                                              ; preds = %121
  %123 = load ptr, ptr %7, align 8
  %124 = load i32, ptr %8, align 4
  %125 = insertvalue { ptr, i32 } poison, ptr %123, 0
  %126 = insertvalue { ptr, i32 } %125, i32 %124, 1
  resume { ptr, i32 } %126
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(224)) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

declare void @_ZN7sc_core8sc_clockC1EPKcdNS_12sc_time_unitEd(ptr noundef nonnull align 8 dereferenceable(592), ptr noundef, double noundef, i32 noundef, double noundef) unnamed_addr #2

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6biquadC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(984), ptr noundef, ptr noundef nonnull align 8 dereferenceable(592), ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #0 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN9testbenchC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(952), ptr noundef, ptr noundef nonnull align 8 dereferenceable(592), ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind willreturn memory(read) uwtable
declare double @atof(ptr noundef nonnull) #4

; Function Attrs: inlinehint mustprogress nounwind willreturn memory(read) uwtable
declare i32 @atoi(ptr noundef nonnull) #4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_startEiNS_12sc_time_unitENS_20sc_starvation_policyE(i32 noundef, i32 noundef, i32 noundef) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN9testbenchD2Ev(ptr noundef nonnull align 8 dereferenceable(952)) unnamed_addr #6 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN6biquadD2Ev(ptr noundef nonnull align 8 dereferenceable(984)) unnamed_addr #6 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core8sc_clockD1Ev(ptr noundef nonnull align 8 dereferenceable(592)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(224)) unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #7 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind willreturn memory(read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { nounwind willreturn memory(read) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"float", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{!7, !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_signal" = type <{ %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, float, [4 x i8], i64, float, [4 x i8] }>
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }
%"class.sc_core::sc_signal.8" = type { %"class.sc_core::sc_signal_inout_if.9", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if.9" = type { %"class.sc_core::sc_signal_in_if.10", %"class.sc_core::sc_signal_write_if.11" }
%"class.sc_core::sc_signal_in_if.10" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if.11" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_clock" = type { %"class.sc_core::sc_signal.8", %"class.sc_core::sc_time", double, %"class.sc_core::sc_time", i8, %"class.sc_core::sc_time", %"class.sc_core::sc_time", %"class.sc_core::sc_event", %"class.sc_core::sc_event" }
%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.12", %"class.std::vector.12", %"class.std::vector.17", %"class.std::vector.17" }
%"class.std::vector.12" = type { %"struct.std::_Vector_base.13" }
%"struct.std::_Vector_base.13" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.17" = type { %"struct.std::_Vector_base.18" }
%"struct.std::_Vector_base.18" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.biquad = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.27", %"class.sc_core::sc_in", %"class.sc_core::sc_out", i32, [4 x float], [5 x float] }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in.27" = type { %"class.sc_core::sc_port.28", ptr, ptr }
%"class.sc_core::sc_port.28" = type { %"class.sc_core::sc_port_b.29" }
%"class.sc_core::sc_port_b.29" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.30" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.30" = type { %"struct.std::_Vector_base.31" }
%"struct.std::_Vector_base.31" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.22" }
%"class.std::vector.22" = type { %"struct.std::_Vector_base.23" }
%"struct.std::_Vector_base.23" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.35", ptr, ptr, ptr }
%"class.sc_core::sc_port.35" = type { %"class.sc_core::sc_port_b.36" }
%"class.sc_core::sc_port_b.36" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.37" }
%"class.std::vector.37" = type { %"struct.std::_Vector_base.38" }
%"struct.std::_Vector_base.38" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>
%struct.testbench = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.27", %"class.sc_core::sc_out.42", %"class.sc_core::sc_out" }
%"class.sc_core::sc_out.42" = type { %"class.sc_core::sc_inout.43" }
%"class.sc_core::sc_inout.43" = type { %"class.sc_core::sc_port.44", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.44" = type { %"class.sc_core::sc_port_b.45" }
%"class.sc_core::sc_port_b.45" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.46" }
%"class.std::vector.46" = type { %"struct.std::_Vector_base.47" }
%"struct.std::_Vector_base.47" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@signal_freq = external dso_local local_unnamed_addr global float, align 4
@.str = external hidden unnamed_addr constant [6 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [8 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [3 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @sc_main(i32 noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
  %3 = alloca %"class.sc_core::sc_signal", align 8
  %4 = alloca %"class.sc_core::sc_signal", align 8
  %5 = alloca %"class.sc_core::sc_signal.8", align 8
  %6 = alloca float, align 4
  %7 = alloca float, align 4
  %8 = alloca i8, align 1
  %9 = alloca %"class.sc_core::sc_clock", align 8
  %10 = alloca %struct.biquad, align 8
  %11 = alloca %"class.sc_core::sc_module_name", align 8
  %12 = alloca %struct.testbench, align 8
  %13 = alloca %"class.sc_core::sc_module_name", align 8
  call void @llvm.lifetime.start.p0(i64 200, ptr nonnull %3) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196) %3)
  call void @llvm.lifetime.start.p0(i64 200, ptr nonnull %4) #8
  invoke void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196) %4)
          to label %14 unwind label %28

14:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 224, ptr nonnull %5) #8
  invoke void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(224) %5)
          to label %15 unwind label %30

15:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #8
  store float 0.000000e+00, ptr %6, align 4, !tbaa !5
  %16 = invoke noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %3, ptr noundef nonnull align 4 dereferenceable(4) %6)
          to label %17 unwind label %32

17:                                               ; preds = %15
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #8
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #8
  store float 0.000000e+00, ptr %7, align 4, !tbaa !5
  %18 = invoke noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %4, ptr noundef nonnull align 4 dereferenceable(4) %7)
          to label %19 unwind label %34

19:                                               ; preds = %17
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #8
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %8) #8
  store i8 0, ptr %8, align 1, !tbaa !9
  %20 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %5, ptr noundef nonnull align 1 dereferenceable(1) %8)
          to label %21 unwind label %36

21:                                               ; preds = %19
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %8) #8
  call void @llvm.lifetime.start.p0(i64 592, ptr nonnull %9) #8
  invoke void @_ZN7sc_core8sc_clockC1EPKcdNS_12sc_time_unitEd(ptr noundef nonnull align 8 dereferenceable(592) %9, ptr noundef nonnull @.str, double noundef 1.000000e+01, i32 noundef 2, double noundef 5.000000e-01)
          to label %22 unwind label %38

22:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 984, ptr nonnull %10) #8
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %11, ptr noundef nonnull @.str.2)
          to label %23 unwind label %40

23:                                               ; preds = %22
  invoke void @_ZN6biquadC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(984) %10, ptr noundef nonnull %11, ptr noundef nonnull align 8 dereferenceable(592) %9, ptr noundef nonnull align 8 dereferenceable(196) %3, ptr noundef nonnull align 8 dereferenceable(224) %5, ptr noundef nonnull align 8 dereferenceable(196) %4)
          to label %24 unwind label %42

24:                                               ; preds = %23
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %11) #8
  call void @llvm.lifetime.start.p0(i64 952, ptr nonnull %12) #8
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %13, ptr noundef nonnull @.str.3)
          to label %25 unwind label %44

25:                                               ; preds = %24
  invoke void @_ZN9testbenchC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(952) %12, ptr noundef nonnull %13, ptr noundef nonnull align 8 dereferenceable(592) %9, ptr noundef nonnull align 8 dereferenceable(196) %4, ptr noundef nonnull align 8 dereferenceable(224) %5, ptr noundef nonnull align 8 dereferenceable(196) %3)
          to label %26 unwind label %46

26:                                               ; preds = %25
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %13) #8
  store float 1.000000e+05, ptr @signal_freq, align 4, !tbaa !5
  %27 = icmp sgt i32 %0, 1
  br i1 %27, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %62, %26
  %.012.lcssa = phi i32 [ 10000, %26 ], [ %.113, %62 ]
  invoke void @_ZN7sc_core8sc_startEiNS_12sc_time_unitENS_20sc_starvation_policyE(i32 noundef %.012.lcssa, i32 noundef 2, i32 noundef 1)
          to label %65 unwind label %66

28:                                               ; preds = %2
  %29 = landingpad { ptr, i32 }
          cleanup
  br label %73

30:                                               ; preds = %14
  %31 = landingpad { ptr, i32 }
          cleanup
  br label %72

32:                                               ; preds = %15
  %33 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #8
  br label %71

34:                                               ; preds = %17
  %35 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #8
  br label %71

36:                                               ; preds = %19
  %37 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %8) #8
  br label %71

38:                                               ; preds = %21
  %39 = landingpad { ptr, i32 }
          cleanup
  br label %70

40:                                               ; preds = %22
  %41 = landingpad { ptr, i32 }
          cleanup
  br label %69

42:                                               ; preds = %23
  %43 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %11) #8
  br label %69

44:                                               ; preds = %24
  %45 = landingpad { ptr, i32 }
          cleanup
  br label %68

46:                                               ; preds = %25
  %47 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %13) #8
  br label %68

.lr.ph:                                           ; preds = %26, %62
  %.029 = phi i32 [ %63, %62 ], [ 1, %26 ]
  %.01228 = phi i32 [ %.113, %62 ], [ 10000, %26 ]
  %48 = sext i32 %.029 to i64
  %49 = getelementptr inbounds ptr, ptr %1, i64 %48
  %50 = load ptr, ptr %49, align 8, !tbaa !11
  %51 = load i8, ptr %50, align 1, !tbaa !13
  %52 = icmp eq i8 %51, 45
  br i1 %52, label %53, label %60

53:                                               ; preds = %.lr.ph
  %54 = add nsw i32 %.029, 1
  %55 = sext i32 %54 to i64
  %56 = getelementptr inbounds ptr, ptr %1, i64 %55
  %57 = load ptr, ptr %56, align 8, !tbaa !11
  %58 = call double @atof(ptr noundef %57) #9
  %59 = fptrunc double %58 to float
  store float %59, ptr @signal_freq, align 4, !tbaa !5
  br label %62

60:                                               ; preds = %.lr.ph
  %61 = call i32 @atoi(ptr nocapture noundef %50) #9
  br label %62

62:                                               ; preds = %60, %53
  %.113 = phi i32 [ %.01228, %53 ], [ %61, %60 ]
  %.1 = phi i32 [ %54, %53 ], [ %.029, %60 ]
  %63 = add nsw i32 %.1, 1
  %64 = icmp slt i32 %63, %0
  br i1 %64, label %.lr.ph, label %._crit_edge, !llvm.loop !14

65:                                               ; preds = %._crit_edge
  call void @_ZN9testbenchD2Ev(ptr noundef nonnull align 8 dereferenceable(952) %12) #8
  call void @llvm.lifetime.end.p0(i64 952, ptr nonnull %12) #8
  call void @_ZN6biquadD2Ev(ptr noundef nonnull align 8 dereferenceable(984) %10) #8
  call void @llvm.lifetime.end.p0(i64 984, ptr nonnull %10) #8
  call void @_ZN7sc_core8sc_clockD1Ev(ptr noundef nonnull align 8 dereferenceable(592) %9) #8
  call void @llvm.lifetime.end.p0(i64 592, ptr nonnull %9) #8
  call void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(224) %5) #8
  call void @llvm.lifetime.end.p0(i64 224, ptr nonnull %5) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %4) #8
  call void @llvm.lifetime.end.p0(i64 200, ptr nonnull %4) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %3) #8
  call void @llvm.lifetime.end.p0(i64 200, ptr nonnull %3) #8
  ret i32 0

66:                                               ; preds = %._crit_edge
  %67 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN9testbenchD2Ev(ptr noundef nonnull align 8 dereferenceable(952) %12) #8
  br label %68

68:                                               ; preds = %66, %46, %44
  %.pn = phi { ptr, i32 } [ %67, %66 ], [ %47, %46 ], [ %45, %44 ]
  call void @llvm.lifetime.end.p0(i64 952, ptr nonnull %12) #8
  call void @_ZN6biquadD2Ev(ptr noundef nonnull align 8 dereferenceable(984) %10) #8
  br label %69

69:                                               ; preds = %68, %42, %40
  %.pn.pn = phi { ptr, i32 } [ %.pn, %68 ], [ %43, %42 ], [ %41, %40 ]
  call void @llvm.lifetime.end.p0(i64 984, ptr nonnull %10) #8
  call void @_ZN7sc_core8sc_clockD1Ev(ptr noundef nonnull align 8 dereferenceable(592) %9) #8
  br label %70

70:                                               ; preds = %69, %38
  %.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn, %69 ], [ %39, %38 ]
  call void @llvm.lifetime.end.p0(i64 592, ptr nonnull %9) #8
  br label %71

71:                                               ; preds = %70, %36, %34, %32
  %.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn, %70 ], [ %37, %36 ], [ %35, %34 ], [ %33, %32 ]
  call void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(224) %5) #8
  br label %72

72:                                               ; preds = %71, %30
  %.pn.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn.pn, %71 ], [ %31, %30 ]
  call void @llvm.lifetime.end.p0(i64 224, ptr nonnull %5) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %4) #8
  br label %73

73:                                               ; preds = %72, %28
  %.pn.pn.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn.pn.pn, %72 ], [ %29, %28 ]
  call void @llvm.lifetime.end.p0(i64 200, ptr nonnull %4) #8
  call void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %3) #8
  call void @llvm.lifetime.end.p0(i64 200, ptr nonnull %3) #8
  resume { ptr, i32 } %.pn.pn.pn.pn.pn.pn
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(224)) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #0 align 2

declare void @_ZN7sc_core8sc_clockC1EPKcdNS_12sc_time_unitEd(ptr noundef nonnull align 8 dereferenceable(592), ptr noundef, double noundef, i32 noundef, double noundef) unnamed_addr #2

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6biquadC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(984), ptr noundef, ptr noundef nonnull align 8 dereferenceable(592), ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #0 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN9testbenchC2EN7sc_core14sc_module_nameERNS0_8sc_clockERNS0_9sc_signalIfLNS0_16sc_writer_policyE0EEERNS4_IbLS5_0EEES7_(ptr noundef nonnull align 8 dereferenceable(952), ptr noundef, ptr noundef nonnull align 8 dereferenceable(592), ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nofree nounwind willreturn memory(read) uwtable
declare double @atof(ptr nocapture noundef nonnull) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nofree nounwind willreturn memory(read) uwtable
declare i32 @atoi(ptr nocapture noundef nonnull) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_startEiNS_12sc_time_unitENS_20sc_starvation_policyE(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN9testbenchD2Ev(ptr noundef nonnull align 8 dereferenceable(952)) unnamed_addr #6 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN6biquadD2Ev(ptr noundef nonnull align 8 dereferenceable(984)) unnamed_addr #6 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core8sc_clockD1Ev(ptr noundef nonnull align 8 dereferenceable(592)) unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(224)) unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #7 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nofree nounwind willreturn memory(read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { nounwind willreturn memory(read) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass