; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int (sc_int_base)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_int_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZN5sc_dt11sc_int_baseaSERKNS_9sc_signedE(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(32) %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %9 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  %10 = getelementptr inbounds %"class.sc_dt::sc_int_base", ptr %9, i32 0, i32 2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = call noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32) %11)
  store i32 %12, ptr %6, align 4, !tbaa !9
  %13 = call noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %10, ptr noundef nonnull align 4 dereferenceable(4) %6)
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  store i32 %13, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #5
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %14

14:                                               ; preds = %23, %2
  %15 = load i32, ptr %7, align 4, !tbaa !9
  %16 = load i32, ptr %5, align 4, !tbaa !9
  %17 = icmp slt i32 %15, %16
  br i1 %17, label %18, label %26

18:                                               ; preds = %14
  %19 = load i32, ptr %7, align 4, !tbaa !9
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = call noundef zeroext i1 @_ZNK5sc_dt9sc_signed4testEi(ptr noundef nonnull align 8 dereferenceable(32) %20, i32 noundef %21)
  call void @_ZN5sc_dt11sc_int_base3setEib(ptr noundef nonnull align 8 dereferenceable(24) %9, i32 noundef %19, i1 noundef zeroext %22)
  br label %23

23:                                               ; preds = %18
  %24 = load i32, ptr %7, align 4, !tbaa !9
  %25 = add nsw i32 %24, 1
  store i32 %25, ptr %7, align 4, !tbaa !9
  br label %14, !llvm.loop !11

26:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #5
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = call noundef zeroext i1 @_ZNK5sc_dt9sc_signed4signEv(ptr noundef nonnull align 8 dereferenceable(32) %27)
  %29 = zext i1 %28 to i8
  store i8 %29, ptr %8, align 1, !tbaa !13
  br label %30

30:                                               ; preds = %39, %26
  %31 = load i32, ptr %7, align 4, !tbaa !9
  %32 = getelementptr inbounds %"class.sc_dt::sc_int_base", ptr %9, i32 0, i32 2
  %33 = load i32, ptr %32, align 8, !tbaa !15
  %34 = icmp slt i32 %31, %33
  br i1 %34, label %35, label %42

35:                                               ; preds = %30
  %36 = load i32, ptr %7, align 4, !tbaa !9
  %37 = load i8, ptr %8, align 1, !tbaa !13, !range !19, !noundef !20
  %38 = trunc i8 %37 to i1
  call void @_ZN5sc_dt11sc_int_base3setEib(ptr noundef nonnull align 8 dereferenceable(24) %9, i32 noundef %36, i1 noundef zeroext %38)
  br label %39

39:                                               ; preds = %35
  %40 = load i32, ptr %7, align 4, !tbaa !9
  %41 = add nsw i32 %40, 1
  store i32 %41, ptr %7, align 4, !tbaa !9
  br label %30, !llvm.loop !21

42:                                               ; preds = %30
  call void @_ZN5sc_dt11sc_int_base11extend_signEv(ptr noundef nonnull align 8 dereferenceable(24) %9)
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  ret ptr %9
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt11sc_int_base11extend_signEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt11sc_int_base3setEib(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i1 noundef zeroext) #1 align 2

declare noundef zeroext i1 @_ZNK5sc_dt9sc_signed4testEi(ptr noundef nonnull align 8 dereferenceable(32), i32 noundef) #4

declare noundef zeroext i1 @_ZNK5sc_dt9sc_signed4signEv(ptr noundef nonnull align 8 dereferenceable(32)) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{!16, !10, i64 16}
!16 = !{!"_ZTSN5sc_dt11sc_int_baseE", !17, i64 0, !18, i64 8, !10, i64 16, !10, i64 20}
!17 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!18 = !{!"long long", !7, i64 0}
!19 = !{i8 0, i8 2}
!20 = !{}
!21 = distinct !{!21, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZN5sc_dt11sc_int_baseaSERKNS_9sc_signedE(ptr noundef nonnull returned align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(32) %1) local_unnamed_addr #2 align 2 {
  %3 = alloca i32, align 4
  %4 = getelementptr inbounds i8, ptr %0, i64 16
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #5
  %5 = tail call noundef i32 @_ZNK5sc_dt9sc_signed6lengthEv(ptr noundef nonnull align 8 dereferenceable(32) %1)
  store i32 %5, ptr %3, align 4, !tbaa !5
  %6 = call noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #5
  %7 = icmp sgt i32 %6, 0
  br i1 %7, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %2, %.lr.ph
  %.012 = phi i32 [ %9, %.lr.ph ], [ 0, %2 ]
  %8 = call noundef zeroext i1 @_ZNK5sc_dt9sc_signed4testEi(ptr noundef nonnull align 8 dereferenceable(32) %1, i32 noundef %.012)
  call void @_ZN5sc_dt11sc_int_base3setEib(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %.012, i1 noundef zeroext %8)
  %9 = add nuw nsw i32 %.012, 1
  %exitcond.not = icmp eq i32 %9, %6
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9

._crit_edge:                                      ; preds = %.lr.ph, %2
  %.0.lcssa = phi i32 [ 0, %2 ], [ %6, %.lr.ph ]
  %10 = call noundef zeroext i1 @_ZNK5sc_dt9sc_signed4signEv(ptr noundef nonnull align 8 dereferenceable(32) %1)
  %11 = load i32, ptr %4, align 8, !tbaa !11
  %12 = icmp slt i32 %.0.lcssa, %11
  br i1 %12, label %.lr.ph15, label %._crit_edge16

.lr.ph15:                                         ; preds = %._crit_edge, %.lr.ph15
  %.113 = phi i32 [ %13, %.lr.ph15 ], [ %.0.lcssa, %._crit_edge ]
  call void @_ZN5sc_dt11sc_int_base3setEib(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %.113, i1 noundef zeroext %10)
  %13 = add nuw nsw i32 %.113, 1
  %14 = load i32, ptr %4, align 8, !tbaa !11
  %15 = icmp slt i32 %13, %14
  br i1 %15, label %.lr.ph15, label %._crit_edge16, !llvm.loop !15

._crit_edge16:                                    ; preds = %.lr.ph15, %._crit_edge
  call void @_ZN5sc_dt11sc_int_base11extend_signEv(ptr noundef nonnull align 8 dereferenceable(24) %0)
  ret ptr %0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt11sc_int_base11extend_signEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt11sc_int_base3setEib(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i1 noundef zeroext) local_unnamed_addr #1 align 2

declare noundef zeroext i1 @_ZNK5sc_dt9sc_signed4testEi(ptr noundef nonnull align 8 dereferenceable(32), i32 noundef) local_unnamed_addr #4

declare noundef zeroext i1 @_ZNK5sc_dt9sc_signed4signEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #4

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !6, i64 16}
!12 = !{!"_ZTSN5sc_dt11sc_int_baseE", !13, i64 0, !14, i64 8, !6, i64 16, !6, i64 20}
!13 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!14 = !{!"long long", !7, i64 0}
!15 = distinct !{!15, !10}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass