; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/stars/star111004 (star111004)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }
%struct.io_controller_m = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_out", %"class.sc_core::sc_inout.20", %"class.sc_core::sc_out.28", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_out.38", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in.47", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_dt::sc_uint", %"class.sc_dt::sc_uint", %"class.sc_core::sc_signal.55" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.13", ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_inout.20" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.28" = type { %"class.sc_core::sc_inout.20" }
%"class.sc_core::sc_out.38" = type { %"class.sc_core::sc_inout.39" }
%"class.sc_core::sc_inout.39" = type { %"class.sc_core::sc_port.40", ptr, ptr, ptr }
%"class.sc_core::sc_port.40" = type { %"class.sc_core::sc_port_b.41" }
%"class.sc_core::sc_port_b.41" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.42" }
%"class.std::vector.42" = type { %"struct.std::_Vector_base.43" }
%"struct.std::_Vector_base.43" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.29" = type { %"class.sc_core::sc_inout.30" }
%"class.sc_core::sc_inout.30" = type { %"class.sc_core::sc_port.31", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.31" = type { %"class.sc_core::sc_port_b.32" }
%"class.sc_core::sc_port_b.32" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.33" }
%"class.std::vector.33" = type { %"struct.std::_Vector_base.34" }
%"struct.std::_Vector_base.34" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.47" = type { %"class.sc_core::sc_port.48", ptr, ptr }
%"class.sc_core::sc_port.48" = type { %"class.sc_core::sc_port_b.49" }
%"class.sc_core::sc_port_b.49" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.50" }
%"class.std::vector.50" = type { %"struct.std::_Vector_base.51" }
%"struct.std::_Vector_base.51" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_signal" = type { %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, %"class.sc_dt::sc_uint", i64, %"class.sc_dt::sc_uint" }
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }
%"class.sc_core::sc_signal.55" = type { %"class.sc_core::sc_signal_inout_if.56", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if.56" = type { %"class.sc_core::sc_signal_in_if.57", %"class.sc_core::sc_signal_write_if.58" }
%"class.sc_core::sc_signal_in_if.57" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if.58" = type { %"class.sc_core::sc_interface" }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m16read_from_memoryEN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_uint") align 8, ptr noundef nonnull align 8 dereferenceable(5288), ptr noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288), ptr noundef, ptr noundef) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15io_controller_m12control_readEv(ptr noundef nonnull align 8 dereferenceable(5288) %0) #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca %"class.sc_dt::sc_uint", align 8
  %5 = alloca %"class.sc_dt::sc_uint", align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca %"class.sc_dt::sc_uint", align 8
  %10 = alloca %"class.sc_dt::sc_uint", align 8
  %11 = alloca %"class.sc_dt::sc_uint", align 8
  %12 = alloca %"class.sc_dt::sc_uint", align 8
  %13 = alloca %"class.sc_dt::sc_uint", align 8
  %14 = alloca %"class.sc_dt::sc_uint", align 8
  %15 = alloca %"class.sc_dt::sc_uint", align 8
  %16 = alloca %"class.sc_dt::sc_uint", align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %17 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %18

18:                                               ; preds = %121, %1
  br label %19

19:                                               ; preds = %18
  br label %20

20:                                               ; preds = %21, %19
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %17)
  br label %21

21:                                               ; preds = %20
  %22 = getelementptr inbounds %struct.io_controller_m, ptr %17, i32 0, i32 23
  %23 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %22)
  %24 = load i8, ptr %23, align 1, !tbaa !11, !range !13, !noundef !14
  %25 = trunc i8 %24 to i1
  %26 = xor i1 %25, true
  br i1 %26, label %20, label %27, !llvm.loop !15

27:                                               ; preds = %21
  call void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
  call void @llvm.lifetime.start.p0(i64 24, ptr %4) #3
  %28 = getelementptr inbounds %struct.io_controller_m, ptr %17, i32 0, i32 26
  %29 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %28)
  %30 = load i32, ptr %3, align 4, !tbaa !9
  %31 = mul nsw i32 %30, 4
  %32 = sext i32 %31 to i64
  %33 = add i64 %29, %32
  call void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %33)
  invoke void @_ZN15io_controller_m16read_from_memoryEN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_uint") align 8 %4, ptr noundef nonnull align 8 dereferenceable(5288) %17, ptr noundef %5)
          to label %34 unwind label %40

34:                                               ; preds = %27
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %35 unwind label %44

35:                                               ; preds = %34
  %36 = load i32, ptr %3, align 4, !tbaa !9
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %3, align 4, !tbaa !9
  %38 = icmp eq i32 %37, 400
  br i1 %38, label %39, label %48

39:                                               ; preds = %35
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %48

40:                                               ; preds = %27
  %41 = landingpad { ptr, i32 }
          cleanup
  %42 = extractvalue { ptr, i32 } %41, 0
  store ptr %42, ptr %6, align 8
  %43 = extractvalue { ptr, i32 } %41, 1
  store i32 %43, ptr %7, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  br label %151

44:                                               ; preds = %34
  %45 = landingpad { ptr, i32 }
          cleanup
  %46 = extractvalue { ptr, i32 } %45, 0
  store ptr %46, ptr %6, align 8
  %47 = extractvalue { ptr, i32 } %45, 1
  store i32 %47, ptr %7, align 4
  br label %150

48:                                               ; preds = %39, %35
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %49

49:                                               ; preds = %79, %48
  %50 = load i32, ptr %8, align 4, !tbaa !9
  %51 = icmp slt i32 %50, 399
  br i1 %51, label %53, label %52

52:                                               ; preds = %49
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %101

53:                                               ; preds = %49
  call void @llvm.lifetime.start.p0(i64 24, ptr %9) #3
  %54 = getelementptr inbounds %struct.io_controller_m, ptr %17, i32 0, i32 19
  %55 = invoke noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core9sc_signalIN5sc_dt7sc_uintILi32EEELNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(232) %54)
          to label %56 unwind label %82

56:                                               ; preds = %53
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %9, ptr noundef nonnull align 8 dereferenceable(24) %55)
          to label %57 unwind label %82

57:                                               ; preds = %56
  invoke void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %58 unwind label %86

58:                                               ; preds = %57
  %59 = invoke noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %60 unwind label %86

60:                                               ; preds = %58
  %61 = load i32, ptr %8, align 4, !tbaa !9
  %62 = mul nsw i32 %61, 4
  %63 = sext i32 %62 to i64
  %64 = add i64 %59, %63
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %64)
          to label %65 unwind label %86

65:                                               ; preds = %60
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %11, ptr noundef nonnull align 8 dereferenceable(24) %9)
          to label %66 unwind label %90

66:                                               ; preds = %65
  invoke void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288) %17, ptr noundef %10, ptr noundef %11)
          to label %67 unwind label %94

67:                                               ; preds = %66
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %10) #3
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %68 unwind label %86

68:                                               ; preds = %67
  br label %69

69:                                               ; preds = %74, %68
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %17)
          to label %70 unwind label %86

70:                                               ; preds = %69
  br label %71

71:                                               ; preds = %70
  %72 = getelementptr inbounds %struct.io_controller_m, ptr %17, i32 0, i32 23
  %73 = invoke noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %72)
          to label %74 unwind label %86

74:                                               ; preds = %71
  %75 = load i8, ptr %73, align 1, !tbaa !11, !range !13, !noundef !14
  %76 = trunc i8 %75 to i1
  %77 = xor i1 %76, true
  br i1 %77, label %69, label %78, !llvm.loop !17

78:                                               ; preds = %74
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %9) #3
  br label %79

79:                                               ; preds = %78
  %80 = load i32, ptr %8, align 4, !tbaa !9
  %81 = add nsw i32 %80, 1
  store i32 %81, ptr %8, align 4, !tbaa !9
  br label %49, !llvm.loop !18

82:                                               ; preds = %56, %53
  %83 = landingpad { ptr, i32 }
          cleanup
  %84 = extractvalue { ptr, i32 } %83, 0
  store ptr %84, ptr %6, align 8
  %85 = extractvalue { ptr, i32 } %83, 1
  store i32 %85, ptr %7, align 4
  br label %100

86:                                               ; preds = %71, %69, %67, %60, %58, %57
  %87 = landingpad { ptr, i32 }
          cleanup
  %88 = extractvalue { ptr, i32 } %87, 0
  store ptr %88, ptr %6, align 8
  %89 = extractvalue { ptr, i32 } %87, 1
  store i32 %89, ptr %7, align 4
  br label %99

90:                                               ; preds = %65
  %91 = landingpad { ptr, i32 }
          cleanup
  %92 = extractvalue { ptr, i32 } %91, 0
  store ptr %92, ptr %6, align 8
  %93 = extractvalue { ptr, i32 } %91, 1
  store i32 %93, ptr %7, align 4
  br label %98

94:                                               ; preds = %66
  %95 = landingpad { ptr, i32 }
          cleanup
  %96 = extractvalue { ptr, i32 } %95, 0
  store ptr %96, ptr %6, align 8
  %97 = extractvalue { ptr, i32 } %95, 1
  store i32 %97, ptr %7, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #3
  br label %98

98:                                               ; preds = %94, %90
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %10) #3
  br label %99

99:                                               ; preds = %98, %86
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  br label %100

100:                                              ; preds = %99, %82
  call void @llvm.lifetime.end.p0(i64 24, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %150

101:                                              ; preds = %52
  call void @llvm.lifetime.start.p0(i64 24, ptr %12) #3
  %102 = getelementptr inbounds %struct.io_controller_m, ptr %17, i32 0, i32 19
  %103 = invoke noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core9sc_signalIN5sc_dt7sc_uintILi32EEELNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(232) %102)
          to label %104 unwind label %122

104:                                              ; preds = %101
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %12, ptr noundef nonnull align 8 dereferenceable(24) %103)
          to label %105 unwind label %122

105:                                              ; preds = %104
  invoke void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %106 unwind label %126

106:                                              ; preds = %105
  %107 = invoke noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %108 unwind label %126

108:                                              ; preds = %106
  %109 = add i64 %107, 1596
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %109)
          to label %110 unwind label %126

110:                                              ; preds = %108
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %14, ptr noundef nonnull align 8 dereferenceable(24) %12)
          to label %111 unwind label %130

111:                                              ; preds = %110
  invoke void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288) %17, ptr noundef %13, ptr noundef %14)
          to label %112 unwind label %134

112:                                              ; preds = %111
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %113 unwind label %126

113:                                              ; preds = %112
  invoke void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %114 unwind label %126

114:                                              ; preds = %113
  %115 = invoke noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %116 unwind label %126

116:                                              ; preds = %114
  %117 = add i64 %115, 1604
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %117)
          to label %118 unwind label %126

118:                                              ; preds = %116
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24) %16, i32 noundef -1)
          to label %119 unwind label %139

119:                                              ; preds = %118
  invoke void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288) %17, ptr noundef %15, ptr noundef %16)
          to label %120 unwind label %143

120:                                              ; preds = %119
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %16) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %17)
          to label %121 unwind label %126

121:                                              ; preds = %120
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %12) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %4) #3
  br label %18, !llvm.loop !19

122:                                              ; preds = %104, %101
  %123 = landingpad { ptr, i32 }
          cleanup
  %124 = extractvalue { ptr, i32 } %123, 0
  store ptr %124, ptr %6, align 8
  %125 = extractvalue { ptr, i32 } %123, 1
  store i32 %125, ptr %7, align 4
  br label %149

126:                                              ; preds = %120, %116, %114, %113, %112, %108, %106, %105
  %127 = landingpad { ptr, i32 }
          cleanup
  %128 = extractvalue { ptr, i32 } %127, 0
  store ptr %128, ptr %6, align 8
  %129 = extractvalue { ptr, i32 } %127, 1
  store i32 %129, ptr %7, align 4
  br label %148

130:                                              ; preds = %110
  %131 = landingpad { ptr, i32 }
          cleanup
  %132 = extractvalue { ptr, i32 } %131, 0
  store ptr %132, ptr %6, align 8
  %133 = extractvalue { ptr, i32 } %131, 1
  store i32 %133, ptr %7, align 4
  br label %138

134:                                              ; preds = %111
  %135 = landingpad { ptr, i32 }
          cleanup
  %136 = extractvalue { ptr, i32 } %135, 0
  store ptr %136, ptr %6, align 8
  %137 = extractvalue { ptr, i32 } %135, 1
  store i32 %137, ptr %7, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  br label %138

138:                                              ; preds = %134, %130
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  br label %148

139:                                              ; preds = %118
  %140 = landingpad { ptr, i32 }
          cleanup
  %141 = extractvalue { ptr, i32 } %140, 0
  store ptr %141, ptr %6, align 8
  %142 = extractvalue { ptr, i32 } %140, 1
  store i32 %142, ptr %7, align 4
  br label %147

143:                                              ; preds = %119
  %144 = landingpad { ptr, i32 }
          cleanup
  %145 = extractvalue { ptr, i32 } %144, 0
  store ptr %145, ptr %6, align 8
  %146 = extractvalue { ptr, i32 } %144, 1
  store i32 %146, ptr %7, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %16) #3
  br label %147

147:                                              ; preds = %143, %139
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  br label %148

148:                                              ; preds = %147, %138, %126
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  br label %149

149:                                              ; preds = %148, %122
  call void @llvm.lifetime.end.p0(i64 24, ptr %12) #3
  br label %150

150:                                              ; preds = %149, %100, %44
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  br label %151

151:                                              ; preds = %150, %40
  call void @llvm.lifetime.end.p0(i64 24, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %152

152:                                              ; preds = %151
  %153 = load ptr, ptr %6, align 8
  %154 = load i32, ptr %7, align 4
  %155 = insertvalue { ptr, i32 } poison, ptr %153, 0
  %156 = insertvalue { ptr, i32 } %155, i32 %154, 1
  resume { ptr, i32 } %156
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core9sc_signalIN5sc_dt7sc_uintILi32EEELNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(232)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}
!18 = distinct !{!18, !16}
!19 = distinct !{!19, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m16read_from_memoryEN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_uint") align 8, ptr noundef nonnull align 8 dereferenceable(5288), ptr noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288), ptr noundef, ptr noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN15io_controller_m12control_readEv(ptr noundef nonnull align 8 dereferenceable(5288) %0) local_unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca %"class.sc_dt::sc_uint", align 8
  %3 = alloca %"class.sc_dt::sc_uint", align 8
  %4 = alloca %"class.sc_dt::sc_uint", align 8
  %5 = alloca %"class.sc_dt::sc_uint", align 8
  %6 = alloca %"class.sc_dt::sc_uint", align 8
  %7 = alloca %"class.sc_dt::sc_uint", align 8
  %8 = alloca %"class.sc_dt::sc_uint", align 8
  %9 = alloca %"class.sc_dt::sc_uint", align 8
  %10 = alloca %"class.sc_dt::sc_uint", align 8
  %11 = alloca %"class.sc_dt::sc_uint", align 8
  %12 = getelementptr inbounds i8, ptr %0, i64 4568
  %13 = getelementptr inbounds i8, ptr %0, i64 5040
  %14 = getelementptr inbounds i8, ptr %0, i64 3664
  br label %15

15:                                               ; preds = %74, %1
  %.017 = phi i32 [ 0, %1 ], [ %spec.store.select, %74 ]
  br label %16

16:                                               ; preds = %16, %15
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %17 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %12)
  %18 = load i8, ptr %17, align 1, !tbaa !5, !range !9, !noundef !10
  %19 = trunc nuw i8 %18 to i1
  br i1 %19, label %20, label %16, !llvm.loop !11

20:                                               ; preds = %16
  call void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %2) #4
  %21 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %13)
  %22 = shl nsw i32 %.017, 2
  %23 = sext i32 %22 to i64
  %24 = add i64 %21, %23
  call void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %24)
  invoke void @_ZN15io_controller_m16read_from_memoryEN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_uint") align 8 %2, ptr noundef nonnull align 8 dereferenceable(5288) %0, ptr noundef nonnull %3)
          to label %25 unwind label %29

25:                                               ; preds = %20
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %26 unwind label %31

26:                                               ; preds = %25
  %27 = add nsw i32 %.017, 1
  %28 = icmp eq i32 %27, 400
  %spec.store.select = select i1 %28, i32 0, i32 %27
  br label %35

29:                                               ; preds = %20
  %30 = landingpad { ptr, i32 }
          cleanup
  br label %91

31:                                               ; preds = %25
  %32 = landingpad { ptr, i32 }
          cleanup
  br label %91

33:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %7) #4
  %34 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core9sc_signalIN5sc_dt7sc_uintILi32EEELNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(232) %14)
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %7, ptr noundef nonnull align 8 dereferenceable(24) %34)
          to label %60 unwind label %75

35:                                               ; preds = %26, %50
  %indvars.iv = phi i64 [ 0, %26 ], [ %indvars.iv.next, %50 ]
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %4) #4
  %36 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core9sc_signalIN5sc_dt7sc_uintILi32EEELNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(232) %14)
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %4, ptr noundef nonnull align 8 dereferenceable(24) %36)
          to label %37 unwind label %51

37:                                               ; preds = %35
  invoke void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %38 unwind label %.loopexit.split-lp

38:                                               ; preds = %37
  %39 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %40 = shl nuw nsw i64 %indvars.iv, 2
  %41 = add i64 %39, %40
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %41)
          to label %42 unwind label %.loopexit.split-lp

42:                                               ; preds = %38
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %43 unwind label %53

43:                                               ; preds = %42
  invoke void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288) %0, ptr noundef nonnull %5, ptr noundef nonnull %6)
          to label %44 unwind label %55

44:                                               ; preds = %43
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #4
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %.preheader unwind label %.loopexit.split-lp

.preheader:                                       ; preds = %44, %47
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %45 unwind label %.loopexit

45:                                               ; preds = %.preheader
  %46 = invoke noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %12)
          to label %47 unwind label %.loopexit

47:                                               ; preds = %45
  %48 = load i8, ptr %46, align 1, !tbaa !5, !range !9, !noundef !10
  %49 = trunc nuw i8 %48 to i1
  br i1 %49, label %50, label %.preheader, !llvm.loop !13

50:                                               ; preds = %47
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %4) #4
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 399
  br i1 %exitcond.not, label %33, label %35, !llvm.loop !14

51:                                               ; preds = %35
  %52 = landingpad { ptr, i32 }
          cleanup
  br label %59

.loopexit:                                        ; preds = %.preheader, %45
  %lpad.loopexit = landingpad { ptr, i32 }
          cleanup
  br label %58

.loopexit.split-lp:                               ; preds = %37, %38, %44
  %lpad.loopexit.split-lp = landingpad { ptr, i32 }
          cleanup
  br label %58

53:                                               ; preds = %42
  %54 = landingpad { ptr, i32 }
          cleanup
  br label %57

55:                                               ; preds = %43
  %56 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #4
  br label %57

57:                                               ; preds = %55, %53
  %.pn24 = phi { ptr, i32 } [ %56, %55 ], [ %54, %53 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #4
  br label %58

58:                                               ; preds = %.loopexit, %.loopexit.split-lp, %57
  %.pn26 = phi { ptr, i32 } [ %.pn24, %57 ], [ %lpad.loopexit, %.loopexit ], [ %lpad.loopexit.split-lp, %.loopexit.split-lp ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  br label %59

59:                                               ; preds = %58, %51
  %.pn26.pn = phi { ptr, i32 } [ %.pn26, %58 ], [ %52, %51 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %4) #4
  br label %91

60:                                               ; preds = %33
  invoke void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %61 unwind label %77

61:                                               ; preds = %60
  %62 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %63 = add i64 %62, 1596
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %63)
          to label %64 unwind label %77

64:                                               ; preds = %61
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %9, ptr noundef nonnull align 8 dereferenceable(24) %7)
          to label %65 unwind label %79

65:                                               ; preds = %64
  invoke void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288) %0, ptr noundef nonnull %8, ptr noundef nonnull %9)
          to label %66 unwind label %81

66:                                               ; preds = %65
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %67 unwind label %77

67:                                               ; preds = %66
  invoke void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %68 unwind label %77

68:                                               ; preds = %67
  %69 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %70 = add i64 %69, 1604
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %70)
          to label %71 unwind label %77

71:                                               ; preds = %68
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24) %11, i32 noundef -1)
          to label %72 unwind label %84

72:                                               ; preds = %71
  invoke void @_ZN15io_controller_m17write_into_memoryEN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(5288) %0, ptr noundef nonnull %10, ptr noundef nonnull %11)
          to label %73 unwind label %86

73:                                               ; preds = %72
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %10) #4
  invoke void @_ZN15io_controller_m1VEv(ptr noundef nonnull align 8 dereferenceable(5288) %0)
          to label %74 unwind label %77

74:                                               ; preds = %73
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %7) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #4
  br label %15, !llvm.loop !15

75:                                               ; preds = %33
  %76 = landingpad { ptr, i32 }
          cleanup
  br label %90

77:                                               ; preds = %73, %68, %67, %66, %61, %60
  %78 = landingpad { ptr, i32 }
          cleanup
  br label %89

79:                                               ; preds = %64
  %80 = landingpad { ptr, i32 }
          cleanup
  br label %83

81:                                               ; preds = %65
  %82 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  br label %83

83:                                               ; preds = %81, %79
  %.pn = phi { ptr, i32 } [ %82, %81 ], [ %80, %79 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  br label %89

84:                                               ; preds = %71
  %85 = landingpad { ptr, i32 }
          cleanup
  br label %88

86:                                               ; preds = %72
  %87 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #4
  br label %88

88:                                               ; preds = %86, %84
  %.pn19 = phi { ptr, i32 } [ %87, %86 ], [ %85, %84 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %10) #4
  br label %89

89:                                               ; preds = %88, %83, %77
  %.pn21 = phi { ptr, i32 } [ %78, %77 ], [ %.pn19, %88 ], [ %.pn, %83 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #4
  br label %90

90:                                               ; preds = %89, %75
  %.pn21.pn = phi { ptr, i32 } [ %.pn21, %89 ], [ %76, %75 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %7) #4
  br label %91

91:                                               ; preds = %31, %59, %90, %29
  %.sink = phi ptr [ %3, %29 ], [ %2, %90 ], [ %2, %59 ], [ %2, %31 ]
  %.pn26.pn.pn.pn = phi { ptr, i32 } [ %30, %29 ], [ %.pn21.pn, %90 ], [ %.pn26.pn, %59 ], [ %32, %31 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %.sink) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #4
  resume { ptr, i32 } %.pn26.pn.pn.pn
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core9sc_signalIN5sc_dt7sc_uintILi32EEELNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(232)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass