; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_port)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector.5", %"class.std::vector.10", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

@_ZTVN7sc_core12sc_port_baseE = external dso_local unnamed_addr constant { [30 x ptr] }, align 8

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #0

declare void @_ZN7sc_core9sc_objectC2EPKc(ptr noundef nonnull align 8 dereferenceable(112), ptr noundef) unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext17get_port_registryEv(ptr noundef nonnull align 8 dereferenceable(344)) #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core16sc_port_registry6insertEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef) #4 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #5

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112)) unnamed_addr #6

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_port_baseC2EPKciNS_14sc_port_policyE(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) unnamed_addr #4 align 2 personality ptr @__gxx_personality_v0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !11
  %11 = load ptr, ptr %5, align 8
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_ZN7sc_core9sc_objectC2EPKc(ptr noundef nonnull align 8 dereferenceable(112) %11, ptr noundef %12)
  store ptr getelementptr inbounds inrange(-16, 224) ({ [30 x ptr] }, ptr @_ZTVN7sc_core12sc_port_baseE, i32 0, i32 0, i32 2), ptr %11, align 8, !tbaa !13
  %13 = getelementptr inbounds %"class.sc_core::sc_port_base", ptr %11, i32 0, i32 1
  store ptr null, ptr %13, align 8, !tbaa !15
  %14 = invoke noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %11)
          to label %15 unwind label %25

15:                                               ; preds = %4
  %16 = invoke noundef ptr @_ZN7sc_core13sc_simcontext17get_port_registryEv(ptr noundef nonnull align 8 dereferenceable(344) %14)
          to label %17 unwind label %25

17:                                               ; preds = %15
  invoke void @_ZN7sc_core16sc_port_registry6insertEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(40) %16, ptr noundef %11)
          to label %18 unwind label %25

18:                                               ; preds = %17
  %19 = invoke noalias noundef nonnull ptr @_Znwm(i64 noundef 96) #7
          to label %20 unwind label %25

20:                                               ; preds = %18
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = load i32, ptr %8, align 4, !tbaa !11
  invoke void @_ZN7sc_core12sc_bind_infoC1EiNS_14sc_port_policyE(ptr noundef nonnull align 8 dereferenceable(96) %19, i32 noundef %21, i32 noundef %22)
          to label %23 unwind label %29

23:                                               ; preds = %20
  %24 = getelementptr inbounds %"class.sc_core::sc_port_base", ptr %11, i32 0, i32 1
  store ptr %19, ptr %24, align 8, !tbaa !15
  ret void

25:                                               ; preds = %18, %17, %15, %4
  %26 = landingpad { ptr, i32 }
          cleanup
  %27 = extractvalue { ptr, i32 } %26, 0
  store ptr %27, ptr %9, align 8
  %28 = extractvalue { ptr, i32 } %26, 1
  store i32 %28, ptr %10, align 4
  br label %33

29:                                               ; preds = %20
  %30 = landingpad { ptr, i32 }
          cleanup
  %31 = extractvalue { ptr, i32 } %30, 0
  store ptr %31, ptr %9, align 8
  %32 = extractvalue { ptr, i32 } %30, 1
  store i32 %32, ptr %10, align 4
  call void @_ZdlPvm(ptr noundef %19, i64 noundef 96) #8
  br label %33

33:                                               ; preds = %29, %25
  call void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112) %11) #9
  br label %34

34:                                               ; preds = %33
  %35 = load ptr, ptr %9, align 8
  %36 = load i32, ptr %10, align 4
  %37 = insertvalue { ptr, i32 } poison, ptr %35, 0
  %38 = insertvalue { ptr, i32 } %37, i32 %36, 1
  resume { ptr, i32 } %38
}

declare void @_ZN7sc_core12sc_bind_infoC1EiNS_14sc_port_policyE(ptr, i32, i32)

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }
attributes #9 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTSN7sc_core14sc_port_policyE", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"vtable pointer", !8, i64 0}
!15 = !{!16, !6, i64 112}
!16 = !{!"_ZTSN7sc_core12sc_port_baseE", !17, i64 0, !6, i64 112}
!17 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !18, i64 16, !22, i64 40, !26, i64 64, !6, i64 96, !6, i64 104}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !27, i64 0, !28, i64 8, !7, i64 16}
!27 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!28 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN7sc_core12sc_port_baseE = external dso_local unnamed_addr constant { [30 x ptr] }, align 8

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #0

declare void @_ZN7sc_core9sc_objectC2EPKc(ptr noundef nonnull align 8 dereferenceable(112), ptr noundef) unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext17get_port_registryEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core16sc_port_registry6insertEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef) local_unnamed_addr #4 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #5

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112)) unnamed_addr #6

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_port_baseC2EPKciNS_14sc_port_policyE(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) unnamed_addr #4 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN7sc_core9sc_objectC2EPKc(ptr noundef nonnull align 8 dereferenceable(112) %0, ptr noundef %1)
  store ptr getelementptr inbounds inrange(-16, 224) (i8, ptr @_ZTVN7sc_core12sc_port_baseE, i64 16), ptr %0, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr null, ptr %5, align 8, !tbaa !8
  %6 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  %7 = tail call noundef ptr @_ZN7sc_core13sc_simcontext17get_port_registryEv(ptr noundef nonnull align 8 dereferenceable(344) %6)
  invoke void @_ZN7sc_core16sc_port_registry6insertEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(40) %7, ptr noundef nonnull %0)
          to label %8 unwind label %12

8:                                                ; preds = %4
  %9 = invoke noalias noundef nonnull dereferenceable(96) ptr @_Znwm(i64 noundef 96) #7
          to label %10 unwind label %12

10:                                               ; preds = %8
  invoke void @_ZN7sc_core12sc_bind_infoC1EiNS_14sc_port_policyE(ptr noundef nonnull align 8 dereferenceable(96) %9, i32 noundef %2, i32 noundef %3)
          to label %11 unwind label %14

11:                                               ; preds = %10
  store ptr %9, ptr %5, align 8, !tbaa !8
  ret void

12:                                               ; preds = %8, %4
  %13 = landingpad { ptr, i32 }
          cleanup
  br label %16

14:                                               ; preds = %10
  %15 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %9, i64 noundef 96) #8
  br label %16

16:                                               ; preds = %14, %12
  %.pn = phi { ptr, i32 } [ %15, %14 ], [ %13, %12 ]
  tail call void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112) %0) #9
  resume { ptr, i32 } %.pn
}

declare void @_ZN7sc_core12sc_bind_infoC1EiNS_14sc_port_policyE(ptr, i32, i32) local_unnamed_addr

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }
attributes #9 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !11, i64 112}
!9 = !{!"_ZTSN7sc_core12sc_port_baseE", !10, i64 0, !11, i64 112}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !12, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!23 = !{!"long", !12, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass