; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_simcontext)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_process_b" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.8", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.13", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8, [3 x i8] }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core34SC_ID_DISABLE_WILL_ORPHAN_PROCESS_E = external constant [0 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core17sc_method_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(400)) #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core17sc_thread_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(404)) #1 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344)) #4 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext19prepare_to_simulateEv(ptr noundef nonnull align 8 dereferenceable(344) %0) #4 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %11 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #8
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #8
  %12 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 29
  %13 = load i8, ptr %12, align 2, !tbaa !9, !range !35, !noundef !36
  %14 = trunc i8 %13 to i1
  br i1 %14, label %18, label %15

15:                                               ; preds = %1
  %16 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %11)
  %17 = icmp ne i32 %16, 0
  br i1 %17, label %18, label %19

18:                                               ; preds = %15, %1
  store i32 1, ptr %5, align 4
  br label %180

19:                                               ; preds = %15
  %20 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 16) #9
  invoke void @_ZN7sc_core13sc_cor_pkg_qtC1EPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(16) %20, ptr noundef %11)
          to label %21 unwind label %44

21:                                               ; preds = %19
  %22 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 37
  store ptr %20, ptr %22, align 8, !tbaa !37
  %23 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 37
  %24 = load ptr, ptr %23, align 8, !tbaa !37
  %25 = load ptr, ptr %24, align 8, !tbaa !38
  %26 = getelementptr inbounds ptr, ptr %25, i64 5
  %27 = load ptr, ptr %26, align 8
  %28 = call noundef ptr %27(ptr noundef nonnull align 8 dereferenceable(16) %24)
  %29 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 38
  store ptr %28, ptr %29, align 8, !tbaa !40
  %30 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 35
  store i32 8, ptr %30, align 4, !tbaa !41
  %31 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 2
  %32 = load ptr, ptr %31, align 8, !tbaa !42
  call void @_ZN7sc_core16sc_port_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40) %32)
  %33 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 3
  %34 = load ptr, ptr %33, align 8, !tbaa !43
  call void @_ZN7sc_core18sc_export_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40) %34)
  %35 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 4
  %36 = load ptr, ptr %35, align 8, !tbaa !44
  call void @_ZN7sc_core24sc_prim_channel_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(56) %36)
  %37 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 1
  %38 = load ptr, ptr %37, align 8, !tbaa !45
  call void @_ZN7sc_core18sc_module_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40) %38)
  %39 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 36
  store i8 1, ptr %39, align 8, !tbaa !46
  %40 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 27
  %41 = load i8, ptr %40, align 8, !tbaa !47, !range !35, !noundef !36
  %42 = trunc i8 %41 to i1
  br i1 %42, label %43, label %48

43:                                               ; preds = %21
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %11)
  store i32 1, ptr %5, align 4
  br label %180

44:                                               ; preds = %19
  %45 = landingpad { ptr, i32 }
          cleanup
  %46 = extractvalue { ptr, i32 } %45, 0
  store ptr %46, ptr %6, align 8
  %47 = extractvalue { ptr, i32 } %45, 1
  store i32 %47, ptr %7, align 4
  call void @_ZdlPvm(ptr noundef %20, i64 noundef 16) #10
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #8
  br label %183

48:                                               ; preds = %21
  %49 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 7
  %50 = load ptr, ptr %49, align 8, !tbaa !48
  %51 = call noundef ptr @_ZN7sc_core16sc_process_table13thread_q_headEv(ptr noundef nonnull align 8 dereferenceable(16) %50)
  store ptr %51, ptr %4, align 8, !tbaa !5
  br label %52

52:                                               ; preds = %60, %48
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  %54 = icmp ne ptr %53, null
  br i1 %54, label %55, label %63

55:                                               ; preds = %52
  %56 = load ptr, ptr %4, align 8, !tbaa !5
  %57 = load ptr, ptr %56, align 8, !tbaa !38
  %58 = getelementptr inbounds ptr, ptr %57, i64 24
  %59 = load ptr, ptr %58, align 8
  call void %59(ptr noundef nonnull align 8 dereferenceable(404) %56)
  br label %60

60:                                               ; preds = %55
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  %62 = call noundef ptr @_ZN7sc_core17sc_thread_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(404) %61)
  store ptr %62, ptr %4, align 8, !tbaa !5
  br label %52, !llvm.loop !49

63:                                               ; preds = %52
  %64 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 35
  store i32 16, ptr %64, align 4, !tbaa !41
  %65 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 29
  store i8 1, ptr %65, align 2, !tbaa !9
  %66 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 19
  %67 = load ptr, ptr %66, align 8, !tbaa !51
  call void @_ZN7sc_core11sc_runnable4initEv(ptr noundef nonnull align 8 dereferenceable(48) %67)
  %68 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 31
  store i32 2, ptr %68, align 4, !tbaa !52
  %69 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 4
  %70 = load ptr, ptr %69, align 8, !tbaa !44
  call void @_ZN7sc_core24sc_prim_channel_registry14perform_updateEv(ptr noundef nonnull align 8 dereferenceable(56) %70)
  %71 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 31
  store i32 3, ptr %71, align 4, !tbaa !52
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #8
  %72 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 7
  %73 = load ptr, ptr %72, align 8, !tbaa !48
  %74 = call noundef ptr @_ZN7sc_core16sc_process_table13method_q_headEv(ptr noundef nonnull align 8 dereferenceable(16) %73)
  store ptr %74, ptr %3, align 8, !tbaa !5
  br label %75

75:                                               ; preds = %111, %63
  %76 = load ptr, ptr %3, align 8, !tbaa !5
  %77 = icmp ne ptr %76, null
  br i1 %77, label %78, label %114

78:                                               ; preds = %75
  %79 = load ptr, ptr %3, align 8, !tbaa !5
  %80 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %79, i32 0, i32 29
  %81 = load i32, ptr %80, align 8, !tbaa !53
  %82 = and i32 %81, 1
  %83 = icmp ne i32 %82, 0
  br i1 %83, label %87, label %84

84:                                               ; preds = %78
  %85 = load ptr, ptr %3, align 8, !tbaa !5
  %86 = call noundef zeroext i1 @_ZNK7sc_core12sc_process_b15dont_initializeEv(ptr noundef nonnull align 8 dereferenceable(357) %85)
  br i1 %86, label %87, label %96

87:                                               ; preds = %84, %78
  %88 = load ptr, ptr %3, align 8, !tbaa !5
  %89 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %88, i32 0, i32 31
  %90 = call noundef i64 @_ZNKSt6vectorIPKN7sc_core8sc_eventESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %89) #8
  %91 = icmp eq i64 %90, 0
  br i1 %91, label %92, label %95

92:                                               ; preds = %87
  %93 = load ptr, ptr %3, align 8, !tbaa !5
  %94 = call noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112) %93)
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef @_ZN7sc_core34SC_ID_DISABLE_WILL_ORPHAN_PROCESS_E, ptr noundef %94, ptr noundef @.str.7, i32 noundef 784)
  br label %95

95:                                               ; preds = %92, %87
  br label %110

96:                                               ; preds = %84
  %97 = load ptr, ptr %3, align 8, !tbaa !5
  %98 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %97, i32 0, i32 29
  %99 = load i32, ptr %98, align 8, !tbaa !53
  %100 = and i32 %99, 4
  %101 = icmp eq i32 %100, 0
  br i1 %101, label %102, label %104

102:                                              ; preds = %96
  %103 = load ptr, ptr %3, align 8, !tbaa !5
  call void @_ZN7sc_core13sc_simcontext26push_runnable_method_frontEPNS_17sc_method_processE(ptr noundef nonnull align 8 dereferenceable(344) %11, ptr noundef %103)
  br label %109

104:                                              ; preds = %96
  %105 = load ptr, ptr %3, align 8, !tbaa !5
  %106 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %105, i32 0, i32 29
  %107 = load i32, ptr %106, align 8, !tbaa !53
  %108 = or i32 %107, 2
  store i32 %108, ptr %106, align 8, !tbaa !53
  br label %109

109:                                              ; preds = %104, %102
  br label %110

110:                                              ; preds = %109, %95
  br label %111

111:                                              ; preds = %110
  %112 = load ptr, ptr %3, align 8, !tbaa !5
  %113 = call noundef ptr @_ZN7sc_core17sc_method_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(400) %112)
  store ptr %113, ptr %3, align 8, !tbaa !5
  br label %75, !llvm.loop !69

114:                                              ; preds = %75
  %115 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 7
  %116 = load ptr, ptr %115, align 8, !tbaa !48
  %117 = call noundef ptr @_ZN7sc_core16sc_process_table13thread_q_headEv(ptr noundef nonnull align 8 dereferenceable(16) %116)
  store ptr %117, ptr %4, align 8, !tbaa !5
  br label %118

118:                                              ; preds = %154, %114
  %119 = load ptr, ptr %4, align 8, !tbaa !5
  %120 = icmp ne ptr %119, null
  br i1 %120, label %121, label %157

121:                                              ; preds = %118
  %122 = load ptr, ptr %4, align 8, !tbaa !5
  %123 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %122, i32 0, i32 29
  %124 = load i32, ptr %123, align 8, !tbaa !53
  %125 = and i32 %124, 1
  %126 = icmp ne i32 %125, 0
  br i1 %126, label %130, label %127

127:                                              ; preds = %121
  %128 = load ptr, ptr %4, align 8, !tbaa !5
  %129 = call noundef zeroext i1 @_ZNK7sc_core12sc_process_b15dont_initializeEv(ptr noundef nonnull align 8 dereferenceable(357) %128)
  br i1 %129, label %130, label %139

130:                                              ; preds = %127, %121
  %131 = load ptr, ptr %4, align 8, !tbaa !5
  %132 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %131, i32 0, i32 31
  %133 = call noundef i64 @_ZNKSt6vectorIPKN7sc_core8sc_eventESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %132) #8
  %134 = icmp eq i64 %133, 0
  br i1 %134, label %135, label %138

135:                                              ; preds = %130
  %136 = load ptr, ptr %4, align 8, !tbaa !5
  %137 = call noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112) %136)
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef @_ZN7sc_core34SC_ID_DISABLE_WILL_ORPHAN_PROCESS_E, ptr noundef %137, ptr noundef @.str.7, i32 noundef 809)
  br label %138

138:                                              ; preds = %135, %130
  br label %153

139:                                              ; preds = %127
  %140 = load ptr, ptr %4, align 8, !tbaa !5
  %141 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %140, i32 0, i32 29
  %142 = load i32, ptr %141, align 8, !tbaa !53
  %143 = and i32 %142, 4
  %144 = icmp eq i32 %143, 0
  br i1 %144, label %145, label %147

145:                                              ; preds = %139
  %146 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN7sc_core13sc_simcontext26push_runnable_thread_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %11, ptr noundef %146)
  br label %152

147:                                              ; preds = %139
  %148 = load ptr, ptr %4, align 8, !tbaa !5
  %149 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %148, i32 0, i32 29
  %150 = load i32, ptr %149, align 8, !tbaa !53
  %151 = or i32 %150, 2
  store i32 %151, ptr %149, align 8, !tbaa !53
  br label %152

152:                                              ; preds = %147, %145
  br label %153

153:                                              ; preds = %152, %138
  br label %154

154:                                              ; preds = %153
  %155 = load ptr, ptr %4, align 8, !tbaa !5
  %156 = call noundef ptr @_ZN7sc_core17sc_thread_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(404) %155)
  store ptr %156, ptr %4, align 8, !tbaa !5
  br label %118, !llvm.loop !70

157:                                              ; preds = %118
  %158 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 15
  %159 = call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %158) #8
  %160 = trunc i64 %159 to i32
  store i32 %160, ptr %8, align 4, !tbaa !71
  %161 = icmp ne i32 %160, 0
  br i1 %161, label %162, label %179

162:                                              ; preds = %157
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #8
  %163 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 15
  %164 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %163, i64 noundef 0) #8
  store ptr %164, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #8
  %165 = load i32, ptr %8, align 4, !tbaa !71
  %166 = sub nsw i32 %165, 1
  store i32 %166, ptr %10, align 4, !tbaa !71
  br label %167

167:                                              ; preds = %173, %162
  %168 = load ptr, ptr %9, align 8, !tbaa !5
  %169 = load i32, ptr %10, align 4, !tbaa !71
  %170 = sext i32 %169 to i64
  %171 = getelementptr inbounds ptr, ptr %168, i64 %170
  %172 = load ptr, ptr %171, align 8, !tbaa !5
  call void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160) %172)
  br label %173

173:                                              ; preds = %167
  %174 = load i32, ptr %10, align 4, !tbaa !71
  %175 = add nsw i32 %174, -1
  store i32 %175, ptr %10, align 4, !tbaa !71
  %176 = icmp sge i32 %175, 0
  br i1 %176, label %167, label %177, !llvm.loop !72

177:                                              ; preds = %173
  %178 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %11, i32 0, i32 15
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %178, i64 noundef 0)
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #8
  br label %179

179:                                              ; preds = %177, %157
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #8
  store i32 0, ptr %5, align 4
  br label %180

180:                                              ; preds = %179, %43, %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #8
  %181 = load i32, ptr %5, align 4
  switch i32 %181, label %188 [
    i32 0, label %182
    i32 1, label %182
  ]

182:                                              ; preds = %180, %180
  ret void

183:                                              ; preds = %44
  %184 = load ptr, ptr %6, align 8
  %185 = load i32, ptr %7, align 4
  %186 = insertvalue { ptr, i32 } poison, ptr %184, 0
  %187 = insertvalue { ptr, i32 } %186, i32 %185, 1
  resume { ptr, i32 } %187

188:                                              ; preds = %180
  unreachable
}

declare void @_ZN7sc_core13sc_cor_pkg_qtC1EPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef) unnamed_addr #5

declare void @_ZN7sc_core16sc_port_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare void @_ZN7sc_core18sc_export_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare void @_ZN7sc_core24sc_prim_channel_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(56)) #5

declare void @_ZN7sc_core18sc_module_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core16sc_process_table13thread_q_headEv(ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core11sc_runnable4initEv(ptr noundef nonnull align 8 dereferenceable(48)) #6 align 2

declare void @_ZN7sc_core24sc_prim_channel_registry14perform_updateEv(ptr noundef nonnull align 8 dereferenceable(56)) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core16sc_process_table13method_q_headEv(ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core12sc_process_b15dont_initializeEv(ptr noundef nonnull align 8 dereferenceable(357)) #7 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPKN7sc_core8sc_eventESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #7 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #5

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112)) #7 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext26push_runnable_method_frontEPNS_17sc_method_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #6 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext26push_runnable_thread_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #6 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #7 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #7 align 2

declare void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160)) #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { builtin allocsize(0) }
attributes #10 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 298}
!10 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !11, i64 64, !6, i64 80, !13, i64 88, !14, i64 92, !15, i64 96, !19, i64 120, !23, i64 144, !19, i64 168, !6, i64 192, !27, i64 200, !13, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !31, i64 256, !31, i64 264, !6, i64 272, !32, i64 280, !32, i64 288, !13, i64 296, !13, i64 297, !13, i64 298, !13, i64 299, !33, i64 300, !6, i64 304, !13, i64 312, !13, i64 313, !34, i64 316, !13, i64 320, !6, i64 328, !6, i64 336}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !12, i64 8}
!12 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core7sc_timeE", !32, i64 0}
!32 = !{!"long long", !7, i64 0}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!35 = !{i8 0, i8 2}
!36 = !{}
!37 = !{!10, !6, i64 328}
!38 = !{!39, !39, i64 0}
!39 = !{!"vtable pointer", !8, i64 0}
!40 = !{!10, !6, i64 336}
!41 = !{!10, !34, i64 316}
!42 = !{!10, !6, i64 16}
!43 = !{!10, !6, i64 24}
!44 = !{!10, !6, i64 32}
!45 = !{!10, !6, i64 8}
!46 = !{!10, !13, i64 320}
!47 = !{!10, !13, i64 296}
!48 = !{!10, !6, i64 56}
!49 = distinct !{!49, !50}
!50 = !{!"llvm.loop.mustprogress"}
!51 = !{!10, !6, i64 232}
!52 = !{!10, !33, i64 300}
!53 = !{!54, !14, i64 280}
!54 = !{!"_ZTSN7sc_core12sc_process_bE", !55, i64 0, !6, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !14, i64 132, !13, i64 136, !13, i64 137, !6, i64 144, !14, i64 152, !6, i64 160, !6, i64 168, !13, i64 176, !13, i64 177, !13, i64 178, !13, i64 179, !6, i64 184, !6, i64 192, !12, i64 200, !14, i64 204, !59, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !14, i64 280, !63, i64 288, !13, i64 312, !6, i64 320, !6, i64 328, !67, i64 336, !13, i64 340, !6, i64 344, !68, i64 352, !13, i64 356}
!55 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !19, i64 16, !23, i64 40, !56, i64 64, !6, i64 96, !6, i64 104}
!56 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !57, i64 0, !58, i64 8, !7, i64 16}
!57 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!58 = !{!"long", !7, i64 0}
!59 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !60, i64 0}
!60 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !61, i64 0}
!61 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !62, i64 0}
!62 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!63 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !64, i64 0}
!64 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !65, i64 0}
!65 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !66, i64 0}
!66 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!67 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!68 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!69 = distinct !{!69, !50}
!70 = distinct !{!70, !50}
!71 = !{!14, !14, i64 0}
!72 = distinct !{!72, !50}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core34SC_ID_DISABLE_WILL_ORPHAN_PROCESS_E = external constant [0 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core17sc_method_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(400)) local_unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core17sc_thread_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(404)) local_unnamed_addr #0 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #1

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext19prepare_to_simulateEv(ptr noundef nonnull align 8 dereferenceable(344) %0) local_unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 298
  %3 = load i8, ptr %2, align 2, !tbaa !5, !range !34, !noundef !35
  %4 = trunc nuw i8 %3 to i1
  br i1 %4, label %99, label %5

5:                                                ; preds = %1
  %6 = tail call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  %.not = icmp eq i32 %6, 0
  br i1 %.not, label %7, label %99

7:                                                ; preds = %5
  %8 = tail call noalias noundef nonnull dereferenceable(16) ptr @_Znwm(i64 noundef 16) #7
  invoke void @_ZN7sc_core13sc_cor_pkg_qtC1EPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(16) %8, ptr noundef nonnull %0)
          to label %9 unwind label %30

9:                                                ; preds = %7
  %10 = getelementptr inbounds i8, ptr %0, i64 328
  store ptr %8, ptr %10, align 8, !tbaa !36
  %11 = load ptr, ptr %8, align 8, !tbaa !37
  %12 = getelementptr inbounds i8, ptr %11, i64 40
  %13 = load ptr, ptr %12, align 8
  %14 = tail call noundef ptr %13(ptr noundef nonnull align 8 dereferenceable(16) %8)
  %15 = getelementptr inbounds i8, ptr %0, i64 336
  store ptr %14, ptr %15, align 8, !tbaa !39
  %16 = getelementptr inbounds i8, ptr %0, i64 316
  store i32 8, ptr %16, align 4, !tbaa !40
  %17 = getelementptr inbounds i8, ptr %0, i64 16
  %18 = load ptr, ptr %17, align 8, !tbaa !41
  tail call void @_ZN7sc_core16sc_port_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40) %18)
  %19 = getelementptr inbounds i8, ptr %0, i64 24
  %20 = load ptr, ptr %19, align 8, !tbaa !42
  tail call void @_ZN7sc_core18sc_export_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40) %20)
  %21 = getelementptr inbounds i8, ptr %0, i64 32
  %22 = load ptr, ptr %21, align 8, !tbaa !43
  tail call void @_ZN7sc_core24sc_prim_channel_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(56) %22)
  %23 = getelementptr inbounds i8, ptr %0, i64 8
  %24 = load ptr, ptr %23, align 8, !tbaa !44
  tail call void @_ZN7sc_core18sc_module_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40) %24)
  %25 = getelementptr inbounds i8, ptr %0, i64 320
  store i8 1, ptr %25, align 8, !tbaa !45
  %26 = getelementptr inbounds i8, ptr %0, i64 296
  %27 = load i8, ptr %26, align 8, !tbaa !46, !range !34, !noundef !35
  %28 = trunc nuw i8 %27 to i1
  br i1 %28, label %29, label %32

29:                                               ; preds = %9
  tail call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  br label %99

30:                                               ; preds = %7
  %31 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %8, i64 noundef 16) #8
  resume { ptr, i32 } %31

32:                                               ; preds = %9
  %33 = getelementptr inbounds i8, ptr %0, i64 56
  %34 = load ptr, ptr %33, align 8, !tbaa !47
  %35 = tail call noundef ptr @_ZN7sc_core16sc_process_table13thread_q_headEv(ptr noundef nonnull align 8 dereferenceable(16) %34)
  %.not3036 = icmp eq ptr %35, null
  br i1 %.not3036, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %32, %.lr.ph
  %.02837 = phi ptr [ %39, %.lr.ph ], [ %35, %32 ]
  %36 = load ptr, ptr %.02837, align 8, !tbaa !37
  %37 = getelementptr inbounds i8, ptr %36, i64 192
  %38 = load ptr, ptr %37, align 8
  tail call void %38(ptr noundef nonnull align 8 dereferenceable(404) %.02837)
  %39 = tail call noundef ptr @_ZN7sc_core17sc_thread_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(404) %.02837)
  %.not30 = icmp eq ptr %39, null
  br i1 %.not30, label %._crit_edge, label %.lr.ph, !llvm.loop !48

._crit_edge:                                      ; preds = %.lr.ph, %32
  store i32 16, ptr %16, align 4, !tbaa !40
  store i8 1, ptr %2, align 2, !tbaa !5
  %40 = getelementptr inbounds i8, ptr %0, i64 232
  %41 = load ptr, ptr %40, align 8, !tbaa !50
  tail call void @_ZN7sc_core11sc_runnable4initEv(ptr noundef nonnull align 8 dereferenceable(48) %41)
  %42 = getelementptr inbounds i8, ptr %0, i64 300
  store i32 2, ptr %42, align 4, !tbaa !51
  %43 = load ptr, ptr %21, align 8, !tbaa !43
  tail call void @_ZN7sc_core24sc_prim_channel_registry14perform_updateEv(ptr noundef nonnull align 8 dereferenceable(56) %43)
  store i32 3, ptr %42, align 4, !tbaa !51
  %44 = load ptr, ptr %33, align 8, !tbaa !47
  %45 = tail call noundef ptr @_ZN7sc_core16sc_process_table13method_q_headEv(ptr noundef nonnull align 8 dereferenceable(16) %44)
  %.not3138 = icmp eq ptr %45, null
  br i1 %.not3138, label %._crit_edge42, label %.lr.ph41

.lr.ph41:                                         ; preds = %._crit_edge, %64
  %.02739 = phi ptr [ %65, %64 ], [ %45, %._crit_edge ]
  %46 = getelementptr inbounds i8, ptr %.02739, i64 280
  %47 = load i32, ptr %46, align 8, !tbaa !52
  %48 = and i32 %47, 1
  %.not35 = icmp eq i32 %48, 0
  br i1 %.not35, label %49, label %51

49:                                               ; preds = %.lr.ph41
  %50 = tail call noundef zeroext i1 @_ZNK7sc_core12sc_process_b15dont_initializeEv(ptr noundef nonnull align 8 dereferenceable(357) %.02739)
  br i1 %50, label %51, label %57

51:                                               ; preds = %49, %.lr.ph41
  %52 = getelementptr inbounds i8, ptr %.02739, i64 288
  %53 = tail call noundef i64 @_ZNKSt6vectorIPKN7sc_core8sc_eventESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %52) #9
  %54 = icmp eq i64 %53, 0
  br i1 %54, label %55, label %64

55:                                               ; preds = %51
  %56 = tail call noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112) %.02739)
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef nonnull @_ZN7sc_core34SC_ID_DISABLE_WILL_ORPHAN_PROCESS_E, ptr noundef %56, ptr noundef nonnull @.str.7, i32 noundef 784)
  br label %64

57:                                               ; preds = %49
  %58 = load i32, ptr %46, align 8, !tbaa !52
  %59 = and i32 %58, 4
  %60 = icmp eq i32 %59, 0
  br i1 %60, label %61, label %62

61:                                               ; preds = %57
  tail call void @_ZN7sc_core13sc_simcontext26push_runnable_method_frontEPNS_17sc_method_processE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr noundef nonnull %.02739)
  br label %64

62:                                               ; preds = %57
  %63 = or i32 %58, 2
  store i32 %63, ptr %46, align 8, !tbaa !52
  br label %64

64:                                               ; preds = %55, %51, %62, %61
  %65 = tail call noundef ptr @_ZN7sc_core17sc_method_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(400) %.02739)
  %.not31 = icmp eq ptr %65, null
  br i1 %.not31, label %._crit_edge42, label %.lr.ph41, !llvm.loop !68

._crit_edge42:                                    ; preds = %64, %._crit_edge
  %66 = load ptr, ptr %33, align 8, !tbaa !47
  %67 = tail call noundef ptr @_ZN7sc_core16sc_process_table13thread_q_headEv(ptr noundef nonnull align 8 dereferenceable(16) %66)
  %.not3243 = icmp eq ptr %67, null
  br i1 %.not3243, label %._crit_edge47, label %.lr.ph46

.lr.ph46:                                         ; preds = %._crit_edge42, %86
  %.144 = phi ptr [ %87, %86 ], [ %67, %._crit_edge42 ]
  %68 = getelementptr inbounds i8, ptr %.144, i64 280
  %69 = load i32, ptr %68, align 8, !tbaa !52
  %70 = and i32 %69, 1
  %.not34 = icmp eq i32 %70, 0
  br i1 %.not34, label %71, label %73

71:                                               ; preds = %.lr.ph46
  %72 = tail call noundef zeroext i1 @_ZNK7sc_core12sc_process_b15dont_initializeEv(ptr noundef nonnull align 8 dereferenceable(357) %.144)
  br i1 %72, label %73, label %79

73:                                               ; preds = %71, %.lr.ph46
  %74 = getelementptr inbounds i8, ptr %.144, i64 288
  %75 = tail call noundef i64 @_ZNKSt6vectorIPKN7sc_core8sc_eventESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %74) #9
  %76 = icmp eq i64 %75, 0
  br i1 %76, label %77, label %86

77:                                               ; preds = %73
  %78 = tail call noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112) %.144)
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef nonnull @_ZN7sc_core34SC_ID_DISABLE_WILL_ORPHAN_PROCESS_E, ptr noundef %78, ptr noundef nonnull @.str.7, i32 noundef 809)
  br label %86

79:                                               ; preds = %71
  %80 = load i32, ptr %68, align 8, !tbaa !52
  %81 = and i32 %80, 4
  %82 = icmp eq i32 %81, 0
  br i1 %82, label %83, label %84

83:                                               ; preds = %79
  tail call void @_ZN7sc_core13sc_simcontext26push_runnable_thread_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr noundef nonnull %.144)
  br label %86

84:                                               ; preds = %79
  %85 = or i32 %80, 2
  store i32 %85, ptr %68, align 8, !tbaa !52
  br label %86

86:                                               ; preds = %77, %73, %84, %83
  %87 = tail call noundef ptr @_ZN7sc_core17sc_thread_process10next_existEv(ptr noundef nonnull align 8 dereferenceable(404) %.144)
  %.not32 = icmp eq ptr %87, null
  br i1 %.not32, label %._crit_edge47, label %.lr.ph46, !llvm.loop !69

._crit_edge47:                                    ; preds = %86, %._crit_edge42
  %88 = getelementptr inbounds i8, ptr %0, i64 168
  %89 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %88) #9
  %90 = and i64 %89, 4294967295
  %.not33 = icmp eq i64 %90, 0
  br i1 %.not33, label %99, label %91

91:                                               ; preds = %._crit_edge47
  %92 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %88, i64 noundef 0) #9
  %sext = shl i64 %89, 32
  %93 = ashr exact i64 %sext, 32
  br label %94

94:                                               ; preds = %94, %91
  %indvars.iv = phi i64 [ %indvars.iv.next, %94 ], [ %93, %91 ]
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %95 = getelementptr inbounds ptr, ptr %92, i64 %indvars.iv.next
  %96 = load ptr, ptr %95, align 8, !tbaa !70
  tail call void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160) %96)
  %97 = icmp sgt i64 %indvars.iv, 1
  br i1 %97, label %94, label %98, !llvm.loop !71

98:                                               ; preds = %94
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %88, i64 noundef 0)
  br label %99

99:                                               ; preds = %._crit_edge47, %98, %1, %5, %29
  ret void
}

declare void @_ZN7sc_core13sc_cor_pkg_qtC1EPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef) unnamed_addr #4

declare void @_ZN7sc_core16sc_port_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare void @_ZN7sc_core18sc_export_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare void @_ZN7sc_core24sc_prim_channel_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #4

declare void @_ZN7sc_core18sc_module_registry16start_simulationEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core16sc_process_table13thread_q_headEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core11sc_runnable4initEv(ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #5 align 2

declare void @_ZN7sc_core24sc_prim_channel_registry14perform_updateEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core16sc_process_table13method_q_headEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core12sc_process_b15dont_initializeEv(ptr noundef nonnull align 8 dereferenceable(357)) local_unnamed_addr #6 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPKN7sc_core8sc_eventESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #6 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #6 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext26push_runnable_method_frontEPNS_17sc_method_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #5 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext26push_runnable_thread_frontEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #5 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #6 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #6 align 2

declare void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160)) local_unnamed_addr #4

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }
attributes #9 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 298}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{i8 0, i8 2}
!35 = !{}
!36 = !{!6, !7, i64 328}
!37 = !{!38, !38, i64 0}
!38 = !{!"vtable pointer", !9, i64 0}
!39 = !{!6, !7, i64 336}
!40 = !{!6, !33, i64 316}
!41 = !{!6, !7, i64 16}
!42 = !{!6, !7, i64 24}
!43 = !{!6, !7, i64 32}
!44 = !{!6, !7, i64 8}
!45 = !{!6, !12, i64 320}
!46 = !{!6, !12, i64 296}
!47 = !{!6, !7, i64 56}
!48 = distinct !{!48, !49}
!49 = !{!"llvm.loop.mustprogress"}
!50 = !{!6, !7, i64 232}
!51 = !{!6, !32, i64 300}
!52 = !{!53, !13, i64 280}
!53 = !{!"_ZTSN7sc_core12sc_process_bE", !54, i64 0, !7, i64 112, !13, i64 120, !13, i64 124, !13, i64 128, !13, i64 132, !12, i64 136, !12, i64 137, !7, i64 144, !13, i64 152, !7, i64 160, !7, i64 168, !12, i64 176, !12, i64 177, !12, i64 178, !12, i64 179, !7, i64 184, !7, i64 192, !11, i64 200, !13, i64 204, !58, i64 208, !7, i64 232, !7, i64 240, !7, i64 248, !7, i64 256, !8, i64 264, !13, i64 280, !62, i64 288, !12, i64 312, !7, i64 320, !7, i64 328, !66, i64 336, !12, i64 340, !7, i64 344, !67, i64 352, !12, i64 356}
!54 = !{!"_ZTSN7sc_core9sc_objectE", !7, i64 8, !18, i64 16, !22, i64 40, !55, i64 64, !7, i64 96, !7, i64 104}
!55 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !56, i64 0, !57, i64 8, !8, i64 16}
!56 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !7, i64 0}
!57 = !{!"long", !8, i64 0}
!58 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !59, i64 0}
!59 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !60, i64 0}
!60 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !61, i64 0}
!61 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!62 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !63, i64 0}
!63 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !64, i64 0}
!64 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !65, i64 0}
!65 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!66 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !8, i64 0}
!67 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !8, i64 0}
!68 = distinct !{!68, !49}
!69 = distinct !{!69, !49}
!70 = !{!7, !7, i64 0}
!71 = distinct !{!71, !49}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass