; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/SourceLevelDebugPkg (XhcCheckUrbResult)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._URB = type <{ i64, i32, i32, i32, i64, i64, i8, i32 }>
%struct._USB3_DEBUG_PORT_INSTANCE = type <{ i8, i8, i8, i8, i64, i64, i64, i64, i64, %struct._TRANSFER_RING, %struct._TRANSFER_RING, %struct._EVENT_RING, %struct._URB, %struct._URB, i8, i64, i64, i64, i8 }>
%struct._TRANSFER_RING = type <{ i64, i32, i64, i64, i32 }>
%struct._EVENT_RING = type <{ i64, i64, i32, i64, i64, i32 }>
%struct._EVT_TRB_TRANSFER = type { i32, i32, i64 }
%struct._TRB_TEMPLATE = type { i32, i32, i32, i32 }

@.str = external hidden unnamed_addr constant [191 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [50 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare zeroext i8 @DebugAssertEnabled() #1

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #1

declare i64 @LShiftU64(i64 noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @XhcSyncEventRing(ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i64 @XhcCheckNewEvent(ptr noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @IsTrbInTrsRing(ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XhcCheckUrbResult(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i64, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  br label %13

13:                                               ; preds = %2
  %14 = call zeroext i8 @DebugAssertEnabled()
  %15 = icmp ne i8 %14, 0
  br i1 %15, label %16, label %24

16:                                               ; preds = %13
  %17 = load ptr, ptr %3, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %22

19:                                               ; preds = %16
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = icmp ne ptr %20, null
  br i1 %21, label %23, label %22

22:                                               ; preds = %19, %16
  call void @DebugAssert(ptr noundef @.str, i64 noundef 228, ptr noundef @.str.8)
  br label %23

23:                                               ; preds = %22, %19
  br label %24

24:                                               ; preds = %23, %13
  br label %25

25:                                               ; preds = %24
  br label %26

26:                                               ; preds = %25
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct._URB, ptr %27, i32 0, i32 6
  %29 = load i8, ptr %28, align 1, !tbaa !9
  %30 = icmp ne i8 %29, 0
  br i1 %30, label %31, label %32

31:                                               ; preds = %26
  br label %185

32:                                               ; preds = %26
  store ptr null, ptr %5, align 8, !tbaa !5
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %34, i32 0, i32 11
  %36 = call i64 @XhcSyncEventRing(ptr noundef %33, ptr noundef %35)
  store i64 0, ptr %7, align 8, !tbaa !13
  br label %37

37:                                               ; preds = %181, %32
  %38 = load i64, ptr %7, align 8, !tbaa !13
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %39, i32 0, i32 11
  %41 = getelementptr inbounds %struct._EVENT_RING, ptr %40, i32 0, i32 2
  %42 = load i32, ptr %41, align 1, !tbaa !14
  %43 = zext i32 %42 to i64
  %44 = icmp ult i64 %38, %43
  br i1 %44, label %45, label %184

45:                                               ; preds = %37
  %46 = load ptr, ptr %3, align 8, !tbaa !5
  %47 = load ptr, ptr %3, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %47, i32 0, i32 11
  %49 = call i64 @XhcCheckNewEvent(ptr noundef %46, ptr noundef %48, ptr noundef %5)
  store i64 %49, ptr %8, align 8, !tbaa !13
  %50 = load i64, ptr %8, align 8, !tbaa !13
  %51 = icmp eq i64 %50, -9223372036854775802
  br i1 %51, label %52, label %53

52:                                               ; preds = %45
  br label %185

53:                                               ; preds = %45
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %54, i32 0, i32 2
  %56 = load i64, ptr %55, align 1
  %57 = lshr i64 %56, 42
  %58 = and i64 %57, 63
  %59 = trunc i64 %58 to i32
  %60 = icmp ne i32 %59, 33
  br i1 %60, label %61, label %70

61:                                               ; preds = %53
  %62 = load ptr, ptr %5, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %62, i32 0, i32 2
  %64 = load i64, ptr %63, align 1
  %65 = lshr i64 %64, 42
  %66 = and i64 %65, 63
  %67 = trunc i64 %66 to i32
  %68 = icmp ne i32 %67, 32
  br i1 %68, label %69, label %70

69:                                               ; preds = %61
  br label %181

70:                                               ; preds = %61, %53
  %71 = load ptr, ptr %5, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %71, i32 0, i32 0
  %73 = load i32, ptr %72, align 1, !tbaa !18
  %74 = zext i32 %73 to i64
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %75, i32 0, i32 1
  %77 = load i32, ptr %76, align 1, !tbaa !20
  %78 = zext i32 %77 to i64
  %79 = call i64 @LShiftU64(i64 noundef %78, i64 noundef 32)
  %80 = or i64 %74, %79
  %81 = inttoptr i64 %80 to ptr
  store ptr %81, ptr %6, align 8, !tbaa !5
  %82 = load ptr, ptr %4, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct._URB, ptr %82, i32 0, i32 4
  %84 = load i64, ptr %83, align 1, !tbaa !21
  %85 = inttoptr i64 %84 to ptr
  %86 = load ptr, ptr %6, align 8, !tbaa !5
  %87 = call zeroext i8 @IsTrbInTrsRing(ptr noundef %85, ptr noundef %86)
  %88 = icmp ne i8 %87, 0
  br i1 %88, label %89, label %91

89:                                               ; preds = %70
  %90 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %90, ptr %9, align 8, !tbaa !5
  br label %143

91:                                               ; preds = %70
  %92 = load ptr, ptr %3, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %92, i32 0, i32 13
  %94 = getelementptr inbounds %struct._URB, ptr %93, i32 0, i32 4
  %95 = load i64, ptr %94, align 1, !tbaa !22
  %96 = inttoptr i64 %95 to ptr
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = call zeroext i8 @IsTrbInTrsRing(ptr noundef %96, ptr noundef %97)
  %99 = icmp ne i8 %98, 0
  br i1 %99, label %100, label %142

100:                                              ; preds = %91
  %101 = load ptr, ptr %3, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %101, i32 0, i32 13
  %103 = getelementptr inbounds %struct._URB, ptr %102, i32 0, i32 1
  %104 = load i32, ptr %103, align 1, !tbaa !23
  %105 = load ptr, ptr %5, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %105, i32 0, i32 2
  %107 = load i64, ptr %106, align 1
  %108 = and i64 %107, 16777215
  %109 = trunc i64 %108 to i32
  %110 = sub i32 %104, %109
  %111 = trunc i32 %110 to i8
  %112 = load ptr, ptr %3, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %112, i32 0, i32 14
  store i8 %111, ptr %113, align 1, !tbaa !24
  %114 = load ptr, ptr %3, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %114, i32 0, i32 15
  %116 = load i64, ptr %115, align 1, !tbaa !25
  %117 = inttoptr i64 %116 to ptr
  %118 = load ptr, ptr %3, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %118, i32 0, i32 13
  %120 = getelementptr inbounds %struct._URB, ptr %119, i32 0, i32 0
  %121 = load i64, ptr %120, align 1, !tbaa !26
  %122 = inttoptr i64 %121 to ptr
  %123 = load ptr, ptr %3, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %123, i32 0, i32 14
  %125 = load i8, ptr %124, align 1, !tbaa !24
  %126 = zext i8 %125 to i64
  %127 = call ptr @CopyMem(ptr noundef %117, ptr noundef %122, i64 noundef %126)
  %128 = load ptr, ptr %6, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct._TRB_TEMPLATE, ptr %128, i32 0, i32 3
  %130 = load i32, ptr %129, align 1
  %131 = and i32 %130, 1
  %132 = and i32 %131, 1
  %133 = icmp ne i32 %132, 0
  %134 = zext i1 %133 to i64
  %135 = select i1 %133, i32 0, i32 1
  %136 = load ptr, ptr %6, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct._TRB_TEMPLATE, ptr %136, i32 0, i32 3
  %138 = load i32, ptr %137, align 1
  %139 = and i32 %135, 1
  %140 = and i32 %138, -2
  %141 = or i32 %140, %139
  store i32 %141, ptr %137, align 1
  br label %181

142:                                              ; preds = %91
  br label %181

143:                                              ; preds = %89
  %144 = load ptr, ptr %5, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %144, i32 0, i32 2
  %146 = load i64, ptr %145, align 1
  %147 = lshr i64 %146, 24
  %148 = and i64 %147, 255
  %149 = trunc i64 %148 to i32
  %150 = icmp eq i32 %149, 13
  br i1 %150, label %159, label %151

151:                                              ; preds = %143
  %152 = load ptr, ptr %5, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %152, i32 0, i32 2
  %154 = load i64, ptr %153, align 1
  %155 = lshr i64 %154, 24
  %156 = and i64 %155, 255
  %157 = trunc i64 %156 to i32
  %158 = icmp eq i32 %157, 1
  br i1 %158, label %159, label %173

159:                                              ; preds = %151, %143
  %160 = load ptr, ptr %9, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct._URB, ptr %160, i32 0, i32 1
  %162 = load i32, ptr %161, align 1, !tbaa !27
  %163 = load ptr, ptr %5, align 8, !tbaa !5
  %164 = getelementptr inbounds %struct._EVT_TRB_TRANSFER, ptr %163, i32 0, i32 2
  %165 = load i64, ptr %164, align 1
  %166 = and i64 %165, 16777215
  %167 = trunc i64 %166 to i32
  %168 = sub i32 %162, %167
  %169 = load ptr, ptr %9, align 8, !tbaa !5
  %170 = getelementptr inbounds %struct._URB, ptr %169, i32 0, i32 3
  %171 = load i32, ptr %170, align 1, !tbaa !28
  %172 = add i32 %171, %168
  store i32 %172, ptr %170, align 1, !tbaa !28
  br label %178

173:                                              ; preds = %151
  %174 = load ptr, ptr %9, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct._URB, ptr %174, i32 0, i32 2
  %176 = load i32, ptr %175, align 1, !tbaa !29
  %177 = or i32 %176, 64
  store i32 %177, ptr %175, align 1, !tbaa !29
  br label %178

178:                                              ; preds = %173, %159
  %179 = load ptr, ptr %9, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct._URB, ptr %179, i32 0, i32 6
  store i8 1, ptr %180, align 1, !tbaa !9
  br label %181

181:                                              ; preds = %178, %142, %100, %69
  %182 = load i64, ptr %7, align 8, !tbaa !13
  %183 = add i64 %182, 1
  store i64 %183, ptr %7, align 8, !tbaa !13
  br label %37, !llvm.loop !30

184:                                              ; preds = %37
  br label %185

185:                                              ; preds = %184, %52, %31
  %186 = load ptr, ptr %3, align 8, !tbaa !5
  %187 = call i32 @XhcReadDebugReg(ptr noundef %186, i32 noundef 24)
  store i32 %187, ptr %12, align 4, !tbaa !32
  %188 = load ptr, ptr %3, align 8, !tbaa !5
  %189 = call i32 @XhcReadDebugReg(ptr noundef %188, i32 noundef 28)
  store i32 %189, ptr %11, align 4, !tbaa !32
  %190 = load i32, ptr %11, align 4, !tbaa !32
  %191 = zext i32 %190 to i64
  %192 = call i64 @LShiftU64(i64 noundef %191, i64 noundef 32)
  %193 = load i32, ptr %12, align 4, !tbaa !32
  %194 = zext i32 %193 to i64
  %195 = or i64 %192, %194
  store i64 %195, ptr %10, align 8, !tbaa !13
  %196 = load i64, ptr %10, align 8, !tbaa !13
  %197 = and i64 %196, -16
  %198 = load ptr, ptr %3, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %198, i32 0, i32 11
  %200 = getelementptr inbounds %struct._EVENT_RING, ptr %199, i32 0, i32 4
  %201 = load i64, ptr %200, align 1, !tbaa !33
  %202 = and i64 %201, -16
  %203 = icmp ne i64 %197, %202
  br i1 %203, label %204, label %220

204:                                              ; preds = %185
  %205 = load ptr, ptr %3, align 8, !tbaa !5
  %206 = load ptr, ptr %3, align 8, !tbaa !5
  %207 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %206, i32 0, i32 11
  %208 = getelementptr inbounds %struct._EVENT_RING, ptr %207, i32 0, i32 4
  %209 = load i64, ptr %208, align 1, !tbaa !33
  %210 = and i64 %209, 4294967295
  %211 = trunc i64 %210 to i32
  call void @XhcWriteDebugReg(ptr noundef %205, i32 noundef 24, i32 noundef %211)
  %212 = load ptr, ptr %3, align 8, !tbaa !5
  %213 = load ptr, ptr %3, align 8, !tbaa !5
  %214 = getelementptr inbounds %struct._USB3_DEBUG_PORT_INSTANCE, ptr %213, i32 0, i32 11
  %215 = getelementptr inbounds %struct._EVENT_RING, ptr %214, i32 0, i32 4
  %216 = load i64, ptr %215, align 1, !tbaa !33
  %217 = call i64 @RShiftU64(i64 noundef %216, i64 noundef 32)
  %218 = and i64 %217, 4294967295
  %219 = trunc i64 %218 to i32
  call void @XhcWriteDebugReg(ptr noundef %212, i32 noundef 28, i32 noundef %219)
  br label %220

220:                                              ; preds = %204, %185
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  ret void
}

declare ptr @CopyMem(ptr noundef, ptr noundef, i64 noundef) #1

declare i32 @XhcReadDebugReg(ptr noundef, i32 noundef) #1

declare void @XhcWriteDebugReg(ptr noundef, i32 noundef, i32 noundef) #1

declare i64 @RShiftU64(i64 noundef, i64 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !7, i64 36}
!10 = !{!"_URB", !11, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !11, i64 20, !11, i64 28, !7, i64 36, !12, i64 37}
!11 = !{!"long long", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!11, !11, i64 0}
!14 = !{!15, !12, i64 124}
!15 = !{!"_USB3_DEBUG_PORT_INSTANCE", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3, !11, i64 4, !11, i64 12, !11, i64 20, !11, i64 28, !11, i64 36, !16, i64 44, !16, i64 76, !17, i64 108, !10, i64 148, !10, i64 189, !7, i64 230, !11, i64 231, !11, i64 239, !11, i64 247, !7, i64 255}
!16 = !{!"_TRANSFER_RING", !11, i64 0, !12, i64 8, !11, i64 12, !11, i64 20, !12, i64 28}
!17 = !{!"_EVENT_RING", !11, i64 0, !11, i64 8, !12, i64 16, !11, i64 20, !11, i64 28, !12, i64 36}
!18 = !{!19, !12, i64 0}
!19 = !{!"_EVT_TRB_TRANSFER", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 11, !12, i64 12, !12, i64 12, !12, i64 12, !12, i64 12, !12, i64 13, !12, i64 14, !12, i64 14, !12, i64 15}
!20 = !{!19, !12, i64 4}
!21 = !{!10, !11, i64 20}
!22 = !{!15, !11, i64 209}
!23 = !{!15, !12, i64 197}
!24 = !{!15, !7, i64 230}
!25 = !{!15, !11, i64 231}
!26 = !{!15, !11, i64 189}
!27 = !{!10, !12, i64 8}
!28 = !{!10, !12, i64 16}
!29 = !{!10, !12, i64 12}
!30 = distinct !{!30, !31}
!31 = !{!"llvm.loop.mustprogress"}
!32 = !{!12, !12, i64 0}
!33 = !{!15, !11, i64 136}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [191 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [50 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #1

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #1

declare i64 @LShiftU64(i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @XhcSyncEventRing(ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local i64 @XhcCheckNewEvent(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @IsTrbInTrsRing(ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local void @XhcCheckUrbResult(ptr noundef %0, ptr noundef %1) local_unnamed_addr #2 {
  %3 = alloca ptr, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #3
  %4 = tail call zeroext i8 @DebugAssertEnabled() #3
  %.not = icmp eq i8 %4, 0
  br i1 %.not, label %9, label %5

5:                                                ; preds = %2
  %6 = icmp ne ptr %0, null
  %7 = icmp ne ptr %1, null
  %or.cond = and i1 %6, %7
  br i1 %or.cond, label %9, label %8

8:                                                ; preds = %5
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 228, ptr noundef nonnull @.str.8) #3
  br label %9

9:                                                ; preds = %8, %5, %2
  %10 = getelementptr inbounds i8, ptr %1, i64 36
  %11 = load i8, ptr %10, align 1, !tbaa !5
  %.not39 = icmp eq i8 %11, 0
  br i1 %.not39, label %12, label %.loopexit

12:                                               ; preds = %9
  store ptr null, ptr %3, align 8, !tbaa !11
  %13 = getelementptr inbounds i8, ptr %0, i64 108
  %14 = tail call i64 @XhcSyncEventRing(ptr noundef %0, ptr noundef nonnull %13)
  %15 = getelementptr inbounds i8, ptr %0, i64 124
  %16 = load i32, ptr %15, align 1, !tbaa !13
  %.not48 = icmp eq i32 %16, 0
  br i1 %.not48, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %12
  %17 = getelementptr inbounds i8, ptr %1, i64 20
  %18 = getelementptr inbounds i8, ptr %1, i64 8
  %19 = getelementptr inbounds i8, ptr %1, i64 16
  %20 = getelementptr inbounds i8, ptr %1, i64 12
  %21 = getelementptr inbounds i8, ptr %0, i64 209
  %22 = getelementptr inbounds i8, ptr %0, i64 189
  %23 = getelementptr inbounds i8, ptr %0, i64 197
  %24 = getelementptr inbounds i8, ptr %0, i64 230
  %25 = getelementptr inbounds i8, ptr %0, i64 231
  br label %26

26:                                               ; preds = %.lr.ph, %83
  %.046 = phi i64 [ 0, %.lr.ph ], [ %84, %83 ]
  %27 = call i64 @XhcCheckNewEvent(ptr noundef nonnull %0, ptr noundef nonnull %13, ptr noundef nonnull %3)
  %28 = icmp eq i64 %27, -9223372036854775802
  br i1 %28, label %.loopexit, label %29

29:                                               ; preds = %26
  %30 = load ptr, ptr %3, align 8, !tbaa !11
  %31 = getelementptr inbounds i8, ptr %30, i64 8
  %32 = load i64, ptr %31, align 1
  %33 = and i64 %32, 272678883688448
  %switch = icmp eq i64 %33, 140737488355328
  br i1 %switch, label %34, label %83

34:                                               ; preds = %29
  %35 = load i32, ptr %30, align 1, !tbaa !17
  %36 = zext i32 %35 to i64
  %37 = getelementptr inbounds i8, ptr %30, i64 4
  %38 = load i32, ptr %37, align 1, !tbaa !19
  %39 = zext i32 %38 to i64
  %40 = call i64 @LShiftU64(i64 noundef %39, i64 noundef 32) #3
  %41 = or i64 %40, %36
  %42 = inttoptr i64 %41 to ptr
  %43 = load i64, ptr %17, align 1, !tbaa !20
  %44 = inttoptr i64 %43 to ptr
  %45 = call zeroext i8 @IsTrbInTrsRing(ptr noundef %44, ptr noundef %42)
  %.not42 = icmp eq i8 %45, 0
  br i1 %.not42, label %51, label %46

46:                                               ; preds = %34
  %47 = load ptr, ptr %3, align 8, !tbaa !11
  %48 = getelementptr inbounds i8, ptr %47, i64 8
  %49 = load i64, ptr %48, align 1
  %50 = lshr i64 %49, 24
  %trunc = trunc i64 %50 to i8
  switch i8 %trunc, label %79 [
    i8 13, label %72
    i8 1, label %72
  ]

51:                                               ; preds = %34
  %52 = load i64, ptr %21, align 1, !tbaa !21
  %53 = inttoptr i64 %52 to ptr
  %54 = call zeroext i8 @IsTrbInTrsRing(ptr noundef %53, ptr noundef %42)
  %.not43 = icmp eq i8 %54, 0
  br i1 %.not43, label %83, label %55

55:                                               ; preds = %51
  %56 = load i32, ptr %23, align 1, !tbaa !22
  %57 = load ptr, ptr %3, align 8, !tbaa !11
  %58 = getelementptr inbounds i8, ptr %57, i64 8
  %59 = load i64, ptr %58, align 1
  %60 = trunc i64 %59 to i32
  %61 = sub i32 %56, %60
  %62 = trunc i32 %61 to i8
  store i8 %62, ptr %24, align 1, !tbaa !23
  %63 = load i64, ptr %25, align 1, !tbaa !24
  %64 = inttoptr i64 %63 to ptr
  %65 = load i64, ptr %22, align 1, !tbaa !25
  %66 = inttoptr i64 %65 to ptr
  %.mask = and i32 %61, 255
  %67 = zext nneg i32 %.mask to i64
  %68 = call ptr @CopyMem(ptr noundef %64, ptr noundef %66, i64 noundef %67) #3
  %69 = getelementptr inbounds i8, ptr %42, i64 12
  %70 = load i32, ptr %69, align 1
  %71 = xor i32 %70, 1
  store i32 %71, ptr %69, align 1
  br label %83

72:                                               ; preds = %46, %46
  %73 = trunc i64 %49 to i32
  %74 = load i32, ptr %18, align 1, !tbaa !26
  %75 = and i32 %73, 16777215
  %76 = sub i32 %74, %75
  %77 = load i32, ptr %19, align 1, !tbaa !27
  %78 = add i32 %76, %77
  store i32 %78, ptr %19, align 1, !tbaa !27
  br label %82

79:                                               ; preds = %46
  %80 = load i32, ptr %20, align 1, !tbaa !28
  %81 = or i32 %80, 64
  store i32 %81, ptr %20, align 1, !tbaa !28
  br label %82

82:                                               ; preds = %79, %72
  store i8 1, ptr %10, align 1, !tbaa !5
  br label %83

83:                                               ; preds = %29, %51, %82, %55
  %84 = add nuw nsw i64 %.046, 1
  %85 = load i32, ptr %15, align 1, !tbaa !13
  %86 = zext i32 %85 to i64
  %87 = icmp ult i64 %84, %86
  br i1 %87, label %26, label %.loopexit, !llvm.loop !29

.loopexit:                                        ; preds = %26, %83, %12, %9
  %88 = call i32 @XhcReadDebugReg(ptr noundef %0, i32 noundef 24) #3
  %89 = call i32 @XhcReadDebugReg(ptr noundef %0, i32 noundef 28) #3
  %90 = zext i32 %89 to i64
  %91 = call i64 @LShiftU64(i64 noundef %90, i64 noundef 32) #3
  %92 = zext i32 %88 to i64
  %93 = or i64 %91, %92
  %94 = getelementptr inbounds i8, ptr %0, i64 136
  %95 = load i64, ptr %94, align 1, !tbaa !31
  %96 = xor i64 %93, %95
  %.not45 = icmp ult i64 %96, 16
  br i1 %.not45, label %102, label %97

97:                                               ; preds = %.loopexit
  %98 = trunc i64 %95 to i32
  call void @XhcWriteDebugReg(ptr noundef nonnull %0, i32 noundef 24, i32 noundef %98) #3
  %99 = load i64, ptr %94, align 1, !tbaa !31
  %100 = call i64 @RShiftU64(i64 noundef %99, i64 noundef 32) #3
  %101 = trunc i64 %100 to i32
  call void @XhcWriteDebugReg(ptr noundef nonnull %0, i32 noundef 28, i32 noundef %101) #3
  br label %102

102:                                              ; preds = %97, %.loopexit
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #3
  ret void
}

declare ptr @CopyMem(ptr noundef, ptr noundef, i64 noundef) local_unnamed_addr #1

declare i32 @XhcReadDebugReg(ptr noundef, i32 noundef) local_unnamed_addr #1

declare void @XhcWriteDebugReg(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare i64 @RShiftU64(i64 noundef, i64 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 36}
!6 = !{!"_URB", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !7, i64 20, !7, i64 28, !8, i64 36, !10, i64 37}
!7 = !{!"long long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!14, !10, i64 124}
!14 = !{!"_USB3_DEBUG_PORT_INSTANCE", !8, i64 0, !8, i64 1, !8, i64 2, !8, i64 3, !7, i64 4, !7, i64 12, !7, i64 20, !7, i64 28, !7, i64 36, !15, i64 44, !15, i64 76, !16, i64 108, !6, i64 148, !6, i64 189, !8, i64 230, !7, i64 231, !7, i64 239, !7, i64 247, !8, i64 255}
!15 = !{!"_TRANSFER_RING", !7, i64 0, !10, i64 8, !7, i64 12, !7, i64 20, !10, i64 28}
!16 = !{!"_EVENT_RING", !7, i64 0, !7, i64 8, !10, i64 16, !7, i64 20, !7, i64 28, !10, i64 36}
!17 = !{!18, !10, i64 0}
!18 = !{!"_EVT_TRB_TRANSFER", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 11, !10, i64 12, !10, i64 12, !10, i64 12, !10, i64 12, !10, i64 13, !10, i64 14, !10, i64 14, !10, i64 15}
!19 = !{!18, !10, i64 4}
!20 = !{!6, !7, i64 20}
!21 = !{!14, !7, i64 209}
!22 = !{!14, !10, i64 197}
!23 = !{!14, !8, i64 230}
!24 = !{!14, !7, i64 231}
!25 = !{!14, !7, i64 189}
!26 = !{!6, !10, i64 8}
!27 = !{!6, !10, i64 16}
!28 = !{!6, !10, i64 12}
!29 = distinct !{!29, !30}
!30 = !{!"llvm.loop.mustprogress"}
!31 = !{!14, !7, i64 136}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass