; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_event_queue)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_event_queue" = type <{ %"class.sc_core::sc_event_queue_if", %"class.sc_core::sc_module", %"class.sc_core::sc_ppq", %"class.sc_core::sc_event", i64, i32, [4 x i8] }>
%"class.sc_core::sc_event_queue_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_ppq" = type { %"class.sc_core::sc_ppq_base" }
%"class.sc_core::sc_ppq_base" = type { ptr, i32, i32, ptr }
%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.13", %"class.std::vector.13" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core14sc_event_queue6notifyERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(436) %0, ptr noundef nonnull align 8 dereferenceable(8) %1) unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  %9 = getelementptr inbounds i8, ptr %8, i64 8
  %10 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %9)
  %11 = call noundef i64 @_ZNK7sc_core13sc_simcontext12change_stampEv(ptr noundef nonnull align 8 dereferenceable(344) %10)
  %12 = getelementptr inbounds %"class.sc_core::sc_event_queue", ptr %8, i32 0, i32 4
  store i64 %11, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #8
  %13 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 8) #9
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core13sc_time_stampEv()
          to label %16 unwind label %29

16:                                               ; preds = %2
  invoke void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind writable sret(%"class.sc_core::sc_time") align 8 %13, ptr noundef nonnull align 8 dereferenceable(8) %14, ptr noundef nonnull align 8 dereferenceable(8) %15)
          to label %17 unwind label %29

17:                                               ; preds = %16
  store ptr %13, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %"class.sc_core::sc_event_queue", ptr %8, i32 0, i32 2
  %19 = call noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %18)
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %26, label %21

21:                                               ; preds = %17
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %"class.sc_core::sc_event_queue", ptr %8, i32 0, i32 2
  %24 = call noundef ptr @_ZNK7sc_core6sc_ppqIPNS_7sc_timeEE3topEv(ptr noundef nonnull align 8 dereferenceable(24) %23)
  %25 = call noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %22, ptr noundef nonnull align 8 dereferenceable(8) %24)
  br i1 %25, label %26, label %33

26:                                               ; preds = %21, %17
  %27 = getelementptr inbounds %"class.sc_core::sc_event_queue", ptr %8, i32 0, i32 3
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN7sc_core8sc_event6notifyERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(160) %27, ptr noundef nonnull align 8 dereferenceable(8) %28)
  br label %33

29:                                               ; preds = %16, %2
  %30 = landingpad { ptr, i32 }
          cleanup
  %31 = extractvalue { ptr, i32 } %30, 0
  store ptr %31, ptr %6, align 8
  %32 = extractvalue { ptr, i32 } %30, 1
  store i32 %32, ptr %7, align 4
  call void @_ZdlPvm(ptr noundef %13, i64 noundef 8) #10
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #8
  br label %36

33:                                               ; preds = %26, %21
  %34 = getelementptr inbounds %"class.sc_core::sc_event_queue", ptr %8, i32 0, i32 2
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  call void @_ZN7sc_core6sc_ppqIPNS_7sc_timeEE6insertES2_(ptr noundef nonnull align 8 dereferenceable(24) %34, ptr noundef %35)
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #8
  ret void

36:                                               ; preds = %29
  %37 = load ptr, ptr %6, align 8
  %38 = load i32, ptr %7, align 4
  %39 = insertvalue { ptr, i32 } poison, ptr %37, 0
  %40 = insertvalue { ptr, i32 } %39, i32 %38, 1
  resume { ptr, i32 } %40
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK7sc_core13sc_simcontext12change_stampEv(ptr noundef nonnull align 8 dereferenceable(344)) #4 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #5

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #6

declare noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core13sc_time_stampEv() #7

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZNK7sc_core6sc_ppqIPNS_7sc_timeEE3topEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

declare void @_ZN7sc_core8sc_event6notifyERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(160), ptr noundef nonnull align 8 dereferenceable(8)) #7

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core6sc_ppqIPNS_7sc_timeEE6insertES2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef) #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { builtin allocsize(0) }
attributes #10 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !46, i64 424}
!10 = !{!"_ZTSN7sc_core14sc_event_queueE", !11, i64 0, !12, i64 8, !34, i64 240, !36, i64 264, !46, i64 424, !33, i64 432}
!11 = !{!"_ZTSN7sc_core17sc_event_queue_ifE"}
!12 = !{!"_ZTSN7sc_core9sc_moduleE", !13, i64 0, !25, i64 112, !26, i64 120, !28, i64 144, !30, i64 168, !32, i64 192, !6, i64 200, !33, i64 208, !6, i64 216, !6, i64 224}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !6, i64 96, !6, i64 104}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !27, i64 8, !6, i64 16}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !29, i64 8, !6, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !31, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!32 = !{!"bool", !7, i64 0}
!33 = !{!"int", !7, i64 0}
!34 = !{!"_ZTSN7sc_core6sc_ppqIPNS_7sc_timeEEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core11sc_ppq_baseE", !6, i64 0, !33, i64 8, !33, i64 12, !6, i64 16}
!36 = !{!"_ZTSN7sc_core8sc_eventE", !22, i64 0, !6, i64 32, !6, i64 40, !37, i64 48, !33, i64 52, !6, i64 56, !38, i64 64, !38, i64 88, !42, i64 112, !42, i64 136}
!37 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!38 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !43, i64 0}
!43 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!46 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core14sc_event_queue6notifyERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(436) %0, ptr noundef nonnull align 8 dereferenceable(8) %1) unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %3)
  %5 = tail call noundef i64 @_ZNK7sc_core13sc_simcontext12change_stampEv(ptr noundef nonnull align 8 dereferenceable(344) %4)
  %6 = getelementptr inbounds i8, ptr %0, i64 424
  store i64 %5, ptr %6, align 8, !tbaa !5
  %7 = tail call noalias noundef nonnull dereferenceable(8) ptr @_Znwm(i64 noundef 8) #7
  %8 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core13sc_time_stampEv()
          to label %9 unwind label %19

9:                                                ; preds = %2
  invoke void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind nonnull writable sret(%"class.sc_core::sc_time") align 8 %7, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) %8)
          to label %10 unwind label %19

10:                                               ; preds = %9
  %11 = getelementptr inbounds i8, ptr %0, i64 240
  %12 = tail call noundef i32 @_ZNK7sc_core11sc_ppq_base4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11)
  %13 = icmp eq i32 %12, 0
  br i1 %13, label %17, label %14

14:                                               ; preds = %10
  %15 = tail call noundef ptr @_ZNK7sc_core6sc_ppqIPNS_7sc_timeEE3topEv(ptr noundef nonnull align 8 dereferenceable(24) %11)
  %16 = tail call noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 8 dereferenceable(8) %15)
  br i1 %16, label %17, label %21

17:                                               ; preds = %14, %10
  %18 = getelementptr inbounds i8, ptr %0, i64 264
  tail call void @_ZN7sc_core8sc_event6notifyERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(160) %18, ptr noundef nonnull align 8 dereferenceable(8) %1)
  br label %21

19:                                               ; preds = %9, %2
  %20 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %7, i64 noundef 8) #8
  resume { ptr, i32 } %20

21:                                               ; preds = %17, %14
  tail call void @_ZN7sc_core6sc_ppqIPNS_7sc_timeEE6insertES2_(ptr noundef nonnull align 8 dereferenceable(24) %11, ptr noundef nonnull %7)
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK7sc_core13sc_simcontext12change_stampEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #3 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_coreplERKNS_7sc_timeES2_(ptr dead_on_unwind noalias writable sret(%"class.sc_core::sc_time") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5

declare noundef nonnull align 8 dereferenceable(8) ptr @_ZN7sc_core13sc_time_stampEv() local_unnamed_addr #6

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core7sc_timeltERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZNK7sc_core6sc_ppqIPNS_7sc_timeEE3topEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

declare void @_ZN7sc_core8sc_event6notifyERKNS_7sc_timeE(ptr noundef nonnull align 8 dereferenceable(160), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #6

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core6sc_ppqIPNS_7sc_timeEE6insertES2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !45, i64 424}
!6 = !{!"_ZTSN7sc_core14sc_event_queueE", !7, i64 0, !8, i64 8, !33, i64 240, !35, i64 264, !45, i64 424, !32, i64 432}
!7 = !{!"_ZTSN7sc_core17sc_event_queue_ifE"}
!8 = !{!"_ZTSN7sc_core9sc_moduleE", !9, i64 0, !24, i64 112, !25, i64 120, !27, i64 144, !29, i64 168, !31, i64 192, !10, i64 200, !32, i64 208, !10, i64 216, !10, i64 224}
!9 = !{!"_ZTSN7sc_core9sc_objectE", !10, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !10, i64 96, !10, i64 104}
!10 = !{!"any pointer", !11, i64 0}
!11 = !{!"omnipotent char", !12, i64 0}
!12 = !{!"Simple C++ TBAA"}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !11, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !10, i64 0}
!23 = !{!"long", !11, i64 0}
!24 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveE", !10, i64 0, !26, i64 8, !10, i64 16}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !11, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !10, i64 0, !28, i64 8, !10, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !11, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !10, i64 0, !30, i64 8, !10, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !11, i64 0}
!31 = !{!"bool", !11, i64 0}
!32 = !{!"int", !11, i64 0}
!33 = !{!"_ZTSN7sc_core6sc_ppqIPNS_7sc_timeEEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core11sc_ppq_baseE", !10, i64 0, !32, i64 8, !32, i64 12, !10, i64 16}
!35 = !{!"_ZTSN7sc_core8sc_eventE", !21, i64 0, !10, i64 32, !10, i64 40, !36, i64 48, !32, i64 52, !10, i64 56, !37, i64 64, !37, i64 88, !41, i64 112, !41, i64 136}
!36 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !11, i64 0}
!37 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!41 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!45 = !{!"long long", !11, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass