; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_module.ll (ZN7sc_core9sc_module14sc_module_initEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core9sc_module14sc_module_initEv(ptr noundef nonnull align 8 dereferenceable(232) %0) #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  %6 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %5)
  %7 = call noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344) %6)
  call void @_ZN7sc_core18sc_module_registry6insertERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40) %7, ptr noundef nonnull align 8 dereferenceable(232) %5)
  %8 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %5)
  call void @_ZN7sc_core13sc_simcontext14hierarchy_pushEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(344) %8, ptr noundef %5)
  %9 = getelementptr inbounds %"class.sc_core::sc_module", ptr %5, i32 0, i32 5
  store i8 0, ptr %9, align 8, !tbaa !9
  %10 = getelementptr inbounds %"class.sc_core::sc_module", ptr %5, i32 0, i32 9
  store ptr null, ptr %10, align 8, !tbaa !32
  %11 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 24) #6
  call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #7
  %12 = getelementptr inbounds %"class.sc_core::sc_module", ptr %5, i32 0, i32 6
  store ptr %11, ptr %12, align 8, !tbaa !33
  %13 = getelementptr inbounds %"class.sc_core::sc_module", ptr %5, i32 0, i32 7
  store i32 0, ptr %13, align 8, !tbaa !34
  %14 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 8248) #6
  invoke void @_ZN7sc_core11sc_name_genC1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %14)
          to label %15 unwind label %17

15:                                               ; preds = %1
  %16 = getelementptr inbounds %"class.sc_core::sc_module", ptr %5, i32 0, i32 8
  store ptr %14, ptr %16, align 8, !tbaa !35
  ret void

17:                                               ; preds = %1
  %18 = landingpad { ptr, i32 }
          cleanup
  %19 = extractvalue { ptr, i32 } %18, 0
  store ptr %19, ptr %3, align 8
  %20 = extractvalue { ptr, i32 } %18, 1
  store i32 %20, ptr %4, align 4
  call void @_ZdlPvm(ptr noundef %14, i64 noundef 8248) #8
  br label %21

21:                                               ; preds = %17
  %22 = load ptr, ptr %3, align 8
  %23 = load i32, ptr %4, align 4
  %24 = insertvalue { ptr, i32 } poison, ptr %22, 0
  %25 = insertvalue { ptr, i32 } %24, i32 %23, 1
  resume { ptr, i32 } %25
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344)) #2 align 2

declare void @_ZN7sc_core18sc_module_registry6insertERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef nonnull align 8 dereferenceable(232)) #3

declare void @_ZN7sc_core13sc_simcontext14hierarchy_pushEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #3

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

declare void @_ZN7sc_core11sc_name_genC1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #5

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { builtin allocsize(0) }
attributes #7 = { nounwind }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !30, i64 192}
!10 = !{!"_ZTSN7sc_core9sc_moduleE", !11, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !6, i64 200, !31, i64 208, !6, i64 216, !6, i64 224}
!11 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !6, i64 96, !6, i64 104}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !7, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!22 = !{!"long", !7, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !25, i64 8, !6, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !27, i64 8, !6, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !29, i64 8, !6, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!30 = !{!"bool", !7, i64 0}
!31 = !{!"int", !7, i64 0}
!32 = !{!10, !6, i64 224}
!33 = !{!10, !6, i64 200}
!34 = !{!10, !31, i64 208}
!35 = !{!10, !6, i64 216}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core9sc_module14sc_module_initEv(ptr noundef nonnull align 8 dereferenceable(232) %0) local_unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  %3 = tail call noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344) %2)
  tail call void @_ZN7sc_core18sc_module_registry6insertERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40) %3, ptr noundef nonnull align 8 dereferenceable(232) %0)
  %4 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  tail call void @_ZN7sc_core13sc_simcontext14hierarchy_pushEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(344) %4, ptr noundef nonnull %0)
  %5 = getelementptr inbounds i8, ptr %0, i64 192
  store i8 0, ptr %5, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 224
  store ptr null, ptr %6, align 8, !tbaa !31
  %7 = tail call noalias noundef nonnull dereferenceable(24) ptr @_Znwm(i64 noundef 24) #6
  tail call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #7
  %8 = getelementptr inbounds i8, ptr %0, i64 200
  store ptr %7, ptr %8, align 8, !tbaa !32
  %9 = getelementptr inbounds i8, ptr %0, i64 208
  store i32 0, ptr %9, align 8, !tbaa !33
  %10 = tail call noalias noundef nonnull dereferenceable(8248) ptr @_Znwm(i64 noundef 8248) #6
  invoke void @_ZN7sc_core11sc_name_genC1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %10)
          to label %11 unwind label %13

11:                                               ; preds = %1
  %12 = getelementptr inbounds i8, ptr %0, i64 216
  store ptr %10, ptr %12, align 8, !tbaa !34
  ret void

13:                                               ; preds = %1
  %14 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %10, i64 noundef 8248) #8
  resume { ptr, i32 } %14
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #2 align 2

declare void @_ZN7sc_core18sc_module_registry6insertERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #3

declare void @_ZN7sc_core13sc_simcontext14hierarchy_pushEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #3

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

declare void @_ZN7sc_core11sc_name_genC1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #5

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { builtin allocsize(0) }
attributes #7 = { nounwind }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !29, i64 192}
!6 = !{!"_ZTSN7sc_core9sc_moduleE", !7, i64 0, !22, i64 112, !23, i64 120, !25, i64 144, !27, i64 168, !29, i64 192, !8, i64 200, !30, i64 208, !8, i64 216, !8, i64 224}
!7 = !{!"_ZTSN7sc_core9sc_objectE", !8, i64 8, !11, i64 16, !15, i64 40, !19, i64 64, !8, i64 96, !8, i64 104}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!15 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !21, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !8, i64 0}
!21 = !{!"long", !9, i64 0}
!22 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!23 = !{!"_ZTSN7sc_core12sc_sensitiveE", !8, i64 0, !24, i64 8, !8, i64 16}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !9, i64 0}
!25 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !8, i64 0, !26, i64 8, !8, i64 16}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !9, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !8, i64 0, !28, i64 8, !8, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !9, i64 0}
!29 = !{!"bool", !9, i64 0}
!30 = !{!"int", !9, i64 0}
!31 = !{!6, !8, i64 224}
!32 = !{!6, !8, i64 200}
!33 = !{!6, !30, i64 208}
!34 = !{!6, !8, i64 216}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass