; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_event.ll (ZN7sc_core8sc_event7triggerEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector", %"class.std::vector", %"class.std::vector.3", %"class.std::vector.3" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  %15 = alloca i32, align 4
  %16 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %17 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  %18 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 6
  %19 = call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_method_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %18) #5
  %20 = trunc i64 %19 to i32
  store i32 %20, ptr %4, align 4, !tbaa !9
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %39

22:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  %23 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 6
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef 0) #5
  store ptr %24, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  %25 = load i32, ptr %4, align 4, !tbaa !9
  %26 = sub nsw i32 %25, 1
  store i32 %26, ptr %6, align 4, !tbaa !9
  br label %27

27:                                               ; preds = %34, %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = load i32, ptr %6, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = getelementptr inbounds ptr, ptr %28, i64 %30
  %32 = load ptr, ptr %31, align 8, !tbaa !5
  store ptr %32, ptr %7, align 8, !tbaa !5
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  call void @_ZN7sc_core17sc_method_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(400) %33)
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %34

34:                                               ; preds = %27
  %35 = load i32, ptr %6, align 4, !tbaa !9
  %36 = add nsw i32 %35, -1
  store i32 %36, ptr %6, align 4, !tbaa !9
  %37 = icmp sge i32 %36, 0
  br i1 %37, label %27, label %38, !llvm.loop !11

38:                                               ; preds = %34
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  br label %39

39:                                               ; preds = %38, %1
  %40 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 7
  %41 = call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_method_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %40) #5
  %42 = trunc i64 %41 to i32
  store i32 %42, ptr %4, align 4, !tbaa !9
  %43 = icmp ne i32 %42, 0
  br i1 %43, label %44, label %85

44:                                               ; preds = %39
  %45 = load i32, ptr %4, align 4, !tbaa !9
  %46 = sub nsw i32 %45, 1
  store i32 %46, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %47 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 7
  %48 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %47, i64 noundef 0) #5
  store ptr %48, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %49

49:                                               ; preds = %77, %44
  %50 = load i32, ptr %9, align 4, !tbaa !9
  %51 = load i32, ptr %3, align 4, !tbaa !9
  %52 = icmp sle i32 %50, %51
  br i1 %52, label %54, label %53

53:                                               ; preds = %49
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %80

54:                                               ; preds = %49
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #5
  %55 = load ptr, ptr %8, align 8, !tbaa !5
  %56 = load i32, ptr %9, align 4, !tbaa !9
  %57 = sext i32 %56 to i64
  %58 = getelementptr inbounds ptr, ptr %55, i64 %57
  %59 = load ptr, ptr %58, align 8, !tbaa !5
  store ptr %59, ptr %10, align 8, !tbaa !5
  %60 = load ptr, ptr %10, align 8, !tbaa !5
  %61 = call noundef zeroext i1 @_ZN7sc_core17sc_method_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(400) %60, ptr noundef %17)
  br i1 %61, label %62, label %76

62:                                               ; preds = %54
  %63 = load ptr, ptr %8, align 8, !tbaa !5
  %64 = load i32, ptr %3, align 4, !tbaa !9
  %65 = sext i32 %64 to i64
  %66 = getelementptr inbounds ptr, ptr %63, i64 %65
  %67 = load ptr, ptr %66, align 8, !tbaa !5
  %68 = load ptr, ptr %8, align 8, !tbaa !5
  %69 = load i32, ptr %9, align 4, !tbaa !9
  %70 = sext i32 %69 to i64
  %71 = getelementptr inbounds ptr, ptr %68, i64 %70
  store ptr %67, ptr %71, align 8, !tbaa !5
  %72 = load i32, ptr %3, align 4, !tbaa !9
  %73 = add nsw i32 %72, -1
  store i32 %73, ptr %3, align 4, !tbaa !9
  %74 = load i32, ptr %9, align 4, !tbaa !9
  %75 = add nsw i32 %74, -1
  store i32 %75, ptr %9, align 4, !tbaa !9
  br label %76

76:                                               ; preds = %62, %54
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #5
  br label %77

77:                                               ; preds = %76
  %78 = load i32, ptr %9, align 4, !tbaa !9
  %79 = add nsw i32 %78, 1
  store i32 %79, ptr %9, align 4, !tbaa !9
  br label %49, !llvm.loop !13

80:                                               ; preds = %53
  %81 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 7
  %82 = load i32, ptr %3, align 4, !tbaa !9
  %83 = add nsw i32 %82, 1
  %84 = sext i32 %83 to i64
  call void @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef %84)
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  br label %85

85:                                               ; preds = %80, %39
  %86 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 8
  %87 = call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %86) #5
  %88 = trunc i64 %87 to i32
  store i32 %88, ptr %4, align 4, !tbaa !9
  %89 = icmp ne i32 %88, 0
  br i1 %89, label %90, label %107

90:                                               ; preds = %85
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #5
  %91 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 8
  %92 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %91, i64 noundef 0) #5
  store ptr %92, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  %93 = load i32, ptr %4, align 4, !tbaa !9
  %94 = sub nsw i32 %93, 1
  store i32 %94, ptr %12, align 4, !tbaa !9
  br label %95

95:                                               ; preds = %102, %90
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #5
  %96 = load ptr, ptr %11, align 8, !tbaa !5
  %97 = load i32, ptr %12, align 4, !tbaa !9
  %98 = sext i32 %97 to i64
  %99 = getelementptr inbounds ptr, ptr %96, i64 %98
  %100 = load ptr, ptr %99, align 8, !tbaa !5
  store ptr %100, ptr %13, align 8, !tbaa !5
  %101 = load ptr, ptr %13, align 8, !tbaa !5
  call void @_ZN7sc_core17sc_thread_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(404) %101)
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #5
  br label %102

102:                                              ; preds = %95
  %103 = load i32, ptr %12, align 4, !tbaa !9
  %104 = add nsw i32 %103, -1
  store i32 %104, ptr %12, align 4, !tbaa !9
  %105 = icmp sge i32 %104, 0
  br i1 %105, label %95, label %106, !llvm.loop !14

106:                                              ; preds = %102
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #5
  br label %107

107:                                              ; preds = %106, %85
  %108 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 9
  %109 = call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %108) #5
  %110 = trunc i64 %109 to i32
  store i32 %110, ptr %4, align 4, !tbaa !9
  %111 = icmp ne i32 %110, 0
  br i1 %111, label %112, label %153

112:                                              ; preds = %107
  %113 = load i32, ptr %4, align 4, !tbaa !9
  %114 = sub nsw i32 %113, 1
  store i32 %114, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #5
  %115 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 9
  %116 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %115, i64 noundef 0) #5
  store ptr %116, ptr %14, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #5
  store i32 0, ptr %15, align 4, !tbaa !9
  br label %117

117:                                              ; preds = %145, %112
  %118 = load i32, ptr %15, align 4, !tbaa !9
  %119 = load i32, ptr %3, align 4, !tbaa !9
  %120 = icmp sle i32 %118, %119
  br i1 %120, label %122, label %121

121:                                              ; preds = %117
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #5
  br label %148

122:                                              ; preds = %117
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #5
  %123 = load ptr, ptr %14, align 8, !tbaa !5
  %124 = load i32, ptr %15, align 4, !tbaa !9
  %125 = sext i32 %124 to i64
  %126 = getelementptr inbounds ptr, ptr %123, i64 %125
  %127 = load ptr, ptr %126, align 8, !tbaa !5
  store ptr %127, ptr %16, align 8, !tbaa !5
  %128 = load ptr, ptr %16, align 8, !tbaa !5
  %129 = call noundef zeroext i1 @_ZN7sc_core17sc_thread_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(404) %128, ptr noundef %17)
  br i1 %129, label %130, label %144

130:                                              ; preds = %122
  %131 = load ptr, ptr %14, align 8, !tbaa !5
  %132 = load i32, ptr %3, align 4, !tbaa !9
  %133 = sext i32 %132 to i64
  %134 = getelementptr inbounds ptr, ptr %131, i64 %133
  %135 = load ptr, ptr %134, align 8, !tbaa !5
  %136 = load ptr, ptr %14, align 8, !tbaa !5
  %137 = load i32, ptr %15, align 4, !tbaa !9
  %138 = sext i32 %137 to i64
  %139 = getelementptr inbounds ptr, ptr %136, i64 %138
  store ptr %135, ptr %139, align 8, !tbaa !5
  %140 = load i32, ptr %15, align 4, !tbaa !9
  %141 = add nsw i32 %140, -1
  store i32 %141, ptr %15, align 4, !tbaa !9
  %142 = load i32, ptr %3, align 4, !tbaa !9
  %143 = add nsw i32 %142, -1
  store i32 %143, ptr %3, align 4, !tbaa !9
  br label %144

144:                                              ; preds = %130, %122
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #5
  br label %145

145:                                              ; preds = %144
  %146 = load i32, ptr %15, align 4, !tbaa !9
  %147 = add nsw i32 %146, 1
  store i32 %147, ptr %15, align 4, !tbaa !9
  br label %117, !llvm.loop !15

148:                                              ; preds = %121
  %149 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 9
  %150 = load i32, ptr %3, align 4, !tbaa !9
  %151 = add nsw i32 %150, 1
  %152 = sext i32 %151 to i64
  call void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %149, i64 noundef %152)
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #5
  br label %153

153:                                              ; preds = %148, %107
  %154 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 3
  store i32 0, ptr %154, align 8, !tbaa !16
  %155 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 4
  store i32 -1, ptr %155, align 4, !tbaa !30
  %156 = getelementptr inbounds %"class.sc_core::sc_event", ptr %17, i32 0, i32 5
  store ptr null, ptr %156, align 8, !tbaa !31
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_method_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core17sc_method_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(400)) #3 align 2

declare noundef zeroext i1 @_ZN7sc_core17sc_method_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(400), ptr noundef) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core17sc_thread_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(404)) #3 align 2

declare noundef zeroext i1 @_ZN7sc_core17sc_thread_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(404), ptr noundef) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = !{!17, !21, i64 48}
!17 = !{!"_ZTSN7sc_core8sc_eventE", !18, i64 0, !6, i64 32, !6, i64 40, !21, i64 48, !10, i64 52, !6, i64 56, !22, i64 64, !22, i64 88, !26, i64 112, !26, i64 136}
!18 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !19, i64 0, !20, i64 8, !7, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!20 = !{!"long", !7, i64 0}
!21 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!17, !10, i64 52}
!31 = !{!17, !6, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_event7triggerEv(ptr noundef nonnull align 8 dereferenceable(160) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 64
  %3 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_method_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %4 = and i64 %3, 4294967295
  %.not = icmp eq i64 %4, 0
  br i1 %.not, label %.loopexit53, label %5

5:                                                ; preds = %1
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 0) #4
  %sext = shl i64 %3, 32
  %7 = ashr exact i64 %sext, 32
  br label %8

8:                                                ; preds = %8, %5
  %indvars.iv = phi i64 [ %indvars.iv.next, %8 ], [ %7, %5 ]
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %9 = getelementptr inbounds ptr, ptr %6, i64 %indvars.iv.next
  %10 = load ptr, ptr %9, align 8, !tbaa !5
  tail call void @_ZN7sc_core17sc_method_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(400) %10)
  %11 = icmp sgt i64 %indvars.iv, 1
  br i1 %11, label %8, label %.loopexit53, !llvm.loop !9

.loopexit53:                                      ; preds = %8, %1
  %12 = getelementptr inbounds i8, ptr %0, i64 88
  %13 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_method_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %14 = trunc i64 %13 to i32
  %.not48 = icmp eq i32 %14, 0
  br i1 %.not48, label %32, label %15

15:                                               ; preds = %.loopexit53
  %16 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef 0) #4
  %.not4954 = icmp slt i32 %14, 1
  br i1 %.not4954, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %15
  %17 = add nsw i32 %14, -1
  br label %.lr.ph

._crit_edge.loopexit:                             ; preds = %30
  %18 = add nsw i32 %.1, 1
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %15
  %.0.lcssa = phi i32 [ %14, %15 ], [ %18, %._crit_edge.loopexit ]
  %19 = sext i32 %.0.lcssa to i64
  tail call void @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %19)
  br label %32

.lr.ph:                                           ; preds = %.lr.ph.preheader, %30
  %.056 = phi i32 [ %.1, %30 ], [ %17, %.lr.ph.preheader ]
  %.04255 = phi i32 [ %31, %30 ], [ 0, %.lr.ph.preheader ]
  %20 = sext i32 %.04255 to i64
  %21 = getelementptr inbounds ptr, ptr %16, i64 %20
  %22 = load ptr, ptr %21, align 8, !tbaa !5
  %23 = tail call noundef zeroext i1 @_ZN7sc_core17sc_method_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(400) %22, ptr noundef nonnull %0)
  br i1 %23, label %24, label %30

24:                                               ; preds = %.lr.ph
  %25 = sext i32 %.056 to i64
  %26 = getelementptr inbounds ptr, ptr %16, i64 %25
  %27 = load ptr, ptr %26, align 8, !tbaa !5
  store ptr %27, ptr %21, align 8, !tbaa !5
  %28 = add nsw i32 %.056, -1
  %29 = add nsw i32 %.04255, -1
  br label %30

30:                                               ; preds = %24, %.lr.ph
  %.143 = phi i32 [ %29, %24 ], [ %.04255, %.lr.ph ]
  %.1 = phi i32 [ %28, %24 ], [ %.056, %.lr.ph ]
  %31 = add nsw i32 %.143, 1
  %.not49.not = icmp slt i32 %.143, %.1
  br i1 %.not49.not, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !11

32:                                               ; preds = %._crit_edge, %.loopexit53
  %33 = getelementptr inbounds i8, ptr %0, i64 112
  %34 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %33) #4
  %35 = and i64 %34, 4294967295
  %.not50 = icmp eq i64 %35, 0
  br i1 %.not50, label %.loopexit, label %36

36:                                               ; preds = %32
  %37 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef 0) #4
  %sext68 = shl i64 %34, 32
  %38 = ashr exact i64 %sext68, 32
  br label %39

39:                                               ; preds = %39, %36
  %indvars.iv65 = phi i64 [ %indvars.iv.next66, %39 ], [ %38, %36 ]
  %indvars.iv.next66 = add nsw i64 %indvars.iv65, -1
  %40 = getelementptr inbounds ptr, ptr %37, i64 %indvars.iv.next66
  %41 = load ptr, ptr %40, align 8, !tbaa !5
  tail call void @_ZN7sc_core17sc_thread_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(404) %41)
  %42 = icmp sgt i64 %indvars.iv65, 1
  br i1 %42, label %39, label %.loopexit, !llvm.loop !12

.loopexit:                                        ; preds = %39, %32
  %43 = getelementptr inbounds i8, ptr %0, i64 136
  %44 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %43) #4
  %45 = trunc i64 %44 to i32
  %.not51 = icmp eq i32 %45, 0
  br i1 %.not51, label %63, label %46

46:                                               ; preds = %.loopexit
  %47 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef 0) #4
  %.not5257 = icmp slt i32 %45, 1
  br i1 %.not5257, label %._crit_edge62, label %.lr.ph61.preheader

.lr.ph61.preheader:                               ; preds = %46
  %48 = add nsw i32 %45, -1
  br label %.lr.ph61

._crit_edge62.loopexit:                           ; preds = %61
  %49 = add nsw i32 %.3, 1
  br label %._crit_edge62

._crit_edge62:                                    ; preds = %._crit_edge62.loopexit, %46
  %.2.lcssa = phi i32 [ %45, %46 ], [ %49, %._crit_edge62.loopexit ]
  %50 = sext i32 %.2.lcssa to i64
  tail call void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %50)
  br label %63

.lr.ph61:                                         ; preds = %.lr.ph61.preheader, %61
  %.259 = phi i32 [ %.3, %61 ], [ %48, %.lr.ph61.preheader ]
  %.03858 = phi i32 [ %62, %61 ], [ 0, %.lr.ph61.preheader ]
  %51 = sext i32 %.03858 to i64
  %52 = getelementptr inbounds ptr, ptr %47, i64 %51
  %53 = load ptr, ptr %52, align 8, !tbaa !5
  %54 = tail call noundef zeroext i1 @_ZN7sc_core17sc_thread_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(404) %53, ptr noundef nonnull %0)
  br i1 %54, label %55, label %61

55:                                               ; preds = %.lr.ph61
  %56 = sext i32 %.259 to i64
  %57 = getelementptr inbounds ptr, ptr %47, i64 %56
  %58 = load ptr, ptr %57, align 8, !tbaa !5
  store ptr %58, ptr %52, align 8, !tbaa !5
  %59 = add nsw i32 %.03858, -1
  %60 = add nsw i32 %.259, -1
  br label %61

61:                                               ; preds = %55, %.lr.ph61
  %.139 = phi i32 [ %59, %55 ], [ %.03858, %.lr.ph61 ]
  %.3 = phi i32 [ %60, %55 ], [ %.259, %.lr.ph61 ]
  %62 = add nsw i32 %.139, 1
  %.not52.not = icmp slt i32 %.139, %.3
  br i1 %.not52.not, label %.lr.ph61, label %._crit_edge62.loopexit, !llvm.loop !13

63:                                               ; preds = %._crit_edge62, %.loopexit
  %64 = getelementptr inbounds i8, ptr %0, i64 48
  store i32 0, ptr %64, align 8, !tbaa !14
  %65 = getelementptr inbounds i8, ptr %0, i64 52
  store i32 -1, ptr %65, align 4, !tbaa !29
  %66 = getelementptr inbounds i8, ptr %0, i64 56
  store ptr null, ptr %66, align 8, !tbaa !30
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_method_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_method_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core17sc_method_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(400)) local_unnamed_addr #2 align 2

declare noundef zeroext i1 @_ZN7sc_core17sc_method_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(400), ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core17sc_thread_process14trigger_staticEv(ptr noundef nonnull align 8 dereferenceable(404)) local_unnamed_addr #2 align 2

declare noundef zeroext i1 @_ZN7sc_core17sc_thread_process15trigger_dynamicEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(404), ptr noundef) local_unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = !{!15, !19, i64 48}
!15 = !{!"_ZTSN7sc_core8sc_eventE", !16, i64 0, !6, i64 32, !6, i64 40, !19, i64 48, !20, i64 52, !6, i64 56, !21, i64 64, !21, i64 88, !25, i64 112, !25, i64 136}
!16 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !17, i64 0, !18, i64 8, !7, i64 16}
!17 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!18 = !{!"long", !7, i64 0}
!19 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!20 = !{!"int", !7, i64 0}
!21 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!15, !20, i64 52}
!30 = !{!15, !6, i64 56}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass