; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_thread_process)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_b" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.8", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.13", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8, [3 x i8] }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTIN7sc_core9sc_objectE = external constant ptr
@_ZTIN7sc_core12sc_process_bE = external constant ptr
@_ZN7sc_core32sc_allow_process_control_cornersE = external global i8, align 1
@_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E = external constant [0 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [46 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core17sc_thread_process15disable_processENS_28sc_descendant_inclusion_infoE(ptr noundef nonnull align 8 dereferenceable(404) %0, i32 noundef %1) unnamed_addr #3 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %9 = load ptr, ptr %3, align 8
  %10 = load i32, ptr %4, align 4, !tbaa !9
  %11 = icmp eq i32 %10, 1
  br i1 %11, label %12, label %50

12:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #7
  %13 = load ptr, ptr %9, align 8, !tbaa !11
  %14 = getelementptr inbounds ptr, ptr %13, i64 5
  %15 = load ptr, ptr %14, align 8
  %16 = call noundef nonnull align 8 dereferenceable(24) ptr %15(ptr noundef nonnull align 8 dereferenceable(357) %9)
  store ptr %16, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #7
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = call noundef i64 @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #7
  %19 = trunc i64 %18 to i32
  store i32 %19, ptr %6, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #7
  store i32 0, ptr %7, align 4, !tbaa !13
  br label %20

20:                                               ; preds = %46, %12
  %21 = load i32, ptr %7, align 4, !tbaa !13
  %22 = load i32, ptr %6, align 4, !tbaa !13
  %23 = icmp slt i32 %21, %22
  br i1 %23, label %25, label %24

24:                                               ; preds = %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #7
  br label %49

25:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #7
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = load i32, ptr %7, align 4, !tbaa !13
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %28) #7
  %30 = load ptr, ptr %29, align 8, !tbaa !5
  %31 = icmp eq ptr %30, null
  br i1 %31, label %34, label %32

32:                                               ; preds = %25
  %33 = call ptr @__dynamic_cast(ptr %30, ptr @_ZTIN7sc_core9sc_objectE, ptr @_ZTIN7sc_core12sc_process_bE, i64 0) #7
  br label %35

34:                                               ; preds = %25
  br label %35

35:                                               ; preds = %34, %32
  %36 = phi ptr [ %33, %32 ], [ null, %34 ]
  store ptr %36, ptr %8, align 8, !tbaa !5
  %37 = load ptr, ptr %8, align 8, !tbaa !5
  %38 = icmp ne ptr %37, null
  br i1 %38, label %39, label %45

39:                                               ; preds = %35
  %40 = load ptr, ptr %8, align 8, !tbaa !5
  %41 = load i32, ptr %4, align 4, !tbaa !9
  %42 = load ptr, ptr %40, align 8, !tbaa !11
  %43 = getelementptr inbounds ptr, ptr %42, i64 16
  %44 = load ptr, ptr %43, align 8
  call void %44(ptr noundef nonnull align 8 dereferenceable(357) %40, i32 noundef %41)
  br label %45

45:                                               ; preds = %39, %35
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #7
  br label %46

46:                                               ; preds = %45
  %47 = load i32, ptr %7, align 4, !tbaa !13
  %48 = add nsw i32 %47, 1
  store i32 %48, ptr %7, align 4, !tbaa !13
  br label %20, !llvm.loop !15

49:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #7
  br label %50

50:                                               ; preds = %49, %2
  %51 = load i8, ptr @_ZN7sc_core32sc_allow_process_control_cornersE, align 1, !tbaa !17, !range !19, !noundef !20
  %52 = trunc i8 %51 to i1
  br i1 %52, label %59, label %53

53:                                               ; preds = %50
  %54 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 40
  %55 = load i32, ptr %54, align 8, !tbaa !21
  switch i32 %55, label %57 [
    i32 7, label %56
    i32 5, label %56
    i32 6, label %56
    i32 4, label %56
  ]

56:                                               ; preds = %53, %53, %53, %53
  call void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357) %9, ptr noundef @_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E, ptr noundef @.str.1)
  br label %58

57:                                               ; preds = %53
  br label %58

58:                                               ; preds = %57, %56
  br label %59

59:                                               ; preds = %58, %50
  %60 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 29
  %61 = load i32, ptr %60, align 8, !tbaa !46
  %62 = or i32 %61, 1
  %63 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 29
  store i32 %62, ptr %63, align 8, !tbaa !46
  %64 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %65 = call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %64)
  br i1 %65, label %72, label %66

66:                                               ; preds = %59
  %67 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 29
  %68 = load i32, ptr %67, align 8, !tbaa !46
  %69 = or i32 %68, 2
  %70 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %9, i32 0, i32 29
  store i32 %69, ptr %70, align 8, !tbaa !46
  %71 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %9)
  call void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %71, ptr noundef %9)
  br label %72

72:                                               ; preds = %66, %59
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) #4

declare void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357), ptr noundef, ptr noundef) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) #6

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind willreturn memory(read) }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN7sc_core28sc_descendant_inclusion_infoE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"vtable pointer", !8, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = !{!18, !18, i64 0}
!18 = !{!"bool", !7, i64 0}
!19 = !{i8 0, i8 2}
!20 = !{}
!21 = !{!22, !45, i64 352}
!22 = !{!"_ZTSN7sc_core12sc_process_bE", !23, i64 0, !6, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !14, i64 132, !18, i64 136, !18, i64 137, !6, i64 144, !14, i64 152, !6, i64 160, !6, i64 168, !18, i64 176, !18, i64 177, !18, i64 178, !18, i64 179, !6, i64 184, !6, i64 192, !35, i64 200, !14, i64 204, !36, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !14, i64 280, !40, i64 288, !18, i64 312, !6, i64 320, !6, i64 328, !44, i64 336, !18, i64 340, !6, i64 344, !45, i64 352, !18, i64 356}
!23 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !24, i64 16, !28, i64 40, !32, i64 64, !6, i64 96, !6, i64 104}
!24 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!28 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !33, i64 0, !34, i64 8, !7, i64 16}
!33 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!34 = !{!"long", !7, i64 0}
!35 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!36 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!40 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !41, i64 0}
!41 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!44 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!45 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!46 = !{!22, !14, i64 280}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN7sc_core9sc_objectE = external constant ptr
@_ZTIN7sc_core12sc_process_bE = external constant ptr
@_ZN7sc_core32sc_allow_process_control_cornersE = external local_unnamed_addr global i8, align 1
@_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E = external constant [0 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [46 x i8], align 1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core17sc_thread_process15disable_processENS_28sc_descendant_inclusion_infoE(ptr noundef nonnull align 8 dereferenceable(404) %0, i32 noundef %1) unnamed_addr #2 align 2 {
  %3 = icmp eq i32 %1, 1
  br i1 %3, label %4, label %.loopexit

4:                                                ; preds = %2
  %5 = load ptr, ptr %0, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %5, i64 40
  %7 = load ptr, ptr %6, align 8
  %8 = tail call noundef nonnull align 8 dereferenceable(24) ptr %7(ptr noundef nonnull align 8 dereferenceable(357) %0)
  %9 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %8) #6
  %10 = trunc i64 %9 to i32
  %11 = icmp sgt i32 %10, 0
  br i1 %11, label %.lr.ph.preheader, label %.loopexit

.lr.ph.preheader:                                 ; preds = %4
  %wide.trip.count = and i64 %9, 2147483647
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.thread
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next, %.thread ]
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %indvars.iv) #6
  %13 = load ptr, ptr %12, align 8, !tbaa !8
  %14 = icmp eq ptr %13, null
  br i1 %14, label %.thread, label %15

15:                                               ; preds = %.lr.ph
  %16 = tail call ptr @__dynamic_cast(ptr nonnull %13, ptr nonnull @_ZTIN7sc_core9sc_objectE, ptr nonnull @_ZTIN7sc_core12sc_process_bE, i64 0) #6
  %.not = icmp eq ptr %16, null
  br i1 %.not, label %.thread, label %17

17:                                               ; preds = %15
  %18 = load ptr, ptr %16, align 8, !tbaa !5
  %19 = getelementptr inbounds i8, ptr %18, i64 128
  %20 = load ptr, ptr %19, align 8
  tail call void %20(ptr noundef nonnull align 8 dereferenceable(357) %16, i32 noundef 1)
  br label %.thread

.thread:                                          ; preds = %.lr.ph, %17, %15
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.loopexit, label %.lr.ph, !llvm.loop !11

.loopexit:                                        ; preds = %.thread, %4, %2
  %21 = load i8, ptr @_ZN7sc_core32sc_allow_process_control_cornersE, align 1, !tbaa !13, !range !15, !noundef !16
  %22 = trunc nuw i8 %21 to i1
  br i1 %22, label %28, label %23

23:                                               ; preds = %.loopexit
  %24 = getelementptr inbounds i8, ptr %0, i64 352
  %25 = load i32, ptr %24, align 8, !tbaa !17
  %26 = and i32 %25, -4
  %switch = icmp eq i32 %26, 4
  br i1 %switch, label %27, label %28

27:                                               ; preds = %23
  tail call void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357) %0, ptr noundef nonnull @_ZN7sc_core34SC_ID_PROCESS_CONTROL_CORNER_CASE_E, ptr noundef nonnull @.str.1)
  br label %28

28:                                               ; preds = %23, %27, %.loopexit
  %29 = getelementptr inbounds i8, ptr %0, i64 280
  %30 = load i32, ptr %29, align 8, !tbaa !43
  %31 = or i32 %30, 1
  store i32 %31, ptr %29, align 8, !tbaa !43
  %32 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %33 = tail call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %32)
  br i1 %33, label %38, label %34

34:                                               ; preds = %28
  %35 = load i32, ptr %29, align 8, !tbaa !43
  %36 = or i32 %35, 2
  store i32 %36, ptr %29, align 8, !tbaa !43
  %37 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  tail call void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %37, ptr noundef nonnull %0)
  br label %38

38:                                               ; preds = %34, %28
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIPN7sc_core9sc_objectESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nofree nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) local_unnamed_addr #3

declare void @_ZNK7sc_core12sc_process_b12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(357), ptr noundef, ptr noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) local_unnamed_addr #5

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nofree nounwind willreturn memory(read) }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !10, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = !{!18, !42, i64 352}
!18 = !{!"_ZTSN7sc_core12sc_process_bE", !19, i64 0, !9, i64 112, !31, i64 120, !31, i64 124, !31, i64 128, !31, i64 132, !14, i64 136, !14, i64 137, !9, i64 144, !31, i64 152, !9, i64 160, !9, i64 168, !14, i64 176, !14, i64 177, !14, i64 178, !14, i64 179, !9, i64 184, !9, i64 192, !32, i64 200, !31, i64 204, !33, i64 208, !9, i64 232, !9, i64 240, !9, i64 248, !9, i64 256, !10, i64 264, !31, i64 280, !37, i64 288, !14, i64 312, !9, i64 320, !9, i64 328, !41, i64 336, !14, i64 340, !9, i64 344, !42, i64 352, !14, i64 356}
!19 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !20, i64 16, !24, i64 40, !28, i64 64, !9, i64 96, !9, i64 104}
!20 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!24 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!28 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !29, i64 0, !30, i64 8, !10, i64 16}
!29 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!30 = !{!"long", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !10, i64 0}
!33 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!37 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!41 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !10, i64 0}
!42 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !10, i64 0}
!43 = !{!18, !31, i64 280}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass