; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/OptionRomPkg/Bus/Usb (Ax88772MulticastSet)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NIC_DEVICE = type { i64, ptr, ptr, %struct._EFI_SIMPLE_NETWORK_PROTOCOL, %struct.EFI_SIMPLE_NETWORK_MODE, i8, ptr, i16, i8, i8, i8, i8, i8, ptr, i64, ptr, ptr, ptr, [2 x i32], ptr }
%struct._EFI_SIMPLE_NETWORK_PROTOCOL = type { i64, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%struct.EFI_SIMPLE_NETWORK_MODE = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x %struct.EFI_MAC_ADDRESS], %struct.EFI_MAC_ADDRESS, %struct.EFI_MAC_ADDRESS, %struct.EFI_MAC_ADDRESS, i8, i8, i8, i8, i8 }
%struct.EFI_MAC_ADDRESS = type { [32 x i8] }

@.str = external hidden unnamed_addr constant [85 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local i32 @Ax88772Crc(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local void @Ax88772MulticastSet(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = call i32 @Ax88772Crc(ptr noundef %8)
  store i32 %9, ptr %6, align 4, !tbaa !9
  %10 = load i32, ptr %6, align 4, !tbaa !9
  %11 = lshr i32 %10, 26
  store i32 %11, ptr %5, align 4, !tbaa !9
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = icmp ugt i32 32, %12
  br i1 %13, label %14, label %23

14:                                               ; preds = %2
  %15 = load i32, ptr %5, align 4, !tbaa !9
  %16 = shl i32 1, %15
  store i32 %16, ptr %7, align 4, !tbaa !9
  %17 = load i32, ptr %7, align 4, !tbaa !9
  %18 = load ptr, ptr %3, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.NIC_DEVICE, ptr %18, i32 0, i32 18
  %20 = getelementptr inbounds [2 x i32], ptr %19, i64 0, i64 0
  %21 = load i32, ptr %20, align 8, !tbaa !9
  %22 = or i32 %21, %17
  store i32 %22, ptr %20, align 8, !tbaa !9
  br label %33

23:                                               ; preds = %2
  %24 = load i32, ptr %5, align 4, !tbaa !9
  %25 = sub i32 %24, 32
  %26 = shl i32 1, %25
  store i32 %26, ptr %7, align 4, !tbaa !9
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = load ptr, ptr %3, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.NIC_DEVICE, ptr %28, i32 0, i32 18
  %30 = getelementptr inbounds [2 x i32], ptr %29, i64 0, i64 1
  %31 = load i32, ptr %30, align 4, !tbaa !9
  %32 = or i32 %31, %27
  store i32 %32, ptr %30, align 4, !tbaa !9
  br label %33

33:                                               ; preds = %23, %14
  br label %34

34:                                               ; preds = %33
  %35 = call zeroext i8 @DebugPrintEnabled()
  %36 = icmp ne i8 %35, 0
  br i1 %36, label %37, label %71

37:                                               ; preds = %34
  br label %38

38:                                               ; preds = %37
  %39 = call zeroext i8 @DebugPrintLevelEnabled(i64 noundef 536870976)
  %40 = icmp ne i8 %39, 0
  br i1 %40, label %41, label %68

41:                                               ; preds = %38
  %42 = load ptr, ptr %4, align 8, !tbaa !5
  %43 = getelementptr inbounds i8, ptr %42, i64 0
  %44 = load i8, ptr %43, align 1, !tbaa !11
  %45 = zext i8 %44 to i32
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = getelementptr inbounds i8, ptr %46, i64 1
  %48 = load i8, ptr %47, align 1, !tbaa !11
  %49 = zext i8 %48 to i32
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds i8, ptr %50, i64 2
  %52 = load i8, ptr %51, align 1, !tbaa !11
  %53 = zext i8 %52 to i32
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = getelementptr inbounds i8, ptr %54, i64 3
  %56 = load i8, ptr %55, align 1, !tbaa !11
  %57 = zext i8 %56 to i32
  %58 = load ptr, ptr %4, align 8, !tbaa !5
  %59 = getelementptr inbounds i8, ptr %58, i64 4
  %60 = load i8, ptr %59, align 1, !tbaa !11
  %61 = zext i8 %60 to i32
  %62 = load ptr, ptr %4, align 8, !tbaa !5
  %63 = getelementptr inbounds i8, ptr %62, i64 5
  %64 = load i8, ptr %63, align 1, !tbaa !11
  %65 = zext i8 %64 to i32
  %66 = load i32, ptr %6, align 4, !tbaa !9
  %67 = load i32, ptr %5, align 4, !tbaa !9
  call void (i64, ptr, ...) @DebugPrint(i64 noundef 536870976, ptr noundef @.str, i32 noundef %45, i32 noundef %49, i32 noundef %53, i32 noundef %57, i32 noundef %61, i32 noundef %65, i32 noundef %66, i32 noundef %67)
  br label %68

68:                                               ; preds = %41, %38
  br label %69

69:                                               ; preds = %68
  br label %70

70:                                               ; preds = %69
  br label %71

71:                                               ; preds = %70, %34
  br label %72

72:                                               ; preds = %71
  br label %73

73:                                               ; preds = %72
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret void
}

declare zeroext i8 @DebugPrintEnabled() #2

declare zeroext i8 @DebugPrintLevelEnabled(i64 noundef) #2

declare void @DebugPrint(i64 noundef, ptr noundef, ...) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [85 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local i32 @Ax88772Crc(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @Ax88772MulticastSet(ptr nocapture noundef %0, ptr noundef %1) local_unnamed_addr #0 {
  %3 = tail call i32 @Ax88772Crc(ptr noundef %1)
  %4 = lshr i32 %3, 26
  %5 = icmp sgt i32 %3, -1
  br i1 %5, label %6, label %11

6:                                                ; preds = %2
  %7 = shl nuw i32 1, %4
  %8 = getelementptr inbounds i8, ptr %0, i64 872
  %9 = load i32, ptr %8, align 8, !tbaa !5
  %10 = or i32 %9, %7
  store i32 %10, ptr %8, align 8, !tbaa !5
  br label %17

11:                                               ; preds = %2
  %12 = add nsw i32 %4, -32
  %13 = shl nuw i32 1, %12
  %14 = getelementptr inbounds i8, ptr %0, i64 876
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = or i32 %15, %13
  store i32 %16, ptr %14, align 4, !tbaa !5
  br label %17

17:                                               ; preds = %6, %11
  %18 = tail call zeroext i8 @DebugPrintEnabled() #2
  %.not = icmp eq i8 %18, 0
  br i1 %.not, label %39, label %19

19:                                               ; preds = %17
  %20 = tail call zeroext i8 @DebugPrintLevelEnabled(i64 noundef 536870976) #2
  %.not16 = icmp eq i8 %20, 0
  br i1 %.not16, label %39, label %21

21:                                               ; preds = %19
  %22 = load i8, ptr %1, align 1, !tbaa !9
  %23 = zext i8 %22 to i32
  %24 = getelementptr inbounds i8, ptr %1, i64 1
  %25 = load i8, ptr %24, align 1, !tbaa !9
  %26 = zext i8 %25 to i32
  %27 = getelementptr inbounds i8, ptr %1, i64 2
  %28 = load i8, ptr %27, align 1, !tbaa !9
  %29 = zext i8 %28 to i32
  %30 = getelementptr inbounds i8, ptr %1, i64 3
  %31 = load i8, ptr %30, align 1, !tbaa !9
  %32 = zext i8 %31 to i32
  %33 = getelementptr inbounds i8, ptr %1, i64 4
  %34 = load i8, ptr %33, align 1, !tbaa !9
  %35 = zext i8 %34 to i32
  %36 = getelementptr inbounds i8, ptr %1, i64 5
  %37 = load i8, ptr %36, align 1, !tbaa !9
  %38 = zext i8 %37 to i32
  tail call void (i64, ptr, ...) @DebugPrint(i64 noundef 536870976, ptr noundef nonnull @.str, i32 noundef %23, i32 noundef %26, i32 noundef %29, i32 noundef %32, i32 noundef %35, i32 noundef %38, i32 noundef %3, i32 noundef %4) #2
  br label %39

39:                                               ; preds = %19, %21, %17
  ret void
}

declare zeroext i8 @DebugPrintEnabled() local_unnamed_addr #1

declare zeroext i8 @DebugPrintLevelEnabled(i64 noundef) local_unnamed_addr #1

declare void @DebugPrint(i64 noundef, ptr noundef, ...) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass