; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/v1.0/resolved_sig/resolved_sig.ll (ZN7stimgen5entryEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.sc_dt::sc_bitref" = type { %"class.sc_dt::sc_bitref_r.base", [4 x i8] }
%"class.sc_dt::sc_bitref_r.base" = type <{ ptr, i32 }>
%"class.sc_dt::sc_lv" = type { %"class.sc_dt::sc_lv_base" }
%"class.sc_dt::sc_lv_base" = type { %"class.sc_dt::sc_proxy", i32, i32, ptr, ptr }
%"class.sc_dt::sc_proxy" = type { ptr }
%"class.sc_dt::sc_logic" = type { i32 }
%struct.stimgen = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.13", %"class.sc_core::sc_out", %"class.sc_core::sc_out", %"class.sc_core::sc_out.36", %"class.sc_core::sc_out_rv" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout.28" }
%"class.sc_core::sc_inout.28" = type { %"class.sc_core::sc_port.29", ptr, ptr, ptr }
%"class.sc_core::sc_port.29" = type { %"class.sc_core::sc_port_b.30" }
%"class.sc_core::sc_port_b.30" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.31" }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.36" = type { %"class.sc_core::sc_inout.37" }
%"class.sc_core::sc_inout.37" = type { %"class.sc_core::sc_port.38", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.38" = type { %"class.sc_core::sc_port_b.39" }
%"class.sc_core::sc_port_b.39" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.40" }
%"class.std::vector.40" = type { %"struct.std::_Vector_base.41" }
%"struct.std::_Vector_base.41" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out_rv" = type { %"class.sc_core::sc_inout_rv" }
%"class.sc_core::sc_inout_rv" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_lv<8>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZSt4cout = external global %"class.std::basic_ostream", align 8
@.str.3 = external hidden unnamed_addr constant [17 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN5sc_dtlsINS_10sc_lv_baseEEERSoS2_RKNS_8sc_proxyIT_EE(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_bitref") align 8, ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSEi(ptr noundef nonnull align 8 dereferenceable(12), i32 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt5sc_lvILi8EEEE5writeERKS3_(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 8 dereferenceable(32)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7stimgen5entryEv(ptr noundef nonnull align 8 dereferenceable(1304) %0) #1 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca %"class.sc_dt::sc_lv", align 8
  %8 = alloca %"class.sc_dt::sc_logic", align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca %"class.sc_dt::sc_bitref", align 8
  %12 = alloca %"class.sc_dt::sc_bitref", align 8
  %13 = alloca %"class.sc_dt::sc_bitref", align 8
  %14 = alloca %"class.sc_dt::sc_bitref", align 8
  %15 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %16 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  %17 = getelementptr inbounds %struct.stimgen, ptr %16, i32 0, i32 5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #5
  store i8 0, ptr %5, align 1, !tbaa !9
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %17, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #5
  store i32 0, ptr %3, align 4, !tbaa !11
  br label %18

18:                                               ; preds = %95, %1
  %19 = load i32, ptr %3, align 4, !tbaa !11
  %20 = icmp slt i32 %19, 6
  br i1 %20, label %21, label %98

21:                                               ; preds = %18
  store i32 0, ptr %4, align 4, !tbaa !11
  br label %22

22:                                               ; preds = %58, %21
  %23 = load i32, ptr %4, align 4, !tbaa !11
  %24 = icmp slt i32 %23, 6
  br i1 %24, label %25, label %94

25:                                               ; preds = %22
  %26 = getelementptr inbounds %struct.stimgen, ptr %16, i32 0, i32 3
  call void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176) %26, ptr noundef nonnull align 4 dereferenceable(4) %3)
  %27 = getelementptr inbounds %struct.stimgen, ptr %16, i32 0, i32 4
  call void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176) %27, ptr noundef nonnull align 4 dereferenceable(4) %4)
  %28 = getelementptr inbounds %struct.stimgen, ptr %16, i32 0, i32 5
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #5
  store i8 1, ptr %6, align 1, !tbaa !9
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %28, ptr noundef nonnull align 1 dereferenceable(1) %6)
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #5
  call void @llvm.lifetime.start.p0(i64 32, ptr %7) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  %29 = load i32, ptr %3, align 4, !tbaa !11
  %30 = srem i32 %29, 4
  call void @_ZN5sc_dt8sc_logicC2Ei(ptr noundef nonnull align 4 dereferenceable(4) %8, i32 noundef %30)
  invoke void @_ZN5sc_dt5sc_lvILi8EEC2ERKNS_8sc_logicE(ptr noundef nonnull align 8 dereferenceable(32) %7, ptr noundef nonnull align 4 dereferenceable(4) %8)
          to label %31 unwind label %61

31:                                               ; preds = %25
  call void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4) %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  %32 = load i32, ptr %4, align 4, !tbaa !11
  %33 = srem i32 %32, 4
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_bitref") align 8 %11, ptr noundef nonnull align 8 dereferenceable(8) %7, i32 noundef 7)
          to label %34 unwind label %65

34:                                               ; preds = %31
  %35 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSEi(ptr noundef nonnull align 8 dereferenceable(12) %11, i32 noundef %33)
          to label %36 unwind label %65

36:                                               ; preds = %34
  call void @llvm.lifetime.start.p0(i64 16, ptr %12) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_bitref") align 8 %12, ptr noundef nonnull align 8 dereferenceable(8) %7, i32 noundef 5)
          to label %37 unwind label %69

37:                                               ; preds = %36
  %38 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12) %12, ptr noundef nonnull align 8 dereferenceable(12) %35)
          to label %39 unwind label %69

39:                                               ; preds = %37
  call void @llvm.lifetime.start.p0(i64 16, ptr %13) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_bitref") align 8 %13, ptr noundef nonnull align 8 dereferenceable(8) %7, i32 noundef 3)
          to label %40 unwind label %73

40:                                               ; preds = %39
  %41 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12) %13, ptr noundef nonnull align 8 dereferenceable(12) %38)
          to label %42 unwind label %73

42:                                               ; preds = %40
  call void @llvm.lifetime.start.p0(i64 16, ptr %14) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_bitref") align 8 %14, ptr noundef nonnull align 8 dereferenceable(8) %7, i32 noundef 1)
          to label %43 unwind label %77

43:                                               ; preds = %42
  %44 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12) %14, ptr noundef nonnull align 8 dereferenceable(12) %41)
          to label %45 unwind label %77

45:                                               ; preds = %43
  call void @llvm.lifetime.end.p0(i64 16, ptr %14) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #5
  %46 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef @.str.3)
          to label %47 unwind label %84

47:                                               ; preds = %45
  %48 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZN5sc_dtlsINS_10sc_lv_baseEEERSoS2_RKNS_8sc_proxyIT_EE(ptr noundef nonnull align 8 dereferenceable(8) %46, ptr noundef nonnull align 8 dereferenceable(8) %7)
          to label %49 unwind label %84

49:                                               ; preds = %47
  %50 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %48, ptr noundef @_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
          to label %51 unwind label %84

51:                                               ; preds = %49
  %52 = getelementptr inbounds %struct.stimgen, ptr %16, i32 0, i32 6
  invoke void @_ZN7sc_core8sc_inoutIN5sc_dt5sc_lvILi8EEEE5writeERKS3_(ptr noundef nonnull align 8 dereferenceable(176) %52, ptr noundef nonnull align 8 dereferenceable(32) %7)
          to label %53 unwind label %84

53:                                               ; preds = %51
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %16)
          to label %54 unwind label %84

54:                                               ; preds = %53
  %55 = getelementptr inbounds %struct.stimgen, ptr %16, i32 0, i32 5
  call void @llvm.lifetime.start.p0(i64 1, ptr %15) #5
  store i8 0, ptr %15, align 1, !tbaa !9
  invoke void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %55, ptr noundef nonnull align 1 dereferenceable(1) %15)
          to label %56 unwind label %88

56:                                               ; preds = %54
  call void @llvm.lifetime.end.p0(i64 1, ptr %15) #5
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %16)
          to label %57 unwind label %84

57:                                               ; preds = %56
  call void @_ZN5sc_dt10sc_lv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %7) #5
  call void @llvm.lifetime.end.p0(i64 32, ptr %7) #5
  br label %58

58:                                               ; preds = %57
  %59 = load i32, ptr %4, align 4, !tbaa !11
  %60 = add nsw i32 %59, 1
  store i32 %60, ptr %4, align 4, !tbaa !11
  br label %22, !llvm.loop !13

61:                                               ; preds = %25
  %62 = landingpad { ptr, i32 }
          cleanup
  %63 = extractvalue { ptr, i32 } %62, 0
  store ptr %63, ptr %9, align 8
  %64 = extractvalue { ptr, i32 } %62, 1
  store i32 %64, ptr %10, align 4
  call void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4) %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  br label %93

65:                                               ; preds = %34, %31
  %66 = landingpad { ptr, i32 }
          cleanup
  %67 = extractvalue { ptr, i32 } %66, 0
  store ptr %67, ptr %9, align 8
  %68 = extractvalue { ptr, i32 } %66, 1
  store i32 %68, ptr %10, align 4
  br label %83

69:                                               ; preds = %37, %36
  %70 = landingpad { ptr, i32 }
          cleanup
  %71 = extractvalue { ptr, i32 } %70, 0
  store ptr %71, ptr %9, align 8
  %72 = extractvalue { ptr, i32 } %70, 1
  store i32 %72, ptr %10, align 4
  br label %82

73:                                               ; preds = %40, %39
  %74 = landingpad { ptr, i32 }
          cleanup
  %75 = extractvalue { ptr, i32 } %74, 0
  store ptr %75, ptr %9, align 8
  %76 = extractvalue { ptr, i32 } %74, 1
  store i32 %76, ptr %10, align 4
  br label %81

77:                                               ; preds = %43, %42
  %78 = landingpad { ptr, i32 }
          cleanup
  %79 = extractvalue { ptr, i32 } %78, 0
  store ptr %79, ptr %9, align 8
  %80 = extractvalue { ptr, i32 } %78, 1
  store i32 %80, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 16, ptr %14) #5
  br label %81

81:                                               ; preds = %77, %73
  call void @llvm.lifetime.end.p0(i64 16, ptr %13) #5
  br label %82

82:                                               ; preds = %81, %69
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #5
  br label %83

83:                                               ; preds = %82, %65
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #5
  br label %92

84:                                               ; preds = %56, %53, %51, %49, %47, %45
  %85 = landingpad { ptr, i32 }
          cleanup
  %86 = extractvalue { ptr, i32 } %85, 0
  store ptr %86, ptr %9, align 8
  %87 = extractvalue { ptr, i32 } %85, 1
  store i32 %87, ptr %10, align 4
  br label %92

88:                                               ; preds = %54
  %89 = landingpad { ptr, i32 }
          cleanup
  %90 = extractvalue { ptr, i32 } %89, 0
  store ptr %90, ptr %9, align 8
  %91 = extractvalue { ptr, i32 } %89, 1
  store i32 %91, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %15) #5
  br label %92

92:                                               ; preds = %88, %84, %83
  call void @_ZN5sc_dt10sc_lv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %7) #5
  br label %93

93:                                               ; preds = %92, %61
  call void @llvm.lifetime.end.p0(i64 32, ptr %7) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  br label %99

94:                                               ; preds = %22
  br label %95

95:                                               ; preds = %94
  %96 = load i32, ptr %3, align 4, !tbaa !11
  %97 = add nsw i32 %96, 1
  store i32 %97, ptr %3, align 4, !tbaa !11
  br label %18, !llvm.loop !15

98:                                               ; preds = %18
  call void @_ZN7sc_core7sc_stopEv()
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  ret void

99:                                               ; preds = %93
  %100 = load ptr, ptr %9, align 8
  %101 = load i32, ptr %10, align 4
  %102 = insertvalue { ptr, i32 } poison, ptr %100, 0
  %103 = insertvalue { ptr, i32 } %102, i32 %101, 1
  resume { ptr, i32 } %103
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt8sc_logicC2Ei(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt5sc_lvILi8EEC2ERKNS_8sc_logicE(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #2

declare void @_ZN7sc_core7sc_stopEv() #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt10sc_lv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.sc_dt::sc_bitref" = type { %"class.sc_dt::sc_bitref_r.base", [4 x i8] }
%"class.sc_dt::sc_bitref_r.base" = type <{ ptr, i32 }>
%"class.sc_dt::sc_lv" = type { %"class.sc_dt::sc_lv_base" }
%"class.sc_dt::sc_lv_base" = type { %"class.sc_dt::sc_proxy", i32, i32, ptr, ptr }
%"class.sc_dt::sc_proxy" = type { ptr }
%"class.sc_dt::sc_logic" = type { i32 }

@_ZSt4cout = external global %"class.std::basic_ostream", align 8
@.str.3 = external hidden unnamed_addr constant [17 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN5sc_dtlsINS_10sc_lv_baseEEERSoS2_RKNS_8sc_proxyIT_EE(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_bitref") align 8, ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) local_unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSEi(ptr noundef nonnull align 8 dereferenceable(12), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt5sc_lvILi8EEEE5writeERKS3_(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7stimgen5entryEv(ptr noundef nonnull align 8 dereferenceable(1304) %0) local_unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca %"class.sc_dt::sc_lv", align 8
  %7 = alloca %"class.sc_dt::sc_logic", align 4
  %8 = alloca %"class.sc_dt::sc_bitref", align 8
  %9 = alloca %"class.sc_dt::sc_bitref", align 8
  %10 = alloca %"class.sc_dt::sc_bitref", align 8
  %11 = alloca %"class.sc_dt::sc_bitref", align 8
  %12 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #5
  %13 = getelementptr inbounds i8, ptr %0, i64 936
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #5
  store i8 0, ptr %4, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %13, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #5
  %14 = getelementptr inbounds i8, ptr %0, i64 584
  %15 = getelementptr inbounds i8, ptr %0, i64 760
  %16 = getelementptr inbounds i8, ptr %0, i64 1128
  store i32 0, ptr %2, align 4, !tbaa !9
  br label %.preheader

.preheader:                                       ; preds = %1, %67
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %17

17:                                               ; preds = %.preheader, %44
  call void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176) %14, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176) %15, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #5
  store i8 1, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %13, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #5
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %6) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #5
  %18 = load i32, ptr %2, align 4, !tbaa !9
  %19 = srem i32 %18, 4
  call void @_ZN5sc_dt8sc_logicC2Ei(ptr noundef nonnull align 4 dereferenceable(4) %7, i32 noundef %19)
  invoke void @_ZN5sc_dt5sc_lvILi8EEC2ERKNS_8sc_logicE(ptr noundef nonnull align 8 dereferenceable(32) %6, ptr noundef nonnull align 4 dereferenceable(4) %7)
          to label %20 unwind label %48

20:                                               ; preds = %17
  call void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4) %7) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #5
  %21 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %8) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_bitref") align 8 %8, ptr noundef nonnull align 8 dereferenceable(8) %6, i32 noundef 7)
          to label %22 unwind label %50

22:                                               ; preds = %20
  %23 = srem i32 %21, 4
  %24 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSEi(ptr noundef nonnull align 8 dereferenceable(12) %8, i32 noundef %23)
          to label %25 unwind label %50

25:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %9) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_bitref") align 8 %9, ptr noundef nonnull align 8 dereferenceable(8) %6, i32 noundef 5)
          to label %26 unwind label %52

26:                                               ; preds = %25
  %27 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12) %9, ptr noundef nonnull align 8 dereferenceable(12) %24)
          to label %28 unwind label %52

28:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %10) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_bitref") align 8 %10, ptr noundef nonnull align 8 dereferenceable(8) %6, i32 noundef 3)
          to label %29 unwind label %54

29:                                               ; preds = %28
  %30 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12) %10, ptr noundef nonnull align 8 dereferenceable(12) %27)
          to label %31 unwind label %54

31:                                               ; preds = %29
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %11) #5
  invoke void @_ZN5sc_dt8sc_proxyINS_10sc_lv_baseEEixEi(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_bitref") align 8 %11, ptr noundef nonnull align 8 dereferenceable(8) %6, i32 noundef 1)
          to label %32 unwind label %56

32:                                               ; preds = %31
  %33 = invoke noundef nonnull align 8 dereferenceable(12) ptr @_ZN5sc_dt9sc_bitrefINS_10sc_lv_baseEEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(12) %11, ptr noundef nonnull align 8 dereferenceable(12) %30)
          to label %34 unwind label %56

34:                                               ; preds = %32
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %11) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %10) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %9) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %8) #5
  %35 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef nonnull @.str.3)
          to label %36 unwind label %61

36:                                               ; preds = %34
  %37 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZN5sc_dtlsINS_10sc_lv_baseEEERSoS2_RKNS_8sc_proxyIT_EE(ptr noundef nonnull align 8 dereferenceable(8) %35, ptr noundef nonnull align 8 dereferenceable(8) %6)
          to label %38 unwind label %61

38:                                               ; preds = %36
  %39 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %37, ptr noundef nonnull @_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
          to label %40 unwind label %61

40:                                               ; preds = %38
  invoke void @_ZN7sc_core8sc_inoutIN5sc_dt5sc_lvILi8EEEE5writeERKS3_(ptr noundef nonnull align 8 dereferenceable(176) %16, ptr noundef nonnull align 8 dereferenceable(32) %6)
          to label %41 unwind label %61

41:                                               ; preds = %40
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %42 unwind label %61

42:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %12) #5
  store i8 0, ptr %12, align 1, !tbaa !5
  invoke void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %13, ptr noundef nonnull align 1 dereferenceable(1) %12)
          to label %43 unwind label %63

43:                                               ; preds = %42
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %12) #5
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %44 unwind label %61

44:                                               ; preds = %43
  call void @_ZN5sc_dt10sc_lv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %6) #5
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %6) #5
  %45 = load i32, ptr %3, align 4, !tbaa !9
  %46 = add nsw i32 %45, 1
  store i32 %46, ptr %3, align 4, !tbaa !9
  %47 = icmp slt i32 %45, 5
  br i1 %47, label %17, label %67, !llvm.loop !11

48:                                               ; preds = %17
  %49 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4) %7) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #5
  br label %66

50:                                               ; preds = %22, %20
  %51 = landingpad { ptr, i32 }
          cleanup
  br label %60

52:                                               ; preds = %26, %25
  %53 = landingpad { ptr, i32 }
          cleanup
  br label %59

54:                                               ; preds = %29, %28
  %55 = landingpad { ptr, i32 }
          cleanup
  br label %58

56:                                               ; preds = %32, %31
  %57 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %11) #5
  br label %58

58:                                               ; preds = %56, %54
  %.pn = phi { ptr, i32 } [ %57, %56 ], [ %55, %54 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %10) #5
  br label %59

59:                                               ; preds = %58, %52
  %.pn.pn = phi { ptr, i32 } [ %.pn, %58 ], [ %53, %52 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %9) #5
  br label %60

60:                                               ; preds = %59, %50
  %.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn, %59 ], [ %51, %50 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %8) #5
  br label %65

61:                                               ; preds = %43, %41, %40, %38, %36, %34
  %62 = landingpad { ptr, i32 }
          cleanup
  br label %65

63:                                               ; preds = %42
  %64 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %12) #5
  br label %65

65:                                               ; preds = %63, %61, %60
  %.pn11 = phi { ptr, i32 } [ %62, %61 ], [ %64, %63 ], [ %.pn.pn.pn, %60 ]
  call void @_ZN5sc_dt10sc_lv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %6) #5
  br label %66

66:                                               ; preds = %65, %48
  %.pn11.pn = phi { ptr, i32 } [ %.pn11, %65 ], [ %49, %48 ]
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %6) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #5
  resume { ptr, i32 } %.pn11.pn

67:                                               ; preds = %44
  %68 = load i32, ptr %2, align 4, !tbaa !9
  %69 = add nsw i32 %68, 1
  store i32 %69, ptr %2, align 4, !tbaa !9
  %70 = icmp slt i32 %68, 5
  br i1 %70, label %.preheader, label %71, !llvm.loop !13

71:                                               ; preds = %67
  call void @_ZN7sc_core7sc_stopEv()
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #5
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt8sc_logicC2Ei(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt5sc_lvILi8EEC2ERKNS_8sc_logicE(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicD2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #2

declare void @_ZN7sc_core7sc_stopEv() local_unnamed_addr #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt10sc_lv_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass