; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/utils/sc_hash.ll (ZN7sc_core18sc_phash_base_iter4stepEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_phash_base_iter" = type <{ ptr, ptr, ptr, ptr, i32, [4 x i8] }>
%"class.sc_core::sc_phash_elem" = type { ptr, ptr, ptr }
%"class.sc_core::sc_phash_base" = type { ptr, i32, i32, i32, i32, double, ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core18sc_phash_base_iter4stepEv(ptr noundef nonnull align 8 dereferenceable(36) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  %6 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  %7 = load ptr, ptr %6, align 8, !tbaa !9
  %8 = icmp ne ptr %7, null
  br i1 %8, label %9, label %14

9:                                                ; preds = %1
  %10 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  %11 = load ptr, ptr %10, align 8, !tbaa !9
  %12 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %11, i32 0, i32 2
  %13 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 3
  store ptr %12, ptr %13, align 8, !tbaa !12
  br label %14

14:                                               ; preds = %9, %1
  %15 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 2
  %16 = load ptr, ptr %15, align 8, !tbaa !13
  %17 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  store ptr %16, ptr %17, align 8, !tbaa !9
  %18 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  %19 = load ptr, ptr %18, align 8, !tbaa !9
  %20 = icmp ne ptr %19, null
  br i1 %20, label %69, label %21

21:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  %22 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 4
  %23 = load i32, ptr %22, align 8, !tbaa !14
  store i32 %23, ptr %3, align 4, !tbaa !15
  br label %24

24:                                               ; preds = %64, %21
  %25 = load i32, ptr %3, align 4, !tbaa !15
  %26 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !16
  %28 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %27, i32 0, i32 1
  %29 = load i32, ptr %28, align 8, !tbaa !17
  %30 = icmp slt i32 %25, %29
  br i1 %30, label %32, label %31

31:                                               ; preds = %24
  store i32 2, ptr %4, align 4
  br label %67

32:                                               ; preds = %24
  %33 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 0
  %34 = load ptr, ptr %33, align 8, !tbaa !16
  %35 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %34, i32 0, i32 6
  %36 = load ptr, ptr %35, align 8, !tbaa !20
  %37 = load i32, ptr %3, align 4, !tbaa !15
  %38 = sext i32 %37 to i64
  %39 = getelementptr inbounds ptr, ptr %36, i64 %38
  %40 = load ptr, ptr %39, align 8, !tbaa !5
  %41 = icmp ne ptr %40, null
  br i1 %41, label %42, label %63

42:                                               ; preds = %32
  %43 = load i32, ptr %3, align 4, !tbaa !15
  %44 = add nsw i32 %43, 1
  %45 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 4
  store i32 %44, ptr %45, align 8, !tbaa !14
  %46 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 0
  %47 = load ptr, ptr %46, align 8, !tbaa !16
  %48 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %47, i32 0, i32 6
  %49 = load ptr, ptr %48, align 8, !tbaa !20
  %50 = load i32, ptr %3, align 4, !tbaa !15
  %51 = sext i32 %50 to i64
  %52 = getelementptr inbounds ptr, ptr %49, i64 %51
  %53 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 3
  store ptr %52, ptr %53, align 8, !tbaa !12
  %54 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 3
  %55 = load ptr, ptr %54, align 8, !tbaa !12
  %56 = load ptr, ptr %55, align 8, !tbaa !5
  %57 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  store ptr %56, ptr %57, align 8, !tbaa !9
  %58 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  %59 = load ptr, ptr %58, align 8, !tbaa !9
  %60 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %59, i32 0, i32 2
  %61 = load ptr, ptr %60, align 8, !tbaa !21
  %62 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 2
  store ptr %61, ptr %62, align 8, !tbaa !13
  store i32 2, ptr %4, align 4
  br label %67

63:                                               ; preds = %32
  br label %64

64:                                               ; preds = %63
  %65 = load i32, ptr %3, align 4, !tbaa !15
  %66 = add nsw i32 %65, 1
  store i32 %66, ptr %3, align 4, !tbaa !15
  br label %24, !llvm.loop !23

67:                                               ; preds = %42, %31
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  br label %68

68:                                               ; preds = %67
  br label %75

69:                                               ; preds = %14
  %70 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 1
  %71 = load ptr, ptr %70, align 8, !tbaa !9
  %72 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %71, i32 0, i32 2
  %73 = load ptr, ptr %72, align 8, !tbaa !21
  %74 = getelementptr inbounds %"class.sc_core::sc_phash_base_iter", ptr %5, i32 0, i32 2
  store ptr %73, ptr %74, align 8, !tbaa !13
  br label %75

75:                                               ; preds = %69, %68
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"_ZTSN7sc_core18sc_phash_base_iterE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !11, i64 32}
!11 = !{!"int", !7, i64 0}
!12 = !{!10, !6, i64 24}
!13 = !{!10, !6, i64 16}
!14 = !{!10, !11, i64 32}
!15 = !{!11, !11, i64 0}
!16 = !{!10, !6, i64 0}
!17 = !{!18, !11, i64 8}
!18 = !{!"_ZTSN7sc_core13sc_phash_baseE", !6, i64 0, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !19, i64 24, !6, i64 32, !6, i64 40, !6, i64 48}
!19 = !{!"double", !7, i64 0}
!20 = !{!18, !6, i64 32}
!21 = !{!22, !6, i64 16}
!22 = !{!"_ZTSN7sc_core13sc_phash_elemE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable
define dso_local void @_ZN7sc_core18sc_phash_base_iter4stepEv(ptr nocapture noundef nonnull align 8 dereferenceable(36) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 8
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %7, label %4

4:                                                ; preds = %1
  %5 = getelementptr inbounds i8, ptr %3, i64 16
  %6 = getelementptr inbounds i8, ptr %0, i64 24
  store ptr %5, ptr %6, align 8, !tbaa !11
  br label %7

7:                                                ; preds = %4, %1
  %8 = getelementptr inbounds i8, ptr %0, i64 16
  %9 = load ptr, ptr %8, align 8, !tbaa !12
  store ptr %9, ptr %2, align 8, !tbaa !5
  %.not7 = icmp eq ptr %9, null
  br i1 %.not7, label %10, label %.loopexit.sink.split

10:                                               ; preds = %7
  %11 = getelementptr inbounds i8, ptr %0, i64 32
  %12 = load i32, ptr %11, align 8, !tbaa !13
  %13 = load ptr, ptr %0, align 8, !tbaa !14
  %14 = getelementptr inbounds i8, ptr %13, i64 8
  %15 = load i32, ptr %14, align 8, !tbaa !15
  %16 = icmp slt i32 %12, %15
  br i1 %16, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %10
  %17 = getelementptr inbounds i8, ptr %13, i64 32
  %18 = load ptr, ptr %17, align 8, !tbaa !18
  %19 = sext i32 %12 to i64
  %wide.trip.count = sext i32 %15 to i64
  br label %20

20:                                               ; preds = %.lr.ph, %29
  %indvars.iv = phi i64 [ %19, %.lr.ph ], [ %indvars.iv.next, %29 ]
  %21 = getelementptr inbounds ptr, ptr %18, i64 %indvars.iv
  %22 = load ptr, ptr %21, align 8, !tbaa !19
  %.not8 = icmp eq ptr %22, null
  br i1 %.not8, label %29, label %23

23:                                               ; preds = %20
  %24 = getelementptr inbounds ptr, ptr %18, i64 %indvars.iv
  %25 = trunc nsw i64 %indvars.iv to i32
  %26 = add nsw i32 %25, 1
  store i32 %26, ptr %11, align 8, !tbaa !13
  %27 = getelementptr inbounds i8, ptr %0, i64 24
  store ptr %24, ptr %27, align 8, !tbaa !11
  %28 = load ptr, ptr %24, align 8, !tbaa !19
  store ptr %28, ptr %2, align 8, !tbaa !5
  br label %.loopexit.sink.split

29:                                               ; preds = %20
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.loopexit, label %20, !llvm.loop !20

.loopexit.sink.split:                             ; preds = %7, %23
  %.sink = phi ptr [ %28, %23 ], [ %9, %7 ]
  %30 = getelementptr inbounds i8, ptr %.sink, i64 16
  %31 = load ptr, ptr %30, align 8, !tbaa !22
  store ptr %31, ptr %8, align 8, !tbaa !12
  br label %.loopexit

.loopexit:                                        ; preds = %29, %.loopexit.sink.split, %10
  ret void
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"_ZTSN7sc_core18sc_phash_base_iterE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !10, i64 32}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!6, !7, i64 24}
!12 = !{!6, !7, i64 16}
!13 = !{!6, !10, i64 32}
!14 = !{!6, !7, i64 0}
!15 = !{!16, !10, i64 8}
!16 = !{!"_ZTSN7sc_core13sc_phash_baseE", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !17, i64 24, !7, i64 32, !7, i64 40, !7, i64 48}
!17 = !{!"double", !8, i64 0}
!18 = !{!16, !7, i64 32}
!19 = !{!7, !7, i64 0}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}
!22 = !{!23, !7, i64 16}
!23 = !{!"_ZTSN7sc_core13sc_phash_elemE", !7, i64 0, !7, i64 8, !7, i64 16}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass