; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_module.ll (ZN7sc_core9sc_moduleD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }

@_ZTVN7sc_core9sc_moduleE = external dso_local unnamed_addr constant { [21 x ptr], [4 x ptr] }, align 8

declare i32 @__gxx_personality_v0(...)

; Function Attrs: noinline noreturn nounwind uwtable
declare hidden void @__clang_call_terminate(ptr noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344)) #2 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #3

; Function Attrs: nounwind
declare void @_ZN7sc_core16sc_sensitive_negD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4

; Function Attrs: nounwind
declare void @_ZN7sc_core16sc_sensitive_posD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4

; Function Attrs: nounwind
declare void @_ZN7sc_core12sc_sensitiveD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112)) unnamed_addr #4

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core9sc_moduleD2Ev(ptr noundef nonnull align 8 dereferenceable(232) %0) unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 152) ({ [21 x ptr], [4 x ptr] }, ptr @_ZTVN7sc_core9sc_moduleE, i32 0, i32 0, i32 2), ptr %3, align 8, !tbaa !9
  %4 = getelementptr inbounds i8, ptr %3, i64 112
  store ptr getelementptr inbounds inrange(-16, 16) ({ [21 x ptr], [4 x ptr] }, ptr @_ZTVN7sc_core9sc_moduleE, i32 0, i32 1, i32 2), ptr %4, align 8, !tbaa !9
  %5 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 6
  %6 = load ptr, ptr %5, align 8, !tbaa !11
  %7 = icmp eq ptr %6, null
  br i1 %7, label %9, label %8

8:                                                ; preds = %1
  call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #7
  call void @_ZdlPvm(ptr noundef %6, i64 noundef 24) #8
  br label %9

9:                                                ; preds = %8, %1
  %10 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 8
  %11 = load ptr, ptr %10, align 8, !tbaa !34
  %12 = icmp eq ptr %11, null
  br i1 %12, label %14, label %13

13:                                               ; preds = %9
  call void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %11) #7
  call void @_ZdlPvm(ptr noundef %11, i64 noundef 8248) #8
  br label %14

14:                                               ; preds = %13, %9
  %15 = load ptr, ptr %3, align 8, !tbaa !9
  %16 = getelementptr inbounds ptr, ptr %15, i64 14
  %17 = load ptr, ptr %16, align 8
  invoke void %17(ptr noundef nonnull align 8 dereferenceable(112) %3)
          to label %18 unwind label %37

18:                                               ; preds = %14
  %19 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 9
  %20 = load ptr, ptr %19, align 8, !tbaa !35
  %21 = icmp ne ptr %20, null
  br i1 %21, label %22, label %27

22:                                               ; preds = %18
  %23 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 9
  %24 = load ptr, ptr %23, align 8, !tbaa !35
  invoke void @_ZN7sc_core14sc_module_name12clear_moduleEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(33) %24, ptr noundef %3)
          to label %25 unwind label %37

25:                                               ; preds = %22
  invoke void @_ZN7sc_core9sc_module10end_moduleEv(ptr noundef nonnull align 8 dereferenceable(232) %3)
          to label %26 unwind label %37

26:                                               ; preds = %25
  br label %27

27:                                               ; preds = %26, %18
  %28 = invoke noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %3)
          to label %29 unwind label %37

29:                                               ; preds = %27
  %30 = invoke noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344) %28)
          to label %31 unwind label %37

31:                                               ; preds = %29
  invoke void @_ZN7sc_core18sc_module_registry6removeERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40) %30, ptr noundef nonnull align 8 dereferenceable(232) %3)
          to label %32 unwind label %37

32:                                               ; preds = %31
  %33 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 4
  call void @_ZN7sc_core16sc_sensitive_negD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %33) #7
  %34 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 3
  call void @_ZN7sc_core16sc_sensitive_posD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %34) #7
  %35 = getelementptr inbounds %"class.sc_core::sc_module", ptr %3, i32 0, i32 2
  call void @_ZN7sc_core12sc_sensitiveD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %35) #7
  %36 = getelementptr inbounds i8, ptr %3, i64 112
  call void @_ZN7sc_core15sc_process_hostD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %36) #7
  call void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112) %3) #7
  ret void

37:                                               ; preds = %31, %29, %27, %25, %22, %14
  %38 = landingpad { ptr, i32 }
          catch ptr null
  %39 = extractvalue { ptr, i32 } %38, 0
  call void @__clang_call_terminate(ptr %39) #9
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core14sc_module_name12clear_moduleEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module10end_moduleEv(ptr noundef nonnull align 8 dereferenceable(232)) #5 align 2

declare void @_ZN7sc_core18sc_module_registry6removeERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef nonnull align 8 dereferenceable(232)) #6

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core15sc_process_hostD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #1 align 2

attributes #0 = { noinline noreturn nounwind uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 200}
!12 = !{!"_ZTSN7sc_core9sc_moduleE", !13, i64 0, !25, i64 112, !26, i64 120, !28, i64 144, !30, i64 168, !32, i64 192, !6, i64 200, !33, i64 208, !6, i64 216, !6, i64 224}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !6, i64 96, !6, i64 104}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !27, i64 8, !6, i64 16}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !29, i64 8, !6, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !31, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!32 = !{!"bool", !7, i64 0}
!33 = !{!"int", !7, i64 0}
!34 = !{!12, !6, i64 216}
!35 = !{!12, !6, i64 224}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN7sc_core9sc_moduleE = external dso_local unnamed_addr constant { [21 x ptr], [4 x ptr] }, align 8

declare i32 @__gxx_personality_v0(...)

; Function Attrs: noinline noreturn nounwind uwtable
declare hidden void @__clang_call_terminate(ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #2 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #3

; Function Attrs: nounwind
declare void @_ZN7sc_core16sc_sensitive_negD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4

; Function Attrs: nounwind
declare void @_ZN7sc_core16sc_sensitive_posD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4

; Function Attrs: nounwind
declare void @_ZN7sc_core12sc_sensitiveD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4

; Function Attrs: nounwind
declare void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112)) unnamed_addr #4

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7sc_core9sc_moduleD2Ev(ptr noundef nonnull align 8 dereferenceable(232) %0) unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  store ptr getelementptr inbounds inrange(-16, 152) (i8, ptr @_ZTVN7sc_core9sc_moduleE, i64 16), ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr getelementptr inbounds inrange(-16, 16) (i8, ptr @_ZTVN7sc_core9sc_moduleE, i64 184), ptr %2, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 200
  %4 = load ptr, ptr %3, align 8, !tbaa !8
  %5 = icmp eq ptr %4, null
  br i1 %5, label %7, label %6

6:                                                ; preds = %1
  tail call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #7
  tail call void @_ZdlPvm(ptr noundef nonnull %4, i64 noundef 24) #8
  br label %7

7:                                                ; preds = %6, %1
  %8 = getelementptr inbounds i8, ptr %0, i64 216
  %9 = load ptr, ptr %8, align 8, !tbaa !33
  %10 = icmp eq ptr %9, null
  br i1 %10, label %12, label %11

11:                                               ; preds = %7
  tail call void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248) %9) #7
  tail call void @_ZdlPvm(ptr noundef nonnull %9, i64 noundef 8248) #8
  br label %12

12:                                               ; preds = %11, %7
  %13 = load ptr, ptr %0, align 8, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %13, i64 112
  %15 = load ptr, ptr %14, align 8
  invoke void %15(ptr noundef nonnull align 8 dereferenceable(112) %0)
          to label %16 unwind label %27

16:                                               ; preds = %12
  %17 = getelementptr inbounds i8, ptr %0, i64 224
  %18 = load ptr, ptr %17, align 8, !tbaa !34
  %.not = icmp eq ptr %18, null
  br i1 %.not, label %20, label %19

19:                                               ; preds = %16
  tail call void @_ZN7sc_core14sc_module_name12clear_moduleEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(33) %18, ptr noundef nonnull %0)
  invoke void @_ZN7sc_core9sc_module10end_moduleEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %20 unwind label %27

20:                                               ; preds = %19, %16
  %21 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  %22 = tail call noundef ptr @_ZN7sc_core13sc_simcontext19get_module_registryEv(ptr noundef nonnull align 8 dereferenceable(344) %21)
  invoke void @_ZN7sc_core18sc_module_registry6removeERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40) %22, ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %23 unwind label %27

23:                                               ; preds = %20
  %24 = getelementptr inbounds i8, ptr %0, i64 168
  tail call void @_ZN7sc_core16sc_sensitive_negD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %24) #7
  %25 = getelementptr inbounds i8, ptr %0, i64 144
  tail call void @_ZN7sc_core16sc_sensitive_posD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %25) #7
  %26 = getelementptr inbounds i8, ptr %0, i64 120
  tail call void @_ZN7sc_core12sc_sensitiveD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %26) #7
  tail call void @_ZN7sc_core15sc_process_hostD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %2) #7
  tail call void @_ZN7sc_core9sc_objectD2Ev(ptr noundef nonnull align 8 dereferenceable(112) %0) #7
  ret void

27:                                               ; preds = %20, %19, %12
  %28 = landingpad { ptr, i32 }
          catch ptr null
  %29 = extractvalue { ptr, i32 } %28, 0
  tail call void @__clang_call_terminate(ptr %29) #9
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core11sc_name_genD1Ev(ptr noundef nonnull align 8 dereferenceable(8248)) unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core14sc_module_name12clear_moduleEPNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module10end_moduleEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #5 align 2

declare void @_ZN7sc_core18sc_module_registry6removeERNS_9sc_moduleE(ptr noundef nonnull align 8 dereferenceable(40), ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #6

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core15sc_process_hostD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #1 align 2

attributes #0 = { noinline noreturn nounwind uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !11, i64 200}
!9 = !{!"_ZTSN7sc_core9sc_moduleE", !10, i64 0, !24, i64 112, !25, i64 120, !27, i64 144, !29, i64 168, !31, i64 192, !11, i64 200, !32, i64 208, !11, i64 216, !11, i64 224}
!10 = !{!"_ZTSN7sc_core9sc_objectE", !11, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !11, i64 96, !11, i64 104}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !12, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !11, i64 0}
!23 = !{!"long", !12, i64 0}
!24 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveE", !11, i64 0, !26, i64 8, !11, i64 16}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !12, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !11, i64 0, !28, i64 8, !11, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !12, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !11, i64 0, !30, i64 8, !11, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !12, i64 0}
!31 = !{!"bool", !12, i64 0}
!32 = !{!"int", !12, i64 0}
!33 = !{!9, !11, i64 216}
!34 = !{!9, !11, i64 224}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass