; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library (SerialPortWrite)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@gUartBase = external dso_local global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare zeroext i8 @IoWrite8(i64 noundef, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i64 @SerialPortWrite(ptr noundef %0, i64 noundef %1) #2 {
  %3 = alloca i64, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = icmp eq ptr %9, null
  br i1 %10, label %11, label %12

11:                                               ; preds = %2
  store i64 0, ptr %3, align 8
  store i32 1, ptr %8, align 4
  br label %39

12:                                               ; preds = %2
  %13 = load i64, ptr %5, align 8, !tbaa !9
  store i64 %13, ptr %6, align 8, !tbaa !9
  br label %14

14:                                               ; preds = %30, %12
  %15 = load i64, ptr %5, align 8, !tbaa !9
  %16 = add i64 %15, -1
  store i64 %16, ptr %5, align 8, !tbaa !9
  %17 = icmp ne i64 %15, 0
  br i1 %17, label %18, label %37

18:                                               ; preds = %14
  br label %19

19:                                               ; preds = %25, %18
  %20 = load i16, ptr @gUartBase, align 2, !tbaa !11
  %21 = zext i16 %20 to i32
  %22 = add nsw i32 %21, 5
  %23 = sext i32 %22 to i64
  %24 = call zeroext i8 @IoRead8(i64 noundef %23)
  store i8 %24, ptr %7, align 1, !tbaa !13
  br label %25

25:                                               ; preds = %19
  %26 = load i8, ptr %7, align 1, !tbaa !13
  %27 = zext i8 %26 to i32
  %28 = and i32 %27, 32
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %19, label %30, !llvm.loop !14

30:                                               ; preds = %25
  %31 = load i16, ptr @gUartBase, align 2, !tbaa !11
  %32 = zext i16 %31 to i64
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  %34 = getelementptr inbounds i8, ptr %33, i32 1
  store ptr %34, ptr %4, align 8, !tbaa !5
  %35 = load i8, ptr %33, align 1, !tbaa !13
  %36 = call zeroext i8 @IoWrite8(i64 noundef %32, i8 noundef zeroext %35)
  br label %14, !llvm.loop !16

37:                                               ; preds = %14
  %38 = load i64, ptr %6, align 8, !tbaa !9
  store i64 %38, ptr %3, align 8
  store i32 1, ptr %8, align 4
  br label %39

39:                                               ; preds = %37, %11
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  %40 = load i64, ptr %3, align 8
  ret i64 %40
}

declare zeroext i8 @IoRead8(i64 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@gUartBase = external dso_local local_unnamed_addr global i16, align 2

declare zeroext i8 @IoWrite8(i64 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local noundef i64 @SerialPortWrite(ptr noundef readonly %0, i64 noundef %1) local_unnamed_addr #1 {
  %3 = icmp eq ptr %0, null
  %.not10 = icmp eq i64 %1, 0
  %or.cond = or i1 %3, %.not10
  br i1 %or.cond, label %.loopexit, label %.preheader

.preheader:                                       ; preds = %2, %11
  %.in = phi i64 [ %12, %11 ], [ %1, %2 ]
  %.0611 = phi ptr [ %15, %11 ], [ %0, %2 ]
  br label %4

4:                                                ; preds = %.preheader, %4
  %5 = load i16, ptr @gUartBase, align 2, !tbaa !5
  %6 = zext i16 %5 to i64
  %7 = add nuw nsw i64 %6, 5
  %8 = tail call zeroext i8 @IoRead8(i64 noundef %7) #2
  %9 = and i8 %8, 32
  %10 = icmp eq i8 %9, 0
  br i1 %10, label %4, label %11, !llvm.loop !9

11:                                               ; preds = %4
  %12 = add i64 %.in, -1
  %13 = load i16, ptr @gUartBase, align 2, !tbaa !5
  %14 = zext i16 %13 to i64
  %15 = getelementptr inbounds i8, ptr %.0611, i64 1
  %16 = load i8, ptr %.0611, align 1, !tbaa !11
  %17 = tail call zeroext i8 @IoWrite8(i64 noundef %14, i8 noundef zeroext %16) #2
  %.not = icmp eq i64 %12, 0
  br i1 %.not, label %.loopexit, label %.preheader, !llvm.loop !12

.loopexit:                                        ; preds = %11, %2
  %.0 = phi i64 [ 0, %2 ], [ %1, %11 ]
  ret i64 %.0
}

declare zeroext i8 @IoRead8(i64 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !10}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass