; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library (PciCf8BitFieldWrite32)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @SaveAndDisableInterrupts() #0

declare i32 @IoRead32(i64 noundef) #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @PciCf8BitFieldWrite32(i64 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3) #2 {
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store i64 %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !5
  store i64 %2, ptr %7, align 8, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  br label %12

12:                                               ; preds = %4
  %13 = call zeroext i8 @DebugAssertEnabled()
  %14 = icmp ne i8 %13, 0
  br i1 %14, label %15, label %21

15:                                               ; preds = %12
  %16 = load i64, ptr %5, align 8, !tbaa !5
  %17 = and i64 %16, -268431613
  %18 = icmp eq i64 %17, 0
  br i1 %18, label %20, label %19

19:                                               ; preds = %15
  call void @DebugAssert(ptr noundef @.str, i64 noundef 1396, ptr noundef @.str.3)
  br label %20

20:                                               ; preds = %19, %15
  br label %21

21:                                               ; preds = %20, %12
  br label %22

22:                                               ; preds = %21
  br label %23

23:                                               ; preds = %22
  %24 = call zeroext i8 @SaveAndDisableInterrupts()
  store i8 %24, ptr %9, align 1, !tbaa !11
  %25 = call i32 @IoRead32(i64 noundef 3320)
  store i32 %25, ptr %10, align 4, !tbaa !9
  %26 = load i64, ptr %5, align 8, !tbaa !5
  %27 = lshr i64 %26, 4
  %28 = and i64 %27, 16776960
  %29 = load i64, ptr %5, align 8, !tbaa !5
  %30 = and i64 %29, 252
  %31 = or i64 %28, %30
  %32 = or i64 %31, 2147483648
  %33 = trunc i64 %32 to i32
  %34 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %33)
  %35 = load i64, ptr %6, align 8, !tbaa !5
  %36 = load i64, ptr %7, align 8, !tbaa !5
  %37 = load i32, ptr %8, align 4, !tbaa !9
  %38 = call i32 @IoBitFieldWrite32(i64 noundef 3324, i64 noundef %35, i64 noundef %36, i32 noundef %37)
  store i32 %38, ptr %11, align 4, !tbaa !9
  %39 = load i32, ptr %10, align 4, !tbaa !9
  %40 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %39)
  %41 = load i8, ptr %9, align 1, !tbaa !11
  %42 = call zeroext i8 @SetInterruptState(i8 noundef zeroext %41)
  %43 = load i32, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  ret i32 %43
}

declare i32 @IoBitFieldWrite32(i64 noundef, i64 noundef, i64 noundef, i32 noundef) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

declare zeroext i8 @SaveAndDisableInterrupts() local_unnamed_addr #0

declare i32 @IoRead32(i64 noundef) local_unnamed_addr #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @PciCf8BitFieldWrite32(i64 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not = icmp eq i8 %5, 0
  %6 = and i64 %0, -268431613
  %7 = icmp eq i64 %6, 0
  %or.cond = or i1 %7, %.not
  br i1 %or.cond, label %9, label %8

8:                                                ; preds = %4
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 1396, ptr noundef nonnull @.str.3) #2
  br label %9

9:                                                ; preds = %8, %4
  %10 = tail call zeroext i8 @SaveAndDisableInterrupts() #2
  %11 = tail call i32 @IoRead32(i64 noundef 3320) #2
  %12 = lshr i64 %0, 4
  %13 = and i64 %12, 16776960
  %14 = and i64 %0, 252
  %15 = or disjoint i64 %13, %14
  %16 = trunc nuw nsw i64 %15 to i32
  %17 = or disjoint i32 %16, -2147483648
  %18 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %17) #2
  %19 = tail call i32 @IoBitFieldWrite32(i64 noundef 3324, i64 noundef %1, i64 noundef %2, i32 noundef %3) #2
  %20 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %11) #2
  %21 = tail call zeroext i8 @SetInterruptState(i8 noundef zeroext %10) #2
  ret i32 %19
}

declare i32 @IoBitFieldWrite32(i64 noundef, i64 noundef, i64 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass