; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/utils (sc_hash)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_phash_base" = type { ptr, i32, i32, i32, i32, double, ptr, ptr, ptr }
%"class.sc_core::sc_phash_elem" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef, i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN7sc_core13sc_phash_base18remove_by_contentsEPFbPKvPvES3_(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef %1, ptr noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %11 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %12

12:                                               ; preds = %59, %3
  %13 = load i32, ptr %10, align 4, !tbaa !9
  %14 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %11, i32 0, i32 1
  %15 = load i32, ptr %14, align 8, !tbaa !11
  %16 = icmp slt i32 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %62

18:                                               ; preds = %12
  %19 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %11, i32 0, i32 6
  %20 = load ptr, ptr %19, align 8, !tbaa !14
  %21 = load i32, ptr %10, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds ptr, ptr %20, i64 %22
  store ptr %23, ptr %7, align 8, !tbaa !5
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  %25 = load ptr, ptr %24, align 8, !tbaa !5
  store ptr %25, ptr %8, align 8, !tbaa !5
  br label %26

26:                                               ; preds = %57, %18
  %27 = load ptr, ptr %8, align 8, !tbaa !5
  %28 = icmp ne ptr %27, null
  br i1 %28, label %29, label %58

29:                                               ; preds = %26
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = load ptr, ptr %8, align 8, !tbaa !5
  %32 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %31, i32 0, i32 1
  %33 = load ptr, ptr %32, align 8, !tbaa !15
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = call noundef zeroext i1 %30(ptr noundef %33, ptr noundef %34)
  br i1 %35, label %41, label %36

36:                                               ; preds = %29
  %37 = load ptr, ptr %8, align 8, !tbaa !5
  %38 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %37, i32 0, i32 2
  store ptr %38, ptr %7, align 8, !tbaa !5
  %39 = load ptr, ptr %7, align 8, !tbaa !5
  %40 = load ptr, ptr %39, align 8, !tbaa !5
  store ptr %40, ptr %8, align 8, !tbaa !5
  br label %57

41:                                               ; preds = %29
  %42 = load ptr, ptr %8, align 8, !tbaa !5
  %43 = getelementptr inbounds %"class.sc_core::sc_phash_elem", ptr %42, i32 0, i32 2
  %44 = load ptr, ptr %43, align 8, !tbaa !17
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  store ptr %44, ptr %45, align 8, !tbaa !5
  %46 = load ptr, ptr %8, align 8, !tbaa !5
  %47 = icmp eq ptr %46, null
  br i1 %47, label %49, label %48

48:                                               ; preds = %41
  call void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %46) #3
  call void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef %46, i64 noundef 24) #3
  br label %49

49:                                               ; preds = %48, %41
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = load ptr, ptr %50, align 8, !tbaa !5
  store ptr %51, ptr %8, align 8, !tbaa !5
  %52 = getelementptr inbounds %"class.sc_core::sc_phash_base", ptr %11, i32 0, i32 2
  %53 = load i32, ptr %52, align 4, !tbaa !18
  %54 = add nsw i32 %53, -1
  store i32 %54, ptr %52, align 4, !tbaa !18
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = add nsw i32 %55, 1
  store i32 %56, ptr %9, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %49, %36
  br label %26, !llvm.loop !19

58:                                               ; preds = %26
  br label %59

59:                                               ; preds = %58
  %60 = load i32, ptr %10, align 4, !tbaa !9
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %10, align 4, !tbaa !9
  br label %12, !llvm.loop !21

62:                                               ; preds = %17
  %63 = load i32, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  ret i32 %63
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"_ZTSN7sc_core13sc_phash_baseE", !6, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !13, i64 24, !6, i64 32, !6, i64 40, !6, i64 48}
!13 = !{!"double", !7, i64 0}
!14 = !{!12, !6, i64 32}
!15 = !{!16, !6, i64 8}
!16 = !{!"_ZTSN7sc_core13sc_phash_elemE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!16, !6, i64 16}
!18 = !{!12, !10, i64 12}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = distinct !{!21, !20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef, i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN7sc_core13sc_phash_base18remove_by_contentsEPFbPKvPvES3_(ptr nocapture noundef nonnull align 8 dereferenceable(56) %0, ptr nocapture noundef readonly %1, ptr noundef %2) local_unnamed_addr #1 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp sgt i32 %5, 0
  br i1 %6, label %.lr.ph28, label %._crit_edge29

.lr.ph28:                                         ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 32
  %8 = getelementptr inbounds i8, ptr %0, i64 12
  br label %9

._crit_edge29:                                    ; preds = %._crit_edge, %3
  %.016.lcssa = phi i32 [ 0, %3 ], [ %.1.lcssa, %._crit_edge ]
  ret i32 %.016.lcssa

9:                                                ; preds = %.lr.ph28, %._crit_edge
  %10 = phi i32 [ %5, %.lr.ph28 ], [ %25, %._crit_edge ]
  %indvars.iv = phi i64 [ 0, %.lr.ph28 ], [ %indvars.iv.next, %._crit_edge ]
  %.01625 = phi i32 [ 0, %.lr.ph28 ], [ %.1.lcssa, %._crit_edge ]
  %11 = load ptr, ptr %7, align 8, !tbaa !12
  %12 = getelementptr inbounds ptr, ptr %11, i64 %indvars.iv
  %13 = load ptr, ptr %12, align 8, !tbaa !13
  %.not21 = icmp eq ptr %13, null
  br i1 %.not21, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %9, %24
  %.124 = phi i32 [ %.2, %24 ], [ %.01625, %9 ]
  %.01723 = phi ptr [ %.118, %24 ], [ %13, %9 ]
  %.01922 = phi ptr [ %.120, %24 ], [ %12, %9 ]
  %14 = getelementptr inbounds i8, ptr %.01723, i64 8
  %15 = load ptr, ptr %14, align 8, !tbaa !14
  %16 = tail call noundef zeroext i1 %1(ptr noundef %15, ptr noundef %2)
  %17 = getelementptr inbounds i8, ptr %.01723, i64 16
  %18 = load ptr, ptr %17, align 8, !tbaa !13
  br i1 %16, label %19, label %24

19:                                               ; preds = %.lr.ph
  store ptr %18, ptr %.01922, align 8, !tbaa !13
  tail call void @_ZN7sc_core13sc_phash_elemD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %.01723) #2
  tail call void @_ZN7sc_core13sc_phash_elemdlEPvm(ptr noundef nonnull %.01723, i64 noundef 24) #2
  %20 = load ptr, ptr %.01922, align 8, !tbaa !13
  %21 = load i32, ptr %8, align 4, !tbaa !16
  %22 = add nsw i32 %21, -1
  store i32 %22, ptr %8, align 4, !tbaa !16
  %23 = add nsw i32 %.124, 1
  br label %24

24:                                               ; preds = %.lr.ph, %19
  %.120 = phi ptr [ %.01922, %19 ], [ %17, %.lr.ph ]
  %.118 = phi ptr [ %20, %19 ], [ %18, %.lr.ph ]
  %.2 = phi i32 [ %23, %19 ], [ %.124, %.lr.ph ]
  %.not = icmp eq ptr %.118, null
  br i1 %.not, label %._crit_edge.loopexit, label %.lr.ph, !llvm.loop !17

._crit_edge.loopexit:                             ; preds = %24
  %.pre = load i32, ptr %4, align 8, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %9
  %25 = phi i32 [ %10, %9 ], [ %.pre, %._crit_edge.loopexit ]
  %.1.lcssa = phi i32 [ %.01625, %9 ], [ %.2, %._crit_edge.loopexit ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %26 = sext i32 %25 to i64
  %27 = icmp slt i64 %indvars.iv.next, %26
  br i1 %27, label %9, label %._crit_edge29, !llvm.loop !19
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"_ZTSN7sc_core13sc_phash_baseE", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !11, i64 24, !7, i64 32, !7, i64 40, !7, i64 48}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"double", !8, i64 0}
!12 = !{!6, !7, i64 32}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !7, i64 8}
!15 = !{!"_ZTSN7sc_core13sc_phash_elemE", !7, i64 0, !7, i64 8, !7, i64 16}
!16 = !{!6, !10, i64 12}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass