; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/gcd.ll (ZN6gcd_cc11gcd_computeEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.gcd_cc = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.13", %"class.sc_core::sc_out", %"class.sc_core::sc_out.28" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.28" = type { %"class.sc_core::sc_inout.29" }
%"class.sc_core::sc_inout.29" = type { %"class.sc_core::sc_port.30", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.30" = type { %"class.sc_core::sc_port_b.31" }
%"class.sc_core::sc_port_b.31" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.32" }
%"class.std::vector.32" = type { %"struct.std::_Vector_base.33" }
%"struct.std::_Vector_base.33" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6gcd_cc11gcd_computeEv(ptr noundef nonnull align 8 dereferenceable(1304) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %8 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  store i32 0, ptr %3, align 4, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  br label %9

9:                                                ; preds = %39, %1
  br label %10

10:                                               ; preds = %9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  %11 = getelementptr inbounds %struct.gcd_cc, ptr %8, i32 0, i32 5
  %12 = call noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIjEaSERKj(ptr noundef nonnull align 8 dereferenceable(176) %11, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  store i8 1, ptr %5, align 1, !tbaa !11
  %13 = getelementptr inbounds %struct.gcd_cc, ptr %8, i32 0, i32 6
  %14 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %13, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  %15 = getelementptr inbounds %struct.gcd_cc, ptr %8, i32 0, i32 3
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %15)
  %17 = load i32, ptr %16, align 4, !tbaa !9
  store i32 %17, ptr %3, align 4, !tbaa !9
  %18 = getelementptr inbounds %struct.gcd_cc, ptr %8, i32 0, i32 4
  %19 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %18)
  %20 = load i32, ptr %19, align 4, !tbaa !9
  store i32 %20, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  store i8 0, ptr %6, align 1, !tbaa !11
  %21 = getelementptr inbounds %struct.gcd_cc, ptr %8, i32 0, i32 6
  %22 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %21, ptr noundef nonnull align 1 dereferenceable(1) %6)
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  br label %23

23:                                               ; preds = %37, %10
  %24 = load i32, ptr %4, align 4, !tbaa !9
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %39

26:                                               ; preds = %23
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %27 = load i32, ptr %3, align 4, !tbaa !9
  store i32 %27, ptr %7, align 4, !tbaa !9
  %28 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %28, ptr %3, align 4, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  br label %29

29:                                               ; preds = %33, %26
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = load i32, ptr %4, align 4, !tbaa !9
  %32 = icmp uge i32 %30, %31
  br i1 %32, label %33, label %37

33:                                               ; preds = %29
  %34 = load i32, ptr %7, align 4, !tbaa !9
  %35 = load i32, ptr %4, align 4, !tbaa !9
  %36 = sub i32 %34, %35
  store i32 %36, ptr %7, align 4, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  br label %29, !llvm.loop !13

37:                                               ; preds = %29
  %38 = load i32, ptr %7, align 4, !tbaa !9
  store i32 %38, ptr %4, align 4, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %8)
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  br label %23, !llvm.loop !15

39:                                               ; preds = %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  br label %9, !llvm.loop !16
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIjEaSERKj(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN6gcd_cc11gcd_computeEv(ptr noundef nonnull align 8 dereferenceable(1304) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca i32, align 4
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #3
  store i32 0, ptr %2, align 4, !tbaa !5
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %5 = getelementptr inbounds i8, ptr %0, i64 936
  %6 = getelementptr inbounds i8, ptr %0, i64 1112
  %7 = getelementptr inbounds i8, ptr %0, i64 600
  %8 = getelementptr inbounds i8, ptr %0, i64 768
  br label %9

.loopexit:                                        ; preds = %._crit_edge, %9
  br label %9, !llvm.loop !9

9:                                                ; preds = %.loopexit, %1
  %10 = call noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIjEaSERKj(ptr noundef nonnull align 8 dereferenceable(176) %5, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  store i8 1, ptr %3, align 1, !tbaa !11
  %11 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %12 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %7)
  %13 = load i32, ptr %12, align 4, !tbaa !5
  store i32 %13, ptr %2, align 4, !tbaa !5
  %14 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %8)
  %15 = load i32, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  store i8 0, ptr %4, align 1, !tbaa !11
  %16 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %.not11 = icmp eq i32 %15, 0
  br i1 %.not11, label %.loopexit, label %.lr.ph14

.lr.ph14:                                         ; preds = %9, %._crit_edge
  %.0712 = phi i32 [ %.0.lcssa, %._crit_edge ], [ %15, %9 ]
  %17 = load i32, ptr %2, align 4, !tbaa !5
  store i32 %.0712, ptr %2, align 4, !tbaa !5
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %.not89 = icmp ult i32 %17, %.0712
  br i1 %.not89, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph14, %.lr.ph
  %.010 = phi i32 [ %18, %.lr.ph ], [ %17, %.lr.ph14 ]
  %18 = sub i32 %.010, %.0712
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %.not8 = icmp ult i32 %18, %.0712
  br i1 %.not8, label %._crit_edge, label %.lr.ph, !llvm.loop !13

._crit_edge:                                      ; preds = %.lr.ph, %.lr.ph14
  %.0.lcssa = phi i32 [ %17, %.lr.ph14 ], [ %18, %.lr.ph ]
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %.not = icmp eq i32 %.0.lcssa, 0
  br i1 %.not, label %.loopexit, label %.lr.ph14, !llvm.loop !14
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIjEaSERKj(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass