; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/datatypes/misc/concat/test05 (test05)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_signed_sigref" = type { %"class.sc_dt::sc_signed_subref_r.base", ptr }
%"class.sc_dt::sc_signed_subref_r.base" = type <{ %"class.sc_dt::sc_value_base", i32, [4 x i8], ptr, i32 }>
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_dt::sc_signed_subref_r" = type <{ %"class.sc_dt::sc_value_base", i32, [4 x i8], ptr, i32, [4 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core16sc_signed_sigref10concat_setExi(ptr noundef nonnull align 8 dereferenceable(40) %0, i64 noundef %1, i32 noundef %2) unnamed_addr #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !11
  %8 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  %9 = load i32, ptr %6, align 4, !tbaa !11
  %10 = icmp slt i32 %9, 63
  br i1 %10, label %11, label %16

11:                                               ; preds = %3
  %12 = load i64, ptr %5, align 8, !tbaa !9
  %13 = load i32, ptr %6, align 4, !tbaa !11
  %14 = zext i32 %13 to i64
  %15 = ashr i64 %12, %14
  store i64 %15, ptr %7, align 8, !tbaa !9
  br label %22

16:                                               ; preds = %3
  %17 = load i64, ptr %5, align 8, !tbaa !9
  %18 = icmp slt i64 %17, 0
  %19 = zext i1 %18 to i64
  %20 = select i1 %18, i32 -1, i32 0
  %21 = sext i32 %20 to i64
  store i64 %21, ptr %7, align 8, !tbaa !9
  br label %22

22:                                               ; preds = %16, %11
  %23 = getelementptr inbounds %"class.sc_core::sc_signed_sigref", ptr %8, i32 0, i32 1
  %24 = load ptr, ptr %23, align 8, !tbaa !13
  %25 = load i64, ptr %7, align 8, !tbaa !9
  %26 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %8, i32 0, i32 1
  %27 = load i32, ptr %26, align 8, !tbaa !17
  %28 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %8, i32 0, i32 4
  %29 = load i32, ptr %28, align 8, !tbaa !18
  %30 = load ptr, ptr %24, align 8, !tbaa !19
  %31 = getelementptr inbounds ptr, ptr %30, i64 7
  %32 = load ptr, ptr %31, align 8
  call void %32(ptr noundef nonnull align 8 dereferenceable(8) %24, i64 noundef %25, i32 noundef %27, i32 noundef %29)
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !6, i64 32}
!14 = !{!"_ZTSN7sc_core16sc_signed_sigrefE", !15, i64 0, !6, i64 32}
!15 = !{!"_ZTSN5sc_dt18sc_signed_subref_rE", !16, i64 0, !12, i64 8, !6, i64 16, !12, i64 24}
!16 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!17 = !{!15, !12, i64 8}
!18 = !{!15, !12, i64 24}
!19 = !{!20, !20, i64 0}
!20 = !{!"vtable pointer", !8, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core16sc_signed_sigref10concat_setExi(ptr nocapture noundef nonnull readonly align 8 dereferenceable(40) %0, i64 noundef %1, i32 noundef %2) unnamed_addr #0 align 2 {
  %narrow = tail call i32 @llvm.smin.i32(i32 %2, i32 63)
  %.pn = zext nneg i32 %narrow to i64
  %.0 = ashr i64 %1, %.pn
  %4 = getelementptr inbounds i8, ptr %0, i64 32
  %5 = load ptr, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = load i32, ptr %6, align 8, !tbaa !13
  %8 = getelementptr inbounds i8, ptr %0, i64 24
  %9 = load i32, ptr %8, align 8, !tbaa !14
  %10 = load ptr, ptr %5, align 8, !tbaa !15
  %11 = getelementptr inbounds i8, ptr %10, i64 56
  %12 = load ptr, ptr %11, align 8
  tail call void %12(ptr noundef nonnull align 8 dereferenceable(8) %5, i64 noundef %.0, i32 noundef %7, i32 noundef %9)
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smin.i32(i32, i32) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 32}
!6 = !{!"_ZTSN7sc_core16sc_signed_sigrefE", !7, i64 0, !12, i64 32}
!7 = !{!"_ZTSN5sc_dt18sc_signed_subref_rE", !8, i64 0, !9, i64 8, !12, i64 16, !9, i64 24}
!8 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"any pointer", !10, i64 0}
!13 = !{!7, !9, i64 8}
!14 = !{!7, !9, i64 24}
!15 = !{!16, !16, i64 0}
!16 = !{!"vtable pointer", !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass