; LLVM IR from gem5/gem5 :: ext/nomali/lib/jobcontrol.ll (ZN6NoMali10JobControl8writeRegENS_7RegAddrEj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.NoMali::RegAddr" = type { i32 }
%"class.NoMali::JobControl" = type { %"class.NoMali::GPUBlockInt", %"class.std::vector.0" }
%"class.NoMali::GPUBlockInt" = type { %"class.NoMali::GPUBlock", %"struct.NoMali::RegAddr", %"struct.NoMali::RegAddr", %"struct.NoMali::RegAddr", %"struct.NoMali::RegAddr" }
%"class.NoMali::GPUBlock" = type { ptr, ptr, %"class.NoMali::RegVector" }
%"class.NoMali::RegVector" = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<NoMali::JobSlot, std::allocator<NoMali::JobSlot>>::_Vector_impl" }
%"struct.std::_Vector_base<NoMali::JobSlot, std::allocator<NoMali::JobSlot>>::_Vector_impl" = type { %"struct.std::_Vector_base<NoMali::JobSlot, std::allocator<NoMali::JobSlot>>::_Vector_impl_data" }
%"struct.std::_Vector_base<NoMali::JobSlot, std::allocator<NoMali::JobSlot>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN6NoMaligeERKNS_7RegAddrES2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali7JobSlotESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i32 @_ZN6NoMaliL12getJobSlotNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: inlinehint mustprogress uwtable
declare hidden i32 @_ZN6NoMaliL14getJobSlotAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6NoMali10JobControl8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(80) %0, i32 %1, i32 noundef %2) unnamed_addr #5 align 2 {
  %4 = alloca %"struct.NoMali::RegAddr", align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca %"struct.NoMali::RegAddr", align 4
  %8 = alloca %"struct.NoMali::RegAddr", align 4
  %9 = alloca %"struct.NoMali::RegAddr", align 4
  %10 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  store i32 %1, ptr %10, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  %11 = load ptr, ptr %5, align 8
  %12 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %4, i32 0, i32 0
  %13 = load i32, ptr %12, align 4, !tbaa !11
  switch i32 %13, label %26 [
    i32 4, label %14
    i32 0, label %22
    i32 8, label %22
    i32 12, label %22
  ]

14:                                               ; preds = %3
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = and i32 %15, 65535
  %17 = load i32, ptr %6, align 4, !tbaa !9
  %18 = and i32 %17, -65536
  %19 = lshr i32 %18, 16
  %20 = or i32 %16, %19
  %21 = trunc i32 %20 to i16
  call void @_ZN6NoMali10JobControl13updateJsStateEt(ptr noundef nonnull align 8 dereferenceable(80) %11, i16 noundef zeroext %21)
  br label %22

22:                                               ; preds = %14, %3, %3, %3
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %7, ptr align 4 %4, i64 4, i1 false), !tbaa.struct !13
  %23 = load i32, ptr %6, align 4, !tbaa !9
  %24 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %7, i32 0, i32 0
  %25 = load i32, ptr %24, align 4
  call void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %11, i32 %25, i32 noundef %23)
  br label %42

26:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #7
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %8, i32 noundef 2048)
  %27 = call noundef zeroext i1 @_ZN6NoMaligeERKNS_7RegAddrES2_(ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %8)
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #7
  br i1 %27, label %28, label %41

28:                                               ; preds = %26
  %29 = getelementptr inbounds %"class.NoMali::JobControl", ptr %11, i32 0, i32 1
  %30 = call noundef i32 @_ZN6NoMaliL12getJobSlotNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %31 = zext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali7JobSlotESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #7
  %33 = call i32 @_ZN6NoMaliL14getJobSlotAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %34 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %9, i32 0, i32 0
  store i32 %33, ptr %34, align 4
  %35 = load i32, ptr %6, align 4, !tbaa !9
  %36 = getelementptr inbounds %"struct.NoMali::RegAddr", ptr %9, i32 0, i32 0
  %37 = load i32, ptr %36, align 4
  %38 = load ptr, ptr %32, align 8, !tbaa !14
  %39 = getelementptr inbounds ptr, ptr %38, i64 4
  %40 = load ptr, ptr %39, align 8
  call void %40(ptr noundef nonnull align 8 dereferenceable(56) %32, i32 %37, i32 noundef %35)
  br label %41

41:                                               ; preds = %28, %26
  br label %42

42:                                               ; preds = %41, %22
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6NoMali10JobControl13updateJsStateEt(ptr noundef nonnull align 8 dereferenceable(80), i16 noundef zeroext) #5 align 2

declare void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56), i32, i32 noundef) unnamed_addr #6

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTSN6NoMali7RegAddrE", !10, i64 0}
!13 = !{i64 0, i64 4, !9}
!14 = !{!15, !15, i64 0}
!15 = !{!"vtable pointer", !8, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.NoMali::RegAddr" = type { i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN6NoMaligeERKNS_7RegAddrES2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali7JobSlotESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i32 @_ZN6NoMaliL12getJobSlotNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare hidden i32 @_ZN6NoMaliL14getJobSlotAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6NoMali10JobControl8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(80) %0, i32 %1, i32 noundef %2) unnamed_addr #4 align 2 {
  %4 = alloca %"struct.NoMali::RegAddr", align 4
  %5 = alloca %"struct.NoMali::RegAddr", align 4
  store i32 %1, ptr %4, align 4
  %6 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  switch i32 %6, label %12 [
    i32 1, label %7
    i32 0, label %11
    i32 2, label %11
    i32 3, label %11
  ]

7:                                                ; preds = %3
  %8 = lshr i32 %2, 16
  %9 = or i32 %8, %2
  %10 = trunc i32 %9 to i16
  tail call void @_ZN6NoMali10JobControl13updateJsStateEt(ptr noundef nonnull align 8 dereferenceable(80) %0, i16 noundef zeroext %10)
  br label %11

11:                                               ; preds = %7, %3, %3, %3
  tail call void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 %1, i32 noundef %2)
  br label %23

12:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #7
  call void @_ZN6NoMali7RegAddrC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %5, i32 noundef 2048)
  %13 = call noundef zeroext i1 @_ZN6NoMaligeERKNS_7RegAddrES2_(ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #7
  br i1 %13, label %14, label %23

14:                                               ; preds = %12
  %15 = getelementptr inbounds i8, ptr %0, i64 56
  %16 = call noundef i32 @_ZN6NoMaliL12getJobSlotNoERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %17 = zext i32 %16 to i64
  %18 = call noundef nonnull align 8 dereferenceable(56) ptr @_ZNSt6vectorIN6NoMali7JobSlotESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %17) #7
  %19 = call i32 @_ZN6NoMaliL14getJobSlotAddrERKNS_7RegAddrE(ptr noundef nonnull align 4 dereferenceable(4) %4)
  %20 = load ptr, ptr %18, align 8, !tbaa !5
  %21 = getelementptr inbounds i8, ptr %20, i64 32
  %22 = load ptr, ptr %21, align 8
  call void %22(ptr noundef nonnull align 8 dereferenceable(56) %18, i32 %19, i32 noundef %2)
  br label %23

23:                                               ; preds = %12, %14, %11
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6NoMali10JobControl13updateJsStateEt(ptr noundef nonnull align 8 dereferenceable(80), i16 noundef zeroext) local_unnamed_addr #4 align 2

declare void @_ZN6NoMali11GPUBlockInt8writeRegENS_7RegAddrEj(ptr noundef nonnull align 8 dereferenceable(56), i32, i32 noundef) unnamed_addr #5

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #6

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass