; LLVM IR from gem5/gem5 :: ext/softfloat (f32_to_f64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.float64_t = type { i64 }
%struct.float32_t = type { i32 }
%union.ui32_f32 = type { i32 }
%struct.commonNaN = type { i8 }
%struct.exp16_sig32 = type { i64, i64 }
%union.ui64_f64 = type { i64 }

; Function Attrs: nounwind uwtable
define dso_local i64 @f32_to_f64(i32 %0) #0 {
  %2 = alloca %struct.float64_t, align 8
  %3 = alloca %struct.float32_t, align 4
  %4 = alloca %union.ui32_f32, align 4
  %5 = alloca i64, align 8
  %6 = alloca i8, align 1
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca %struct.commonNaN, align 1
  %10 = alloca i64, align 8
  %11 = alloca %struct.exp16_sig32, align 8
  %12 = alloca %union.ui64_f64, align 8
  %13 = alloca %struct.exp16_sig32, align 8
  %14 = getelementptr inbounds %struct.float32_t, ptr %3, i32 0, i32 0
  store i32 %0, ptr %14, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %4, ptr align 4 %3, i64 4, i1 false), !tbaa.struct !5
  %15 = load i32, ptr %4, align 4, !tbaa !10
  %16 = zext i32 %15 to i64
  store i64 %16, ptr %5, align 8, !tbaa !11
  %17 = load i64, ptr %5, align 8, !tbaa !11
  %18 = trunc i64 %17 to i32
  %19 = lshr i32 %18, 31
  %20 = icmp ne i32 %19, 0
  %21 = zext i1 %20 to i8
  store i8 %21, ptr %6, align 1, !tbaa !13
  %22 = load i64, ptr %5, align 8, !tbaa !11
  %23 = lshr i64 %22, 23
  %24 = and i64 %23, 255
  store i64 %24, ptr %7, align 8, !tbaa !11
  %25 = load i64, ptr %5, align 8, !tbaa !11
  %26 = and i64 %25, 8388607
  store i64 %26, ptr %8, align 8, !tbaa !11
  %27 = load i64, ptr %7, align 8, !tbaa !11
  %28 = icmp eq i64 %27, 255
  br i1 %28, label %29, label %46

29:                                               ; preds = %1
  %30 = load i64, ptr %8, align 8, !tbaa !11
  %31 = icmp ne i64 %30, 0
  br i1 %31, label %32, label %38

32:                                               ; preds = %29
  %33 = load i64, ptr %5, align 8, !tbaa !11
  %34 = and i64 %33, 4194304
  %35 = icmp ne i64 %34, 0
  br i1 %35, label %37, label %36

36:                                               ; preds = %32
  call void @softfloat_raiseFlags(i8 noundef zeroext 16)
  br label %37

37:                                               ; preds = %36, %32
  store i64 9221120237041090560, ptr %10, align 8, !tbaa !11
  br label %45

38:                                               ; preds = %29
  %39 = load i8, ptr %6, align 1, !tbaa !13, !range !15, !noundef !16
  %40 = trunc i8 %39 to i1
  %41 = zext i1 %40 to i64
  %42 = shl i64 %41, 63
  %43 = add i64 %42, 9218868437227405312
  %44 = add i64 %43, 0
  store i64 %44, ptr %10, align 8, !tbaa !11
  br label %45

45:                                               ; preds = %38, %37
  br label %83

46:                                               ; preds = %1
  %47 = load i64, ptr %7, align 8, !tbaa !11
  %48 = icmp ne i64 %47, 0
  br i1 %48, label %71, label %49

49:                                               ; preds = %46
  %50 = load i64, ptr %8, align 8, !tbaa !11
  %51 = icmp ne i64 %50, 0
  br i1 %51, label %59, label %52

52:                                               ; preds = %49
  %53 = load i8, ptr %6, align 1, !tbaa !13, !range !15, !noundef !16
  %54 = trunc i8 %53 to i1
  %55 = zext i1 %54 to i64
  %56 = shl i64 %55, 63
  %57 = add i64 %56, 0
  %58 = add i64 %57, 0
  store i64 %58, ptr %10, align 8, !tbaa !11
  br label %83

59:                                               ; preds = %49
  call void @llvm.lifetime.start.p0(i64 16, ptr %13) #4
  %60 = load i64, ptr %8, align 8, !tbaa !11
  %61 = call { i64, i64 } @softfloat_normSubnormalF32Sig(i64 noundef %60)
  %62 = getelementptr inbounds { i64, i64 }, ptr %13, i32 0, i32 0
  %63 = extractvalue { i64, i64 } %61, 0
  store i64 %63, ptr %62, align 8
  %64 = getelementptr inbounds { i64, i64 }, ptr %13, i32 0, i32 1
  %65 = extractvalue { i64, i64 } %61, 1
  store i64 %65, ptr %64, align 8
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %11, ptr align 8 %13, i64 16, i1 false), !tbaa.struct !17
  call void @llvm.lifetime.end.p0(i64 16, ptr %13) #4
  %66 = getelementptr inbounds %struct.exp16_sig32, ptr %11, i32 0, i32 0
  %67 = load i64, ptr %66, align 8, !tbaa !18
  %68 = sub nsw i64 %67, 1
  store i64 %68, ptr %7, align 8, !tbaa !11
  %69 = getelementptr inbounds %struct.exp16_sig32, ptr %11, i32 0, i32 1
  %70 = load i64, ptr %69, align 8, !tbaa !20
  store i64 %70, ptr %8, align 8, !tbaa !11
  br label %71

71:                                               ; preds = %59, %46
  %72 = load i8, ptr %6, align 1, !tbaa !13, !range !15, !noundef !16
  %73 = trunc i8 %72 to i1
  %74 = zext i1 %73 to i64
  %75 = shl i64 %74, 63
  %76 = load i64, ptr %7, align 8, !tbaa !11
  %77 = add nsw i64 %76, 896
  %78 = shl i64 %77, 52
  %79 = add i64 %75, %78
  %80 = load i64, ptr %8, align 8, !tbaa !11
  %81 = shl i64 %80, 29
  %82 = add i64 %79, %81
  store i64 %82, ptr %10, align 8, !tbaa !11
  br label %83

83:                                               ; preds = %71, %52, %45
  %84 = load i64, ptr %10, align 8, !tbaa !11
  store i64 %84, ptr %12, align 8, !tbaa !10
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %2, ptr align 8 %12, i64 8, i1 false), !tbaa.struct !21
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %85 = getelementptr inbounds %struct.float64_t, ptr %2, i32 0, i32 0
  %86 = load i64, ptr %85, align 8
  ret i64 %86
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

declare void @softfloat_raiseFlags(i8 noundef zeroext) #3

declare { i64, i64 } @softfloat_normSubnormalF32Sig(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 0, i64 4, !6}
!6 = !{!7, !7, i64 0}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!8, !8, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !8, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_Bool", !8, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = !{i64 0, i64 8, !11, i64 8, i64 8, !11}
!18 = !{!19, !12, i64 0}
!19 = !{!"exp16_sig32", !12, i64 0, !12, i64 8}
!20 = !{!19, !12, i64 8}
!21 = !{i64 0, i64 8, !11}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i64 @f32_to_f64(i32 %0) local_unnamed_addr #0 {
  %2 = zext i32 %0 to i64
  %3 = lshr i64 %2, 23
  %4 = and i64 %3, 255
  %5 = and i64 %2, 8388607
  %trunc = trunc i64 %3 to i8
  switch i8 %trunc, label %23 [
    i8 -1, label %6
    i8 0, label %14
  ]

6:                                                ; preds = %1
  %.not28 = icmp eq i64 %5, 0
  br i1 %.not28, label %10, label %7

7:                                                ; preds = %6
  %8 = and i64 %2, 4194304
  %.not30 = icmp eq i64 %8, 0
  br i1 %.not30, label %9, label %31

9:                                                ; preds = %7
  tail call void @softfloat_raiseFlags(i8 noundef zeroext 16) #2
  br label %31

10:                                               ; preds = %6
  %.lobit29 = lshr i32 %0, 31
  %11 = zext nneg i32 %.lobit29 to i64
  %12 = shl nuw i64 %11, 63
  %13 = or disjoint i64 %12, 9218868437227405312
  br label %31

14:                                               ; preds = %1
  %.not26 = icmp eq i64 %5, 0
  br i1 %.not26, label %15, label %18

15:                                               ; preds = %14
  %.lobit = lshr i32 %0, 31
  %16 = zext nneg i32 %.lobit to i64
  %17 = shl nuw i64 %16, 63
  br label %31

18:                                               ; preds = %14
  %19 = tail call { i64, i64 } @softfloat_normSubnormalF32Sig(i64 noundef %5) #2
  %20 = extractvalue { i64, i64 } %19, 0
  %21 = extractvalue { i64, i64 } %19, 1
  %22 = add nsw i64 %20, -1
  br label %23

23:                                               ; preds = %1, %18
  %.022 = phi i64 [ %21, %18 ], [ %5, %1 ]
  %.0 = phi i64 [ %22, %18 ], [ %4, %1 ]
  %.lobit27 = lshr i32 %0, 31
  %24 = zext nneg i32 %.lobit27 to i64
  %25 = shl nuw i64 %24, 63
  %26 = shl i64 %.0, 52
  %27 = shl i64 %.022, 29
  %28 = or disjoint i64 %25, 4035225266123964416
  %29 = add i64 %28, %27
  %30 = add i64 %29, %26
  br label %31

31:                                               ; preds = %7, %9, %10, %23, %15
  %.023 = phi i64 [ %13, %10 ], [ %30, %23 ], [ %17, %15 ], [ 9221120237041090560, %9 ], [ 9221120237041090560, %7 ]
  ret i64 %.023
}

declare void @softfloat_raiseFlags(i8 noundef zeroext) local_unnamed_addr #1

declare { i64, i64 } @softfloat_normSubnormalF32Sig(i64 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass