; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_thread_process)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_b" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.8", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.13", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8, [3 x i8] }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_thread_process" = type <{ %"class.sc_core::sc_process_b.base", [3 x i8], ptr, %"class.std::vector.18", i64, i32, [4 x i8] }>
%"class.sc_core::sc_process_b.base" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.8", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.13", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8 }>
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core32SC_ID_PROCESS_ALREADY_UNWINDING_E = external constant [0 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [93 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112)) #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #1 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext12preempt_withEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #1 align 2

declare void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357), i1 noundef zeroext) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core17sc_thread_process11throw_resetEb(ptr noundef nonnull align 8 dereferenceable(404) %0, i1 noundef zeroext %1) unnamed_addr #3 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  %5 = zext i1 %1 to i8
  store i8 %5, ptr %4, align 1, !tbaa !9
  %6 = load ptr, ptr %3, align 8
  %7 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %6, i32 0, i32 41
  %8 = load i8, ptr %7, align 4, !tbaa !11, !range !37, !noundef !38
  %9 = trunc i8 %8 to i1
  br i1 %9, label %10, label %12

10:                                               ; preds = %2
  %11 = call noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112) %6)
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef @_ZN7sc_core32SC_ID_PROCESS_ALREADY_UNWINDING_E, ptr noundef %11, ptr noundef @.str.3, i32 noundef 569)
  br label %43

12:                                               ; preds = %2
  %13 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %6, i32 0, i32 29
  %14 = load i32, ptr %13, align 8, !tbaa !39
  %15 = and i32 %14, 8
  %16 = icmp ne i32 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %12
  br label %43

18:                                               ; preds = %12
  %19 = load i8, ptr %4, align 1, !tbaa !9, !range !37, !noundef !38
  %20 = trunc i8 %19 to i1
  %21 = zext i1 %20 to i64
  %22 = select i1 %20, i32 3, i32 4
  %23 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %6, i32 0, i32 36
  store i32 %22, ptr %23, align 8, !tbaa !40
  %24 = getelementptr inbounds %"class.sc_core::sc_thread_process", ptr %6, i32 0, i32 5
  store i32 0, ptr %24, align 8, !tbaa !41
  %25 = load i8, ptr %4, align 1, !tbaa !9, !range !37, !noundef !38
  %26 = trunc i8 %25 to i1
  br i1 %26, label %27, label %43

27:                                               ; preds = %18
  %28 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %6, i32 0, i32 29
  %29 = load i32, ptr %28, align 8, !tbaa !39
  %30 = and i32 %29, -3
  %31 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %6, i32 0, i32 29
  store i32 %30, ptr %31, align 8, !tbaa !39
  call void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357) %6, i1 noundef zeroext false)
  %32 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %6)
  %33 = call noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16evaluation_phaseEv(ptr noundef nonnull align 8 dereferenceable(344) %32)
  br i1 %33, label %34, label %36

34:                                               ; preds = %27
  %35 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %6)
  call void @_ZN7sc_core13sc_simcontext12preempt_withEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %35, ptr noundef %6)
  br label %42

36:                                               ; preds = %27
  %37 = call noundef zeroext i1 @_ZNK7sc_core12sc_process_b11is_runnableEv(ptr noundef nonnull align 8 dereferenceable(357) %6)
  br i1 %37, label %38, label %40

38:                                               ; preds = %36
  %39 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %6)
  call void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %39, ptr noundef %6)
  br label %40

40:                                               ; preds = %38, %36
  %41 = call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %6)
  call void @_ZN7sc_core13sc_simcontext19execute_thread_nextEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %41, ptr noundef %6)
  br label %42

42:                                               ; preds = %40, %34
  br label %43

43:                                               ; preds = %42, %18, %17, %10
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16evaluation_phaseEv(ptr noundef nonnull align 8 dereferenceable(344)) #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core12sc_process_b11is_runnableEv(ptr noundef nonnull align 8 dereferenceable(357)) #4 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext19execute_thread_nextEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !10, i64 356}
!12 = !{!"_ZTSN7sc_core12sc_process_bE", !13, i64 0, !6, i64 112, !25, i64 120, !25, i64 124, !25, i64 128, !25, i64 132, !10, i64 136, !10, i64 137, !6, i64 144, !25, i64 152, !6, i64 160, !6, i64 168, !10, i64 176, !10, i64 177, !10, i64 178, !10, i64 179, !6, i64 184, !6, i64 192, !26, i64 200, !25, i64 204, !27, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !25, i64 280, !31, i64 288, !10, i64 312, !6, i64 320, !6, i64 328, !35, i64 336, !10, i64 340, !6, i64 344, !36, i64 352, !10, i64 356}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !6, i64 96, !6, i64 104}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"int", !7, i64 0}
!26 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!27 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!35 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!36 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!37 = !{i8 0, i8 2}
!38 = !{}
!39 = !{!12, !25, i64 280}
!40 = !{!12, !35, i64 336}
!41 = !{!42, !25, i64 400}
!42 = !{!"_ZTSN7sc_core17sc_thread_processE", !12, i64 0, !6, i64 360, !43, i64 368, !24, i64 392, !25, i64 400}
!43 = !{!"_ZTSSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE", !44, i64 0}
!44 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE12_Vector_implE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core32SC_ID_PROCESS_ALREADY_UNWINDING_E = external constant [0 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [93 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #1 align 2

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext12preempt_withEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #1 align 2

declare void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357), i1 noundef zeroext) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core17sc_thread_process11throw_resetEb(ptr noundef nonnull align 8 dereferenceable(404) %0, i1 noundef zeroext %1) unnamed_addr #3 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 356
  %4 = load i8, ptr %3, align 4, !tbaa !5, !range !35, !noundef !36
  %5 = trunc nuw i8 %4 to i1
  br i1 %5, label %6, label %8

6:                                                ; preds = %2
  %7 = tail call noundef ptr @_ZNK7sc_core9sc_object4nameEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 1, ptr noundef nonnull @_ZN7sc_core32SC_ID_PROCESS_ALREADY_UNWINDING_E, ptr noundef %7, ptr noundef nonnull @.str.3, i32 noundef 569)
  br label %28

8:                                                ; preds = %2
  %9 = getelementptr inbounds i8, ptr %0, i64 280
  %10 = load i32, ptr %9, align 8, !tbaa !37
  %11 = and i32 %10, 8
  %.not = icmp eq i32 %11, 0
  br i1 %.not, label %12, label %28

12:                                               ; preds = %8
  %13 = select i1 %1, i32 3, i32 4
  %14 = getelementptr inbounds i8, ptr %0, i64 336
  store i32 %13, ptr %14, align 8, !tbaa !38
  %15 = getelementptr inbounds i8, ptr %0, i64 400
  store i32 0, ptr %15, align 8, !tbaa !39
  br i1 %1, label %16, label %28

16:                                               ; preds = %12
  %17 = and i32 %10, -11
  store i32 %17, ptr %9, align 8, !tbaa !37
  tail call void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357) %0, i1 noundef zeroext false)
  %18 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  %19 = tail call noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16evaluation_phaseEv(ptr noundef nonnull align 8 dereferenceable(344) %18)
  br i1 %19, label %20, label %22

20:                                               ; preds = %16
  %21 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  tail call void @_ZN7sc_core13sc_simcontext12preempt_withEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %21, ptr noundef nonnull %0)
  br label %28

22:                                               ; preds = %16
  %23 = tail call noundef zeroext i1 @_ZNK7sc_core12sc_process_b11is_runnableEv(ptr noundef nonnull align 8 dereferenceable(357) %0)
  br i1 %23, label %24, label %26

24:                                               ; preds = %22
  %25 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  tail call void @_ZN7sc_core13sc_simcontext22remove_runnable_threadEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %25, ptr noundef nonnull %0)
  br label %26

26:                                               ; preds = %24, %22
  %27 = tail call noundef ptr @_ZNK7sc_core9sc_object10simcontextEv(ptr noundef nonnull align 8 dereferenceable(112) %0)
  tail call void @_ZN7sc_core13sc_simcontext19execute_thread_nextEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344) %27, ptr noundef nonnull %0)
  br label %28

28:                                               ; preds = %20, %26, %8, %12, %6
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16evaluation_phaseEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core12sc_process_b11is_runnableEv(ptr noundef nonnull align 8 dereferenceable(357)) local_unnamed_addr #4 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext19execute_thread_nextEPNS_17sc_thread_processE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !23, i64 356}
!6 = !{!"_ZTSN7sc_core12sc_process_bE", !7, i64 0, !8, i64 112, !22, i64 120, !22, i64 124, !22, i64 128, !22, i64 132, !23, i64 136, !23, i64 137, !8, i64 144, !22, i64 152, !8, i64 160, !8, i64 168, !23, i64 176, !23, i64 177, !23, i64 178, !23, i64 179, !8, i64 184, !8, i64 192, !24, i64 200, !22, i64 204, !25, i64 208, !8, i64 232, !8, i64 240, !8, i64 248, !8, i64 256, !9, i64 264, !22, i64 280, !29, i64 288, !23, i64 312, !8, i64 320, !8, i64 328, !33, i64 336, !23, i64 340, !8, i64 344, !34, i64 352, !23, i64 356}
!7 = !{!"_ZTSN7sc_core9sc_objectE", !8, i64 8, !11, i64 16, !15, i64 40, !19, i64 64, !8, i64 96, !8, i64 104}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!15 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !21, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !8, i64 0}
!21 = !{!"long", !9, i64 0}
!22 = !{!"int", !9, i64 0}
!23 = !{!"bool", !9, i64 0}
!24 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !9, i64 0}
!25 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!29 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!33 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !9, i64 0}
!34 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !9, i64 0}
!35 = !{i8 0, i8 2}
!36 = !{}
!37 = !{!6, !22, i64 280}
!38 = !{!6, !33, i64 336}
!39 = !{!40, !22, i64 400}
!40 = !{!"_ZTSN7sc_core17sc_thread_processE", !6, i64 0, !8, i64 360, !41, i64 368, !21, i64 392, !22, i64 400}
!41 = !{!"_ZTSSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass