; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int (sc_signed)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef, ptr noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt17mul_signed_friendEiiiPKjiiS1_(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_signed") align 8 %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, ptr noundef %7) #2 {
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  store ptr %0, ptr %9, align 8
  store i32 %1, ptr %10, align 4, !tbaa !5
  store i32 %2, ptr %11, align 4, !tbaa !5
  store i32 %3, ptr %12, align 4, !tbaa !5
  store ptr %4, ptr %13, align 8, !tbaa !9
  store i32 %5, ptr %14, align 4, !tbaa !5
  store i32 %6, ptr %15, align 4, !tbaa !5
  store ptr %7, ptr %16, align 8, !tbaa !9
  %22 = load i32, ptr %12, align 4, !tbaa !5
  %23 = load ptr, ptr %13, align 8, !tbaa !9
  %24 = call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %22, ptr noundef %23)
  store i32 %24, ptr %12, align 4, !tbaa !5
  %25 = load i32, ptr %15, align 4, !tbaa !5
  %26 = load ptr, ptr %16, align 8, !tbaa !9
  %27 = call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %25, ptr noundef %26)
  store i32 %27, ptr %15, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #7
  %28 = load i32, ptr %11, align 4, !tbaa !5
  %29 = load i32, ptr %14, align 4, !tbaa !5
  %30 = add nsw i32 %28, %29
  store i32 %30, ptr %17, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #7
  %31 = load i32, ptr %12, align 4, !tbaa !5
  %32 = load i32, ptr %15, align 4, !tbaa !5
  %33 = add nsw i32 %31, %32
  store i32 %33, ptr %18, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #7
  %34 = load i32, ptr %18, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %35, i64 4)
  %37 = extractvalue { i64, i1 } %36, 1
  %38 = extractvalue { i64, i1 } %36, 0
  %39 = select i1 %37, i64 -1, i64 %38
  %40 = call noalias noundef nonnull ptr @_Znam(i64 noundef %39) #8
  store ptr %40, ptr %19, align 8, !tbaa !9
  %41 = load i32, ptr %18, align 4, !tbaa !5
  %42 = load ptr, ptr %19, align 8, !tbaa !9
  call void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef %41, ptr noundef %42)
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #7
  %43 = load ptr, ptr %13, align 8, !tbaa !9
  %44 = load i32, ptr %43, align 4, !tbaa !5
  store i32 %44, ptr %20, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #7
  %45 = load ptr, ptr %16, align 8, !tbaa !9
  %46 = load i32, ptr %45, align 4, !tbaa !5
  store i32 %46, ptr %21, align 4, !tbaa !5
  %47 = load i32, ptr %15, align 4, !tbaa !5
  %48 = icmp eq i32 %47, 1
  br i1 %48, label %49, label %56

49:                                               ; preds = %8
  %50 = load i32, ptr %21, align 4, !tbaa !5
  %51 = icmp eq i32 %50, 1
  br i1 %51, label %52, label %56

52:                                               ; preds = %49
  %53 = load i32, ptr %12, align 4, !tbaa !5
  %54 = load ptr, ptr %19, align 8, !tbaa !9
  %55 = load ptr, ptr %13, align 8, !tbaa !9
  call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %53, ptr noundef %54, ptr noundef %55)
  br label %131

56:                                               ; preds = %49, %8
  %57 = load i32, ptr %12, align 4, !tbaa !5
  %58 = icmp eq i32 %57, 1
  br i1 %58, label %59, label %66

59:                                               ; preds = %56
  %60 = load i32, ptr %20, align 4, !tbaa !5
  %61 = icmp eq i32 %60, 1
  br i1 %61, label %62, label %66

62:                                               ; preds = %59
  %63 = load i32, ptr %15, align 4, !tbaa !5
  %64 = load ptr, ptr %19, align 8, !tbaa !9
  %65 = load ptr, ptr %16, align 8, !tbaa !9
  call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %63, ptr noundef %64, ptr noundef %65)
  br label %130

66:                                               ; preds = %59, %56
  %67 = load i32, ptr %12, align 4, !tbaa !5
  %68 = icmp eq i32 %67, 1
  br i1 %68, label %69, label %86

69:                                               ; preds = %66
  %70 = load i32, ptr %15, align 4, !tbaa !5
  %71 = icmp eq i32 %70, 1
  br i1 %71, label %72, label %86

72:                                               ; preds = %69
  %73 = load i32, ptr %20, align 4, !tbaa !5
  %74 = zext i32 %73 to i64
  %75 = icmp ult i64 %74, 32768
  br i1 %75, label %76, label %86

76:                                               ; preds = %72
  %77 = load i32, ptr %21, align 4, !tbaa !5
  %78 = zext i32 %77 to i64
  %79 = icmp ult i64 %78, 32768
  br i1 %79, label %80, label %86

80:                                               ; preds = %76
  %81 = load i32, ptr %20, align 4, !tbaa !5
  %82 = load i32, ptr %21, align 4, !tbaa !5
  %83 = mul i32 %81, %82
  %84 = load ptr, ptr %19, align 8, !tbaa !9
  %85 = getelementptr inbounds i32, ptr %84, i64 0
  store i32 %83, ptr %85, align 4, !tbaa !5
  br label %129

86:                                               ; preds = %76, %72, %69, %66
  %87 = load i32, ptr %12, align 4, !tbaa !5
  %88 = icmp eq i32 %87, 1
  br i1 %88, label %89, label %98

89:                                               ; preds = %86
  %90 = load i32, ptr %20, align 4, !tbaa !5
  %91 = zext i32 %90 to i64
  %92 = icmp ult i64 %91, 32768
  br i1 %92, label %93, label %98

93:                                               ; preds = %89
  %94 = load i32, ptr %15, align 4, !tbaa !5
  %95 = load ptr, ptr %16, align 8, !tbaa !9
  %96 = load i32, ptr %20, align 4, !tbaa !5
  %97 = load ptr, ptr %19, align 8, !tbaa !9
  call void @_ZN5sc_dt13vec_mul_smallEiPKjjPj(i32 noundef %94, ptr noundef %95, i32 noundef %96, ptr noundef %97)
  br label %128

98:                                               ; preds = %89, %86
  %99 = load i32, ptr %15, align 4, !tbaa !5
  %100 = icmp eq i32 %99, 1
  br i1 %100, label %101, label %110

101:                                              ; preds = %98
  %102 = load i32, ptr %21, align 4, !tbaa !5
  %103 = zext i32 %102 to i64
  %104 = icmp ult i64 %103, 32768
  br i1 %104, label %105, label %110

105:                                              ; preds = %101
  %106 = load i32, ptr %12, align 4, !tbaa !5
  %107 = load ptr, ptr %13, align 8, !tbaa !9
  %108 = load i32, ptr %21, align 4, !tbaa !5
  %109 = load ptr, ptr %19, align 8, !tbaa !9
  call void @_ZN5sc_dt13vec_mul_smallEiPKjjPj(i32 noundef %106, ptr noundef %107, i32 noundef %108, ptr noundef %109)
  br label %127

110:                                              ; preds = %101, %98
  %111 = load i32, ptr %15, align 4, !tbaa !5
  %112 = load i32, ptr %12, align 4, !tbaa !5
  %113 = icmp slt i32 %111, %112
  br i1 %113, label %114, label %120

114:                                              ; preds = %110
  %115 = load i32, ptr %12, align 4, !tbaa !5
  %116 = load ptr, ptr %13, align 8, !tbaa !9
  %117 = load i32, ptr %15, align 4, !tbaa !5
  %118 = load ptr, ptr %16, align 8, !tbaa !9
  %119 = load ptr, ptr %19, align 8, !tbaa !9
  call void @_ZN5sc_dt7vec_mulEiPKjiS1_Pj(i32 noundef %115, ptr noundef %116, i32 noundef %117, ptr noundef %118, ptr noundef %119)
  br label %126

120:                                              ; preds = %110
  %121 = load i32, ptr %15, align 4, !tbaa !5
  %122 = load ptr, ptr %16, align 8, !tbaa !9
  %123 = load i32, ptr %12, align 4, !tbaa !5
  %124 = load ptr, ptr %13, align 8, !tbaa !9
  %125 = load ptr, ptr %19, align 8, !tbaa !9
  call void @_ZN5sc_dt7vec_mulEiPKjiS1_Pj(i32 noundef %121, ptr noundef %122, i32 noundef %123, ptr noundef %124, ptr noundef %125)
  br label %126

126:                                              ; preds = %120, %114
  br label %127

127:                                              ; preds = %126, %105
  br label %128

128:                                              ; preds = %127, %93
  br label %129

129:                                              ; preds = %128, %80
  br label %130

130:                                              ; preds = %129, %62
  br label %131

131:                                              ; preds = %130, %52
  %132 = load i32, ptr %10, align 4, !tbaa !5
  %133 = load i32, ptr %17, align 4, !tbaa !5
  %134 = load i32, ptr %18, align 4, !tbaa !5
  %135 = load ptr, ptr %19, align 8, !tbaa !9
  call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %132, i32 noundef %133, i32 noundef %134, ptr noundef %135, i1 noundef zeroext true)
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #7
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef, ptr noundef) #3

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #4

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef, ptr noundef, ptr noundef) #3

declare void @_ZN5sc_dt13vec_mul_smallEiPKjjPj(i32 noundef, ptr noundef, i32 noundef, ptr noundef) #6

declare void @_ZN5sc_dt7vec_mulEiPKjiS1_Pj(i32 noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) #6

declare void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr, i32, i32, i32, ptr, i1)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed" = type { %"class.sc_dt::sc_value_base", i32, i32, i32, ptr }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt17mul_signed_friendEiiiPKjiiS1_(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_signed") align 8 %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, ptr noundef %7) local_unnamed_addr #1 {
  %9 = tail call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %3, ptr noundef %4)
  %10 = tail call noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef %6, ptr noundef %7)
  %11 = add nsw i32 %10, %9
  %12 = zext nneg i32 %11 to i64
  %13 = icmp slt i32 %11, 0
  %14 = shl nuw nsw i64 %12, 2
  %15 = select i1 %13, i64 -1, i64 %14
  %16 = tail call noalias noundef nonnull ptr @_Znam(i64 noundef %15) #5
  tail call void @_ZN5sc_dt8vec_zeroEiPj(i32 noundef %11, ptr noundef nonnull %16)
  %17 = load i32, ptr %4, align 4, !tbaa !5
  %18 = load i32, ptr %7, align 4, !tbaa !5
  %19 = icmp eq i32 %10, 1
  %20 = icmp eq i32 %18, 1
  %or.cond = select i1 %19, i1 %20, i1 false
  br i1 %or.cond, label %21, label %22

21:                                               ; preds = %8
  tail call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %9, ptr noundef nonnull %16, ptr noundef nonnull %4)
  br label %39

22:                                               ; preds = %8
  %23 = icmp eq i32 %9, 1
  %24 = icmp eq i32 %17, 1
  %or.cond3 = select i1 %23, i1 %24, i1 false
  br i1 %or.cond3, label %25, label %26

25:                                               ; preds = %22
  tail call void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef %10, ptr noundef nonnull %16, ptr noundef nonnull %7)
  br label %39

26:                                               ; preds = %22
  %or.cond5 = and i1 %23, %19
  %27 = icmp ult i32 %17, 32768
  %or.cond8 = select i1 %or.cond5, i1 %27, i1 false
  %28 = icmp ult i32 %18, 32768
  %or.cond11 = select i1 %or.cond8, i1 %28, i1 false
  br i1 %or.cond11, label %29, label %31

29:                                               ; preds = %26
  %30 = mul nuw nsw i32 %18, %17
  store i32 %30, ptr %16, align 4, !tbaa !5
  br label %39

31:                                               ; preds = %26
  %or.cond14 = select i1 %23, i1 %27, i1 false
  br i1 %or.cond14, label %32, label %33

32:                                               ; preds = %31
  tail call void @_ZN5sc_dt13vec_mul_smallEiPKjjPj(i32 noundef %10, ptr noundef nonnull %7, i32 noundef %17, ptr noundef nonnull %16)
  br label %39

33:                                               ; preds = %31
  %or.cond17 = select i1 %19, i1 %28, i1 false
  br i1 %or.cond17, label %34, label %35

34:                                               ; preds = %33
  tail call void @_ZN5sc_dt13vec_mul_smallEiPKjjPj(i32 noundef %9, ptr noundef nonnull %4, i32 noundef %18, ptr noundef nonnull %16)
  br label %39

35:                                               ; preds = %33
  %36 = icmp slt i32 %10, %9
  br i1 %36, label %37, label %38

37:                                               ; preds = %35
  tail call void @_ZN5sc_dt7vec_mulEiPKjiS1_Pj(i32 noundef %9, ptr noundef nonnull %4, i32 noundef %10, ptr noundef nonnull %7, ptr noundef nonnull %16)
  br label %39

38:                                               ; preds = %35
  tail call void @_ZN5sc_dt7vec_mulEiPKjiS1_Pj(i32 noundef %10, ptr noundef nonnull %7, i32 noundef %9, ptr noundef nonnull %4, ptr noundef nonnull %16)
  br label %39

39:                                               ; preds = %25, %32, %37, %38, %34, %29, %21
  %40 = add nsw i32 %5, %2
  tail call void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr noundef nonnull align 8 dereferenceable(32) %0, i32 noundef %1, i32 noundef %40, i32 noundef %11, ptr noundef nonnull %16, i1 noundef zeroext true)
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt22vec_skip_leading_zerosEiPKj(i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8vec_copyEiPjPKj(i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @_ZN5sc_dt13vec_mul_smallEiPKjjPj(i32 noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #4

declare void @_ZN5sc_dt7vec_mulEiPKjiS1_Pj(i32 noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #4

declare void @_ZN5sc_dt9sc_signedC1EiiiPjb(ptr, i32, i32, i32, ptr, i1) local_unnamed_addr

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass