; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/stars/star111657 (star111657)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }
%struct.io_controller_m = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_out", %"class.sc_core::sc_out", %"class.sc_core::sc_inout.20", %"class.sc_core::sc_out.28", %"class.sc_core::sc_out.28", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_out.38", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in.47", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_dt::sc_uint", %"class.sc_dt::sc_uint", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", [400 x %"class.sc_dt::sc_uint"], [400 x %"class.sc_dt::sc_uint"] }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.13", ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_inout.20" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.28" = type { %"class.sc_core::sc_inout.20" }
%"class.sc_core::sc_out.38" = type { %"class.sc_core::sc_inout.39" }
%"class.sc_core::sc_inout.39" = type { %"class.sc_core::sc_port.40", ptr, ptr, ptr }
%"class.sc_core::sc_port.40" = type { %"class.sc_core::sc_port_b.41" }
%"class.sc_core::sc_port_b.41" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.42" }
%"class.std::vector.42" = type { %"struct.std::_Vector_base.43" }
%"struct.std::_Vector_base.43" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.29" = type { %"class.sc_core::sc_inout.30" }
%"class.sc_core::sc_inout.30" = type { %"class.sc_core::sc_port.31", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.31" = type { %"class.sc_core::sc_port_b.32" }
%"class.sc_core::sc_port_b.32" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.33" }
%"class.std::vector.33" = type { %"struct.std::_Vector_base.34" }
%"struct.std::_Vector_base.34" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.47" = type { %"class.sc_core::sc_port.48", ptr, ptr }
%"class.sc_core::sc_port.48" = type { %"class.sc_core::sc_port_b.49" }
%"class.sc_core::sc_port_b.49" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.50" }
%"class.std::vector.50" = type { %"struct.std::_Vector_base.51" }
%"struct.std::_Vector_base.51" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_signal" = type { %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(224)) unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 1 dereferenceable(1)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m17read_from_memory1EN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_uint") align 8, ptr noundef nonnull align 8 dereferenceable(24296), ptr noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m18write_into_memory1EN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(24296), ptr noundef, ptr noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15io_controller_m12control_readEv(ptr noundef nonnull align 8 dereferenceable(24296) %0) #2 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  %5 = alloca %"class.sc_dt::sc_uint", align 8
  %6 = alloca %"class.sc_dt::sc_uint", align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca %"class.sc_dt::sc_uint", align 8
  %12 = alloca i8, align 1
  %13 = alloca %"class.sc_dt::sc_uint", align 8
  %14 = alloca %"class.sc_dt::sc_uint", align 8
  %15 = alloca i8, align 1
  %16 = alloca i8, align 1
  %17 = alloca %"class.sc_dt::sc_uint", align 8
  %18 = alloca %"class.sc_dt::sc_uint", align 8
  %19 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %20 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %21

21:                                               ; preds = %154, %1
  br label %22

22:                                               ; preds = %21
  br label %23

23:                                               ; preds = %30, %22
  %24 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 22
  %25 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(224) %24)
  %26 = load i8, ptr %25, align 1, !tbaa !11, !range !13, !noundef !14
  %27 = trunc i8 %26 to i1
  %28 = zext i1 %27 to i32
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %23
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %20)
  br label %23, !llvm.loop !15

31:                                               ; preds = %23
  br label %32

32:                                               ; preds = %37, %31
  %33 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %34 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %33)
  %35 = load i8, ptr %34, align 1, !tbaa !11, !range !13, !noundef !14
  %36 = trunc i8 %35 to i1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %20)
  br label %32, !llvm.loop !17

38:                                               ; preds = %32
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #3
  store i8 1, ptr %4, align 1, !tbaa !11
  %39 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %40 = call noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %39, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 24, ptr %5) #3
  %41 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 25
  %42 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %41)
  %43 = load i32, ptr %3, align 4, !tbaa !9
  %44 = mul nsw i32 %43, 4
  %45 = sext i32 %44 to i64
  %46 = add i64 %42, %45
  call void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %46)
  invoke void @_ZN15io_controller_m17read_from_memory1EN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind writable sret(%"class.sc_dt::sc_uint") align 8 %5, ptr noundef nonnull align 8 dereferenceable(24296) %20, ptr noundef %6)
          to label %47 unwind label %55

47:                                               ; preds = %38
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  store i8 0, ptr %9, align 1, !tbaa !11
  %48 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %49 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %48, ptr noundef nonnull align 1 dereferenceable(1) %9)
          to label %50 unwind label %59

50:                                               ; preds = %47
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  %51 = load i32, ptr %3, align 4, !tbaa !9
  %52 = add nsw i32 %51, 1
  store i32 %52, ptr %3, align 4, !tbaa !9
  %53 = icmp eq i32 %52, 400
  br i1 %53, label %54, label %63

54:                                               ; preds = %50
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %63

55:                                               ; preds = %38
  %56 = landingpad { ptr, i32 }
          cleanup
  %57 = extractvalue { ptr, i32 } %56, 0
  store ptr %57, ptr %7, align 8
  %58 = extractvalue { ptr, i32 } %56, 1
  store i32 %58, ptr %8, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  br label %173

59:                                               ; preds = %47
  %60 = landingpad { ptr, i32 }
          cleanup
  %61 = extractvalue { ptr, i32 } %60, 0
  store ptr %61, ptr %7, align 8
  %62 = extractvalue { ptr, i32 } %60, 1
  store i32 %62, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  br label %172

63:                                               ; preds = %54, %50
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %64

64:                                               ; preds = %107, %63
  %65 = load i32, ptr %10, align 4, !tbaa !9
  %66 = icmp slt i32 %65, 400
  br i1 %66, label %68, label %67

67:                                               ; preds = %64
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %129

68:                                               ; preds = %64
  call void @llvm.lifetime.start.p0(i64 24, ptr %11) #3
  %69 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 29
  %70 = load i32, ptr %10, align 4, !tbaa !9
  %71 = sext i32 %70 to i64
  %72 = getelementptr inbounds [400 x %"class.sc_dt::sc_uint"], ptr %69, i64 0, i64 %71
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %11, ptr noundef nonnull align 8 dereferenceable(24) %72)
          to label %73 unwind label %82

73:                                               ; preds = %68
  br label %74

74:                                               ; preds = %81, %73
  %75 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %76 = invoke noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %75)
          to label %77 unwind label %86

77:                                               ; preds = %74
  %78 = load i8, ptr %76, align 1, !tbaa !11, !range !13, !noundef !14
  %79 = trunc i8 %78 to i1
  br i1 %79, label %80, label %90

80:                                               ; preds = %77
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %20)
          to label %81 unwind label %86

81:                                               ; preds = %80
  br label %74, !llvm.loop !18

82:                                               ; preds = %68
  %83 = landingpad { ptr, i32 }
          cleanup
  %84 = extractvalue { ptr, i32 } %83, 0
  store ptr %84, ptr %7, align 8
  %85 = extractvalue { ptr, i32 } %83, 1
  store i32 %85, ptr %8, align 4
  br label %128

86:                                               ; preds = %105, %95, %93, %80, %74
  %87 = landingpad { ptr, i32 }
          cleanup
  %88 = extractvalue { ptr, i32 } %87, 0
  store ptr %88, ptr %7, align 8
  %89 = extractvalue { ptr, i32 } %87, 1
  store i32 %89, ptr %8, align 4
  br label %127

90:                                               ; preds = %77
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #3
  store i8 1, ptr %12, align 1, !tbaa !11
  %91 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %92 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %91, ptr noundef nonnull align 1 dereferenceable(1) %12)
          to label %93 unwind label %110

93:                                               ; preds = %90
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #3
  %94 = invoke noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %5)
          to label %95 unwind label %86

95:                                               ; preds = %93
  %96 = load i32, ptr %10, align 4, !tbaa !9
  %97 = mul nsw i32 %96, 4
  %98 = sext i32 %97 to i64
  %99 = add i64 %94, %98
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %99)
          to label %100 unwind label %86

100:                                              ; preds = %95
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %14, ptr noundef nonnull align 8 dereferenceable(24) %11)
          to label %101 unwind label %114

101:                                              ; preds = %100
  invoke void @_ZN15io_controller_m18write_into_memory1EN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(24296) %20, ptr noundef %13, ptr noundef %14)
          to label %102 unwind label %118

102:                                              ; preds = %101
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %15) #3
  store i8 0, ptr %15, align 1, !tbaa !11
  %103 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %104 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %103, ptr noundef nonnull align 1 dereferenceable(1) %15)
          to label %105 unwind label %123

105:                                              ; preds = %102
  call void @llvm.lifetime.end.p0(i64 1, ptr %15) #3
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %20)
          to label %106 unwind label %86

106:                                              ; preds = %105
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %11) #3
  br label %107

107:                                              ; preds = %106
  %108 = load i32, ptr %10, align 4, !tbaa !9
  %109 = add nsw i32 %108, 1
  store i32 %109, ptr %10, align 4, !tbaa !9
  br label %64, !llvm.loop !19

110:                                              ; preds = %90
  %111 = landingpad { ptr, i32 }
          cleanup
  %112 = extractvalue { ptr, i32 } %111, 0
  store ptr %112, ptr %7, align 8
  %113 = extractvalue { ptr, i32 } %111, 1
  store i32 %113, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #3
  br label %127

114:                                              ; preds = %100
  %115 = landingpad { ptr, i32 }
          cleanup
  %116 = extractvalue { ptr, i32 } %115, 0
  store ptr %116, ptr %7, align 8
  %117 = extractvalue { ptr, i32 } %115, 1
  store i32 %117, ptr %8, align 4
  br label %122

118:                                              ; preds = %101
  %119 = landingpad { ptr, i32 }
          cleanup
  %120 = extractvalue { ptr, i32 } %119, 0
  store ptr %120, ptr %7, align 8
  %121 = extractvalue { ptr, i32 } %119, 1
  store i32 %121, ptr %8, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  br label %122

122:                                              ; preds = %118, %114
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  br label %127

123:                                              ; preds = %102
  %124 = landingpad { ptr, i32 }
          cleanup
  %125 = extractvalue { ptr, i32 } %124, 0
  store ptr %125, ptr %7, align 8
  %126 = extractvalue { ptr, i32 } %124, 1
  store i32 %126, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %15) #3
  br label %127

127:                                              ; preds = %123, %122, %110, %86
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #3
  br label %128

128:                                              ; preds = %127, %82
  call void @llvm.lifetime.end.p0(i64 24, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %172

129:                                              ; preds = %67
  br label %130

130:                                              ; preds = %137, %129
  %131 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %132 = invoke noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %131)
          to label %133 unwind label %138

133:                                              ; preds = %130
  %134 = load i8, ptr %132, align 1, !tbaa !11, !range !13, !noundef !14
  %135 = trunc i8 %134 to i1
  br i1 %135, label %136, label %142

136:                                              ; preds = %133
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %20)
          to label %137 unwind label %138

137:                                              ; preds = %136
  br label %130, !llvm.loop !20

138:                                              ; preds = %147, %145, %136, %130
  %139 = landingpad { ptr, i32 }
          cleanup
  %140 = extractvalue { ptr, i32 } %139, 0
  store ptr %140, ptr %7, align 8
  %141 = extractvalue { ptr, i32 } %139, 1
  store i32 %141, ptr %8, align 4
  br label %172

142:                                              ; preds = %133
  call void @llvm.lifetime.start.p0(i64 1, ptr %16) #3
  store i8 1, ptr %16, align 1, !tbaa !11
  %143 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %144 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %143, ptr noundef nonnull align 1 dereferenceable(1) %16)
          to label %145 unwind label %155

145:                                              ; preds = %142
  call void @llvm.lifetime.end.p0(i64 1, ptr %16) #3
  %146 = invoke noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %5)
          to label %147 unwind label %138

147:                                              ; preds = %145
  %148 = add i64 %146, 1604
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %148)
          to label %149 unwind label %138

149:                                              ; preds = %147
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24) %18, i32 noundef -1)
          to label %150 unwind label %159

150:                                              ; preds = %149
  invoke void @_ZN15io_controller_m18write_into_memory1EN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(24296) %20, ptr noundef %17, ptr noundef %18)
          to label %151 unwind label %163

151:                                              ; preds = %150
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %19) #3
  store i8 0, ptr %19, align 1, !tbaa !11
  %152 = getelementptr inbounds %struct.io_controller_m, ptr %20, i32 0, i32 26
  %153 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %152, ptr noundef nonnull align 1 dereferenceable(1) %19)
          to label %154 unwind label %168

154:                                              ; preds = %151
  call void @llvm.lifetime.end.p0(i64 1, ptr %19) #3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #3
  br label %21, !llvm.loop !21

155:                                              ; preds = %142
  %156 = landingpad { ptr, i32 }
          cleanup
  %157 = extractvalue { ptr, i32 } %156, 0
  store ptr %157, ptr %7, align 8
  %158 = extractvalue { ptr, i32 } %156, 1
  store i32 %158, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %16) #3
  br label %172

159:                                              ; preds = %149
  %160 = landingpad { ptr, i32 }
          cleanup
  %161 = extractvalue { ptr, i32 } %160, 0
  store ptr %161, ptr %7, align 8
  %162 = extractvalue { ptr, i32 } %160, 1
  store i32 %162, ptr %8, align 4
  br label %167

163:                                              ; preds = %150
  %164 = landingpad { ptr, i32 }
          cleanup
  %165 = extractvalue { ptr, i32 } %164, 0
  store ptr %165, ptr %7, align 8
  %166 = extractvalue { ptr, i32 } %164, 1
  store i32 %166, ptr %8, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #3
  br label %167

167:                                              ; preds = %163, %159
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  br label %172

168:                                              ; preds = %151
  %169 = landingpad { ptr, i32 }
          cleanup
  %170 = extractvalue { ptr, i32 } %169, 0
  store ptr %170, ptr %7, align 8
  %171 = extractvalue { ptr, i32 } %169, 1
  store i32 %171, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %19) #3
  br label %172

172:                                              ; preds = %168, %167, %155, %138, %128, %59
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  br label %173

173:                                              ; preds = %172, %55
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %174

174:                                              ; preds = %173
  %175 = load ptr, ptr %7, align 8
  %176 = load i32, ptr %8, align 4
  %177 = insertvalue { ptr, i32 } poison, ptr %175, 0
  %178 = insertvalue { ptr, i32 } %177, i32 %176, 1
  resume { ptr, i32 } %178
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}
!18 = distinct !{!18, !16}
!19 = distinct !{!19, !16}
!20 = distinct !{!20, !16}
!21 = distinct !{!21, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(224)) unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m17read_from_memory1EN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_uint") align 8, ptr noundef nonnull align 8 dereferenceable(24296), ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN15io_controller_m18write_into_memory1EN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(24296), ptr noundef, ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN15io_controller_m12control_readEv(ptr noundef nonnull align 8 dereferenceable(24296) %0) local_unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca i8, align 1
  %3 = alloca %"class.sc_dt::sc_uint", align 8
  %4 = alloca %"class.sc_dt::sc_uint", align 8
  %5 = alloca i8, align 1
  %6 = alloca %"class.sc_dt::sc_uint", align 8
  %7 = alloca i8, align 1
  %8 = alloca %"class.sc_dt::sc_uint", align 8
  %9 = alloca %"class.sc_dt::sc_uint", align 8
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca %"class.sc_dt::sc_uint", align 8
  %13 = alloca %"class.sc_dt::sc_uint", align 8
  %14 = alloca i8, align 1
  %15 = getelementptr inbounds i8, ptr %0, i64 4152
  %16 = getelementptr inbounds i8, ptr %0, i64 4648
  %17 = getelementptr inbounds i8, ptr %0, i64 4624
  %18 = getelementptr inbounds i8, ptr %0, i64 14696
  br label %19

19:                                               ; preds = %92, %1
  %.015 = phi i32 [ 0, %1 ], [ %spec.store.select, %92 ]
  %20 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(224) %15)
  %21 = load i8, ptr %20, align 1, !tbaa !5, !range !9, !noundef !10
  %22 = icmp eq i8 %21, 0
  br i1 %22, label %.lr.ph, label %.preheader30

.preheader30:                                     ; preds = %.lr.ph, %19
  %23 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %16)
  %24 = load i8, ptr %23, align 1, !tbaa !5, !range !9, !noundef !10
  %25 = trunc nuw i8 %24 to i1
  br i1 %25, label %.lr.ph31, label %._crit_edge

.lr.ph:                                           ; preds = %19, %.lr.ph
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %26 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4readEv(ptr noundef nonnull align 8 dereferenceable(224) %15)
  %27 = load i8, ptr %26, align 1, !tbaa !5, !range !9, !noundef !10
  %28 = icmp eq i8 %27, 0
  br i1 %28, label %.lr.ph, label %.preheader30, !llvm.loop !11

.lr.ph31:                                         ; preds = %.preheader30, %.lr.ph31
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %29 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %16)
  %30 = load i8, ptr %29, align 1, !tbaa !5, !range !9, !noundef !10
  %31 = trunc nuw i8 %30 to i1
  br i1 %31, label %.lr.ph31, label %._crit_edge, !llvm.loop !13

._crit_edge:                                      ; preds = %.lr.ph31, %.preheader30
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #4
  store i8 1, ptr %2, align 1, !tbaa !5
  %32 = call noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %16, ptr noundef nonnull align 1 dereferenceable(1) %2)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #4
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %3) #4
  %33 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %17)
  %34 = shl nsw i32 %.015, 2
  %35 = sext i32 %34 to i64
  %36 = add i64 %33, %35
  call void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %36)
  invoke void @_ZN15io_controller_m17read_from_memory1EN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind nonnull writable sret(%"class.sc_dt::sc_uint") align 8 %3, ptr noundef nonnull align 8 dereferenceable(24296) %0, ptr noundef nonnull %4)
          to label %37 unwind label %42

37:                                               ; preds = %._crit_edge
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #4
  store i8 0, ptr %5, align 1, !tbaa !5
  %38 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %16, ptr noundef nonnull align 1 dereferenceable(1) %5)
          to label %39 unwind label %44

39:                                               ; preds = %37
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #4
  %40 = add nsw i32 %.015, 1
  %41 = icmp eq i32 %40, 400
  %spec.store.select = select i1 %41, i32 0, i32 %40
  br label %46

42:                                               ; preds = %._crit_edge
  %43 = landingpad { ptr, i32 }
          cleanup
  br label %102

44:                                               ; preds = %37
  %45 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #4
  br label %102

46:                                               ; preds = %39, %66
  %indvars.iv = phi i64 [ 0, %39 ], [ %indvars.iv.next, %66 ]
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %6) #4
  %47 = getelementptr inbounds [400 x %"class.sc_dt::sc_uint"], ptr %18, i64 0, i64 %indvars.iv
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 8 dereferenceable(24) %47)
          to label %.preheader unwind label %53

.preheader:                                       ; preds = %46, %52
  %48 = invoke noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %16)
          to label %49 unwind label %.loopexit

49:                                               ; preds = %.preheader
  %50 = load i8, ptr %48, align 1, !tbaa !5, !range !9, !noundef !10
  %51 = trunc nuw i8 %50 to i1
  br i1 %51, label %52, label %55

52:                                               ; preds = %49
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %.preheader unwind label %.loopexit, !llvm.loop !14

53:                                               ; preds = %46
  %54 = landingpad { ptr, i32 }
          cleanup
  br label %77

.loopexit:                                        ; preds = %.preheader, %52
  %lpad.loopexit = landingpad { ptr, i32 }
          cleanup
  br label %76

.loopexit.split-lp:                               ; preds = %57, %65
  %lpad.loopexit.split-lp = landingpad { ptr, i32 }
          cleanup
  br label %76

55:                                               ; preds = %49
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %7) #4
  store i8 1, ptr %7, align 1, !tbaa !5
  %56 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %16, ptr noundef nonnull align 1 dereferenceable(1) %7)
          to label %57 unwind label %67

57:                                               ; preds = %55
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %7) #4
  %58 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %3)
  %59 = shl nuw nsw i64 %indvars.iv, 2
  %60 = add i64 %58, %59
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %60)
          to label %61 unwind label %.loopexit.split-lp

61:                                               ; preds = %57
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %9, ptr noundef nonnull align 8 dereferenceable(24) %6)
          to label %62 unwind label %69

62:                                               ; preds = %61
  invoke void @_ZN15io_controller_m18write_into_memory1EN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(24296) %0, ptr noundef nonnull %8, ptr noundef nonnull %9)
          to label %63 unwind label %71

63:                                               ; preds = %62
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %10) #4
  store i8 0, ptr %10, align 1, !tbaa !5
  %64 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %16, ptr noundef nonnull align 1 dereferenceable(1) %10)
          to label %65 unwind label %74

65:                                               ; preds = %63
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %10) #4
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %66 unwind label %.loopexit.split-lp

66:                                               ; preds = %65
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %6) #4
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 400
  br i1 %exitcond.not, label %.preheader24, label %46, !llvm.loop !15

67:                                               ; preds = %55
  %68 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %7) #4
  br label %76

69:                                               ; preds = %61
  %70 = landingpad { ptr, i32 }
          cleanup
  br label %73

71:                                               ; preds = %62
  %72 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  br label %73

73:                                               ; preds = %71, %69
  %.pn17 = phi { ptr, i32 } [ %72, %71 ], [ %70, %69 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  br label %76

74:                                               ; preds = %63
  %75 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %10) #4
  br label %76

76:                                               ; preds = %.loopexit, %.loopexit.split-lp, %74, %73, %67
  %.pn19 = phi { ptr, i32 } [ %75, %74 ], [ %.pn17, %73 ], [ %68, %67 ], [ %lpad.loopexit, %.loopexit ], [ %lpad.loopexit.split-lp, %.loopexit.split-lp ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #4
  br label %77

77:                                               ; preds = %76, %53
  %.pn19.pn = phi { ptr, i32 } [ %.pn19, %76 ], [ %54, %53 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %6) #4
  br label %102

.preheader24:                                     ; preds = %66, %82
  %78 = invoke noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %16)
          to label %79 unwind label %.loopexit25

79:                                               ; preds = %.preheader24
  %80 = load i8, ptr %78, align 1, !tbaa !5, !range !9, !noundef !10
  %81 = trunc nuw i8 %80 to i1
  br i1 %81, label %82, label %83

82:                                               ; preds = %79
  invoke void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
          to label %.preheader24 unwind label %.loopexit25, !llvm.loop !16

.loopexit25:                                      ; preds = %.preheader24, %82
  %lpad.loopexit27 = landingpad { ptr, i32 }
          cleanup
  br label %102

.loopexit.split-lp26:                             ; preds = %85
  %lpad.loopexit.split-lp28 = landingpad { ptr, i32 }
          cleanup
  br label %102

83:                                               ; preds = %79
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %11) #4
  store i8 1, ptr %11, align 1, !tbaa !5
  %84 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %16, ptr noundef nonnull align 1 dereferenceable(1) %11)
          to label %85 unwind label %93

85:                                               ; preds = %83
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %11) #4
  %86 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %3)
  %87 = add i64 %86, 1604
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %87)
          to label %88 unwind label %.loopexit.split-lp26

88:                                               ; preds = %85
  invoke void @_ZN5sc_dt7sc_uintILi32EEC2Ej(ptr noundef nonnull align 8 dereferenceable(24) %13, i32 noundef -1)
          to label %89 unwind label %95

89:                                               ; preds = %88
  invoke void @_ZN15io_controller_m18write_into_memory1EN5sc_dt7sc_uintILi32EEES2_(ptr noundef nonnull align 8 dereferenceable(24296) %0, ptr noundef nonnull %12, ptr noundef nonnull %13)
          to label %90 unwind label %97

90:                                               ; preds = %89
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %14) #4
  store i8 0, ptr %14, align 1, !tbaa !5
  %91 = invoke noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %16, ptr noundef nonnull align 1 dereferenceable(1) %14)
          to label %92 unwind label %100

92:                                               ; preds = %90
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %14) #4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #4
  br label %19, !llvm.loop !17

93:                                               ; preds = %83
  %94 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %11) #4
  br label %102

95:                                               ; preds = %88
  %96 = landingpad { ptr, i32 }
          cleanup
  br label %99

97:                                               ; preds = %89
  %98 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #4
  br label %99

99:                                               ; preds = %97, %95
  %.pn = phi { ptr, i32 } [ %98, %97 ], [ %96, %95 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  br label %102

100:                                              ; preds = %90
  %101 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %14) #4
  br label %102

102:                                              ; preds = %44, %77, %93, %99, %100, %.loopexit.split-lp26, %.loopexit25, %42
  %.sink = phi ptr [ %4, %42 ], [ %3, %.loopexit25 ], [ %3, %.loopexit.split-lp26 ], [ %3, %100 ], [ %3, %99 ], [ %3, %93 ], [ %3, %77 ], [ %3, %44 ]
  %.pn19.pn.pn.pn = phi { ptr, i32 } [ %43, %42 ], [ %lpad.loopexit27, %.loopexit25 ], [ %lpad.loopexit.split-lp28, %.loopexit.split-lp26 ], [ %101, %100 ], [ %.pn, %99 ], [ %94, %93 ], [ %.pn19.pn, %77 ], [ %45, %44 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %.sink) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #4
  resume { ptr, i32 } %.pn19.pn.pn.pn
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass