; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/compliance_1666/test001 (test001)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.sc_core::sc_signal.41" = type <{ %"class.sc_core::sc_signal_inout_if.42", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i32, [4 x i8], i64, i32, [4 x i8] }>
%"class.sc_core::sc_signal_inout_if.42" = type { %"class.sc_core::sc_signal_in_if.43", %"class.sc_core::sc_signal_write_if.44" }
%"class.sc_core::sc_signal_in_if.43" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if.44" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.3", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }
%struct.Top = type { %"class.sc_core::sc_module", %"struct.Top::Nested", ptr, %"class.sc_core::sc_signal.52", ptr, %struct.MyMod, %struct.Moda, %struct.Modb, %struct.C0, %struct.C1, %struct.C2, %struct.C3, %struct.S, %"class.sc_core::sc_signal", %struct.Mod0 }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"struct.Top::Nested" = type { %"class.sc_core::sc_module", ptr, %"class.sc_core::sc_out" }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.45", ptr, ptr, ptr }
%"class.sc_core::sc_port.45" = type { %"class.sc_core::sc_port_b.46" }
%"class.sc_core::sc_port_b.46" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.47" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.47" = type { %"struct.std::_Vector_base.48" }
%"struct.std::_Vector_base.48" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_signal.52" = type { %"class.sc_core::sc_signal_inout_if.53", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if.53" = type { %"class.sc_core::sc_signal_in_if.54", %"class.sc_core::sc_signal_write_if.55" }
%"class.sc_core::sc_signal_in_if.54" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if.55" = type { %"class.sc_core::sc_interface" }
%struct.MyMod = type { %struct.Mod, %"class.sc_core::sc_in", %struct.Chan }
%struct.Mod = type { %"class.sc_core::sc_module" }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port.56", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.56" = type { %"class.sc_core::sc_port_b.57" }
%"class.sc_core::sc_port_b.57" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.58" }
%"class.std::vector.58" = type { %"struct.std::_Vector_base.59" }
%"struct.std::_Vector_base.59" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Chan = type { i32, i8, i8, %"class.sc_core::sc_event" }
%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.63", %"class.std::vector.63", %"class.std::vector.68", %"class.std::vector.68" }
%"class.std::vector.63" = type { %"struct.std::_Vector_base.64" }
%"struct.std::_Vector_base.64" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.68" = type { %"struct.std::_Vector_base.69" }
%"struct.std::_Vector_base.69" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Moda = type { %"class.sc_core::sc_module", %"class.sc_core::sc_port", %"class.sc_core::sc_port.13", %"class.sc_core::sc_port.20", %"class.sc_core::sc_port.27", %"class.sc_core::sc_port.34", %struct.Modtype }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.20" = type { %"class.sc_core::sc_port_b.21" }
%"class.sc_core::sc_port_b.21" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.22" }
%"class.std::vector.22" = type { %"struct.std::_Vector_base.23" }
%"struct.std::_Vector_base.23" = type { %"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.27" = type { %"class.sc_core::sc_port_b.28" }
%"class.sc_core::sc_port_b.28" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.29" }
%"class.std::vector.29" = type { %"struct.std::_Vector_base.30" }
%"struct.std::_Vector_base.30" = type { %"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.34" = type { %"class.sc_core::sc_port_b.35" }
%"class.sc_core::sc_port_b.35" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.36" }
%"class.std::vector.36" = type { %"struct.std::_Vector_base.37" }
%"struct.std::_Vector_base.37" = type { %"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Modtype = type { %"class.sc_core::sc_module" }
%struct.Modb = type { %"class.sc_core::sc_module", %"class.sc_core::sc_port", %"class.sc_core::sc_port.13", %"class.sc_core::sc_port.20", %"class.sc_core::sc_port.27", %"class.sc_core::sc_port.34" }
%struct.C0 = type <{ %"class.sc_core::sc_module", i32, [4 x i8], %"class.sc_core::sc_interface" }>
%struct.C1 = type <{ %"class.sc_core::sc_interface", i32, [4 x i8] }>
%struct.C2 = type { %struct.I_F }
%struct.I_F = type { %"class.sc_core::sc_interface" }
%struct.C3 = type { %"class.sc_core::sc_object", %struct.I_F }
%struct.S = type { %struct.Modtype }
%"class.sc_core::sc_signal" = type { %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, ptr, i64, ptr }
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%struct.Mod0 = type { %"class.sc_core::sc_module" }
%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>
%struct.Link = type { ptr, ptr, ptr, ptr }

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [105 x i8], align 1
@_ZSt4cout = external global %"class.std::basic_ostream", align 8
@.str.7 = external hidden unnamed_addr constant [54 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [4 x i8], align 1
@_ZL12global_count = external hidden global i32, align 4
@.str.9 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.10 = external hidden unnamed_addr constant [21 x i8], align 1
@.str.11 = external hidden unnamed_addr constant [8 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local i32 @sc_main(i32 noundef %0, ptr noundef %1) #2 personality ptr @__gxx_personality_v0 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca %"class.sc_core::sc_signal.41", align 8
  %6 = alloca %struct.Top, align 8
  %7 = alloca %"class.sc_core::sc_module_name", align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !9
  %10 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef @.str.7)
  %11 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %10, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  call void @llvm.lifetime.start.p0(i64 200, ptr %5) #7
  call void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196) %5)
  call void @llvm.lifetime.start.p0(i64 4744, ptr %6) #7
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %7, ptr noundef @.str.8)
          to label %12 unwind label %60

12:                                               ; preds = %2
  invoke void @_ZN3TopC2EN7sc_core14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(4744) %6, ptr noundef %7)
          to label %13 unwind label %64

13:                                               ; preds = %12
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %7) #7
  %14 = getelementptr inbounds %struct.Top, ptr %6, i32 0, i32 2
  %15 = load ptr, ptr %14, align 8, !tbaa !11
  %16 = getelementptr inbounds %struct.Link, ptr %15, i32 0, i32 3
  %17 = load ptr, ptr %16, align 8, !tbaa !117
  %18 = load ptr, ptr %17, align 8, !tbaa !119
  %19 = getelementptr inbounds ptr, ptr %18, i64 28
  %20 = load ptr, ptr %19, align 8
  invoke void %20(ptr noundef nonnull align 8 dereferenceable(168) %17, ptr noundef nonnull align 8 dereferenceable(8) %5)
          to label %21 unwind label %68

21:                                               ; preds = %13
  %22 = getelementptr inbounds %struct.Top, ptr %6, i32 0, i32 2
  %23 = load ptr, ptr %22, align 8, !tbaa !11
  %24 = getelementptr inbounds %struct.Link, ptr %23, i32 0, i32 0
  %25 = load ptr, ptr %24, align 8, !tbaa !121
  %26 = getelementptr inbounds %struct.Link, ptr %25, i32 0, i32 3
  %27 = load ptr, ptr %26, align 8, !tbaa !117
  %28 = load ptr, ptr %27, align 8, !tbaa !119
  %29 = getelementptr inbounds ptr, ptr %28, i64 28
  %30 = load ptr, ptr %29, align 8
  invoke void %30(ptr noundef nonnull align 8 dereferenceable(168) %27, ptr noundef nonnull align 8 dereferenceable(8) %5)
          to label %31 unwind label %68

31:                                               ; preds = %21
  invoke void @_ZN7sc_core8sc_startEv()
          to label %32 unwind label %68

32:                                               ; preds = %31
  %33 = load i32, ptr @_ZL12global_count, align 4, !tbaa !5
  %34 = icmp eq i32 %33, 10
  br i1 %34, label %35, label %36

35:                                               ; preds = %32
  br label %38

36:                                               ; preds = %32
  invoke void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.9, ptr noundef @.str.3, i32 noundef 325)
          to label %37 unwind label %68

37:                                               ; preds = %36
  br label %38

38:                                               ; preds = %37, %35
  %39 = phi i32 [ 0, %35 ], [ 0, %37 ]
  %40 = getelementptr inbounds %struct.Top, ptr %6, i32 0, i32 4
  %41 = load ptr, ptr %40, align 8, !tbaa !122
  %42 = load ptr, ptr %41, align 8, !tbaa !119
  %43 = getelementptr inbounds ptr, ptr %42, i64 5
  %44 = load ptr, ptr %43, align 8
  %45 = invoke noundef nonnull align 4 dereferenceable(4) ptr %44(ptr noundef nonnull align 8 dereferenceable(196) %41)
          to label %46 unwind label %68

46:                                               ; preds = %38
  %47 = load i32, ptr %45, align 4, !tbaa !5
  %48 = icmp eq i32 %47, 3
  br i1 %48, label %49, label %50

49:                                               ; preds = %46
  br label %52

50:                                               ; preds = %46
  invoke void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.10, ptr noundef @.str.3, i32 noundef 326)
          to label %51 unwind label %68

51:                                               ; preds = %50
  br label %52

52:                                               ; preds = %51, %49
  %53 = phi i32 [ 0, %49 ], [ 0, %51 ]
  %54 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
          to label %55 unwind label %68

55:                                               ; preds = %52
  %56 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) %54, ptr noundef @.str.11)
          to label %57 unwind label %68

57:                                               ; preds = %55
  %58 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %56, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
          to label %59 unwind label %68

59:                                               ; preds = %57
  call void @_ZN3TopD2Ev(ptr noundef nonnull align 8 dereferenceable(4744) %6) #7
  call void @llvm.lifetime.end.p0(i64 4744, ptr %6) #7
  call void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %5) #7
  call void @llvm.lifetime.end.p0(i64 200, ptr %5) #7
  ret i32 0

60:                                               ; preds = %2
  %61 = landingpad { ptr, i32 }
          cleanup
  %62 = extractvalue { ptr, i32 } %61, 0
  store ptr %62, ptr %8, align 8
  %63 = extractvalue { ptr, i32 } %61, 1
  store i32 %63, ptr %9, align 4
  br label %72

64:                                               ; preds = %12
  %65 = landingpad { ptr, i32 }
          cleanup
  %66 = extractvalue { ptr, i32 } %65, 0
  store ptr %66, ptr %8, align 8
  %67 = extractvalue { ptr, i32 } %65, 1
  store i32 %67, ptr %9, align 4
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %7) #7
  br label %72

68:                                               ; preds = %57, %55, %52, %50, %38, %36, %31, %21, %13
  %69 = landingpad { ptr, i32 }
          cleanup
  %70 = extractvalue { ptr, i32 } %69, 0
  store ptr %70, ptr %8, align 8
  %71 = extractvalue { ptr, i32 } %69, 1
  store i32 %71, ptr %9, align 4
  call void @_ZN3TopD2Ev(ptr noundef nonnull align 8 dereferenceable(4744) %6) #7
  br label %72

72:                                               ; preds = %68, %64, %60
  call void @llvm.lifetime.end.p0(i64 4744, ptr %6) #7
  call void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %5) #7
  call void @llvm.lifetime.end.p0(i64 200, ptr %5) #7
  br label %73

73:                                               ; preds = %72
  %74 = load ptr, ptr %8, align 8
  %75 = load i32, ptr %9, align 4
  %76 = insertvalue { ptr, i32 } poison, ptr %74, 0
  %77 = insertvalue { ptr, i32 } %76, i32 %75, 1
  resume { ptr, i32 } %77
}

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #3

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #2 align 2

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN3TopC2EN7sc_core14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(4744), ptr noundef) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #4

declare void @_ZN7sc_core8sc_startEv() #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3TopD2Ev(ptr noundef nonnull align 8 dereferenceable(4744)) unnamed_addr #5 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #6 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !10, i64 648}
!12 = !{!"_ZTS3Top", !13, i64 0, !34, i64 232, !10, i64 648, !44, i64 656, !10, i64 880, !53, i64 888, !73, i64 1472, !105, i64 2696, !106, i64 3688, !107, i64 3936, !108, i64 3952, !110, i64 3960, !111, i64 4080, !112, i64 4312, !116, i64 4512}
!13 = !{!"_ZTSN7sc_core9sc_moduleE", !14, i64 0, !26, i64 112, !27, i64 120, !29, i64 144, !31, i64 168, !33, i64 192, !10, i64 200, !6, i64 208, !10, i64 216, !10, i64 224}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !10, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !10, i64 96, !10, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !10, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveE", !10, i64 0, !28, i64 8, !10, i64 16}
!28 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !10, i64 0, !30, i64 8, !10, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !10, i64 0, !32, i64 8, !10, i64 16}
!32 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!33 = !{!"bool", !7, i64 0}
!34 = !{!"_ZTSN3Top6NestedE", !13, i64 0, !10, i64 232, !35, i64 240}
!35 = !{!"_ZTSN7sc_core6sc_outIiEE", !36, i64 0}
!36 = !{!"_ZTSN7sc_core8sc_inoutIiEE", !37, i64 0, !10, i64 152, !10, i64 160, !10, i64 168}
!37 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIiEELi1ELNS_14sc_port_policyE0EEE", !38, i64 0}
!38 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIiEEEE", !39, i64 0, !10, i64 120, !40, i64 128}
!39 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !10, i64 112}
!40 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !41, i64 0}
!41 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE12_Vector_implE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!44 = !{!"_ZTSN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEE", !45, i64 0, !48, i64 16, !49, i64 144, !10, i64 168, !33, i64 176, !52, i64 184, !10, i64 192, !33, i64 200, !10, i64 208, !10, i64 216}
!45 = !{!"_ZTSN7sc_core18sc_signal_inout_ifIbEE", !46, i64 0, !47, i64 8}
!46 = !{!"_ZTSN7sc_core15sc_signal_in_ifIbEE"}
!47 = !{!"_ZTSN7sc_core18sc_signal_write_ifIbEE"}
!48 = !{!"_ZTSN7sc_core15sc_prim_channelE", !14, i64 0, !10, i64 112, !10, i64 120}
!49 = !{!"_ZTSN7sc_core22sc_writer_policy_checkILNS_16sc_writer_policyE0EEE", !50, i64 0, !51, i64 8}
!50 = !{!"_ZTSN7sc_core27sc_writer_policy_check_portE", !10, i64 0}
!51 = !{!"_ZTSN7sc_core28sc_writer_policy_check_writeE", !33, i64 0, !10, i64 8}
!52 = !{!"long long", !7, i64 0}
!53 = !{!"_ZTS5MyMod", !54, i64 0, !55, i64 232, !62, i64 416}
!54 = !{!"_ZTS3Mod", !13, i64 0}
!55 = !{!"_ZTSN7sc_core5sc_inIbEE", !56, i64 0, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176}
!56 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !57, i64 0}
!57 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !39, i64 0, !10, i64 120, !58, i64 128}
!58 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !59, i64 0}
!59 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !60, i64 0}
!60 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !61, i64 0}
!61 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!62 = !{!"_ZTS4Chan", !6, i64 0, !33, i64 4, !33, i64 5, !63, i64 8}
!63 = !{!"_ZTSN7sc_core8sc_eventE", !23, i64 0, !10, i64 32, !10, i64 40, !64, i64 48, !6, i64 52, !10, i64 56, !65, i64 64, !65, i64 88, !69, i64 112, !69, i64 136}
!64 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!65 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !66, i64 0}
!66 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !67, i64 0}
!67 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !68, i64 0}
!68 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!69 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !70, i64 0}
!70 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !71, i64 0}
!71 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !72, i64 0}
!72 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!73 = !{!"_ZTS4Moda", !13, i64 0, !74, i64 232, !80, i64 384, !86, i64 536, !92, i64 688, !98, i64 840, !104, i64 992}
!74 = !{!"_ZTSN7sc_core7sc_portI2C0Li1ELNS_14sc_port_policyE0EEE", !75, i64 0}
!75 = !{!"_ZTSN7sc_core9sc_port_bI2C0EE", !39, i64 0, !10, i64 120, !76, i64 128}
!76 = !{!"_ZTSSt6vectorIP2C0SaIS1_EE", !77, i64 0}
!77 = !{!"_ZTSSt12_Vector_baseIP2C0SaIS1_EE", !78, i64 0}
!78 = !{!"_ZTSNSt12_Vector_baseIP2C0SaIS1_EE12_Vector_implE", !79, i64 0}
!79 = !{!"_ZTSNSt12_Vector_baseIP2C0SaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!80 = !{!"_ZTSN7sc_core7sc_portI2C1Li1ELNS_14sc_port_policyE0EEE", !81, i64 0}
!81 = !{!"_ZTSN7sc_core9sc_port_bI2C1EE", !39, i64 0, !10, i64 120, !82, i64 128}
!82 = !{!"_ZTSSt6vectorIP2C1SaIS1_EE", !83, i64 0}
!83 = !{!"_ZTSSt12_Vector_baseIP2C1SaIS1_EE", !84, i64 0}
!84 = !{!"_ZTSNSt12_Vector_baseIP2C1SaIS1_EE12_Vector_implE", !85, i64 0}
!85 = !{!"_ZTSNSt12_Vector_baseIP2C1SaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!86 = !{!"_ZTSN7sc_core7sc_portI2C2Li1ELNS_14sc_port_policyE0EEE", !87, i64 0}
!87 = !{!"_ZTSN7sc_core9sc_port_bI2C2EE", !39, i64 0, !10, i64 120, !88, i64 128}
!88 = !{!"_ZTSSt6vectorIP2C2SaIS1_EE", !89, i64 0}
!89 = !{!"_ZTSSt12_Vector_baseIP2C2SaIS1_EE", !90, i64 0}
!90 = !{!"_ZTSNSt12_Vector_baseIP2C2SaIS1_EE12_Vector_implE", !91, i64 0}
!91 = !{!"_ZTSNSt12_Vector_baseIP2C2SaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!92 = !{!"_ZTSN7sc_core7sc_portI2C3Li1ELNS_14sc_port_policyE0EEE", !93, i64 0}
!93 = !{!"_ZTSN7sc_core9sc_port_bI2C3EE", !39, i64 0, !10, i64 120, !94, i64 128}
!94 = !{!"_ZTSSt6vectorIP2C3SaIS1_EE", !95, i64 0}
!95 = !{!"_ZTSSt12_Vector_baseIP2C3SaIS1_EE", !96, i64 0}
!96 = !{!"_ZTSNSt12_Vector_baseIP2C3SaIS1_EE12_Vector_implE", !97, i64 0}
!97 = !{!"_ZTSNSt12_Vector_baseIP2C3SaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!98 = !{!"_ZTSN7sc_core7sc_portINS_9sc_signalIP7ModtypeLNS_16sc_writer_policyE0EEELi1ELNS_14sc_port_policyE0EEE", !99, i64 0}
!99 = !{!"_ZTSN7sc_core9sc_port_bINS_9sc_signalIP7ModtypeLNS_16sc_writer_policyE0EEEEE", !39, i64 0, !10, i64 120, !100, i64 128}
!100 = !{!"_ZTSSt6vectorIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE", !101, i64 0}
!101 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE", !102, i64 0}
!102 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE12_Vector_implE", !103, i64 0}
!103 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!104 = !{!"_ZTS7Modtype", !13, i64 0}
!105 = !{!"_ZTS4Modb", !13, i64 0, !74, i64 232, !80, i64 384, !86, i64 536, !92, i64 688, !98, i64 840}
!106 = !{!"_ZTS2C0", !13, i64 0, !6, i64 232}
!107 = !{!"_ZTS2C1", !6, i64 8}
!108 = !{!"_ZTS2C2", !109, i64 0}
!109 = !{!"_ZTS3I_F"}
!110 = !{!"_ZTS2C3", !14, i64 0, !109, i64 112}
!111 = !{!"_ZTS1SI7ModtypeE", !104, i64 0}
!112 = !{!"_ZTSN7sc_core9sc_signalIP7ModtypeLNS_16sc_writer_policyE0EEE", !113, i64 0, !48, i64 16, !49, i64 144, !10, i64 168, !10, i64 176, !52, i64 184, !10, i64 192}
!113 = !{!"_ZTSN7sc_core18sc_signal_inout_ifIP7ModtypeEE", !114, i64 0, !115, i64 8}
!114 = !{!"_ZTSN7sc_core15sc_signal_in_ifIP7ModtypeEE"}
!115 = !{!"_ZTSN7sc_core18sc_signal_write_ifIP7ModtypeEE"}
!116 = !{!"_ZTS4Mod0", !13, i64 0}
!117 = !{!118, !10, i64 24}
!118 = !{!"_ZTS4Link", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24}
!119 = !{!120, !120, i64 0}
!120 = !{!"vtable pointer", !8, i64 0}
!121 = !{!118, !10, i64 0}
!122 = !{!12, !10, i64 880}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.sc_core::sc_signal.41" = type <{ %"class.sc_core::sc_signal_inout_if.42", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i32, [4 x i8], i64, i32, [4 x i8] }>
%"class.sc_core::sc_signal_inout_if.42" = type { %"class.sc_core::sc_signal_in_if.43", %"class.sc_core::sc_signal_write_if.44" }
%"class.sc_core::sc_signal_in_if.43" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if.44" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.3", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }
%struct.Top = type { %"class.sc_core::sc_module", %"struct.Top::Nested", ptr, %"class.sc_core::sc_signal.52", ptr, %struct.MyMod, %struct.Moda, %struct.Modb, %struct.C0, %struct.C1, %struct.C2, %struct.C3, %struct.S, %"class.sc_core::sc_signal", %struct.Mod0 }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"struct.Top::Nested" = type { %"class.sc_core::sc_module", ptr, %"class.sc_core::sc_out" }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.45", ptr, ptr, ptr }
%"class.sc_core::sc_port.45" = type { %"class.sc_core::sc_port_b.46" }
%"class.sc_core::sc_port_b.46" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.47" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.47" = type { %"struct.std::_Vector_base.48" }
%"struct.std::_Vector_base.48" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_signal.52" = type { %"class.sc_core::sc_signal_inout_if.53", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if.53" = type { %"class.sc_core::sc_signal_in_if.54", %"class.sc_core::sc_signal_write_if.55" }
%"class.sc_core::sc_signal_in_if.54" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if.55" = type { %"class.sc_core::sc_interface" }
%struct.MyMod = type { %struct.Mod, %"class.sc_core::sc_in", %struct.Chan }
%struct.Mod = type { %"class.sc_core::sc_module" }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port.56", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.56" = type { %"class.sc_core::sc_port_b.57" }
%"class.sc_core::sc_port_b.57" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.58" }
%"class.std::vector.58" = type { %"struct.std::_Vector_base.59" }
%"struct.std::_Vector_base.59" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Chan = type { i32, i8, i8, %"class.sc_core::sc_event" }
%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.63", %"class.std::vector.63", %"class.std::vector.68", %"class.std::vector.68" }
%"class.std::vector.63" = type { %"struct.std::_Vector_base.64" }
%"struct.std::_Vector_base.64" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.68" = type { %"struct.std::_Vector_base.69" }
%"struct.std::_Vector_base.69" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Moda = type { %"class.sc_core::sc_module", %"class.sc_core::sc_port", %"class.sc_core::sc_port.13", %"class.sc_core::sc_port.20", %"class.sc_core::sc_port.27", %"class.sc_core::sc_port.34", %struct.Modtype }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C0 *, std::allocator<C0 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C1 *, std::allocator<C1 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.20" = type { %"class.sc_core::sc_port_b.21" }
%"class.sc_core::sc_port_b.21" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.22" }
%"class.std::vector.22" = type { %"struct.std::_Vector_base.23" }
%"struct.std::_Vector_base.23" = type { %"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C2 *, std::allocator<C2 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.27" = type { %"class.sc_core::sc_port_b.28" }
%"class.sc_core::sc_port_b.28" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.29" }
%"class.std::vector.29" = type { %"struct.std::_Vector_base.30" }
%"struct.std::_Vector_base.30" = type { %"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl" }
%"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl" = type { %"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<C3 *, std::allocator<C3 *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_port.34" = type { %"class.sc_core::sc_port_b.35" }
%"class.sc_core::sc_port_b.35" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.36" }
%"class.std::vector.36" = type { %"struct.std::_Vector_base.37" }
%"struct.std::_Vector_base.37" = type { %"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal<Modtype *> *, std::allocator<sc_core::sc_signal<Modtype *> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Modtype = type { %"class.sc_core::sc_module" }
%struct.Modb = type { %"class.sc_core::sc_module", %"class.sc_core::sc_port", %"class.sc_core::sc_port.13", %"class.sc_core::sc_port.20", %"class.sc_core::sc_port.27", %"class.sc_core::sc_port.34" }
%struct.C0 = type <{ %"class.sc_core::sc_module", i32, [4 x i8], %"class.sc_core::sc_interface" }>
%struct.C1 = type <{ %"class.sc_core::sc_interface", i32, [4 x i8] }>
%struct.C2 = type { %struct.I_F }
%struct.I_F = type { %"class.sc_core::sc_interface" }
%struct.C3 = type { %"class.sc_core::sc_object", %struct.I_F }
%struct.S = type { %struct.Modtype }
%"class.sc_core::sc_signal" = type { %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, ptr, i64, ptr }
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%struct.Mod0 = type { %"class.sc_core::sc_module" }
%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [105 x i8], align 1
@_ZSt4cout = external global %"class.std::basic_ostream", align 8
@.str.7 = external hidden unnamed_addr constant [54 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [4 x i8], align 1
@_ZL12global_count = external hidden local_unnamed_addr global i32, align 4
@.str.9 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.10 = external hidden unnamed_addr constant [21 x i8], align 1
@.str.11 = external hidden unnamed_addr constant [8 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @sc_main(i32 noundef %0, ptr nocapture noundef readnone %1) local_unnamed_addr #2 personality ptr @__gxx_personality_v0 {
  %3 = alloca %"class.sc_core::sc_signal.41", align 8
  %4 = alloca %struct.Top, align 8
  %5 = alloca %"class.sc_core::sc_module_name", align 8
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef nonnull @.str.7)
  %7 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  call void @llvm.lifetime.start.p0(i64 200, ptr nonnull %3) #7
  call void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196) %3)
  call void @llvm.lifetime.start.p0(i64 4744, ptr nonnull %4) #7
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %5, ptr noundef nonnull @.str.8)
          to label %8 unwind label %48

8:                                                ; preds = %2
  invoke void @_ZN3TopC2EN7sc_core14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(4744) %4, ptr noundef nonnull %5)
          to label %9 unwind label %50

9:                                                ; preds = %8
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %5) #7
  %10 = getelementptr inbounds i8, ptr %4, i64 648
  %11 = load ptr, ptr %10, align 8, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %11, i64 24
  %13 = load ptr, ptr %12, align 8, !tbaa !115
  %14 = load ptr, ptr %13, align 8, !tbaa !117
  %15 = getelementptr inbounds i8, ptr %14, i64 224
  %16 = load ptr, ptr %15, align 8
  invoke void %16(ptr noundef nonnull align 8 dereferenceable(168) %13, ptr noundef nonnull align 8 dereferenceable(8) %3)
          to label %17 unwind label %52

17:                                               ; preds = %9
  %18 = load ptr, ptr %10, align 8, !tbaa !5
  %19 = load ptr, ptr %18, align 8, !tbaa !119
  %20 = getelementptr inbounds i8, ptr %19, i64 24
  %21 = load ptr, ptr %20, align 8, !tbaa !115
  %22 = load ptr, ptr %21, align 8, !tbaa !117
  %23 = getelementptr inbounds i8, ptr %22, i64 224
  %24 = load ptr, ptr %23, align 8
  invoke void %24(ptr noundef nonnull align 8 dereferenceable(168) %21, ptr noundef nonnull align 8 dereferenceable(8) %3)
          to label %25 unwind label %52

25:                                               ; preds = %17
  invoke void @_ZN7sc_core8sc_startEv()
          to label %26 unwind label %52

26:                                               ; preds = %25
  %27 = load i32, ptr @_ZL12global_count, align 4, !tbaa !120
  %28 = icmp eq i32 %27, 10
  br i1 %28, label %30, label %29

29:                                               ; preds = %26
  invoke void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.9, ptr noundef nonnull @.str.3, i32 noundef 325)
          to label %30 unwind label %52

30:                                               ; preds = %29, %26
  %31 = getelementptr inbounds i8, ptr %4, i64 880
  %32 = load ptr, ptr %31, align 8, !tbaa !121
  %33 = load ptr, ptr %32, align 8, !tbaa !117
  %34 = getelementptr inbounds i8, ptr %33, i64 40
  %35 = load ptr, ptr %34, align 8
  %36 = invoke noundef nonnull align 4 dereferenceable(4) ptr %35(ptr noundef nonnull align 8 dereferenceable(196) %32)
          to label %37 unwind label %52

37:                                               ; preds = %30
  %38 = load i32, ptr %36, align 4, !tbaa !120
  %39 = icmp eq i32 %38, 3
  br i1 %39, label %41, label %40

40:                                               ; preds = %37
  invoke void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.10, ptr noundef nonnull @.str.3, i32 noundef 326)
          to label %41 unwind label %52

41:                                               ; preds = %40, %37
  %42 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
          to label %43 unwind label %52

43:                                               ; preds = %41
  %44 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) %42, ptr noundef nonnull @.str.11)
          to label %45 unwind label %52

45:                                               ; preds = %43
  %46 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %44, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
          to label %47 unwind label %52

47:                                               ; preds = %45
  call void @_ZN3TopD2Ev(ptr noundef nonnull align 8 dereferenceable(4744) %4) #7
  call void @llvm.lifetime.end.p0(i64 4744, ptr nonnull %4) #7
  call void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %3) #7
  call void @llvm.lifetime.end.p0(i64 200, ptr nonnull %3) #7
  ret i32 0

48:                                               ; preds = %2
  %49 = landingpad { ptr, i32 }
          cleanup
  br label %54

50:                                               ; preds = %8
  %51 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %5) #7
  br label %54

52:                                               ; preds = %45, %43, %41, %40, %30, %29, %25, %17, %9
  %53 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN3TopD2Ev(ptr noundef nonnull align 8 dereferenceable(4744) %4) #7
  br label %54

54:                                               ; preds = %52, %50, %48
  %.pn = phi { ptr, i32 } [ %53, %52 ], [ %51, %50 ], [ %49, %48 ]
  call void @llvm.lifetime.end.p0(i64 4744, ptr nonnull %4) #7
  call void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196) %3) #7
  call void @llvm.lifetime.end.p0(i64 200, ptr nonnull %3) #7
  resume { ptr, i32 } %.pn
}

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEC1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #2 align 2

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN3TopC2EN7sc_core14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(4744), ptr noundef) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #4

declare void @_ZN7sc_core8sc_startEv() local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3TopD2Ev(ptr noundef nonnull align 8 dereferenceable(4744)) unnamed_addr #5 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EED1Ev(ptr noundef nonnull align 8 dereferenceable(196)) unnamed_addr #6 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 648}
!6 = !{!"_ZTS3Top", !7, i64 0, !32, i64 232, !9, i64 648, !42, i64 656, !9, i64 880, !51, i64 888, !71, i64 1472, !103, i64 2696, !104, i64 3688, !105, i64 3936, !106, i64 3952, !108, i64 3960, !109, i64 4080, !110, i64 4312, !114, i64 4512}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN3Top6NestedE", !7, i64 0, !9, i64 232, !33, i64 240}
!33 = !{!"_ZTSN7sc_core6sc_outIiEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core8sc_inoutIiEE", !35, i64 0, !9, i64 152, !9, i64 160, !9, i64 168}
!35 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIiEELi1ELNS_14sc_port_policyE0EEE", !36, i64 0}
!36 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIiEEEE", !37, i64 0, !9, i64 120, !38, i64 128}
!37 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!38 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!42 = !{!"_ZTSN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEE", !43, i64 0, !46, i64 16, !47, i64 144, !9, i64 168, !30, i64 176, !50, i64 184, !9, i64 192, !30, i64 200, !9, i64 208, !9, i64 216}
!43 = !{!"_ZTSN7sc_core18sc_signal_inout_ifIbEE", !44, i64 0, !45, i64 8}
!44 = !{!"_ZTSN7sc_core15sc_signal_in_ifIbEE"}
!45 = !{!"_ZTSN7sc_core18sc_signal_write_ifIbEE"}
!46 = !{!"_ZTSN7sc_core15sc_prim_channelE", !8, i64 0, !9, i64 112, !9, i64 120}
!47 = !{!"_ZTSN7sc_core22sc_writer_policy_checkILNS_16sc_writer_policyE0EEE", !48, i64 0, !49, i64 8}
!48 = !{!"_ZTSN7sc_core27sc_writer_policy_check_portE", !9, i64 0}
!49 = !{!"_ZTSN7sc_core28sc_writer_policy_check_writeE", !30, i64 0, !9, i64 8}
!50 = !{!"long long", !10, i64 0}
!51 = !{!"_ZTS5MyMod", !52, i64 0, !53, i64 232, !60, i64 416}
!52 = !{!"_ZTS3Mod", !7, i64 0}
!53 = !{!"_ZTSN7sc_core5sc_inIbEE", !54, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!54 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !55, i64 0}
!55 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !37, i64 0, !9, i64 120, !56, i64 128}
!56 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !57, i64 0}
!57 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !58, i64 0}
!58 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !59, i64 0}
!59 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!60 = !{!"_ZTS4Chan", !31, i64 0, !30, i64 4, !30, i64 5, !61, i64 8}
!61 = !{!"_ZTSN7sc_core8sc_eventE", !20, i64 0, !9, i64 32, !9, i64 40, !62, i64 48, !31, i64 52, !9, i64 56, !63, i64 64, !63, i64 88, !67, i64 112, !67, i64 136}
!62 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !10, i64 0}
!63 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !64, i64 0}
!64 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !65, i64 0}
!65 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !66, i64 0}
!66 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!67 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !68, i64 0}
!68 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !69, i64 0}
!69 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !70, i64 0}
!70 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!71 = !{!"_ZTS4Moda", !7, i64 0, !72, i64 232, !78, i64 384, !84, i64 536, !90, i64 688, !96, i64 840, !102, i64 992}
!72 = !{!"_ZTSN7sc_core7sc_portI2C0Li1ELNS_14sc_port_policyE0EEE", !73, i64 0}
!73 = !{!"_ZTSN7sc_core9sc_port_bI2C0EE", !37, i64 0, !9, i64 120, !74, i64 128}
!74 = !{!"_ZTSSt6vectorIP2C0SaIS1_EE", !75, i64 0}
!75 = !{!"_ZTSSt12_Vector_baseIP2C0SaIS1_EE", !76, i64 0}
!76 = !{!"_ZTSNSt12_Vector_baseIP2C0SaIS1_EE12_Vector_implE", !77, i64 0}
!77 = !{!"_ZTSNSt12_Vector_baseIP2C0SaIS1_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!78 = !{!"_ZTSN7sc_core7sc_portI2C1Li1ELNS_14sc_port_policyE0EEE", !79, i64 0}
!79 = !{!"_ZTSN7sc_core9sc_port_bI2C1EE", !37, i64 0, !9, i64 120, !80, i64 128}
!80 = !{!"_ZTSSt6vectorIP2C1SaIS1_EE", !81, i64 0}
!81 = !{!"_ZTSSt12_Vector_baseIP2C1SaIS1_EE", !82, i64 0}
!82 = !{!"_ZTSNSt12_Vector_baseIP2C1SaIS1_EE12_Vector_implE", !83, i64 0}
!83 = !{!"_ZTSNSt12_Vector_baseIP2C1SaIS1_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!84 = !{!"_ZTSN7sc_core7sc_portI2C2Li1ELNS_14sc_port_policyE0EEE", !85, i64 0}
!85 = !{!"_ZTSN7sc_core9sc_port_bI2C2EE", !37, i64 0, !9, i64 120, !86, i64 128}
!86 = !{!"_ZTSSt6vectorIP2C2SaIS1_EE", !87, i64 0}
!87 = !{!"_ZTSSt12_Vector_baseIP2C2SaIS1_EE", !88, i64 0}
!88 = !{!"_ZTSNSt12_Vector_baseIP2C2SaIS1_EE12_Vector_implE", !89, i64 0}
!89 = !{!"_ZTSNSt12_Vector_baseIP2C2SaIS1_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!90 = !{!"_ZTSN7sc_core7sc_portI2C3Li1ELNS_14sc_port_policyE0EEE", !91, i64 0}
!91 = !{!"_ZTSN7sc_core9sc_port_bI2C3EE", !37, i64 0, !9, i64 120, !92, i64 128}
!92 = !{!"_ZTSSt6vectorIP2C3SaIS1_EE", !93, i64 0}
!93 = !{!"_ZTSSt12_Vector_baseIP2C3SaIS1_EE", !94, i64 0}
!94 = !{!"_ZTSNSt12_Vector_baseIP2C3SaIS1_EE12_Vector_implE", !95, i64 0}
!95 = !{!"_ZTSNSt12_Vector_baseIP2C3SaIS1_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!96 = !{!"_ZTSN7sc_core7sc_portINS_9sc_signalIP7ModtypeLNS_16sc_writer_policyE0EEELi1ELNS_14sc_port_policyE0EEE", !97, i64 0}
!97 = !{!"_ZTSN7sc_core9sc_port_bINS_9sc_signalIP7ModtypeLNS_16sc_writer_policyE0EEEEE", !37, i64 0, !9, i64 120, !98, i64 128}
!98 = !{!"_ZTSSt6vectorIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE", !99, i64 0}
!99 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE", !100, i64 0}
!100 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE12_Vector_implE", !101, i64 0}
!101 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_signalIP7ModtypeLNS0_16sc_writer_policyE0EEESaIS6_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!102 = !{!"_ZTS7Modtype", !7, i64 0}
!103 = !{!"_ZTS4Modb", !7, i64 0, !72, i64 232, !78, i64 384, !84, i64 536, !90, i64 688, !96, i64 840}
!104 = !{!"_ZTS2C0", !7, i64 0, !31, i64 232}
!105 = !{!"_ZTS2C1", !31, i64 8}
!106 = !{!"_ZTS2C2", !107, i64 0}
!107 = !{!"_ZTS3I_F"}
!108 = !{!"_ZTS2C3", !8, i64 0, !107, i64 112}
!109 = !{!"_ZTS1SI7ModtypeE", !102, i64 0}
!110 = !{!"_ZTSN7sc_core9sc_signalIP7ModtypeLNS_16sc_writer_policyE0EEE", !111, i64 0, !46, i64 16, !47, i64 144, !9, i64 168, !9, i64 176, !50, i64 184, !9, i64 192}
!111 = !{!"_ZTSN7sc_core18sc_signal_inout_ifIP7ModtypeEE", !112, i64 0, !113, i64 8}
!112 = !{!"_ZTSN7sc_core15sc_signal_in_ifIP7ModtypeEE"}
!113 = !{!"_ZTSN7sc_core18sc_signal_write_ifIP7ModtypeEE"}
!114 = !{!"_ZTS4Mod0", !7, i64 0}
!115 = !{!116, !9, i64 24}
!116 = !{!"_ZTS4Link", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24}
!117 = !{!118, !118, i64 0}
!118 = !{!"vtable pointer", !11, i64 0}
!119 = !{!116, !9, i64 0}
!120 = !{!31, !31, i64 0}
!121 = !{!6, !9, i64 880}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass