; LLVM IR from hoodoer/ENNEoS :: enneosEncoder/phenotype.ll (ZN10CNeuralNet31getNumberOfRecurrentConnectionsEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.CNeuralNet = type { %"class.std::vector.5", i32, i32, double, i32, %"class.std::vector.0" }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<SNeuron *, std::allocator<SNeuron *>>::_Vector_impl" }
%"struct.std::_Vector_base<SNeuron *, std::allocator<SNeuron *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SNeuron *, std::allocator<SNeuron *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SNeuron *, std::allocator<SNeuron *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SNeuron = type { i32, i32, double, double, double, double, double, %"class.std::vector.10", %"class.std::vector.10" }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<SLink, std::allocator<SLink>>::_Vector_impl" }
%"struct.std::_Vector_base<SLink, std::allocator<SLink>>::_Vector_impl" = type { %"struct.std::_Vector_base<SLink, std::allocator<SLink>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SLink, std::allocator<SLink>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SLink = type <{ double, ptr, ptr, i8, [7 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP7SNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI5SLinkSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI5SLinkSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN10CNeuralNet31getNumberOfRecurrentConnectionsEv(ptr noundef nonnull align 8 dereferenceable(72) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %7 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  store i32 0, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %8

8:                                                ; preds = %49, %1
  %9 = load i32, ptr %4, align 4, !tbaa !9
  %10 = sext i32 %9 to i64
  %11 = getelementptr inbounds %class.CNeuralNet, ptr %7, i32 0, i32 0
  %12 = call noundef i64 @_ZNKSt6vectorIP7SNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11) #2
  %13 = icmp ult i64 %10, %12
  br i1 %13, label %15, label %14

14:                                               ; preds = %8
  store i32 2, ptr %5, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  br label %52

15:                                               ; preds = %8
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %16

16:                                               ; preds = %45, %15
  %17 = load i32, ptr %6, align 4, !tbaa !9
  %18 = sext i32 %17 to i64
  %19 = getelementptr inbounds %class.CNeuralNet, ptr %7, i32 0, i32 0
  %20 = load i32, ptr %4, align 4, !tbaa !9
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %21) #2
  %23 = load ptr, ptr %22, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.SNeuron, ptr %23, i32 0, i32 7
  %25 = call noundef i64 @_ZNKSt6vectorI5SLinkSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %24) #2
  %26 = icmp ult i64 %18, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %16
  store i32 5, ptr %5, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %48

28:                                               ; preds = %16
  %29 = getelementptr inbounds %class.CNeuralNet, ptr %7, i32 0, i32 0
  %30 = load i32, ptr %4, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #2
  %33 = load ptr, ptr %32, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.SNeuron, ptr %33, i32 0, i32 7
  %35 = load i32, ptr %6, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI5SLinkSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36) #2
  %38 = getelementptr inbounds %struct.SLink, ptr %37, i32 0, i32 3
  %39 = load i8, ptr %38, align 8, !tbaa !11, !range !15, !noundef !16
  %40 = trunc i8 %39 to i1
  br i1 %40, label %41, label %44

41:                                               ; preds = %28
  %42 = load i32, ptr %3, align 4, !tbaa !9
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %3, align 4, !tbaa !9
  br label %44

44:                                               ; preds = %41, %28
  br label %45

45:                                               ; preds = %44
  %46 = load i32, ptr %6, align 4, !tbaa !9
  %47 = add nsw i32 %46, 1
  store i32 %47, ptr %6, align 4, !tbaa !9
  br label %16, !llvm.loop !17

48:                                               ; preds = %27
  br label %49

49:                                               ; preds = %48
  %50 = load i32, ptr %4, align 4, !tbaa !9
  %51 = add nsw i32 %50, 1
  store i32 %51, ptr %4, align 4, !tbaa !9
  br label %8, !llvm.loop !19

52:                                               ; preds = %14
  %53 = load i32, ptr %3, align 4, !tbaa !9
  store i32 1, ptr %5, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret i32 %53
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !14, i64 24}
!12 = !{!"_ZTS5SLink", !13, i64 0, !6, i64 8, !6, i64 16, !14, i64 24}
!13 = !{!"double", !7, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP7SNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI5SLinkSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI5SLinkSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN10CNeuralNet31getNumberOfRecurrentConnectionsEv(ptr noundef nonnull align 8 dereferenceable(72) %0) local_unnamed_addr #0 align 2 {
  %2 = tail call noundef i64 @_ZNKSt6vectorIP7SNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %.not = icmp eq i64 %2, 0
  br i1 %.not, label %._crit_edge17, label %.preheader

.preheader:                                       ; preds = %1, %._crit_edge
  %indvars.iv21 = phi i64 [ %indvars.iv.next22, %._crit_edge ], [ 0, %1 ]
  %.01015 = phi i32 [ %.1.lcssa, %._crit_edge ], [ 0, %1 ]
  %3 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv21) #1
  %4 = load ptr, ptr %3, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %4, i64 48
  %6 = tail call noundef i64 @_ZNKSt6vectorI5SLinkSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #1
  %.not19 = icmp eq i64 %6, 0
  br i1 %.not19, label %._crit_edge, label %.lr.ph

._crit_edge17:                                    ; preds = %._crit_edge, %1
  %.010.lcssa = phi i32 [ 0, %1 ], [ %.1.lcssa, %._crit_edge ]
  ret i32 %.010.lcssa

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  %.1.lcssa = phi i32 [ %.01015, %.preheader ], [ %spec.select, %.lr.ph ]
  %indvars.iv.next22 = add nuw nsw i64 %indvars.iv21, 1
  %7 = tail call noundef i64 @_ZNKSt6vectorIP7SNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %8 = icmp ugt i64 %7, %indvars.iv.next22
  br i1 %8, label %.preheader, label %._crit_edge17, !llvm.loop !9

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.preheader ]
  %.113 = phi i32 [ %spec.select, %.lr.ph ], [ %.01015, %.preheader ]
  %9 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv21) #1
  %10 = load ptr, ptr %9, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %10, i64 48
  %12 = tail call noundef nonnull align 8 dereferenceable(25) ptr @_ZNSt6vectorI5SLinkSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %indvars.iv) #1
  %13 = getelementptr inbounds i8, ptr %12, i64 24
  %14 = load i8, ptr %13, align 8, !tbaa !11, !range !15, !noundef !16
  %15 = zext nneg i8 %14 to i32
  %spec.select = add nsw i32 %.113, %15
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %16 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SNeuronSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv21) #1
  %17 = load ptr, ptr %16, align 8, !tbaa !5
  %18 = getelementptr inbounds i8, ptr %17, i64 48
  %19 = tail call noundef i64 @_ZNKSt6vectorI5SLinkSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %18) #1
  %20 = icmp ugt i64 %19, %indvars.iv.next
  br i1 %20, label %.lr.ph, label %._crit_edge, !llvm.loop !17
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !14, i64 24}
!12 = !{!"_ZTS5SLink", !13, i64 0, !6, i64 8, !6, i64 16, !14, i64 24}
!13 = !{!"double", !7, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = distinct !{!17, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass