; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_wait_cthread)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4), i8 noundef signext) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core10at_negedgeERKNS_15sc_signal_in_ifIN5sc_dt8sc_logicEEEPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8, !tbaa !5
  %6 = load ptr, ptr %5, align 8, !tbaa !9
  %7 = getelementptr inbounds ptr, ptr %6, i64 7
  %8 = load ptr, ptr %7, align 8
  %9 = call noundef nonnull align 4 dereferenceable(4) ptr %8(ptr noundef nonnull align 8 dereferenceable(8) %5)
  %10 = call noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4) %9, i8 noundef signext 48)
  br i1 %10, label %11, label %22

11:                                               ; preds = %2
  br label %12

12:                                               ; preds = %14, %11
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef %13)
  br label %14

14:                                               ; preds = %12
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  %16 = load ptr, ptr %15, align 8, !tbaa !9
  %17 = getelementptr inbounds ptr, ptr %16, i64 7
  %18 = load ptr, ptr %17, align 8
  %19 = call noundef nonnull align 4 dereferenceable(4) ptr %18(ptr noundef nonnull align 8 dereferenceable(8) %15)
  %20 = call noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4) %19, i8 noundef signext 48)
  br i1 %20, label %12, label %21, !llvm.loop !11

21:                                               ; preds = %14
  br label %22

22:                                               ; preds = %21, %2
  br label %23

23:                                               ; preds = %25, %22
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef %24)
  br label %25

25:                                               ; preds = %23
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = load ptr, ptr %26, align 8, !tbaa !9
  %28 = getelementptr inbounds ptr, ptr %27, i64 7
  %29 = load ptr, ptr %28, align 8
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr %29(ptr noundef nonnull align 8 dereferenceable(8) %26)
  %31 = call noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4) %30, i8 noundef signext 49)
  br i1 %31, label %23, label %32, !llvm.loop !13

32:                                               ; preds = %25
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4), i8 noundef signext) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core10at_negedgeERKNS_15sc_signal_in_ifIN5sc_dt8sc_logicEEEPNS_13sc_simcontextE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %1) local_unnamed_addr #2 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %3, i64 56
  %5 = load ptr, ptr %4, align 8
  %6 = tail call noundef nonnull align 4 dereferenceable(4) ptr %5(ptr noundef nonnull align 8 dereferenceable(8) %0)
  %7 = tail call noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4) %6, i8 noundef signext 48)
  br i1 %7, label %.preheader, label %.loopexit.preheader

.preheader:                                       ; preds = %2, %.preheader
  tail call void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef %1)
  %8 = load ptr, ptr %0, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %8, i64 56
  %10 = load ptr, ptr %9, align 8
  %11 = tail call noundef nonnull align 4 dereferenceable(4) ptr %10(ptr noundef nonnull align 8 dereferenceable(8) %0)
  %12 = tail call noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4) %11, i8 noundef signext 48)
  br i1 %12, label %.preheader, label %.loopexit.preheader, !llvm.loop !8

.loopexit.preheader:                              ; preds = %.preheader, %2
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.preheader, %.loopexit
  tail call void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef %1)
  %13 = load ptr, ptr %0, align 8, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %13, i64 56
  %15 = load ptr, ptr %14, align 8
  %16 = tail call noundef nonnull align 4 dereferenceable(4) ptr %15(ptr noundef nonnull align 8 dereferenceable(8) %0)
  %17 = tail call noundef zeroext i1 @_ZN5sc_dteqERKNS_8sc_logicEc(ptr noundef nonnull align 4 dereferenceable(4) %16, i8 noundef signext 49)
  br i1 %17, label %.loopexit, label %18, !llvm.loop !10

18:                                               ; preds = %.loopexit
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}
!10 = distinct !{!10, !9}


; Effective O3 passes: GlobalOptPass,InstCombinePass,JumpThreadingPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass