; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_simcontext.ll (ZN7sc_core13sc_simcontext9elaborateEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }

@.str.6 = external hidden unnamed_addr constant [36 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #1

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext9elaborateEv(ptr noundef nonnull align 8 dereferenceable(344) %0) #3 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca %"class.sc_core::sc_module_name", align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i1, align 1
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %9 = load ptr, ptr %2, align 8
  %10 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 30
  %11 = load i8, ptr %10, align 1, !tbaa !9, !range !35, !noundef !36
  %12 = trunc i8 %11 to i1
  br i1 %12, label %16, label %13

13:                                               ; preds = %1
  %14 = call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %9)
  %15 = icmp ne i32 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %13, %1
  br label %84

17:                                               ; preds = %13
  %18 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 424) #7
  store i1 true, ptr %6, align 1
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %3, ptr noundef @.str.6)
          to label %19 unwind label %27

19:                                               ; preds = %17
  invoke void @_ZN7sc_core16sc_invoke_methodC2ENS_14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(424) %18, ptr noundef %3)
          to label %20 unwind label %31

20:                                               ; preds = %19
  store i1 false, ptr %6, align 1
  %21 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 24
  store ptr %18, ptr %21, align 8, !tbaa !37
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %3) #8
  %22 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 35
  store i32 2, ptr %22, align 4, !tbaa !38
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #8
  store i32 0, ptr %7, align 4, !tbaa !39
  br label %23

23:                                               ; preds = %66, %20
  %24 = load i32, ptr %7, align 4, !tbaa !39
  %25 = icmp ne i32 %24, 4
  br i1 %25, label %39, label %26

26:                                               ; preds = %23
  store i32 2, ptr %8, align 4
  br label %67

27:                                               ; preds = %17
  %28 = landingpad { ptr, i32 }
          cleanup
  %29 = extractvalue { ptr, i32 } %28, 0
  store ptr %29, ptr %4, align 8
  %30 = extractvalue { ptr, i32 } %28, 1
  store i32 %30, ptr %5, align 4
  br label %35

31:                                               ; preds = %19
  %32 = landingpad { ptr, i32 }
          cleanup
  %33 = extractvalue { ptr, i32 } %32, 0
  store ptr %33, ptr %4, align 8
  %34 = extractvalue { ptr, i32 } %32, 1
  store i32 %34, ptr %5, align 4
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %3) #8
  br label %35

35:                                               ; preds = %31, %27
  %36 = load i1, ptr %6, align 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %35
  call void @_ZdlPvm(ptr noundef %18, i64 noundef 424) #9
  br label %38

38:                                               ; preds = %37, %35
  br label %85

39:                                               ; preds = %23
  %40 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 2
  %41 = load ptr, ptr %40, align 8, !tbaa !40
  %42 = call noundef zeroext i1 @_ZN7sc_core16sc_port_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %41)
  %43 = zext i1 %42 to i32
  store i32 %43, ptr %7, align 4, !tbaa !39
  %44 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 3
  %45 = load ptr, ptr %44, align 8, !tbaa !41
  %46 = call noundef zeroext i1 @_ZN7sc_core18sc_export_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %45)
  %47 = zext i1 %46 to i32
  %48 = load i32, ptr %7, align 4, !tbaa !39
  %49 = add nsw i32 %48, %47
  store i32 %49, ptr %7, align 4, !tbaa !39
  %50 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 4
  %51 = load ptr, ptr %50, align 8, !tbaa !42
  %52 = call noundef zeroext i1 @_ZN7sc_core24sc_prim_channel_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(56) %51)
  %53 = zext i1 %52 to i32
  %54 = load i32, ptr %7, align 4, !tbaa !39
  %55 = add nsw i32 %54, %53
  store i32 %55, ptr %7, align 4, !tbaa !39
  %56 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 1
  %57 = load ptr, ptr %56, align 8, !tbaa !43
  %58 = call noundef zeroext i1 @_ZN7sc_core18sc_module_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %57)
  %59 = zext i1 %58 to i32
  %60 = load i32, ptr %7, align 4, !tbaa !39
  %61 = add nsw i32 %60, %59
  store i32 %61, ptr %7, align 4, !tbaa !39
  %62 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 27
  %63 = load i8, ptr %62, align 8, !tbaa !44, !range !35, !noundef !36
  %64 = trunc i8 %63 to i1
  br i1 %64, label %65, label %66

65:                                               ; preds = %39
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %9)
  store i32 1, ptr %8, align 4
  br label %67

66:                                               ; preds = %39
  br label %23, !llvm.loop !45

67:                                               ; preds = %65, %26
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #8
  %68 = load i32, ptr %8, align 4
  switch i32 %68, label %90 [
    i32 2, label %69
    i32 1, label %84
  ]

69:                                               ; preds = %67
  %70 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 30
  store i8 1, ptr %70, align 1, !tbaa !9
  %71 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 35
  store i32 4, ptr %71, align 4, !tbaa !38
  %72 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 2
  %73 = load ptr, ptr %72, align 8, !tbaa !40
  call void @_ZN7sc_core16sc_port_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %73)
  %74 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 3
  %75 = load ptr, ptr %74, align 8, !tbaa !41
  call void @_ZN7sc_core18sc_export_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %75)
  %76 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 4
  %77 = load ptr, ptr %76, align 8, !tbaa !42
  call void @_ZN7sc_core24sc_prim_channel_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(56) %77)
  %78 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 1
  %79 = load ptr, ptr %78, align 8, !tbaa !43
  call void @_ZN7sc_core18sc_module_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %79)
  call void @_ZN7sc_core8sc_reset16reconcile_resetsEv()
  %80 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %9, i32 0, i32 27
  %81 = load i8, ptr %80, align 8, !tbaa !44, !range !35, !noundef !36
  %82 = trunc i8 %81 to i1
  br i1 %82, label %83, label %84

83:                                               ; preds = %69
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %9)
  br label %84

84:                                               ; preds = %83, %69, %67, %16
  ret void

85:                                               ; preds = %38
  %86 = load ptr, ptr %4, align 8
  %87 = load i32, ptr %5, align 4
  %88 = insertvalue { ptr, i32 } poison, ptr %86, 0
  %89 = insertvalue { ptr, i32 } %88, i32 %87, 1
  resume { ptr, i32 } %89

90:                                               ; preds = %67
  unreachable
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) #4 align 2

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #5

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core16sc_invoke_methodC2ENS_14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(424), ptr noundef) unnamed_addr #3 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #6

declare noundef zeroext i1 @_ZN7sc_core16sc_port_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare noundef zeroext i1 @_ZN7sc_core18sc_export_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare noundef zeroext i1 @_ZN7sc_core24sc_prim_channel_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(56)) #5

declare noundef zeroext i1 @_ZN7sc_core18sc_module_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344)) #3 align 2

declare void @_ZN7sc_core16sc_port_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare void @_ZN7sc_core18sc_export_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare void @_ZN7sc_core24sc_prim_channel_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(56)) #5

declare void @_ZN7sc_core18sc_module_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) #5

declare void @_ZN7sc_core8sc_reset16reconcile_resetsEv() #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { nounwind }
attributes #9 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 299}
!10 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !11, i64 64, !6, i64 80, !13, i64 88, !14, i64 92, !15, i64 96, !19, i64 120, !23, i64 144, !19, i64 168, !6, i64 192, !27, i64 200, !13, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !31, i64 256, !31, i64 264, !6, i64 272, !32, i64 280, !32, i64 288, !13, i64 296, !13, i64 297, !13, i64 298, !13, i64 299, !33, i64 300, !6, i64 304, !13, i64 312, !13, i64 313, !34, i64 316, !13, i64 320, !6, i64 328, !6, i64 336}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !12, i64 8}
!12 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core7sc_timeE", !32, i64 0}
!32 = !{!"long long", !7, i64 0}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!35 = !{i8 0, i8 2}
!36 = !{}
!37 = !{!10, !6, i64 272}
!38 = !{!10, !34, i64 316}
!39 = !{!14, !14, i64 0}
!40 = !{!10, !6, i64 16}
!41 = !{!10, !6, i64 24}
!42 = !{!10, !6, i64 32}
!43 = !{!10, !6, i64 8}
!44 = !{!10, !13, i64 296}
!45 = distinct !{!45, !46}
!46 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>

@.str.6 = external hidden unnamed_addr constant [36 x i8], align 1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #0

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext9elaborateEv(ptr noundef nonnull align 8 dereferenceable(344) %0) local_unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca %"class.sc_core::sc_module_name", align 8
  %3 = getelementptr inbounds i8, ptr %0, i64 299
  %4 = load i8, ptr %3, align 1, !tbaa !5, !range !34, !noundef !35
  %5 = trunc nuw i8 %4 to i1
  br i1 %5, label %50, label %6

6:                                                ; preds = %1
  %7 = tail call noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  %.not = icmp eq i32 %7, 0
  br i1 %.not, label %8, label %50

8:                                                ; preds = %6
  %9 = tail call noalias noundef nonnull dereferenceable(424) ptr @_Znwm(i64 noundef 424) #6
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %2, ptr noundef nonnull @.str.6)
          to label %10 unwind label %20

10:                                               ; preds = %8
  invoke void @_ZN7sc_core16sc_invoke_methodC2ENS_14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(424) %9, ptr noundef nonnull %2)
          to label %11 unwind label %22

11:                                               ; preds = %10
  %12 = getelementptr inbounds i8, ptr %0, i64 272
  store ptr %9, ptr %12, align 8, !tbaa !36
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %2) #7
  %13 = getelementptr inbounds i8, ptr %0, i64 316
  store i32 2, ptr %13, align 4, !tbaa !37
  %14 = getelementptr inbounds i8, ptr %0, i64 16
  %15 = getelementptr inbounds i8, ptr %0, i64 24
  %16 = getelementptr inbounds i8, ptr %0, i64 32
  %17 = getelementptr inbounds i8, ptr %0, i64 8
  %18 = getelementptr inbounds i8, ptr %0, i64 296
  br label %19

19:                                               ; preds = %25, %11
  %.08 = phi i32 [ 0, %11 ], [ %40, %25 ]
  %.not12 = icmp eq i32 %.08, 4
  br i1 %.not12, label %43, label %25

20:                                               ; preds = %8
  %21 = landingpad { ptr, i32 }
          cleanup
  br label %24

22:                                               ; preds = %10
  %23 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %2) #7
  br label %24

24:                                               ; preds = %20, %22
  %.pn = phi { ptr, i32 } [ %23, %22 ], [ %21, %20 ]
  call void @_ZdlPvm(ptr noundef nonnull %9, i64 noundef 424) #8
  resume { ptr, i32 } %.pn

25:                                               ; preds = %19
  %26 = load ptr, ptr %14, align 8, !tbaa !38
  %27 = call noundef zeroext i1 @_ZN7sc_core16sc_port_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %26)
  %28 = zext i1 %27 to i32
  %29 = load ptr, ptr %15, align 8, !tbaa !39
  %30 = call noundef zeroext i1 @_ZN7sc_core18sc_export_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %29)
  %31 = zext i1 %30 to i32
  %32 = add nuw nsw i32 %31, %28
  %33 = load ptr, ptr %16, align 8, !tbaa !40
  %34 = call noundef zeroext i1 @_ZN7sc_core24sc_prim_channel_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(56) %33)
  %35 = zext i1 %34 to i32
  %36 = add nuw nsw i32 %32, %35
  %37 = load ptr, ptr %17, align 8, !tbaa !41
  %38 = call noundef zeroext i1 @_ZN7sc_core18sc_module_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %37)
  %39 = zext i1 %38 to i32
  %40 = add nuw nsw i32 %36, %39
  %41 = load i8, ptr %18, align 8, !tbaa !42, !range !34, !noundef !35
  %42 = trunc nuw i8 %41 to i1
  br i1 %42, label %.sink.split, label %19, !llvm.loop !43

43:                                               ; preds = %19
  store i8 1, ptr %3, align 1, !tbaa !5
  store i32 4, ptr %13, align 4, !tbaa !37
  %44 = load ptr, ptr %14, align 8, !tbaa !38
  call void @_ZN7sc_core16sc_port_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %44)
  %45 = load ptr, ptr %15, align 8, !tbaa !39
  call void @_ZN7sc_core18sc_export_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %45)
  %46 = load ptr, ptr %16, align 8, !tbaa !40
  call void @_ZN7sc_core24sc_prim_channel_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(56) %46)
  %47 = load ptr, ptr %17, align 8, !tbaa !41
  call void @_ZN7sc_core18sc_module_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %47)
  call void @_ZN7sc_core8sc_reset16reconcile_resetsEv()
  %48 = load i8, ptr %18, align 8, !tbaa !42, !range !34, !noundef !35
  %49 = trunc nuw i8 %48 to i1
  br i1 %49, label %.sink.split, label %50

.sink.split:                                      ; preds = %25, %43
  call void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  br label %50

50:                                               ; preds = %.sink.split, %1, %6, %43
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core13sc_simcontext10sim_statusEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #3 align 2

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core16sc_invoke_methodC2ENS_14sc_module_nameE(ptr noundef nonnull align 8 dereferenceable(424), ptr noundef) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #5

declare noundef zeroext i1 @_ZN7sc_core16sc_port_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare noundef zeroext i1 @_ZN7sc_core18sc_export_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare noundef zeroext i1 @_ZN7sc_core24sc_prim_channel_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #4

declare noundef zeroext i1 @_ZN7sc_core18sc_module_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext17do_sc_stop_actionEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #2 align 2

declare void @_ZN7sc_core16sc_port_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare void @_ZN7sc_core18sc_export_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare void @_ZN7sc_core24sc_prim_channel_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #4

declare void @_ZN7sc_core18sc_module_registry16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #4

declare void @_ZN7sc_core8sc_reset16reconcile_resetsEv() local_unnamed_addr #4

attributes #0 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { builtin allocsize(0) }
attributes #7 = { nounwind }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 299}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{i8 0, i8 2}
!35 = !{}
!36 = !{!6, !7, i64 272}
!37 = !{!6, !33, i64 316}
!38 = !{!6, !7, i64 16}
!39 = !{!6, !7, i64 24}
!40 = !{!6, !7, i64 32}
!41 = !{!6, !7, i64 8}
!42 = !{!6, !12, i64 296}
!43 = distinct !{!43, !44}
!44 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass