; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_process)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_process_b" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.18", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.23", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8, [3 x i8] }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_thread_process" = type <{ %"class.sc_core::sc_process_b.base", [3 x i8], ptr, %"class.std::vector.28", i64, i32, [4 x i8] }>
%"class.sc_core::sc_process_b.base" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.18", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.23", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8 }>
%"class.std::vector.28" = type { %"struct.std::_Vector_base.29" }
%"struct.std::_Vector_base.29" = type { %"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_process_b18disconnect_processEv(ptr noundef nonnull align 8 dereferenceable(357) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %8 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #5
  %9 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 29
  %10 = load i32, ptr %9, align 8, !tbaa !9
  %11 = and i32 %10, 8
  %12 = icmp ne i32 %11, 0
  br i1 %12, label %13, label %14

13:                                               ; preds = %1
  store i32 1, ptr %5, align 4
  br label %72

14:                                               ; preds = %1
  %15 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 21
  %16 = load i32, ptr %15, align 8, !tbaa !36
  switch i32 %16, label %46 [
    i32 2, label %17
    i32 3, label %17
  ]

17:                                               ; preds = %14, %14
  store ptr %8, ptr %4, align 8, !tbaa !5
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %"class.sc_core::sc_thread_process", ptr %18, i32 0, i32 3
  %20 = call noundef i64 @_ZNKSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %19) #5
  %21 = trunc i64 %20 to i32
  store i32 %21, ptr %3, align 4, !tbaa !37
  %22 = load i32, ptr %3, align 4, !tbaa !37
  %23 = icmp ne i32 %22, 0
  br i1 %23, label %24, label %45

24:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  store i32 0, ptr %6, align 4, !tbaa !37
  br label %25

25:                                               ; preds = %41, %24
  %26 = load i32, ptr %6, align 4, !tbaa !37
  %27 = load i32, ptr %3, align 4, !tbaa !37
  %28 = icmp slt i32 %26, %27
  br i1 %28, label %30, label %29

29:                                               ; preds = %25
  store i32 3, ptr %5, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  br label %44

30:                                               ; preds = %25
  %31 = load ptr, ptr %4, align 8, !tbaa !5
  %32 = getelementptr inbounds %"class.sc_core::sc_thread_process", ptr %31, i32 0, i32 3
  %33 = load i32, ptr %6, align 4, !tbaa !37
  %34 = sext i32 %33 to i64
  %35 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %34) #5
  %36 = load ptr, ptr %35, align 8, !tbaa !5
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = load ptr, ptr %36, align 8, !tbaa !38
  %39 = getelementptr inbounds ptr, ptr %38, i64 2
  %40 = load ptr, ptr %39, align 8
  call void %40(ptr noundef nonnull align 8 dereferenceable(8) %36, ptr noundef %37, i32 noundef 0)
  br label %41

41:                                               ; preds = %30
  %42 = load i32, ptr %6, align 4, !tbaa !37
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %6, align 4, !tbaa !37
  br label %25, !llvm.loop !40

44:                                               ; preds = %29
  br label %45

45:                                               ; preds = %44, %17
  br label %47

46:                                               ; preds = %14
  br label %47

47:                                               ; preds = %46, %45
  call void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357) %8, i1 noundef zeroext false)
  call void @_ZN7sc_core12sc_process_b20remove_static_eventsEv(ptr noundef nonnull align 8 dereferenceable(357) %8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  store i64 0, ptr %7, align 8, !tbaa !42
  br label %48

48:                                               ; preds = %59, %47
  %49 = load i64, ptr %7, align 8, !tbaa !42
  %50 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 23
  %51 = call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_resetESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %50) #5
  %52 = icmp ult i64 %49, %51
  br i1 %52, label %54, label %53

53:                                               ; preds = %48
  store i32 6, ptr %5, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %62

54:                                               ; preds = %48
  %55 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 23
  %56 = load i64, ptr %7, align 8, !tbaa !42
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %55, i64 noundef %56) #5
  %58 = load ptr, ptr %57, align 8, !tbaa !5
  call void @_ZN7sc_core8sc_reset14remove_processEPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(32) %58, ptr noundef %8)
  br label %59

59:                                               ; preds = %54
  %60 = load i64, ptr %7, align 8, !tbaa !42
  %61 = add i64 %60, 1
  store i64 %61, ptr %7, align 8, !tbaa !42
  br label %48, !llvm.loop !43

62:                                               ; preds = %53
  %63 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 23
  call void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef 0)
  %64 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 29
  store i32 8, ptr %64, align 8, !tbaa !9
  %65 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 34
  %66 = load ptr, ptr %65, align 8, !tbaa !44
  %67 = icmp ne ptr %66, null
  br i1 %67, label %68, label %71

68:                                               ; preds = %62
  %69 = getelementptr inbounds %"class.sc_core::sc_process_b", ptr %8, i32 0, i32 34
  %70 = load ptr, ptr %69, align 8, !tbaa !44
  call void @_ZN7sc_core8sc_event6notifyEv(ptr noundef nonnull align 8 dereferenceable(160) %70)
  br label %71

71:                                               ; preds = %68, %62
  call void @_ZN7sc_core12sc_process_b19reference_decrementEv(ptr noundef nonnull align 8 dereferenceable(357) %8)
  store i32 0, ptr %5, align 4
  br label %72

72:                                               ; preds = %71, %13
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  %73 = load i32, ptr %5, align 4
  switch i32 %73, label %75 [
    i32 0, label %74
    i32 1, label %74
  ]

74:                                               ; preds = %72, %72
  ret void

75:                                               ; preds = %72
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357), i1 noundef zeroext) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_process_b20remove_static_eventsEv(ptr noundef nonnull align 8 dereferenceable(357)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_resetESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

declare void @_ZN7sc_core8sc_reset14remove_processEPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef) #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

declare void @_ZN7sc_core8sc_event6notifyEv(ptr noundef nonnull align 8 dereferenceable(160)) #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_process_b19reference_decrementEv(ptr noundef nonnull align 8 dereferenceable(357)) #4 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !23, i64 280}
!10 = !{!"_ZTSN7sc_core12sc_process_bE", !11, i64 0, !6, i64 112, !23, i64 120, !23, i64 124, !23, i64 128, !23, i64 132, !24, i64 136, !24, i64 137, !6, i64 144, !23, i64 152, !6, i64 160, !6, i64 168, !24, i64 176, !24, i64 177, !24, i64 178, !24, i64 179, !6, i64 184, !6, i64 192, !25, i64 200, !23, i64 204, !26, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !23, i64 280, !30, i64 288, !24, i64 312, !6, i64 320, !6, i64 328, !34, i64 336, !24, i64 340, !6, i64 344, !35, i64 352, !24, i64 356}
!11 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !6, i64 96, !6, i64 104}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !7, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!22 = !{!"long", !7, i64 0}
!23 = !{!"int", !7, i64 0}
!24 = !{!"bool", !7, i64 0}
!25 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!26 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!35 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!36 = !{!10, !25, i64 200}
!37 = !{!23, !23, i64 0}
!38 = !{!39, !39, i64 0}
!39 = !{!"vtable pointer", !8, i64 0}
!40 = distinct !{!40, !41}
!41 = !{!"llvm.loop.mustprogress"}
!42 = !{!22, !22, i64 0}
!43 = distinct !{!43, !41}
!44 = !{!10, !6, i64 320}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core12sc_process_b18disconnect_processEv(ptr noundef nonnull align 8 dereferenceable(357) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 280
  %3 = load i32, ptr %2, align 8, !tbaa !5
  %4 = and i32 %3, 8
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %5, label %30

5:                                                ; preds = %1
  %6 = getelementptr inbounds i8, ptr %0, i64 200
  %7 = load i32, ptr %6, align 8, !tbaa !35
  %8 = and i32 %7, -2
  %switch = icmp eq i32 %8, 2
  br i1 %switch, label %9, label %.loopexit

9:                                                ; preds = %5
  %10 = getelementptr inbounds i8, ptr %0, i64 368
  %11 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #4
  %12 = trunc i64 %11 to i32
  %13 = icmp sgt i32 %12, 0
  br i1 %13, label %.lr.ph.preheader, label %.loopexit

.lr.ph.preheader:                                 ; preds = %9
  %wide.trip.count = and i64 %11, 2147483647
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next, %.lr.ph ]
  %14 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %indvars.iv) #4
  %15 = load ptr, ptr %14, align 8, !tbaa !36
  %16 = load ptr, ptr %15, align 8, !tbaa !37
  %17 = getelementptr inbounds i8, ptr %16, i64 16
  %18 = load ptr, ptr %17, align 8
  tail call void %18(ptr noundef nonnull align 8 dereferenceable(8) %15, ptr noundef nonnull %0, i32 noundef 0)
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.loopexit, label %.lr.ph, !llvm.loop !39

.loopexit:                                        ; preds = %.lr.ph, %5, %9
  tail call void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357) %0, i1 noundef zeroext false)
  tail call void @_ZN7sc_core12sc_process_b20remove_static_eventsEv(ptr noundef nonnull align 8 dereferenceable(357) %0)
  %19 = getelementptr inbounds i8, ptr %0, i64 208
  %20 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_resetESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %19) #4
  %.not19 = icmp eq i64 %20, 0
  br i1 %.not19, label %._crit_edge, label %.lr.ph18

._crit_edge:                                      ; preds = %.lr.ph18, %.loopexit
  tail call void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef 0)
  store i32 8, ptr %2, align 8, !tbaa !5
  %21 = getelementptr inbounds i8, ptr %0, i64 320
  %22 = load ptr, ptr %21, align 8, !tbaa !41
  %.not15 = icmp eq ptr %22, null
  br i1 %.not15, label %29, label %28

.lr.ph18:                                         ; preds = %.loopexit, %.lr.ph18
  %.017 = phi i64 [ %25, %.lr.ph18 ], [ 0, %.loopexit ]
  %23 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %.017) #4
  %24 = load ptr, ptr %23, align 8, !tbaa !36
  tail call void @_ZN7sc_core8sc_reset14remove_processEPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(32) %24, ptr noundef nonnull %0)
  %25 = add nuw i64 %.017, 1
  %26 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_resetESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %19) #4
  %27 = icmp ult i64 %25, %26
  br i1 %27, label %.lr.ph18, label %._crit_edge, !llvm.loop !42

28:                                               ; preds = %._crit_edge
  tail call void @_ZN7sc_core8sc_event6notifyEv(ptr noundef nonnull align 8 dereferenceable(160) %22)
  br label %29

29:                                               ; preds = %28, %._crit_edge
  tail call void @_ZN7sc_core12sc_process_b19reference_decrementEv(ptr noundef nonnull align 8 dereferenceable(357) %0)
  br label %30

30:                                               ; preds = %1, %29
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_process_b21remove_dynamic_eventsEb(ptr noundef nonnull align 8 dereferenceable(357), i1 noundef zeroext) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_process_b20remove_static_eventsEv(ptr noundef nonnull align 8 dereferenceable(357)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_resetESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

declare void @_ZN7sc_core8sc_reset14remove_processEPNS_12sc_process_bE(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_resetESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

declare void @_ZN7sc_core8sc_event6notifyEv(ptr noundef nonnull align 8 dereferenceable(160)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_process_b19reference_decrementEv(ptr noundef nonnull align 8 dereferenceable(357)) local_unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !22, i64 280}
!6 = !{!"_ZTSN7sc_core12sc_process_bE", !7, i64 0, !8, i64 112, !22, i64 120, !22, i64 124, !22, i64 128, !22, i64 132, !23, i64 136, !23, i64 137, !8, i64 144, !22, i64 152, !8, i64 160, !8, i64 168, !23, i64 176, !23, i64 177, !23, i64 178, !23, i64 179, !8, i64 184, !8, i64 192, !24, i64 200, !22, i64 204, !25, i64 208, !8, i64 232, !8, i64 240, !8, i64 248, !8, i64 256, !9, i64 264, !22, i64 280, !29, i64 288, !23, i64 312, !8, i64 320, !8, i64 328, !33, i64 336, !23, i64 340, !8, i64 344, !34, i64 352, !23, i64 356}
!7 = !{!"_ZTSN7sc_core9sc_objectE", !8, i64 8, !11, i64 16, !15, i64 40, !19, i64 64, !8, i64 96, !8, i64 104}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!15 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !21, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !8, i64 0}
!21 = !{!"long", !9, i64 0}
!22 = !{!"int", !9, i64 0}
!23 = !{!"bool", !9, i64 0}
!24 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !9, i64 0}
!25 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!29 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !8, i64 0, !8, i64 8, !8, i64 16}
!33 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !9, i64 0}
!34 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !9, i64 0}
!35 = !{!6, !24, i64 200}
!36 = !{!8, !8, i64 0}
!37 = !{!38, !38, i64 0}
!38 = !{!"vtable pointer", !10, i64 0}
!39 = distinct !{!39, !40}
!40 = !{!"llvm.loop.mustprogress"}
!41 = !{!6, !8, i64 320}
!42 = distinct !{!42, !40}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass