; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/datatypes/int (sc_signed)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_signed_subref_r" = type <{ %"class.sc_dt::sc_value_base", i32, [4 x i8], ptr, i32, [4 x i8] }>
%"class.sc_dt::sc_value_base" = type { ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32), i32 noundef, i1 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt16sc_signed_subref10concat_setExi(ptr noundef nonnull align 8 dereferenceable(28) %0, i64 noundef %1, i32 noundef %2) unnamed_addr #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !11
  %11 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  %12 = load i64, ptr %5, align 8, !tbaa !9
  %13 = icmp slt i64 %12, 0
  %14 = zext i1 %13 to i8
  store i8 %14, ptr %9, align 1, !tbaa !13
  %15 = load i32, ptr %6, align 4, !tbaa !11
  %16 = icmp slt i32 %15, 64
  br i1 %16, label %17, label %63

17:                                               ; preds = %3
  %18 = load i64, ptr %5, align 8, !tbaa !9
  %19 = load i32, ptr %6, align 4, !tbaa !11
  %20 = zext i32 %19 to i64
  %21 = ashr i64 %18, %20
  store i64 %21, ptr %5, align 8, !tbaa !9
  %22 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 1
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %23 = load i32, ptr %6, align 4, !tbaa !11
  %24 = sub nsw i32 63, %23
  %25 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 4
  %26 = load i32, ptr %25, align 8, !tbaa !15
  %27 = add nsw i32 %24, %26
  store i32 %27, ptr %10, align 4, !tbaa !11
  %28 = call noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %22, ptr noundef nonnull align 4 dereferenceable(4) %10)
  store i32 %28, ptr %8, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %29 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 4
  %30 = load i32, ptr %29, align 8, !tbaa !15
  store i32 %30, ptr %7, align 4, !tbaa !11
  br label %31

31:                                               ; preds = %44, %17
  %32 = load i32, ptr %7, align 4, !tbaa !11
  %33 = load i32, ptr %8, align 4, !tbaa !11
  %34 = icmp sle i32 %32, %33
  br i1 %34, label %35, label %47

35:                                               ; preds = %31
  %36 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 3
  %37 = load ptr, ptr %36, align 8, !tbaa !18
  %38 = load i32, ptr %7, align 4, !tbaa !11
  %39 = load i64, ptr %5, align 8, !tbaa !9
  %40 = and i64 %39, 1
  %41 = icmp ne i64 %40, 0
  call void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32) %37, i32 noundef %38, i1 noundef zeroext %41)
  %42 = load i64, ptr %5, align 8, !tbaa !9
  %43 = ashr i64 %42, 1
  store i64 %43, ptr %5, align 8, !tbaa !9
  br label %44

44:                                               ; preds = %35
  %45 = load i32, ptr %7, align 4, !tbaa !11
  %46 = add nsw i32 %45, 1
  store i32 %46, ptr %7, align 4, !tbaa !11
  br label %31, !llvm.loop !19

47:                                               ; preds = %31
  br label %48

48:                                               ; preds = %59, %47
  %49 = load i32, ptr %7, align 4, !tbaa !11
  %50 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 1
  %51 = load i32, ptr %50, align 8, !tbaa !21
  %52 = icmp sle i32 %49, %51
  br i1 %52, label %53, label %62

53:                                               ; preds = %48
  %54 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 3
  %55 = load ptr, ptr %54, align 8, !tbaa !18
  %56 = load i32, ptr %7, align 4, !tbaa !11
  %57 = load i8, ptr %9, align 1, !tbaa !13, !range !22, !noundef !23
  %58 = trunc i8 %57 to i1
  call void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32) %55, i32 noundef %56, i1 noundef zeroext %58)
  br label %59

59:                                               ; preds = %53
  %60 = load i32, ptr %7, align 4, !tbaa !11
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %7, align 4, !tbaa !11
  br label %48, !llvm.loop !24

62:                                               ; preds = %48
  br label %81

63:                                               ; preds = %3
  %64 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 4
  %65 = load i32, ptr %64, align 8, !tbaa !15
  store i32 %65, ptr %7, align 4, !tbaa !11
  br label %66

66:                                               ; preds = %77, %63
  %67 = load i32, ptr %7, align 4, !tbaa !11
  %68 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 1
  %69 = load i32, ptr %68, align 8, !tbaa !21
  %70 = icmp sle i32 %67, %69
  br i1 %70, label %71, label %80

71:                                               ; preds = %66
  %72 = getelementptr inbounds %"class.sc_dt::sc_signed_subref_r", ptr %11, i32 0, i32 3
  %73 = load ptr, ptr %72, align 8, !tbaa !18
  %74 = load i32, ptr %7, align 4, !tbaa !11
  %75 = load i8, ptr %9, align 1, !tbaa !13, !range !22, !noundef !23
  %76 = trunc i8 %75 to i1
  call void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32) %73, i32 noundef %74, i1 noundef zeroext %76)
  br label %77

77:                                               ; preds = %71
  %78 = load i32, ptr %7, align 4, !tbaa !11
  %79 = add nsw i32 %78, 1
  store i32 %79, ptr %7, align 4, !tbaa !11
  br label %66, !llvm.loop !25

80:                                               ; preds = %66
  br label %81

81:                                               ; preds = %80, %62
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{!16, !12, i64 24}
!16 = !{!"_ZTSN5sc_dt18sc_signed_subref_rE", !17, i64 0, !12, i64 8, !6, i64 16, !12, i64 24}
!17 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!18 = !{!16, !6, i64 16}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = !{!16, !12, i64 8}
!22 = !{i8 0, i8 2}
!23 = !{}
!24 = distinct !{!24, !20}
!25 = distinct !{!25, !20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32), i32 noundef, i1 noundef zeroext) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5sc_dt16sc_signed_subref10concat_setExi(ptr noundef nonnull align 8 dereferenceable(28) %0, i64 noundef %1, i32 noundef %2) unnamed_addr #2 align 2 {
  %4 = alloca i32, align 4
  %5 = icmp slt i64 %1, 0
  %6 = icmp slt i32 %2, 64
  br i1 %6, label %7, label %30

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 8
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #3
  %9 = getelementptr inbounds i8, ptr %0, i64 24
  %10 = load i32, ptr %9, align 8, !tbaa !5
  %reass.sub33 = sub i32 %10, %2
  %11 = add i32 %reass.sub33, 63
  store i32 %11, ptr %4, align 4, !tbaa !12
  %12 = call noundef i32 @_ZN5sc_dt6sc_minIiEEKT_RS2_S3_(ptr noundef nonnull align 4 dereferenceable(4) %8, ptr noundef nonnull align 4 dereferenceable(4) %4)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #3
  %13 = load i32, ptr %9, align 8, !tbaa !5
  %.not2126 = icmp sgt i32 %13, %12
  br i1 %.not2126, label %.preheader, label %.lr.ph29

.lr.ph29:                                         ; preds = %7
  %14 = zext nneg i32 %2 to i64
  %15 = ashr i64 %1, %14
  %16 = getelementptr inbounds i8, ptr %0, i64 16
  %17 = add i32 %12, 1
  br label %20

.preheader:                                       ; preds = %20, %7
  %.019.lcssa = phi i32 [ %13, %7 ], [ %17, %20 ]
  %18 = load i32, ptr %8, align 8, !tbaa !13
  %.not2230 = icmp sgt i32 %.019.lcssa, %18
  br i1 %.not2230, label %.loopexit, label %.lr.ph32

.lr.ph32:                                         ; preds = %.preheader
  %19 = getelementptr inbounds i8, ptr %0, i64 16
  br label %26

20:                                               ; preds = %.lr.ph29, %20
  %.028 = phi i64 [ %15, %.lr.ph29 ], [ %24, %20 ]
  %.01927 = phi i32 [ %13, %.lr.ph29 ], [ %25, %20 ]
  %21 = load ptr, ptr %16, align 8, !tbaa !14
  %22 = and i64 %.028, 1
  %23 = icmp ne i64 %22, 0
  call void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32) %21, i32 noundef %.01927, i1 noundef zeroext %23)
  %24 = ashr i64 %.028, 1
  %25 = add i32 %.01927, 1
  %exitcond.not = icmp eq i32 %.01927, %12
  br i1 %exitcond.not, label %.preheader, label %20, !llvm.loop !15

26:                                               ; preds = %.lr.ph32, %26
  %.131 = phi i32 [ %.019.lcssa, %.lr.ph32 ], [ %28, %26 ]
  %27 = load ptr, ptr %19, align 8, !tbaa !14
  call void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32) %27, i32 noundef %.131, i1 noundef zeroext %5)
  %28 = add nsw i32 %.131, 1
  %29 = load i32, ptr %8, align 8, !tbaa !13
  %.not22.not = icmp slt i32 %.131, %29
  br i1 %.not22.not, label %26, label %.loopexit, !llvm.loop !17

30:                                               ; preds = %3
  %31 = getelementptr inbounds i8, ptr %0, i64 24
  %32 = load i32, ptr %31, align 8, !tbaa !5
  %33 = getelementptr inbounds i8, ptr %0, i64 8
  %34 = load i32, ptr %33, align 8, !tbaa !13
  %.not24 = icmp sgt i32 %32, %34
  br i1 %.not24, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %30
  %35 = getelementptr inbounds i8, ptr %0, i64 16
  br label %36

36:                                               ; preds = %.lr.ph, %36
  %.225 = phi i32 [ %32, %.lr.ph ], [ %38, %36 ]
  %37 = load ptr, ptr %35, align 8, !tbaa !14
  tail call void @_ZN5sc_dt9sc_signed3setEib(ptr noundef nonnull align 8 dereferenceable(32) %37, i32 noundef %.225, i1 noundef zeroext %5)
  %38 = add nsw i32 %.225, 1
  %39 = load i32, ptr %33, align 8, !tbaa !13
  %.not.not = icmp slt i32 %.225, %39
  br i1 %.not.not, label %36, label %.loopexit, !llvm.loop !18

.loopexit:                                        ; preds = %36, %26, %30, %.preheader
  ret void
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 24}
!6 = !{!"_ZTSN5sc_dt18sc_signed_subref_rE", !7, i64 0, !8, i64 8, !11, i64 16, !8, i64 24}
!7 = !{!"_ZTSN5sc_dt13sc_value_baseE"}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"any pointer", !9, i64 0}
!12 = !{!8, !8, i64 0}
!13 = !{!6, !8, i64 8}
!14 = !{!6, !11, i64 16}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}
!18 = distinct !{!18, !16}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass