; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_wait.ll (ZN7sc_core4waitEPNS_13sc_simcontextE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>

@.str.1 = external hidden unnamed_addr constant [83 x i8], align 1
@_ZN7sc_core23SC_ID_WAIT_NOT_ALLOWED_E = external constant [0 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [50 x i8], align 1

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = call noundef ptr @_ZN7sc_core13sc_simcontext18get_curr_proc_infoEv(ptr noundef nonnull align 8 dereferenceable(344) %4)
  store ptr %5, ptr %3, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8, !tbaa !5
  %7 = getelementptr inbounds %"struct.sc_core::sc_curr_proc_info", ptr %6, i32 0, i32 1
  %8 = load i32, ptr %7, align 8, !tbaa !9
  switch i32 %8, label %13 [
    i32 2, label %9
    i32 3, label %9
  ]

9:                                                ; preds = %1, %1
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = getelementptr inbounds %"struct.sc_core::sc_curr_proc_info", ptr %10, i32 0, i32 0
  %12 = load ptr, ptr %11, align 8, !tbaa !12
  call void @_ZN7sc_core17sc_thread_process11wait_cyclesEi(ptr noundef nonnull align 8 dereferenceable(404) %12, i32 noundef 1)
  br label %14

13:                                               ; preds = %1
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef @_ZN7sc_core23SC_ID_WAIT_NOT_ALLOWED_E, ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 68)
  br label %14

14:                                               ; preds = %13, %9
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext18get_curr_proc_infoEv(ptr noundef nonnull align 8 dereferenceable(344)) #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core17sc_thread_process11wait_cyclesEi(ptr noundef nonnull align 8 dereferenceable(404), i32 noundef) #4 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 8}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!12 = !{!10, !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.1 = external hidden unnamed_addr constant [83 x i8], align 1
@_ZN7sc_core23SC_ID_WAIT_NOT_ALLOWED_E = external constant [0 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [50 x i8], align 1

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core4waitEPNS_13sc_simcontextE(ptr noundef nonnull %0) local_unnamed_addr #1 {
  %2 = tail call noundef ptr @_ZN7sc_core13sc_simcontext18get_curr_proc_infoEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  %3 = getelementptr inbounds i8, ptr %2, i64 8
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = and i32 %4, -2
  %switch = icmp eq i32 %5, 2
  br i1 %switch, label %6, label %8

6:                                                ; preds = %1
  %7 = load ptr, ptr %2, align 8, !tbaa !11
  tail call void @_ZN7sc_core17sc_thread_process11wait_cyclesEi(ptr noundef nonnull align 8 dereferenceable(404) %7, i32 noundef 1)
  br label %9

8:                                                ; preds = %1
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 2, ptr noundef nonnull @_ZN7sc_core23SC_ID_WAIT_NOT_ALLOWED_E, ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 68)
  br label %9

9:                                                ; preds = %8, %6
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext18get_curr_proc_infoEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN7sc_core17sc_thread_process11wait_cyclesEi(ptr noundef nonnull align 8 dereferenceable(404), i32 noundef) local_unnamed_addr #3 align 2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !10, i64 8}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!11 = !{!6, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass