; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/synth/add_chain_FUNC (add_chain)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_Z11f_add_chainPKcRN7sc_core8sc_clockERKNS1_9sc_signalIbLNS1_16sc_writer_policyE3EEERKNS4_IN5sc_dt5sc_bvILi8EEELS5_3EEERNS4_INSA_ILi4EEELS5_3EEERS6_(ptr noundef %0, ptr noundef nonnull align 8 dereferenceable(592) %1, ptr noundef nonnull align 8 dereferenceable(200) %2, ptr noundef nonnull align 8 dereferenceable(208) %3, ptr noundef nonnull align 8 dereferenceable(208) %4, ptr noundef nonnull align 8 dereferenceable(200) %5) #0 personality ptr @__gxx_personality_v0 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca %"class.sc_core::sc_module_name", align 8
  %14 = alloca ptr, align 8
  %15 = alloca i32, align 4
  %16 = alloca i1, align 1
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store ptr %2, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store ptr %4, ptr %11, align 8, !tbaa !5
  store ptr %5, ptr %12, align 8, !tbaa !5
  %17 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 448) #5
  store i1 true, ptr %16, align 1
  %18 = load ptr, ptr %7, align 8, !tbaa !5
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %13, ptr noundef %18)
          to label %19 unwind label %26

19:                                               ; preds = %6
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  %21 = load ptr, ptr %9, align 8, !tbaa !5
  %22 = load ptr, ptr %10, align 8, !tbaa !5
  %23 = load ptr, ptr %11, align 8, !tbaa !5
  %24 = load ptr, ptr %12, align 8, !tbaa !5
  invoke void @_ZN9add_chainC2EN7sc_core14sc_module_nameERNS0_8sc_clockERKNS0_9sc_signalIbLNS0_16sc_writer_policyE3EEERKNS4_IN5sc_dt5sc_bvILi8EEELS5_3EEERNS4_INSA_ILi4EEELS5_3EEERS6_(ptr noundef nonnull align 8 dereferenceable(448) %17, ptr noundef %13, ptr noundef nonnull align 8 dereferenceable(592) %20, ptr noundef nonnull align 8 dereferenceable(200) %21, ptr noundef nonnull align 8 dereferenceable(208) %22, ptr noundef nonnull align 8 dereferenceable(208) %23, ptr noundef nonnull align 8 dereferenceable(200) %24)
          to label %25 unwind label %30

25:                                               ; preds = %19
  store i1 false, ptr %16, align 1
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %13) #6
  ret void

26:                                               ; preds = %6
  %27 = landingpad { ptr, i32 }
          cleanup
  %28 = extractvalue { ptr, i32 } %27, 0
  store ptr %28, ptr %14, align 8
  %29 = extractvalue { ptr, i32 } %27, 1
  store i32 %29, ptr %15, align 4
  br label %34

30:                                               ; preds = %19
  %31 = landingpad { ptr, i32 }
          cleanup
  %32 = extractvalue { ptr, i32 } %31, 0
  store ptr %32, ptr %14, align 8
  %33 = extractvalue { ptr, i32 } %31, 1
  store i32 %33, ptr %15, align 4
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %13) #6
  br label %34

34:                                               ; preds = %30, %26
  %35 = load i1, ptr %16, align 1
  br i1 %35, label %36, label %37

36:                                               ; preds = %34
  call void @_ZdlPvm(ptr noundef %17, i64 noundef 448) #7
  br label %37

37:                                               ; preds = %36, %34
  br label %38

38:                                               ; preds = %37
  %39 = load ptr, ptr %14, align 8
  %40 = load i32, ptr %15, align 4
  %41 = insertvalue { ptr, i32 } poison, ptr %39, 0
  %42 = insertvalue { ptr, i32 } %41, i32 %40, 1
  resume { ptr, i32 } %42
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #1

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN9add_chainC2EN7sc_core14sc_module_nameERNS0_8sc_clockERKNS0_9sc_signalIbLNS0_16sc_writer_policyE3EEERKNS4_IN5sc_dt5sc_bvILi8EEELS5_3EEERNS4_INSA_ILi4EEELS5_3EEERS6_(ptr noundef nonnull align 8 dereferenceable(448), ptr noundef, ptr noundef nonnull align 8 dereferenceable(592), ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(208), ptr noundef nonnull align 8 dereferenceable(208), ptr noundef nonnull align 8 dereferenceable(200)) unnamed_addr #0 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { builtin allocsize(0) }
attributes #6 = { nounwind }
attributes #7 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_module_name" = type <{ ptr, ptr, ptr, ptr, i8, [7 x i8] }>

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_Z11f_add_chainPKcRN7sc_core8sc_clockERKNS1_9sc_signalIbLNS1_16sc_writer_policyE3EEERKNS4_IN5sc_dt5sc_bvILi8EEELS5_3EEERNS4_INSA_ILi4EEELS5_3EEERS6_(ptr noundef %0, ptr noundef nonnull align 8 dereferenceable(592) %1, ptr noundef nonnull align 8 dereferenceable(200) %2, ptr noundef nonnull align 8 dereferenceable(208) %3, ptr noundef nonnull align 8 dereferenceable(208) %4, ptr noundef nonnull align 8 dereferenceable(200) %5) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
  %7 = alloca %"class.sc_core::sc_module_name", align 8
  %8 = tail call noalias noundef nonnull dereferenceable(448) ptr @_Znwm(i64 noundef 448) #5
  invoke void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33) %7, ptr noundef %0)
          to label %9 unwind label %11

9:                                                ; preds = %6
  invoke void @_ZN9add_chainC2EN7sc_core14sc_module_nameERNS0_8sc_clockERKNS0_9sc_signalIbLNS0_16sc_writer_policyE3EEERKNS4_IN5sc_dt5sc_bvILi8EEELS5_3EEERNS4_INSA_ILi4EEELS5_3EEERS6_(ptr noundef nonnull align 8 dereferenceable(448) %8, ptr noundef nonnull %7, ptr noundef nonnull align 8 dereferenceable(592) %1, ptr noundef nonnull align 8 dereferenceable(200) %2, ptr noundef nonnull align 8 dereferenceable(208) %3, ptr noundef nonnull align 8 dereferenceable(208) %4, ptr noundef nonnull align 8 dereferenceable(200) %5)
          to label %10 unwind label %13

10:                                               ; preds = %9
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %7) #6
  ret void

11:                                               ; preds = %6
  %12 = landingpad { ptr, i32 }
          cleanup
  br label %15

13:                                               ; preds = %9
  %14 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33) %7) #6
  br label %15

15:                                               ; preds = %11, %13
  %.pn = phi { ptr, i32 } [ %14, %13 ], [ %12, %11 ]
  call void @_ZdlPvm(ptr noundef nonnull %8, i64 noundef 448) #7
  resume { ptr, i32 } %.pn
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #1

declare void @_ZN7sc_core14sc_module_nameC1EPKc(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN9add_chainC2EN7sc_core14sc_module_nameERNS0_8sc_clockERKNS0_9sc_signalIbLNS0_16sc_writer_policyE3EEERKNS4_IN5sc_dt5sc_bvILi8EEELS5_3EEERNS4_INSA_ILi4EEELS5_3EEERS6_(ptr noundef nonnull align 8 dereferenceable(448), ptr noundef, ptr noundef nonnull align 8 dereferenceable(592), ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(208), ptr noundef nonnull align 8 dereferenceable(208), ptr noundef nonnull align 8 dereferenceable(200)) unnamed_addr #0 align 2

; Function Attrs: nounwind
declare void @_ZN7sc_core14sc_module_nameD1Ev(ptr noundef nonnull align 8 dereferenceable(33)) unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { builtin allocsize(0) }
attributes #6 = { nounwind }
attributes #7 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass