; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_simcontext.ll (ZN7sc_core13sc_simcontext8next_corEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_thread_process" = type <{ %"class.sc_core::sc_process_b.base", [3 x i8], ptr, %"class.std::vector.18", i64, i32, [4 x i8] }>
%"class.sc_core::sc_process_b.base" = type <{ %"class.sc_core::sc_object", ptr, i32, i32, i32, i32, i8, i8, [6 x i8], ptr, i32, [4 x i8], ptr, ptr, i8, i8, i8, i8, [4 x i8], ptr, ptr, i32, i32, %"class.std::vector.8", ptr, ptr, ptr, ptr, { i64, i64 }, i32, [4 x i8], %"class.std::vector.13", i8, [7 x i8], ptr, ptr, i32, i8, [3 x i8], ptr, i32, i8 }>
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_reset *, std::allocator<sc_core::sc_reset *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<const sc_core::sc_event *, std::allocator<const sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_process_monitor *, std::allocator<sc_core::sc_process_monitor *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN7sc_core13sc_simcontext8next_corEv(ptr noundef nonnull align 8 dereferenceable(344) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  %7 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %6, i32 0, i32 32
  %8 = load ptr, ptr %7, align 8, !tbaa !9
  %9 = icmp ne ptr %8, null
  br i1 %9, label %10, label %13

10:                                               ; preds = %1
  %11 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %6, i32 0, i32 38
  %12 = load ptr, ptr %11, align 8, !tbaa !35
  store ptr %12, ptr %2, align 8
  br label %37

13:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #3
  %14 = call noundef ptr @_ZN7sc_core13sc_simcontext19pop_runnable_threadEv(ptr noundef nonnull align 8 dereferenceable(344) %6)
  store ptr %14, ptr %4, align 8, !tbaa !5
  br label %15

15:                                               ; preds = %24, %13
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = icmp ne ptr %16, null
  br i1 %17, label %18, label %26

18:                                               ; preds = %15
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %"class.sc_core::sc_thread_process", ptr %19, i32 0, i32 2
  %21 = load ptr, ptr %20, align 8, !tbaa !36
  %22 = icmp ne ptr %21, null
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  br label %26

24:                                               ; preds = %18
  %25 = call noundef ptr @_ZN7sc_core13sc_simcontext19pop_runnable_threadEv(ptr noundef nonnull align 8 dereferenceable(344) %6)
  store ptr %25, ptr %4, align 8, !tbaa !5
  br label %15, !llvm.loop !57

26:                                               ; preds = %23, %15
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = icmp ne ptr %27, null
  br i1 %28, label %29, label %33

29:                                               ; preds = %26
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %"class.sc_core::sc_thread_process", ptr %30, i32 0, i32 2
  %32 = load ptr, ptr %31, align 8, !tbaa !36
  store ptr %32, ptr %2, align 8
  store i32 1, ptr %5, align 4
  br label %36

33:                                               ; preds = %26
  %34 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %6, i32 0, i32 38
  %35 = load ptr, ptr %34, align 8, !tbaa !35
  store ptr %35, ptr %2, align 8
  store i32 1, ptr %5, align 4
  br label %36

36:                                               ; preds = %33, %29
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #3
  br label %37

37:                                               ; preds = %36, %10
  %38 = load ptr, ptr %2, align 8
  ret ptr %38
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext19pop_runnable_threadEv(ptr noundef nonnull align 8 dereferenceable(344)) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 304}
!10 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !11, i64 64, !6, i64 80, !13, i64 88, !14, i64 92, !15, i64 96, !19, i64 120, !23, i64 144, !19, i64 168, !6, i64 192, !27, i64 200, !13, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !31, i64 256, !31, i64 264, !6, i64 272, !32, i64 280, !32, i64 288, !13, i64 296, !13, i64 297, !13, i64 298, !13, i64 299, !33, i64 300, !6, i64 304, !13, i64 312, !13, i64 313, !34, i64 316, !13, i64 320, !6, i64 328, !6, i64 336}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !12, i64 8}
!12 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core7sc_timeE", !32, i64 0}
!32 = !{!"long long", !7, i64 0}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!35 = !{!10, !6, i64 336}
!36 = !{!37, !6, i64 360}
!37 = !{!"_ZTSN7sc_core17sc_thread_processE", !38, i64 0, !6, i64 360, !53, i64 368, !42, i64 392, !14, i64 400}
!38 = !{!"_ZTSN7sc_core12sc_process_bE", !39, i64 0, !6, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !14, i64 132, !13, i64 136, !13, i64 137, !6, i64 144, !14, i64 152, !6, i64 160, !6, i64 168, !13, i64 176, !13, i64 177, !13, i64 178, !13, i64 179, !6, i64 184, !6, i64 192, !12, i64 200, !14, i64 204, !43, i64 208, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !7, i64 264, !14, i64 280, !47, i64 288, !13, i64 312, !6, i64 320, !6, i64 328, !51, i64 336, !13, i64 340, !6, i64 344, !52, i64 352, !13, i64 356}
!39 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !19, i64 16, !23, i64 40, !40, i64 64, !6, i64 96, !6, i64 104}
!40 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !41, i64 0, !42, i64 8, !7, i64 16}
!41 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!42 = !{!"long", !7, i64 0}
!43 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !44, i64 0}
!44 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!47 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !48, i64 0}
!48 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !49, i64 0}
!49 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !50, i64 0}
!50 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!51 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !7, i64 0}
!52 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !7, i64 0}
!53 = !{!"_ZTSSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE", !54, i64 0}
!54 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE", !55, i64 0}
!55 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE12_Vector_implE", !56, i64 0}
!56 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!57 = distinct !{!57, !58}
!58 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN7sc_core13sc_simcontext8next_corEv(ptr noundef nonnull align 8 dereferenceable(344) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 304
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %6, label %4

4:                                                ; preds = %1
  %5 = getelementptr inbounds i8, ptr %0, i64 336
  br label %.loopexit

6:                                                ; preds = %1
  %7 = tail call noundef ptr @_ZN7sc_core13sc_simcontext19pop_runnable_threadEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  %.not79 = icmp eq ptr %7, null
  br i1 %.not79, label %.critedge, label %.lr.ph

.lr.ph:                                           ; preds = %6, %10
  %.010 = phi ptr [ %11, %10 ], [ %7, %6 ]
  %8 = getelementptr inbounds i8, ptr %.010, i64 360
  %9 = load ptr, ptr %8, align 8, !tbaa !34
  %.not8 = icmp eq ptr %9, null
  br i1 %.not8, label %10, label %.loopexit.loopexit

10:                                               ; preds = %.lr.ph
  %11 = tail call noundef ptr @_ZN7sc_core13sc_simcontext19pop_runnable_threadEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
  %.not7 = icmp eq ptr %11, null
  br i1 %.not7, label %.critedge, label %.lr.ph, !llvm.loop !55

.critedge:                                        ; preds = %10, %6
  %12 = getelementptr inbounds i8, ptr %0, i64 336
  br label %.loopexit

.loopexit.loopexit:                               ; preds = %.lr.ph
  %13 = getelementptr inbounds i8, ptr %.010, i64 360
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.loopexit, %.critedge, %4
  %.1.in = phi ptr [ %5, %4 ], [ %12, %.critedge ], [ %13, %.loopexit.loopexit ]
  %.1 = load ptr, ptr %.1.in, align 8, !tbaa !57
  ret ptr %.1
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core13sc_simcontext19pop_runnable_threadEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 304}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{!35, !7, i64 360}
!35 = !{!"_ZTSN7sc_core17sc_thread_processE", !36, i64 0, !7, i64 360, !51, i64 368, !40, i64 392, !13, i64 400}
!36 = !{!"_ZTSN7sc_core12sc_process_bE", !37, i64 0, !7, i64 112, !13, i64 120, !13, i64 124, !13, i64 128, !13, i64 132, !12, i64 136, !12, i64 137, !7, i64 144, !13, i64 152, !7, i64 160, !7, i64 168, !12, i64 176, !12, i64 177, !12, i64 178, !12, i64 179, !7, i64 184, !7, i64 192, !11, i64 200, !13, i64 204, !41, i64 208, !7, i64 232, !7, i64 240, !7, i64 248, !7, i64 256, !8, i64 264, !13, i64 280, !45, i64 288, !12, i64 312, !7, i64 320, !7, i64 328, !49, i64 336, !12, i64 340, !7, i64 344, !50, i64 352, !12, i64 356}
!37 = !{!"_ZTSN7sc_core9sc_objectE", !7, i64 8, !18, i64 16, !22, i64 40, !38, i64 64, !7, i64 96, !7, i64 104}
!38 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !39, i64 0, !40, i64 8, !8, i64 16}
!39 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !7, i64 0}
!40 = !{!"long", !8, i64 0}
!41 = !{!"_ZTSSt6vectorIPN7sc_core8sc_resetESaIS2_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_resetESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!45 = !{!"_ZTSSt6vectorIPKN7sc_core8sc_eventESaIS3_EE", !46, i64 0}
!46 = !{!"_ZTSSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE", !47, i64 0}
!47 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE12_Vector_implE", !48, i64 0}
!48 = !{!"_ZTSNSt12_Vector_baseIPKN7sc_core8sc_eventESaIS3_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!49 = !{!"_ZTSN7sc_core12sc_process_b18process_throw_typeE", !8, i64 0}
!50 = !{!"_ZTSN7sc_core12sc_process_b9trigger_tE", !8, i64 0}
!51 = !{!"_ZTSSt6vectorIPN7sc_core18sc_process_monitorESaIS2_EE", !52, i64 0}
!52 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE", !53, i64 0}
!53 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE12_Vector_implE", !54, i64 0}
!54 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_process_monitorESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!55 = distinct !{!55, !56}
!56 = !{!"llvm.loop.mustprogress"}
!57 = !{!7, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass