; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/stars/star110089 (star110089)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lp_write_buf = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in.21", %"class.sc_core::sc_out", %"class.sc_core::sc_out.36", %"class.sc_core::sc_out.45", %"class.sc_core::sc_inout.54", %"class.sc_core::sc_in.62", %"class.sc_core::sc_out.36", %"class.sc_core::sc_out.70", %"class.sc_core::sc_in.62", %"class.sc_core::sc_out.45", %"class.sc_core::sc_out.36", %"class.sc_core::sc_out.36", %"class.sc_core::sc_out.36" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<unsigned int> *, std::allocator<sc_core::sc_signal_in_if<unsigned int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.21" = type { %"class.sc_core::sc_port.22", ptr, ptr }
%"class.sc_core::sc_port.22" = type { %"class.sc_core::sc_port_b.23" }
%"class.sc_core::sc_port_b.23" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.24" }
%"class.std::vector.24" = type { %"struct.std::_Vector_base.25" }
%"struct.std::_Vector_base.25" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.29", ptr, ptr, ptr }
%"class.sc_core::sc_port.29" = type { %"class.sc_core::sc_port_b.30" }
%"class.sc_core::sc_port_b.30" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.31" }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_inout.54" = type { %"class.sc_core::sc_port.55", ptr, ptr, ptr }
%"class.sc_core::sc_port.55" = type { %"class.sc_core::sc_port_b.56" }
%"class.sc_core::sc_port_b.56" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.57" }
%"class.std::vector.57" = type { %"struct.std::_Vector_base.58" }
%"struct.std::_Vector_base.58" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<unsigned int> *, std::allocator<sc_core::sc_signal_inout_if<unsigned int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.70" = type { %"class.sc_core::sc_inout.54" }
%"class.sc_core::sc_in.62" = type { %"class.sc_core::sc_port.63", ptr, ptr }
%"class.sc_core::sc_port.63" = type { %"class.sc_core::sc_port_b.64" }
%"class.sc_core::sc_port_b.64" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.65" }
%"class.std::vector.65" = type { %"struct.std::_Vector_base.66" }
%"struct.std::_Vector_base.66" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<char> *, std::allocator<sc_core::sc_signal_in_if<char> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<char> *, std::allocator<sc_core::sc_signal_in_if<char> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<char> *, std::allocator<sc_core::sc_signal_in_if<char> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<char> *, std::allocator<sc_core::sc_signal_in_if<char> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.45" = type { %"class.sc_core::sc_inout.46" }
%"class.sc_core::sc_inout.46" = type { %"class.sc_core::sc_port.47", ptr, ptr, ptr }
%"class.sc_core::sc_port.47" = type { %"class.sc_core::sc_port_b.48" }
%"class.sc_core::sc_port_b.48" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.49" }
%"class.std::vector.49" = type { %"struct.std::_Vector_base.50" }
%"struct.std::_Vector_base.50" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<char> *, std::allocator<sc_core::sc_signal_inout_if<char> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<char> *, std::allocator<sc_core::sc_signal_inout_if<char> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<char> *, std::allocator<sc_core::sc_signal_inout_if<char> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<char> *, std::allocator<sc_core::sc_signal_inout_if<char> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.36" = type { %"class.sc_core::sc_inout.37" }
%"class.sc_core::sc_inout.37" = type { %"class.sc_core::sc_port.38", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.38" = type { %"class.sc_core::sc_port_b.39" }
%"class.sc_core::sc_port_b.39" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.40" }
%"class.std::vector.40" = type { %"struct.std::_Vector_base.41" }
%"struct.std::_Vector_base.41" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12lp_write_buf18check_read_addressEv(ptr noundef nonnull align 8 dereferenceable(3280) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  br label %5

5:                                                ; preds = %25, %1
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #2
  %6 = getelementptr inbounds %struct.lp_write_buf, ptr %4, i32 0, i32 9
  %7 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core8sc_inoutIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(176) %6)
  %8 = load i32, ptr %7, align 4, !tbaa !9
  %9 = getelementptr inbounds %struct.lp_write_buf, ptr %4, i32 0, i32 4
  %10 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %9)
  %11 = load i32, ptr %10, align 4, !tbaa !9
  %12 = icmp ult i32 %8, %11
  br i1 %12, label %25, label %13

13:                                               ; preds = %5
  %14 = getelementptr inbounds %struct.lp_write_buf, ptr %4, i32 0, i32 9
  %15 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core8sc_inoutIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(176) %14)
  %16 = load i32, ptr %15, align 4, !tbaa !9
  %17 = getelementptr inbounds %struct.lp_write_buf, ptr %4, i32 0, i32 4
  %18 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %17)
  %19 = load i32, ptr %18, align 4, !tbaa !9
  %20 = getelementptr inbounds %struct.lp_write_buf, ptr %4, i32 0, i32 5
  %21 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %20)
  %22 = load i32, ptr %21, align 4, !tbaa !9
  %23 = add i32 %19, %22
  %24 = icmp uge i32 %16, %23
  br label %25

25:                                               ; preds = %13, %5
  %26 = phi i1 [ true, %5 ], [ %24, %13 ]
  %27 = zext i1 %26 to i8
  store i8 %27, ptr %3, align 1, !tbaa !11
  %28 = getelementptr inbounds %struct.lp_write_buf, ptr %4, i32 0, i32 17
  %29 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %28, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %4)
  br label %5, !llvm.loop !13
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core8sc_inoutIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(176)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN12lp_write_buf18check_read_addressEv(ptr noundef nonnull align 8 dereferenceable(3280) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca i8, align 1
  %3 = getelementptr inbounds i8, ptr %0, i64 1648
  %4 = getelementptr inbounds i8, ptr %0, i64 768
  %5 = getelementptr inbounds i8, ptr %0, i64 936
  %6 = getelementptr inbounds i8, ptr %0, i64 3088
  br label %7

7:                                                ; preds = %22, %1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  %8 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core8sc_inoutIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(176) %3)
  %9 = load i32, ptr %8, align 4, !tbaa !5
  %10 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %4)
  %11 = load i32, ptr %10, align 4, !tbaa !5
  %12 = icmp ult i32 %9, %11
  br i1 %12, label %22, label %13

13:                                               ; preds = %7
  %14 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core8sc_inoutIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(176) %3)
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168) %4)
  %17 = load i32, ptr %16, align 4, !tbaa !5
  %18 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168) %5)
  %19 = load i32, ptr %18, align 4, !tbaa !5
  %20 = add i32 %19, %17
  %21 = icmp uge i32 %15, %20
  br label %22

22:                                               ; preds = %13, %7
  %23 = phi i1 [ true, %7 ], [ %21, %13 ]
  %24 = zext i1 %23 to i8
  store i8 %24, ptr %2, align 1, !tbaa !9
  %25 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 1 dereferenceable(1) %2)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  br label %7, !llvm.loop !11
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core8sc_inoutIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(176)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIjEcvRKjEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiEcvRKiEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass