; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo (cycle_model)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.cycle_model = type <{ %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [65536 x i32], [65536 x i32], [2048 x i32], i32, [8 x i32], [4 x i8], ptr, i32, i32, i32, [4 x i8] }>
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@ALL_CYCLES = external dso_local global i8, align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN11cycle_model15request_addressEi(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11cycle_model14exec_bus_cycleE14bus_cycle_typeiiPi(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef, i32 noundef, i32 noundef, ptr noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN11cycle_model10write_dataEii(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef %1, i32 noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !9
  %10 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  %11 = load i32, ptr %5, align 4, !tbaa !9
  %12 = call noundef zeroext i1 @_ZN11cycle_model15request_addressEi(ptr noundef nonnull align 8 dereferenceable(533052) %10, i32 noundef %11)
  %13 = zext i1 %12 to i8
  store i8 %13, ptr %8, align 1, !tbaa !11
  %14 = load i8, ptr %8, align 1, !tbaa !11, !range !13, !noundef !14
  %15 = trunc i8 %14 to i1
  br i1 %15, label %16, label %44

16:                                               ; preds = %3
  %17 = getelementptr inbounds %struct.cycle_model, ptr %10, i32 0, i32 21
  %18 = load i32, ptr %17, align 8, !tbaa !15
  %19 = icmp sgt i32 %18, 0
  br i1 %19, label %23, label %20

20:                                               ; preds = %16
  %21 = load i8, ptr @ALL_CYCLES, align 1, !tbaa !11, !range !13, !noundef !14
  %22 = trunc i8 %21 to i1
  br i1 %22, label %23, label %38

23:                                               ; preds = %20, %16
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %24

24:                                               ; preds = %34, %23
  %25 = load i32, ptr %9, align 4, !tbaa !9
  %26 = getelementptr inbounds %struct.cycle_model, ptr %10, i32 0, i32 23
  %27 = load i32, ptr %26, align 8, !tbaa !45
  %28 = add nsw i32 %27, 1
  %29 = icmp slt i32 %25, %28
  br i1 %29, label %31, label %30

30:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %37

31:                                               ; preds = %24
  %32 = load i32, ptr %5, align 4, !tbaa !9
  %33 = load i32, ptr %6, align 4, !tbaa !9
  call void @_ZN11cycle_model14exec_bus_cycleE14bus_cycle_typeiiPi(ptr noundef nonnull align 8 dereferenceable(533052) %10, i32 noundef 0, i32 noundef %32, i32 noundef %33, ptr noundef %7)
  br label %34

34:                                               ; preds = %31
  %35 = load i32, ptr %9, align 4, !tbaa !9
  %36 = add nsw i32 %35, 1
  store i32 %36, ptr %9, align 4, !tbaa !9
  br label %24, !llvm.loop !46

37:                                               ; preds = %30
  br label %38

38:                                               ; preds = %37, %20
  %39 = load i32, ptr %6, align 4, !tbaa !9
  %40 = getelementptr inbounds %struct.cycle_model, ptr %10, i32 0, i32 15
  %41 = load i32, ptr %5, align 4, !tbaa !9
  %42 = sext i32 %41 to i64
  %43 = getelementptr inbounds [65536 x i32], ptr %40, i64 0, i64 %42
  store i32 %39, ptr %43, align 4, !tbaa !9
  br label %47

44:                                               ; preds = %3
  %45 = load i32, ptr %5, align 4, !tbaa !9
  %46 = load i32, ptr %6, align 4, !tbaa !9
  call void @_ZN11cycle_model14exec_bus_cycleE14bus_cycle_typeiiPi(ptr noundef nonnull align 8 dereferenceable(533052) %10, i32 noundef 2, i32 noundef %45, i32 noundef %46, ptr noundef %7)
  br label %47

47:                                               ; preds = %44, %38
  %48 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret i32 %48
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!16, !10, i64 533040}
!16 = !{!"_ZTS11cycle_model", !17, i64 0, !37, i64 232, !6, i64 416, !6, i64 424, !6, i64 432, !6, i64 440, !6, i64 448, !6, i64 456, !6, i64 464, !6, i64 472, !6, i64 480, !6, i64 488, !6, i64 496, !6, i64 504, !7, i64 512, !7, i64 262656, !7, i64 524800, !10, i64 532992, !7, i64 532996, !6, i64 533032, !10, i64 533040, !10, i64 533044, !10, i64 533048}
!17 = !{!"_ZTSN7sc_core9sc_moduleE", !18, i64 0, !30, i64 112, !31, i64 120, !33, i64 144, !35, i64 168, !12, i64 192, !6, i64 200, !10, i64 208, !6, i64 216, !6, i64 224}
!18 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !19, i64 16, !23, i64 40, !27, i64 64, !6, i64 96, !6, i64 104}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !28, i64 0, !29, i64 8, !7, i64 16}
!28 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!29 = !{!"long", !7, i64 0}
!30 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!31 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !32, i64 8, !6, i64 16}
!32 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!33 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !34, i64 8, !6, i64 16}
!34 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!35 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !36, i64 8, !6, i64 16}
!36 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!37 = !{!"_ZTSN7sc_core5sc_inIbEE", !38, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!38 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !39, i64 0}
!39 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !40, i64 0, !6, i64 120, !41, i64 128}
!40 = !{!"_ZTSN7sc_core12sc_port_baseE", !18, i64 0, !6, i64 112}
!41 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!45 = !{!16, !10, i64 533048}
!46 = distinct !{!46, !47}
!47 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@ALL_CYCLES = external dso_local local_unnamed_addr global i8, align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN11cycle_model15request_addressEi(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN11cycle_model14exec_bus_cycleE14bus_cycle_typeiiPi(ptr noundef nonnull align 8 dereferenceable(533052), i32 noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN11cycle_model10write_dataEii(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #2 align 2 {
  %4 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #3
  store i32 0, ptr %4, align 4, !tbaa !5
  %5 = tail call noundef zeroext i1 @_ZN11cycle_model15request_addressEi(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef %1)
  br i1 %5, label %6, label %21

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 533040
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp sgt i32 %8, 0
  br i1 %9, label %13, label %10

10:                                               ; preds = %6
  %11 = load i8, ptr @ALL_CYCLES, align 1, !tbaa !41, !range !42, !noundef !43
  %12 = trunc nuw i8 %11 to i1
  br i1 %12, label %13, label %.loopexit

13:                                               ; preds = %10, %6
  %14 = getelementptr inbounds i8, ptr %0, i64 533048
  %15 = load i32, ptr %14, align 8, !tbaa !44
  %.not10 = icmp slt i32 %15, 0
  br i1 %.not10, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %13, %.lr.ph
  %.011 = phi i32 [ %16, %.lr.ph ], [ 0, %13 ]
  call void @_ZN11cycle_model14exec_bus_cycleE14bus_cycle_typeiiPi(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef 0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull %4)
  %16 = add nuw nsw i32 %.011, 1
  %17 = load i32, ptr %14, align 8, !tbaa !44
  %.not.not = icmp slt i32 %.011, %17
  br i1 %.not.not, label %.lr.ph, label %.loopexit, !llvm.loop !45

.loopexit:                                        ; preds = %.lr.ph, %13, %10
  %18 = getelementptr inbounds i8, ptr %0, i64 262656
  %19 = sext i32 %1 to i64
  %20 = getelementptr inbounds [65536 x i32], ptr %18, i64 0, i64 %19
  store i32 %2, ptr %20, align 4, !tbaa !5
  br label %22

21:                                               ; preds = %3
  call void @_ZN11cycle_model14exec_bus_cycleE14bus_cycle_typeiiPi(ptr noundef nonnull align 8 dereferenceable(533052) %0, i32 noundef 2, i32 noundef %1, i32 noundef %2, ptr noundef nonnull %4)
  br label %22

22:                                               ; preds = %21, %.loopexit
  %23 = load i32, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #3
  ret i32 %23
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 533040}
!10 = !{!"_ZTS11cycle_model", !11, i64 0, !33, i64 232, !13, i64 416, !13, i64 424, !13, i64 432, !13, i64 440, !13, i64 448, !13, i64 456, !13, i64 464, !13, i64 472, !13, i64 480, !13, i64 488, !13, i64 496, !13, i64 504, !7, i64 512, !7, i64 262656, !7, i64 524800, !6, i64 532992, !7, i64 532996, !13, i64 533032, !6, i64 533040, !6, i64 533044, !6, i64 533048}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !25, i64 112, !26, i64 120, !28, i64 144, !30, i64 168, !32, i64 192, !13, i64 200, !6, i64 208, !13, i64 216, !13, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !13, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !13, i64 96, !13, i64 104}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveE", !13, i64 0, !27, i64 8, !13, i64 16}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !13, i64 0, !29, i64 8, !13, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !13, i64 0, !31, i64 8, !13, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!32 = !{!"bool", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !13, i64 152, !13, i64 160, !13, i64 168, !13, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !13, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !13, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!41 = !{!32, !32, i64 0}
!42 = !{i8 0, i8 2}
!43 = !{}
!44 = !{!10, !6, i64 533048}
!45 = distinct !{!45, !46}
!46 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass