; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/if_transforms/loop_unrolling/test1 (test)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.test = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4test5entryEv(ptr noundef nonnull align 8 dereferenceable(528) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca [10 x i32], align 16
  %6 = alloca [10 x i32], align 16
  store ptr %0, ptr %2, align 8, !tbaa !5
  %7 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 40, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 40, ptr %6) #2
  br label %8

8:                                                ; preds = %9, %1
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  br label %9

9:                                                ; preds = %8
  %10 = getelementptr inbounds %struct.test, ptr %7, i32 0, i32 8
  %11 = load ptr, ptr %10, align 8, !tbaa !9
  %12 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %11)
  %13 = load i8, ptr %12, align 1, !tbaa !41, !range !42, !noundef !43
  %14 = trunc i8 %13 to i1
  %15 = zext i1 %14 to i32
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %8, label %17, !llvm.loop !44

17:                                               ; preds = %9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  store i32 0, ptr %3, align 4, !tbaa !46
  br label %18

18:                                               ; preds = %21, %17
  %19 = load i32, ptr %3, align 4, !tbaa !46
  %20 = icmp slt i32 %19, 4
  br i1 %20, label %21, label %27

21:                                               ; preds = %18
  %22 = load i32, ptr %3, align 4, !tbaa !46
  %23 = sext i32 %22 to i64
  %24 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %23
  store i32 0, ptr %24, align 4, !tbaa !46
  %25 = load i32, ptr %3, align 4, !tbaa !46
  %26 = add nsw i32 %25, 1
  store i32 %26, ptr %3, align 4, !tbaa !46
  br label %18, !llvm.loop !47

27:                                               ; preds = %18
  store i32 0, ptr %3, align 4, !tbaa !46
  br label %28

28:                                               ; preds = %31, %27
  %29 = load i32, ptr %3, align 4, !tbaa !46
  %30 = icmp sle i32 %29, 4
  br i1 %30, label %31, label %37

31:                                               ; preds = %28
  %32 = load i32, ptr %3, align 4, !tbaa !46
  %33 = sext i32 %32 to i64
  %34 = getelementptr inbounds [10 x i32], ptr %6, i64 0, i64 %33
  store i32 10, ptr %34, align 4, !tbaa !46
  %35 = load i32, ptr %3, align 4, !tbaa !46
  %36 = add nsw i32 %35, 1
  store i32 %36, ptr %3, align 4, !tbaa !46
  br label %28, !llvm.loop !48

37:                                               ; preds = %28
  store i32 9, ptr %3, align 4, !tbaa !46
  br label %38

38:                                               ; preds = %41, %37
  %39 = load i32, ptr %3, align 4, !tbaa !46
  %40 = icmp sgt i32 %39, 4
  br i1 %40, label %41, label %47

41:                                               ; preds = %38
  %42 = load i32, ptr %3, align 4, !tbaa !46
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %43
  store i32 20, ptr %44, align 4, !tbaa !46
  %45 = load i32, ptr %3, align 4, !tbaa !46
  %46 = sub nsw i32 %45, 1
  store i32 %46, ptr %3, align 4, !tbaa !46
  br label %38, !llvm.loop !49

47:                                               ; preds = %38
  store i32 9, ptr %3, align 4, !tbaa !46
  br label %48

48:                                               ; preds = %51, %47
  %49 = load i32, ptr %3, align 4, !tbaa !46
  %50 = icmp sge i32 %49, 4
  br i1 %50, label %51, label %57

51:                                               ; preds = %48
  %52 = load i32, ptr %3, align 4, !tbaa !46
  %53 = sext i32 %52 to i64
  %54 = getelementptr inbounds [10 x i32], ptr %6, i64 0, i64 %53
  store i32 30, ptr %54, align 4, !tbaa !46
  %55 = load i32, ptr %3, align 4, !tbaa !46
  %56 = sub nsw i32 %55, 1
  store i32 %56, ptr %3, align 4, !tbaa !46
  br label %48, !llvm.loop !50

57:                                               ; preds = %48
  store i32 -4, ptr %3, align 4, !tbaa !46
  br label %58

58:                                               ; preds = %61, %57
  %59 = load i32, ptr %3, align 4, !tbaa !46
  %60 = icmp slt i32 %59, 0
  br i1 %60, label %61, label %68

61:                                               ; preds = %58
  %62 = load i32, ptr %3, align 4, !tbaa !46
  %63 = add nsw i32 %62, 4
  %64 = sext i32 %63 to i64
  %65 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %64
  store i32 40, ptr %65, align 4, !tbaa !46
  %66 = load i32, ptr %3, align 4, !tbaa !46
  %67 = add nsw i32 %66, 1
  store i32 %67, ptr %3, align 4, !tbaa !46
  br label %58, !llvm.loop !51

68:                                               ; preds = %58
  store i32 -4, ptr %3, align 4, !tbaa !46
  br label %69

69:                                               ; preds = %72, %68
  %70 = load i32, ptr %3, align 4, !tbaa !46
  %71 = icmp slt i32 %70, 0
  br i1 %71, label %72, label %79

72:                                               ; preds = %69
  %73 = load i32, ptr %3, align 4, !tbaa !46
  %74 = add nsw i32 %73, 4
  %75 = sext i32 %74 to i64
  %76 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %75
  store i32 50, ptr %76, align 4, !tbaa !46
  %77 = load i32, ptr %3, align 4, !tbaa !46
  %78 = add nsw i32 %77, 2
  store i32 %78, ptr %3, align 4, !tbaa !46
  br label %69, !llvm.loop !52

79:                                               ; preds = %69
  store i32 -4, ptr %3, align 4, !tbaa !46
  br label %80

80:                                               ; preds = %83, %79
  %81 = load i32, ptr %3, align 4, !tbaa !46
  %82 = icmp sle i32 %81, 0
  br i1 %82, label %83, label %90

83:                                               ; preds = %80
  %84 = load i32, ptr %3, align 4, !tbaa !46
  %85 = add nsw i32 %84, 4
  %86 = sext i32 %85 to i64
  %87 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %86
  store i32 60, ptr %87, align 4, !tbaa !46
  %88 = load i32, ptr %3, align 4, !tbaa !46
  %89 = add nsw i32 %88, 2
  store i32 %89, ptr %3, align 4, !tbaa !46
  br label %80, !llvm.loop !53

90:                                               ; preds = %80
  store i32 -4, ptr %3, align 4, !tbaa !46
  br label %91

91:                                               ; preds = %94, %90
  %92 = load i32, ptr %3, align 4, !tbaa !46
  %93 = icmp sle i32 %92, 0
  br i1 %93, label %94, label %101

94:                                               ; preds = %91
  %95 = load i32, ptr %3, align 4, !tbaa !46
  %96 = add nsw i32 %95, 4
  %97 = sext i32 %96 to i64
  %98 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %97
  store i32 70, ptr %98, align 4, !tbaa !46
  %99 = load i32, ptr %3, align 4, !tbaa !46
  %100 = add nsw i32 %99, 3
  store i32 %100, ptr %3, align 4, !tbaa !46
  br label %91, !llvm.loop !54

101:                                              ; preds = %91
  store i32 -4, ptr %3, align 4, !tbaa !46
  br label %102

102:                                              ; preds = %105, %101
  %103 = load i32, ptr %3, align 4, !tbaa !46
  %104 = icmp sle i32 %103, 0
  br i1 %104, label %105, label %112

105:                                              ; preds = %102
  %106 = load i32, ptr %3, align 4, !tbaa !46
  %107 = add nsw i32 %106, 4
  %108 = sext i32 %107 to i64
  %109 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %108
  store i32 80, ptr %109, align 4, !tbaa !46
  %110 = load i32, ptr %3, align 4, !tbaa !46
  %111 = add nsw i32 %110, 4
  store i32 %111, ptr %3, align 4, !tbaa !46
  br label %102, !llvm.loop !55

112:                                              ; preds = %102
  store i32 -6, ptr %3, align 4, !tbaa !46
  br label %113

113:                                              ; preds = %116, %112
  %114 = load i32, ptr %3, align 4, !tbaa !46
  %115 = icmp sle i32 %114, 0
  br i1 %115, label %116, label %123

116:                                              ; preds = %113
  %117 = load i32, ptr %3, align 4, !tbaa !46
  %118 = add nsw i32 %117, 6
  %119 = sext i32 %118 to i64
  %120 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %119
  store i32 90, ptr %120, align 4, !tbaa !46
  %121 = load i32, ptr %3, align 4, !tbaa !46
  %122 = add nsw i32 %121, 5
  store i32 %122, ptr %3, align 4, !tbaa !46
  br label %113, !llvm.loop !56

123:                                              ; preds = %113
  store i32 8, ptr %3, align 4, !tbaa !46
  %124 = load i32, ptr %3, align 4, !tbaa !46
  %125 = icmp ne i32 %124, 0
  br i1 %125, label %126, label %127

126:                                              ; preds = %123
  store i32 9, ptr %4, align 4, !tbaa !46
  br label %127

127:                                              ; preds = %126, %123
  br label %128

128:                                              ; preds = %131, %127
  %129 = load i32, ptr %3, align 4, !tbaa !46
  %130 = icmp sle i32 %129, 10
  br i1 %130, label %131, label %137

131:                                              ; preds = %128
  %132 = load i32, ptr %3, align 4, !tbaa !46
  %133 = sext i32 %132 to i64
  %134 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %133
  store i32 80, ptr %134, align 4, !tbaa !46
  %135 = load i32, ptr %3, align 4, !tbaa !46
  %136 = add nsw i32 %135, 5
  store i32 %136, ptr %3, align 4, !tbaa !46
  br label %128, !llvm.loop !57

137:                                              ; preds = %128
  store i32 0, ptr %3, align 4, !tbaa !46
  br label %138

138:                                              ; preds = %145, %137
  %139 = load i32, ptr %3, align 4, !tbaa !46
  %140 = icmp slt i32 %139, 2
  br i1 %140, label %141, label %148

141:                                              ; preds = %138
  %142 = load i32, ptr %3, align 4, !tbaa !46
  %143 = sext i32 %142 to i64
  %144 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %143
  store i32 8, ptr %144, align 4, !tbaa !46
  br label %145

145:                                              ; preds = %141
  %146 = load i32, ptr %3, align 4, !tbaa !46
  %147 = add nsw i32 %146, 1
  store i32 %147, ptr %3, align 4, !tbaa !46
  br label %138, !llvm.loop !58

148:                                              ; preds = %138
  store i32 0, ptr %3, align 4, !tbaa !46
  br label %149

149:                                              ; preds = %156, %148
  %150 = load i32, ptr %3, align 4, !tbaa !46
  %151 = icmp slt i32 %150, 3
  br i1 %151, label %152, label %159

152:                                              ; preds = %149
  %153 = load i32, ptr %3, align 4, !tbaa !46
  %154 = sext i32 %153 to i64
  %155 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %154
  store i32 10, ptr %155, align 4, !tbaa !46
  br label %156

156:                                              ; preds = %152
  %157 = load i32, ptr %3, align 4, !tbaa !46
  %158 = add nsw i32 %157, 1
  store i32 %158, ptr %3, align 4, !tbaa !46
  br label %149, !llvm.loop !59

159:                                              ; preds = %149
  store i32 0, ptr %3, align 4, !tbaa !46
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  br label %160

160:                                              ; preds = %167, %159
  %161 = load i32, ptr %3, align 4, !tbaa !46
  %162 = icmp slt i32 %161, 3
  br i1 %162, label %163, label %170

163:                                              ; preds = %160
  %164 = load i32, ptr %3, align 4, !tbaa !46
  %165 = sext i32 %164 to i64
  %166 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %165
  store i32 11, ptr %166, align 4, !tbaa !46
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  br label %167

167:                                              ; preds = %163
  %168 = load i32, ptr %3, align 4, !tbaa !46
  %169 = add nsw i32 %168, 1
  store i32 %169, ptr %3, align 4, !tbaa !46
  br label %160, !llvm.loop !60

170:                                              ; preds = %160
  store i32 0, ptr %3, align 4, !tbaa !46
  br label %171

171:                                              ; preds = %178, %170
  %172 = load i32, ptr %3, align 4, !tbaa !46
  %173 = icmp slt i32 %172, 3
  br i1 %173, label %174, label %181

174:                                              ; preds = %171
  %175 = load i32, ptr %3, align 4, !tbaa !46
  %176 = sext i32 %175 to i64
  %177 = getelementptr inbounds [10 x i32], ptr %5, i64 0, i64 %176
  store i32 12, ptr %177, align 4, !tbaa !46
  br label %178

178:                                              ; preds = %174
  %179 = load i32, ptr %3, align 4, !tbaa !46
  %180 = add nsw i32 %179, 1
  store i32 %180, ptr %3, align 4, !tbaa !46
  br label %171, !llvm.loop !61

181:                                              ; preds = %171
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %7)
  call void @llvm.lifetime.end.p0(i64 40, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 40, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 464}
!10 = !{!"_ZTS4test", !11, i64 0, !33, i64 232, !6, i64 416, !6, i64 424, !6, i64 432, !6, i64 440, !6, i64 448, !6, i64 456, !6, i64 464, !6, i64 472, !6, i64 480, !6, i64 488, !6, i64 496, !6, i64 504, !6, i64 512, !6, i64 520}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !24, i64 112, !25, i64 120, !27, i64 144, !29, i64 168, !31, i64 192, !6, i64 200, !32, i64 208, !6, i64 216, !6, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !6, i64 96, !6, i64 104}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !7, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!23 = !{!"long", !7, i64 0}
!24 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !26, i64 8, !6, i64 16}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !28, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !30, i64 8, !6, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!31 = !{!"bool", !7, i64 0}
!32 = !{!"int", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !6, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !6, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = !{!31, !31, i64 0}
!42 = !{i8 0, i8 2}
!43 = !{}
!44 = distinct !{!44, !45}
!45 = !{!"llvm.loop.mustprogress"}
!46 = !{!32, !32, i64 0}
!47 = distinct !{!47, !45}
!48 = distinct !{!48, !45}
!49 = distinct !{!49, !45}
!50 = distinct !{!50, !45}
!51 = distinct !{!51, !45}
!52 = distinct !{!52, !45}
!53 = distinct !{!53, !45}
!54 = distinct !{!54, !45}
!55 = distinct !{!55, !45}
!56 = distinct !{!56, !45}
!57 = distinct !{!57, !45}
!58 = distinct !{!58, !45}
!59 = distinct !{!59, !45}
!60 = distinct !{!60, !45}
!61 = distinct !{!61, !45}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4test5entryEv(ptr noundef nonnull align 8 dereferenceable(528) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 464
  br label %3

3:                                                ; preds = %3, %1
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %4)
  %6 = load i8, ptr %5, align 1, !tbaa !40, !range !41, !noundef !42
  %7 = icmp eq i8 %6, 0
  br i1 %7, label %3, label %.preheader57.preheader, !llvm.loop !43

.preheader57.preheader:                           ; preds = %3
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 464}
!6 = !{!"_ZTS4test", !7, i64 0, !32, i64 232, !9, i64 416, !9, i64 424, !9, i64 432, !9, i64 440, !9, i64 448, !9, i64 456, !9, i64 464, !9, i64 472, !9, i64 480, !9, i64 488, !9, i64 496, !9, i64 504, !9, i64 512, !9, i64 520}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core5sc_inIbEE", !33, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!33 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !35, i64 0, !9, i64 120, !36, i64 128}
!35 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!36 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!40 = !{!30, !30, i64 0}
!41 = !{i8 0, i8 2}
!42 = !{}
!43 = distinct !{!43, !44}
!44 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass