; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci (NvmExpressGetNextNamespace)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._NVME_CONTROLLER_PRIVATE_DATA = type { i32, ptr, ptr, ptr, ptr, i64, ptr, %struct.NVM_EXPRESS_PASS_THRU_MODE, %struct._NVM_EXPRESS_PASS_THRU_PROTOCOL, ptr, ptr, ptr, [2 x ptr], [2 x ptr], [2 x ptr], [2 x ptr], [2 x %struct.NVME_SQTDBL], [2 x %struct.NVME_CQHDBL], [2 x i8], [2 x i16], %struct.NVME_CAP, ptr }
%struct.NVM_EXPRESS_PASS_THRU_MODE = type { i32, i32, i32, i32, i64, i32 }
%struct._NVM_EXPRESS_PASS_THRU_PROTOCOL = type { ptr, ptr, ptr, ptr, ptr }
%struct.NVME_SQTDBL = type { i16, i16 }
%struct.NVME_CQHDBL = type { i16, i16 }
%struct.NVME_CAP = type { i16, i8, i8, i16, i8, i8 }
%struct.NVME_ADMIN_NAMESPACE_DATA = type { i64, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8, [88 x i8], i64, [16 x %struct.NVME_LBAFORMAT], [192 x i8], [3712 x i8] }
%struct.NVME_LBAFORMAT = type { i16, i8, i8 }
%struct.NVME_ADMIN_CONTROLLER_DATA = type { i16, i16, [20 x i8], [40 x i8], [8 x i8], i8, [3 x i8], i8, i8, [2 x i8], [176 x i8], i16, i8, i8, i8, i8, i8, i8, i8, i8, [246 x i8], i8, i8, i16, i32, i16, i16, i8, i8, i16, i16, i8, i8, i16, i16, i32, [164 x i8], [1344 x i8], [32 x %struct.NVME_PSDESCRIPTOR], [1024 x i8] }
%struct.NVME_PSDESCRIPTOR = type { i16, i8, i8, i32, i32, i32, [16 x i8] }

@.str.52 = external hidden unnamed_addr constant [157 x i8], align 1
@.str.53 = external hidden unnamed_addr constant [21 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare zeroext i8 @DebugAssertEnabled() #1

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i64 @NvmExpressGetNextNamespace(ptr noundef %0, ptr noundef %1, ptr noundef %2) #2 {
  %4 = alloca i64, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = icmp eq ptr %13, null
  br i1 %14, label %18, label %15

15:                                               ; preds = %3
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %19

18:                                               ; preds = %15, %3
  store i64 -9223372036854775806, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %112

19:                                               ; preds = %15
  store ptr null, ptr %9, align 8, !tbaa !5
  store i64 -9223372036854775794, ptr %11, align 8, !tbaa !9
  %20 = call zeroext i8 @DebugAssertEnabled()
  %21 = zext i8 %20 to i32
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %33

23:                                               ; preds = %19
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = ptrtoint ptr %24 to i64
  %26 = sub i64 %25, ptrtoint (ptr getelementptr inbounds (%struct._NVME_CONTROLLER_PRIVATE_DATA, ptr null, i32 0, i32 8) to i64)
  %27 = inttoptr i64 %26 to ptr
  %28 = getelementptr inbounds %struct._NVME_CONTROLLER_PRIVATE_DATA, ptr %27, i32 0, i32 0
  %29 = load i32, ptr %28, align 8, !tbaa !11
  %30 = icmp ne i32 %29, 1162696270
  br i1 %30, label %31, label %33

31:                                               ; preds = %23
  call void @DebugAssert(ptr noundef @.str.52, i64 noundef 693, ptr noundef @.str.53)
  %32 = load ptr, ptr %5, align 8, !tbaa !5
  br label %38

33:                                               ; preds = %23, %19
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = ptrtoint ptr %34 to i64
  %36 = sub i64 %35, ptrtoint (ptr getelementptr inbounds (%struct._NVME_CONTROLLER_PRIVATE_DATA, ptr null, i32 0, i32 8) to i64)
  %37 = inttoptr i64 %36 to ptr
  br label %38

38:                                               ; preds = %33, %31
  %39 = phi ptr [ %32, %31 ], [ %37, %33 ]
  store ptr %39, ptr %8, align 8, !tbaa !5
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = load i32, ptr %40, align 4, !tbaa !18
  %42 = icmp eq i32 %41, -1
  br i1 %42, label %43, label %67

43:                                               ; preds = %38
  store i32 1, ptr %10, align 4, !tbaa !18
  %44 = call ptr @AllocateZeroPool(i64 noundef 4096)
  store ptr %44, ptr %9, align 8, !tbaa !5
  %45 = load ptr, ptr %9, align 8, !tbaa !5
  %46 = icmp eq ptr %45, null
  br i1 %46, label %47, label %48

47:                                               ; preds = %43
  store i64 -9223372036854775794, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %112

48:                                               ; preds = %43
  %49 = load ptr, ptr %8, align 8, !tbaa !5
  %50 = load i32, ptr %10, align 4, !tbaa !18
  %51 = load ptr, ptr %9, align 8, !tbaa !5
  %52 = call i64 @NvmeIdentifyNamespace(ptr noundef %49, i32 noundef %50, ptr noundef %51)
  store i64 %52, ptr %11, align 8, !tbaa !9
  %53 = load i64, ptr %11, align 8, !tbaa !9
  %54 = icmp slt i64 %53, 0
  br i1 %54, label %55, label %56

55:                                               ; preds = %48
  br label %105

56:                                               ; preds = %48
  %57 = load i32, ptr %10, align 4, !tbaa !18
  %58 = load ptr, ptr %6, align 8, !tbaa !5
  store i32 %57, ptr %58, align 4, !tbaa !18
  %59 = load ptr, ptr %7, align 8, !tbaa !5
  %60 = icmp ne ptr %59, null
  br i1 %60, label %61, label %66

61:                                               ; preds = %56
  %62 = load ptr, ptr %9, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.NVME_ADMIN_NAMESPACE_DATA, ptr %62, i32 0, i32 12
  %64 = load i64, ptr %63, align 1, !tbaa !19
  %65 = load ptr, ptr %7, align 8, !tbaa !5
  store i64 %64, ptr %65, align 8, !tbaa !9
  br label %66

66:                                               ; preds = %61, %56
  br label %104

67:                                               ; preds = %38
  %68 = load ptr, ptr %6, align 8, !tbaa !5
  %69 = load i32, ptr %68, align 4, !tbaa !18
  %70 = load ptr, ptr %8, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct._NVME_CONTROLLER_PRIVATE_DATA, ptr %70, i32 0, i32 9
  %72 = load ptr, ptr %71, align 8, !tbaa !21
  %73 = getelementptr inbounds %struct.NVME_ADMIN_CONTROLLER_DATA, ptr %72, i32 0, i32 24
  %74 = load i32, ptr %73, align 1, !tbaa !22
  %75 = icmp uge i32 %69, %74
  br i1 %75, label %76, label %77

76:                                               ; preds = %67
  store i64 -9223372036854775806, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %112

77:                                               ; preds = %67
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  %79 = load i32, ptr %78, align 4, !tbaa !18
  %80 = add i32 %79, 1
  store i32 %80, ptr %10, align 4, !tbaa !18
  %81 = call ptr @AllocateZeroPool(i64 noundef 4096)
  store ptr %81, ptr %9, align 8, !tbaa !5
  %82 = load ptr, ptr %9, align 8, !tbaa !5
  %83 = icmp eq ptr %82, null
  br i1 %83, label %84, label %85

84:                                               ; preds = %77
  store i64 -9223372036854775794, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %112

85:                                               ; preds = %77
  %86 = load ptr, ptr %8, align 8, !tbaa !5
  %87 = load i32, ptr %10, align 4, !tbaa !18
  %88 = load ptr, ptr %9, align 8, !tbaa !5
  %89 = call i64 @NvmeIdentifyNamespace(ptr noundef %86, i32 noundef %87, ptr noundef %88)
  store i64 %89, ptr %11, align 8, !tbaa !9
  %90 = load i64, ptr %11, align 8, !tbaa !9
  %91 = icmp slt i64 %90, 0
  br i1 %91, label %92, label %93

92:                                               ; preds = %85
  br label %105

93:                                               ; preds = %85
  %94 = load i32, ptr %10, align 4, !tbaa !18
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  store i32 %94, ptr %95, align 4, !tbaa !18
  %96 = load ptr, ptr %7, align 8, !tbaa !5
  %97 = icmp ne ptr %96, null
  br i1 %97, label %98, label %103

98:                                               ; preds = %93
  %99 = load ptr, ptr %9, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.NVME_ADMIN_NAMESPACE_DATA, ptr %99, i32 0, i32 12
  %101 = load i64, ptr %100, align 1, !tbaa !19
  %102 = load ptr, ptr %7, align 8, !tbaa !5
  store i64 %101, ptr %102, align 8, !tbaa !9
  br label %103

103:                                              ; preds = %98, %93
  br label %104

104:                                              ; preds = %103, %66
  br label %105

105:                                              ; preds = %104, %92, %55
  %106 = load ptr, ptr %9, align 8, !tbaa !5
  %107 = icmp ne ptr %106, null
  br i1 %107, label %108, label %110

108:                                              ; preds = %105
  %109 = load ptr, ptr %9, align 8, !tbaa !5
  call void @FreePool(ptr noundef %109)
  br label %110

110:                                              ; preds = %108, %105
  %111 = load i64, ptr %11, align 8, !tbaa !9
  store i64 %111, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %112

112:                                              ; preds = %110, %84, %76, %47, %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  %113 = load i64, ptr %4, align 8
  ret i64 %113
}

declare ptr @AllocateZeroPool(i64 noundef) #1

declare i64 @NvmeIdentifyNamespace(ptr noundef, i32 noundef, ptr noundef) #1

declare void @FreePool(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !13, i64 0}
!12 = !{!"_NVME_CONTROLLER_PRIVATE_DATA", !13, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !6, i64 48, !14, i64 56, !15, i64 88, !6, i64 128, !6, i64 136, !6, i64 144, !7, i64 152, !7, i64 168, !7, i64 184, !7, i64 200, !7, i64 216, !7, i64 224, !7, i64 232, !7, i64 234, !16, i64 238, !6, i64 248}
!13 = !{!"int", !7, i64 0}
!14 = !{!"", !13, i64 0, !13, i64 4, !13, i64 8, !13, i64 12, !10, i64 16, !13, i64 24}
!15 = !{!"_NVM_EXPRESS_PASS_THRU_PROTOCOL", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!16 = !{!"", !17, i64 0, !7, i64 2, !7, i64 2, !7, i64 2, !7, i64 3, !17, i64 4, !17, i64 4, !17, i64 4, !17, i64 5, !7, i64 6, !7, i64 6, !7, i64 7}
!17 = !{!"short", !7, i64 0}
!18 = !{!13, !13, i64 0}
!19 = !{!20, !10, i64 120}
!20 = !{!"", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 25, !7, i64 26, !7, i64 27, !7, i64 28, !7, i64 29, !7, i64 30, !7, i64 31, !7, i64 32, !10, i64 120, !7, i64 128, !7, i64 192, !7, i64 384}
!21 = !{!12, !6, i64 128}
!22 = !{!23, !13, i64 516}
!23 = !{!"", !17, i64 0, !17, i64 2, !7, i64 4, !7, i64 24, !7, i64 64, !7, i64 72, !7, i64 73, !7, i64 76, !7, i64 77, !7, i64 78, !7, i64 80, !17, i64 256, !7, i64 258, !7, i64 259, !7, i64 260, !7, i64 261, !7, i64 262, !7, i64 263, !7, i64 264, !7, i64 265, !7, i64 266, !7, i64 512, !7, i64 513, !17, i64 514, !13, i64 516, !17, i64 520, !17, i64 522, !7, i64 524, !7, i64 525, !17, i64 526, !17, i64 528, !7, i64 530, !7, i64 531, !17, i64 532, !17, i64 534, !13, i64 536, !7, i64 540, !7, i64 704, !7, i64 2048, !7, i64 3072}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.52 = external hidden unnamed_addr constant [157 x i8], align 1
@.str.53 = external hidden unnamed_addr constant [21 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i64 @NvmExpressGetNextNamespace(ptr noundef %0, ptr noundef %1, ptr noundef writeonly %2) local_unnamed_addr #1 {
  %4 = icmp eq ptr %0, null
  %5 = icmp eq ptr %1, null
  %or.cond = or i1 %4, %5
  br i1 %or.cond, label %37, label %6

6:                                                ; preds = %3
  %7 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not = icmp eq i8 %7, 0
  %.pre = ptrtoint ptr %0 to i64
  %.pre49 = add i64 %.pre, -88
  %.pre51 = inttoptr i64 %.pre49 to ptr
  br i1 %.not, label %._crit_edge, label %8

8:                                                ; preds = %6
  %9 = load i32, ptr %.pre51, align 8, !tbaa !5
  %.not45 = icmp eq i32 %9, 1162696270
  br i1 %.not45, label %._crit_edge, label %10

10:                                               ; preds = %8
  tail call void @DebugAssert(ptr noundef nonnull @.str.52, i64 noundef 693, ptr noundef nonnull @.str.53) #2
  br label %._crit_edge

._crit_edge:                                      ; preds = %6, %8, %10
  %11 = phi ptr [ %0, %10 ], [ %.pre51, %8 ], [ %.pre51, %6 ]
  %12 = load i32, ptr %1, align 4, !tbaa !16
  %13 = icmp eq i32 %12, -1
  br i1 %13, label %14, label %21

14:                                               ; preds = %._crit_edge
  %15 = tail call ptr @AllocateZeroPool(i64 noundef 4096) #2
  %16 = icmp eq ptr %15, null
  br i1 %16, label %37, label %17

17:                                               ; preds = %14
  %18 = tail call i64 @NvmeIdentifyNamespace(ptr noundef %11, i32 noundef 1, ptr noundef nonnull %15) #2
  %19 = icmp slt i64 %18, 0
  br i1 %19, label %36, label %20

20:                                               ; preds = %17
  store i32 1, ptr %1, align 4, !tbaa !16
  %.not48 = icmp eq ptr %2, null
  br i1 %.not48, label %36, label %.sink.split

21:                                               ; preds = %._crit_edge
  %22 = getelementptr inbounds i8, ptr %11, i64 128
  %23 = load ptr, ptr %22, align 8, !tbaa !17
  %24 = getelementptr inbounds i8, ptr %23, i64 516
  %25 = load i32, ptr %24, align 1, !tbaa !18
  %.not46 = icmp ult i32 %12, %25
  br i1 %.not46, label %26, label %37

26:                                               ; preds = %21
  %27 = add nuw i32 %12, 1
  %28 = tail call ptr @AllocateZeroPool(i64 noundef 4096) #2
  %29 = icmp eq ptr %28, null
  br i1 %29, label %37, label %30

30:                                               ; preds = %26
  %31 = tail call i64 @NvmeIdentifyNamespace(ptr noundef nonnull %11, i32 noundef %27, ptr noundef nonnull %28) #2
  %32 = icmp slt i64 %31, 0
  br i1 %32, label %36, label %33

33:                                               ; preds = %30
  store i32 %27, ptr %1, align 4, !tbaa !16
  %.not47 = icmp eq ptr %2, null
  br i1 %.not47, label %36, label %.sink.split

.sink.split:                                      ; preds = %33, %20
  %.sink = phi ptr [ %15, %20 ], [ %28, %33 ]
  %.0.ph = phi i64 [ %18, %20 ], [ %31, %33 ]
  %34 = getelementptr inbounds i8, ptr %.sink, i64 120
  %35 = load i64, ptr %34, align 1, !tbaa !20
  store i64 %35, ptr %2, align 8, !tbaa !22
  br label %36

36:                                               ; preds = %.sink.split, %17, %30, %33, %20
  %.033 = phi ptr [ %15, %17 ], [ %15, %20 ], [ %28, %30 ], [ %28, %33 ], [ %.sink, %.sink.split ]
  %.0 = phi i64 [ %18, %17 ], [ %18, %20 ], [ %31, %30 ], [ %31, %33 ], [ %.0.ph, %.sink.split ]
  tail call void @FreePool(ptr noundef nonnull %.033) #2
  br label %37

37:                                               ; preds = %26, %21, %14, %3, %36
  %.034 = phi i64 [ %.0, %36 ], [ -9223372036854775806, %3 ], [ -9223372036854775794, %14 ], [ -9223372036854775806, %21 ], [ -9223372036854775794, %26 ]
  ret i64 %.034
}

declare ptr @AllocateZeroPool(i64 noundef) local_unnamed_addr #0

declare i64 @NvmeIdentifyNamespace(ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #0

declare void @FreePool(ptr noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_NVME_CONTROLLER_PRIVATE_DATA", !7, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !11, i64 40, !10, i64 48, !12, i64 56, !13, i64 88, !10, i64 128, !10, i64 136, !10, i64 144, !8, i64 152, !8, i64 168, !8, i64 184, !8, i64 200, !8, i64 216, !8, i64 224, !8, i64 232, !8, i64 234, !14, i64 238, !10, i64 248}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!"long long", !8, i64 0}
!12 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !11, i64 16, !7, i64 24}
!13 = !{!"_NVM_EXPRESS_PASS_THRU_PROTOCOL", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32}
!14 = !{!"", !15, i64 0, !8, i64 2, !8, i64 2, !8, i64 2, !8, i64 3, !15, i64 4, !15, i64 4, !15, i64 4, !15, i64 5, !8, i64 6, !8, i64 6, !8, i64 7}
!15 = !{!"short", !8, i64 0}
!16 = !{!7, !7, i64 0}
!17 = !{!6, !10, i64 128}
!18 = !{!19, !7, i64 516}
!19 = !{!"", !15, i64 0, !15, i64 2, !8, i64 4, !8, i64 24, !8, i64 64, !8, i64 72, !8, i64 73, !8, i64 76, !8, i64 77, !8, i64 78, !8, i64 80, !15, i64 256, !8, i64 258, !8, i64 259, !8, i64 260, !8, i64 261, !8, i64 262, !8, i64 263, !8, i64 264, !8, i64 265, !8, i64 266, !8, i64 512, !8, i64 513, !15, i64 514, !7, i64 516, !15, i64 520, !15, i64 522, !8, i64 524, !8, i64 525, !15, i64 526, !15, i64 528, !8, i64 530, !8, i64 531, !15, i64 532, !15, i64 534, !7, i64 536, !8, i64 540, !8, i64 704, !8, i64 2048, !8, i64 3072}
!20 = !{!21, !11, i64 120}
!21 = !{!"", !11, i64 0, !11, i64 8, !11, i64 16, !8, i64 24, !8, i64 25, !8, i64 26, !8, i64 27, !8, i64 28, !8, i64 29, !8, i64 30, !8, i64 31, !8, i64 32, !11, i64 120, !8, i64 128, !8, i64 192, !8, i64 384}
!22 = !{!11, !11, i64 0}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass