; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_port)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_port_registry" = type { i32, %"class.std::vector.48", ptr }
%"class.std::vector.48" = type { %"struct.std::_Vector_base.49" }
%"struct.std::_Vector_base.49" = type { %"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_port_base17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(120)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN7sc_core16sc_port_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %0) #1 align 2 {
  %2 = alloca i1, align 1
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  %6 = call noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %5)
  %7 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %5, i32 0, i32 0
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp eq i32 %6, %8
  br i1 %9, label %10, label %11

10:                                               ; preds = %1
  store i1 true, ptr %2, align 1
  br label %32

11:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  %12 = call noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %5)
  %13 = sub nsw i32 %12, 1
  store i32 %13, ptr %4, align 4, !tbaa !16
  br label %14

14:                                               ; preds = %26, %11
  %15 = load i32, ptr %4, align 4, !tbaa !16
  %16 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %5, i32 0, i32 0
  %17 = load i32, ptr %16, align 8, !tbaa !9
  %18 = icmp sge i32 %15, %17
  br i1 %18, label %20, label %19

19:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  br label %29

20:                                               ; preds = %14
  %21 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %5, i32 0, i32 1
  %22 = load i32, ptr %4, align 4, !tbaa !16
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #3
  %25 = load ptr, ptr %24, align 8, !tbaa !5
  call void @_ZN7sc_core12sc_port_base17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(120) %25)
  br label %26

26:                                               ; preds = %20
  %27 = load i32, ptr %4, align 4, !tbaa !16
  %28 = add nsw i32 %27, -1
  store i32 %28, ptr %4, align 4, !tbaa !16
  br label %14, !llvm.loop !17

29:                                               ; preds = %19
  %30 = call noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %5)
  %31 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %5, i32 0, i32 0
  store i32 %30, ptr %31, align 8, !tbaa !9
  store i1 false, ptr %2, align 1
  br label %32

32:                                               ; preds = %29, %10
  %33 = load i1, ptr %2, align 1
  ret i1 %33
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTSN7sc_core16sc_port_registryE", !11, i64 0, !12, i64 8, !6, i64 32}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!11, !11, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core12sc_port_base17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(120)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN7sc_core16sc_port_registry17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(40) %0) local_unnamed_addr #0 align 2 {
  %2 = tail call noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  %3 = load i32, ptr %0, align 8, !tbaa !5
  %4 = icmp eq i32 %2, %3
  br i1 %4, label %16, label %5

5:                                                ; preds = %1
  %6 = tail call noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  %7 = load i32, ptr %0, align 8, !tbaa !5
  %.not.not5 = icmp sgt i32 %6, %7
  br i1 %.not.not5, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %5
  %8 = getelementptr inbounds i8, ptr %0, i64 8
  %9 = sext i32 %6 to i64
  br label %11

._crit_edge:                                      ; preds = %11, %5
  %10 = tail call noundef i32 @_ZNK7sc_core16sc_port_registry4sizeEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  store i32 %10, ptr %0, align 8, !tbaa !5
  br label %16

11:                                               ; preds = %.lr.ph, %11
  %indvars.iv = phi i64 [ %9, %.lr.ph ], [ %indvars.iv.next, %11 ]
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %indvars.iv.next) #2
  %13 = load ptr, ptr %12, align 8, !tbaa !15
  tail call void @_ZN7sc_core12sc_port_base17construction_doneEv(ptr noundef nonnull align 8 dereferenceable(120) %13)
  %14 = load i32, ptr %0, align 8, !tbaa !5
  %15 = sext i32 %14 to i64
  %.not.not = icmp sgt i64 %indvars.iv.next, %15
  br i1 %.not.not, label %11, label %._crit_edge, !llvm.loop !16

16:                                               ; preds = %1, %._crit_edge
  ret i1 %4
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7sc_core16sc_port_registryE", !7, i64 0, !10, i64 8, !14, i64 32}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!14, !14, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass