; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_signal_ports)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_inout.41" = type { %"class.sc_core::sc_port.34", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.34" = type { %"class.sc_core::sc_port_b.35" }
%"class.sc_core::sc_port_b.35" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.36" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.36" = type { %"struct.std::_Vector_base.37" }
%"struct.std::_Vector_base.37" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_logic> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTIN7sc_core12sc_interfaceE = external constant ptr
@_ZTIN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEE = external dso_local constant { ptr, ptr, i32, i32, ptr, i64, ptr, i64 }, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicdlEPvm(ptr noundef, i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE10initializeERKS2_(ptr noundef nonnull align 8 dereferenceable(192) %0, ptr noundef nonnull align 4 dereferenceable(4) %1) #3 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %9 = load ptr, ptr %8, align 8, !tbaa !9
  %10 = getelementptr inbounds ptr, ptr %9, i64 15
  %11 = load ptr, ptr %10, align 8
  %12 = call noundef ptr %11(ptr noundef nonnull align 8 dereferenceable(152) %8)
  %13 = icmp eq ptr %12, null
  br i1 %13, label %16, label %14

14:                                               ; preds = %2
  %15 = call ptr @__dynamic_cast(ptr %12, ptr @_ZTIN7sc_core12sc_interfaceE, ptr @_ZTIN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEE, i64 -1) #4
  br label %17

16:                                               ; preds = %2
  br label %17

17:                                               ; preds = %16, %14
  %18 = phi ptr [ %15, %14 ], [ null, %16 ]
  store ptr %18, ptr %5, align 8, !tbaa !5
  %19 = load ptr, ptr %5, align 8, !tbaa !5
  %20 = icmp ne ptr %19, null
  br i1 %20, label %21, label %28

21:                                               ; preds = %17
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds i8, ptr %22, i64 8
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = load ptr, ptr %23, align 8, !tbaa !9
  %26 = getelementptr inbounds ptr, ptr %25, i64 4
  %27 = load ptr, ptr %26, align 8
  call void %27(ptr noundef nonnull align 8 dereferenceable(8) %23, ptr noundef nonnull align 4 dereferenceable(4) %24)
  br label %45

28:                                               ; preds = %17
  %29 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %8, i32 0, i32 1
  %30 = load ptr, ptr %29, align 8, !tbaa !11
  %31 = icmp eq ptr %30, null
  br i1 %31, label %32, label %40

32:                                               ; preds = %28
  %33 = call noundef ptr @_ZN5sc_dt8sc_logicnwEm(i64 noundef 4)
  invoke void @_ZN5sc_dt8sc_logicC2Ev(ptr noundef nonnull align 4 dereferenceable(4) %33)
          to label %34 unwind label %36

34:                                               ; preds = %32
  %35 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %8, i32 0, i32 1
  store ptr %33, ptr %35, align 8, !tbaa !11
  br label %40

36:                                               ; preds = %32
  %37 = landingpad { ptr, i32 }
          cleanup
  %38 = extractvalue { ptr, i32 } %37, 0
  store ptr %38, ptr %6, align 8
  %39 = extractvalue { ptr, i32 } %37, 1
  store i32 %39, ptr %7, align 4
  call void @_ZN5sc_dt8sc_logicdlEPvm(ptr noundef %33, i64 noundef 4) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  br label %46

40:                                               ; preds = %34, %28
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  %42 = getelementptr inbounds %"class.sc_core::sc_inout.41", ptr %8, i32 0, i32 1
  %43 = load ptr, ptr %42, align 8, !tbaa !11
  %44 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN5sc_dt8sc_logicaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) %43, ptr noundef nonnull align 4 dereferenceable(4) %41)
  br label %45

45:                                               ; preds = %40, %21
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret void

46:                                               ; preds = %36
  %47 = load ptr, ptr %6, align 8
  %48 = load i32, ptr %7, align 4
  %49 = insertvalue { ptr, i32 } poison, ptr %47, 0
  %50 = insertvalue { ptr, i32 } %49, i32 %48, 1
  resume { ptr, i32 } %50
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN5sc_dt8sc_logicnwEm(i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicC2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN5sc_dt8sc_logicaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind willreturn memory(read) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 152}
!12 = !{!"_ZTSN7sc_core8sc_inoutIN5sc_dt8sc_logicEEE", !13, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176, !6, i64 184}
!13 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !14, i64 0}
!14 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEEEE", !15, i64 0, !6, i64 120, !28, i64 128}
!15 = !{!"_ZTSN7sc_core12sc_port_baseE", !16, i64 0, !6, i64 112}
!16 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !17, i64 16, !21, i64 40, !25, i64 64, !6, i64 96, !6, i64 104}
!17 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !26, i64 0, !27, i64 8, !7, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!27 = !{!"long", !7, i64 0}
!28 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN7sc_core12sc_interfaceE = external constant ptr
@_ZTIN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEE = external dso_local constant { ptr, ptr, i32, i32, ptr, i64, ptr, i64 }, align 8

; Function Attrs: mustprogress nofree nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) local_unnamed_addr #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_inoutIN5sc_dt8sc_logicEE10initializeERKS2_(ptr noundef nonnull align 8 dereferenceable(192) %0, ptr noundef nonnull align 4 dereferenceable(4) %1) local_unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %3, i64 120
  %5 = load ptr, ptr %4, align 8
  %6 = tail call noundef ptr %5(ptr noundef nonnull align 8 dereferenceable(152) %0)
  %7 = icmp eq ptr %6, null
  br i1 %7, label %.thread, label %8

8:                                                ; preds = %2
  %9 = tail call ptr @__dynamic_cast(ptr nonnull %6, ptr nonnull @_ZTIN7sc_core12sc_interfaceE, ptr nonnull @_ZTIN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEE, i64 -1) #3
  %.not = icmp eq ptr %9, null
  br i1 %.not, label %.thread, label %10

10:                                               ; preds = %8
  %11 = getelementptr inbounds i8, ptr %9, i64 8
  %12 = load ptr, ptr %11, align 8, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %12, i64 32
  %14 = load ptr, ptr %13, align 8
  tail call void %14(ptr noundef nonnull align 8 dereferenceable(8) %11, ptr noundef nonnull align 4 dereferenceable(4) %1)
  br label %23

.thread:                                          ; preds = %2, %8
  %15 = getelementptr inbounds i8, ptr %0, i64 152
  %16 = load ptr, ptr %15, align 8, !tbaa !8
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %20

18:                                               ; preds = %.thread
  %19 = tail call noundef ptr @_ZN5sc_dt8sc_logicnwEm(i64 noundef 4)
  tail call void @_ZN5sc_dt8sc_logicC2Ev(ptr noundef nonnull align 4 dereferenceable(4) %19)
  store ptr %19, ptr %15, align 8, !tbaa !8
  br label %20

20:                                               ; preds = %18, %.thread
  %21 = phi ptr [ %19, %18 ], [ %16, %.thread ]
  %22 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN5sc_dt8sc_logicaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) %21, ptr noundef nonnull align 4 dereferenceable(4) %1)
  br label %23

23:                                               ; preds = %20, %10
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN5sc_dt8sc_logicnwEm(i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt8sc_logicC2Ev(ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN5sc_dt8sc_logicaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nofree nounwind willreturn memory(read) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !14, i64 152}
!9 = !{!"_ZTSN7sc_core8sc_inoutIN5sc_dt8sc_logicEEE", !10, i64 0, !14, i64 152, !14, i64 160, !14, i64 168, !14, i64 176, !14, i64 184}
!10 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEELi1ELNS_14sc_port_policyE0EEE", !11, i64 0}
!11 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIN5sc_dt8sc_logicEEEEE", !12, i64 0, !14, i64 120, !27, i64 128}
!12 = !{!"_ZTSN7sc_core12sc_port_baseE", !13, i64 0, !14, i64 112}
!13 = !{!"_ZTSN7sc_core9sc_objectE", !14, i64 8, !16, i64 16, !20, i64 40, !24, i64 64, !14, i64 96, !14, i64 104}
!14 = !{!"any pointer", !15, i64 0}
!15 = !{!"omnipotent char", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !25, i64 0, !26, i64 8, !15, i64 16}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !14, i64 0}
!26 = !{!"long", !15, i64 0}
!27 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIN5sc_dt8sc_logicEEESaIS5_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass