; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel (sc_simcontext)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector.56", %"class.std::vector.56", %"class.std::vector.26", %"class.std::vector.26" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.56" = type { %"struct.std::_Vector_base.57" }
%"struct.std::_Vector_base.57" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_time" = type { i64 }

@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1
@.str.18 = external hidden unnamed_addr constant [17 x i8], align 1
@__PRETTY_FUNCTION__._ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE = external hidden unnamed_addr constant [60 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr noundef %1) #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %"class.sc_core::sc_event", ptr %9, i32 0, i32 4
  %11 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %11, ptr %5, align 4, !tbaa !24
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %12 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %8, i32 0, i32 15
  %13 = call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %14 = sub i64 %13, 1
  %15 = trunc i64 %14 to i32
  store i32 %15, ptr %6, align 4, !tbaa !24
  %16 = load i32, ptr %5, align 4, !tbaa !24
  %17 = icmp sge i32 %16, 0
  br i1 %17, label %18, label %22

18:                                               ; preds = %2
  %19 = load i32, ptr %5, align 4, !tbaa !24
  %20 = load i32, ptr %6, align 4, !tbaa !24
  %21 = icmp sle i32 %19, %20
  br label %22

22:                                               ; preds = %18, %2
  %23 = phi i1 [ false, %2 ], [ %21, %18 ]
  br i1 %23, label %24, label %25

24:                                               ; preds = %22
  br label %27

25:                                               ; preds = %22
  call void @__assert_fail(ptr noundef @.str.18, ptr noundef @.str.7, i32 noundef 1377, ptr noundef @__PRETTY_FUNCTION__._ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE) #5
  unreachable

26:                                               ; No predecessors!
  br label %27

27:                                               ; preds = %26, %24
  %28 = load i32, ptr %5, align 4, !tbaa !24
  %29 = load i32, ptr %6, align 4, !tbaa !24
  %30 = icmp ne i32 %28, %29
  br i1 %30, label %31, label %50

31:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %32 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %8, i32 0, i32 15
  %33 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef 0) #4
  store ptr %33, ptr %7, align 8, !tbaa !5
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = load i32, ptr %6, align 4, !tbaa !24
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds ptr, ptr %34, i64 %36
  %38 = load ptr, ptr %37, align 8, !tbaa !5
  %39 = load ptr, ptr %7, align 8, !tbaa !5
  %40 = load i32, ptr %5, align 4, !tbaa !24
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds ptr, ptr %39, i64 %41
  store ptr %38, ptr %42, align 8, !tbaa !5
  %43 = load i32, ptr %5, align 4, !tbaa !24
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = load i32, ptr %5, align 4, !tbaa !24
  %46 = sext i32 %45 to i64
  %47 = getelementptr inbounds ptr, ptr %44, i64 %46
  %48 = load ptr, ptr %47, align 8, !tbaa !5
  %49 = getelementptr inbounds %"class.sc_core::sc_event", ptr %48, i32 0, i32 4
  store i32 %43, ptr %49, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %50

50:                                               ; preds = %31, %27
  %51 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %8, i32 0, i32 15
  %52 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %8, i32 0, i32 15
  %53 = call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %52) #4
  %54 = sub i64 %53, 1
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %51, i64 noundef %54)
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  %56 = getelementptr inbounds %"class.sc_core::sc_event", ptr %55, i32 0, i32 4
  store i32 -1, ptr %56, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret void
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !15, i64 52}
!10 = !{!"_ZTSN7sc_core8sc_eventE", !11, i64 0, !6, i64 32, !6, i64 40, !14, i64 48, !15, i64 52, !6, i64 56, !16, i64 64, !16, i64 88, !20, i64 112, !20, i64 136}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !13, i64 8, !7, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!13 = !{!"long", !7, i64 0}
!14 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!15, !15, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.7 = external hidden unnamed_addr constant [89 x i8], align 1
@.str.18 = external hidden unnamed_addr constant [17 x i8], align 1
@__PRETTY_FUNCTION__._ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE = external hidden unnamed_addr constant [60 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(344) %0, ptr nocapture noundef %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %1, i64 52
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 168
  %6 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  %7 = trunc i64 %6 to i32
  %8 = add i32 %7, -1
  %9 = icmp sgt i32 %4, -1
  %10 = icmp sle i32 %4, %8
  %11 = and i1 %9, %10
  br i1 %11, label %13, label %12

12:                                               ; preds = %2
  tail call void @__assert_fail(ptr noundef nonnull @.str.18, ptr noundef nonnull @.str.7, i32 noundef 1377, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE) #4
  unreachable

13:                                               ; preds = %2
  %.not = icmp eq i32 %4, %8
  br i1 %.not, label %22, label %14

14:                                               ; preds = %13
  %15 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef 0) #3
  %16 = sext i32 %8 to i64
  %17 = getelementptr inbounds ptr, ptr %15, i64 %16
  %18 = load ptr, ptr %17, align 8, !tbaa !23
  %19 = zext nneg i32 %4 to i64
  %20 = getelementptr inbounds ptr, ptr %15, i64 %19
  store ptr %18, ptr %20, align 8, !tbaa !23
  %21 = getelementptr inbounds i8, ptr %18, i64 52
  store i32 %4, ptr %21, align 4, !tbaa !5
  br label %22

22:                                               ; preds = %14, %13
  %23 = tail call noundef i64 @_ZNKSt6vectorIPN7sc_core8sc_eventESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  %24 = add i64 %23, -1
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %24)
  store i32 -1, ptr %3, align 4, !tbaa !5
  ret void
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 52}
!6 = !{!"_ZTSN7sc_core8sc_eventE", !7, i64 0, !9, i64 32, !9, i64 40, !13, i64 48, !14, i64 52, !9, i64 56, !15, i64 64, !15, i64 88, !19, i64 112, !19, i64 136}
!7 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !8, i64 0, !12, i64 8, !10, i64 16}
!8 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"long", !10, i64 0}
!13 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !10, i64 0}
!14 = !{!"int", !10, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!23 = !{!9, !9, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass