; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_event.ll (ZN7sc_core8sc_event6cancelEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_event" = type { %"class.std::__cxx11::basic_string", ptr, ptr, i32, i32, ptr, %"class.std::vector", %"class.std::vector", %"class.std::vector.3", %"class.std::vector.3" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_method_process *, std::allocator<sc_core::sc_method_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_event_timed" = type { ptr, %"class.sc_core::sc_time" }
%"class.sc_core::sc_time" = type { i64 }

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str = external hidden unnamed_addr constant [13 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [84 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_event6cancelEv(ptr noundef nonnull align 8 dereferenceable(160) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  %4 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 3
  %5 = load i32, ptr %4, align 8, !tbaa !9
  switch i32 %5, label %23 [
    i32 1, label %6
    i32 2, label %10
  ]

6:                                                ; preds = %1
  %7 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 2
  %8 = load ptr, ptr %7, align 8, !tbaa !24
  call void @_ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(344) %8, ptr noundef %3)
  %9 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 3
  store i32 0, ptr %9, align 8, !tbaa !9
  br label %24

10:                                               ; preds = %1
  %11 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 5
  %12 = load ptr, ptr %11, align 8, !tbaa !25
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %15

14:                                               ; preds = %10
  br label %16

15:                                               ; preds = %10
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str, ptr noundef @.str.1, i32 noundef 69)
  br label %16

16:                                               ; preds = %15, %14
  %17 = phi i32 [ 0, %14 ], [ 0, %15 ]
  %18 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 5
  %19 = load ptr, ptr %18, align 8, !tbaa !25
  %20 = getelementptr inbounds %"class.sc_core::sc_event_timed", ptr %19, i32 0, i32 0
  store ptr null, ptr %20, align 8, !tbaa !26
  %21 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 5
  store ptr null, ptr %21, align 8, !tbaa !25
  %22 = getelementptr inbounds %"class.sc_core::sc_event", ptr %3, i32 0, i32 3
  store i32 0, ptr %22, align 8, !tbaa !9
  br label %24

23:                                               ; preds = %1
  br label %24

24:                                               ; preds = %23, %16, %6
  ret void
}

declare void @_ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) #1

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !14, i64 48}
!10 = !{!"_ZTSN7sc_core8sc_eventE", !11, i64 0, !6, i64 32, !6, i64 40, !14, i64 48, !15, i64 52, !6, i64 56, !16, i64 64, !16, i64 88, !20, i64 112, !20, i64 136}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !13, i64 8, !7, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!13 = !{!"long", !7, i64 0}
!14 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !7, i64 0}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!10, !6, i64 40}
!25 = !{!10, !6, i64 56}
!26 = !{!27, !6, i64 0}
!27 = !{!"_ZTSN7sc_core14sc_event_timedE", !6, i64 0, !28, i64 8}
!28 = !{!"_ZTSN7sc_core7sc_timeE", !29, i64 0}
!29 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str = external hidden unnamed_addr constant [13 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [84 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core8sc_event6cancelEv(ptr noundef nonnull align 8 dereferenceable(160) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 48
  %3 = load i32, ptr %2, align 8, !tbaa !5
  switch i32 %3, label %13 [
    i32 1, label %4
    i32 2, label %7
  ]

4:                                                ; preds = %1
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load ptr, ptr %5, align 8, !tbaa !23
  tail call void @_ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(344) %6, ptr noundef nonnull %0)
  br label %.sink.split

7:                                                ; preds = %1
  %8 = getelementptr inbounds i8, ptr %0, i64 56
  %9 = load ptr, ptr %8, align 8, !tbaa !24
  %.not = icmp eq ptr %9, null
  br i1 %.not, label %10, label %11

10:                                               ; preds = %7
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 69)
  %.pre = load ptr, ptr %8, align 8, !tbaa !24
  br label %11

11:                                               ; preds = %7, %10
  %12 = phi ptr [ %9, %7 ], [ %.pre, %10 ]
  store ptr null, ptr %12, align 8, !tbaa !25
  store ptr null, ptr %8, align 8, !tbaa !24
  br label %.sink.split

.sink.split:                                      ; preds = %4, %11
  store i32 0, ptr %2, align 8, !tbaa !5
  br label %13

13:                                               ; preds = %.sink.split, %1
  ret void
}

declare void @_ZN7sc_core13sc_simcontext18remove_delta_eventEPNS_8sc_eventE(ptr noundef nonnull align 8 dereferenceable(344), ptr noundef) local_unnamed_addr #1

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !13, i64 48}
!6 = !{!"_ZTSN7sc_core8sc_eventE", !7, i64 0, !9, i64 32, !9, i64 40, !13, i64 48, !14, i64 52, !9, i64 56, !15, i64 64, !15, i64 88, !19, i64 112, !19, i64 136}
!7 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !8, i64 0, !12, i64 8, !10, i64 16}
!8 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"long", !10, i64 0}
!13 = !{!"_ZTSN7sc_core8sc_event8notify_tE", !10, i64 0}
!14 = !{!"int", !10, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_method_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_method_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!23 = !{!6, !9, i64 40}
!24 = !{!6, !9, i64 56}
!25 = !{!26, !9, i64 0}
!26 = !{!"_ZTSN7sc_core14sc_event_timedE", !9, i64 0, !27, i64 8}
!27 = !{!"_ZTSN7sc_core7sc_timeE", !28, i64 0}
!28 = !{!"long long", !10, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass