; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib_ (BitFieldAnd64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [135 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [12 x i8], align 1
@.str.9 = external hidden unnamed_addr constant [87 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #0

declare i64 @RShiftU64(i64 noundef, i64 noundef) #0

declare i64 @LShiftU64(i64 noundef, i64 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i64 @BitFieldAnd64(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3) #2 {
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  store i64 %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !5
  store i64 %2, ptr %7, align 8, !tbaa !5
  store i64 %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  br label %11

11:                                               ; preds = %4
  %12 = call zeroext i8 @DebugAssertEnabled()
  %13 = icmp ne i8 %12, 0
  br i1 %13, label %14, label %19

14:                                               ; preds = %11
  %15 = load i64, ptr %7, align 8, !tbaa !5
  %16 = icmp ult i64 %15, 64
  br i1 %16, label %18, label %17

17:                                               ; preds = %14
  call void @DebugAssert(ptr noundef @.str, i64 noundef 861, ptr noundef @.str.7)
  br label %18

18:                                               ; preds = %17, %14
  br label %19

19:                                               ; preds = %18, %11
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  br label %22

22:                                               ; preds = %21
  %23 = call zeroext i8 @DebugAssertEnabled()
  %24 = icmp ne i8 %23, 0
  br i1 %24, label %25, label %31

25:                                               ; preds = %22
  %26 = load i64, ptr %6, align 8, !tbaa !5
  %27 = load i64, ptr %7, align 8, !tbaa !5
  %28 = icmp ule i64 %26, %27
  br i1 %28, label %30, label %29

29:                                               ; preds = %25
  call void @DebugAssert(ptr noundef @.str, i64 noundef 862, ptr noundef @.str.4)
  br label %30

30:                                               ; preds = %29, %25
  br label %31

31:                                               ; preds = %30, %22
  br label %32

32:                                               ; preds = %31
  br label %33

33:                                               ; preds = %32
  br label %34

34:                                               ; preds = %33
  %35 = call zeroext i8 @DebugAssertEnabled()
  %36 = icmp ne i8 %35, 0
  br i1 %36, label %37, label %52

37:                                               ; preds = %34
  %38 = load i64, ptr %8, align 8, !tbaa !5
  %39 = load i64, ptr %7, align 8, !tbaa !5
  %40 = load i64, ptr %6, align 8, !tbaa !5
  %41 = sub i64 %39, %40
  %42 = call i64 @RShiftU64(i64 noundef %38, i64 noundef %41)
  %43 = load i64, ptr %8, align 8, !tbaa !5
  %44 = load i64, ptr %7, align 8, !tbaa !5
  %45 = load i64, ptr %6, align 8, !tbaa !5
  %46 = sub i64 %44, %45
  %47 = call i64 @RShiftU64(i64 noundef %43, i64 noundef %46)
  %48 = and i64 %47, 1
  %49 = icmp eq i64 %42, %48
  br i1 %49, label %51, label %50

50:                                               ; preds = %37
  call void @DebugAssert(ptr noundef @.str, i64 noundef 869, ptr noundef @.str.9)
  br label %51

51:                                               ; preds = %50, %37
  br label %52

52:                                               ; preds = %51, %34
  br label %53

53:                                               ; preds = %52
  br label %54

54:                                               ; preds = %53
  %55 = load i64, ptr %8, align 8, !tbaa !5
  %56 = xor i64 %55, -1
  %57 = load i64, ptr %6, align 8, !tbaa !5
  %58 = call i64 @LShiftU64(i64 noundef %56, i64 noundef %57)
  store i64 %58, ptr %9, align 8, !tbaa !5
  %59 = load i64, ptr %7, align 8, !tbaa !5
  %60 = call i64 @LShiftU64(i64 noundef -2, i64 noundef %59)
  store i64 %60, ptr %10, align 8, !tbaa !5
  %61 = load i64, ptr %5, align 8, !tbaa !5
  %62 = load i64, ptr %9, align 8, !tbaa !5
  %63 = load i64, ptr %10, align 8, !tbaa !5
  %64 = xor i64 %63, -1
  %65 = and i64 %62, %64
  %66 = xor i64 %65, -1
  %67 = and i64 %61, %66
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  ret i64 %67
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [135 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [12 x i8], align 1
@.str.9 = external hidden unnamed_addr constant [87 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

declare i64 @RShiftU64(i64 noundef, i64 noundef) local_unnamed_addr #0

declare i64 @LShiftU64(i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i64 @BitFieldAnd64(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3) local_unnamed_addr #1 {
  %5 = tail call zeroext i8 @DebugAssertEnabled() #2
  %6 = icmp eq i8 %5, 0
  %7 = icmp ult i64 %2, 64
  %or.cond = or i1 %7, %6
  br i1 %or.cond, label %9, label %8

8:                                                ; preds = %4
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 861, ptr noundef nonnull @.str.7) #2
  br label %9

9:                                                ; preds = %4, %8
  %10 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not = icmp ne i8 %10, 0
  %.not16 = icmp ugt i64 %1, %2
  %or.cond19 = and i1 %.not16, %.not
  br i1 %or.cond19, label %11, label %12

11:                                               ; preds = %9
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 862, ptr noundef nonnull @.str.4) #2
  br label %12

12:                                               ; preds = %9, %11
  %13 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not17 = icmp eq i8 %13, 0
  br i1 %.not17, label %21, label %14

14:                                               ; preds = %12
  %15 = sub i64 %2, %1
  %16 = tail call i64 @RShiftU64(i64 noundef %3, i64 noundef %15) #2
  %17 = tail call i64 @RShiftU64(i64 noundef %3, i64 noundef %15) #2
  %18 = and i64 %17, 1
  %19 = icmp eq i64 %16, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %14
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 869, ptr noundef nonnull @.str.9) #2
  br label %21

21:                                               ; preds = %14, %20, %12
  %22 = xor i64 %3, -1
  %23 = tail call i64 @LShiftU64(i64 noundef %22, i64 noundef %1) #2
  %24 = tail call i64 @LShiftU64(i64 noundef -2, i64 noundef %2) #2
  %.not18 = xor i64 %23, -1
  %25 = or i64 %24, %.not18
  %26 = and i64 %25, %0
  ret i64 %26
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass