; LLVM IR from hoodoer/ENNEoS :: enneosEncoder/CInnovation.ll (ZN11CInnovation18CreateNeuronFromIDEi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SNeuronGene = type { i32, i32, i8, double, double, double }
%class.CInnovation = type { %"class.std::vector.5", i32, i32 }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl" }
%"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl" = type { %"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SInnovation, std::allocator<SInnovation>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SInnovation = type { i32, i32, i32, i32, i32, i32, double, double }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI11SInnovationSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11CInnovation18CreateNeuronFromIDEi(ptr dead_on_unwind noalias writable sret(%struct.SNeuronGene) align 8 %0, ptr noundef nonnull align 8 dereferenceable(32) %1, i32 noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %1, ptr %4, align 8, !tbaa !5
  store i32 %2, ptr %5, align 4, !tbaa !9
  %8 = load ptr, ptr %4, align 8
  call void @_ZN11SNeuronGeneC2E11neuron_typeiddb(ptr noundef nonnull align 8 dereferenceable(40) %0, i32 noundef 1, i32 noundef 0, double noundef 0.000000e+00, double noundef 0.000000e+00, i1 noundef zeroext false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %9

9:                                                ; preds = %55, %3
  %10 = load i32, ptr %6, align 4, !tbaa !9
  %11 = sext i32 %10 to i64
  %12 = getelementptr inbounds %class.CInnovation, ptr %8, i32 0, i32 0
  %13 = call noundef i64 @_ZNKSt6vectorI11SInnovationSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  %14 = icmp ult i64 %11, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %9
  store i32 2, ptr %7, align 4
  br label %58

16:                                               ; preds = %9
  %17 = getelementptr inbounds %class.CInnovation, ptr %8, i32 0, i32 0
  %18 = load i32, ptr %6, align 4, !tbaa !9
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %19) #3
  %21 = getelementptr inbounds %struct.SInnovation, ptr %20, i32 0, i32 4
  %22 = load i32, ptr %21, align 8, !tbaa !11
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = icmp eq i32 %22, %23
  br i1 %24, label %25, label %54

25:                                               ; preds = %16
  %26 = getelementptr inbounds %class.CInnovation, ptr %8, i32 0, i32 0
  %27 = load i32, ptr %6, align 4, !tbaa !9
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %28) #3
  %30 = getelementptr inbounds %struct.SInnovation, ptr %29, i32 0, i32 5
  %31 = load i32, ptr %30, align 4, !tbaa !16
  %32 = getelementptr inbounds %struct.SNeuronGene, ptr %0, i32 0, i32 1
  store i32 %31, ptr %32, align 4, !tbaa !17
  %33 = getelementptr inbounds %class.CInnovation, ptr %8, i32 0, i32 0
  %34 = load i32, ptr %6, align 4, !tbaa !9
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %35) #3
  %37 = getelementptr inbounds %struct.SInnovation, ptr %36, i32 0, i32 4
  %38 = load i32, ptr %37, align 8, !tbaa !11
  %39 = getelementptr inbounds %struct.SNeuronGene, ptr %0, i32 0, i32 0
  store i32 %38, ptr %39, align 8, !tbaa !20
  %40 = getelementptr inbounds %class.CInnovation, ptr %8, i32 0, i32 0
  %41 = load i32, ptr %6, align 4, !tbaa !9
  %42 = sext i32 %41 to i64
  %43 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %40, i64 noundef %42) #3
  %44 = getelementptr inbounds %struct.SInnovation, ptr %43, i32 0, i32 6
  %45 = load double, ptr %44, align 8, !tbaa !21
  %46 = getelementptr inbounds %struct.SNeuronGene, ptr %0, i32 0, i32 3
  store double %45, ptr %46, align 8, !tbaa !22
  %47 = getelementptr inbounds %class.CInnovation, ptr %8, i32 0, i32 0
  %48 = load i32, ptr %6, align 4, !tbaa !9
  %49 = sext i32 %48 to i64
  %50 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %47, i64 noundef %49) #3
  %51 = getelementptr inbounds %struct.SInnovation, ptr %50, i32 0, i32 7
  %52 = load double, ptr %51, align 8, !tbaa !23
  %53 = getelementptr inbounds %struct.SNeuronGene, ptr %0, i32 0, i32 4
  store double %52, ptr %53, align 8, !tbaa !24
  store i32 1, ptr %7, align 4
  br label %58

54:                                               ; preds = %16
  br label %55

55:                                               ; preds = %54
  %56 = load i32, ptr %6, align 4, !tbaa !9
  %57 = add nsw i32 %56, 1
  store i32 %57, ptr %6, align 4, !tbaa !9
  br label %9, !llvm.loop !25

58:                                               ; preds = %25, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %59 = load i32, ptr %7, align 4
  switch i32 %59, label %62 [
    i32 2, label %60
    i32 1, label %61
  ]

60:                                               ; preds = %58
  br label %61

61:                                               ; preds = %60, %58
  ret void

62:                                               ; preds = %58
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN11SNeuronGeneC2E11neuron_typeiddb(ptr noundef nonnull align 8 dereferenceable(40), i32 noundef, i32 noundef, double noundef, double noundef, i1 noundef zeroext) unnamed_addr #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"_ZTS11SInnovation", !13, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !14, i64 20, !15, i64 24, !15, i64 32}
!13 = !{!"_ZTS10innov_type", !7, i64 0}
!14 = !{!"_ZTS11neuron_type", !7, i64 0}
!15 = !{!"double", !7, i64 0}
!16 = !{!12, !14, i64 20}
!17 = !{!18, !14, i64 4}
!18 = !{!"_ZTS11SNeuronGene", !10, i64 0, !14, i64 4, !19, i64 8, !15, i64 16, !15, i64 24, !15, i64 32}
!19 = !{!"bool", !7, i64 0}
!20 = !{!18, !10, i64 0}
!21 = !{!12, !15, i64 24}
!22 = !{!18, !15, i64 16}
!23 = !{!12, !15, i64 32}
!24 = !{!18, !15, i64 24}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SNeuronGene = type { i32, i32, i8, double, double, double }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI11SInnovationSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN11CInnovation18CreateNeuronFromIDEi(ptr dead_on_unwind noalias nonnull writable sret(%struct.SNeuronGene) align 8 %0, ptr noundef nonnull align 8 dereferenceable(32) %1, i32 noundef %2) local_unnamed_addr #0 align 2 {
  tail call void @_ZN11SNeuronGeneC2E11neuron_typeiddb(ptr noundef nonnull align 8 dereferenceable(40) %0, i32 noundef 1, i32 noundef 0, double noundef 0.000000e+00, double noundef 0.000000e+00, i1 noundef zeroext false)
  %4 = tail call noundef i64 @_ZNKSt6vectorI11SInnovationSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #1
  %.not = icmp eq i64 %4, 0
  br i1 %.not, label %.loopexit, label %.lr.ph

5:                                                ; preds = %.lr.ph
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %6 = tail call noundef i64 @_ZNKSt6vectorI11SInnovationSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #1
  %7 = icmp ugt i64 %6, %indvars.iv.next
  br i1 %7, label %.lr.ph, label %.loopexit, !llvm.loop !5

.lr.ph:                                           ; preds = %3, %5
  %indvars.iv = phi i64 [ %indvars.iv.next, %5 ], [ 0, %3 ]
  %8 = tail call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %9 = getelementptr inbounds i8, ptr %8, i64 16
  %10 = load i32, ptr %9, align 8, !tbaa !7
  %11 = icmp eq i32 %10, %2
  br i1 %11, label %12, label %5

12:                                               ; preds = %.lr.ph
  %13 = tail call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %14 = getelementptr inbounds i8, ptr %13, i64 20
  %15 = load i32, ptr %14, align 4, !tbaa !15
  %16 = getelementptr inbounds i8, ptr %0, i64 4
  store i32 %15, ptr %16, align 4, !tbaa !16
  %17 = tail call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %18 = getelementptr inbounds i8, ptr %17, i64 16
  %19 = load i32, ptr %18, align 8, !tbaa !7
  store i32 %19, ptr %0, align 8, !tbaa !19
  %20 = tail call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %21 = getelementptr inbounds i8, ptr %20, i64 24
  %22 = load double, ptr %21, align 8, !tbaa !20
  %23 = getelementptr inbounds i8, ptr %0, i64 16
  store double %22, ptr %23, align 8, !tbaa !21
  %24 = tail call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorI11SInnovationSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %25 = getelementptr inbounds i8, ptr %24, i64 32
  %26 = load double, ptr %25, align 8, !tbaa !22
  %27 = getelementptr inbounds i8, ptr %0, i64 24
  store double %26, ptr %27, align 8, !tbaa !23
  br label %.loopexit

.loopexit:                                        ; preds = %5, %3, %12
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN11SNeuronGeneC2E11neuron_typeiddb(ptr noundef nonnull align 8 dereferenceable(40), i32 noundef, i32 noundef, double noundef, double noundef, i1 noundef zeroext) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !12, i64 16}
!8 = !{!"_ZTS11SInnovation", !9, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !13, i64 20, !14, i64 24, !14, i64 32}
!9 = !{!"_ZTS10innov_type", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"int", !10, i64 0}
!13 = !{!"_ZTS11neuron_type", !10, i64 0}
!14 = !{!"double", !10, i64 0}
!15 = !{!8, !13, i64 20}
!16 = !{!17, !13, i64 4}
!17 = !{!"_ZTS11SNeuronGene", !12, i64 0, !13, i64 4, !18, i64 8, !14, i64 16, !14, i64 24, !14, i64 32}
!18 = !{!"bool", !10, i64 0}
!19 = !{!17, !12, i64 0}
!20 = !{!8, !14, i64 24}
!21 = !{!17, !14, i64 16}
!22 = !{!8, !14, i64 32}
!23 = !{!17, !14, i64 24}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass