; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/tracing/vcd_trace/test08/test08.ll (ZN5proc15entryEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_logic" = type { i32 }
%struct.proc1 = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN5sc_dt10SC_LOGIC_XE = external global %"class.sc_dt::sc_logic", align 4
@_ZN5sc_dt10SC_LOGIC_ZE = external global %"class.sc_dt::sc_logic", align 4

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5proc15entryEv(ptr noundef nonnull align 8 dereferenceable(448) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  %5 = alloca float, align 4
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca float, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %9 = load ptr, ptr %2, align 8
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  br label %10

10:                                               ; preds = %10, %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  store i32 1023, ptr %3, align 4, !tbaa !9
  %11 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 2
  %12 = load ptr, ptr %11, align 8, !tbaa !11
  %13 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %12, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #2
  store i8 15, ptr %4, align 1, !tbaa !42
  %14 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 3
  %15 = load ptr, ptr %14, align 8, !tbaa !43
  %16 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %15, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store float -4.000000e+00, ptr %5, align 4, !tbaa !44
  %17 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 4
  %18 = load ptr, ptr %17, align 8, !tbaa !46
  %19 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %18, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  %20 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 5
  %21 = load ptr, ptr %20, align 8, !tbaa !47
  %22 = call noundef nonnull align 8 dereferenceable(216) ptr @_ZN7sc_core9sc_signalIN5sc_dt8sc_logicELNS_16sc_writer_policyE0EEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(216) %21, ptr noundef nonnull align 4 dereferenceable(4) @_ZN5sc_dt10SC_LOGIC_XE)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 10, ptr %6, align 4, !tbaa !9
  %23 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 2
  %24 = load ptr, ptr %23, align 8, !tbaa !11
  %25 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %24, ptr noundef nonnull align 4 dereferenceable(4) %6)
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  store i8 8, ptr %7, align 1, !tbaa !42
  %26 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 3
  %27 = load ptr, ptr %26, align 8, !tbaa !43
  %28 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %27, ptr noundef nonnull align 1 dereferenceable(1) %7)
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store float 0x408F41E060000000, ptr %8, align 4, !tbaa !44
  %29 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 4
  %30 = load ptr, ptr %29, align 8, !tbaa !46
  %31 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %30, ptr noundef nonnull align 4 dereferenceable(4) %8)
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %32 = getelementptr inbounds %struct.proc1, ptr %9, i32 0, i32 5
  %33 = load ptr, ptr %32, align 8, !tbaa !47
  %34 = call noundef nonnull align 8 dereferenceable(216) ptr @_ZN7sc_core9sc_signalIN5sc_dt8sc_logicELNS_16sc_writer_policyE0EEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(216) %33, ptr noundef nonnull align 4 dereferenceable(4) @_ZN5sc_dt10SC_LOGIC_ZE)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  br label %10, !llvm.loop !48
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(216) ptr @_ZN7sc_core9sc_signalIN5sc_dt8sc_logicELNS_16sc_writer_policyE0EEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(216), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 416}
!12 = !{!"_ZTS5proc1", !13, i64 0, !34, i64 232, !6, i64 416, !6, i64 424, !6, i64 432, !6, i64 440}
!13 = !{!"_ZTSN7sc_core9sc_moduleE", !14, i64 0, !26, i64 112, !27, i64 120, !29, i64 144, !31, i64 168, !33, i64 192, !6, i64 200, !10, i64 208, !6, i64 216, !6, i64 224}
!14 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !15, i64 16, !19, i64 40, !23, i64 64, !6, i64 96, !6, i64 104}
!15 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !28, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !30, i64 8, !6, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !32, i64 8, !6, i64 16}
!32 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!33 = !{!"bool", !7, i64 0}
!34 = !{!"_ZTSN7sc_core5sc_inIbEE", !35, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!35 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !36, i64 0}
!36 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !37, i64 0, !6, i64 120, !38, i64 128}
!37 = !{!"_ZTSN7sc_core12sc_port_baseE", !14, i64 0, !6, i64 112}
!38 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!7, !7, i64 0}
!43 = !{!12, !6, i64 424}
!44 = !{!45, !45, i64 0}
!45 = !{!"float", !7, i64 0}
!46 = !{!12, !6, i64 432}
!47 = !{!12, !6, i64 440}
!48 = distinct !{!48, !49}
!49 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_logic" = type { i32 }

@_ZN5sc_dt10SC_LOGIC_XE = external global %"class.sc_dt::sc_logic", align 4
@_ZN5sc_dt10SC_LOGIC_ZE = external global %"class.sc_dt::sc_logic", align 4

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN5proc15entryEv(ptr noundef nonnull align 8 dereferenceable(448) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca i32, align 4
  %3 = alloca i8, align 1
  %4 = alloca float, align 4
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca float, align 4
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %8 = getelementptr inbounds i8, ptr %0, i64 416
  %9 = getelementptr inbounds i8, ptr %0, i64 424
  %10 = getelementptr inbounds i8, ptr %0, i64 432
  %11 = getelementptr inbounds i8, ptr %0, i64 440
  br label %12

12:                                               ; preds = %12, %1
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #3
  store i32 1023, ptr %2, align 4, !tbaa !5
  %13 = load ptr, ptr %8, align 8, !tbaa !9
  %14 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %13, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  store i8 15, ptr %3, align 1, !tbaa !41
  %15 = load ptr, ptr %9, align 8, !tbaa !42
  %16 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %15, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #3
  store float -4.000000e+00, ptr %4, align 4, !tbaa !43
  %17 = load ptr, ptr %10, align 8, !tbaa !45
  %18 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %17, ptr noundef nonnull align 4 dereferenceable(4) %4)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #3
  %19 = load ptr, ptr %11, align 8, !tbaa !46
  %20 = call noundef nonnull align 8 dereferenceable(216) ptr @_ZN7sc_core9sc_signalIN5sc_dt8sc_logicELNS_16sc_writer_policyE0EEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(216) %19, ptr noundef nonnull align 4 dereferenceable(4) @_ZN5sc_dt10SC_LOGIC_XE)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #3
  store i32 10, ptr %5, align 4, !tbaa !5
  %21 = load ptr, ptr %8, align 8, !tbaa !9
  %22 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196) %21, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) #3
  store i8 8, ptr %6, align 1, !tbaa !41
  %23 = load ptr, ptr %9, align 8, !tbaa !42
  %24 = call noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193) %23, ptr noundef nonnull align 1 dereferenceable(1) %6)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #3
  store float 0x408F41E060000000, ptr %7, align 4, !tbaa !43
  %25 = load ptr, ptr %10, align 8, !tbaa !45
  %26 = call noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196) %25, ptr noundef nonnull align 4 dereferenceable(4) %7)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #3
  %27 = load ptr, ptr %11, align 8, !tbaa !46
  %28 = call noundef nonnull align 8 dereferenceable(216) ptr @_ZN7sc_core9sc_signalIN5sc_dt8sc_logicELNS_16sc_writer_policyE0EEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(216) %27, ptr noundef nonnull align 4 dereferenceable(4) @_ZN5sc_dt10SC_LOGIC_ZE)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  br label %12, !llvm.loop !47
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIiLNS_16sc_writer_policyE0EEaSERKi(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(193) ptr @_ZN7sc_core9sc_signalIcLNS_16sc_writer_policyE0EEaSERKc(ptr noundef nonnull align 8 dereferenceable(193), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(196) ptr @_ZN7sc_core9sc_signalIfLNS_16sc_writer_policyE0EEaSERKf(ptr noundef nonnull align 8 dereferenceable(196), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(216) ptr @_ZN7sc_core9sc_signalIN5sc_dt8sc_logicELNS_16sc_writer_policyE0EEaSERKS2_(ptr noundef nonnull align 8 dereferenceable(216), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 416}
!10 = !{!"_ZTS5proc1", !11, i64 0, !33, i64 232, !13, i64 416, !13, i64 424, !13, i64 432, !13, i64 440}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !25, i64 112, !26, i64 120, !28, i64 144, !30, i64 168, !32, i64 192, !13, i64 200, !6, i64 208, !13, i64 216, !13, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !13, i64 8, !14, i64 16, !18, i64 40, !22, i64 64, !13, i64 96, !13, i64 104}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !24, i64 8, !7, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!24 = !{!"long", !7, i64 0}
!25 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveE", !13, i64 0, !27, i64 8, !13, i64 16}
!27 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !13, i64 0, !29, i64 8, !13, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !13, i64 0, !31, i64 8, !13, i64 16}
!31 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!32 = !{!"bool", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !13, i64 152, !13, i64 160, !13, i64 168, !13, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !13, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !13, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!41 = !{!7, !7, i64 0}
!42 = !{!10, !13, i64 424}
!43 = !{!44, !44, i64 0}
!44 = !{!"float", !7, i64 0}
!45 = !{!10, !13, i64 432}
!46 = !{!10, !13, i64 440}
!47 = distinct !{!47, !48}
!48 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,PostOrderFunctionAttrsPass,SROAPass,TailCallElimPass