; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/kernel/sc_simcontext.ll (ZN7sc_core13sc_simcontextC2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }
%"class.sc_core::sc_simcontext" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"struct.sc_core::sc_curr_proc_info", ptr, i8, i32, %"class.std::vector.26", %"class.std::vector", %"class.std::vector.0", %"class.std::vector", ptr, %"class.std::vector.31", i8, ptr, ptr, ptr, %"class.sc_core::sc_time", %"class.sc_core::sc_time", ptr, i64, i64, i8, i8, i8, i8, i32, ptr, i8, i8, i32, i8, ptr, ptr }
%"struct.sc_core::sc_curr_proc_info" = type <{ ptr, i32, [4 x i8] }>
%"class.std::vector.26" = type { %"struct.std::_Vector_base.27" }
%"struct.std::_Vector_base.27" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_thread_process *, std::allocator<sc_core::sc_thread_process *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.31" = type { %"struct.std::_Vector_base.32" }
%"struct.std::_Vector_base.32" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_trace_file *, std::allocator<sc_core::sc_trace_file *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZN7sc_core12SC_ZERO_TIMEE = external global %"class.sc_core::sc_time", align 8

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext4initEv(ptr noundef nonnull align 8 dereferenceable(344)) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontextC2Ev(ptr noundef nonnull align 8 dereferenceable(344) %0) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  %6 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 0
  store ptr null, ptr %6, align 8, !tbaa !9
  %7 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 1
  store ptr null, ptr %7, align 8, !tbaa !35
  %8 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 2
  store ptr null, ptr %8, align 8, !tbaa !36
  %9 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 3
  store ptr null, ptr %9, align 8, !tbaa !37
  %10 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 4
  store ptr null, ptr %10, align 8, !tbaa !38
  %11 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 5
  store ptr null, ptr %11, align 8, !tbaa !39
  %12 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 6
  store ptr null, ptr %12, align 8, !tbaa !40
  %13 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 7
  store ptr null, ptr %13, align 8, !tbaa !41
  %14 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 8
  call void @_ZN7sc_core17sc_curr_proc_infoC2Ev(ptr noundef nonnull align 8 dereferenceable(12) %14)
  %15 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 9
  store ptr null, ptr %15, align 8, !tbaa !42
  %16 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 10
  store i8 0, ptr %16, align 8, !tbaa !43
  %17 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 11
  store i32 -1, ptr %17, align 4, !tbaa !44
  %18 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 12
  call void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #4
  %19 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 13
  call void @llvm.memset.p0.i64(ptr align 8 %19, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %19) #4
  %20 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 14
  call void @llvm.memset.p0.i64(ptr align 8 %20, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %20) #4
  %21 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 15
  call void @llvm.memset.p0.i64(ptr align 8 %21, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %21) #4
  %22 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 16
  store ptr null, ptr %22, align 8, !tbaa !45
  %23 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 17
  call void @llvm.memset.p0.i64(ptr align 8 %23, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %23) #4
  %24 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 18
  store i8 0, ptr %24, align 8, !tbaa !46
  %25 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 19
  store ptr null, ptr %25, align 8, !tbaa !47
  %26 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 20
  store ptr null, ptr %26, align 8, !tbaa !48
  %27 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 21
  store ptr null, ptr %27, align 8, !tbaa !49
  %28 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 22
  invoke void @_ZN7sc_core7sc_timeC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %28, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
          to label %29 unwind label %47

29:                                               ; preds = %1
  %30 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 23
  invoke void @_ZN7sc_core7sc_timeC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %30, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
          to label %31 unwind label %47

31:                                               ; preds = %29
  %32 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 25
  store i64 0, ptr %32, align 8, !tbaa !50
  %33 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 26
  store i64 0, ptr %33, align 8, !tbaa !51
  %34 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 27
  store i8 0, ptr %34, align 8, !tbaa !52
  %35 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 28
  store i8 0, ptr %35, align 1, !tbaa !53
  %36 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 29
  store i8 0, ptr %36, align 2, !tbaa !54
  %37 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 30
  store i8 0, ptr %37, align 1, !tbaa !55
  %38 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 31
  store i32 0, ptr %38, align 4, !tbaa !56
  %39 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 32
  store ptr null, ptr %39, align 8, !tbaa !57
  %40 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 33
  store i8 0, ptr %40, align 8, !tbaa !58
  %41 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 34
  store i8 0, ptr %41, align 1, !tbaa !59
  %42 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 35
  store i32 1, ptr %42, align 4, !tbaa !60
  %43 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 36
  store i8 0, ptr %43, align 8, !tbaa !61
  %44 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 37
  store ptr null, ptr %44, align 8, !tbaa !62
  %45 = getelementptr inbounds %"class.sc_core::sc_simcontext", ptr %5, i32 0, i32 38
  store ptr null, ptr %45, align 8, !tbaa !63
  invoke void @_ZN7sc_core13sc_simcontext4initEv(ptr noundef nonnull align 8 dereferenceable(344) %5)
          to label %46 unwind label %47

46:                                               ; preds = %31
  ret void

47:                                               ; preds = %31, %29, %1
  %48 = landingpad { ptr, i32 }
          cleanup
  %49 = extractvalue { ptr, i32 } %48, 0
  store ptr %49, ptr %3, align 8
  %50 = extractvalue { ptr, i32 } %48, 1
  store i32 %50, ptr %4, align 4
  call void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %23) #4
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %21) #4
  call void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %20) #4
  call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %19) #4
  call void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #4
  br label %51

51:                                               ; preds = %47
  %52 = load ptr, ptr %3, align 8
  %53 = load i32, ptr %4, align 4
  %54 = insertvalue { ptr, i32 } poison, ptr %52, 0
  %55 = insertvalue { ptr, i32 } %54, i32 %53, 1
  resume { ptr, i32 } %55
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core17sc_curr_proc_infoC2Ev(ptr noundef nonnull align 8 dereferenceable(12)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core7sc_timeC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTSN7sc_core13sc_simcontextE", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !11, i64 64, !6, i64 80, !13, i64 88, !14, i64 92, !15, i64 96, !19, i64 120, !23, i64 144, !19, i64 168, !6, i64 192, !27, i64 200, !13, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !31, i64 256, !31, i64 264, !6, i64 272, !32, i64 280, !32, i64 288, !13, i64 296, !13, i64 297, !13, i64 298, !13, i64 299, !33, i64 300, !6, i64 304, !13, i64 312, !13, i64 313, !34, i64 316, !13, i64 320, !6, i64 328, !6, i64 336}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !6, i64 0, !12, i64 8}
!12 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTSN7sc_core7sc_timeE", !32, i64 0}
!32 = !{!"long long", !7, i64 0}
!33 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !7, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_statusE", !7, i64 0}
!35 = !{!10, !6, i64 8}
!36 = !{!10, !6, i64 16}
!37 = !{!10, !6, i64 24}
!38 = !{!10, !6, i64 32}
!39 = !{!10, !6, i64 40}
!40 = !{!10, !6, i64 48}
!41 = !{!10, !6, i64 56}
!42 = !{!10, !6, i64 80}
!43 = !{!10, !13, i64 88}
!44 = !{!10, !14, i64 92}
!45 = !{!10, !6, i64 192}
!46 = !{!10, !13, i64 224}
!47 = !{!10, !6, i64 232}
!48 = !{!10, !6, i64 240}
!49 = !{!10, !6, i64 248}
!50 = !{!10, !32, i64 280}
!51 = !{!10, !32, i64 288}
!52 = !{!10, !13, i64 296}
!53 = !{!10, !13, i64 297}
!54 = !{!10, !13, i64 298}
!55 = !{!10, !13, i64 299}
!56 = !{!10, !33, i64 300}
!57 = !{!10, !6, i64 304}
!58 = !{!10, !13, i64 312}
!59 = !{!10, !13, i64 313}
!60 = !{!10, !34, i64 316}
!61 = !{!10, !13, i64 320}
!62 = !{!10, !6, i64 328}
!63 = !{!10, !6, i64 336}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_time" = type { i64 }

@_ZN7sc_core12SC_ZERO_TIMEE = external global %"class.sc_core::sc_time", align 8

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core13sc_simcontext4initEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core13sc_simcontextC2Ev(ptr noundef nonnull align 8 dereferenceable(344) %0) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 64
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(64) %0, i8 0, i64 64, i1 false)
  tail call void @_ZN7sc_core17sc_curr_proc_infoC2Ev(ptr noundef nonnull align 8 dereferenceable(12) %2)
  %3 = getelementptr inbounds i8, ptr %0, i64 80
  store ptr null, ptr %3, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 88
  store i8 0, ptr %4, align 8, !tbaa !34
  %5 = getelementptr inbounds i8, ptr %0, i64 92
  store i32 -1, ptr %5, align 4, !tbaa !35
  %6 = getelementptr inbounds i8, ptr %0, i64 96
  tail call void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #4
  %7 = getelementptr inbounds i8, ptr %0, i64 120
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %7, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #4
  %8 = getelementptr inbounds i8, ptr %0, i64 144
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %8, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  %9 = getelementptr inbounds i8, ptr %0, i64 168
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %9, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  %10 = getelementptr inbounds i8, ptr %0, i64 192
  %11 = getelementptr inbounds i8, ptr %0, i64 200
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %10, i8 0, i64 32, i1 false)
  tail call void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #4
  %12 = getelementptr inbounds i8, ptr %0, i64 224
  store i8 0, ptr %12, align 8, !tbaa !36
  %13 = getelementptr inbounds i8, ptr %0, i64 232
  %14 = getelementptr inbounds i8, ptr %0, i64 256
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %13, i8 0, i64 24, i1 false)
  tail call void @_ZN7sc_core7sc_timeC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %14, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  %15 = getelementptr inbounds i8, ptr %0, i64 264
  tail call void @_ZN7sc_core7sc_timeC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(8) %15, ptr noundef nonnull align 8 dereferenceable(8) @_ZN7sc_core12SC_ZERO_TIMEE)
  %16 = getelementptr inbounds i8, ptr %0, i64 280
  %17 = getelementptr inbounds i8, ptr %0, i64 316
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(34) %16, i8 0, i64 34, i1 false)
  store i32 1, ptr %17, align 4, !tbaa !37
  %18 = getelementptr inbounds i8, ptr %0, i64 320
  store i8 0, ptr %18, align 8, !tbaa !38
  %19 = getelementptr inbounds i8, ptr %0, i64 328
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %19, i8 0, i64 16, i1 false)
  invoke void @_ZN7sc_core13sc_simcontext4initEv(ptr noundef nonnull align 8 dereferenceable(344) %0)
          to label %20 unwind label %21

20:                                               ; preds = %1
  ret void

21:                                               ; preds = %1
  %22 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #4
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  tail call void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  tail call void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #4
  tail call void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #4
  resume { ptr, i32 } %22
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core17sc_curr_proc_infoC2Ev(ptr noundef nonnull align 8 dereferenceable(12)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7sc_core7sc_timeC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core8sc_eventESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core9sc_objectESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core17sc_thread_processESaIS2_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 80}
!6 = !{!"_ZTSN7sc_core13sc_simcontextE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !10, i64 64, !7, i64 80, !12, i64 88, !13, i64 92, !14, i64 96, !18, i64 120, !22, i64 144, !18, i64 168, !7, i64 192, !26, i64 200, !12, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !30, i64 256, !30, i64 264, !7, i64 272, !31, i64 280, !31, i64 288, !12, i64 296, !12, i64 297, !12, i64 298, !12, i64 299, !32, i64 300, !7, i64 304, !12, i64 312, !12, i64 313, !33, i64 316, !12, i64 320, !7, i64 328, !7, i64 336}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN7sc_core17sc_curr_proc_infoE", !7, i64 0, !11, i64 8}
!11 = !{!"_ZTSN7sc_core17sc_curr_proc_kindE", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTSSt6vectorIPN7sc_core17sc_thread_processESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core17sc_thread_processESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!26 = !{!"_ZTSSt6vectorIPN7sc_core13sc_trace_fileESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core13sc_trace_fileESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!30 = !{!"_ZTSN7sc_core7sc_timeE", !31, i64 0}
!31 = !{!"long long", !8, i64 0}
!32 = !{!"_ZTSN7sc_core13sc_simcontext16execution_phasesE", !8, i64 0}
!33 = !{!"_ZTSN7sc_core9sc_statusE", !8, i64 0}
!34 = !{!6, !12, i64 88}
!35 = !{!6, !13, i64 92}
!36 = !{!6, !12, i64 224}
!37 = !{!6, !33, i64 316}
!38 = !{!6, !12, i64 320}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass