; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/stars/star111004/star111004.ll (ZN15io_controller_m1PEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.io_controller_m = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_out", %"class.sc_core::sc_inout.20", %"class.sc_core::sc_out.28", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_out.38", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in.47", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_core::sc_signal.55", %"class.sc_dt::sc_uint", %"class.sc_dt::sc_uint", %"class.sc_core::sc_signal.55" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.13", ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_inout.20" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.28" = type { %"class.sc_core::sc_inout.20" }
%"class.sc_core::sc_out.38" = type { %"class.sc_core::sc_inout.39" }
%"class.sc_core::sc_inout.39" = type { %"class.sc_core::sc_port.40", ptr, ptr, ptr }
%"class.sc_core::sc_port.40" = type { %"class.sc_core::sc_port_b.41" }
%"class.sc_core::sc_port_b.41" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.42" }
%"class.std::vector.42" = type { %"struct.std::_Vector_base.43" }
%"struct.std::_Vector_base.43" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.29" = type { %"class.sc_core::sc_inout.30" }
%"class.sc_core::sc_inout.30" = type { %"class.sc_core::sc_port.31", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.31" = type { %"class.sc_core::sc_port_b.32" }
%"class.sc_core::sc_port_b.32" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.33" }
%"class.std::vector.33" = type { %"struct.std::_Vector_base.34" }
%"struct.std::_Vector_base.34" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.47" = type { %"class.sc_core::sc_port.48", ptr, ptr }
%"class.sc_core::sc_port.48" = type { %"class.sc_core::sc_port_b.49" }
%"class.sc_core::sc_port_b.49" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.50" }
%"class.std::vector.50" = type { %"struct.std::_Vector_base.51" }
%"struct.std::_Vector_base.51" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_signal" = type { %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, %"class.sc_dt::sc_uint", i64, %"class.sc_dt::sc_uint" }
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }
%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_core::sc_signal.55" = type { %"class.sc_core::sc_signal_inout_if.56", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if.56" = type { %"class.sc_core::sc_signal_in_if.57", %"class.sc_core::sc_signal_write_if.58" }
%"class.sc_core::sc_signal_in_if.57" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_signal_write_if.58" = type { %"class.sc_core::sc_interface" }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  br label %5

5:                                                ; preds = %10, %1
  %6 = getelementptr inbounds %struct.io_controller_m, ptr %4, i32 0, i32 27
  %7 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %6)
  %8 = load i8, ptr %7, align 1, !tbaa !9, !range !11, !noundef !12
  %9 = trunc i8 %8 to i1
  br i1 %9, label %10, label %11

10:                                               ; preds = %5
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %4)
  br label %5, !llvm.loop !13

11:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #2
  store i8 1, ptr %3, align 1, !tbaa !9
  %12 = getelementptr inbounds %struct.io_controller_m, ptr %4, i32 0, i32 27
  %13 = call noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %12, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #2
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15io_controller_m1PEv(ptr noundef nonnull align 8 dereferenceable(5288) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca i8, align 1
  %3 = getelementptr inbounds i8, ptr %0, i64 5064
  %4 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %3)
  %5 = load i8, ptr %4, align 1, !tbaa !5, !range !9, !noundef !10
  %6 = trunc nuw i8 %5 to i1
  br i1 %6, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %1, %.lr.ph
  tail call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %7 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224) %3)
  %8 = load i8, ptr %7, align 1, !tbaa !5, !range !9, !noundef !10
  %9 = trunc nuw i8 %8 to i1
  br i1 %9, label %.lr.ph, label %._crit_edge, !llvm.loop !11

._crit_edge:                                      ; preds = %.lr.ph, %1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #2
  store i8 1, ptr %2, align 1, !tbaa !5
  %10 = call noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224) %3, ptr noundef nonnull align 1 dereferenceable(1) %2)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #2
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(224)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(224) ptr @_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEaSERKb(ptr noundef nonnull align 8 dereferenceable(224), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass