; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/stars/star111657 (star111657)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_dt::sc_uint.56" = type { %"class.sc_dt::sc_uint_base" }
%struct.io_controller_m = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_out", %"class.sc_core::sc_out", %"class.sc_core::sc_inout.20", %"class.sc_core::sc_out.28", %"class.sc_core::sc_out.28", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_out.38", %"class.sc_core::sc_out.29", %"class.sc_core::sc_in.47", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", %"class.sc_dt::sc_uint", %"class.sc_dt::sc_uint", %"class.sc_core::sc_signal", %"class.sc_core::sc_signal", [400 x %"class.sc_dt::sc_uint"], [400 x %"class.sc_dt::sc_uint"] }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.13", ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<30>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_inout.20" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<32>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.28" = type { %"class.sc_core::sc_inout.20" }
%"class.sc_core::sc_out.38" = type { %"class.sc_core::sc_inout.39" }
%"class.sc_core::sc_inout.39" = type { %"class.sc_core::sc_port.40", ptr, ptr, ptr }
%"class.sc_core::sc_port.40" = type { %"class.sc_core::sc_port_b.41" }
%"class.sc_core::sc_port_b.41" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.42" }
%"class.std::vector.42" = type { %"struct.std::_Vector_base.43" }
%"struct.std::_Vector_base.43" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_inout_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.29" = type { %"class.sc_core::sc_inout.30" }
%"class.sc_core::sc_inout.30" = type { %"class.sc_core::sc_port.31", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.31" = type { %"class.sc_core::sc_port_b.32" }
%"class.sc_core::sc_port_b.32" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.33" }
%"class.std::vector.33" = type { %"struct.std::_Vector_base.34" }
%"struct.std::_Vector_base.34" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.47" = type { %"class.sc_core::sc_port.48", ptr, ptr }
%"class.sc_core::sc_port.48" = type { %"class.sc_core::sc_port_b.49" }
%"class.sc_core::sc_port_b.49" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.50" }
%"class.std::vector.50" = type { %"struct.std::_Vector_base.51" }
%"struct.std::_Vector_base.51" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *, std::allocator<sc_core::sc_signal_in_if<sc_dt::sc_uint<4>> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_signal" = type { %"class.sc_core::sc_signal_inout_if", %"class.sc_core::sc_prim_channel", %"struct.sc_core::sc_writer_policy_check", ptr, i8, i64, ptr, i8, ptr, ptr }
%"class.sc_core::sc_signal_inout_if" = type { %"class.sc_core::sc_signal_in_if", %"class.sc_core::sc_signal_write_if" }
%"class.sc_core::sc_signal_in_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_interface" = type { ptr }
%"class.sc_core::sc_signal_write_if" = type { %"class.sc_core::sc_interface" }
%"class.sc_core::sc_prim_channel" = type { %"class.sc_core::sc_object", ptr, ptr }
%"struct.sc_core::sc_writer_policy_check" = type { %"struct.sc_core::sc_writer_policy_check_port", %"struct.sc_core::sc_writer_policy_check_write" }
%"struct.sc_core::sc_writer_policy_check_port" = type { ptr }
%"struct.sc_core::sc_writer_policy_check_write" = type { i8, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15io_controller_m17read_from_memory0EN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_uint") align 8 %0, ptr noundef nonnull align 8 dereferenceable(24296) %1, ptr noundef %2) #1 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca %"class.sc_dt::sc_uint.56", align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca i8, align 1
  %13 = alloca i1, align 1
  %14 = alloca i8, align 1
  %15 = alloca %"class.sc_dt::sc_uint.56", align 8
  store ptr %0, ptr %4, align 8
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %16 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 24, ptr %7) #3
  %17 = call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %18 = lshr i64 %17, 2
  call void @_ZN5sc_dt7sc_uintILi30EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %18)
  %19 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 2
  %20 = invoke noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIN5sc_dt7sc_uintILi30EEEEaSERKS3_(ptr noundef nonnull align 8 dereferenceable(176) %19, ptr noundef nonnull align 8 dereferenceable(24) %7)
          to label %21 unwind label %36

21:                                               ; preds = %3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  store i8 0, ptr %10, align 1, !tbaa !9
  %22 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 7
  %23 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %22, ptr noundef nonnull align 1 dereferenceable(1) %10)
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #3
  store i8 0, ptr %11, align 1, !tbaa !9
  %24 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 9
  %25 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %24, ptr noundef nonnull align 1 dereferenceable(1) %11)
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %16)
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #3
  store i8 1, ptr %12, align 1, !tbaa !9
  %26 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 7
  %27 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %26, ptr noundef nonnull align 1 dereferenceable(1) %12)
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #3
  br label %28

28:                                               ; preds = %35, %21
  %29 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 11
  %30 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184) %29)
  %31 = load i8, ptr %30, align 1, !tbaa !9, !range !11, !noundef !12
  %32 = trunc i8 %31 to i1
  %33 = zext i1 %32 to i32
  %34 = icmp eq i32 %33, 1
  br i1 %34, label %35, label %40

35:                                               ; preds = %28
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %16)
  br label %28, !llvm.loop !13

36:                                               ; preds = %3
  %37 = landingpad { ptr, i32 }
          cleanup
  %38 = extractvalue { ptr, i32 } %37, 0
  store ptr %38, ptr %8, align 8
  %39 = extractvalue { ptr, i32 } %37, 1
  store i32 %39, ptr %9, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %7) #3
  br label %67

40:                                               ; preds = %28
  store i1 false, ptr %13, align 1
  %41 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 4
  %42 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core8sc_inoutIN5sc_dt7sc_uintILi32EEEE4readEv(ptr noundef nonnull align 8 dereferenceable(176) %41)
  call void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %42)
  call void @llvm.lifetime.start.p0(i64 1, ptr %14) #3
  store i8 1, ptr %14, align 1, !tbaa !9
  %43 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 9
  %44 = invoke noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %43, ptr noundef nonnull align 1 dereferenceable(1) %14)
          to label %45 unwind label %51

45:                                               ; preds = %40
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #3
  call void @llvm.lifetime.start.p0(i64 24, ptr %15) #3
  invoke void @_ZN5sc_dt7sc_uintILi30EEC2Ei(ptr noundef nonnull align 8 dereferenceable(24) %15, i32 noundef 0)
          to label %46 unwind label %55

46:                                               ; preds = %45
  %47 = getelementptr inbounds %struct.io_controller_m, ptr %16, i32 0, i32 2
  %48 = invoke noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIN5sc_dt7sc_uintILi30EEEEaSERKS3_(ptr noundef nonnull align 8 dereferenceable(176) %47, ptr noundef nonnull align 8 dereferenceable(24) %15)
          to label %49 unwind label %59

49:                                               ; preds = %46
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %15) #3
  store i1 true, ptr %13, align 1
  %50 = load i1, ptr %13, align 1
  br i1 %50, label %65, label %64

51:                                               ; preds = %40
  %52 = landingpad { ptr, i32 }
          cleanup
  %53 = extractvalue { ptr, i32 } %52, 0
  store ptr %53, ptr %8, align 8
  %54 = extractvalue { ptr, i32 } %52, 1
  store i32 %54, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #3
  br label %66

55:                                               ; preds = %45
  %56 = landingpad { ptr, i32 }
          cleanup
  %57 = extractvalue { ptr, i32 } %56, 0
  store ptr %57, ptr %8, align 8
  %58 = extractvalue { ptr, i32 } %56, 1
  store i32 %58, ptr %9, align 4
  br label %63

59:                                               ; preds = %46
  %60 = landingpad { ptr, i32 }
          cleanup
  %61 = extractvalue { ptr, i32 } %60, 0
  store ptr %61, ptr %8, align 8
  %62 = extractvalue { ptr, i32 } %60, 1
  store i32 %62, ptr %9, align 4
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  br label %63

63:                                               ; preds = %59, %55
  call void @llvm.lifetime.end.p0(i64 24, ptr %15) #3
  br label %66

64:                                               ; preds = %49
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  br label %65

65:                                               ; preds = %64, %49
  ret void

66:                                               ; preds = %63, %51
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  br label %67

67:                                               ; preds = %66, %36
  %68 = load ptr, ptr %8, align 8
  %69 = load i32, ptr %9, align 4
  %70 = insertvalue { ptr, i32 } poison, ptr %68, 0
  %71 = insertvalue { ptr, i32 } %70, i32 %69, 1
  resume { ptr, i32 } %71
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi30EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIN5sc_dt7sc_uintILi30EEEEaSERKS3_(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core8sc_inoutIN5sc_dt7sc_uintILi32EEEE4readEv(ptr noundef nonnull align 8 dereferenceable(176)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi30EEC2Ei(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_dt::sc_uint" = type { %"class.sc_dt::sc_uint_base" }
%"class.sc_dt::sc_uint_base" = type { %"class.sc_dt::sc_value_base", i64, i32, i32 }
%"class.sc_dt::sc_value_base" = type { ptr }
%"class.sc_dt::sc_uint.56" = type { %"class.sc_dt::sc_uint_base" }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15io_controller_m17read_from_memory0EN5sc_dt7sc_uintILi32EEE(ptr dead_on_unwind noalias writable sret(%"class.sc_dt::sc_uint") align 8 %0, ptr noundef nonnull align 8 dereferenceable(24296) %1, ptr noundef nonnull %2) local_unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca %"class.sc_dt::sc_uint.56", align 8
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca %"class.sc_dt::sc_uint.56", align 8
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %4) #3
  %10 = tail call noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %11 = lshr i64 %10, 2
  call void @_ZN5sc_dt7sc_uintILi30EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %11)
  %12 = getelementptr inbounds i8, ptr %1, i64 416
  %13 = invoke noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIN5sc_dt7sc_uintILi30EEEEaSERKS3_(ptr noundef nonnull align 8 dereferenceable(176) %12, ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %14 unwind label %27

14:                                               ; preds = %3
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %4) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #3
  store i8 0, ptr %5, align 1, !tbaa !5
  %15 = getelementptr inbounds i8, ptr %1, i64 1296
  %16 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %15, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) #3
  store i8 0, ptr %6, align 1, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %1, i64 1680
  %18 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %17, ptr noundef nonnull align 1 dereferenceable(1) %6)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %6) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %1)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %7) #3
  store i8 1, ptr %7, align 1, !tbaa !5
  %19 = call noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %15, ptr noundef nonnull align 1 dereferenceable(1) %7)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %7) #3
  %20 = getelementptr inbounds i8, ptr %1, i64 2064
  %21 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184) %20)
  %22 = load i8, ptr %21, align 1, !tbaa !5, !range !9, !noundef !10
  %23 = trunc nuw i8 %22 to i1
  br i1 %23, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %14, %.lr.ph
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %1)
  %24 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184) %20)
  %25 = load i8, ptr %24, align 1, !tbaa !5, !range !9, !noundef !10
  %26 = trunc nuw i8 %25 to i1
  br i1 %26, label %.lr.ph, label %._crit_edge, !llvm.loop !11

27:                                               ; preds = %3
  %28 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %4) #3
  br label %44

._crit_edge:                                      ; preds = %.lr.ph, %14
  %29 = getelementptr inbounds i8, ptr %1, i64 768
  %30 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core8sc_inoutIN5sc_dt7sc_uintILi32EEEE4readEv(ptr noundef nonnull align 8 dereferenceable(176) %29)
  call void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %30)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %8) #3
  store i8 1, ptr %8, align 1, !tbaa !5
  %31 = invoke noundef nonnull align 8 dereferenceable(192) ptr @_ZN7sc_core6sc_outIbEaSERKb(ptr noundef nonnull align 8 dereferenceable(192) %17, ptr noundef nonnull align 1 dereferenceable(1) %8)
          to label %32 unwind label %36

32:                                               ; preds = %._crit_edge
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %8) #3
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %9) #3
  invoke void @_ZN5sc_dt7sc_uintILi30EEC2Ei(ptr noundef nonnull align 8 dereferenceable(24) %9, i32 noundef 0)
          to label %33 unwind label %38

33:                                               ; preds = %32
  %34 = invoke noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIN5sc_dt7sc_uintILi30EEEEaSERKS3_(ptr noundef nonnull align 8 dereferenceable(176) %12, ptr noundef nonnull align 8 dereferenceable(24) %9)
          to label %35 unwind label %40

35:                                               ; preds = %33
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %9) #3
  ret void

36:                                               ; preds = %._crit_edge
  %37 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %8) #3
  br label %43

38:                                               ; preds = %32
  %39 = landingpad { ptr, i32 }
          cleanup
  br label %42

40:                                               ; preds = %33
  %41 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  br label %42

42:                                               ; preds = %40, %38
  %.pn = phi { ptr, i32 } [ %41, %40 ], [ %39, %38 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %9) #3
  br label %43

43:                                               ; preds = %42, %36
  %.pn.pn = phi { ptr, i32 } [ %.pn, %42 ], [ %37, %36 ]
  call void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  br label %44

44:                                               ; preds = %43, %27
  %.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn, %43 ], [ %28, %27 ]
  resume { ptr, i32 } %.pn.pn.pn
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK5sc_dt12sc_uint_basecvyEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi30EEC2Ey(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIN5sc_dt7sc_uintILi30EEEEaSERKS3_(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5sc_dt13sc_value_baseD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7sc_core8sc_inoutIN5sc_dt7sc_uintILi32EEEE4readEv(ptr noundef nonnull align 8 dereferenceable(176)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi32EEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5sc_dt7sc_uintILi30EEC2Ei(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #1 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass