; LLVM IR from gem5/gem5 :: ext/drampower/src (CAHelpers)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Data::CommandAnalysis" = type { %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", i64, %"class.std::vector", i64, i64, %"class.std::vector", i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, %"class.Data::MemorySpecification", i64, %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.13", %"class.std::vector.13", %"class.std::vector", i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i64, i64, %"class.std::vector", i64 }
%"class.Data::MemorySpecification" = type { ptr, %"class.std::__cxx11::basic_string", %"class.Data::MemoryType", [4 x i8], %"class.Data::MemArchitectureSpec", %"class.Data::MemTimingSpec", %"class.Data::MemPowerSpec", %"class.Data::Parametrisable" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.Data::MemoryType" = type { i32 }
%"class.Data::MemArchitectureSpec" = type <{ ptr, i64, i64, i64, i64, i64, i64, i64, i64, i8, i8, i8, [5 x i8], %"class.Data::Parametrisable" }>
%"class.Data::MemTimingSpec" = type { ptr, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, %"class.Data::Parametrisable" }
%"class.Data::MemPowerSpec" = type { ptr, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, %"class.Data::Parametrisable" }
%"class.Data::Parametrisable" = type { ptr, %"class.std::vector.3" }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::MemCommand, std::allocator<Data::MemCommand>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::CommandAnalysis::BankState, std::allocator<Data::CommandAnalysis::BankState>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_ZN4Data15CommandAnalysis16timeToCompletionENS_10MemCommand4cmdsE(ptr noundef nonnull align 8 dereferenceable(1392) %0, i32 noundef %1) #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i64, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %8 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #2
  store i64 0, ptr %5, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  %9 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %8, i32 0, i32 30
  %10 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %9, i32 0, i32 5
  store ptr %10, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  %11 = getelementptr inbounds %"class.Data::CommandAnalysis", ptr %8, i32 0, i32 30
  %12 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %11, i32 0, i32 4
  store ptr %12, ptr %7, align 8, !tbaa !5
  %13 = load i32, ptr %4, align 4, !tbaa !9
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %32

15:                                               ; preds = %2
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %16, i32 0, i32 16
  %18 = load i64, ptr %17, align 8, !tbaa !13
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %19, i32 0, i32 23
  %21 = load i64, ptr %20, align 8, !tbaa !16
  %22 = add nsw i64 %18, %21
  %23 = add nsw i64 %22, 1
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  %25 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %24, i32 0, i32 1
  %26 = load i64, ptr %25, align 8, !tbaa !17
  %27 = load ptr, ptr %7, align 8, !tbaa !5
  %28 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %27, i32 0, i32 4
  %29 = load i64, ptr %28, align 8, !tbaa !20
  %30 = sdiv i64 %26, %29
  %31 = add nsw i64 %23, %30
  store i64 %31, ptr %5, align 8, !tbaa !11
  br label %71

32:                                               ; preds = %2
  %33 = load i32, ptr %4, align 4, !tbaa !9
  %34 = icmp eq i32 %33, 2
  br i1 %34, label %35, label %51

35:                                               ; preds = %32
  %36 = load ptr, ptr %6, align 8, !tbaa !5
  %37 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %36, i32 0, i32 21
  %38 = load i64, ptr %37, align 8, !tbaa !21
  %39 = load ptr, ptr %7, align 8, !tbaa !5
  %40 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %39, i32 0, i32 1
  %41 = load i64, ptr %40, align 8, !tbaa !17
  %42 = load ptr, ptr %7, align 8, !tbaa !5
  %43 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %42, i32 0, i32 4
  %44 = load i64, ptr %43, align 8, !tbaa !20
  %45 = sdiv i64 %41, %44
  %46 = add nsw i64 %38, %45
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %47, i32 0, i32 25
  %49 = load i64, ptr %48, align 8, !tbaa !22
  %50 = add nsw i64 %46, %49
  store i64 %50, ptr %5, align 8, !tbaa !11
  br label %70

51:                                               ; preds = %32
  %52 = load i32, ptr %4, align 4, !tbaa !9
  %53 = icmp eq i32 %52, 0
  br i1 %53, label %54, label %58

54:                                               ; preds = %51
  %55 = load ptr, ptr %6, align 8, !tbaa !5
  %56 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %55, i32 0, i32 3
  %57 = load i64, ptr %56, align 8, !tbaa !23
  store i64 %57, ptr %5, align 8, !tbaa !11
  br label %69

58:                                               ; preds = %51
  %59 = load i32, ptr %4, align 4, !tbaa !9
  %60 = icmp eq i32 %59, 3
  br i1 %60, label %64, label %61

61:                                               ; preds = %58
  %62 = load i32, ptr %4, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 9
  br i1 %63, label %64, label %68

64:                                               ; preds = %61, %58
  %65 = load ptr, ptr %6, align 8, !tbaa !5
  %66 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %65, i32 0, i32 17
  %67 = load i64, ptr %66, align 8, !tbaa !24
  store i64 %67, ptr %5, align 8, !tbaa !11
  br label %68

68:                                               ; preds = %64, %61
  br label %69

69:                                               ; preds = %68, %54
  br label %70

70:                                               ; preds = %69, %35
  br label %71

71:                                               ; preds = %70, %15
  %72 = load i64, ptr %5, align 8, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #2
  ret i64 %72
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN4Data10MemCommand4cmdsE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !12, i64 128}
!14 = !{!"_ZTSN4Data13MemTimingSpecE", !15, i64 8, !12, i64 16, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !12, i64 64, !12, i64 72, !12, i64 80, !12, i64 88, !12, i64 96, !12, i64 104, !12, i64 112, !12, i64 120, !12, i64 128, !12, i64 136, !12, i64 144, !12, i64 152, !12, i64 160, !12, i64 168, !12, i64 176, !12, i64 184, !12, i64 192, !12, i64 200, !12, i64 208, !12, i64 216, !12, i64 224, !12, i64 232, !12, i64 240, !12, i64 248, !15, i64 256}
!15 = !{!"double", !7, i64 0}
!16 = !{!14, !12, i64 184}
!17 = !{!18, !12, i64 8}
!18 = !{!"_ZTSN4Data19MemArchitectureSpecE", !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !12, i64 64, !19, i64 72, !19, i64 73, !19, i64 74}
!19 = !{!"bool", !7, i64 0}
!20 = !{!18, !12, i64 32}
!21 = !{!14, !12, i64 168}
!22 = !{!14, !12, i64 200}
!23 = !{!14, !12, i64 24}
!24 = !{!14, !12, i64 136}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) uwtable
define dso_local noundef i64 @_ZN4Data15CommandAnalysis16timeToCompletionENS_10MemCommand4cmdsE(ptr nocapture noundef nonnull readonly align 8 dereferenceable(1392) %0, i32 noundef %1) local_unnamed_addr #0 align 2 {
  switch i32 %1, label %34 [
    i32 1, label %3
    i32 2, label %16
    i32 0, label %28
    i32 9, label %31
    i32 3, label %31
  ]

3:                                                ; preds = %2
  %4 = getelementptr inbounds i8, ptr %0, i64 624
  %5 = load i64, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 680
  %7 = load i64, ptr %6, align 8, !tbaa !11
  %8 = getelementptr inbounds i8, ptr %0, i64 392
  %9 = load i64, ptr %8, align 8, !tbaa !12
  %10 = getelementptr inbounds i8, ptr %0, i64 416
  %11 = load i64, ptr %10, align 8, !tbaa !15
  %12 = sdiv i64 %9, %11
  %13 = add i64 %5, 1
  %14 = add i64 %13, %7
  %15 = add nsw i64 %14, %12
  br label %34

16:                                               ; preds = %2
  %17 = getelementptr inbounds i8, ptr %0, i64 664
  %18 = load i64, ptr %17, align 8, !tbaa !16
  %19 = getelementptr inbounds i8, ptr %0, i64 392
  %20 = load i64, ptr %19, align 8, !tbaa !12
  %21 = getelementptr inbounds i8, ptr %0, i64 416
  %22 = load i64, ptr %21, align 8, !tbaa !15
  %23 = sdiv i64 %20, %22
  %24 = add nsw i64 %23, %18
  %25 = getelementptr inbounds i8, ptr %0, i64 696
  %26 = load i64, ptr %25, align 8, !tbaa !17
  %27 = add nsw i64 %24, %26
  br label %34

28:                                               ; preds = %2
  %29 = getelementptr inbounds i8, ptr %0, i64 520
  %30 = load i64, ptr %29, align 8, !tbaa !18
  br label %34

31:                                               ; preds = %2, %2
  %32 = getelementptr inbounds i8, ptr %0, i64 632
  %33 = load i64, ptr %32, align 8, !tbaa !19
  br label %34

34:                                               ; preds = %2, %16, %31, %28, %3
  %.0 = phi i64 [ %15, %3 ], [ %27, %16 ], [ %30, %28 ], [ %33, %31 ], [ 0, %2 ]
  ret i64 %.0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 128}
!6 = !{!"_ZTSN4Data13MemTimingSpecE", !7, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !7, i64 256}
!7 = !{!"double", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"long", !8, i64 0}
!11 = !{!6, !10, i64 184}
!12 = !{!13, !10, i64 8}
!13 = !{!"_ZTSN4Data19MemArchitectureSpecE", !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !14, i64 72, !14, i64 73, !14, i64 74}
!14 = !{!"bool", !8, i64 0}
!15 = !{!13, !10, i64 32}
!16 = !{!6, !10, i64 168}
!17 = !{!6, !10, i64 200}
!18 = !{!6, !10, i64 24}
!19 = !{!6, !10, i64 136}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass