; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/sim_tests/biquad/biquad2 (op_queue)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%struct.op_queue = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in.13", %"class.sc_core::sc_in", %"class.sc_core::sc_out", i32, ptr }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<float> *, std::allocator<sc_core::sc_signal_in_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<float> *, std::allocator<sc_core::sc_signal_inout_if<float> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZSt4cout = external global %"class.std::basic_ostream", align 8
@.str = external hidden unnamed_addr constant [50 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [39 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN8op_queue5entryEv(ptr noundef nonnull align 8 dereferenceable(960) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca i8, align 1
  %8 = alloca float, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %9 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #3
  store i8 1, ptr %6, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  store i8 0, ptr %7, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store float 0.000000e+00, ptr %8, align 4, !tbaa !11
  %10 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 4
  %11 = call noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIfEaSERKf(ptr noundef nonnull align 8 dereferenceable(176) %10, ptr noundef nonnull align 4 dereferenceable(4) %8)
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  store i32 0, ptr %5, align 4, !tbaa !13
  store i32 0, ptr %4, align 4, !tbaa !13
  br label %12

12:                                               ; preds = %70, %1
  br label %13

13:                                               ; preds = %12
  %14 = load i8, ptr %7, align 1, !tbaa !9, !range !15, !noundef !16
  %15 = trunc i8 %14 to i1
  br i1 %15, label %35, label %16

16:                                               ; preds = %13
  %17 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 2
  %18 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168) %17)
  %19 = load float, ptr %18, align 4, !tbaa !11
  %20 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 6
  %21 = load ptr, ptr %20, align 8, !tbaa !17
  %22 = load i32, ptr %4, align 4, !tbaa !13
  %23 = sext i32 %22 to i64
  %24 = getelementptr inbounds float, ptr %21, i64 %23
  store float %19, ptr %24, align 4, !tbaa !11
  %25 = load i32, ptr %4, align 4, !tbaa !13
  %26 = add nsw i32 %25, 1
  %27 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 5
  %28 = load i32, ptr %27, align 8, !tbaa !62
  %29 = srem i32 %26, %28
  store i32 %29, ptr %4, align 4, !tbaa !13
  store i8 0, ptr %6, align 1, !tbaa !9
  %30 = load i32, ptr %4, align 4, !tbaa !13
  %31 = load i32, ptr %5, align 4, !tbaa !13
  %32 = icmp eq i32 %30, %31
  br i1 %32, label %33, label %34

33:                                               ; preds = %16
  store i8 1, ptr %7, align 1, !tbaa !9
  br label %34

34:                                               ; preds = %33, %16
  br label %38

35:                                               ; preds = %13
  %36 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef @.str)
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %36, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  br label %38

38:                                               ; preds = %35, %34
  %39 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 3
  %40 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184) %39)
  %41 = load i8, ptr %40, align 1, !tbaa !9, !range !15, !noundef !16
  %42 = trunc i8 %41 to i1
  %43 = zext i1 %42 to i8
  store i8 %43, ptr %3, align 1, !tbaa !9
  %44 = load i8, ptr %3, align 1, !tbaa !9, !range !15, !noundef !16
  %45 = trunc i8 %44 to i1
  br i1 %45, label %46, label %70

46:                                               ; preds = %38
  %47 = load i8, ptr %6, align 1, !tbaa !9, !range !15, !noundef !16
  %48 = trunc i8 %47 to i1
  br i1 %48, label %66, label %49

49:                                               ; preds = %46
  %50 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 4
  %51 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 6
  %52 = load ptr, ptr %51, align 8, !tbaa !17
  %53 = load i32, ptr %5, align 4, !tbaa !13
  %54 = sext i32 %53 to i64
  %55 = getelementptr inbounds float, ptr %52, i64 %54
  call void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176) %50, ptr noundef nonnull align 4 dereferenceable(4) %55)
  %56 = load i32, ptr %5, align 4, !tbaa !13
  %57 = add nsw i32 %56, 1
  %58 = getelementptr inbounds %struct.op_queue, ptr %9, i32 0, i32 5
  %59 = load i32, ptr %58, align 8, !tbaa !62
  %60 = srem i32 %57, %59
  store i32 %60, ptr %5, align 4, !tbaa !13
  store i8 0, ptr %7, align 1, !tbaa !9
  %61 = load i32, ptr %5, align 4, !tbaa !13
  %62 = load i32, ptr %4, align 4, !tbaa !13
  %63 = icmp eq i32 %61, %62
  br i1 %63, label %64, label %65

64:                                               ; preds = %49
  store i8 1, ptr %6, align 1, !tbaa !9
  br label %65

65:                                               ; preds = %64, %49
  br label %69

66:                                               ; preds = %46
  %67 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef @.str.2)
  %68 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %67, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  br label %69

69:                                               ; preds = %66, %65
  br label %70

70:                                               ; preds = %69, %38
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %9)
  br label %12, !llvm.loop !63
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIfEaSERKf(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168)) #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"float", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = !{!18, !6, i64 952}
!18 = !{!"_ZTS8op_queue", !19, i64 0, !39, i64 232, !47, i64 416, !39, i64 584, !54, i64 768, !14, i64 944, !6, i64 952}
!19 = !{!"_ZTSN7sc_core9sc_moduleE", !20, i64 0, !32, i64 112, !33, i64 120, !35, i64 144, !37, i64 168, !10, i64 192, !6, i64 200, !14, i64 208, !6, i64 216, !6, i64 224}
!20 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !21, i64 16, !25, i64 40, !29, i64 64, !6, i64 96, !6, i64 104}
!21 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !30, i64 0, !31, i64 8, !7, i64 16}
!30 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!31 = !{!"long", !7, i64 0}
!32 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!33 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !34, i64 8, !6, i64 16}
!34 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!35 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !36, i64 8, !6, i64 16}
!36 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!37 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !38, i64 8, !6, i64 16}
!38 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!39 = !{!"_ZTSN7sc_core5sc_inIbEE", !40, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!40 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !41, i64 0}
!41 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !42, i64 0, !6, i64 120, !43, i64 128}
!42 = !{!"_ZTSN7sc_core12sc_port_baseE", !20, i64 0, !6, i64 112}
!43 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !44, i64 0}
!44 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!47 = !{!"_ZTSN7sc_core5sc_inIfEE", !48, i64 0, !6, i64 152, !6, i64 160}
!48 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIfEELi1ELNS_14sc_port_policyE0EEE", !49, i64 0}
!49 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIfEEEE", !42, i64 0, !6, i64 120, !50, i64 128}
!50 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE", !51, i64 0}
!51 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE", !52, i64 0}
!52 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE12_Vector_implE", !53, i64 0}
!53 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!54 = !{!"_ZTSN7sc_core6sc_outIfEE", !55, i64 0}
!55 = !{!"_ZTSN7sc_core8sc_inoutIfEE", !56, i64 0, !6, i64 152, !6, i64 160, !6, i64 168}
!56 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIfEELi1ELNS_14sc_port_policyE0EEE", !57, i64 0}
!57 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIfEEEE", !42, i64 0, !6, i64 120, !58, i64 128}
!58 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE", !59, i64 0}
!59 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE", !60, i64 0}
!60 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE12_Vector_implE", !61, i64 0}
!61 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!62 = !{!18, !14, i64 944}
!63 = distinct !{!63, !64}
!64 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }

@_ZSt4cout = external global %"class.std::basic_ostream", align 8
@.str = external hidden unnamed_addr constant [50 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [39 x i8], align 1

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN8op_queue5entryEv(ptr noundef nonnull align 8 dereferenceable(960) %0) local_unnamed_addr #0 align 2 {
  %2 = alloca float, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #4
  store float 0.000000e+00, ptr %2, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 768
  %4 = call noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIfEaSERKf(ptr noundef nonnull align 8 dereferenceable(176) %3, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #4
  %5 = getelementptr inbounds i8, ptr %0, i64 416
  %6 = getelementptr inbounds i8, ptr %0, i64 952
  %7 = getelementptr inbounds i8, ptr %0, i64 944
  %8 = getelementptr inbounds i8, ptr %0, i64 584
  br label %9

9:                                                ; preds = %39, %1
  %.016 = phi i32 [ 0, %1 ], [ %.11726, %39 ]
  %.014 = phi i32 [ 0, %1 ], [ %.115, %39 ]
  %.011 = phi i1 [ true, %1 ], [ %.213, %39 ]
  %.0 = phi i1 [ false, %1 ], [ %.2, %39 ]
  br i1 %.0, label %10, label %.thread

10:                                               ; preds = %9
  %11 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef nonnull @.str)
  %12 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %11, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %13 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184) %8)
  %14 = load i8, ptr %13, align 1, !tbaa !9, !range !11, !noundef !12
  %15 = trunc nuw i8 %14 to i1
  br i1 %15, label %28, label %39

.thread:                                          ; preds = %9
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168) %5)
  %17 = load float, ptr %16, align 4, !tbaa !5
  %18 = load ptr, ptr %6, align 8, !tbaa !13
  %19 = sext i32 %.016 to i64
  %20 = getelementptr inbounds float, ptr %18, i64 %19
  store float %17, ptr %20, align 4, !tbaa !5
  %21 = add nsw i32 %.016, 1
  %22 = load i32, ptr %7, align 8, !tbaa !60
  %23 = srem i32 %21, %22
  %24 = icmp eq i32 %23, %.014
  %25 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184) %8)
  %26 = load i8, ptr %25, align 1, !tbaa !9, !range !11, !noundef !12
  %27 = trunc nuw i8 %26 to i1
  br i1 %27, label %.thread30, label %39

28:                                               ; preds = %10
  br i1 %.011, label %36, label %.thread30

.thread30:                                        ; preds = %.thread, %28
  %.1172734 = phi i32 [ %.016, %28 ], [ %23, %.thread ]
  %29 = load ptr, ptr %6, align 8, !tbaa !13
  %30 = sext i32 %.014 to i64
  %31 = getelementptr inbounds float, ptr %29, i64 %30
  call void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176) %3, ptr noundef nonnull align 4 dereferenceable(4) %31)
  %32 = add nsw i32 %.014, 1
  %33 = load i32, ptr %7, align 8, !tbaa !60
  %34 = srem i32 %32, %33
  %35 = icmp eq i32 %34, %.1172734
  br label %39

36:                                               ; preds = %28
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, ptr noundef nonnull @.str.2)
  %38 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %37, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  br label %39

39:                                               ; preds = %.thread, %.thread30, %36, %10
  %.11726 = phi i32 [ %.016, %36 ], [ %.016, %10 ], [ %.1172734, %.thread30 ], [ %23, %.thread ]
  %.115 = phi i32 [ %.014, %36 ], [ %.014, %10 ], [ %34, %.thread30 ], [ %.014, %.thread ]
  %.213 = phi i1 [ true, %36 ], [ %.011, %10 ], [ %35, %.thread30 ], [ false, %.thread ]
  %.2 = phi i1 [ true, %36 ], [ true, %10 ], [ false, %.thread30 ], [ %24, %.thread ]
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  br label %9, !llvm.loop !61
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(176) ptr @_ZN7sc_core6sc_outIfEaSERKf(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIfE4readEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #3

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbE4readEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIfE5writeERKf(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!14, !17, i64 952}
!14 = !{!"_ZTS8op_queue", !15, i64 0, !37, i64 232, !45, i64 416, !37, i64 584, !52, i64 768, !36, i64 944, !17, i64 952}
!15 = !{!"_ZTSN7sc_core9sc_moduleE", !16, i64 0, !29, i64 112, !30, i64 120, !32, i64 144, !34, i64 168, !10, i64 192, !17, i64 200, !36, i64 208, !17, i64 216, !17, i64 224}
!16 = !{!"_ZTSN7sc_core9sc_objectE", !17, i64 8, !18, i64 16, !22, i64 40, !26, i64 64, !17, i64 96, !17, i64 104}
!17 = !{!"any pointer", !7, i64 0}
!18 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!22 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !27, i64 0, !28, i64 8, !7, i64 16}
!27 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !17, i64 0}
!28 = !{!"long", !7, i64 0}
!29 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!30 = !{!"_ZTSN7sc_core12sc_sensitiveE", !17, i64 0, !31, i64 8, !17, i64 16}
!31 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!32 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !17, i64 0, !33, i64 8, !17, i64 16}
!33 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!34 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !17, i64 0, !35, i64 8, !17, i64 16}
!35 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!36 = !{!"int", !7, i64 0}
!37 = !{!"_ZTSN7sc_core5sc_inIbEE", !38, i64 0, !17, i64 152, !17, i64 160, !17, i64 168, !17, i64 176}
!38 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !39, i64 0}
!39 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !40, i64 0, !17, i64 120, !41, i64 128}
!40 = !{!"_ZTSN7sc_core12sc_port_baseE", !16, i64 0, !17, i64 112}
!41 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!45 = !{!"_ZTSN7sc_core5sc_inIfEE", !46, i64 0, !17, i64 152, !17, i64 160}
!46 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIfEELi1ELNS_14sc_port_policyE0EEE", !47, i64 0}
!47 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIfEEEE", !40, i64 0, !17, i64 120, !48, i64 128}
!48 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE", !49, i64 0}
!49 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE", !50, i64 0}
!50 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE12_Vector_implE", !51, i64 0}
!51 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIfEESaIS3_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!52 = !{!"_ZTSN7sc_core6sc_outIfEE", !53, i64 0}
!53 = !{!"_ZTSN7sc_core8sc_inoutIfEE", !54, i64 0, !17, i64 152, !17, i64 160, !17, i64 168}
!54 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIfEELi1ELNS_14sc_port_policyE0EEE", !55, i64 0}
!55 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIfEEEE", !40, i64 0, !17, i64 120, !56, i64 128}
!56 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE", !57, i64 0}
!57 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE", !58, i64 0}
!58 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE12_Vector_implE", !59, i64 0}
!59 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIfEESaIS3_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!60 = !{!14, !36, i64 944}
!61 = distinct !{!61, !62}
!62 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass