; LLVM IR from gem5/gem5 :: ext/systemc/src/sysc/communication (sc_port)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.sc_core::sc_port_registry" = type { i32, %"class.std::vector.48", ptr }
%"class.std::vector.48" = type { %"struct.std::_Vector_base.49" }
%"struct.std::_Vector_base.49" = type { %"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_port_base *, std::allocator<sc_core::sc_port_base *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@_ZN7sc_core18SC_ID_INSERT_PORT_E = external constant [0 x i8], align 1
@.str.11 = external hidden unnamed_addr constant [17 x i8], align 1
@_ZN7sc_core26SC_ID_PORT_OUTSIDE_MODULE_E = external constant [0 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef, ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core16sc_port_registry6insertEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(40) %0, ptr noundef %1) #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  %7 = call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %8 = call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %7)
  br i1 %8, label %9, label %11

9:                                                ; preds = %2
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %10, ptr noundef @_ZN7sc_core18SC_ID_INSERT_PORT_E, ptr noundef @.str.4)
  br label %11

11:                                               ; preds = %9, %2
  %12 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %6, i32 0, i32 2
  %13 = load ptr, ptr %12, align 8, !tbaa !9
  %14 = call noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(344) %13)
  br i1 %14, label %15, label %17

15:                                               ; preds = %11
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %16, ptr noundef @_ZN7sc_core18SC_ID_INSERT_PORT_E, ptr noundef @.str.11)
  br label %17

17:                                               ; preds = %15, %11
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  %18 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %6, i32 0, i32 2
  %19 = load ptr, ptr %18, align 8, !tbaa !9
  %20 = call noundef ptr @_ZNK7sc_core13sc_simcontext14hierarchy_currEv(ptr noundef nonnull align 8 dereferenceable(344) %19)
  store ptr %20, ptr %5, align 8, !tbaa !5
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %23, label %25

23:                                               ; preds = %17
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %24, ptr noundef @_ZN7sc_core26SC_ID_PORT_OUTSIDE_MODULE_E, ptr noundef null)
  br label %25

25:                                               ; preds = %23, %17
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = call noundef i32 @_ZN7sc_core9sc_module11append_portEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(232) %26, ptr noundef %27)
  %29 = getelementptr inbounds %"class.sc_core::sc_port_registry", ptr %6, i32 0, i32 1
  call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE9push_backERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %29, ptr noundef nonnull align 8 dereferenceable(8) %4)
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(344)) #2 align 2

declare noundef ptr @_ZNK7sc_core13sc_simcontext14hierarchy_currEv(ptr noundef nonnull align 8 dereferenceable(344)) #4

declare noundef i32 @_ZN7sc_core9sc_module11append_portEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(232), ptr noundef) #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE9push_backERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 32}
!10 = !{!"_ZTSN7sc_core16sc_port_registryE", !11, i64 0, !12, i64 8, !6, i64 32}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@_ZN7sc_core18SC_ID_INSERT_PORT_E = external constant [0 x i8], align 1
@.str.11 = external hidden unnamed_addr constant [17 x i8], align 1
@_ZN7sc_core26SC_ID_PORT_OUTSIDE_MODULE_E = external constant [0 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef, ptr noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7sc_core16sc_port_registry6insertEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(40) %0, ptr noundef %1) local_unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  store ptr %1, ptr %3, align 8, !tbaa !5
  %4 = tail call noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv()
  %5 = tail call noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef %4)
  br i1 %5, label %6, label %7

6:                                                ; preds = %2
  tail call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %1, ptr noundef nonnull @_ZN7sc_core18SC_ID_INSERT_PORT_E, ptr noundef nonnull @.str.4)
  br label %7

7:                                                ; preds = %6, %2
  %8 = getelementptr inbounds i8, ptr %0, i64 32
  %9 = load ptr, ptr %8, align 8, !tbaa !9
  %10 = tail call noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(344) %9)
  br i1 %10, label %11, label %12

11:                                               ; preds = %7
  tail call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %1, ptr noundef nonnull @_ZN7sc_core18SC_ID_INSERT_PORT_E, ptr noundef nonnull @.str.11)
  br label %12

12:                                               ; preds = %11, %7
  %13 = load ptr, ptr %8, align 8, !tbaa !9
  %14 = tail call noundef ptr @_ZNK7sc_core13sc_simcontext14hierarchy_currEv(ptr noundef nonnull align 8 dereferenceable(344) %13)
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %12
  tail call void @_ZNK7sc_core12sc_port_base12report_errorEPKcS2_(ptr noundef nonnull align 8 dereferenceable(120) %1, ptr noundef nonnull @_ZN7sc_core26SC_ID_PORT_OUTSIDE_MODULE_E, ptr noundef null)
  br label %17

17:                                               ; preds = %16, %12
  %18 = tail call noundef i32 @_ZN7sc_core9sc_module11append_portEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(232) %14, ptr noundef %1)
  %19 = getelementptr inbounds i8, ptr %0, i64 8
  call void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE9push_backERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %19, ptr noundef nonnull align 8 dereferenceable(8) %3)
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN7sc_core13sc_is_runningEPKNS_13sc_simcontextE(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef ptr @_ZN7sc_core22sc_get_curr_simcontextEv() local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK7sc_core13sc_simcontext16elaboration_doneEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #1 align 2

declare noundef ptr @_ZNK7sc_core13sc_simcontext14hierarchy_currEv(ptr noundef nonnull align 8 dereferenceable(344)) local_unnamed_addr #3

declare noundef i32 @_ZN7sc_core9sc_module11append_portEPNS_12sc_port_baseE(ptr noundef nonnull align 8 dereferenceable(232), ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE9push_backERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 32}
!10 = !{!"_ZTSN7sc_core16sc_port_registryE", !11, i64 0, !12, i64 8, !6, i64 32}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIPN7sc_core12sc_port_baseESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core12sc_port_baseESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,TailCallElimPass