; LLVM IR from thalium/icebox :: third_party/virtualbox/src/VBox/Devices/EFI/Firmware/MdePkg/Library (PciCf8BitFieldAndThenOr16)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @SaveAndDisableInterrupts() #0

declare i32 @IoRead32(i64 noundef) #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @PciCf8BitFieldAndThenOr16(i64 noundef %0, i64 noundef %1, i64 noundef %2, i16 noundef zeroext %3, i16 noundef zeroext %4) #2 {
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i8, align 1
  %12 = alloca i32, align 4
  %13 = alloca i16, align 2
  store i64 %0, ptr %6, align 8, !tbaa !5
  store i64 %1, ptr %7, align 8, !tbaa !5
  store i64 %2, ptr %8, align 8, !tbaa !5
  store i16 %3, ptr %9, align 2, !tbaa !9
  store i16 %4, ptr %10, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %13) #3
  br label %14

14:                                               ; preds = %5
  %15 = call zeroext i8 @DebugAssertEnabled()
  %16 = icmp ne i8 %15, 0
  br i1 %16, label %17, label %23

17:                                               ; preds = %14
  %18 = load i64, ptr %6, align 8, !tbaa !5
  %19 = and i64 %18, -268431615
  %20 = icmp eq i64 %19, 0
  br i1 %20, label %22, label %21

21:                                               ; preds = %17
  call void @DebugAssert(ptr noundef @.str, i64 noundef 1071, ptr noundef @.str.2)
  br label %22

22:                                               ; preds = %21, %17
  br label %23

23:                                               ; preds = %22, %14
  br label %24

24:                                               ; preds = %23
  br label %25

25:                                               ; preds = %24
  %26 = call zeroext i8 @SaveAndDisableInterrupts()
  store i8 %26, ptr %11, align 1, !tbaa !11
  %27 = call i32 @IoRead32(i64 noundef 3320)
  store i32 %27, ptr %12, align 4, !tbaa !12
  %28 = load i64, ptr %6, align 8, !tbaa !5
  %29 = lshr i64 %28, 4
  %30 = and i64 %29, 16776960
  %31 = load i64, ptr %6, align 8, !tbaa !5
  %32 = and i64 %31, 252
  %33 = or i64 %30, %32
  %34 = or i64 %33, 2147483648
  %35 = trunc i64 %34 to i32
  %36 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %35)
  %37 = load i64, ptr %6, align 8, !tbaa !5
  %38 = and i64 %37, 2
  %39 = trunc i64 %38 to i16
  %40 = zext i16 %39 to i32
  %41 = add nsw i32 3324, %40
  %42 = sext i32 %41 to i64
  %43 = load i64, ptr %7, align 8, !tbaa !5
  %44 = load i64, ptr %8, align 8, !tbaa !5
  %45 = load i16, ptr %9, align 2, !tbaa !9
  %46 = load i16, ptr %10, align 2, !tbaa !9
  %47 = call zeroext i16 @IoBitFieldAndThenOr16(i64 noundef %42, i64 noundef %43, i64 noundef %44, i16 noundef zeroext %45, i16 noundef zeroext %46)
  store i16 %47, ptr %13, align 2, !tbaa !9
  %48 = load i32, ptr %12, align 4, !tbaa !12
  %49 = call i32 @IoWrite32(i64 noundef 3320, i32 noundef %48)
  %50 = load i8, ptr %11, align 1, !tbaa !11
  %51 = call zeroext i8 @SetInterruptState(i8 noundef zeroext %50)
  %52 = load i16, ptr %13, align 2, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 2, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #3
  ret i16 %52
}

declare zeroext i16 @IoBitFieldAndThenOr16(i64 noundef, i64 noundef, i64 noundef, i16 noundef zeroext, i16 noundef zeroext) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [142 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [38 x i8], align 1

declare zeroext i8 @DebugAssertEnabled() local_unnamed_addr #0

declare void @DebugAssert(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

declare zeroext i8 @SaveAndDisableInterrupts() local_unnamed_addr #0

declare i32 @IoRead32(i64 noundef) local_unnamed_addr #0

declare i32 @IoWrite32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare zeroext i8 @SetInterruptState(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @PciCf8BitFieldAndThenOr16(i64 noundef %0, i64 noundef %1, i64 noundef %2, i16 noundef zeroext %3, i16 noundef zeroext %4) local_unnamed_addr #1 {
  %6 = tail call zeroext i8 @DebugAssertEnabled() #2
  %.not = icmp eq i8 %6, 0
  %7 = and i64 %0, -268431615
  %8 = icmp eq i64 %7, 0
  %or.cond = or i1 %8, %.not
  br i1 %or.cond, label %10, label %9

9:                                                ; preds = %5
  tail call void @DebugAssert(ptr noundef nonnull @.str, i64 noundef 1071, ptr noundef nonnull @.str.2) #2
  br label %10

10:                                               ; preds = %9, %5
  %11 = tail call zeroext i8 @SaveAndDisableInterrupts() #2
  %12 = tail call i32 @IoRead32(i64 noundef 3320) #2
  %13 = lshr i64 %0, 4
  %14 = and i64 %13, 16776960
  %15 = and i64 %0, 252
  %16 = or disjoint i64 %14, %15
  %17 = trunc nuw nsw i64 %16 to i32
  %18 = or disjoint i32 %17, -2147483648
  %19 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %18) #2
  %20 = and i64 %0, 2
  %21 = or disjoint i64 %20, 3324
  %22 = tail call zeroext i16 @IoBitFieldAndThenOr16(i64 noundef %21, i64 noundef %1, i64 noundef %2, i16 noundef zeroext %3, i16 noundef zeroext %4) #2
  %23 = tail call i32 @IoWrite32(i64 noundef 3320, i32 noundef %12) #2
  %24 = tail call zeroext i8 @SetInterruptState(i8 noundef zeroext %11) #2
  ret i16 %22
}

declare zeroext i16 @IoBitFieldAndThenOr16(i64 noundef, i64 noundef, i64 noundef, i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass