; LLVM IR from gem5/gem5 :: ext/drampower/src (MemoryPowerModel)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Data::MemBankWiseParams" = type <{ %"class.std::vector.23", i64, i64, i8, i8, [6 x i8] }>
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef double @_ZN4Data16MemoryPowerModel15engy_sref_banksEdddddddddddRKNS_17MemBankWiseParamsEjl(double noundef %0, double noundef %1, double noundef %2, double noundef %3, double noundef %4, double noundef %5, double noundef %6, double noundef %7, double noundef %8, double noundef %9, double noundef %10, ptr noundef nonnull align 8 dereferenceable(42) %11, i32 noundef %12, i64 noundef %13) #2 align 2 {
  %15 = alloca double, align 8
  %16 = alloca double, align 8
  %17 = alloca double, align 8
  %18 = alloca double, align 8
  %19 = alloca double, align 8
  %20 = alloca double, align 8
  %21 = alloca double, align 8
  %22 = alloca double, align 8
  %23 = alloca double, align 8
  %24 = alloca double, align 8
  %25 = alloca double, align 8
  %26 = alloca ptr, align 8
  %27 = alloca i32, align 4
  %28 = alloca i64, align 8
  %29 = alloca double, align 8
  %30 = alloca double, align 8
  %31 = alloca double, align 8
  %32 = alloca double, align 8
  store double %0, ptr %15, align 8, !tbaa !5
  store double %1, ptr %16, align 8, !tbaa !5
  store double %2, ptr %17, align 8, !tbaa !5
  store double %3, ptr %18, align 8, !tbaa !5
  store double %4, ptr %19, align 8, !tbaa !5
  store double %5, ptr %20, align 8, !tbaa !5
  store double %6, ptr %21, align 8, !tbaa !5
  store double %7, ptr %22, align 8, !tbaa !5
  store double %8, ptr %23, align 8, !tbaa !5
  store double %9, ptr %24, align 8, !tbaa !5
  store double %10, ptr %25, align 8, !tbaa !5
  store ptr %11, ptr %26, align 8, !tbaa !9
  store i32 %12, ptr %27, align 4, !tbaa !11
  store i64 %13, ptr %28, align 8, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 8, ptr %29) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %30) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %31) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %32) #4
  %33 = load ptr, ptr %26, align 8, !tbaa !9
  %34 = getelementptr inbounds %"class.Data::MemBankWiseParams", ptr %33, i32 0, i32 4
  %35 = load i8, ptr %34, align 1, !tbaa !15, !range !22, !noundef !23
  %36 = trunc i8 %35 to i1
  br i1 %36, label %37, label %90

37:                                               ; preds = %14
  %38 = load double, ptr %17, align 8, !tbaa !5
  %39 = load double, ptr %16, align 8, !tbaa !5
  %40 = fsub double %38, %39
  %41 = load double, ptr %20, align 8, !tbaa !5
  %42 = load double, ptr %22, align 8, !tbaa !5
  %43 = fadd double %41, %42
  %44 = load double, ptr %21, align 8, !tbaa !5
  %45 = fadd double %43, %44
  %46 = load double, ptr %23, align 8, !tbaa !5
  %47 = fadd double %45, %46
  %48 = fmul double %40, %47
  %49 = load double, ptr %18, align 8, !tbaa !5
  %50 = fmul double %48, %49
  %51 = load double, ptr %24, align 8, !tbaa !5
  %52 = fmul double %50, %51
  %53 = load i64, ptr %28, align 8, !tbaa !13
  %54 = sitofp i64 %53 to double
  %55 = fdiv double %52, %54
  store double %55, ptr %32, align 8, !tbaa !5
  %56 = load ptr, ptr %26, align 8, !tbaa !9
  %57 = load i32, ptr %27, align 4, !tbaa !11
  %58 = call noundef zeroext i1 @_ZNK4Data17MemBankWiseParams18isBankActiveInPasrEj(ptr noundef nonnull align 8 dereferenceable(42) %56, i32 noundef %57)
  br i1 %58, label %59, label %84

59:                                               ; preds = %37
  %60 = load ptr, ptr %26, align 8, !tbaa !9
  %61 = getelementptr inbounds %"class.Data::MemBankWiseParams", ptr %60, i32 0, i32 2
  %62 = load i64, ptr %61, align 8, !tbaa !24
  %63 = sub nsw i64 100, %62
  %64 = sitofp i64 %63 to double
  %65 = load i64, ptr %28, align 8, !tbaa !13
  %66 = sitofp i64 %65 to double
  %67 = fmul double 1.000000e+02, %66
  %68 = fdiv double %64, %67
  %69 = load double, ptr %15, align 8, !tbaa !5
  %70 = fmul double %68, %69
  store double %70, ptr %30, align 8, !tbaa !5
  %71 = load double, ptr %18, align 8, !tbaa !5
  %72 = load double, ptr %30, align 8, !tbaa !5
  %73 = fmul double %71, %72
  %74 = load double, ptr %19, align 8, !tbaa !5
  %75 = fmul double %73, %74
  store double %75, ptr %31, align 8, !tbaa !5
  %76 = load double, ptr %32, align 8, !tbaa !5
  %77 = load double, ptr %31, align 8, !tbaa !5
  %78 = fadd double %76, %77
  %79 = load double, ptr %25, align 8, !tbaa !5
  %80 = load i64, ptr %28, align 8, !tbaa !13
  %81 = sitofp i64 %80 to double
  %82 = fdiv double %79, %81
  %83 = fadd double %78, %82
  store double %83, ptr %29, align 8, !tbaa !5
  br label %89

84:                                               ; preds = %37
  %85 = load double, ptr %25, align 8, !tbaa !5
  %86 = load i64, ptr %28, align 8, !tbaa !13
  %87 = sitofp i64 %86 to double
  %88 = fdiv double %85, %87
  store double %88, ptr %29, align 8, !tbaa !5
  br label %89

89:                                               ; preds = %84, %59
  br label %112

90:                                               ; preds = %14
  %91 = load double, ptr %15, align 8, !tbaa !5
  %92 = load double, ptr %19, align 8, !tbaa !5
  %93 = load double, ptr %17, align 8, !tbaa !5
  %94 = load double, ptr %16, align 8, !tbaa !5
  %95 = fsub double %93, %94
  %96 = load double, ptr %20, align 8, !tbaa !5
  %97 = load double, ptr %22, align 8, !tbaa !5
  %98 = fadd double %96, %97
  %99 = load double, ptr %21, align 8, !tbaa !5
  %100 = fadd double %98, %99
  %101 = load double, ptr %23, align 8, !tbaa !5
  %102 = fadd double %100, %101
  %103 = fmul double %95, %102
  %104 = call double @llvm.fmuladd.f64(double %91, double %92, double %103)
  %105 = load double, ptr %18, align 8, !tbaa !5
  %106 = fmul double %104, %105
  %107 = load double, ptr %24, align 8, !tbaa !5
  %108 = fmul double %106, %107
  %109 = load i64, ptr %28, align 8, !tbaa !13
  %110 = sitofp i64 %109 to double
  %111 = fdiv double %108, %110
  store double %111, ptr %29, align 8, !tbaa !5
  br label %112

112:                                              ; preds = %90, %89
  %113 = load double, ptr %29, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %32) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %31) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %30) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %29) #4
  ret double %113
}

declare noundef zeroext i1 @_ZNK4Data17MemBankWiseParams18isBankActiveInPasrEj(ptr noundef nonnull align 8 dereferenceable(42), i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!16, !21, i64 41}
!16 = !{!"_ZTSN4Data17MemBankWiseParamsE", !17, i64 0, !14, i64 24, !14, i64 32, !21, i64 40, !21, i64 41}
!17 = !{!"_ZTSSt6vectorIjSaIjEE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!21 = !{!"bool", !7, i64 0}
!22 = !{i8 0, i8 2}
!23 = !{}
!24 = !{!16, !14, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef double @_ZN4Data16MemoryPowerModel15engy_sref_banksEdddddddddddRKNS_17MemBankWiseParamsEjl(double noundef %0, double noundef %1, double noundef %2, double noundef %3, double noundef %4, double noundef %5, double noundef %6, double noundef %7, double noundef %8, double noundef %9, double noundef %10, ptr noundef nonnull align 8 dereferenceable(42) %11, i32 noundef %12, i64 noundef %13) local_unnamed_addr #1 align 2 {
  %15 = getelementptr inbounds i8, ptr %11, i64 41
  %16 = load i8, ptr %15, align 1, !tbaa !5, !range !16, !noundef !17
  %17 = trunc nuw i8 %16 to i1
  br i1 %17, label %18, label %49

18:                                               ; preds = %14
  %19 = sitofp i64 %13 to double
  %20 = tail call noundef zeroext i1 @_ZNK4Data17MemBankWiseParams18isBankActiveInPasrEj(ptr noundef nonnull align 8 dereferenceable(42) %11, i32 noundef %12)
  br i1 %20, label %21, label %47

21:                                               ; preds = %18
  %22 = fsub double %2, %1
  %23 = fadd double %5, %7
  %24 = fadd double %23, %6
  %25 = fadd double %24, %8
  %26 = fmul double %22, %25
  %27 = fmul double %26, %3
  %28 = fmul double %27, %9
  %29 = getelementptr inbounds i8, ptr %11, i64 32
  %30 = load i64, ptr %29, align 8, !tbaa !18
  %31 = sub nsw i64 100, %30
  %32 = sitofp i64 %31 to double
  %33 = fmul double %19, 1.000000e+02
  %34 = fdiv double %32, %33
  %35 = fmul double %34, %0
  %36 = fmul double %35, %3
  %37 = fmul double %36, %4
  %38 = insertelement <2 x double> poison, double %10, i64 0
  %39 = insertelement <2 x double> %38, double %28, i64 1
  %40 = insertelement <2 x double> poison, double %19, i64 0
  %41 = shufflevector <2 x double> %40, <2 x double> poison, <2 x i32> zeroinitializer
  %42 = fdiv <2 x double> %39, %41
  %43 = extractelement <2 x double> %42, i64 1
  %44 = fadd double %43, %37
  %45 = extractelement <2 x double> %42, i64 0
  %46 = fadd double %45, %44
  br label %60

47:                                               ; preds = %18
  %48 = fdiv double %10, %19
  br label %60

49:                                               ; preds = %14
  %50 = fsub double %2, %1
  %51 = fadd double %5, %7
  %52 = fadd double %51, %6
  %53 = fadd double %52, %8
  %54 = fmul double %50, %53
  %55 = tail call double @llvm.fmuladd.f64(double %0, double %4, double %54)
  %56 = fmul double %55, %3
  %57 = fmul double %56, %9
  %58 = sitofp i64 %13 to double
  %59 = fdiv double %57, %58
  br label %60

60:                                               ; preds = %21, %47, %49
  %.0 = phi double [ %46, %21 ], [ %48, %47 ], [ %59, %49 ]
  ret double %.0
}

declare noundef zeroext i1 @_ZNK4Data17MemBankWiseParams18isBankActiveInPasrEj(ptr noundef nonnull align 8 dereferenceable(42), i32 noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !15, i64 41}
!6 = !{!"_ZTSN4Data17MemBankWiseParamsE", !7, i64 0, !14, i64 24, !14, i64 32, !15, i64 40, !15, i64 41}
!7 = !{!"_ZTSSt6vectorIjSaIjEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"long", !12, i64 0}
!15 = !{!"bool", !12, i64 0}
!16 = !{i8 0, i8 2}
!17 = !{}
!18 = !{!6, !14, i64 32}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass