; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/misc/sim_tests/popc/popc.ll (ZN5proc25entryEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.proc2 = type <{ %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_in.13", %"class.sc_core::sc_out", %"class.sc_core::sc_out.28", i32, i32, i32, [4 x i8] }>
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_in.13" = type { %"class.sc_core::sc_port.14", ptr, ptr }
%"class.sc_core::sc_port.14" = type { %"class.sc_core::sc_port_b.15" }
%"class.sc_core::sc_port_b.15" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.16" }
%"class.std::vector.16" = type { %"struct.std::_Vector_base.17" }
%"struct.std::_Vector_base.17" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<int> *, std::allocator<sc_core::sc_signal_in_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.21", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.21" = type { %"class.sc_core::sc_port_b.22" }
%"class.sc_core::sc_port_b.22" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.23" }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out.28" = type { %"class.sc_core::sc_inout.29" }
%"class.sc_core::sc_inout.29" = type { %"class.sc_core::sc_port.30", ptr, ptr, ptr }
%"class.sc_core::sc_port.30" = type { %"class.sc_core::sc_port_b.31" }
%"class.sc_core::sc_port_b.31" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.32" }
%"class.std::vector.32" = type { %"struct.std::_Vector_base.33" }
%"struct.std::_Vector_base.33" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<int> *, std::allocator<sc_core::sc_signal_inout_if<int> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiE4readEv(ptr noundef nonnull align 8 dereferenceable(168)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5proc25entryEv(ptr noundef nonnull align 8 dereferenceable(1332) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8
  %7 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 9
  store i32 0, ptr %7, align 8, !tbaa !9
  %8 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #2
  store i8 0, ptr %3, align 1, !tbaa !64
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %8, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %9

9:                                                ; preds = %53, %1
  br label %10

10:                                               ; preds = %11, %9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %11

11:                                               ; preds = %10
  %12 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 3
  %13 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %12)
  %14 = load i8, ptr %13, align 1, !tbaa !64, !range !65, !noundef !66
  %15 = trunc i8 %14 to i1
  %16 = zext i1 %15 to i32
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %10, label %18, !llvm.loop !67

18:                                               ; preds = %11
  %19 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 4
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiE4readEv(ptr noundef nonnull align 8 dereferenceable(168) %19)
  %21 = load i32, ptr %20, align 4, !tbaa !69
  %22 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 8
  store i32 %21, ptr %22, align 4, !tbaa !70
  %23 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 7
  store i32 0, ptr %23, align 8, !tbaa !71
  br label %24

24:                                               ; preds = %28, %18
  %25 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 8
  %26 = load i32, ptr %25, align 4, !tbaa !70
  %27 = icmp ne i32 %26, 0
  br i1 %27, label %28, label %38

28:                                               ; preds = %24
  %29 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 7
  %30 = load i32, ptr %29, align 8, !tbaa !71
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %29, align 8, !tbaa !71
  %32 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 8
  %33 = load i32, ptr %32, align 4, !tbaa !70
  %34 = sub nsw i32 %33, 1
  %35 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 8
  %36 = load i32, ptr %35, align 4, !tbaa !70
  %37 = and i32 %36, %34
  store i32 %37, ptr %35, align 4, !tbaa !70
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %24, !llvm.loop !72

38:                                               ; preds = %24
  %39 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 9
  %40 = load i32, ptr %39, align 8, !tbaa !9
  %41 = add nsw i32 %40, 1
  store i32 %41, ptr %39, align 8, !tbaa !9
  %42 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 6
  %43 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 7
  call void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176) %42, ptr noundef nonnull align 4 dereferenceable(4) %43)
  %44 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 5
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #2
  store i8 1, ptr %4, align 1, !tbaa !64
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %44, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #2
  br label %45

45:                                               ; preds = %46, %38
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %6)
  br label %46

46:                                               ; preds = %45
  %47 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 3
  %48 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %47)
  %49 = load i8, ptr %48, align 1, !tbaa !64, !range !65, !noundef !66
  %50 = trunc i8 %49 to i1
  %51 = zext i1 %50 to i32
  %52 = icmp eq i32 %51, 1
  br i1 %52, label %45, label %53, !llvm.loop !73

53:                                               ; preds = %46
  %54 = getelementptr inbounds %struct.proc2, ptr %6, i32 0, i32 5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  store i8 0, ptr %5, align 1, !tbaa !64
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %54, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  br label %9, !llvm.loop !74
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !32, i64 1328}
!10 = !{!"_ZTS5proc2", !11, i64 0, !33, i64 232, !33, i64 416, !33, i64 600, !41, i64 784, !48, i64 952, !56, i64 1144, !32, i64 1320, !32, i64 1324, !32, i64 1328}
!11 = !{!"_ZTSN7sc_core9sc_moduleE", !12, i64 0, !24, i64 112, !25, i64 120, !27, i64 144, !29, i64 168, !31, i64 192, !6, i64 200, !32, i64 208, !6, i64 216, !6, i64 224}
!12 = !{!"_ZTSN7sc_core9sc_objectE", !6, i64 8, !13, i64 16, !17, i64 40, !21, i64 64, !6, i64 96, !6, i64 104}
!13 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !23, i64 8, !7, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!23 = !{!"long", !7, i64 0}
!24 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveE", !6, i64 0, !26, i64 8, !6, i64 16}
!26 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !7, i64 0}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !6, i64 0, !28, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !7, i64 0}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !6, i64 0, !30, i64 8, !6, i64 16}
!30 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !7, i64 0}
!31 = !{!"bool", !7, i64 0}
!32 = !{!"int", !7, i64 0}
!33 = !{!"_ZTSN7sc_core5sc_inIbEE", !34, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176}
!34 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !35, i64 0}
!35 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !36, i64 0, !6, i64 120, !37, i64 128}
!36 = !{!"_ZTSN7sc_core12sc_port_baseE", !12, i64 0, !6, i64 112}
!37 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = !{!"_ZTSN7sc_core5sc_inIiEE", !42, i64 0, !6, i64 152, !6, i64 160}
!42 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIiEELi1ELNS_14sc_port_policyE0EEE", !43, i64 0}
!43 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIiEEEE", !36, i64 0, !6, i64 120, !44, i64 128}
!44 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !45, i64 0}
!45 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE12_Vector_implE", !47, i64 0}
!47 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!48 = !{!"_ZTSN7sc_core6sc_outIbEE", !49, i64 0}
!49 = !{!"_ZTSN7sc_core8sc_inoutIbEE", !50, i64 0, !6, i64 152, !6, i64 160, !6, i64 168, !6, i64 176, !6, i64 184}
!50 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIbEELi1ELNS_14sc_port_policyE0EEE", !51, i64 0}
!51 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIbEEEE", !36, i64 0, !6, i64 120, !52, i64 128}
!52 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE", !53, i64 0}
!53 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE", !54, i64 0}
!54 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE12_Vector_implE", !55, i64 0}
!55 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!56 = !{!"_ZTSN7sc_core6sc_outIiEE", !57, i64 0}
!57 = !{!"_ZTSN7sc_core8sc_inoutIiEE", !58, i64 0, !6, i64 152, !6, i64 160, !6, i64 168}
!58 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIiEELi1ELNS_14sc_port_policyE0EEE", !59, i64 0}
!59 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIiEEEE", !36, i64 0, !6, i64 120, !60, i64 128}
!60 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !61, i64 0}
!61 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !62, i64 0}
!62 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE12_Vector_implE", !63, i64 0}
!63 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!64 = !{!31, !31, i64 0}
!65 = !{i8 0, i8 2}
!66 = !{}
!67 = distinct !{!67, !68}
!68 = !{!"llvm.loop.mustprogress"}
!69 = !{!32, !32, i64 0}
!70 = !{!10, !32, i64 1324}
!71 = !{!10, !32, i64 1320}
!72 = distinct !{!72, !68}
!73 = distinct !{!73, !68}
!74 = distinct !{!74, !68}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiE4readEv(ptr noundef nonnull align 8 dereferenceable(168)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress noreturn uwtable
define dso_local void @_ZN5proc25entryEv(ptr noundef nonnull align 8 dereferenceable(1332) %0) local_unnamed_addr #2 align 2 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = getelementptr inbounds i8, ptr %0, i64 1328
  store i32 0, ptr %5, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 952
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  store i8 0, ptr %2, align 1, !tbaa !63
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 1 dereferenceable(1) %2)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %7 = getelementptr inbounds i8, ptr %0, i64 600
  %8 = getelementptr inbounds i8, ptr %0, i64 784
  %9 = getelementptr inbounds i8, ptr %0, i64 1324
  %10 = getelementptr inbounds i8, ptr %0, i64 1320
  %11 = getelementptr inbounds i8, ptr %0, i64 1144
  br label %12

12:                                               ; preds = %.backedge, %1
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %13 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %7)
  %14 = load i8, ptr %13, align 1, !tbaa !63, !range !64, !noundef !65
  %15 = icmp eq i8 %14, 0
  br i1 %15, label %.backedge, label %16

.backedge:                                        ; preds = %12, %30
  br label %12, !llvm.loop !66

16:                                               ; preds = %12
  %17 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNK7sc_core5sc_inIiE4readEv(ptr noundef nonnull align 8 dereferenceable(168) %8)
  %18 = load i32, ptr %17, align 4, !tbaa !68
  store i32 %18, ptr %9, align 4, !tbaa !69
  store i32 0, ptr %10, align 8, !tbaa !70
  %.not1 = icmp eq i32 %18, 0
  br i1 %.not1, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %16, %.lr.ph
  %19 = phi i32 [ %.pr, %.lr.ph ], [ %18, %16 ]
  %20 = load i32, ptr %10, align 8, !tbaa !70
  %21 = add nsw i32 %20, 1
  store i32 %21, ptr %10, align 8, !tbaa !70
  %22 = add nsw i32 %19, -1
  %23 = and i32 %22, %19
  store i32 %23, ptr %9, align 4, !tbaa !69
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %.pr = load i32, ptr %9, align 4, !tbaa !69
  %.not = icmp eq i32 %.pr, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph, !llvm.loop !71

._crit_edge:                                      ; preds = %.lr.ph, %16
  %24 = load i32, ptr %5, align 8, !tbaa !5
  %25 = add nsw i32 %24, 1
  store i32 %25, ptr %5, align 8, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIiE5writeERKi(ptr noundef nonnull align 8 dereferenceable(176) %11, ptr noundef nonnull align 4 dereferenceable(4) %10)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  store i8 1, ptr %3, align 1, !tbaa !63
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  br label %26

26:                                               ; preds = %26, %._crit_edge
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %27 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %7)
  %28 = load i8, ptr %27, align 1, !tbaa !63, !range !64, !noundef !65
  %29 = trunc nuw i8 %28 to i1
  br i1 %29, label %26, label %30, !llvm.loop !72

30:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  store i8 0, ptr %4, align 1, !tbaa !63
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %6, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  br label %.backedge
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress noreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !31, i64 1328}
!6 = !{!"_ZTS5proc2", !7, i64 0, !32, i64 232, !32, i64 416, !32, i64 600, !40, i64 784, !47, i64 952, !55, i64 1144, !31, i64 1320, !31, i64 1324, !31, i64 1328}
!7 = !{!"_ZTSN7sc_core9sc_moduleE", !8, i64 0, !23, i64 112, !24, i64 120, !26, i64 144, !28, i64 168, !30, i64 192, !9, i64 200, !31, i64 208, !9, i64 216, !9, i64 224}
!8 = !{!"_ZTSN7sc_core9sc_objectE", !9, i64 8, !12, i64 16, !16, i64 40, !20, i64 64, !9, i64 96, !9, i64 104}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIPN7sc_core8sc_eventESaIS2_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core8sc_eventESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!16 = !{!"_ZTSSt6vectorIPN7sc_core9sc_objectESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core9sc_objectESaIS2_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !22, i64 8, !10, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!22 = !{!"long", !10, i64 0}
!23 = !{!"_ZTSN7sc_core15sc_process_hostE"}
!24 = !{!"_ZTSN7sc_core12sc_sensitiveE", !9, i64 0, !25, i64 8, !9, i64 16}
!25 = !{!"_ZTSN7sc_core12sc_sensitiveUt_E", !10, i64 0}
!26 = !{!"_ZTSN7sc_core16sc_sensitive_posE", !9, i64 0, !27, i64 8, !9, i64 16}
!27 = !{!"_ZTSN7sc_core16sc_sensitive_posUt_E", !10, i64 0}
!28 = !{!"_ZTSN7sc_core16sc_sensitive_negE", !9, i64 0, !29, i64 8, !9, i64 16}
!29 = !{!"_ZTSN7sc_core16sc_sensitive_negUt_E", !10, i64 0}
!30 = !{!"bool", !10, i64 0}
!31 = !{!"int", !10, i64 0}
!32 = !{!"_ZTSN7sc_core5sc_inIbEE", !33, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176}
!33 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE", !34, i64 0}
!34 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE", !35, i64 0, !9, i64 120, !36, i64 128}
!35 = !{!"_ZTSN7sc_core12sc_port_baseE", !8, i64 0, !9, i64 112}
!36 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!40 = !{!"_ZTSN7sc_core5sc_inIiEE", !41, i64 0, !9, i64 152, !9, i64 160}
!41 = !{!"_ZTSN7sc_core7sc_portINS_15sc_signal_in_ifIiEELi1ELNS_14sc_port_policyE0EEE", !42, i64 0}
!42 = !{!"_ZTSN7sc_core9sc_port_bINS_15sc_signal_in_ifIiEEEE", !35, i64 0, !9, i64 120, !43, i64 128}
!43 = !{!"_ZTSSt6vectorIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !44, i64 0}
!44 = !{!"_ZTSSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE12_Vector_implE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core15sc_signal_in_ifIiEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!47 = !{!"_ZTSN7sc_core6sc_outIbEE", !48, i64 0}
!48 = !{!"_ZTSN7sc_core8sc_inoutIbEE", !49, i64 0, !9, i64 152, !9, i64 160, !9, i64 168, !9, i64 176, !9, i64 184}
!49 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIbEELi1ELNS_14sc_port_policyE0EEE", !50, i64 0}
!50 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIbEEEE", !35, i64 0, !9, i64 120, !51, i64 128}
!51 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE", !52, i64 0}
!52 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE", !53, i64 0}
!53 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE12_Vector_implE", !54, i64 0}
!54 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIbEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!55 = !{!"_ZTSN7sc_core6sc_outIiEE", !56, i64 0}
!56 = !{!"_ZTSN7sc_core8sc_inoutIiEE", !57, i64 0, !9, i64 152, !9, i64 160, !9, i64 168}
!57 = !{!"_ZTSN7sc_core7sc_portINS_18sc_signal_inout_ifIiEELi1ELNS_14sc_port_policyE0EEE", !58, i64 0}
!58 = !{!"_ZTSN7sc_core9sc_port_bINS_18sc_signal_inout_ifIiEEEE", !35, i64 0, !9, i64 120, !59, i64 128}
!59 = !{!"_ZTSSt6vectorIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !60, i64 0}
!60 = !{!"_ZTSSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE", !61, i64 0}
!61 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE12_Vector_implE", !62, i64 0}
!62 = !{!"_ZTSNSt12_Vector_baseIPN7sc_core18sc_signal_inout_ifIiEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!63 = !{!30, !30, i64 0}
!64 = !{i8 0, i8 2}
!65 = !{}
!66 = distinct !{!66, !67}
!67 = !{!"llvm.loop.mustprogress"}
!68 = !{!31, !31, i64 0}
!69 = !{!6, !31, i64 1324}
!70 = !{!6, !31, i64 1320}
!71 = distinct !{!71, !67}
!72 = distinct !{!72, !67}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass