; LLVM IR from smwikipedia/EmbeddedAndRTOSSamples :: C5.4_3/devices/uart/tf-m (uart_pl011_drv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.uart_pl011_dev_t = type { ptr, ptr }
%struct.uart_pl011_dev_cfg_t = type { i32, i32, i32, i32, i32 }
%struct.uart_pl011_dev_data_t = type { i32, i32, i32 }
%struct._uart_pl011_reg_map_t = type { i32, %union.anon, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [13 x i32], [4 x i32], [976 x i32], [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32 }
%union.anon = type { i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @uart_pl011_get_state(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @uart_pl011_set_sirlp_divisor(ptr noundef %0, i32 noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.uart_pl011_dev_t, ptr %9, i32 0, i32 0
  %11 = load ptr, ptr %10, align 8, !tbaa !11
  %12 = getelementptr inbounds %struct.uart_pl011_dev_cfg_t, ptr %11, i32 0, i32 0
  %13 = load i32, ptr %12, align 4, !tbaa !13
  %14 = zext i32 %13 to i64
  %15 = inttoptr i64 %14 to ptr
  store ptr %15, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = call i32 @uart_pl011_get_state(ptr noundef %16)
  %18 = icmp ne i32 %17, 1
  br i1 %18, label %19, label %20

19:                                               ; preds = %2
  store i32 19, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %42

20:                                               ; preds = %2
  %21 = load i32, ptr %5, align 4, !tbaa !9
  %22 = icmp eq i32 %21, 0
  br i1 %22, label %23, label %24

23:                                               ; preds = %20
  store i32 16, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %42

24:                                               ; preds = %20
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.uart_pl011_dev_t, ptr %25, i32 0, i32 1
  %27 = load ptr, ptr %26, align 8, !tbaa !15
  %28 = getelementptr inbounds %struct.uart_pl011_dev_data_t, ptr %27, i32 0, i32 1
  %29 = load i32, ptr %28, align 4, !tbaa !16
  %30 = load i32, ptr %5, align 4, !tbaa !9
  %31 = udiv i32 %29, %30
  store i32 %31, ptr %7, align 4, !tbaa !9
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = icmp ult i32 %32, 1420000
  br i1 %33, label %37, label %34

34:                                               ; preds = %24
  %35 = load i32, ptr %7, align 4, !tbaa !9
  %36 = icmp ugt i32 %35, 2120000
  br i1 %36, label %37, label %38

37:                                               ; preds = %34, %24
  store i32 16, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %42

38:                                               ; preds = %34
  %39 = load i32, ptr %5, align 4, !tbaa !9
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct._uart_pl011_reg_map_t, ptr %40, i32 0, i32 5
  store volatile i32 %39, ptr %41, align 4, !tbaa !18
  store i32 0, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %42

42:                                               ; preds = %38, %37, %23, %19
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  %43 = load i32, ptr %3, align 4
  ret i32 %43
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"uart_pl011_dev_t", !6, i64 0, !6, i64 8}
!13 = !{!14, !10, i64 0}
!14 = !{!"uart_pl011_dev_cfg_t", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16}
!15 = !{!12, !6, i64 8}
!16 = !{!17, !10, i64 4}
!17 = !{!"uart_pl011_dev_data_t", !10, i64 0, !10, i64 4, !10, i64 8}
!18 = !{!19, !10, i64 32}
!19 = !{!"_uart_pl011_reg_map_t", !10, i64 0, !7, i64 4, !7, i64 8, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !7, i64 76, !7, i64 128, !7, i64 144, !7, i64 4048, !10, i64 4064, !10, i64 4068, !10, i64 4072, !10, i64 4076, !10, i64 4080, !10, i64 4084, !10, i64 4088, !10, i64 4092}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @uart_pl011_get_state(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 20) i32 @uart_pl011_set_sirlp_divisor(ptr noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = load i32, ptr %3, align 4, !tbaa !10
  %5 = zext i32 %4 to i64
  %6 = inttoptr i64 %5 to ptr
  %7 = tail call i32 @uart_pl011_get_state(ptr noundef nonnull %0)
  %.not = icmp eq i32 %7, 1
  br i1 %.not, label %8, label %19

8:                                                ; preds = %2
  %9 = icmp eq i32 %1, 0
  br i1 %9, label %19, label %10

10:                                               ; preds = %8
  %11 = getelementptr inbounds i8, ptr %0, i64 8
  %12 = load ptr, ptr %11, align 8, !tbaa !13
  %13 = getelementptr inbounds i8, ptr %12, i64 4
  %14 = load i32, ptr %13, align 4, !tbaa !14
  %15 = udiv i32 %14, %1
  %16 = add i32 %15, -2120001
  %or.cond = icmp ult i32 %16, -700001
  br i1 %or.cond, label %19, label %17

17:                                               ; preds = %10
  %18 = getelementptr inbounds i8, ptr %6, i64 32
  store volatile i32 %1, ptr %18, align 4, !tbaa !16
  br label %19

19:                                               ; preds = %10, %8, %2, %17
  %.0 = phi i32 [ 0, %17 ], [ 19, %2 ], [ 16, %8 ], [ 16, %10 ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"uart_pl011_dev_t", !7, i64 0, !7, i64 8}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!11, !12, i64 0}
!11 = !{!"uart_pl011_dev_cfg_t", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16}
!12 = !{!"int", !8, i64 0}
!13 = !{!6, !7, i64 8}
!14 = !{!15, !12, i64 4}
!15 = !{!"uart_pl011_dev_data_t", !12, i64 0, !12, i64 4, !12, i64 8}
!16 = !{!17, !12, i64 32}
!17 = !{!"_uart_pl011_reg_map_t", !12, i64 0, !8, i64 4, !8, i64 8, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !8, i64 76, !8, i64 128, !8, i64 144, !8, i64 4048, !12, i64 4064, !12, i64 4068, !12, i64 4072, !12, i64 4076, !12, i64 4080, !12, i64 4084, !12, i64 4088, !12, i64 4092}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass