; LLVM IR from gem5/gem5 :: src/systemc/dt/int/sc_nbutils.ll (ZN5sc_dt8fsm_moveEcRiS0_S0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str.12 = external hidden unnamed_addr constant [29 x i8], align 1
@.str.13 = external hidden unnamed_addr constant [76 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN5sc_dt8fsm_moveEcRiS0_S0_(i8 noundef signext %0, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 4 dereferenceable(4) %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  store i8 %0, ptr %6, align 1, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !8
  store ptr %2, ptr %8, align 8, !tbaa !8
  store ptr %3, ptr %9, align 8, !tbaa !8
  %10 = load ptr, ptr %9, align 8, !tbaa !8
  %11 = load i32, ptr %10, align 4, !tbaa !10
  switch i32 %11, label %54 [
    i32 0, label %12
    i32 1, label %28
    i32 2, label %46
    i32 3, label %66
  ]

12:                                               ; preds = %4
  %13 = load i8, ptr %6, align 1, !tbaa !5
  %14 = sext i8 %13 to i32
  switch i32 %14, label %24 [
    i32 48, label %15
    i32 43, label %18
    i32 45, label %21
  ]

15:                                               ; preds = %12
  %16 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 1, ptr %16, align 4, !tbaa !10
  %17 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 1, ptr %17, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %67

18:                                               ; preds = %12
  %19 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 1, ptr %19, align 4, !tbaa !10
  %20 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 2, ptr %20, align 4, !tbaa !10
  store i32 1, ptr %5, align 4
  br label %67

21:                                               ; preds = %12
  %22 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 -1, ptr %22, align 4, !tbaa !10
  %23 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 2, ptr %23, align 4, !tbaa !10
  store i32 1, ptr %5, align 4
  br label %67

24:                                               ; preds = %12
  %25 = load ptr, ptr %8, align 8, !tbaa !8
  store i32 1, ptr %25, align 4, !tbaa !10
  %26 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 10, ptr %26, align 4, !tbaa !10
  %27 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %27, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %67

28:                                               ; preds = %4
  %29 = load i8, ptr %6, align 1, !tbaa !5
  %30 = sext i8 %29 to i32
  switch i32 %30, label %43 [
    i32 120, label %31
    i32 88, label %31
    i32 100, label %34
    i32 68, label %34
    i32 111, label %37
    i32 79, label %37
    i32 98, label %40
    i32 66, label %40
  ]

31:                                               ; preds = %28, %28
  %32 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 16, ptr %32, align 4, !tbaa !10
  %33 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %33, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %67

34:                                               ; preds = %28, %28
  %35 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 10, ptr %35, align 4, !tbaa !10
  %36 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %36, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %67

37:                                               ; preds = %28, %28
  %38 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 8, ptr %38, align 4, !tbaa !10
  %39 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %39, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %67

40:                                               ; preds = %28, %28
  %41 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 2, ptr %41, align 4, !tbaa !10
  %42 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %42, align 4, !tbaa !10
  store i32 2, ptr %5, align 4
  br label %67

43:                                               ; preds = %28
  %44 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 10, ptr %44, align 4, !tbaa !10
  %45 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %45, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %67

46:                                               ; preds = %4
  %47 = load i8, ptr %6, align 1, !tbaa !5
  %48 = sext i8 %47 to i32
  switch i32 %48, label %51 [
    i32 48, label %49
  ]

49:                                               ; preds = %46
  %50 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 1, ptr %50, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %67

51:                                               ; preds = %46
  %52 = load ptr, ptr %7, align 8, !tbaa !8
  store i32 10, ptr %52, align 4, !tbaa !10
  %53 = load ptr, ptr %9, align 8, !tbaa !8
  store i32 3, ptr %53, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %67

54:                                               ; preds = %4
  %55 = load ptr, ptr %9, align 8, !tbaa !8
  %56 = load i32, ptr %55, align 4, !tbaa !10
  %57 = icmp sle i32 0, %56
  br i1 %57, label %58, label %63

58:                                               ; preds = %54
  %59 = load ptr, ptr %9, align 8, !tbaa !8
  %60 = load i32, ptr %59, align 4, !tbaa !10
  %61 = icmp sle i32 %60, 3
  br i1 %61, label %62, label %63

62:                                               ; preds = %58
  br label %64

63:                                               ; preds = %58, %54
  call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef @.str.12, ptr noundef @.str.13, i32 noundef 186)
  br label %64

64:                                               ; preds = %63, %62
  %65 = phi i32 [ 0, %62 ], [ 0, %63 ]
  br label %66

66:                                               ; preds = %64, %4
  store i32 0, ptr %5, align 4
  br label %67

67:                                               ; preds = %66, %51, %49, %43, %40, %37, %34, %31, %24, %21, %18, %15
  %68 = load i32, ptr %5, align 4
  ret i32 %68
}

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN7sc_core23SC_ID_ASSERTION_FAILED_E = external constant [0 x i8], align 1
@.str.12 = external hidden unnamed_addr constant [29 x i8], align 1
@.str.13 = external hidden unnamed_addr constant [76 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef range(i32 0, 3) i32 @_ZN5sc_dt8fsm_moveEcRiS0_S0_(i8 noundef signext %0, ptr nocapture noundef nonnull writeonly align 4 dereferenceable(4) %1, ptr nocapture noundef nonnull writeonly align 4 dereferenceable(4) %2, ptr nocapture noundef nonnull align 4 dereferenceable(4) %3) local_unnamed_addr #0 {
  %5 = load i32, ptr %3, align 4, !tbaa !5
  switch i32 %5, label %20 [
    i32 0, label %6
    i32 1, label %11
    i32 2, label %17
    i32 3, label %21
  ]

6:                                                ; preds = %4
  switch i8 %0, label %10 [
    i8 48, label %7
    i8 43, label %8
    i8 45, label %9
  ]

7:                                                ; preds = %6
  store i32 1, ptr %2, align 4, !tbaa !5
  store i32 1, ptr %3, align 4, !tbaa !5
  br label %21

8:                                                ; preds = %6
  store i32 1, ptr %2, align 4, !tbaa !5
  store i32 2, ptr %3, align 4, !tbaa !5
  br label %21

9:                                                ; preds = %6
  store i32 -1, ptr %2, align 4, !tbaa !5
  store i32 2, ptr %3, align 4, !tbaa !5
  br label %21

10:                                               ; preds = %6
  store i32 1, ptr %2, align 4, !tbaa !5
  store i32 10, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

11:                                               ; preds = %4
  switch i8 %0, label %16 [
    i8 120, label %12
    i8 88, label %12
    i8 100, label %13
    i8 68, label %13
    i8 111, label %14
    i8 79, label %14
    i8 98, label %15
    i8 66, label %15
  ]

12:                                               ; preds = %11, %11
  store i32 16, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

13:                                               ; preds = %11, %11
  store i32 10, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

14:                                               ; preds = %11, %11
  store i32 8, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

15:                                               ; preds = %11, %11
  store i32 2, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

16:                                               ; preds = %11
  store i32 10, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

17:                                               ; preds = %4
  %cond = icmp eq i8 %0, 48
  br i1 %cond, label %18, label %19

18:                                               ; preds = %17
  store i32 1, ptr %3, align 4, !tbaa !5
  br label %21

19:                                               ; preds = %17
  store i32 10, ptr %1, align 4, !tbaa !5
  store i32 3, ptr %3, align 4, !tbaa !5
  br label %21

20:                                               ; preds = %4
  tail call void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef 3, ptr noundef nonnull @_ZN7sc_core23SC_ID_ASSERTION_FAILED_E, ptr noundef nonnull @.str.12, ptr noundef nonnull @.str.13, i32 noundef 186)
  br label %21

21:                                               ; preds = %4, %20, %19, %18, %16, %15, %14, %13, %12, %10, %9, %8, %7
  %.0 = phi i32 [ 0, %18 ], [ 0, %19 ], [ 0, %16 ], [ 2, %15 ], [ 2, %14 ], [ 2, %13 ], [ 2, %12 ], [ 0, %10 ], [ 1, %9 ], [ 1, %8 ], [ 0, %7 ], [ 0, %20 ], [ 0, %4 ]
  ret i32 %.0
}

declare void @_ZN7sc_core17sc_report_handler6reportENS_11sc_severityEPKcS3_S3_i(i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass