; LLVM IR from gem5/gem5 :: src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.ll (ZN6sio_tx4byteEc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.sio_tx = type { %"class.sc_core::sc_module", %"class.sc_core::sc_in", %"class.sc_core::sc_in", %"class.sc_core::sc_out" }
%"class.sc_core::sc_module" = type { %"class.sc_core::sc_object", %"class.sc_core::sc_process_host", %"class.sc_core::sc_sensitive", %"class.sc_core::sc_sensitive_pos", %"class.sc_core::sc_sensitive_neg", i8, ptr, i32, ptr, ptr }
%"class.sc_core::sc_object" = type { ptr, ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::__cxx11::basic_string", ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_event *, std::allocator<sc_core::sc_event *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_object *, std::allocator<sc_core::sc_object *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.sc_core::sc_process_host" = type { ptr }
%"class.sc_core::sc_sensitive" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_pos" = type { ptr, i32, ptr }
%"class.sc_core::sc_sensitive_neg" = type { ptr, i32, ptr }
%"class.sc_core::sc_in" = type { %"class.sc_core::sc_port", ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port" = type { %"class.sc_core::sc_port_b" }
%"class.sc_core::sc_port_b" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.8" }
%"class.sc_core::sc_port_base" = type { %"class.sc_core::sc_object", ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_in_if<bool> *, std::allocator<sc_core::sc_signal_in_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.sc_core::sc_out" = type { %"class.sc_core::sc_inout" }
%"class.sc_core::sc_inout" = type { %"class.sc_core::sc_port.13", ptr, ptr, ptr, ptr, ptr }
%"class.sc_core::sc_port.13" = type { %"class.sc_core::sc_port_b.14" }
%"class.sc_core::sc_port_b.14" = type { %"class.sc_core::sc_port_base", ptr, %"class.std::vector.15" }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl" = type { %"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<sc_core::sc_signal_inout_if<bool> *, std::allocator<sc_core::sc_signal_inout_if<bool> *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6sio_tx4byteEc(ptr noundef nonnull align 8 dereferenceable(792) %0, i8 noundef signext %1) #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i8 %1, ptr %4, align 1, !tbaa !9
  %12 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  store i8 0, ptr %5, align 1, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %13 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 3
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  store i8 0, ptr %7, align 1, !tbaa !10
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %13, ptr noundef nonnull align 1 dereferenceable(1) %7)
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %12)
  store i32 0, ptr %6, align 4, !tbaa !12
  br label %14

14:                                               ; preds = %38, %2
  %15 = load i32, ptr %6, align 4, !tbaa !12
  %16 = icmp slt i32 %15, 8
  br i1 %16, label %17, label %41

17:                                               ; preds = %14
  %18 = load i8, ptr %4, align 1, !tbaa !9
  %19 = sext i8 %18 to i32
  %20 = and i32 %19, 1
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %27

22:                                               ; preds = %17
  %23 = load i8, ptr %5, align 1, !tbaa !10, !range !14, !noundef !15
  %24 = trunc i8 %23 to i1
  %25 = xor i1 %24, true
  %26 = zext i1 %25 to i8
  store i8 %26, ptr %5, align 1, !tbaa !10
  br label %27

27:                                               ; preds = %22, %17
  %28 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 3
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #2
  %29 = load i8, ptr %4, align 1, !tbaa !9
  %30 = sext i8 %29 to i32
  %31 = and i32 %30, 1
  %32 = icmp ne i32 %31, 0
  %33 = zext i1 %32 to i8
  store i8 %33, ptr %8, align 1, !tbaa !10
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %28, ptr noundef nonnull align 1 dereferenceable(1) %8)
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #2
  %34 = load i8, ptr %4, align 1, !tbaa !9
  %35 = sext i8 %34 to i32
  %36 = ashr i32 %35, 1
  %37 = trunc i32 %36 to i8
  store i8 %37, ptr %4, align 1, !tbaa !9
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %12)
  br label %38

38:                                               ; preds = %27
  %39 = load i32, ptr %6, align 4, !tbaa !12
  %40 = add nsw i32 %39, 1
  store i32 %40, ptr %6, align 4, !tbaa !12
  br label %14, !llvm.loop !16

41:                                               ; preds = %14
  %42 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 3
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %42, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %12)
  %43 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 2
  %44 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %43)
  %45 = load i8, ptr %44, align 1, !tbaa !10, !range !14, !noundef !15
  %46 = trunc i8 %45 to i1
  br i1 %46, label %47, label %50

47:                                               ; preds = %41
  %48 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #2
  store i8 1, ptr %9, align 1, !tbaa !10
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %48, ptr noundef nonnull align 1 dereferenceable(1) %9)
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %12)
  %49 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 3
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #2
  store i8 1, ptr %10, align 1, !tbaa !10
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %49, ptr noundef nonnull align 1 dereferenceable(1) %10)
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %12)
  br label %52

50:                                               ; preds = %41
  %51 = getelementptr inbounds %struct.sio_tx, ptr %12, i32 0, i32 3
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #2
  store i8 1, ptr %11, align 1, !tbaa !10
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %51, ptr noundef nonnull align 1 dereferenceable(1) %11)
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %12)
  br label %52

52:                                               ; preds = %50, %47
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"bool", !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !7, i64 0}
!14 = !{i8 0, i8 2}
!15 = !{}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6sio_tx4byteEc(ptr noundef nonnull align 8 dereferenceable(792) %0, i8 noundef signext %1) local_unnamed_addr #0 align 2 {
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  store i8 0, ptr %3, align 1, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %0, i64 600
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #2
  store i8 0, ptr %4, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %4)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %10 = and i8 %1, 1
  %.not = icmp eq i8 %10, 0
  br i1 %.not, label %12, label %11

11:                                               ; preds = %2
  store i8 1, ptr %3, align 1, !tbaa !5
  br label %12

12:                                               ; preds = %11, %2
  %13 = phi i8 [ 1, %11 ], [ 0, %2 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %10, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %14 = lshr i8 %1, 1
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %15 = and i8 %14, 1
  %.not.1 = icmp eq i8 %15, 0
  br i1 %.not.1, label %18, label %16

16:                                               ; preds = %12
  %17 = xor i8 %13, 1
  store i8 %17, ptr %3, align 1, !tbaa !5
  br label %18

18:                                               ; preds = %16, %12
  %19 = phi i8 [ %17, %16 ], [ %13, %12 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %15, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %20 = lshr i8 %1, 2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %21 = and i8 %20, 1
  %.not.2 = icmp eq i8 %21, 0
  br i1 %.not.2, label %24, label %22

22:                                               ; preds = %18
  %23 = xor i8 %19, 1
  store i8 %23, ptr %3, align 1, !tbaa !5
  br label %24

24:                                               ; preds = %22, %18
  %25 = phi i8 [ %23, %22 ], [ %19, %18 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %21, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %26 = lshr i8 %1, 3
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %27 = and i8 %26, 1
  %.not.3 = icmp eq i8 %27, 0
  br i1 %.not.3, label %30, label %28

28:                                               ; preds = %24
  %29 = xor i8 %25, 1
  store i8 %29, ptr %3, align 1, !tbaa !5
  br label %30

30:                                               ; preds = %28, %24
  %31 = phi i8 [ %29, %28 ], [ %25, %24 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %27, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %32 = lshr i8 %1, 4
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %33 = and i8 %32, 1
  %.not.4 = icmp eq i8 %33, 0
  br i1 %.not.4, label %36, label %34

34:                                               ; preds = %30
  %35 = xor i8 %31, 1
  store i8 %35, ptr %3, align 1, !tbaa !5
  br label %36

36:                                               ; preds = %34, %30
  %37 = phi i8 [ %35, %34 ], [ %31, %30 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %33, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %38 = lshr i8 %1, 5
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %39 = and i8 %38, 1
  %.not.5 = icmp eq i8 %39, 0
  br i1 %.not.5, label %42, label %40

40:                                               ; preds = %36
  %41 = xor i8 %37, 1
  store i8 %41, ptr %3, align 1, !tbaa !5
  br label %42

42:                                               ; preds = %40, %36
  %43 = phi i8 [ %41, %40 ], [ %37, %36 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %39, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %44 = lshr i8 %1, 6
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %45 = and i8 %44, 1
  %.not.6 = icmp eq i8 %45, 0
  br i1 %.not.6, label %48, label %46

46:                                               ; preds = %42
  %47 = xor i8 %43, 1
  store i8 %47, ptr %3, align 1, !tbaa !5
  br label %48

48:                                               ; preds = %46, %42
  %49 = phi i8 [ %47, %46 ], [ %43, %42 ]
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %45, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  %50 = lshr i8 %1, 7
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %.not.7 = icmp sgt i8 %1, -1
  br i1 %.not.7, label %53, label %51

51:                                               ; preds = %48
  %52 = xor i8 %49, 1
  store i8 %52, ptr %3, align 1, !tbaa !5
  br label %53

53:                                               ; preds = %51, %48
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  store i8 %50, ptr %5, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %5)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %3)
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  %54 = getelementptr inbounds i8, ptr %0, i64 416
  %55 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184) %54)
  %56 = load i8, ptr %55, align 1, !tbaa !5, !range !9, !noundef !10
  %57 = trunc nuw i8 %56 to i1
  br i1 %57, label %58, label %59

58:                                               ; preds = %53
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) #2
  store i8 1, ptr %6, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %6)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %6) #2
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %7) #2
  store i8 1, ptr %7, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %7)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %7) #2
  br label %60

59:                                               ; preds = %53
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %8) #2
  store i8 1, ptr %8, align 1, !tbaa !5
  call void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192) %9, ptr noundef nonnull align 1 dereferenceable(1) %8)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %8) #2
  br label %60

60:                                               ; preds = %59, %58
  call void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232) %0)
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core8sc_inoutIbE5writeERKb(ptr noundef nonnull align 8 dereferenceable(192), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7sc_core9sc_module4waitEv(ptr noundef nonnull align 8 dereferenceable(232)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK7sc_core5sc_inIbEcvRKbEv(ptr noundef nonnull align 8 dereferenceable(184)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,SROAPass,SimplifyCFGPass