; LLVM IR from gem5/gem5 :: ext/drampower/src (CmdScheduler)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Data::MemorySpecification" = type { ptr, %"class.std::__cxx11::basic_string", %"class.Data::MemoryType", [4 x i8], %"class.Data::MemArchitectureSpec", %"class.Data::MemTimingSpec", %"class.Data::MemPowerSpec", %"class.Data::Parametrisable" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.Data::MemoryType" = type { i32 }
%"class.Data::MemArchitectureSpec" = type <{ ptr, i64, i64, i64, i64, i64, i64, i64, i64, i8, i8, i8, [5 x i8], %"class.Data::Parametrisable" }>
%"class.Data::MemTimingSpec" = type { ptr, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, %"class.Data::Parametrisable" }
%"class.Data::MemPowerSpec" = type { ptr, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, %"class.Data::Parametrisable" }
%"class.Data::Parametrisable" = type { ptr, %"class.std::vector.14" }
%"class.std::vector.14" = type { %"struct.std::_Vector_base.15" }
%"struct.std::_Vector_base.15" = type { %"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::Parameter, std::allocator<Data::Parameter>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.Data::cmdScheduler" = type { %"class.std::vector", %"class.Data::cmdScheduler::commandItem", %"class.Data::cmdScheduler::commandItem", %"class.Data::cmdScheduler::commandItem", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.8", %"class.std::vector.3", %"class.std::vector.3", i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i8, i64, %"class.std::basic_ofstream" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Data::cmdScheduler::trans, std::allocator<Data::cmdScheduler::trans>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::cmdScheduler::trans, std::allocator<Data::cmdScheduler::trans>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::cmdScheduler::trans, std::allocator<Data::cmdScheduler::trans>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::cmdScheduler::trans, std::allocator<Data::cmdScheduler::trans>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.Data::cmdScheduler::commandItem" = type { i64, i64, i64, %"class.std::__cxx11::basic_string", %"class.Data::cmdScheduler::physicalAddr" }
%"class.Data::cmdScheduler::physicalAddr" = type { i64, i64, i64, i64 }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<std::vector<Data::cmdScheduler::commandItem>, std::allocator<std::vector<Data::cmdScheduler::commandItem>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<Data::cmdScheduler::commandItem>, std::allocator<std::vector<Data::cmdScheduler::commandItem>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<Data::cmdScheduler::commandItem>, std::allocator<std::vector<Data::cmdScheduler::commandItem>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<Data::cmdScheduler::commandItem>, std::allocator<std::vector<Data::cmdScheduler::commandItem>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<Data::cmdScheduler::commandItem, std::allocator<Data::cmdScheduler::commandItem>>::_Vector_impl" }
%"struct.std::_Vector_base<Data::cmdScheduler::commandItem, std::allocator<Data::cmdScheduler::commandItem>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data::cmdScheduler::commandItem, std::allocator<Data::cmdScheduler::commandItem>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data::cmdScheduler::commandItem, std::allocator<Data::cmdScheduler::commandItem>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::basic_ofstream" = type { %"class.std::basic_ostream.base", %"class.std::basic_filebuf", %"class.std::basic_ios" }
%"class.std::basic_ostream.base" = type { ptr }
%"class.std::basic_filebuf" = type { %"class.std::basic_streambuf", %union.pthread_mutex_t, %"class.std::__basic_file", i32, %struct.__mbstate_t, %struct.__mbstate_t, %struct.__mbstate_t, ptr, i64, i8, i8, i8, i8, ptr, ptr, i8, ptr, ptr, i64, ptr, ptr }
%"class.std::basic_streambuf" = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, %"class.std::locale" }
%"class.std::locale" = type { ptr }
%union.pthread_mutex_t = type { %struct.__pthread_mutex_s }
%struct.__pthread_mutex_s = type { i32, i32, i32, i32, i32, i16, i16, %struct.__pthread_internal_list }
%struct.__pthread_internal_list = type { ptr, ptr }
%"class.std::__basic_file" = type <{ ptr, i8, [7 x i8] }>
%struct.__mbstate_t = type { i32, %union.anon.13 }
%union.anon.13 = type { i32 }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Data12cmdScheduler20getTimingConstraintsEbRKNS_19MemorySpecificationEll(ptr noundef nonnull align 8 dereferenceable(1080) %0, i1 noundef zeroext %1, ptr noundef nonnull align 8 dereferenceable(736) %2, i64 noundef %3, i64 noundef %4) #2 align 2 {
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  store ptr %0, ptr %6, align 8, !tbaa !5
  %13 = zext i1 %1 to i8
  store i8 %13, ptr %7, align 1, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i64 %3, ptr %9, align 8, !tbaa !11
  store i64 %4, ptr %10, align 8, !tbaa !11
  %14 = load ptr, ptr %6, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %15 = load ptr, ptr %8, align 8, !tbaa !5
  %16 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %15, i32 0, i32 5
  store ptr %16, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #3
  %17 = load ptr, ptr %8, align 8, !tbaa !5
  %18 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %17, i32 0, i32 4
  store ptr %18, ptr %12, align 8, !tbaa !5
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  %20 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %19, i32 0, i32 2
  %21 = call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %20)
  %22 = icmp ne i32 %21, 2
  br i1 %22, label %23, label %100

23:                                               ; preds = %5
  %24 = load ptr, ptr %11, align 8, !tbaa !5
  %25 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %24, i32 0, i32 7
  %26 = load i64, ptr %25, align 8, !tbaa !13
  %27 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 16
  store i64 %26, ptr %27, align 8, !tbaa !16
  %28 = load i64, ptr %9, align 8, !tbaa !11
  %29 = load i64, ptr %10, align 8, !tbaa !11
  %30 = icmp eq i64 %28, %29
  br i1 %30, label %31, label %37

31:                                               ; preds = %23
  %32 = load ptr, ptr %11, align 8, !tbaa !5
  %33 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %32, i32 0, i32 4
  %34 = load i64, ptr %33, align 8, !tbaa !43
  %35 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %34, ptr %35, align 8, !tbaa !44
  %36 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 27
  store i8 1, ptr %36, align 8, !tbaa !45
  br label %37

37:                                               ; preds = %31, %23
  %38 = load i64, ptr %9, align 8, !tbaa !11
  %39 = icmp eq i64 %38, 1
  br i1 %39, label %40, label %99

40:                                               ; preds = %37
  %41 = load i64, ptr %10, align 8, !tbaa !11
  %42 = icmp eq i64 %41, 0
  br i1 %42, label %43, label %99

43:                                               ; preds = %40
  %44 = load ptr, ptr %8, align 8, !tbaa !5
  %45 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %44, i32 0, i32 2
  %46 = call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %45)
  %47 = icmp eq i32 %46, 6
  br i1 %47, label %48, label %66

48:                                               ; preds = %43
  %49 = load ptr, ptr %11, align 8, !tbaa !5
  %50 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %49, i32 0, i32 21
  %51 = load i64, ptr %50, align 8, !tbaa !46
  %52 = load ptr, ptr %12, align 8, !tbaa !5
  %53 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %52, i32 0, i32 1
  %54 = load i64, ptr %53, align 8, !tbaa !47
  %55 = load ptr, ptr %12, align 8, !tbaa !5
  %56 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %55, i32 0, i32 4
  %57 = load i64, ptr %56, align 8, !tbaa !49
  %58 = sdiv i64 %54, %57
  %59 = add nsw i64 %51, %58
  %60 = sub nsw i64 %59, 1
  %61 = load ptr, ptr %11, align 8, !tbaa !5
  %62 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %61, i32 0, i32 12
  %63 = load i64, ptr %62, align 8, !tbaa !50
  %64 = add nsw i64 %60, %63
  %65 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %64, ptr %65, align 8, !tbaa !44
  br label %83

66:                                               ; preds = %43
  %67 = load ptr, ptr %11, align 8, !tbaa !5
  %68 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %67, i32 0, i32 21
  %69 = load i64, ptr %68, align 8, !tbaa !46
  %70 = load ptr, ptr %12, align 8, !tbaa !5
  %71 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %70, i32 0, i32 1
  %72 = load i64, ptr %71, align 8, !tbaa !47
  %73 = load ptr, ptr %12, align 8, !tbaa !5
  %74 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %73, i32 0, i32 4
  %75 = load i64, ptr %74, align 8, !tbaa !49
  %76 = sdiv i64 %72, %75
  %77 = add nsw i64 %69, %76
  %78 = load ptr, ptr %11, align 8, !tbaa !5
  %79 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %78, i32 0, i32 12
  %80 = load i64, ptr %79, align 8, !tbaa !50
  %81 = add nsw i64 %77, %80
  %82 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %81, ptr %82, align 8, !tbaa !44
  br label %83

83:                                               ; preds = %66, %48
  %84 = load ptr, ptr %8, align 8, !tbaa !5
  %85 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %84, i32 0, i32 2
  %86 = call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %85)
  %87 = icmp eq i32 %86, 4
  br i1 %87, label %93, label %88

88:                                               ; preds = %83
  %89 = load ptr, ptr %8, align 8, !tbaa !5
  %90 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %89, i32 0, i32 2
  %91 = call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %90)
  %92 = icmp eq i32 %91, 5
  br i1 %92, label %93, label %98

93:                                               ; preds = %88, %83
  %94 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  %95 = load i64, ptr %94, align 8, !tbaa !44
  %96 = add nsw i64 %95, 1
  %97 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %96, ptr %97, align 8, !tbaa !44
  br label %98

98:                                               ; preds = %93, %88
  br label %99

99:                                               ; preds = %98, %40, %37
  br label %100

100:                                              ; preds = %99, %5
  %101 = load ptr, ptr %8, align 8, !tbaa !5
  %102 = getelementptr inbounds %"class.Data::MemorySpecification", ptr %101, i32 0, i32 2
  %103 = call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %102)
  %104 = icmp eq i32 %103, 2
  br i1 %104, label %105, label %167

105:                                              ; preds = %100
  %106 = load i8, ptr %7, align 1, !tbaa !9, !range !51, !noundef !52
  %107 = trunc i8 %106 to i1
  br i1 %107, label %108, label %121

108:                                              ; preds = %105
  %109 = load ptr, ptr %11, align 8, !tbaa !5
  %110 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %109, i32 0, i32 5
  %111 = load i64, ptr %110, align 8, !tbaa !53
  %112 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 17
  store i64 %111, ptr %112, align 8, !tbaa !54
  %113 = load ptr, ptr %11, align 8, !tbaa !5
  %114 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %113, i32 0, i32 8
  %115 = load i64, ptr %114, align 8, !tbaa !55
  %116 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 16
  store i64 %115, ptr %116, align 8, !tbaa !16
  %117 = load ptr, ptr %11, align 8, !tbaa !5
  %118 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %117, i32 0, i32 13
  %119 = load i64, ptr %118, align 8, !tbaa !56
  %120 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 18
  store i64 %119, ptr %120, align 8, !tbaa !57
  br label %134

121:                                              ; preds = %105
  %122 = load ptr, ptr %11, align 8, !tbaa !5
  %123 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %122, i32 0, i32 6
  %124 = load i64, ptr %123, align 8, !tbaa !58
  %125 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 17
  store i64 %124, ptr %125, align 8, !tbaa !54
  %126 = load ptr, ptr %11, align 8, !tbaa !5
  %127 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %126, i32 0, i32 9
  %128 = load i64, ptr %127, align 8, !tbaa !59
  %129 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 16
  store i64 %128, ptr %129, align 8, !tbaa !16
  %130 = load ptr, ptr %11, align 8, !tbaa !5
  %131 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %130, i32 0, i32 14
  %132 = load i64, ptr %131, align 8, !tbaa !60
  %133 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 18
  store i64 %132, ptr %133, align 8, !tbaa !57
  br label %134

134:                                              ; preds = %121, %108
  %135 = load i64, ptr %9, align 8, !tbaa !11
  %136 = load i64, ptr %10, align 8, !tbaa !11
  %137 = icmp eq i64 %135, %136
  br i1 %137, label %138, label %143

138:                                              ; preds = %134
  %139 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 17
  %140 = load i64, ptr %139, align 8, !tbaa !54
  %141 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %140, ptr %141, align 8, !tbaa !44
  %142 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 27
  store i8 1, ptr %142, align 8, !tbaa !45
  br label %166

143:                                              ; preds = %134
  %144 = load i64, ptr %9, align 8, !tbaa !11
  %145 = icmp eq i64 %144, 1
  br i1 %145, label %146, label %165

146:                                              ; preds = %143
  %147 = load i64, ptr %10, align 8, !tbaa !11
  %148 = icmp eq i64 %147, 0
  br i1 %148, label %149, label %165

149:                                              ; preds = %146
  %150 = load ptr, ptr %11, align 8, !tbaa !5
  %151 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %150, i32 0, i32 21
  %152 = load i64, ptr %151, align 8, !tbaa !46
  %153 = load ptr, ptr %12, align 8, !tbaa !5
  %154 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %153, i32 0, i32 1
  %155 = load i64, ptr %154, align 8, !tbaa !47
  %156 = load ptr, ptr %12, align 8, !tbaa !5
  %157 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %156, i32 0, i32 4
  %158 = load i64, ptr %157, align 8, !tbaa !49
  %159 = sdiv i64 %155, %158
  %160 = add nsw i64 %152, %159
  %161 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 18
  %162 = load i64, ptr %161, align 8, !tbaa !57
  %163 = add nsw i64 %160, %162
  %164 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %163, ptr %164, align 8, !tbaa !44
  br label %165

165:                                              ; preds = %149, %146, %143
  br label %166

166:                                              ; preds = %165, %138
  br label %167

167:                                              ; preds = %166, %100
  %168 = load i64, ptr %9, align 8, !tbaa !11
  %169 = icmp eq i64 %168, 0
  br i1 %169, label %170, label %191

170:                                              ; preds = %167
  %171 = load i64, ptr %10, align 8, !tbaa !11
  %172 = icmp eq i64 %171, 1
  br i1 %172, label %173, label %191

173:                                              ; preds = %170
  %174 = load ptr, ptr %11, align 8, !tbaa !5
  %175 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %174, i32 0, i32 16
  %176 = load i64, ptr %175, align 8, !tbaa !61
  %177 = load ptr, ptr %12, align 8, !tbaa !5
  %178 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %177, i32 0, i32 1
  %179 = load i64, ptr %178, align 8, !tbaa !47
  %180 = load ptr, ptr %12, align 8, !tbaa !5
  %181 = getelementptr inbounds %"class.Data::MemArchitectureSpec", ptr %180, i32 0, i32 4
  %182 = load i64, ptr %181, align 8, !tbaa !49
  %183 = sdiv i64 %179, %182
  %184 = add nsw i64 %176, %183
  %185 = add nsw i64 %184, 2
  %186 = load ptr, ptr %11, align 8, !tbaa !5
  %187 = getelementptr inbounds %"class.Data::MemTimingSpec", ptr %186, i32 0, i32 21
  %188 = load i64, ptr %187, align 8, !tbaa !46
  %189 = sub nsw i64 %185, %188
  %190 = getelementptr inbounds %"class.Data::cmdScheduler", ptr %14, i32 0, i32 20
  store i64 %189, ptr %190, align 8, !tbaa !44
  br label %191

191:                                              ; preds = %173, %170, %167
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !12, i64 56}
!14 = !{!"_ZTSN4Data13MemTimingSpecE", !15, i64 8, !12, i64 16, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !12, i64 64, !12, i64 72, !12, i64 80, !12, i64 88, !12, i64 96, !12, i64 104, !12, i64 112, !12, i64 120, !12, i64 128, !12, i64 136, !12, i64 144, !12, i64 152, !12, i64 160, !12, i64 168, !12, i64 176, !12, i64 184, !12, i64 192, !12, i64 200, !12, i64 208, !12, i64 216, !12, i64 224, !12, i64 232, !12, i64 240, !12, i64 248, !15, i64 256}
!15 = !{!"double", !7, i64 0}
!16 = !{!17, !12, i64 464}
!17 = !{!"_ZTSN4Data12cmdSchedulerE", !18, i64 0, !22, i64 24, !22, i64 112, !22, i64 200, !26, i64 288, !26, i64 312, !30, i64 336, !26, i64 360, !26, i64 384, !34, i64 408, !12, i64 416, !12, i64 424, !12, i64 432, !12, i64 440, !12, i64 448, !12, i64 456, !12, i64 464, !12, i64 472, !12, i64 480, !12, i64 488, !12, i64 496, !12, i64 504, !12, i64 512, !12, i64 520, !12, i64 528, !12, i64 536, !12, i64 544, !10, i64 552, !12, i64 560, !35, i64 568}
!18 = !{!"_ZTSSt6vectorIN4Data12cmdScheduler5transESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIN4Data12cmdScheduler5transESaIS2_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler5transESaIS2_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler5transESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSN4Data12cmdScheduler11commandItemE", !12, i64 0, !12, i64 8, !12, i64 16, !23, i64 24, !25, i64 56}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !12, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"_ZTSN4Data12cmdScheduler12physicalAddrE", !12, i64 0, !12, i64 8, !12, i64 16, !12, i64 24}
!26 = !{!"_ZTSSt6vectorIN4Data12cmdScheduler11commandItemESaIS2_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIN4Data12cmdScheduler11commandItemESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler11commandItemESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler11commandItemESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIS_IN4Data12cmdScheduler11commandItemESaIS2_EESaIS4_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseISt6vectorIN4Data12cmdScheduler11commandItemESaIS3_EESaIS5_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN4Data12cmdScheduler11commandItemESaIS3_EESaIS5_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN4Data12cmdScheduler11commandItemESaIS3_EESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"int", !7, i64 0}
!35 = !{!"_ZTSSt14basic_ofstreamIcSt11char_traitsIcEE", !36, i64 0, !37, i64 8}
!36 = !{!"_ZTSSo"}
!37 = !{!"_ZTSSt13basic_filebufIcSt11char_traitsIcEE", !38, i64 0, !7, i64 64, !40, i64 104, !41, i64 120, !42, i64 124, !42, i64 132, !42, i64 140, !6, i64 152, !12, i64 160, !10, i64 168, !10, i64 169, !10, i64 170, !7, i64 171, !6, i64 176, !6, i64 184, !10, i64 192, !6, i64 200, !6, i64 208, !12, i64 216, !6, i64 224, !6, i64 232}
!38 = !{!"_ZTSSt15basic_streambufIcSt11char_traitsIcEE", !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !39, i64 56}
!39 = !{!"_ZTSSt6locale", !6, i64 0}
!40 = !{!"_ZTSSt12__basic_fileIcE", !6, i64 0, !10, i64 8}
!41 = !{!"_ZTSSt13_Ios_Openmode", !7, i64 0}
!42 = !{!"_ZTS11__mbstate_t", !34, i64 0, !7, i64 4}
!43 = !{!14, !12, i64 32}
!44 = !{!17, !12, i64 496}
!45 = !{!17, !10, i64 552}
!46 = !{!14, !12, i64 168}
!47 = !{!48, !12, i64 8}
!48 = !{!"_ZTSN4Data19MemArchitectureSpecE", !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !12, i64 64, !10, i64 72, !10, i64 73, !10, i64 74}
!49 = !{!48, !12, i64 32}
!50 = !{!14, !12, i64 96}
!51 = !{i8 0, i8 2}
!52 = !{}
!53 = !{!14, !12, i64 40}
!54 = !{!17, !12, i64 472}
!55 = !{!14, !12, i64 64}
!56 = !{!14, !12, i64 104}
!57 = !{!17, !12, i64 480}
!58 = !{!14, !12, i64 48}
!59 = !{!14, !12, i64 72}
!60 = !{!14, !12, i64 112}
!61 = !{!14, !12, i64 128}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Data12cmdScheduler20getTimingConstraintsEbRKNS_19MemorySpecificationEll(ptr nocapture noundef nonnull align 8 dereferenceable(1080) %0, i1 noundef zeroext %1, ptr noundef nonnull align 8 dereferenceable(736) %2, i64 noundef %3, i64 noundef %4) local_unnamed_addr #0 align 2 {
  %6 = getelementptr inbounds i8, ptr %2, i64 40
  %7 = tail call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %6)
  %.not = icmp eq i32 %7, 2
  br i1 %.not, label %52, label %8

8:                                                ; preds = %5
  %9 = getelementptr inbounds i8, ptr %2, i64 216
  %10 = load i64, ptr %9, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %0, i64 464
  store i64 %10, ptr %11, align 8, !tbaa !11
  %12 = icmp eq i64 %3, %4
  br i1 %12, label %13, label %18

13:                                               ; preds = %8
  %14 = getelementptr inbounds i8, ptr %2, i64 192
  %15 = load i64, ptr %14, align 8, !tbaa !40
  %16 = getelementptr inbounds i8, ptr %0, i64 496
  store i64 %15, ptr %16, align 8, !tbaa !41
  %17 = getelementptr inbounds i8, ptr %0, i64 552
  store i8 1, ptr %17, align 8, !tbaa !42
  br label %18

18:                                               ; preds = %13, %8
  %19 = icmp eq i64 %3, 1
  %20 = icmp eq i64 %4, 0
  %or.cond = and i1 %19, %20
  br i1 %or.cond, label %21, label %52

21:                                               ; preds = %18
  %22 = tail call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %6)
  %23 = icmp eq i32 %22, 6
  %24 = getelementptr inbounds i8, ptr %2, i64 328
  %25 = load i64, ptr %24, align 8, !tbaa !43
  %26 = getelementptr inbounds i8, ptr %2, i64 56
  %27 = load i64, ptr %26, align 8, !tbaa !44
  %28 = getelementptr inbounds i8, ptr %2, i64 80
  %29 = load i64, ptr %28, align 8, !tbaa !46
  %30 = sdiv i64 %27, %29
  br i1 %23, label %31, label %37

31:                                               ; preds = %21
  %32 = getelementptr inbounds i8, ptr %2, i64 256
  %33 = load i64, ptr %32, align 8, !tbaa !47
  %34 = add i64 %25, -1
  %35 = add i64 %34, %30
  %36 = add nsw i64 %35, %33
  br label %42

37:                                               ; preds = %21
  %38 = add nsw i64 %30, %25
  %39 = getelementptr inbounds i8, ptr %2, i64 256
  %40 = load i64, ptr %39, align 8, !tbaa !47
  %41 = add nsw i64 %38, %40
  br label %42

42:                                               ; preds = %37, %31
  %.sink = phi i64 [ %36, %31 ], [ %41, %37 ]
  %43 = getelementptr inbounds i8, ptr %0, i64 496
  store i64 %.sink, ptr %43, align 8
  %44 = tail call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %6)
  %45 = icmp eq i32 %44, 4
  br i1 %45, label %49, label %46

46:                                               ; preds = %42
  %47 = tail call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %6)
  %48 = icmp eq i32 %47, 5
  br i1 %48, label %49, label %52

49:                                               ; preds = %46, %42
  %50 = load i64, ptr %43, align 8, !tbaa !41
  %51 = add nsw i64 %50, 1
  store i64 %51, ptr %43, align 8, !tbaa !41
  br label %52

52:                                               ; preds = %18, %49, %46, %5
  %53 = tail call noundef i32 @_ZNK4Data10MemoryTypecvNS0_12MemoryType_tEEv(ptr noundef nonnull align 4 dereferenceable(4) %6)
  %54 = icmp eq i32 %53, 2
  br i1 %54, label %55, label %80

55:                                               ; preds = %52
  %. = select i1 %1, i64 200, i64 208
  %.57 = select i1 %1, i64 224, i64 232
  %.58 = select i1 %1, i64 264, i64 272
  %56 = getelementptr inbounds i8, ptr %2, i64 %.
  %57 = getelementptr inbounds i8, ptr %2, i64 %.57
  %58 = getelementptr inbounds i8, ptr %2, i64 %.58
  %59 = load i64, ptr %58, align 8, !tbaa !48
  %.sink49 = load i64, ptr %57, align 8, !tbaa !48
  %60 = load i64, ptr %56, align 8, !tbaa !48
  %61 = getelementptr inbounds i8, ptr %0, i64 472
  store i64 %60, ptr %61, align 8
  %62 = getelementptr inbounds i8, ptr %0, i64 464
  store i64 %.sink49, ptr %62, align 8
  %63 = getelementptr inbounds i8, ptr %0, i64 480
  store i64 %59, ptr %63, align 8
  %64 = icmp eq i64 %3, %4
  br i1 %64, label %65, label %68

65:                                               ; preds = %55
  %66 = getelementptr inbounds i8, ptr %0, i64 496
  store i64 %60, ptr %66, align 8, !tbaa !41
  %67 = getelementptr inbounds i8, ptr %0, i64 552
  store i8 1, ptr %67, align 8, !tbaa !42
  br label %80

68:                                               ; preds = %55
  %69 = icmp eq i64 %3, 1
  %70 = icmp eq i64 %4, 0
  %or.cond3 = and i1 %69, %70
  br i1 %or.cond3, label %.thread, label %80

.thread:                                          ; preds = %68
  %71 = getelementptr inbounds i8, ptr %2, i64 328
  %72 = load i64, ptr %71, align 8, !tbaa !43
  %73 = getelementptr inbounds i8, ptr %2, i64 56
  %74 = load i64, ptr %73, align 8, !tbaa !44
  %75 = getelementptr inbounds i8, ptr %2, i64 80
  %76 = load i64, ptr %75, align 8, !tbaa !46
  %77 = sdiv i64 %74, %76
  %78 = add nsw i64 %77, %72
  %79 = add nsw i64 %78, %59
  br label %.sink.split

80:                                               ; preds = %65, %68, %52
  %81 = icmp eq i64 %3, 0
  %82 = icmp eq i64 %4, 1
  %or.cond5 = and i1 %81, %82
  br i1 %or.cond5, label %83, label %97

83:                                               ; preds = %80
  %84 = getelementptr inbounds i8, ptr %2, i64 288
  %85 = load i64, ptr %84, align 8, !tbaa !49
  %86 = getelementptr inbounds i8, ptr %2, i64 56
  %87 = load i64, ptr %86, align 8, !tbaa !44
  %88 = getelementptr inbounds i8, ptr %2, i64 80
  %89 = load i64, ptr %88, align 8, !tbaa !46
  %90 = sdiv i64 %87, %89
  %91 = getelementptr inbounds i8, ptr %2, i64 328
  %92 = load i64, ptr %91, align 8, !tbaa !43
  %93 = add i64 %85, 2
  %94 = add i64 %93, %90
  %95 = sub i64 %94, %92
  br label %.sink.split

.sink.split:                                      ; preds = %83, %.thread
  %.sink55 = phi i64 [ %79, %.thread ], [ %95, %83 ]
  %96 = getelementptr inbounds i8, ptr %0, i64 496
  store i64 %.sink55, ptr %96, align 8, !tbaa !41
  br label %97

97:                                               ; preds = %.sink.split, %80
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 56}
!6 = !{!"_ZTSN4Data13MemTimingSpecE", !7, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !10, i64 168, !10, i64 176, !10, i64 184, !10, i64 192, !10, i64 200, !10, i64 208, !10, i64 216, !10, i64 224, !10, i64 232, !10, i64 240, !10, i64 248, !7, i64 256}
!7 = !{!"double", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"long", !8, i64 0}
!11 = !{!12, !10, i64 464}
!12 = !{!"_ZTSN4Data12cmdSchedulerE", !13, i64 0, !18, i64 24, !18, i64 112, !18, i64 200, !22, i64 288, !22, i64 312, !26, i64 336, !22, i64 360, !22, i64 384, !30, i64 408, !10, i64 416, !10, i64 424, !10, i64 432, !10, i64 440, !10, i64 448, !10, i64 456, !10, i64 464, !10, i64 472, !10, i64 480, !10, i64 488, !10, i64 496, !10, i64 504, !10, i64 512, !10, i64 520, !10, i64 528, !10, i64 536, !10, i64 544, !31, i64 552, !10, i64 560, !32, i64 568}
!13 = !{!"_ZTSSt6vectorIN4Data12cmdScheduler5transESaIS2_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIN4Data12cmdScheduler5transESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler5transESaIS2_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler5transESaIS2_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!17 = !{!"any pointer", !8, i64 0}
!18 = !{!"_ZTSN4Data12cmdScheduler11commandItemE", !10, i64 0, !10, i64 8, !10, i64 16, !19, i64 24, !21, i64 56}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !10, i64 8, !8, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !17, i64 0}
!21 = !{!"_ZTSN4Data12cmdScheduler12physicalAddrE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24}
!22 = !{!"_ZTSSt6vectorIN4Data12cmdScheduler11commandItemESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIN4Data12cmdScheduler11commandItemESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler11commandItemESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN4Data12cmdScheduler11commandItemESaIS2_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!26 = !{!"_ZTSSt6vectorIS_IN4Data12cmdScheduler11commandItemESaIS2_EESaIS4_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseISt6vectorIN4Data12cmdScheduler11commandItemESaIS3_EESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN4Data12cmdScheduler11commandItemESaIS3_EESaIS5_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN4Data12cmdScheduler11commandItemESaIS3_EESaIS5_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!30 = !{!"int", !8, i64 0}
!31 = !{!"bool", !8, i64 0}
!32 = !{!"_ZTSSt14basic_ofstreamIcSt11char_traitsIcEE", !33, i64 0, !34, i64 8}
!33 = !{!"_ZTSSo"}
!34 = !{!"_ZTSSt13basic_filebufIcSt11char_traitsIcEE", !35, i64 0, !8, i64 64, !37, i64 104, !38, i64 120, !39, i64 124, !39, i64 132, !39, i64 140, !17, i64 152, !10, i64 160, !31, i64 168, !31, i64 169, !31, i64 170, !8, i64 171, !17, i64 176, !17, i64 184, !31, i64 192, !17, i64 200, !17, i64 208, !10, i64 216, !17, i64 224, !17, i64 232}
!35 = !{!"_ZTSSt15basic_streambufIcSt11char_traitsIcEE", !17, i64 8, !17, i64 16, !17, i64 24, !17, i64 32, !17, i64 40, !17, i64 48, !36, i64 56}
!36 = !{!"_ZTSSt6locale", !17, i64 0}
!37 = !{!"_ZTSSt12__basic_fileIcE", !17, i64 0, !31, i64 8}
!38 = !{!"_ZTSSt13_Ios_Openmode", !8, i64 0}
!39 = !{!"_ZTS11__mbstate_t", !30, i64 0, !8, i64 4}
!40 = !{!6, !10, i64 32}
!41 = !{!12, !10, i64 496}
!42 = !{!12, !31, i64 552}
!43 = !{!6, !10, i64 168}
!44 = !{!45, !10, i64 8}
!45 = !{!"_ZTSN4Data19MemArchitectureSpecE", !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !31, i64 72, !31, i64 73, !31, i64 74}
!46 = !{!45, !10, i64 32}
!47 = !{!6, !10, i64 96}
!48 = !{!10, !10, i64 0}
!49 = !{!6, !10, i64 128}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MergedLoadStoreMotionPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass