; LLVM IR from m-boutaleb/LZS :: src (buffer_service)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @write_bits_buffer(i8 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local void @load_byte(i16 noundef zeroext %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i8 noundef zeroext %3) #1 {
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  %7 = alloca i16, align 2
  %8 = alloca i8, align 1
  %9 = alloca i16, align 2
  store i16 %0, ptr %5, align 2, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !5
  store i8 %3, ptr %8, align 1, !tbaa !9
  %10 = load i16, ptr %5, align 2, !tbaa !5
  %11 = icmp ne i16 %10, 0
  br i1 %11, label %12, label %14

12:                                               ; preds = %4
  call void @write_bits_buffer(i8 noundef zeroext 0, i16 noundef zeroext 1)
  %13 = load i8, ptr %8, align 1, !tbaa !9
  call void @write_bits_buffer(i8 noundef zeroext %13, i16 noundef zeroext 8)
  br label %85

14:                                               ; preds = %4
  call void @write_bits_buffer(i8 noundef zeroext 1, i16 noundef zeroext 1)
  %15 = load i16, ptr %6, align 2, !tbaa !5
  %16 = zext i16 %15 to i32
  %17 = icmp slt i32 %16, 128
  br i1 %17, label %18, label %23

18:                                               ; preds = %14
  %19 = load i16, ptr %6, align 2, !tbaa !5
  %20 = zext i16 %19 to i32
  %21 = or i32 128, %20
  %22 = trunc i32 %21 to i8
  call void @write_bits_buffer(i8 noundef zeroext %22, i16 noundef zeroext 8)
  br label %37

23:                                               ; preds = %14
  %24 = load i16, ptr %6, align 2, !tbaa !5
  %25 = zext i16 %24 to i32
  %26 = icmp sgt i32 %25, 127
  br i1 %26, label %27, label %36

27:                                               ; preds = %23
  call void @write_bits_buffer(i8 noundef zeroext 0, i16 noundef zeroext 1)
  %28 = load i16, ptr %6, align 2, !tbaa !5
  %29 = zext i16 %28 to i32
  %30 = ashr i32 %29, 4
  %31 = trunc i32 %30 to i8
  call void @write_bits_buffer(i8 noundef zeroext %31, i16 noundef zeroext 7)
  %32 = load i16, ptr %6, align 2, !tbaa !5
  %33 = zext i16 %32 to i32
  %34 = and i32 %33, 15
  %35 = trunc i32 %34 to i8
  call void @write_bits_buffer(i8 noundef zeroext %35, i16 noundef zeroext 4)
  br label %36

36:                                               ; preds = %27, %23
  br label %37

37:                                               ; preds = %36, %18
  %38 = load i16, ptr %7, align 2, !tbaa !5
  %39 = zext i16 %38 to i32
  %40 = icmp slt i32 %39, 5
  br i1 %40, label %41, label %46

41:                                               ; preds = %37
  %42 = load i16, ptr %7, align 2, !tbaa !5
  %43 = zext i16 %42 to i32
  %44 = sub nsw i32 %43, 2
  %45 = trunc i32 %44 to i8
  call void @write_bits_buffer(i8 noundef zeroext %45, i16 noundef zeroext 2)
  br label %84

46:                                               ; preds = %37
  %47 = load i16, ptr %7, align 2, !tbaa !5
  %48 = zext i16 %47 to i32
  %49 = icmp sgt i32 %48, 4
  br i1 %49, label %50, label %60

50:                                               ; preds = %46
  %51 = load i16, ptr %7, align 2, !tbaa !5
  %52 = zext i16 %51 to i32
  %53 = icmp slt i32 %52, 8
  br i1 %53, label %54, label %60

54:                                               ; preds = %50
  %55 = load i16, ptr %7, align 2, !tbaa !5
  %56 = zext i16 %55 to i32
  %57 = sub nsw i32 %56, 5
  %58 = or i32 12, %57
  %59 = trunc i32 %58 to i8
  call void @write_bits_buffer(i8 noundef zeroext %59, i16 noundef zeroext 4)
  br label %83

60:                                               ; preds = %50, %46
  %61 = load i16, ptr %7, align 2, !tbaa !5
  %62 = zext i16 %61 to i32
  %63 = icmp sgt i32 %62, 7
  br i1 %63, label %64, label %82

64:                                               ; preds = %60
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #2
  %65 = load i16, ptr %7, align 2, !tbaa !5
  %66 = zext i16 %65 to i32
  %67 = sub nsw i32 %66, 8
  %68 = sdiv i32 %67, 15
  %69 = add nsw i32 %68, 1
  %70 = trunc i32 %69 to i16
  store i16 %70, ptr %9, align 2, !tbaa !5
  br label %71

71:                                               ; preds = %75, %64
  %72 = load i16, ptr %9, align 2, !tbaa !5
  %73 = add i16 %72, -1
  store i16 %73, ptr %9, align 2, !tbaa !5
  %74 = icmp ne i16 %72, 0
  br i1 %74, label %75, label %76

75:                                               ; preds = %71
  call void @write_bits_buffer(i8 noundef zeroext 15, i16 noundef zeroext 4)
  br label %71, !llvm.loop !10

76:                                               ; preds = %71
  %77 = load i16, ptr %7, align 2, !tbaa !5
  %78 = zext i16 %77 to i32
  %79 = sub nsw i32 %78, 8
  %80 = srem i32 %79, 15
  %81 = trunc i32 %80 to i8
  call void @write_bits_buffer(i8 noundef zeroext %81, i16 noundef zeroext 4)
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #2
  br label %82

82:                                               ; preds = %76, %60
  br label %83

83:                                               ; preds = %82, %54
  br label %84

84:                                               ; preds = %83, %41
  br label %85

85:                                               ; preds = %84, %12
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @write_bits_buffer(i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @load_byte(i16 noundef zeroext %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i8 noundef zeroext %3) local_unnamed_addr #0 {
  %.not = icmp eq i16 %0, 0
  br i1 %.not, label %6, label %5

5:                                                ; preds = %4
  tail call void @write_bits_buffer(i8 noundef zeroext 0, i16 noundef zeroext 1)
  tail call void @write_bits_buffer(i8 noundef zeroext %3, i16 noundef zeroext 8)
  br label %36

6:                                                ; preds = %4
  tail call void @write_bits_buffer(i8 noundef zeroext 1, i16 noundef zeroext 1)
  %7 = icmp ult i16 %1, 128
  br i1 %7, label %8, label %11

8:                                                ; preds = %6
  %9 = trunc nuw i16 %1 to i8
  %10 = or disjoint i8 %9, -128
  tail call void @write_bits_buffer(i8 noundef zeroext %10, i16 noundef zeroext 8)
  br label %16

11:                                               ; preds = %6
  tail call void @write_bits_buffer(i8 noundef zeroext 0, i16 noundef zeroext 1)
  %12 = lshr i16 %1, 4
  %13 = trunc i16 %12 to i8
  tail call void @write_bits_buffer(i8 noundef zeroext %13, i16 noundef zeroext 7)
  %14 = trunc i16 %1 to i8
  %15 = and i8 %14, 15
  tail call void @write_bits_buffer(i8 noundef zeroext %15, i16 noundef zeroext 4)
  br label %16

16:                                               ; preds = %11, %8
  %17 = zext i16 %2 to i32
  %18 = icmp ult i16 %2, 5
  br i1 %18, label %19, label %22

19:                                               ; preds = %16
  %20 = trunc nuw i16 %2 to i8
  %21 = add nsw i8 %20, -2
  tail call void @write_bits_buffer(i8 noundef zeroext %21, i16 noundef zeroext 2)
  br label %36

22:                                               ; preds = %16
  %23 = icmp ult i16 %2, 8
  br i1 %23, label %24, label %28

24:                                               ; preds = %22
  %25 = trunc nuw i16 %2 to i8
  %26 = add nsw i8 %25, -5
  %27 = or i8 %26, 12
  tail call void @write_bits_buffer(i8 noundef zeroext %27, i16 noundef zeroext 4)
  br label %36

28:                                               ; preds = %22
  %29 = add nsw i32 %17, -8
  %30 = udiv i32 %29, 15
  %31 = urem i32 %29, 15
  %32 = trunc i32 %30 to i16
  %33 = add i16 %32, 1
  %.not2122 = icmp eq i16 %33, 0
  br i1 %.not2122, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %28, %.lr.ph
  %.023 = phi i16 [ %34, %.lr.ph ], [ %33, %28 ]
  %34 = add i16 %.023, -1
  tail call void @write_bits_buffer(i8 noundef zeroext 15, i16 noundef zeroext 4)
  %.not21 = icmp eq i16 %34, 0
  br i1 %.not21, label %._crit_edge, label %.lr.ph, !llvm.loop !5

._crit_edge:                                      ; preds = %.lr.ph, %28
  %35 = trunc nuw nsw i32 %31 to i8
  tail call void @write_bits_buffer(i8 noundef zeroext %35, i16 noundef zeroext 4)
  br label %36

36:                                               ; preds = %19, %._crit_edge, %24, %5
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DivRemPairsPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass