; LLVM IR from mitdbg/deneva :: system/sim_manager.ll (ZN10SimManager14is_warmup_doneEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.SimManager = type { i8, i8, i64, i8, i8, i64, i64, i64, i64, i64, i64, i64, i64, i64 }

@g_warmup_timer = external global i64, align 8

declare noundef i64 @_Z13get_sys_clockv() #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96) %0) #2 align 2 {
  %2 = alloca i1, align 1
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  %6 = getelementptr inbounds %class.SimManager, ptr %5, i32 0, i32 1
  %7 = load volatile i8, ptr %6, align 1, !tbaa !9, !range !13, !noundef !14
  %8 = trunc i8 %7 to i1
  br i1 %8, label %9, label %10

9:                                                ; preds = %1
  store i1 true, ptr %2, align 1
  br label %31

10:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #3
  %11 = call noundef i64 @_Z13get_sys_clockv()
  %12 = getelementptr inbounds %class.SimManager, ptr %5, i32 0, i32 5
  %13 = load i64, ptr %12, align 8, !tbaa !15
  %14 = sub i64 %11, %13
  %15 = load i64, ptr @g_warmup_timer, align 8, !tbaa !16
  %16 = icmp uge i64 %14, %15
  %17 = zext i1 %16 to i8
  store i8 %17, ptr %4, align 1, !tbaa !17
  %18 = load i8, ptr %4, align 1, !tbaa !17, !range !13, !noundef !14
  %19 = trunc i8 %18 to i1
  br i1 %19, label %20, label %28

20:                                               ; preds = %10
  %21 = getelementptr inbounds %class.SimManager, ptr %5, i32 0, i32 2
  %22 = call noundef i64 @_Z13get_sys_clockv()
  %23 = cmpxchg ptr %21, i64 0, i64 %22 seq_cst seq_cst, align 8
  %24 = extractvalue { i64, i1 } %23, 1
  %25 = getelementptr inbounds %class.SimManager, ptr %5, i32 0, i32 1
  %26 = cmpxchg ptr %25, i8 0, i8 1 seq_cst seq_cst, align 1
  %27 = extractvalue { i8, i1 } %26, 1
  br label %28

28:                                               ; preds = %20, %10
  %29 = load i8, ptr %4, align 1, !tbaa !17, !range !13, !noundef !14
  %30 = trunc i8 %29 to i1
  store i1 %30, ptr %2, align 1
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #3
  br label %31

31:                                               ; preds = %28, %9
  %32 = load i1, ptr %2, align 1
  ret i1 %32
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 1}
!10 = !{!"_ZTS10SimManager", !11, i64 0, !11, i64 1, !12, i64 8, !11, i64 16, !11, i64 17, !12, i64 24, !12, i64 32, !12, i64 40, !12, i64 48, !12, i64 56, !12, i64 64, !12, i64 72, !12, i64 80, !12, i64 88}
!11 = !{!"bool", !7, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!10, !12, i64 24}
!16 = !{!12, !12, i64 0}
!17 = !{!11, !11, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@g_warmup_timer = external local_unnamed_addr global i64, align 8

declare noundef i64 @_Z13get_sys_clockv() local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96) %0) local_unnamed_addr #1 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 1
  %3 = load volatile i8, ptr %2, align 1, !tbaa !5, !range !11, !noundef !12
  %4 = trunc nuw i8 %3 to i1
  br i1 %4, label %16, label %5

5:                                                ; preds = %1
  %6 = tail call noundef i64 @_Z13get_sys_clockv()
  %7 = getelementptr inbounds i8, ptr %0, i64 24
  %8 = load i64, ptr %7, align 8, !tbaa !13
  %9 = sub i64 %6, %8
  %10 = load i64, ptr @g_warmup_timer, align 8, !tbaa !14
  %.not = icmp ult i64 %9, %10
  br i1 %.not, label %16, label %11

11:                                               ; preds = %5
  %12 = getelementptr inbounds i8, ptr %0, i64 8
  %13 = tail call noundef i64 @_Z13get_sys_clockv()
  %14 = cmpxchg ptr %12, i64 0, i64 %13 seq_cst seq_cst, align 8
  %15 = cmpxchg ptr %2, i8 0, i8 1 seq_cst seq_cst, align 1
  br label %16

16:                                               ; preds = %5, %11, %1
  %.0 = phi i1 [ true, %1 ], [ true, %11 ], [ false, %5 ]
  ret i1 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 1}
!6 = !{!"_ZTS10SimManager", !7, i64 0, !7, i64 1, !10, i64 8, !7, i64 16, !7, i64 17, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88}
!7 = !{!"bool", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"long", !8, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!6, !10, i64 24}
!14 = !{!10, !10, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass