; LLVM IR from shupx/swarm_sync_sim :: src/fw_plane_sim/src/px4_lib/hysteresis (hysteresis)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.systemlib::Hysteresis" = type <{ i64, i64, i64, i8, i8, [6 x i8] }>

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9systemlib10Hysteresis20set_state_and_updateEbRKm(ptr noundef nonnull align 8 dereferenceable(26) %0, i1 noundef zeroext %1, ptr noundef nonnull align 8 dereferenceable(8) %2) #0 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca ptr, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  %7 = zext i1 %1 to i8
  store i8 %7, ptr %5, align 1, !tbaa !9
  store ptr %2, ptr %6, align 8, !tbaa !5
  %8 = load ptr, ptr %4, align 8
  %9 = load i8, ptr %5, align 1, !tbaa !9, !range !11, !noundef !12
  %10 = trunc i8 %9 to i1
  %11 = zext i1 %10 to i32
  %12 = getelementptr inbounds %"class.systemlib::Hysteresis", ptr %8, i32 0, i32 3
  %13 = load i8, ptr %12, align 8, !tbaa !13, !range !11, !noundef !12
  %14 = trunc i8 %13 to i1
  %15 = zext i1 %14 to i32
  %16 = icmp ne i32 %11, %15
  br i1 %16, label %17, label %35

17:                                               ; preds = %3
  %18 = load i8, ptr %5, align 1, !tbaa !9, !range !11, !noundef !12
  %19 = trunc i8 %18 to i1
  %20 = zext i1 %19 to i32
  %21 = getelementptr inbounds %"class.systemlib::Hysteresis", ptr %8, i32 0, i32 4
  %22 = load i8, ptr %21, align 1, !tbaa !16, !range !11, !noundef !12
  %23 = trunc i8 %22 to i1
  %24 = zext i1 %23 to i32
  %25 = icmp ne i32 %20, %24
  br i1 %25, label %26, label %34

26:                                               ; preds = %17
  %27 = load i8, ptr %5, align 1, !tbaa !9, !range !11, !noundef !12
  %28 = trunc i8 %27 to i1
  %29 = getelementptr inbounds %"class.systemlib::Hysteresis", ptr %8, i32 0, i32 4
  %30 = zext i1 %28 to i8
  store i8 %30, ptr %29, align 1, !tbaa !16
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = load i64, ptr %31, align 8, !tbaa !17
  %33 = getelementptr inbounds %"class.systemlib::Hysteresis", ptr %8, i32 0, i32 0
  store i64 %32, ptr %33, align 8, !tbaa !18
  br label %34

34:                                               ; preds = %26, %17
  br label %41

35:                                               ; preds = %3
  %36 = getelementptr inbounds %"class.systemlib::Hysteresis", ptr %8, i32 0, i32 3
  %37 = load i8, ptr %36, align 8, !tbaa !13, !range !11, !noundef !12
  %38 = trunc i8 %37 to i1
  %39 = getelementptr inbounds %"class.systemlib::Hysteresis", ptr %8, i32 0, i32 4
  %40 = zext i1 %38 to i8
  store i8 %40, ptr %39, align 1, !tbaa !16
  br label %41

41:                                               ; preds = %35, %34
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_ZN9systemlib10Hysteresis6updateERKm(ptr noundef nonnull align 8 dereferenceable(26) %8, ptr noundef nonnull align 8 dereferenceable(8) %42)
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN9systemlib10Hysteresis6updateERKm(ptr noundef nonnull align 8 dereferenceable(26), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!14, !10, i64 24}
!14 = !{!"_ZTSN9systemlib10HysteresisE", !15, i64 0, !15, i64 8, !15, i64 16, !10, i64 24, !10, i64 25}
!15 = !{!"long", !7, i64 0}
!16 = !{!14, !10, i64 25}
!17 = !{!15, !15, i64 0}
!18 = !{!14, !15, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN9systemlib10Hysteresis20set_state_and_updateEbRKm(ptr noundef nonnull align 8 dereferenceable(26) %0, i1 noundef zeroext %1, ptr noundef nonnull align 8 dereferenceable(8) %2) local_unnamed_addr #0 align 2 {
  %4 = zext i1 %1 to i8
  %5 = getelementptr inbounds i8, ptr %0, i64 24
  %6 = load i8, ptr %5, align 8, !tbaa !5, !range !11, !noundef !12
  %.not = icmp eq i8 %6, %4
  %7 = getelementptr inbounds i8, ptr %0, i64 25
  br i1 %.not, label %12, label %8

8:                                                ; preds = %3
  %9 = load i8, ptr %7, align 1, !tbaa !13, !range !11, !noundef !12
  %.not5 = icmp eq i8 %9, %4
  br i1 %.not5, label %13, label %10

10:                                               ; preds = %8
  store i8 %4, ptr %7, align 1, !tbaa !13
  %11 = load i64, ptr %2, align 8, !tbaa !14
  store i64 %11, ptr %0, align 8, !tbaa !15
  br label %13

12:                                               ; preds = %3
  store i8 %4, ptr %7, align 1, !tbaa !13
  br label %13

13:                                               ; preds = %8, %10, %12
  tail call void @_ZN9systemlib10Hysteresis6updateERKm(ptr noundef nonnull align 8 dereferenceable(26) %0, ptr noundef nonnull align 8 dereferenceable(8) %2)
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN9systemlib10Hysteresis6updateERKm(ptr noundef nonnull align 8 dereferenceable(26), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 24}
!6 = !{!"_ZTSN9systemlib10HysteresisE", !7, i64 0, !7, i64 8, !7, i64 16, !10, i64 24, !10, i64 25}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"bool", !8, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!6, !10, i64 25}
!14 = !{!7, !7, i64 0}
!15 = !{!6, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass