; LLVM IR from pms67/HadesFCS :: Firmware/F4Quad/Middlewares/Third_Party/FreeRTOS/Source (queue)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }
%struct.QueueDefinition = type { ptr, ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8, i8 }
%union.anon = type { ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare void @vPortEnterCritical() #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

declare void @vPortExitCritical() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @xTaskGetSchedulerState() #2

declare void @vTaskInternalSetTimeOutState(ptr noundef) #2

declare void @vTaskSuspendAll() #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) #2

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) #3

declare i64 @xTaskResumeAll() #2

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueueReceive(ptr noundef %0, ptr noundef %1, i32 noundef %2) #3 {
  %4 = alloca i64, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca %struct.xTIME_OUT, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  store i64 0, ptr %8, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 16, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %13, ptr %10, align 8, !tbaa !5
  %14 = load ptr, ptr %10, align 8, !tbaa !5
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %18

16:                                               ; preds = %3
  call void @vPortRaiseBASEPRI()
  br label %17

17:                                               ; preds = %17, %16
  br label %17

18:                                               ; preds = %3
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = icmp eq ptr %19, null
  br i1 %20, label %21, label %26

21:                                               ; preds = %18
  %22 = load ptr, ptr %10, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.QueueDefinition, ptr %22, i32 0, i32 8
  %24 = load i64, ptr %23, align 8, !tbaa !13
  %25 = icmp ne i64 %24, 0
  br label %26

26:                                               ; preds = %21, %18
  %27 = phi i1 [ false, %18 ], [ %25, %21 ]
  %28 = xor i1 %27, true
  %29 = zext i1 %28 to i32
  %30 = icmp eq i32 %29, 0
  br i1 %30, label %31, label %33

31:                                               ; preds = %26
  call void @vPortRaiseBASEPRI()
  br label %32

32:                                               ; preds = %32, %31
  br label %32

33:                                               ; preds = %26
  %34 = call i64 @xTaskGetSchedulerState()
  %35 = icmp eq i64 %34, 0
  br i1 %35, label %36, label %39

36:                                               ; preds = %33
  %37 = load i32, ptr %7, align 4, !tbaa !9
  %38 = icmp ne i32 %37, 0
  br label %39

39:                                               ; preds = %36, %33
  %40 = phi i1 [ false, %33 ], [ %38, %36 ]
  %41 = xor i1 %40, true
  %42 = zext i1 %41 to i32
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %46

44:                                               ; preds = %39
  call void @vPortRaiseBASEPRI()
  br label %45

45:                                               ; preds = %45, %44
  br label %45

46:                                               ; preds = %39
  br label %47

47:                                               ; preds = %140, %46
  call void @vPortEnterCritical()
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %48 = load ptr, ptr %10, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.QueueDefinition, ptr %48, i32 0, i32 6
  %50 = load volatile i64, ptr %49, align 8, !tbaa !17
  store i64 %50, ptr %11, align 8, !tbaa !11
  %51 = load i64, ptr %11, align 8, !tbaa !11
  %52 = icmp ugt i64 %51, 0
  br i1 %52, label %53, label %78

53:                                               ; preds = %47
  %54 = load ptr, ptr %10, align 8, !tbaa !5
  %55 = load ptr, ptr %6, align 8, !tbaa !5
  call void @prvCopyDataFromQueue(ptr noundef %54, ptr noundef %55)
  %56 = load i64, ptr %11, align 8, !tbaa !11
  %57 = sub i64 %56, 1
  %58 = load ptr, ptr %10, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.QueueDefinition, ptr %58, i32 0, i32 6
  store volatile i64 %57, ptr %59, align 8, !tbaa !17
  %60 = load ptr, ptr %10, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.QueueDefinition, ptr %60, i32 0, i32 4
  %62 = getelementptr inbounds %struct.xLIST, ptr %61, i32 0, i32 0
  %63 = load volatile i64, ptr %62, align 8, !tbaa !18
  %64 = icmp eq i64 %63, 0
  %65 = zext i1 %64 to i32
  %66 = sext i32 %65 to i64
  %67 = icmp eq i64 %66, 0
  br i1 %67, label %68, label %76

68:                                               ; preds = %53
  %69 = load ptr, ptr %10, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.QueueDefinition, ptr %69, i32 0, i32 4
  %71 = call i64 @xTaskRemoveFromEventList(ptr noundef %70)
  %72 = icmp ne i64 %71, 0
  br i1 %72, label %73, label %74

73:                                               ; preds = %68
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  br label %75

74:                                               ; preds = %68
  br label %75

75:                                               ; preds = %74, %73
  br label %77

76:                                               ; preds = %53
  br label %77

77:                                               ; preds = %76, %75
  call void @vPortExitCritical()
  store i64 1, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %90

78:                                               ; preds = %47
  %79 = load i32, ptr %7, align 4, !tbaa !9
  %80 = icmp eq i32 %79, 0
  br i1 %80, label %81, label %82

81:                                               ; preds = %78
  call void @vPortExitCritical()
  store i64 0, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %90

82:                                               ; preds = %78
  %83 = load i64, ptr %8, align 8, !tbaa !11
  %84 = icmp eq i64 %83, 0
  br i1 %84, label %85, label %86

85:                                               ; preds = %82
  call void @vTaskInternalSetTimeOutState(ptr noundef %9)
  store i64 1, ptr %8, align 8, !tbaa !11
  br label %87

86:                                               ; preds = %82
  br label %87

87:                                               ; preds = %86, %85
  br label %88

88:                                               ; preds = %87
  br label %89

89:                                               ; preds = %88
  store i32 0, ptr %12, align 4
  br label %90

90:                                               ; preds = %89, %81, %77
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  %91 = load i32, ptr %12, align 4
  switch i32 %91, label %141 [
    i32 0, label %92
  ]

92:                                               ; preds = %90
  call void @vPortExitCritical()
  call void @vTaskSuspendAll()
  call void @vPortEnterCritical()
  %93 = load ptr, ptr %10, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.QueueDefinition, ptr %93, i32 0, i32 9
  %95 = load volatile i8, ptr %94, align 8, !tbaa !21
  %96 = sext i8 %95 to i32
  %97 = icmp eq i32 %96, -1
  br i1 %97, label %98, label %101

98:                                               ; preds = %92
  %99 = load ptr, ptr %10, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.QueueDefinition, ptr %99, i32 0, i32 9
  store volatile i8 0, ptr %100, align 8, !tbaa !21
  br label %101

101:                                              ; preds = %98, %92
  %102 = load ptr, ptr %10, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.QueueDefinition, ptr %102, i32 0, i32 10
  %104 = load volatile i8, ptr %103, align 1, !tbaa !22
  %105 = sext i8 %104 to i32
  %106 = icmp eq i32 %105, -1
  br i1 %106, label %107, label %110

107:                                              ; preds = %101
  %108 = load ptr, ptr %10, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.QueueDefinition, ptr %108, i32 0, i32 10
  store volatile i8 0, ptr %109, align 1, !tbaa !22
  br label %110

110:                                              ; preds = %107, %101
  call void @vPortExitCritical()
  %111 = call i64 @xTaskCheckForTimeOut(ptr noundef %9, ptr noundef %7)
  %112 = icmp eq i64 %111, 0
  br i1 %112, label %113, label %131

113:                                              ; preds = %110
  %114 = load ptr, ptr %10, align 8, !tbaa !5
  %115 = call i64 @prvIsQueueEmpty(ptr noundef %114)
  %116 = icmp ne i64 %115, 0
  br i1 %116, label %117, label %127

117:                                              ; preds = %113
  %118 = load ptr, ptr %10, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.QueueDefinition, ptr %118, i32 0, i32 5
  %120 = load i32, ptr %7, align 4, !tbaa !9
  call void @vTaskPlaceOnEventList(ptr noundef %119, i32 noundef %120)
  %121 = load ptr, ptr %10, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %121)
  %122 = call i64 @xTaskResumeAll()
  %123 = icmp eq i64 %122, 0
  br i1 %123, label %124, label %125

124:                                              ; preds = %117
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !23
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !24
  br label %126

125:                                              ; preds = %117
  br label %126

126:                                              ; preds = %125, %124
  br label %130

127:                                              ; preds = %113
  %128 = load ptr, ptr %10, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %128)
  %129 = call i64 @xTaskResumeAll()
  br label %130

130:                                              ; preds = %127, %126
  br label %140

131:                                              ; preds = %110
  %132 = load ptr, ptr %10, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %132)
  %133 = call i64 @xTaskResumeAll()
  %134 = load ptr, ptr %10, align 8, !tbaa !5
  %135 = call i64 @prvIsQueueEmpty(ptr noundef %134)
  %136 = icmp ne i64 %135, 0
  br i1 %136, label %137, label %138

137:                                              ; preds = %131
  store i64 0, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %141

138:                                              ; preds = %131
  br label %139

139:                                              ; preds = %138
  br label %140

140:                                              ; preds = %139, %130
  br label %47

141:                                              ; preds = %137, %90
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  %142 = load i64, ptr %4, align 8
  ret i64 %142
}

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueEmpty(ptr noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !12, i64 128}
!14 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !6, i64 16, !7, i64 24, !15, i64 32, !15, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137, !7, i64 138}
!15 = !{!"xLIST", !12, i64 0, !6, i64 8, !16, i64 16}
!16 = !{!"xMINI_LIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!14, !12, i64 112}
!18 = !{!14, !12, i64 32}
!19 = !{i64 2148168683}
!20 = !{i64 2148168733}
!21 = !{!14, !7, i64 136}
!22 = !{!14, !7, i64 137}
!23 = !{i64 2148169978}
!24 = !{i64 2148170028}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare void @vPortEnterCritical() local_unnamed_addr #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #2

declare void @vPortExitCritical() local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @xTaskGetSchedulerState() local_unnamed_addr #2

declare void @vTaskInternalSetTimeOutState(ptr noundef) local_unnamed_addr #2

declare void @vTaskSuspendAll() local_unnamed_addr #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) local_unnamed_addr #3

declare i64 @xTaskResumeAll() local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local noundef i64 @xQueueReceive(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #3 {
  %4 = alloca i32, align 4
  %5 = alloca %struct.xTIME_OUT, align 8
  store i32 %2, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #4
  %6 = icmp eq ptr %0, null
  br i1 %6, label %7, label %9

7:                                                ; preds = %3
  tail call void @vPortRaiseBASEPRI()
  br label %8

8:                                                ; preds = %8, %7
  br label %8

9:                                                ; preds = %3
  %10 = icmp eq ptr %1, null
  br i1 %10, label %11, label %.critedge

11:                                               ; preds = %9
  %12 = getelementptr inbounds i8, ptr %0, i64 128
  %13 = load i64, ptr %12, align 8, !tbaa !9
  %.not39 = icmp eq i64 %13, 0
  br i1 %.not39, label %.critedge, label %14

14:                                               ; preds = %11
  tail call void @vPortRaiseBASEPRI()
  br label %15

15:                                               ; preds = %15, %14
  br label %15

.critedge:                                        ; preds = %9, %11
  %16 = tail call i64 @xTaskGetSchedulerState() #4
  %17 = icmp eq i64 %16, 0
  %18 = icmp ne i32 %2, 0
  %19 = and i1 %17, %18
  br i1 %19, label %52, label %.preheader

.preheader:                                       ; preds = %.critedge
  tail call void @vPortEnterCritical() #4
  %20 = getelementptr inbounds i8, ptr %0, i64 112
  %21 = load volatile i64, ptr %20, align 8, !tbaa !15
  %.not45 = icmp eq i64 %21, 0
  br i1 %.not45, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %.preheader
  %22 = getelementptr inbounds i8, ptr %0, i64 136
  %23 = getelementptr inbounds i8, ptr %0, i64 137
  %24 = getelementptr inbounds i8, ptr %0, i64 72
  %25 = load i32, ptr %4, align 4, !tbaa !5
  %26 = icmp eq i32 %25, 0
  br i1 %26, label %.loopexit.sink.split, label %27

27:                                               ; preds = %.lr.ph
  call void @vTaskInternalSetTimeOutState(ptr noundef nonnull %5) #4
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %28 = load volatile i8, ptr %22, align 8, !tbaa !16
  %29 = icmp eq i8 %28, -1
  br i1 %29, label %30, label %31

30:                                               ; preds = %27
  store volatile i8 0, ptr %22, align 8, !tbaa !16
  br label %31

31:                                               ; preds = %30, %27
  %32 = load volatile i8, ptr %23, align 1, !tbaa !17
  %33 = icmp eq i8 %32, -1
  br i1 %33, label %34, label %35

34:                                               ; preds = %31
  store volatile i8 0, ptr %23, align 1, !tbaa !17
  br label %35

35:                                               ; preds = %34, %31
  call void @vPortExitCritical() #4
  %36 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %5, ptr noundef nonnull %4) #4
  %37 = icmp eq i64 %36, 0
  br i1 %37, label %41, label %38

38:                                               ; preds = %35
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %39 = call i64 @xTaskResumeAll() #4
  %40 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not32.peel = icmp eq i64 %40, 0
  br i1 %.not32.peel, label %50, label %.loopexit

41:                                               ; preds = %35
  %42 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not33.peel = icmp eq i64 %42, 0
  br i1 %.not33.peel, label %48, label %43

43:                                               ; preds = %41
  %44 = load i32, ptr %4, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %24, i32 noundef %44) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %45 = call i64 @xTaskResumeAll() #4
  %46 = icmp eq i64 %45, 0
  br i1 %46, label %47, label %50

47:                                               ; preds = %43
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  br label %50

48:                                               ; preds = %41
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %49 = call i64 @xTaskResumeAll() #4
  br label %50

50:                                               ; preds = %48, %47, %43, %38
  call void @vPortEnterCritical() #4
  %51 = load volatile i64, ptr %20, align 8, !tbaa !15
  %.not.peel = icmp eq i64 %51, 0
  br i1 %.not.peel, label %.peel.next, label %._crit_edge

52:                                               ; preds = %.critedge
  tail call void @vPortRaiseBASEPRI()
  br label %53

53:                                               ; preds = %53, %52
  br label %53

._crit_edge:                                      ; preds = %85, %50, %.preheader
  %.lcssa = phi i64 [ %21, %.preheader ], [ %51, %50 ], [ %86, %85 ]
  call void @prvCopyDataFromQueue(ptr noundef nonnull %0, ptr noundef %1)
  %54 = add i64 %.lcssa, -1
  store volatile i64 %54, ptr %20, align 8, !tbaa !15
  %55 = getelementptr inbounds i8, ptr %0, i64 32
  %56 = load volatile i64, ptr %55, align 8, !tbaa !20
  %.not30 = icmp eq i64 %56, 0
  br i1 %.not30, label %.loopexit.sink.split, label %57

57:                                               ; preds = %._crit_edge
  %58 = call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %55) #4
  %.not31 = icmp eq i64 %58, 0
  br i1 %.not31, label %.loopexit.sink.split, label %59

59:                                               ; preds = %57
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !21
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !22
  br label %.loopexit.sink.split

.peel.next:                                       ; preds = %50, %85
  %60 = load i32, ptr %4, align 4, !tbaa !5
  %61 = icmp eq i32 %60, 0
  br i1 %61, label %.loopexit.sink.split, label %62

62:                                               ; preds = %.peel.next
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %63 = load volatile i8, ptr %22, align 8, !tbaa !16
  %64 = icmp eq i8 %63, -1
  br i1 %64, label %65, label %66

65:                                               ; preds = %62
  store volatile i8 0, ptr %22, align 8, !tbaa !16
  br label %66

66:                                               ; preds = %65, %62
  %67 = load volatile i8, ptr %23, align 1, !tbaa !17
  %68 = icmp eq i8 %67, -1
  br i1 %68, label %69, label %70

69:                                               ; preds = %66
  store volatile i8 0, ptr %23, align 1, !tbaa !17
  br label %70

70:                                               ; preds = %69, %66
  call void @vPortExitCritical() #4
  %71 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %5, ptr noundef nonnull %4) #4
  %72 = icmp eq i64 %71, 0
  br i1 %72, label %73, label %82

73:                                               ; preds = %70
  %74 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not33 = icmp eq i64 %74, 0
  br i1 %.not33, label %80, label %75

75:                                               ; preds = %73
  %76 = load i32, ptr %4, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %24, i32 noundef %76) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %77 = call i64 @xTaskResumeAll() #4
  %78 = icmp eq i64 %77, 0
  br i1 %78, label %79, label %85

79:                                               ; preds = %75
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  br label %85

80:                                               ; preds = %73
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %81 = call i64 @xTaskResumeAll() #4
  br label %85

82:                                               ; preds = %70
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %83 = call i64 @xTaskResumeAll() #4
  %84 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not32 = icmp eq i64 %84, 0
  br i1 %.not32, label %85, label %.loopexit

85:                                               ; preds = %82, %80, %75, %79
  call void @vPortEnterCritical() #4
  %86 = load volatile i64, ptr %20, align 8, !tbaa !15
  %.not = icmp eq i64 %86, 0
  br i1 %.not, label %.peel.next, label %._crit_edge, !llvm.loop !23

.loopexit.sink.split:                             ; preds = %.peel.next, %.lr.ph, %57, %59, %._crit_edge
  %.2.ph = phi i64 [ 1, %._crit_edge ], [ 1, %59 ], [ 1, %57 ], [ 0, %.lr.ph ], [ 0, %.peel.next ]
  call void @vPortExitCritical() #4
  br label %.loopexit

.loopexit:                                        ; preds = %82, %.loopexit.sink.split, %38
  %.2 = phi i64 [ 0, %38 ], [ %.2.ph, %.loopexit.sink.split ], [ 0, %82 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #4
  ret i64 %.2
}

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueEmpty(ptr noundef) local_unnamed_addr #3

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !13, i64 128}
!10 = !{!"QueueDefinition", !11, i64 0, !11, i64 8, !11, i64 16, !7, i64 24, !12, i64 32, !12, i64 72, !13, i64 112, !13, i64 120, !13, i64 128, !7, i64 136, !7, i64 137, !7, i64 138}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"xLIST", !13, i64 0, !11, i64 8, !14, i64 16}
!13 = !{!"long", !7, i64 0}
!14 = !{!"xMINI_LIST_ITEM", !6, i64 0, !11, i64 8, !11, i64 16}
!15 = !{!10, !13, i64 112}
!16 = !{!10, !7, i64 136}
!17 = !{!10, !7, i64 137}
!18 = !{i64 2148169978}
!19 = !{i64 2148170028}
!20 = !{!10, !13, i64 32}
!21 = !{i64 2148168683}
!22 = !{i64 2148168733}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopFullUnrollPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass