; LLVM IR from tangjz/acm-icpc :: self_training/2015-09-22/B.ll (Z5tflipiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Segment = type { i32, i32, i32 }

@m = external dso_local global i32, align 4
@tseg = external dso_local global [200010 x %struct.Segment], align 16

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7seg_idxii(i32 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z7push_upiii(i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5tflipiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = load i32, ptr %6, align 4, !tbaa !5
  %16 = call noundef i32 @_Z7seg_idxii(i32 noundef %14, i32 noundef %15)
  store i32 %16, ptr %9, align 4, !tbaa !5
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = load i32, ptr %5, align 4, !tbaa !5
  %19 = icmp sle i32 %17, %18
  br i1 %19, label %20, label %69

20:                                               ; preds = %4
  %21 = load i32, ptr %6, align 4, !tbaa !5
  %22 = load i32, ptr %8, align 4, !tbaa !5
  %23 = icmp sle i32 %21, %22
  br i1 %23, label %24, label %69

24:                                               ; preds = %20
  %25 = load i32, ptr %9, align 4, !tbaa !5
  %26 = sext i32 %25 to i64
  %27 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %26
  %28 = getelementptr inbounds %struct.Segment, ptr %27, i32 0, i32 0
  %29 = load i32, ptr %28, align 4, !tbaa !9
  %30 = icmp ne i32 %29, -1
  br i1 %30, label %31, label %62

31:                                               ; preds = %24
  %32 = load i32, ptr %9, align 4, !tbaa !5
  %33 = sext i32 %32 to i64
  %34 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %33
  %35 = getelementptr inbounds %struct.Segment, ptr %34, i32 0, i32 0
  %36 = load i32, ptr %9, align 4, !tbaa !5
  %37 = sext i32 %36 to i64
  %38 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %37
  %39 = getelementptr inbounds %struct.Segment, ptr %38, i32 0, i32 1
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %35, ptr noundef nonnull align 4 dereferenceable(4) %39) #4
  %40 = load i32, ptr @m, align 4, !tbaa !5
  %41 = load i32, ptr %9, align 4, !tbaa !5
  %42 = sext i32 %41 to i64
  %43 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %42
  %44 = getelementptr inbounds %struct.Segment, ptr %43, i32 0, i32 0
  %45 = load i32, ptr %44, align 4, !tbaa !9
  %46 = sub nsw i32 %40, %45
  %47 = load i32, ptr %9, align 4, !tbaa !5
  %48 = sext i32 %47 to i64
  %49 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %48
  %50 = getelementptr inbounds %struct.Segment, ptr %49, i32 0, i32 0
  store i32 %46, ptr %50, align 4, !tbaa !9
  %51 = load i32, ptr @m, align 4, !tbaa !5
  %52 = load i32, ptr %9, align 4, !tbaa !5
  %53 = sext i32 %52 to i64
  %54 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %53
  %55 = getelementptr inbounds %struct.Segment, ptr %54, i32 0, i32 1
  %56 = load i32, ptr %55, align 4, !tbaa !11
  %57 = sub nsw i32 %51, %56
  %58 = load i32, ptr %9, align 4, !tbaa !5
  %59 = sext i32 %58 to i64
  %60 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %59
  %61 = getelementptr inbounds %struct.Segment, ptr %60, i32 0, i32 1
  store i32 %57, ptr %61, align 4, !tbaa !11
  br label %62

62:                                               ; preds = %31, %24
  %63 = load i32, ptr %9, align 4, !tbaa !5
  %64 = sext i32 %63 to i64
  %65 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %64
  %66 = getelementptr inbounds %struct.Segment, ptr %65, i32 0, i32 2
  %67 = load i32, ptr %66, align 4, !tbaa !12
  %68 = xor i32 %67, 1
  store i32 %68, ptr %66, align 4, !tbaa !12
  store i32 1, ptr %10, align 4
  br label %106

69:                                               ; preds = %20, %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %70 = load i32, ptr %5, align 4, !tbaa !5
  %71 = load i32, ptr %6, align 4, !tbaa !5
  %72 = add nsw i32 %70, %71
  %73 = ashr i32 %72, 1
  store i32 %73, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %74 = load i32, ptr %5, align 4, !tbaa !5
  %75 = load i32, ptr %11, align 4, !tbaa !5
  %76 = call noundef i32 @_Z7seg_idxii(i32 noundef %74, i32 noundef %75)
  store i32 %76, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  %77 = load i32, ptr %11, align 4, !tbaa !5
  %78 = add nsw i32 %77, 1
  %79 = load i32, ptr %6, align 4, !tbaa !5
  %80 = call noundef i32 @_Z7seg_idxii(i32 noundef %78, i32 noundef %79)
  store i32 %80, ptr %13, align 4, !tbaa !5
  %81 = load i32, ptr %9, align 4, !tbaa !5
  %82 = load i32, ptr %12, align 4, !tbaa !5
  %83 = load i32, ptr %13, align 4, !tbaa !5
  call void @_Z9push_downiii(i32 noundef %81, i32 noundef %82, i32 noundef %83)
  %84 = load i32, ptr %7, align 4, !tbaa !5
  %85 = load i32, ptr %11, align 4, !tbaa !5
  %86 = icmp sle i32 %84, %85
  br i1 %86, label %87, label %92

87:                                               ; preds = %69
  %88 = load i32, ptr %5, align 4, !tbaa !5
  %89 = load i32, ptr %11, align 4, !tbaa !5
  %90 = load i32, ptr %7, align 4, !tbaa !5
  %91 = load i32, ptr %8, align 4, !tbaa !5
  call void @_Z5tflipiiii(i32 noundef %88, i32 noundef %89, i32 noundef %90, i32 noundef %91)
  br label %92

92:                                               ; preds = %87, %69
  %93 = load i32, ptr %8, align 4, !tbaa !5
  %94 = load i32, ptr %11, align 4, !tbaa !5
  %95 = icmp sgt i32 %93, %94
  br i1 %95, label %96, label %102

96:                                               ; preds = %92
  %97 = load i32, ptr %11, align 4, !tbaa !5
  %98 = add nsw i32 %97, 1
  %99 = load i32, ptr %6, align 4, !tbaa !5
  %100 = load i32, ptr %7, align 4, !tbaa !5
  %101 = load i32, ptr %8, align 4, !tbaa !5
  call void @_Z5tflipiiii(i32 noundef %98, i32 noundef %99, i32 noundef %100, i32 noundef %101)
  br label %102

102:                                              ; preds = %96, %92
  %103 = load i32, ptr %9, align 4, !tbaa !5
  %104 = load i32, ptr %12, align 4, !tbaa !5
  %105 = load i32, ptr %13, align 4, !tbaa !5
  call void @_Z7push_upiii(i32 noundef %103, i32 noundef %104, i32 noundef %105)
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  store i32 0, ptr %10, align 4
  br label %106

106:                                              ; preds = %102, %62
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  %107 = load i32, ptr %10, align 4
  switch i32 %107, label %109 [
    i32 0, label %108
    i32 1, label %108
  ]

108:                                              ; preds = %106, %106
  ret void

109:                                              ; preds = %106
  unreachable
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z9push_downiii(i32 noundef, i32 noundef, i32 noundef) #0

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTS7Segment", !6, i64 0, !6, i64 4, !6, i64 8}
!11 = !{!10, !6, i64 4}
!12 = !{!10, !6, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Segment = type { i32, i32, i32 }

@m = external dso_local local_unnamed_addr global i32, align 4
@tseg = external dso_local global [200010 x %struct.Segment], align 16

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7seg_idxii(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z7push_upiii(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5tflipiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = tail call noundef i32 @_Z7seg_idxii(i32 noundef %0, i32 noundef %1)
  %.not = icmp sgt i32 %2, %0
  %.not40 = icmp sgt i32 %1, %3
  %or.cond = or i1 %.not, %.not40
  br i1 %or.cond, label %21, label %6

6:                                                ; preds = %4
  %7 = sext i32 %5 to i64
  %8 = getelementptr inbounds [200010 x %struct.Segment], ptr @tseg, i64 0, i64 %7
  %9 = load i32, ptr %8, align 4, !tbaa !5
  %.not42 = icmp eq i32 %9, -1
  br i1 %.not42, label %17, label %10

10:                                               ; preds = %6
  %11 = getelementptr inbounds i8, ptr %8, i64 4
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %8, ptr noundef nonnull align 4 dereferenceable(4) %11) #3
  %12 = load i32, ptr @m, align 4, !tbaa !10
  %13 = load <2 x i32>, ptr %8, align 4, !tbaa !10
  %14 = insertelement <2 x i32> poison, i32 %12, i64 0
  %15 = shufflevector <2 x i32> %14, <2 x i32> poison, <2 x i32> zeroinitializer
  %16 = sub nsw <2 x i32> %15, %13
  store <2 x i32> %16, ptr %8, align 4, !tbaa !10
  br label %17

17:                                               ; preds = %10, %6
  %18 = getelementptr inbounds i8, ptr %8, i64 8
  %19 = load i32, ptr %18, align 4, !tbaa !11
  %20 = xor i32 %19, 1
  store i32 %20, ptr %18, align 4, !tbaa !11
  br label %32

21:                                               ; preds = %4
  %22 = add nsw i32 %1, %0
  %23 = ashr i32 %22, 1
  %24 = tail call noundef i32 @_Z7seg_idxii(i32 noundef %0, i32 noundef %23)
  %25 = add nsw i32 %23, 1
  %26 = tail call noundef i32 @_Z7seg_idxii(i32 noundef %25, i32 noundef %1)
  tail call void @_Z9push_downiii(i32 noundef %5, i32 noundef %24, i32 noundef %26)
  %.not41 = icmp slt i32 %23, %2
  br i1 %.not41, label %28, label %27

27:                                               ; preds = %21
  tail call void @_Z5tflipiiii(i32 noundef %0, i32 noundef %23, i32 noundef %2, i32 noundef %3)
  br label %28

28:                                               ; preds = %27, %21
  %29 = icmp slt i32 %23, %3
  br i1 %29, label %30, label %31

30:                                               ; preds = %28
  tail call void @_Z5tflipiiii(i32 noundef %25, i32 noundef %1, i32 noundef %2, i32 noundef %3)
  br label %31

31:                                               ; preds = %30, %28
  tail call void @_Z7push_upiii(i32 noundef %5, i32 noundef %24, i32 noundef %26)
  br label %32

32:                                               ; preds = %31, %17
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z9push_downiii(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS7Segment", !7, i64 0, !7, i64 4, !7, i64 8}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!7, !7, i64 0}
!11 = !{!6, !7, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass