; LLVM IR from Yinxiaoli/iros2015_folding :: src/folding_planner_cmake/project/2dregistration_v2 (mesh2d)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SMesh = type <{ %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::map", i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl" }
%"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl" }
%"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl" }
%"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::map" = type { %"class.std::_Rb_tree" }
%"class.std::_Rb_tree" = type { %"struct.std::_Rb_tree<SVertexPair, std::pair<const SVertexPair, SHalfEdge *>, std::_Select1st<std::pair<const SVertexPair, SHalfEdge *>>, std::less<SVertexPair>>::_Rb_tree_impl" }
%"struct.std::_Rb_tree<SVertexPair, std::pair<const SVertexPair, SHalfEdge *>, std::_Select1st<std::pair<const SVertexPair, SHalfEdge *>>, std::less<SVertexPair>>::_Rb_tree_impl" = type { [8 x i8], %"struct.std::_Rb_tree_header" }
%"struct.std::_Rb_tree_header" = type { %"struct.std::_Rb_tree_node_base", i64 }
%"struct.std::_Rb_tree_node_base" = type { i32, ptr, ptr, ptr }
%struct.SVertex = type { ptr, i8, i32, i8, i8 }
%struct.SHalfEdge = type { ptr, ptr, ptr, ptr, ptr, i32, i32, i8, i8 }
%struct.SFace = type { ptr, i32, i8, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z21removeInvalidElementsP5SMeshRSt6vectorIiSaIiEE(ptr noundef %0, ptr noundef nonnull align 8 dereferenceable(24) %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZNSt6vectorIiSaIiEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %13

13:                                               ; preds = %47, %2
  %14 = load i32, ptr %6, align 4, !tbaa !9
  %15 = zext i32 %14 to i64
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.SMesh, ptr %16, i32 0, i32 0
  %18 = call noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  %19 = icmp ult i64 %15, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %50

21:                                               ; preds = %13
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.SMesh, ptr %22, i32 0, i32 0
  %24 = load i32, ptr %6, align 4, !tbaa !9
  %25 = zext i32 %24 to i64
  %26 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %25) #3
  %27 = load ptr, ptr %26, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.SVertex, ptr %27, i32 0, i32 3
  %29 = load i8, ptr %28, align 8, !tbaa !11, !range !14, !noundef !15
  %30 = trunc i8 %29 to i1
  br i1 %30, label %32, label %31

31:                                               ; preds = %21
  br label %47

32:                                               ; preds = %21
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.SMesh, ptr %33, i32 0, i32 0
  %35 = load i32, ptr %6, align 4, !tbaa !9
  %36 = zext i32 %35 to i64
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36) #3
  %38 = load ptr, ptr %37, align 8, !tbaa !5
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.SMesh, ptr %39, i32 0, i32 0
  %41 = load i32, ptr %5, align 4, !tbaa !9
  %42 = add nsw i32 %41, 1
  store i32 %42, ptr %5, align 4, !tbaa !9
  %43 = sext i32 %41 to i64
  %44 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %40, i64 noundef %43) #3
  store ptr %38, ptr %44, align 8, !tbaa !5
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %46 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %46, ptr %7, align 4, !tbaa !9
  call void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24) %45, ptr noundef nonnull align 4 dereferenceable(4) %7)
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  br label %47

47:                                               ; preds = %32, %31
  %48 = load i32, ptr %6, align 4, !tbaa !9
  %49 = add i32 %48, 1
  store i32 %49, ptr %6, align 4, !tbaa !9
  br label %13, !llvm.loop !16

50:                                               ; preds = %20
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.SMesh, ptr %51, i32 0, i32 0
  %53 = load i32, ptr %5, align 4, !tbaa !9
  %54 = sext i32 %53 to i64
  call void @_ZNSt6vectorIP7SVertexSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %54)
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %55

55:                                               ; preds = %87, %50
  %56 = load i32, ptr %9, align 4, !tbaa !9
  %57 = zext i32 %56 to i64
  %58 = load ptr, ptr %3, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.SMesh, ptr %58, i32 0, i32 1
  %60 = call noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %59) #3
  %61 = icmp ult i64 %57, %60
  br i1 %61, label %63, label %62

62:                                               ; preds = %55
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %90

63:                                               ; preds = %55
  %64 = load ptr, ptr %3, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.SMesh, ptr %64, i32 0, i32 1
  %66 = load i32, ptr %9, align 4, !tbaa !9
  %67 = zext i32 %66 to i64
  %68 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %65, i64 noundef %67) #3
  %69 = load ptr, ptr %68, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.SHalfEdge, ptr %69, i32 0, i32 7
  %71 = load i8, ptr %70, align 8, !tbaa !18, !range !14, !noundef !15
  %72 = trunc i8 %71 to i1
  br i1 %72, label %74, label %73

73:                                               ; preds = %63
  br label %87

74:                                               ; preds = %63
  %75 = load ptr, ptr %3, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.SMesh, ptr %75, i32 0, i32 1
  %77 = load i32, ptr %9, align 4, !tbaa !9
  %78 = zext i32 %77 to i64
  %79 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %76, i64 noundef %78) #3
  %80 = load ptr, ptr %79, align 8, !tbaa !5
  %81 = load ptr, ptr %3, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.SMesh, ptr %81, i32 0, i32 1
  %83 = load i32, ptr %8, align 4, !tbaa !9
  %84 = add nsw i32 %83, 1
  store i32 %84, ptr %8, align 4, !tbaa !9
  %85 = sext i32 %83 to i64
  %86 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %82, i64 noundef %85) #3
  store ptr %80, ptr %86, align 8, !tbaa !5
  br label %87

87:                                               ; preds = %74, %73
  %88 = load i32, ptr %9, align 4, !tbaa !9
  %89 = add i32 %88, 1
  store i32 %89, ptr %9, align 4, !tbaa !9
  br label %55, !llvm.loop !20

90:                                               ; preds = %62
  %91 = load ptr, ptr %3, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.SMesh, ptr %91, i32 0, i32 1
  %93 = load i32, ptr %8, align 4, !tbaa !9
  %94 = sext i32 %93 to i64
  call void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %92, i64 noundef %94)
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %95

95:                                               ; preds = %127, %90
  %96 = load i32, ptr %11, align 4, !tbaa !9
  %97 = zext i32 %96 to i64
  %98 = load ptr, ptr %3, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.SMesh, ptr %98, i32 0, i32 2
  %100 = call noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %99) #3
  %101 = icmp ult i64 %97, %100
  br i1 %101, label %103, label %102

102:                                              ; preds = %95
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %130

103:                                              ; preds = %95
  %104 = load ptr, ptr %3, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.SMesh, ptr %104, i32 0, i32 2
  %106 = load i32, ptr %11, align 4, !tbaa !9
  %107 = zext i32 %106 to i64
  %108 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %105, i64 noundef %107) #3
  %109 = load ptr, ptr %108, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.SFace, ptr %109, i32 0, i32 2
  %111 = load i8, ptr %110, align 4, !tbaa !21, !range !14, !noundef !15
  %112 = trunc i8 %111 to i1
  br i1 %112, label %114, label %113

113:                                              ; preds = %103
  br label %127

114:                                              ; preds = %103
  %115 = load ptr, ptr %3, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.SMesh, ptr %115, i32 0, i32 2
  %117 = load i32, ptr %11, align 4, !tbaa !9
  %118 = zext i32 %117 to i64
  %119 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %116, i64 noundef %118) #3
  %120 = load ptr, ptr %119, align 8, !tbaa !5
  %121 = load ptr, ptr %3, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.SMesh, ptr %121, i32 0, i32 2
  %123 = load i32, ptr %10, align 4, !tbaa !9
  %124 = add nsw i32 %123, 1
  store i32 %124, ptr %10, align 4, !tbaa !9
  %125 = sext i32 %123 to i64
  %126 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %122, i64 noundef %125) #3
  store ptr %120, ptr %126, align 8, !tbaa !5
  br label %127

127:                                              ; preds = %114, %113
  %128 = load i32, ptr %11, align 4, !tbaa !9
  %129 = add i32 %128, 1
  store i32 %129, ptr %11, align 4, !tbaa !9
  br label %95, !llvm.loop !23

130:                                              ; preds = %102
  %131 = load ptr, ptr %3, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.SMesh, ptr %131, i32 0, i32 2
  %133 = load i32, ptr %10, align 4, !tbaa !9
  %134 = sext i32 %133 to i64
  call void @_ZNSt6vectorIP5SFaceSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %132, i64 noundef %134)
  %135 = load ptr, ptr %3, align 8, !tbaa !5
  call void @_Z15resetElementIDsP5SMesh(ptr noundef %135)
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP7SVertexSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP5SFaceSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z15resetElementIDsP5SMesh(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !13, i64 16}
!12 = !{!"_ZTS7SVertex", !6, i64 0, !13, i64 8, !10, i64 12, !13, i64 16, !13, i64 17}
!13 = !{!"bool", !7, i64 0}
!14 = !{i8 0, i8 2}
!15 = !{}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{!19, !13, i64 48}
!19 = !{!"_ZTS9SHalfEdge", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 44, !13, i64 48, !13, i64 49}
!20 = distinct !{!20, !17}
!21 = !{!22, !13, i64 12}
!22 = !{!"_ZTS5SFace", !6, i64 0, !10, i64 8, !13, i64 12, !13, i64 13}
!23 = distinct !{!23, !17}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z21removeInvalidElementsP5SMeshRSt6vectorIiSaIiEE(ptr noundef %0, ptr noundef nonnull align 8 dereferenceable(24) %1) local_unnamed_addr #2 {
  %3 = alloca i32, align 4
  tail call void @_ZNSt6vectorIiSaIiEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #3
  %4 = tail call noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %.not = icmp eq i64 %4, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge.loopexit:                             ; preds = %20
  %5 = sext i32 %.142 to i64
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %2
  %.041.lcssa = phi i64 [ 0, %2 ], [ %5, %._crit_edge.loopexit ]
  call void @_ZNSt6vectorIP7SVertexSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.041.lcssa)
  %6 = getelementptr inbounds i8, ptr %0, i64 24
  %7 = call noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  %.not63 = icmp eq i64 %7, 0
  br i1 %.not63, label %._crit_edge53, label %.lr.ph52

.lr.ph:                                           ; preds = %2, %20
  %8 = phi i64 [ %22, %20 ], [ 0, %2 ]
  %.04048 = phi i32 [ %21, %20 ], [ 0, %2 ]
  %.04147 = phi i32 [ %.142, %20 ], [ 0, %2 ]
  %9 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #3
  %10 = load ptr, ptr %9, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %10, i64 16
  %12 = load i8, ptr %11, align 8, !tbaa !9, !range !13, !noundef !14
  %13 = trunc nuw i8 %12 to i1
  br i1 %13, label %14, label %20

14:                                               ; preds = %.lr.ph
  %15 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #3
  %16 = load ptr, ptr %15, align 8, !tbaa !5
  %17 = add nsw i32 %.04147, 1
  %18 = sext i32 %.04147 to i64
  %19 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %18) #3
  store ptr %16, ptr %19, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #3
  store i32 %.04048, ptr %3, align 4, !tbaa !15
  call void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #3
  br label %20

20:                                               ; preds = %.lr.ph, %14
  %.142 = phi i32 [ %17, %14 ], [ %.04147, %.lr.ph ]
  %21 = add i32 %.04048, 1
  %22 = zext i32 %21 to i64
  %23 = call noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %24 = icmp ugt i64 %23, %22
  br i1 %24, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !16

._crit_edge53.loopexit:                           ; preds = %40
  %25 = sext i32 %.139 to i64
  br label %._crit_edge53

._crit_edge53:                                    ; preds = %._crit_edge53.loopexit, %._crit_edge
  %.038.lcssa = phi i64 [ 0, %._crit_edge ], [ %25, %._crit_edge53.loopexit ]
  call void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %.038.lcssa)
  %26 = getelementptr inbounds i8, ptr %0, i64 48
  %27 = call noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #3
  %.not64 = icmp eq i64 %27, 0
  br i1 %.not64, label %._crit_edge60, label %.lr.ph59

.lr.ph52:                                         ; preds = %._crit_edge, %40
  %28 = phi i64 [ %42, %40 ], [ 0, %._crit_edge ]
  %.03750 = phi i32 [ %41, %40 ], [ 0, %._crit_edge ]
  %.03849 = phi i32 [ %.139, %40 ], [ 0, %._crit_edge ]
  %29 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %28) #3
  %30 = load ptr, ptr %29, align 8, !tbaa !5
  %31 = getelementptr inbounds i8, ptr %30, i64 48
  %32 = load i8, ptr %31, align 8, !tbaa !18, !range !13, !noundef !14
  %33 = trunc nuw i8 %32 to i1
  br i1 %33, label %34, label %40

34:                                               ; preds = %.lr.ph52
  %35 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %28) #3
  %36 = load ptr, ptr %35, align 8, !tbaa !5
  %37 = add nsw i32 %.03849, 1
  %38 = sext i32 %.03849 to i64
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %38) #3
  store ptr %36, ptr %39, align 8, !tbaa !5
  br label %40

40:                                               ; preds = %.lr.ph52, %34
  %.139 = phi i32 [ %37, %34 ], [ %.03849, %.lr.ph52 ]
  %41 = add i32 %.03750, 1
  %42 = zext i32 %41 to i64
  %43 = call noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  %44 = icmp ugt i64 %43, %42
  br i1 %44, label %.lr.ph52, label %._crit_edge53.loopexit, !llvm.loop !20

._crit_edge60.loopexit:                           ; preds = %58
  %45 = sext i32 %.1 to i64
  br label %._crit_edge60

._crit_edge60:                                    ; preds = %._crit_edge60.loopexit, %._crit_edge53
  %.036.lcssa = phi i64 [ 0, %._crit_edge53 ], [ %45, %._crit_edge60.loopexit ]
  call void @_ZNSt6vectorIP5SFaceSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %.036.lcssa)
  call void @_Z15resetElementIDsP5SMesh(ptr noundef nonnull %0)
  ret void

.lr.ph59:                                         ; preds = %._crit_edge53, %58
  %46 = phi i64 [ %60, %58 ], [ 0, %._crit_edge53 ]
  %.057 = phi i32 [ %59, %58 ], [ 0, %._crit_edge53 ]
  %.03656 = phi i32 [ %.1, %58 ], [ 0, %._crit_edge53 ]
  %47 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %46) #3
  %48 = load ptr, ptr %47, align 8, !tbaa !5
  %49 = getelementptr inbounds i8, ptr %48, i64 12
  %50 = load i8, ptr %49, align 4, !tbaa !21, !range !13, !noundef !14
  %51 = trunc nuw i8 %50 to i1
  br i1 %51, label %52, label %58

52:                                               ; preds = %.lr.ph59
  %53 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %46) #3
  %54 = load ptr, ptr %53, align 8, !tbaa !5
  %55 = add nsw i32 %.03656, 1
  %56 = sext i32 %.03656 to i64
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %56) #3
  store ptr %54, ptr %57, align 8, !tbaa !5
  br label %58

58:                                               ; preds = %.lr.ph59, %52
  %.1 = phi i32 [ %55, %52 ], [ %.03656, %.lr.ph59 ]
  %59 = add i32 %.057, 1
  %60 = zext i32 %59 to i64
  %61 = call noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #3
  %62 = icmp ugt i64 %61, %60
  br i1 %62, label %.lr.ph59, label %._crit_edge60.loopexit, !llvm.loop !23
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP7SVertexSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP5SFaceSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z15resetElementIDsP5SMesh(ptr noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 16}
!10 = !{!"_ZTS7SVertex", !6, i64 0, !11, i64 8, !12, i64 12, !11, i64 16, !11, i64 17}
!11 = !{!"bool", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!12, !12, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{!19, !11, i64 48}
!19 = !{!"_ZTS9SHalfEdge", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !12, i64 40, !12, i64 44, !11, i64 48, !11, i64 49}
!20 = distinct !{!20, !17}
!21 = !{!22, !11, i64 12}
!22 = !{!"_ZTS5SFace", !6, i64 0, !12, i64 8, !11, i64 12, !11, i64 13}
!23 = distinct !{!23, !17}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass