; LLVM IR from intel/intel-ipsec-mb :: lib/x86_64 (ooo_mgr_reset)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.MB_MGR_HMAC_MD5_OOO = type { %struct.MD5_ARGS, [32 x i16], i64, [24 x i8], [32 x %struct.HMAC_SHA1_LANE_DATA], i32, i32, i64, [16 x i8] }
%struct.MD5_ARGS = type { [128 x i32], [32 x ptr] }
%struct.HMAC_SHA1_LANE_DATA = type { [136 x i8], ptr, [64 x i8], i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define hidden void @ooo_mgr_hmac_md5_reset(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  store ptr %7, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %8 = load ptr, ptr %5, align 8, !tbaa !5
  call void @llvm.memset.p0.i64(ptr align 32 %8, i8 0, i64 8040, i1 false)
  %9 = load ptr, ptr %5, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %9, i32 0, i32 1
  %11 = getelementptr inbounds [32 x i16], ptr %10, i64 0, i64 0
  call void @llvm.memset.p0.i64(ptr align 32 %11, i8 -1, i64 64, i1 false)
  %12 = load i32, ptr %4, align 4, !tbaa !9
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %13, i32 0, i32 6
  store i32 %12, ptr %14, align 4, !tbaa !11
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %15

15:                                               ; preds = %48, %2
  %16 = load i32, ptr %6, align 4, !tbaa !9
  %17 = load i32, ptr %4, align 4, !tbaa !9
  %18 = icmp ult i32 %16, %17
  br i1 %18, label %19, label %51

19:                                               ; preds = %15
  %20 = load ptr, ptr %5, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %20, i32 0, i32 4
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = zext i32 %22 to i64
  %24 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %21, i64 0, i64 %23
  %25 = getelementptr inbounds %struct.HMAC_SHA1_LANE_DATA, ptr %24, i32 0, i32 0
  %26 = getelementptr inbounds [136 x i8], ptr %25, i64 0, i64 64
  store i8 -128, ptr %26, align 32, !tbaa !15
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %27, i32 0, i32 4
  %29 = load i32, ptr %6, align 4, !tbaa !9
  %30 = zext i32 %29 to i64
  %31 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %28, i64 0, i64 %30
  %32 = getelementptr inbounds %struct.HMAC_SHA1_LANE_DATA, ptr %31, i32 0, i32 2
  %33 = getelementptr inbounds [64 x i8], ptr %32, i64 0, i64 16
  store i8 -128, ptr %33, align 16, !tbaa !15
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %34, i32 0, i32 4
  %36 = load i32, ptr %6, align 4, !tbaa !9
  %37 = zext i32 %36 to i64
  %38 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %35, i64 0, i64 %37
  %39 = getelementptr inbounds %struct.HMAC_SHA1_LANE_DATA, ptr %38, i32 0, i32 2
  %40 = getelementptr inbounds [64 x i8], ptr %39, i64 0, i64 57
  store i8 2, ptr %40, align 1, !tbaa !15
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %41, i32 0, i32 4
  %43 = load i32, ptr %6, align 4, !tbaa !9
  %44 = zext i32 %43 to i64
  %45 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %42, i64 0, i64 %44
  %46 = getelementptr inbounds %struct.HMAC_SHA1_LANE_DATA, ptr %45, i32 0, i32 2
  %47 = getelementptr inbounds [64 x i8], ptr %46, i64 0, i64 56
  store i8 -128, ptr %47, align 8, !tbaa !15
  br label %48

48:                                               ; preds = %19
  %49 = load i32, ptr %6, align 4, !tbaa !9
  %50 = add i32 %49, 1
  store i32 %50, ptr %6, align 4, !tbaa !9
  br label %15, !llvm.loop !16

51:                                               ; preds = %15
  %52 = load i32, ptr %4, align 4, !tbaa !9
  %53 = icmp eq i32 %52, 8
  br i1 %53, label %54, label %57

54:                                               ; preds = %51
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %55, i32 0, i32 2
  store i64 66409738768, ptr %56, align 32, !tbaa !18
  br label %64

57:                                               ; preds = %51
  %58 = load i32, ptr %4, align 4, !tbaa !9
  %59 = icmp eq i32 %58, 16
  br i1 %59, label %60, label %63

60:                                               ; preds = %57
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.MB_MGR_HMAC_MD5_OOO, ptr %61, i32 0, i32 2
  store i64 -81985529216486896, ptr %62, align 32, !tbaa !18
  br label %63

63:                                               ; preds = %60, %57
  br label %64

64:                                               ; preds = %63, %54
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8036}
!12 = !{!"", !13, i64 0, !7, i64 768, !14, i64 832, !7, i64 864, !10, i64 8032, !10, i64 8036, !14, i64 8040}
!13 = !{!"", !7, i64 0, !7, i64 512}
!14 = !{!"long", !7, i64 0}
!15 = !{!7, !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{!12, !14, i64 832}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.HMAC_SHA1_LANE_DATA = type { [136 x i8], ptr, [64 x i8], i32, i32, i32, i32 }

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #0

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: write) uwtable
define hidden void @ooo_mgr_hmac_md5_reset(ptr nocapture noundef writeonly %0, i32 noundef %1) local_unnamed_addr #1 {
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 32 dereferenceable(8040) %0, i8 0, i64 8040, i1 false)
  %3 = getelementptr inbounds i8, ptr %0, i64 768
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 32 dereferenceable(64) %3, i8 -1, i64 64, i1 false)
  %4 = getelementptr inbounds i8, ptr %0, i64 8036
  store i32 %1, ptr %4, align 4, !tbaa !5
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %._crit_edge.thread, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %5 = getelementptr inbounds i8, ptr %0, i64 864
  %wide.trip.count = zext i32 %1 to i64
  %xtraiter = and i64 %wide.trip.count, 3
  %6 = icmp ult i32 %1, 4
  br i1 %6, label %._crit_edge.unr-lcssa, label %.lr.ph.new

.lr.ph.new:                                       ; preds = %.lr.ph
  %unroll_iter = and i64 %wide.trip.count, 4294967292
  br label %7

7:                                                ; preds = %7, %.lr.ph.new
  %indvars.iv = phi i64 [ 0, %.lr.ph.new ], [ %indvars.iv.next.3, %7 ]
  %niter = phi i64 [ 0, %.lr.ph.new ], [ %niter.next.3, %7 ]
  %8 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %5, i64 0, i64 %indvars.iv
  %9 = getelementptr inbounds i8, ptr %8, i64 64
  store i8 -128, ptr %9, align 32, !tbaa !12
  %10 = getelementptr inbounds i8, ptr %8, i64 160
  store i8 -128, ptr %10, align 16, !tbaa !12
  %11 = getelementptr inbounds i8, ptr %8, i64 201
  store i8 2, ptr %11, align 1, !tbaa !12
  %12 = getelementptr inbounds i8, ptr %8, i64 200
  store i8 -128, ptr %12, align 8, !tbaa !12
  %indvars.iv.next = or disjoint i64 %indvars.iv, 1
  %13 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %5, i64 0, i64 %indvars.iv.next
  %14 = getelementptr inbounds i8, ptr %13, i64 64
  store i8 -128, ptr %14, align 32, !tbaa !12
  %15 = getelementptr inbounds i8, ptr %13, i64 160
  store i8 -128, ptr %15, align 16, !tbaa !12
  %16 = getelementptr inbounds i8, ptr %13, i64 201
  store i8 2, ptr %16, align 1, !tbaa !12
  %17 = getelementptr inbounds i8, ptr %13, i64 200
  store i8 -128, ptr %17, align 8, !tbaa !12
  %indvars.iv.next.1 = or disjoint i64 %indvars.iv, 2
  %18 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %5, i64 0, i64 %indvars.iv.next.1
  %19 = getelementptr inbounds i8, ptr %18, i64 64
  store i8 -128, ptr %19, align 32, !tbaa !12
  %20 = getelementptr inbounds i8, ptr %18, i64 160
  store i8 -128, ptr %20, align 16, !tbaa !12
  %21 = getelementptr inbounds i8, ptr %18, i64 201
  store i8 2, ptr %21, align 1, !tbaa !12
  %22 = getelementptr inbounds i8, ptr %18, i64 200
  store i8 -128, ptr %22, align 8, !tbaa !12
  %indvars.iv.next.2 = or disjoint i64 %indvars.iv, 3
  %23 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %5, i64 0, i64 %indvars.iv.next.2
  %24 = getelementptr inbounds i8, ptr %23, i64 64
  store i8 -128, ptr %24, align 32, !tbaa !12
  %25 = getelementptr inbounds i8, ptr %23, i64 160
  store i8 -128, ptr %25, align 16, !tbaa !12
  %26 = getelementptr inbounds i8, ptr %23, i64 201
  store i8 2, ptr %26, align 1, !tbaa !12
  %27 = getelementptr inbounds i8, ptr %23, i64 200
  store i8 -128, ptr %27, align 8, !tbaa !12
  %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
  %niter.next.3 = add i64 %niter, 4
  %niter.ncmp.3 = icmp eq i64 %niter.next.3, %unroll_iter
  br i1 %niter.ncmp.3, label %._crit_edge.unr-lcssa, label %7, !llvm.loop !13

._crit_edge.unr-lcssa:                            ; preds = %7, %.lr.ph
  %indvars.iv.unr = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next.3, %7 ]
  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
  br i1 %lcmp.mod.not, label %._crit_edge, label %.epil.preheader

.epil.preheader:                                  ; preds = %._crit_edge.unr-lcssa, %.epil.preheader
  %indvars.iv.epil = phi i64 [ %indvars.iv.next.epil, %.epil.preheader ], [ %indvars.iv.unr, %._crit_edge.unr-lcssa ]
  %epil.iter = phi i64 [ %epil.iter.next, %.epil.preheader ], [ 0, %._crit_edge.unr-lcssa ]
  %28 = getelementptr inbounds [32 x %struct.HMAC_SHA1_LANE_DATA], ptr %5, i64 0, i64 %indvars.iv.epil
  %29 = getelementptr inbounds i8, ptr %28, i64 64
  store i8 -128, ptr %29, align 32, !tbaa !12
  %30 = getelementptr inbounds i8, ptr %28, i64 160
  store i8 -128, ptr %30, align 16, !tbaa !12
  %31 = getelementptr inbounds i8, ptr %28, i64 201
  store i8 2, ptr %31, align 1, !tbaa !12
  %32 = getelementptr inbounds i8, ptr %28, i64 200
  store i8 -128, ptr %32, align 8, !tbaa !12
  %indvars.iv.next.epil = add nuw nsw i64 %indvars.iv.epil, 1
  %epil.iter.next = add i64 %epil.iter, 1
  %epil.iter.cmp.not = icmp eq i64 %epil.iter.next, %xtraiter
  br i1 %epil.iter.cmp.not, label %._crit_edge, label %.epil.preheader, !llvm.loop !15

._crit_edge:                                      ; preds = %.epil.preheader, %._crit_edge.unr-lcssa
  switch i32 %1, label %._crit_edge.thread [
    i32 8, label %._crit_edge.thread.sink.split
    i32 16, label %33
  ]

33:                                               ; preds = %._crit_edge
  br label %._crit_edge.thread.sink.split

._crit_edge.thread.sink.split:                    ; preds = %._crit_edge, %33
  %.sink = phi i64 [ -81985529216486896, %33 ], [ 66409738768, %._crit_edge ]
  %34 = getelementptr inbounds i8, ptr %0, i64 832
  store i64 %.sink, ptr %34, align 32, !tbaa !17
  br label %._crit_edge.thread

._crit_edge.thread:                               ; preds = %._crit_edge.thread.sink.split, %2, %._crit_edge
  ret void
}

attributes #0 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #1 = { nofree norecurse nosync nounwind memory(argmem: write) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 8036}
!6 = !{!"", !7, i64 0, !8, i64 768, !10, i64 832, !8, i64 864, !11, i64 8032, !11, i64 8036, !10, i64 8040}
!7 = !{!"", !8, i64 0, !8, i64 512}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"long", !8, i64 0}
!11 = !{!"int", !8, i64 0}
!12 = !{!8, !8, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.unroll.disable"}
!17 = !{!6, !10, i64 832}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass