; LLVM IR from tangjz/acm-icpc :: lydsy/4587.ll (Z6calc_1ii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mod = external dso_local global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z4initv() #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z6updateii(i32 noundef, i32 noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z5queryv() #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z6calc_1ii(i32 noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  %10 = load i32, ptr %4, align 4, !tbaa !5
  %11 = load i32, ptr %5, align 4, !tbaa !5
  %12 = icmp sgt i32 %10, %11
  br i1 %12, label %13, label %14

13:                                               ; preds = %2
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %5) #4
  br label %14

14:                                               ; preds = %13, %2
  %15 = load i32, ptr %4, align 4, !tbaa !5
  %16 = icmp slt i32 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %14
  store i32 0, ptr %3, align 4
  br label %71

18:                                               ; preds = %14
  %19 = load i32, ptr %4, align 4, !tbaa !5
  %20 = icmp ne i32 %19, 0
  br i1 %20, label %22, label %21

21:                                               ; preds = %18
  store i32 1, ptr %3, align 4
  br label %71

22:                                               ; preds = %18
  br label %23

23:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  store i32 0, ptr %6, align 4, !tbaa !5
  call void @_Z4initv()
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %24

24:                                               ; preds = %34, %23
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = icmp sle i32 %25, %26
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %37

29:                                               ; preds = %24
  %30 = load i32, ptr %5, align 4, !tbaa !5
  %31 = load i32, ptr %7, align 4, !tbaa !5
  %32 = add nsw i32 %30, %31
  call void @_Z6updateii(i32 noundef %32, i32 noundef 1)
  %33 = load i32, ptr %7, align 4, !tbaa !5
  call void @_Z6updateii(i32 noundef %33, i32 noundef -1)
  br label %34

34:                                               ; preds = %29
  %35 = load i32, ptr %7, align 4, !tbaa !5
  %36 = add nsw i32 %35, 1
  store i32 %36, ptr %7, align 4, !tbaa !5
  br label %24, !llvm.loop !9

37:                                               ; preds = %28
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 0, ptr %8, align 4, !tbaa !5
  br label %38

38:                                               ; preds = %65, %37
  %39 = load i32, ptr %8, align 4, !tbaa !5
  %40 = load i32, ptr %4, align 4, !tbaa !5
  %41 = icmp sle i32 %39, %40
  br i1 %41, label %43, label %42

42:                                               ; preds = %38
  store i32 5, ptr %9, align 4
  br label %68

43:                                               ; preds = %38
  %44 = load i32, ptr @mod, align 4, !tbaa !5
  %45 = call noundef i32 @_Z5queryv()
  %46 = sub nsw i32 %44, %45
  call void @_Z7mod_decRiii(ptr noundef nonnull align 4 dereferenceable(4) %6, i32 noundef %46, i32 noundef 1)
  %47 = load i32, ptr %8, align 4, !tbaa !5
  %48 = load i32, ptr %4, align 4, !tbaa !5
  %49 = icmp eq i32 %47, %48
  br i1 %49, label %50, label %51

50:                                               ; preds = %43
  store i32 5, ptr %9, align 4
  br label %68

51:                                               ; preds = %43
  %52 = load i32, ptr %4, align 4, !tbaa !5
  %53 = load i32, ptr %8, align 4, !tbaa !5
  %54 = sub nsw i32 %52, %53
  call void @_Z6updateii(i32 noundef %54, i32 noundef 1)
  %55 = load i32, ptr %5, align 4, !tbaa !5
  %56 = load i32, ptr %8, align 4, !tbaa !5
  %57 = sub nsw i32 %55, %56
  call void @_Z6updateii(i32 noundef %57, i32 noundef 1)
  %58 = load i32, ptr %4, align 4, !tbaa !5
  %59 = load i32, ptr %5, align 4, !tbaa !5
  %60 = add nsw i32 %58, %59
  %61 = load i32, ptr %8, align 4, !tbaa !5
  %62 = sub nsw i32 %60, %61
  call void @_Z6updateii(i32 noundef %62, i32 noundef -1)
  %63 = load i32, ptr %8, align 4, !tbaa !5
  %64 = add nsw i32 %63, 1
  call void @_Z6updateii(i32 noundef %64, i32 noundef -1)
  br label %65

65:                                               ; preds = %51
  %66 = load i32, ptr %8, align 4, !tbaa !5
  %67 = add nsw i32 %66, 1
  store i32 %67, ptr %8, align 4, !tbaa !5
  br label %38, !llvm.loop !11

68:                                               ; preds = %50, %42
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %69

69:                                               ; preds = %68
  %70 = load i32, ptr %6, align 4, !tbaa !5
  store i32 %70, ptr %3, align 4
  store i32 1, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  br label %71

71:                                               ; preds = %69, %21, %17
  %72 = load i32, ptr %3, align 4
  ret i32 %72
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z7mod_decRiii(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mod = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z4initv() local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z6updateii(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z5queryv() local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z6calc_1ii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #2 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %6 = icmp sgt i32 %0, %1
  br i1 %6, label %7, label %8

7:                                                ; preds = %2
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %4) #4
  %.pr = load i32, ptr %3, align 4, !tbaa !5
  br label %8

8:                                                ; preds = %7, %2
  %9 = phi i32 [ %.pr, %7 ], [ %0, %2 ]
  %10 = icmp slt i32 %9, 0
  br i1 %10, label %35, label %11

11:                                               ; preds = %8
  %.not = icmp eq i32 %9, 0
  br i1 %.not, label %35, label %12

12:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #4
  store i32 0, ptr %5, align 4, !tbaa !5
  call void @_Z4initv()
  %13 = load i32, ptr %3, align 4, !tbaa !5
  %.not1618 = icmp slt i32 %13, 1
  br i1 %.not1618, label %.preheader, label %.lr.ph

.preheader:                                       ; preds = %.lr.ph, %12
  %14 = phi i32 [ %13, %12 ], [ %18, %.lr.ph ]
  %.not1720 = icmp slt i32 %14, 0
  br i1 %.not1720, label %._crit_edge, label %.lr.ph22

.lr.ph:                                           ; preds = %12, %.lr.ph
  %.01219 = phi i32 [ %17, %.lr.ph ], [ 1, %12 ]
  %15 = load i32, ptr %4, align 4, !tbaa !5
  %16 = add nsw i32 %15, %.01219
  call void @_Z6updateii(i32 noundef %16, i32 noundef 1)
  call void @_Z6updateii(i32 noundef %.01219, i32 noundef -1)
  %17 = add nuw nsw i32 %.01219, 1
  %18 = load i32, ptr %3, align 4, !tbaa !5
  %.not16.not = icmp slt i32 %.01219, %18
  br i1 %.not16.not, label %.lr.ph, label %.preheader, !llvm.loop !9

.lr.ph22:                                         ; preds = %.preheader, %24
  %.021 = phi i32 [ %32, %24 ], [ 0, %.preheader ]
  %19 = load i32, ptr @mod, align 4, !tbaa !5
  %20 = call noundef i32 @_Z5queryv()
  %21 = sub nsw i32 %19, %20
  call void @_Z7mod_decRiii(ptr noundef nonnull align 4 dereferenceable(4) %5, i32 noundef %21, i32 noundef 1)
  %22 = load i32, ptr %3, align 4, !tbaa !5
  %23 = icmp eq i32 %.021, %22
  br i1 %23, label %._crit_edge.loopexit, label %24

24:                                               ; preds = %.lr.ph22
  %25 = sub nsw i32 %22, %.021
  call void @_Z6updateii(i32 noundef %25, i32 noundef 1)
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = sub nsw i32 %26, %.021
  call void @_Z6updateii(i32 noundef %27, i32 noundef 1)
  %28 = load i32, ptr %3, align 4, !tbaa !5
  %29 = load i32, ptr %4, align 4, !tbaa !5
  %30 = sub i32 %28, %.021
  %31 = add i32 %30, %29
  call void @_Z6updateii(i32 noundef %31, i32 noundef -1)
  %32 = add nuw nsw i32 %.021, 1
  call void @_Z6updateii(i32 noundef %32, i32 noundef -1)
  %33 = load i32, ptr %3, align 4, !tbaa !5
  %.not17.not = icmp slt i32 %.021, %33
  br i1 %.not17.not, label %.lr.ph22, label %._crit_edge.loopexit, !llvm.loop !11

._crit_edge.loopexit:                             ; preds = %.lr.ph22, %24
  %.pre = load i32, ptr %5, align 4, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.preheader
  %34 = phi i32 [ %.pre, %._crit_edge.loopexit ], [ 0, %.preheader ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #4
  br label %35

35:                                               ; preds = %11, %8, %._crit_edge
  %.013 = phi i32 [ %34, %._crit_edge ], [ 0, %8 ], [ 1, %11 ]
  ret i32 %.013
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z7mod_decRiii(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef, i32 noundef) local_unnamed_addr #3

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass