; LLVM IR from tangjz/acm-icpc :: codeforces/complete/1033D.ll (Z3gcdxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z3gcdxx(i64 noundef %0, i64 noundef %1) #1 {
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i32, align 4
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %6

6:                                                ; preds = %54, %2
  %7 = load i64, ptr %3, align 8, !tbaa !5
  %8 = icmp ne i64 %7, 0
  br i1 %8, label %9, label %58

9:                                                ; preds = %6
  br label %10

10:                                               ; preds = %22, %9
  %11 = load i64, ptr %3, align 8, !tbaa !5
  %12 = and i64 %11, 1
  %13 = icmp ne i64 %12, 0
  br i1 %13, label %19, label %14

14:                                               ; preds = %10
  %15 = load i64, ptr %4, align 8, !tbaa !5
  %16 = and i64 %15, 1
  %17 = icmp ne i64 %16, 0
  %18 = xor i1 %17, true
  br label %19

19:                                               ; preds = %14, %10
  %20 = phi i1 [ false, %10 ], [ %18, %14 ]
  br i1 %20, label %21, label %29

21:                                               ; preds = %19
  br label %22

22:                                               ; preds = %21
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = add nsw i32 %23, 1
  store i32 %24, ptr %5, align 4, !tbaa !9
  %25 = load i64, ptr %3, align 8, !tbaa !5
  %26 = ashr i64 %25, 1
  store i64 %26, ptr %3, align 8, !tbaa !5
  %27 = load i64, ptr %4, align 8, !tbaa !5
  %28 = ashr i64 %27, 1
  store i64 %28, ptr %4, align 8, !tbaa !5
  br label %10, !llvm.loop !11

29:                                               ; preds = %19
  br label %30

30:                                               ; preds = %36, %29
  %31 = load i64, ptr %3, align 8, !tbaa !5
  %32 = and i64 %31, 1
  %33 = icmp ne i64 %32, 0
  %34 = xor i1 %33, true
  br i1 %34, label %35, label %39

35:                                               ; preds = %30
  br label %36

36:                                               ; preds = %35
  %37 = load i64, ptr %3, align 8, !tbaa !5
  %38 = ashr i64 %37, 1
  store i64 %38, ptr %3, align 8, !tbaa !5
  br label %30, !llvm.loop !13

39:                                               ; preds = %30
  br label %40

40:                                               ; preds = %46, %39
  %41 = load i64, ptr %4, align 8, !tbaa !5
  %42 = and i64 %41, 1
  %43 = icmp ne i64 %42, 0
  %44 = xor i1 %43, true
  br i1 %44, label %45, label %49

45:                                               ; preds = %40
  br label %46

46:                                               ; preds = %45
  %47 = load i64, ptr %4, align 8, !tbaa !5
  %48 = ashr i64 %47, 1
  store i64 %48, ptr %4, align 8, !tbaa !5
  br label %40, !llvm.loop !14

49:                                               ; preds = %40
  %50 = load i64, ptr %3, align 8, !tbaa !5
  %51 = load i64, ptr %4, align 8, !tbaa !5
  %52 = icmp slt i64 %50, %51
  br i1 %52, label %53, label %54

53:                                               ; preds = %49
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef nonnull align 8 dereferenceable(8) %4) #3
  br label %54

54:                                               ; preds = %53, %49
  %55 = load i64, ptr %4, align 8, !tbaa !5
  %56 = load i64, ptr %3, align 8, !tbaa !5
  %57 = sub nsw i64 %56, %55
  store i64 %57, ptr %3, align 8, !tbaa !5
  br label %6, !llvm.loop !15

58:                                               ; preds = %6
  %59 = load i64, ptr %4, align 8, !tbaa !5
  %60 = load i32, ptr %5, align 4, !tbaa !9
  %61 = zext i32 %60 to i64
  %62 = shl i64 %59, %61
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i64 %62
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z3gcdxx(i64 noundef %0, i64 noundef %1) local_unnamed_addr #0 {
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !5
  %.not25 = icmp eq i64 %0, 0
  br i1 %.not25, label %._crit_edge27, label %.preheader7

.preheader7:                                      ; preds = %2, %30
  %5 = phi i64 [ %32, %30 ], [ %1, %2 ]
  %.promoted = phi i64 [ %33, %30 ], [ %0, %2 ]
  %.026 = phi i32 [ %.1.lcssa, %30 ], [ 0, %2 ]
  %6 = or i64 %.promoted, %5
  %7 = and i64 %6, 1
  %8 = icmp eq i64 %7, 0
  br i1 %8, label %.lr.ph, label %.preheader6

..preheader6_crit_edge:                           ; preds = %.lr.ph
  store i64 %14, ptr %3, align 8, !tbaa !5
  store i64 %15, ptr %4, align 8, !tbaa !5
  br label %.preheader6

.preheader6:                                      ; preds = %..preheader6_crit_edge, %.preheader7
  %9 = phi i64 [ %15, %..preheader6_crit_edge ], [ %5, %.preheader7 ]
  %.promoted15 = phi i64 [ %14, %..preheader6_crit_edge ], [ %.promoted, %.preheader7 ]
  %.1.lcssa = phi i32 [ %13, %..preheader6_crit_edge ], [ %.026, %.preheader7 ]
  %10 = and i64 %.promoted15, 1
  %.not416 = icmp eq i64 %10, 0
  br i1 %.not416, label %.lr.ph17, label %.preheader

.lr.ph:                                           ; preds = %.preheader7, %.lr.ph
  %.112 = phi i32 [ %13, %.lr.ph ], [ %.026, %.preheader7 ]
  %11 = phi i64 [ %14, %.lr.ph ], [ %.promoted, %.preheader7 ]
  %12 = phi i64 [ %15, %.lr.ph ], [ %5, %.preheader7 ]
  %13 = add nsw i32 %.112, 1
  %14 = ashr exact i64 %11, 1
  %15 = ashr exact i64 %12, 1
  %16 = and i64 %11, 2
  %.not2 = icmp eq i64 %16, 0
  %17 = and i64 %12, 2
  %.not3 = icmp eq i64 %17, 0
  %18 = select i1 %.not2, i1 %.not3, i1 false
  br i1 %18, label %.lr.ph, label %..preheader6_crit_edge, !llvm.loop !9

..preheader_crit_edge:                            ; preds = %.lr.ph17
  store i64 %21, ptr %3, align 8, !tbaa !5
  br label %.preheader

.preheader:                                       ; preds = %..preheader_crit_edge, %.preheader6
  %.lcssa = phi i64 [ %21, %..preheader_crit_edge ], [ %.promoted15, %.preheader6 ]
  %19 = and i64 %9, 1
  %.not521 = icmp eq i64 %19, 0
  br i1 %.not521, label %.lr.ph22, label %26

.lr.ph17:                                         ; preds = %.preheader6, %.lr.ph17
  %20 = phi i64 [ %21, %.lr.ph17 ], [ %.promoted15, %.preheader6 ]
  %21 = ashr exact i64 %20, 1
  %22 = and i64 %20, 2
  %.not4 = icmp eq i64 %22, 0
  br i1 %.not4, label %.lr.ph17, label %..preheader_crit_edge, !llvm.loop !11

.lr.ph22:                                         ; preds = %.preheader, %.lr.ph22
  %23 = phi i64 [ %24, %.lr.ph22 ], [ %9, %.preheader ]
  %24 = ashr exact i64 %23, 1
  %25 = and i64 %23, 2
  %.not5 = icmp eq i64 %25, 0
  br i1 %.not5, label %.lr.ph22, label %._crit_edge, !llvm.loop !12

._crit_edge:                                      ; preds = %.lr.ph22
  store i64 %24, ptr %4, align 8, !tbaa !5
  br label %26

26:                                               ; preds = %._crit_edge, %.preheader
  %27 = phi i64 [ %24, %._crit_edge ], [ %9, %.preheader ]
  %28 = icmp slt i64 %.lcssa, %27
  br i1 %28, label %29, label %30

29:                                               ; preds = %26
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef nonnull align 8 dereferenceable(8) %4) #2
  %.pre = load i64, ptr %4, align 8
  %.pre38 = load i64, ptr %3, align 8, !tbaa !5
  br label %30

30:                                               ; preds = %29, %26
  %31 = phi i64 [ %.pre38, %29 ], [ %.lcssa, %26 ]
  %32 = phi i64 [ %.pre, %29 ], [ %27, %26 ]
  %33 = sub nsw i64 %31, %32
  store i64 %33, ptr %3, align 8, !tbaa !5
  %.not = icmp eq i64 %31, %32
  br i1 %.not, label %._crit_edge27.loopexit, label %.preheader7, !llvm.loop !13

._crit_edge27.loopexit:                           ; preds = %30
  %34 = zext nneg i32 %.1.lcssa to i64
  br label %._crit_edge27

._crit_edge27:                                    ; preds = %._crit_edge27.loopexit, %2
  %35 = phi i64 [ %1, %2 ], [ %31, %._crit_edge27.loopexit ]
  %.0.lcssa = phi i64 [ 0, %2 ], [ %34, %._crit_edge27.loopexit ]
  %36 = shl i64 %35, %.0.lcssa
  ret i64 %36
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass