; LLVM IR from ubaldot/defrecs :: stm32f4x/ADC_Readings/Drivers/CMSIS/DSP/Source/FastMathFunctions (q15)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_divide_q15(i16 noundef signext %0, i16 noundef signext %1, ptr noundef %2, ptr noundef %3) #2 {
  %5 = alloca i32, align 4
  %6 = alloca i16, align 2
  %7 = alloca i16, align 2
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i16, align 2
  %11 = alloca i32, align 4
  %12 = alloca i16, align 2
  %13 = alloca i32, align 4
  store i16 %0, ptr %6, align 2, !tbaa !5
  store i16 %1, ptr %7, align 2, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #4
  store i16 0, ptr %10, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %12) #4
  %14 = load ptr, ptr %9, align 8, !tbaa !9
  store i16 0, ptr %14, align 2, !tbaa !5
  %15 = load i16, ptr %6, align 2, !tbaa !5
  %16 = sext i16 %15 to i32
  %17 = ashr i32 %16, 15
  %18 = load i16, ptr %7, align 2, !tbaa !5
  %19 = sext i16 %18 to i32
  %20 = ashr i32 %19, 15
  %21 = xor i32 %17, %20
  %22 = trunc i32 %21 to i16
  store i16 %22, ptr %10, align 2, !tbaa !5
  %23 = load i16, ptr %7, align 2, !tbaa !5
  %24 = sext i16 %23 to i32
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %34

26:                                               ; preds = %4
  %27 = load i16, ptr %10, align 2, !tbaa !5
  %28 = icmp ne i16 %27, 0
  br i1 %28, label %29, label %31

29:                                               ; preds = %26
  %30 = load ptr, ptr %8, align 8, !tbaa !9
  store i16 -32768, ptr %30, align 2, !tbaa !5
  br label %33

31:                                               ; preds = %26
  %32 = load ptr, ptr %8, align 8, !tbaa !9
  store i16 32767, ptr %32, align 2, !tbaa !5
  br label %33

33:                                               ; preds = %31, %29
  store i32 -4, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %66

34:                                               ; preds = %4
  call void @arm_abs_q15(ptr noundef %6, ptr noundef %6, i32 noundef 1)
  call void @arm_abs_q15(ptr noundef %7, ptr noundef %7, i32 noundef 1)
  %35 = load i16, ptr %6, align 2, !tbaa !5
  %36 = sext i16 %35 to i32
  %37 = shl i32 %36, 15
  %38 = load i16, ptr %7, align 2, !tbaa !5
  %39 = sext i16 %38 to i32
  %40 = sdiv i32 %37, %39
  store i32 %40, ptr %11, align 4, !tbaa !11
  %41 = load i32, ptr %11, align 4, !tbaa !11
  %42 = call zeroext i8 @__CLZ(i32 noundef %41)
  %43 = zext i8 %42 to i32
  %44 = sub nsw i32 17, %43
  %45 = trunc i32 %44 to i16
  store i16 %45, ptr %12, align 2, !tbaa !5
  %46 = load i16, ptr %12, align 2, !tbaa !5
  %47 = sext i16 %46 to i32
  %48 = icmp sgt i32 %47, 0
  br i1 %48, label %49, label %56

49:                                               ; preds = %34
  %50 = load i16, ptr %12, align 2, !tbaa !5
  %51 = load ptr, ptr %9, align 8, !tbaa !9
  store i16 %50, ptr %51, align 2, !tbaa !5
  %52 = load i32, ptr %11, align 4, !tbaa !11
  %53 = load i16, ptr %12, align 2, !tbaa !5
  %54 = sext i16 %53 to i32
  %55 = ashr i32 %52, %54
  store i32 %55, ptr %11, align 4, !tbaa !11
  br label %56

56:                                               ; preds = %49, %34
  %57 = load i16, ptr %10, align 2, !tbaa !5
  %58 = icmp ne i16 %57, 0
  br i1 %58, label %59, label %62

59:                                               ; preds = %56
  %60 = load i32, ptr %11, align 4, !tbaa !11
  %61 = sub nsw i32 0, %60
  store i32 %61, ptr %11, align 4, !tbaa !11
  br label %62

62:                                               ; preds = %59, %56
  %63 = load i32, ptr %11, align 4, !tbaa !11
  %64 = trunc i32 %63 to i16
  %65 = load ptr, ptr %8, align 8, !tbaa !9
  store i16 %64, ptr %65, align 2, !tbaa !5
  store i32 0, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %66

66:                                               ; preds = %62, %33
  call void @llvm.lifetime.end.p0(i64 2, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #4
  %67 = load i32, ptr %5, align 4
  ret i32 %67
}

declare void @arm_abs_q15(ptr noundef, ptr noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 -4, 1) i32 @arm_divide_q15(i16 noundef signext %0, i16 noundef signext %1, ptr nocapture noundef writeonly %2, ptr nocapture noundef writeonly %3) local_unnamed_addr #1 {
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  store i16 %0, ptr %5, align 2, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !5
  store i16 0, ptr %3, align 2, !tbaa !5
  %7 = xor i16 %1, %0
  %8 = icmp eq i16 %1, 0
  br i1 %8, label %9, label %10

9:                                                ; preds = %4
  %.not16 = icmp sgt i16 %0, -1
  %. = select i1 %.not16, i16 32767, i16 -32768
  br label %27

10:                                               ; preds = %4
  call void @arm_abs_q15(ptr noundef nonnull %5, ptr noundef nonnull %5, i32 noundef 1) #3
  call void @arm_abs_q15(ptr noundef nonnull %6, ptr noundef nonnull %6, i32 noundef 1) #3
  %11 = load i16, ptr %5, align 2, !tbaa !5
  %12 = sext i16 %11 to i32
  %13 = shl nsw i32 %12, 15
  %14 = load i16, ptr %6, align 2, !tbaa !5
  %15 = sext i16 %14 to i32
  %16 = sdiv i32 %13, %15
  %17 = call zeroext i8 @__CLZ(i32 noundef %16)
  %18 = icmp ult i8 %17, 17
  br i1 %18, label %19, label %24

19:                                               ; preds = %10
  %20 = zext nneg i8 %17 to i16
  %21 = sub nuw nsw i16 17, %20
  store i16 %21, ptr %3, align 2, !tbaa !5
  %22 = zext nneg i16 %21 to i32
  %23 = ashr i32 %16, %22
  br label %24

24:                                               ; preds = %19, %10
  %.014 = phi i32 [ %23, %19 ], [ %16, %10 ]
  %25 = sub nsw i32 0, %.014
  %.not18 = icmp slt i16 %7, 0
  %spec.select = select i1 %.not18, i32 %25, i32 %.014
  %26 = trunc i32 %spec.select to i16
  br label %27

27:                                               ; preds = %24, %9
  %storemerge17 = phi i16 [ %., %9 ], [ %26, %24 ]
  %.0 = phi i32 [ -4, %9 ], [ 0, %24 ]
  store i16 %storemerge17, ptr %2, align 2, !tbaa !5
  ret i32 %.0
}

declare void @arm_abs_q15(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass