; LLVM IR from CRAFT-THU/BSim :: src/neuron/constant/ConstantNeuron.ll (ZN14ConstantNeuronC2ERKS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.ConstantNeuron = type { %class.NeuronBase.base, float, i32, i32, float, float, ptr }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>

@_ZTV14ConstantNeuron = external dso_local unnamed_addr constant { [19 x ptr] }, align 8

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN14ConstantNeuronC2ERKS_(ptr noundef nonnull align 8 dereferenceable(80) %0, ptr noundef nonnull align 8 dereferenceable(80) %1) unnamed_addr #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %5, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 136) ({ [19 x ptr] }, ptr @_ZTV14ConstantNeuron, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !9
  %6 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 6
  store ptr null, ptr %6, align 8, !tbaa !11
  %7 = getelementptr inbounds %class.NeuronBase, ptr %5, i32 0, i32 2
  store i8 0, ptr %7, align 8, !tbaa !22
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = getelementptr inbounds %class.ConstantNeuron, ptr %8, i32 0, i32 1
  %10 = load float, ptr %9, align 4, !tbaa !23
  %11 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 1
  store float %10, ptr %11, align 4, !tbaa !23
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %class.ConstantNeuron, ptr %12, i32 0, i32 4
  %14 = load float, ptr %13, align 8, !tbaa !24
  %15 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 4
  store float %14, ptr %15, align 8, !tbaa !24
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %class.ConstantNeuron, ptr %16, i32 0, i32 5
  %18 = load float, ptr %17, align 4, !tbaa !25
  %19 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 5
  store float %18, ptr %19, align 4, !tbaa !25
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %class.NeuronBase, ptr %20, i32 0, i32 3
  %22 = load i8, ptr %21, align 1, !tbaa !26, !range !27, !noundef !28
  %23 = trunc i8 %22 to i1
  %24 = getelementptr inbounds %class.NeuronBase, ptr %5, i32 0, i32 3
  %25 = zext i1 %23 to i8
  store i8 %25, ptr %24, align 1, !tbaa !26
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 72}
!12 = !{!"_ZTS14ConstantNeuron", !13, i64 0, !21, i64 52, !15, i64 56, !15, i64 60, !21, i64 64, !21, i64 68, !6, i64 72}
!13 = !{!"_ZTS10NeuronBase", !14, i64 0, !16, i64 16, !20, i64 40, !20, i64 41, !15, i64 44, !21, i64 48}
!14 = !{!"_ZTS4Base", !15, i64 8, !15, i64 12}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"float", !7, i64 0}
!22 = !{!13, !20, i64 40}
!23 = !{!12, !21, i64 52}
!24 = !{!12, !21, i64 64}
!25 = !{!12, !21, i64 68}
!26 = !{!13, !20, i64 41}
!27 = !{i8 0, i8 2}
!28 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV14ConstantNeuron = external dso_local unnamed_addr constant { [19 x ptr] }, align 8

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN14ConstantNeuronC2ERKS_(ptr noundef nonnull align 8 dereferenceable(80) %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(80) %1) unnamed_addr #1 align 2 {
  tail call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %0, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 136) (i8, ptr @_ZTV14ConstantNeuron, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 72
  store ptr null, ptr %3, align 8, !tbaa !8
  %4 = getelementptr inbounds i8, ptr %0, i64 40
  store i8 0, ptr %4, align 8, !tbaa !21
  %5 = getelementptr inbounds i8, ptr %1, i64 52
  %6 = load float, ptr %5, align 4, !tbaa !22
  %7 = getelementptr inbounds i8, ptr %0, i64 52
  store float %6, ptr %7, align 4, !tbaa !22
  %8 = getelementptr inbounds i8, ptr %1, i64 64
  %9 = getelementptr inbounds i8, ptr %0, i64 64
  %10 = load <2 x float>, ptr %8, align 8, !tbaa !23
  store <2 x float> %10, ptr %9, align 8, !tbaa !23
  %11 = getelementptr inbounds i8, ptr %1, i64 41
  %12 = load i8, ptr %11, align 1, !tbaa !24, !range !25, !noundef !26
  %13 = getelementptr inbounds i8, ptr %0, i64 41
  store i8 %12, ptr %13, align 1, !tbaa !24
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !18, i64 72}
!9 = !{!"_ZTS14ConstantNeuron", !10, i64 0, !20, i64 52, !12, i64 56, !12, i64 60, !20, i64 64, !20, i64 68, !18, i64 72}
!10 = !{!"_ZTS10NeuronBase", !11, i64 0, !14, i64 16, !19, i64 40, !19, i64 41, !12, i64 44, !20, i64 48}
!11 = !{!"_ZTS4Base", !12, i64 8, !12, i64 12}
!12 = !{!"int", !13, i64 0}
!13 = !{!"omnipotent char", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!18 = !{!"any pointer", !13, i64 0}
!19 = !{!"bool", !13, i64 0}
!20 = !{!"float", !13, i64 0}
!21 = !{!10, !19, i64 40}
!22 = !{!9, !20, i64 52}
!23 = !{!20, !20, i64 0}
!24 = !{!10, !19, i64 41}
!25 = !{i8 0, i8 2}
!26 = !{}


; Effective O3 passes: IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,TailCallElimPass