; LLVM IR from CRAFT-THU/BSim :: src/neuron/max/MaxNeuron.ll (ZN9MaxNeuron6updateER7SimInfo)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.MaxNeuron = type <{ %class.NeuronBase.base, [4 x i8], ptr, i32, i32, i32, [4 x i8] }>
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SimInfo = type { i32, float, %"class.std::vector.0", %"class.std::vector.5" }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN9MaxNeuron6updateER7SimInfo(ptr noundef nonnull align 8 dereferenceable(76) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) unnamed_addr #0 align 2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  %11 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #3
  store i8 0, ptr %6, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 1, ptr %7, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %12

12:                                               ; preds = %46, %2
  %13 = load i32, ptr %8, align 4, !tbaa !11
  %14 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 5
  %15 = load i32, ptr %14, align 8, !tbaa !13
  %16 = icmp slt i32 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %49

18:                                               ; preds = %12
  %19 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 4
  %20 = load i32, ptr %19, align 4, !tbaa !22
  %21 = load i32, ptr %7, align 4, !tbaa !11
  %22 = and i32 %20, %21
  %23 = icmp ne i32 %22, 0
  br i1 %23, label %24, label %43

24:                                               ; preds = %18
  %25 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 2
  %26 = load ptr, ptr %25, align 8, !tbaa !23
  %27 = load i32, ptr %8, align 4, !tbaa !11
  %28 = sext i32 %27 to i64
  %29 = getelementptr inbounds i32, ptr %26, i64 %28
  %30 = load i32, ptr %29, align 4, !tbaa !11
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %29, align 4, !tbaa !11
  %32 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 2
  %33 = load ptr, ptr %32, align 8, !tbaa !23
  %34 = load i32, ptr %8, align 4, !tbaa !11
  %35 = sext i32 %34 to i64
  %36 = getelementptr inbounds i32, ptr %33, i64 %35
  %37 = load i32, ptr %36, align 4, !tbaa !11
  %38 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 3
  %39 = load i32, ptr %38, align 8, !tbaa !24
  %40 = icmp sgt i32 %37, %39
  br i1 %40, label %41, label %42

41:                                               ; preds = %24
  store i8 1, ptr %6, align 1, !tbaa !9
  br label %42

42:                                               ; preds = %41, %24
  br label %43

43:                                               ; preds = %42, %18
  %44 = load i32, ptr %7, align 4, !tbaa !11
  %45 = shl i32 %44, 1
  store i32 %45, ptr %7, align 4, !tbaa !11
  br label %46

46:                                               ; preds = %43
  %47 = load i32, ptr %8, align 4, !tbaa !11
  %48 = add nsw i32 %47, 1
  store i32 %48, ptr %8, align 4, !tbaa !11
  br label %12, !llvm.loop !25

49:                                               ; preds = %17
  %50 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 4
  store i32 0, ptr %50, align 4, !tbaa !22
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.SimInfo, ptr %51, i32 0, i32 2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %53 = load i8, ptr %6, align 1, !tbaa !9, !range !27, !noundef !28
  %54 = trunc i8 %53 to i1
  %55 = zext i1 %54 to i32
  store i32 %55, ptr %9, align 4, !tbaa !11
  call void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24) %52, ptr noundef nonnull align 4 dereferenceable(4) %9)
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  %56 = load i8, ptr %6, align 1, !tbaa !9, !range !27, !noundef !28
  %57 = trunc i8 %56 to i1
  br i1 %57, label %58, label %66

58:                                               ; preds = %49
  %59 = getelementptr inbounds %class.MaxNeuron, ptr %11, i32 0, i32 3
  %60 = load i32, ptr %59, align 8, !tbaa !24
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %59, align 8, !tbaa !24
  %62 = call noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52) %11)
  %63 = getelementptr inbounds %class.NeuronBase, ptr %11, i32 0, i32 5
  %64 = load i32, ptr %63, align 4, !tbaa !29
  %65 = add nsw i32 %64, 1
  store i32 %65, ptr %63, align 4, !tbaa !29
  store i32 1, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %67

66:                                               ; preds = %49
  store i32 -1, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %67

67:                                               ; preds = %66, %58
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #3
  %68 = load i32, ptr %3, align 4
  ret i32 %68
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

declare noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52)) unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 72}
!14 = !{!"_ZTS9MaxNeuron", !15, i64 0, !6, i64 56, !12, i64 64, !12, i64 68, !12, i64 72}
!15 = !{!"_ZTS10NeuronBase", !16, i64 0, !17, i64 16, !10, i64 40, !10, i64 41, !12, i64 44, !21, i64 48}
!16 = !{!"_ZTS4Base", !12, i64 8, !12, i64 12}
!17 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"float", !7, i64 0}
!22 = !{!14, !12, i64 68}
!23 = !{!14, !6, i64 56}
!24 = !{!14, !12, i64 64}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = !{i8 0, i8 2}
!28 = !{}
!29 = !{!15, !12, i64 44}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef range(i32 -1, 2) i32 @_ZN9MaxNeuron6updateER7SimInfo(ptr noundef nonnull align 8 dereferenceable(76) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) unnamed_addr #0 align 2 {
  %3 = alloca i32, align 4
  %4 = getelementptr inbounds i8, ptr %0, i64 72
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp sgt i32 %5, 0
  br i1 %6, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 68
  %8 = getelementptr inbounds i8, ptr %0, i64 56
  %9 = load ptr, ptr %8, align 8
  %10 = getelementptr inbounds i8, ptr %0, i64 64
  br label %15

._crit_edge:                                      ; preds = %24, %2
  %.011.lcssa = phi i8 [ 0, %2 ], [ %.1, %24 ]
  %11 = getelementptr inbounds i8, ptr %0, i64 68
  store i32 0, ptr %11, align 4, !tbaa !19
  %12 = getelementptr inbounds i8, ptr %1, i64 8
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #3
  %13 = trunc nuw i8 %.011.lcssa to i1
  %.mask = and i8 %.011.lcssa, 1
  %14 = zext nneg i8 %.mask to i32
  store i32 %14, ptr %3, align 4, !tbaa !20
  call void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24) %12, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #3
  br i1 %13, label %29, label %37

15:                                               ; preds = %.lr.ph, %24
  %16 = phi i32 [ %5, %.lr.ph ], [ %25, %24 ]
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %24 ]
  %.01015 = phi i32 [ 1, %.lr.ph ], [ %26, %24 ]
  %.01114 = phi i8 [ 0, %.lr.ph ], [ %.1, %24 ]
  %17 = load i32, ptr %7, align 4, !tbaa !19
  %18 = and i32 %17, %.01015
  %.not = icmp eq i32 %18, 0
  br i1 %.not, label %24, label %19

19:                                               ; preds = %15
  %20 = getelementptr inbounds i32, ptr %9, i64 %indvars.iv
  %21 = load i32, ptr %20, align 4, !tbaa !20
  %22 = add nsw i32 %21, 1
  store i32 %22, ptr %20, align 4, !tbaa !20
  %23 = load i32, ptr %10, align 8, !tbaa !21
  %.not13 = icmp slt i32 %21, %23
  %spec.select = select i1 %.not13, i8 %.01114, i8 1
  %.pre = load i32, ptr %4, align 8, !tbaa !5
  br label %24

24:                                               ; preds = %19, %15
  %25 = phi i32 [ %16, %15 ], [ %.pre, %19 ]
  %.1 = phi i8 [ %.01114, %15 ], [ %spec.select, %19 ]
  %26 = shl i32 %.01015, 1
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %27 = sext i32 %25 to i64
  %28 = icmp slt i64 %indvars.iv.next, %27
  br i1 %28, label %15, label %._crit_edge, !llvm.loop !22

29:                                               ; preds = %._crit_edge
  %30 = getelementptr inbounds i8, ptr %0, i64 64
  %31 = load i32, ptr %30, align 8, !tbaa !21
  %32 = add nsw i32 %31, 1
  store i32 %32, ptr %30, align 8, !tbaa !21
  %33 = call noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52) %0)
  %34 = getelementptr inbounds i8, ptr %0, i64 44
  %35 = load i32, ptr %34, align 4, !tbaa !24
  %36 = add nsw i32 %35, 1
  store i32 %36, ptr %34, align 4, !tbaa !24
  br label %37

37:                                               ; preds = %._crit_edge, %29
  %.012 = phi i32 [ 1, %29 ], [ -1, %._crit_edge ]
  ret i32 %.012
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

declare noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52)) unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 72}
!6 = !{!"_ZTS9MaxNeuron", !7, i64 0, !16, i64 56, !9, i64 64, !9, i64 68, !9, i64 72}
!7 = !{!"_ZTS10NeuronBase", !8, i64 0, !12, i64 16, !17, i64 40, !17, i64 41, !9, i64 44, !18, i64 48}
!8 = !{!"_ZTS4Base", !9, i64 8, !9, i64 12}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!16 = !{!"any pointer", !10, i64 0}
!17 = !{!"bool", !10, i64 0}
!18 = !{!"float", !10, i64 0}
!19 = !{!6, !9, i64 68}
!20 = !{!9, !9, i64 0}
!21 = !{!6, !9, i64 64}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}
!24 = !{!7, !9, i64 44}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass