; LLVM IR from CRAFT-THU/BSim :: src/neuron/poisson/PoissonNeuron.ll (ZN13PoissonNeuron6updateER7SimInfo)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.PoissonNeuron = type { %class.NeuronBase.base, %"class.std::vector", %"class.std::linear_congruential_engine", %"class.std::poisson_distribution", float, float, float, float, i8, i8, i32, i32, i32, i32, ptr }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::linear_congruential_engine" = type { i64 }
%"class.std::poisson_distribution" = type { %"struct.std::poisson_distribution<>::param_type", %"class.std::normal_distribution" }
%"struct.std::poisson_distribution<>::param_type" = type { double, double, double, double, double, double, double, double, double }
%"class.std::normal_distribution" = type <{ %"struct.std::normal_distribution<>::param_type", double, i8, [7 x i8] }>
%"struct.std::normal_distribution<>::param_type" = type { double, double }
%struct.SimInfo = type { i32, float, %"class.std::vector.0", %"class.std::vector.5" }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZNSt20poisson_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_(ptr noundef nonnull align 8 dereferenceable(104), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN13PoissonNeuron6updateER7SimInfo(ptr noundef nonnull align 8 dereferenceable(240) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) unnamed_addr #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  %7 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 8
  store i8 0, ptr %7, align 8, !tbaa !9
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.SimInfo, ptr %8, i32 0, i32 0
  %10 = load i32, ptr %9, align 8, !tbaa !27
  %11 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 11
  %12 = load i32, ptr %11, align 8, !tbaa !37
  %13 = icmp eq i32 %10, %12
  br i1 %13, label %14, label %34

14:                                               ; preds = %2
  %15 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 11
  %16 = load i32, ptr %15, align 8, !tbaa !37
  %17 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 12
  %18 = load i32, ptr %17, align 4, !tbaa !38
  %19 = icmp slt i32 %16, %18
  br i1 %19, label %20, label %34

20:                                               ; preds = %14
  %21 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 8
  store i8 1, ptr %21, align 8, !tbaa !9
  %22 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 11
  %23 = load i32, ptr %22, align 8, !tbaa !37
  %24 = add nsw i32 %23, 1
  %25 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 3
  %26 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 2
  %27 = call noundef i32 @_ZNSt20poisson_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_(ptr noundef nonnull align 8 dereferenceable(104) %25, ptr noundef nonnull align 8 dereferenceable(8) %26)
  %28 = add nsw i32 %24, %27
  %29 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 11
  store i32 %28, ptr %29, align 8, !tbaa !37
  %30 = call noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52) %6)
  %31 = getelementptr inbounds %class.NeuronBase, ptr %6, i32 0, i32 5
  %32 = load i32, ptr %31, align 4, !tbaa !39
  %33 = add nsw i32 %32, 1
  store i32 %33, ptr %31, align 4, !tbaa !39
  br label %34

34:                                               ; preds = %20, %14, %2
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.SimInfo, ptr %35, i32 0, i32 2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %37 = getelementptr inbounds %class.PoissonNeuron, ptr %6, i32 0, i32 8
  %38 = load i8, ptr %37, align 8, !tbaa !9, !range !40, !noundef !41
  %39 = trunc i8 %38 to i1
  %40 = zext i1 %39 to i32
  store i32 %40, ptr %5, align 4, !tbaa !42
  call void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24) %36, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i32 0
}

declare noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52)) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !18, i64 208}
!10 = !{!"_ZTS13PoissonNeuron", !11, i64 0, !14, i64 56, !20, i64 80, !22, i64 88, !19, i64 192, !19, i64 196, !19, i64 200, !19, i64 204, !18, i64 208, !18, i64 209, !13, i64 212, !13, i64 216, !13, i64 220, !13, i64 224, !6, i64 232}
!11 = !{!"_ZTS10NeuronBase", !12, i64 0, !14, i64 16, !18, i64 40, !18, i64 41, !13, i64 44, !19, i64 48}
!12 = !{!"_ZTS4Base", !13, i64 8, !13, i64 12}
!13 = !{!"int", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"bool", !7, i64 0}
!19 = !{!"float", !7, i64 0}
!20 = !{!"_ZTSSt26linear_congruential_engineImLm16807ELm0ELm2147483647EE", !21, i64 0}
!21 = !{!"long", !7, i64 0}
!22 = !{!"_ZTSSt20poisson_distributionIiE", !23, i64 0, !25, i64 72}
!23 = !{!"_ZTSNSt20poisson_distributionIiE10param_typeE", !24, i64 0, !24, i64 8, !24, i64 16, !24, i64 24, !24, i64 32, !24, i64 40, !24, i64 48, !24, i64 56, !24, i64 64}
!24 = !{!"double", !7, i64 0}
!25 = !{!"_ZTSSt19normal_distributionIdE", !26, i64 0, !24, i64 16, !18, i64 24}
!26 = !{!"_ZTSNSt19normal_distributionIdE10param_typeE", !24, i64 0, !24, i64 8}
!27 = !{!28, !13, i64 0}
!28 = !{!"_ZTS7SimInfo", !13, i64 0, !19, i64 4, !29, i64 8, !33, i64 32}
!29 = !{!"_ZTSSt6vectorIiSaIiEE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorIfSaIfEE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!10, !13, i64 216}
!38 = !{!10, !13, i64 220}
!39 = !{!11, !13, i64 44}
!40 = !{i8 0, i8 2}
!41 = !{}
!42 = !{!13, !13, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZNSt20poisson_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_(ptr noundef nonnull align 8 dereferenceable(104), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN13PoissonNeuron6updateER7SimInfo(ptr noundef nonnull align 8 dereferenceable(240) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) unnamed_addr #1 align 2 {
  %3 = alloca i32, align 4
  %4 = getelementptr inbounds i8, ptr %0, i64 208
  store i8 0, ptr %4, align 8, !tbaa !5
  %5 = load i32, ptr %1, align 8, !tbaa !26
  %6 = getelementptr inbounds i8, ptr %0, i64 216
  %7 = load i32, ptr %6, align 8, !tbaa !36
  %8 = icmp eq i32 %5, %7
  %9 = getelementptr inbounds i8, ptr %0, i64 220
  %10 = load i32, ptr %9, align 4
  %11 = icmp slt i32 %7, %10
  %or.cond = select i1 %8, i1 %11, i1 false
  br i1 %or.cond, label %12, label %23

12:                                               ; preds = %2
  store i8 1, ptr %4, align 8, !tbaa !5
  %13 = add nsw i32 %5, 1
  %14 = getelementptr inbounds i8, ptr %0, i64 88
  %15 = getelementptr inbounds i8, ptr %0, i64 80
  %16 = tail call noundef i32 @_ZNSt20poisson_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_(ptr noundef nonnull align 8 dereferenceable(104) %14, ptr noundef nonnull align 8 dereferenceable(8) %15)
  %17 = add nsw i32 %13, %16
  store i32 %17, ptr %6, align 8, !tbaa !36
  %18 = tail call noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52) %0)
  %19 = getelementptr inbounds i8, ptr %0, i64 44
  %20 = load i32, ptr %19, align 4, !tbaa !37
  %21 = add nsw i32 %20, 1
  store i32 %21, ptr %19, align 4, !tbaa !37
  %.pre = load i8, ptr %4, align 8, !tbaa !5, !range !38
  %22 = zext nneg i8 %.pre to i32
  br label %23

23:                                               ; preds = %12, %2
  %24 = phi i32 [ %22, %12 ], [ 0, %2 ]
  %25 = getelementptr inbounds i8, ptr %1, i64 8
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #3
  store i32 %24, ptr %3, align 4, !tbaa !39
  call void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24) %25, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #3
  ret i32 0
}

declare noundef i32 @_ZN10NeuronBase4fireEv(ptr noundef nonnull align 8 dereferenceable(52)) unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backEOi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !17, i64 208}
!6 = !{!"_ZTS13PoissonNeuron", !7, i64 0, !12, i64 56, !19, i64 80, !21, i64 88, !18, i64 192, !18, i64 196, !18, i64 200, !18, i64 204, !17, i64 208, !17, i64 209, !9, i64 212, !9, i64 216, !9, i64 220, !9, i64 224, !16, i64 232}
!7 = !{!"_ZTS10NeuronBase", !8, i64 0, !12, i64 16, !17, i64 40, !17, i64 41, !9, i64 44, !18, i64 48}
!8 = !{!"_ZTS4Base", !9, i64 8, !9, i64 12}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!16 = !{!"any pointer", !10, i64 0}
!17 = !{!"bool", !10, i64 0}
!18 = !{!"float", !10, i64 0}
!19 = !{!"_ZTSSt26linear_congruential_engineImLm16807ELm0ELm2147483647EE", !20, i64 0}
!20 = !{!"long", !10, i64 0}
!21 = !{!"_ZTSSt20poisson_distributionIiE", !22, i64 0, !24, i64 72}
!22 = !{!"_ZTSNSt20poisson_distributionIiE10param_typeE", !23, i64 0, !23, i64 8, !23, i64 16, !23, i64 24, !23, i64 32, !23, i64 40, !23, i64 48, !23, i64 56, !23, i64 64}
!23 = !{!"double", !10, i64 0}
!24 = !{!"_ZTSSt19normal_distributionIdE", !25, i64 0, !23, i64 16, !17, i64 24}
!25 = !{!"_ZTSNSt19normal_distributionIdE10param_typeE", !23, i64 0, !23, i64 8}
!26 = !{!27, !9, i64 0}
!27 = !{!"_ZTS7SimInfo", !9, i64 0, !18, i64 4, !28, i64 8, !32, i64 32}
!28 = !{!"_ZTSSt6vectorIiSaIiEE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!32 = !{!"_ZTSSt6vectorIfSaIfEE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!36 = !{!6, !9, i64 216}
!37 = !{!7, !9, i64 44}
!38 = !{i8 0, i8 2}
!39 = !{!9, !9, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass