; LLVM IR from CRAFT-THU/BSim :: src/neuron/tj/TJNeuron.ll (ZN8TJNeuron7monitorER7SimInfo)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.TJNeuron = type { %class.NeuronBase.base, float, float, float, float, float, float, float, float, float, float, i32, i32, ptr }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%struct.SimInfo = type { i32, float, %"class.std::vector.0", %"class.std::vector.5" }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str = external hidden unnamed_addr constant [14 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [3 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [22 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [19 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN8TJNeuron7monitorER7SimInfo(ptr noundef nonnull align 8 dereferenceable(112) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) unnamed_addr #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca [128 x i8], align 16
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8
  %8 = getelementptr inbounds %class.NeuronBase, ptr %7, i32 0, i32 3
  %9 = load i8, ptr %8, align 1, !tbaa !9, !range !19, !noundef !20
  %10 = trunc i8 %9 to i1
  br i1 %10, label %11, label %42

11:                                               ; preds = %2
  %12 = getelementptr inbounds %class.TJNeuron, ptr %7, i32 0, i32 13
  %13 = load ptr, ptr %12, align 8, !tbaa !21
  %14 = icmp eq ptr %13, null
  br i1 %14, label %15, label %32

15:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 128, ptr %5) #5
  %16 = getelementptr inbounds [128 x i8], ptr %5, i64 0, i64 0
  %17 = call noundef i32 @_ZN4Base5getIDEv(ptr noundef nonnull align 8 dereferenceable(16) %7)
  %18 = call i32 (ptr, ptr, ...) @sprintf(ptr noundef %16, ptr noundef @.str, i32 noundef %17) #5
  %19 = getelementptr inbounds [128 x i8], ptr %5, i64 0, i64 0
  %20 = call noalias ptr @fopen(ptr noundef %19, ptr noundef @.str.1)
  %21 = getelementptr inbounds %class.TJNeuron, ptr %7, i32 0, i32 13
  store ptr %20, ptr %21, align 8, !tbaa !21
  %22 = getelementptr inbounds %class.TJNeuron, ptr %7, i32 0, i32 13
  %23 = load ptr, ptr %22, align 8, !tbaa !21
  %24 = icmp eq ptr %23, null
  br i1 %24, label %25, label %28

25:                                               ; preds = %15
  %26 = getelementptr inbounds [128 x i8], ptr %5, i64 0, i64 0
  %27 = call i32 (ptr, ...) @printf(ptr noundef @.str.2, ptr noundef %26)
  store i32 1, ptr %6, align 4
  br label %29

28:                                               ; preds = %15
  store i32 0, ptr %6, align 4
  br label %29

29:                                               ; preds = %28, %25
  call void @llvm.lifetime.end.p0(i64 128, ptr %5) #5
  %30 = load i32, ptr %6, align 4
  switch i32 %30, label %43 [
    i32 0, label %31
    i32 1, label %42
  ]

31:                                               ; preds = %29
  br label %32

32:                                               ; preds = %31, %11
  %33 = getelementptr inbounds %class.TJNeuron, ptr %7, i32 0, i32 13
  %34 = load ptr, ptr %33, align 8, !tbaa !21
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.SimInfo, ptr %35, i32 0, i32 0
  %37 = load i32, ptr %36, align 8, !tbaa !23
  %38 = getelementptr inbounds %class.TJNeuron, ptr %7, i32 0, i32 9
  %39 = load float, ptr %38, align 4, !tbaa !33
  %40 = fpext float %39 to double
  %41 = call i32 (ptr, ptr, ...) @fprintf(ptr noundef %34, ptr noundef @.str.3, i32 noundef %37, double noundef %40) #5
  br label %42

42:                                               ; preds = %32, %29, %2
  ret void

43:                                               ; preds = %29
  unreachable
}

; Function Attrs: nounwind
declare i32 @sprintf(ptr noundef, ptr noundef, ...) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4Base5getIDEv(ptr noundef nonnull align 8 dereferenceable(16)) #3 align 2

declare noalias ptr @fopen(ptr noundef, ptr noundef) #4

declare i32 @printf(ptr noundef, ...) #4

; Function Attrs: nounwind
declare i32 @fprintf(ptr noundef, ptr noundef, ...) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !17, i64 41}
!10 = !{!"_ZTS10NeuronBase", !11, i64 0, !13, i64 16, !17, i64 40, !17, i64 41, !12, i64 44, !18, i64 48}
!11 = !{!"_ZTS4Base", !12, i64 8, !12, i64 12}
!12 = !{!"int", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"bool", !7, i64 0}
!18 = !{!"float", !7, i64 0}
!19 = !{i8 0, i8 2}
!20 = !{}
!21 = !{!22, !6, i64 104}
!22 = !{!"_ZTS8TJNeuron", !10, i64 0, !18, i64 52, !18, i64 56, !18, i64 60, !18, i64 64, !18, i64 68, !18, i64 72, !18, i64 76, !18, i64 80, !18, i64 84, !18, i64 88, !12, i64 92, !12, i64 96, !6, i64 104}
!23 = !{!24, !12, i64 0}
!24 = !{!"_ZTS7SimInfo", !12, i64 0, !18, i64 4, !25, i64 8, !29, i64 32}
!25 = !{!"_ZTSSt6vectorIiSaIiEE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!"_ZTSSt6vectorIfSaIfEE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!22, !18, i64 84}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [14 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [3 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [22 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [19 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN8TJNeuron7monitorER7SimInfo(ptr noundef nonnull align 8 dereferenceable(112) %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(56) %1) unnamed_addr #1 align 2 {
  %3 = alloca [128 x i8], align 16
  %4 = getelementptr inbounds i8, ptr %0, i64 41
  %5 = load i8, ptr %4, align 1, !tbaa !5, !range !18, !noundef !19
  %6 = trunc nuw i8 %5 to i1
  br i1 %6, label %7, label %25

7:                                                ; preds = %2
  %8 = getelementptr inbounds i8, ptr %0, i64 104
  %9 = load ptr, ptr %8, align 8, !tbaa !20
  %10 = icmp eq ptr %9, null
  br i1 %10, label %11, label %18

11:                                               ; preds = %7
  call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %3) #4
  %12 = tail call noundef i32 @_ZN4Base5getIDEv(ptr noundef nonnull align 8 dereferenceable(16) %0)
  %13 = call i32 (ptr, ptr, ...) @sprintf(ptr noundef nonnull dereferenceable(1) %3, ptr noundef nonnull dereferenceable(1) @.str, i32 noundef %12) #4
  %14 = call noalias ptr @fopen(ptr noundef nonnull %3, ptr noundef nonnull @.str.1)
  store ptr %14, ptr %8, align 8, !tbaa !20
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %.thread

.thread:                                          ; preds = %11
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %3) #4
  br label %18

16:                                               ; preds = %11
  %17 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.2, ptr noundef nonnull %3)
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %3) #4
  br label %25

18:                                               ; preds = %.thread, %7
  %19 = phi ptr [ %14, %.thread ], [ %9, %7 ]
  %20 = load i32, ptr %1, align 8, !tbaa !22
  %21 = getelementptr inbounds i8, ptr %0, i64 84
  %22 = load float, ptr %21, align 4, !tbaa !32
  %23 = fpext float %22 to double
  %24 = tail call i32 (ptr, ptr, ...) @fprintf(ptr noundef nonnull %19, ptr noundef nonnull @.str.3, i32 noundef %20, double noundef %23) #4
  br label %25

25:                                               ; preds = %16, %18, %2
  ret void
}

; Function Attrs: nofree nounwind
declare noundef i32 @sprintf(ptr noalias nocapture noundef writeonly, ptr nocapture noundef readonly, ...) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4Base5getIDEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #3 align 2

; Function Attrs: nofree nounwind
declare noalias noundef ptr @fopen(ptr nocapture noundef readonly, ptr nocapture noundef readonly) local_unnamed_addr #2

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #2

; Function Attrs: nofree nounwind
declare noundef i32 @fprintf(ptr nocapture noundef, ptr nocapture noundef readonly, ...) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !16, i64 41}
!6 = !{!"_ZTS10NeuronBase", !7, i64 0, !11, i64 16, !16, i64 40, !16, i64 41, !8, i64 44, !17, i64 48}
!7 = !{!"_ZTS4Base", !8, i64 8, !8, i64 12}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!15 = !{!"any pointer", !9, i64 0}
!16 = !{!"bool", !9, i64 0}
!17 = !{!"float", !9, i64 0}
!18 = !{i8 0, i8 2}
!19 = !{}
!20 = !{!21, !15, i64 104}
!21 = !{!"_ZTS8TJNeuron", !6, i64 0, !17, i64 52, !17, i64 56, !17, i64 60, !17, i64 64, !17, i64 68, !17, i64 72, !17, i64 76, !17, i64 80, !17, i64 84, !17, i64 88, !8, i64 92, !8, i64 96, !15, i64 104}
!22 = !{!23, !8, i64 0}
!23 = !{!"_ZTS7SimInfo", !8, i64 0, !17, i64 4, !24, i64 8, !28, i64 32}
!24 = !{!"_ZTSSt6vectorIiSaIiEE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!28 = !{!"_ZTSSt6vectorIfSaIfEE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!32 = !{!21, !17, i64 84}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass