; LLVM IR from CRAFT-THU/BSim :: src/neuron/mem/MemNeuron.ll (ZN9MemNeuron8hardCopyEPvii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.MemNeuron = type { %class.NeuronBase.base, float, ptr }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.GMemNeurons = type { ptr, ptr }
%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN9MemNeuron8hardCopyEPvii(ptr noundef nonnull align 8 dereferenceable(64) %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) unnamed_addr #1 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !9
  %10 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  %11 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %11, ptr %9, align 8, !tbaa !5
  %12 = load i32, ptr %7, align 4, !tbaa !9
  %13 = load i32, ptr %8, align 4, !tbaa !9
  %14 = add nsw i32 %12, %13
  call void @_ZN4Base5setIDEi(ptr noundef nonnull align 8 dereferenceable(16) %10, i32 noundef %14)
  %15 = getelementptr inbounds %class.MemNeuron, ptr %10, i32 0, i32 1
  %16 = load float, ptr %15, align 4, !tbaa !11
  %17 = load ptr, ptr %9, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.GMemNeurons, ptr %17, i32 0, i32 0
  %19 = load ptr, ptr %18, align 8, !tbaa !21
  %20 = load i32, ptr %7, align 4, !tbaa !9
  %21 = sext i32 %20 to i64
  %22 = getelementptr inbounds float, ptr %19, i64 %21
  store float %16, ptr %22, align 4, !tbaa !23
  %23 = getelementptr inbounds %class.NeuronBase, ptr %10, i32 0, i32 5
  %24 = load i32, ptr %23, align 4, !tbaa !24
  %25 = load ptr, ptr %9, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.GMemNeurons, ptr %25, i32 0, i32 1
  %27 = load ptr, ptr %26, align 8, !tbaa !25
  %28 = load i32, ptr %7, align 4, !tbaa !9
  %29 = sext i32 %28 to i64
  %30 = getelementptr inbounds i32, ptr %27, i64 %29
  store i32 %24, ptr %30, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  ret i32 1
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Base5setIDEi(ptr noundef nonnull align 8 dereferenceable(16), i32 noundef) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !20, i64 52}
!12 = !{!"_ZTS9MemNeuron", !13, i64 0, !20, i64 52, !6, i64 56}
!13 = !{!"_ZTS10NeuronBase", !14, i64 0, !15, i64 16, !19, i64 40, !19, i64 41, !10, i64 44, !20, i64 48}
!14 = !{!"_ZTS4Base", !10, i64 8, !10, i64 12}
!15 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"bool", !7, i64 0}
!20 = !{!"float", !7, i64 0}
!21 = !{!22, !6, i64 0}
!22 = !{!"_ZTS11GMemNeurons", !6, i64 0, !6, i64 8}
!23 = !{!20, !20, i64 0}
!24 = !{!13, !10, i64 44}
!25 = !{!22, !6, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN9MemNeuron8hardCopyEPvii(ptr noundef nonnull align 8 dereferenceable(64) %0, ptr nocapture noundef readonly %1, i32 noundef %2, i32 noundef %3) unnamed_addr #0 align 2 {
  %5 = add nsw i32 %3, %2
  tail call void @_ZN4Base5setIDEi(ptr noundef nonnull align 8 dereferenceable(16) %0, i32 noundef %5)
  %6 = getelementptr inbounds i8, ptr %0, i64 52
  %7 = load float, ptr %6, align 4, !tbaa !5
  %8 = load ptr, ptr %1, align 8, !tbaa !19
  %9 = sext i32 %2 to i64
  %10 = getelementptr inbounds float, ptr %8, i64 %9
  store float %7, ptr %10, align 4, !tbaa !21
  %11 = getelementptr inbounds i8, ptr %0, i64 44
  %12 = load i32, ptr %11, align 4, !tbaa !22
  %13 = getelementptr inbounds i8, ptr %1, i64 8
  %14 = load ptr, ptr %13, align 8, !tbaa !23
  %15 = getelementptr inbounds i32, ptr %14, i64 %9
  store i32 %12, ptr %15, align 4, !tbaa !24
  ret i32 1
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Base5setIDEi(ptr noundef nonnull align 8 dereferenceable(16), i32 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !18, i64 52}
!6 = !{!"_ZTS9MemNeuron", !7, i64 0, !18, i64 52, !16, i64 56}
!7 = !{!"_ZTS10NeuronBase", !8, i64 0, !12, i64 16, !17, i64 40, !17, i64 41, !9, i64 44, !18, i64 48}
!8 = !{!"_ZTS4Base", !9, i64 8, !9, i64 12}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!16 = !{!"any pointer", !10, i64 0}
!17 = !{!"bool", !10, i64 0}
!18 = !{!"float", !10, i64 0}
!19 = !{!20, !16, i64 0}
!20 = !{!"_ZTS11GMemNeurons", !16, i64 0, !16, i64 8}
!21 = !{!18, !18, i64 0}
!22 = !{!7, !9, i64 44}
!23 = !{!20, !16, i64 8}
!24 = !{!9, !9, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,TailCallElimPass