; LLVM IR from tangjz/acm-icpc :: leetcode/extra/LCP 81-与非的谜题.ll (Z6segUpdiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Node = type { [2 x i32] }

@seg = external dso_local global [20003 x %struct.Node], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z6segIdxii(i32 noundef, i32 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6segUpdiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = load i32, ptr %6, align 4, !tbaa !5
  %16 = call noundef i32 @_Z6segIdxii(i32 noundef %14, i32 noundef %15)
  store i32 %16, ptr %9, align 4, !tbaa !5
  %17 = load i32, ptr %5, align 4, !tbaa !5
  %18 = load i32, ptr %6, align 4, !tbaa !5
  %19 = icmp eq i32 %17, %18
  br i1 %19, label %20, label %25

20:                                               ; preds = %4
  %21 = load i32, ptr %9, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %22
  %24 = load i32, ptr %8, align 4, !tbaa !5
  call void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8) %23, i32 noundef %24)
  store i32 1, ptr %10, align 4
  br label %61

25:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %26 = load i32, ptr %5, align 4, !tbaa !5
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = add nsw i32 %26, %27
  %29 = ashr i32 %28, 1
  store i32 %29, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %30 = load i32, ptr %5, align 4, !tbaa !5
  %31 = load i32, ptr %11, align 4, !tbaa !5
  %32 = call noundef i32 @_Z6segIdxii(i32 noundef %30, i32 noundef %31)
  store i32 %32, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  %33 = load i32, ptr %11, align 4, !tbaa !5
  %34 = add nsw i32 %33, 1
  %35 = load i32, ptr %6, align 4, !tbaa !5
  %36 = call noundef i32 @_Z6segIdxii(i32 noundef %34, i32 noundef %35)
  store i32 %36, ptr %13, align 4, !tbaa !5
  %37 = load i32, ptr %7, align 4, !tbaa !5
  %38 = load i32, ptr %11, align 4, !tbaa !5
  %39 = icmp sle i32 %37, %38
  br i1 %39, label %40, label %45

40:                                               ; preds = %25
  %41 = load i32, ptr %5, align 4, !tbaa !5
  %42 = load i32, ptr %11, align 4, !tbaa !5
  %43 = load i32, ptr %7, align 4, !tbaa !5
  %44 = load i32, ptr %8, align 4, !tbaa !5
  call void @_Z6segUpdiiii(i32 noundef %41, i32 noundef %42, i32 noundef %43, i32 noundef %44)
  br label %51

45:                                               ; preds = %25
  %46 = load i32, ptr %11, align 4, !tbaa !5
  %47 = add nsw i32 %46, 1
  %48 = load i32, ptr %6, align 4, !tbaa !5
  %49 = load i32, ptr %7, align 4, !tbaa !5
  %50 = load i32, ptr %8, align 4, !tbaa !5
  call void @_Z6segUpdiiii(i32 noundef %47, i32 noundef %48, i32 noundef %49, i32 noundef %50)
  br label %51

51:                                               ; preds = %45, %40
  %52 = load i32, ptr %9, align 4, !tbaa !5
  %53 = sext i32 %52 to i64
  %54 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %53
  %55 = load i32, ptr %12, align 4, !tbaa !5
  %56 = sext i32 %55 to i64
  %57 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %56
  %58 = load i32, ptr %13, align 4, !tbaa !5
  %59 = sext i32 %58 to i64
  %60 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %59
  call void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8) %54, ptr noundef nonnull align 4 dereferenceable(8) %57, ptr noundef nonnull align 4 dereferenceable(8) %60)
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  store i32 0, ptr %10, align 4
  br label %61

61:                                               ; preds = %51, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  %62 = load i32, ptr %10, align 4
  switch i32 %62, label %64 [
    i32 0, label %63
    i32 1, label %63
  ]

63:                                               ; preds = %61, %61
  ret void

64:                                               ; preds = %61
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Node = type { [2 x i32] }

@seg = external dso_local global [20003 x %struct.Node], align 16

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z6segIdxii(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6segUpdiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = tail call noundef i32 @_Z6segIdxii(i32 noundef %0, i32 noundef %1)
  %6 = icmp eq i32 %0, %1
  br i1 %6, label %7, label %10

7:                                                ; preds = %4
  %8 = sext i32 %5 to i64
  %9 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %8
  tail call void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8) %9, i32 noundef %3)
  br label %25

10:                                               ; preds = %4
  %11 = add nsw i32 %1, %0
  %12 = ashr i32 %11, 1
  %13 = tail call noundef i32 @_Z6segIdxii(i32 noundef %0, i32 noundef %12)
  %14 = add nsw i32 %12, 1
  %15 = tail call noundef i32 @_Z6segIdxii(i32 noundef %14, i32 noundef %1)
  %.not = icmp slt i32 %12, %2
  br i1 %.not, label %17, label %16

16:                                               ; preds = %10
  tail call void @_Z6segUpdiiii(i32 noundef %0, i32 noundef %12, i32 noundef %2, i32 noundef %3)
  br label %18

17:                                               ; preds = %10
  tail call void @_Z6segUpdiiii(i32 noundef %14, i32 noundef %1, i32 noundef %2, i32 noundef %3)
  br label %18

18:                                               ; preds = %17, %16
  %19 = sext i32 %5 to i64
  %20 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %19
  %21 = sext i32 %13 to i64
  %22 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %21
  %23 = sext i32 %15 to i64
  %24 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %23
  tail call void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8) %20, ptr noundef nonnull align 4 dereferenceable(8) %22, ptr noundef nonnull align 4 dereferenceable(8) %24)
  br label %25

25:                                               ; preds = %18, %7
  ret void
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass