; LLVM IR from CRAFT-THU/BSim :: src/neuron/constant/ConstantNeuron.ll (ZN14ConstantNeuron5resetER7SimInfo)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.ConstantNeuron = type { %class.NeuronBase.base, float, i32, i32, float, float, ptr }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%struct.SimInfo = type { i32, float, %"class.std::vector.0", %"class.std::vector.5" }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN14ConstantNeuron5resetER7SimInfo(ptr noundef nonnull align 8 dereferenceable(80) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  %6 = getelementptr inbounds %class.NeuronBase, ptr %5, i32 0, i32 2
  store i8 0, ptr %6, align 8, !tbaa !9
  %7 = getelementptr inbounds %class.NeuronBase, ptr %5, i32 0, i32 5
  store i32 0, ptr %7, align 4, !tbaa !19
  %8 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 4
  %9 = load float, ptr %8, align 8, !tbaa !20
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.SimInfo, ptr %10, i32 0, i32 1
  %12 = load float, ptr %11, align 4, !tbaa !22
  %13 = fdiv float %9, %12
  %14 = fptosi float %13 to i32
  %15 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 2
  store i32 %14, ptr %15, align 8, !tbaa !32
  %16 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 5
  %17 = load float, ptr %16, align 4, !tbaa !33
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.SimInfo, ptr %18, i32 0, i32 1
  %20 = load float, ptr %19, align 4, !tbaa !22
  %21 = fdiv float %17, %20
  %22 = fptosi float %21 to i32
  %23 = getelementptr inbounds %class.ConstantNeuron, ptr %5, i32 0, i32 3
  store i32 %22, ptr %23, align 4, !tbaa !34
  ret i32 0
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !17, i64 40}
!10 = !{!"_ZTS10NeuronBase", !11, i64 0, !13, i64 16, !17, i64 40, !17, i64 41, !12, i64 44, !18, i64 48}
!11 = !{!"_ZTS4Base", !12, i64 8, !12, i64 12}
!12 = !{!"int", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"bool", !7, i64 0}
!18 = !{!"float", !7, i64 0}
!19 = !{!10, !12, i64 44}
!20 = !{!21, !18, i64 64}
!21 = !{!"_ZTS14ConstantNeuron", !10, i64 0, !18, i64 52, !12, i64 56, !12, i64 60, !18, i64 64, !18, i64 68, !6, i64 72}
!22 = !{!23, !18, i64 4}
!23 = !{!"_ZTS7SimInfo", !12, i64 0, !18, i64 4, !24, i64 8, !28, i64 32}
!24 = !{!"_ZTSSt6vectorIiSaIiEE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!28 = !{!"_ZTSSt6vectorIfSaIfEE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!21, !12, i64 56}
!33 = !{!21, !18, i64 68}
!34 = !{!21, !12, i64 60}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
define dso_local noundef i32 @_ZN14ConstantNeuron5resetER7SimInfo(ptr nocapture noundef nonnull align 8 dereferenceable(80) %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(56) %1) unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 40
  store i8 0, ptr %3, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 44
  store i32 0, ptr %4, align 4, !tbaa !18
  %5 = getelementptr inbounds i8, ptr %0, i64 64
  %6 = getelementptr inbounds i8, ptr %1, i64 4
  %7 = load <4 x float>, ptr %6, align 4
  %8 = getelementptr inbounds i8, ptr %0, i64 56
  %9 = load <2 x float>, ptr %5, align 8, !tbaa !19
  %10 = shufflevector <4 x float> %7, <4 x float> poison, <2 x i32> zeroinitializer
  %11 = fdiv <2 x float> %9, %10
  %12 = fptosi <2 x float> %11 to <2 x i32>
  store <2 x i32> %12, ptr %8, align 8, !tbaa !20
  ret i32 0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !16, i64 40}
!6 = !{!"_ZTS10NeuronBase", !7, i64 0, !11, i64 16, !16, i64 40, !16, i64 41, !8, i64 44, !17, i64 48}
!7 = !{!"_ZTS4Base", !8, i64 8, !8, i64 12}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!15 = !{!"any pointer", !9, i64 0}
!16 = !{!"bool", !9, i64 0}
!17 = !{!"float", !9, i64 0}
!18 = !{!6, !8, i64 44}
!19 = !{!17, !17, i64 0}
!20 = !{!8, !8, i64 0}


; Effective O3 passes: EarlyCSEPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,VectorCombinePass