; LLVM IR from ubaldot/defrecs :: stm32f4x/ADC_Readings/Drivers/CMSIS/DSP/Source/FastMathFunctions (q31)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_divide_q31(i32 noundef %0, i32 noundef %1, ptr noundef %2, ptr noundef %3) #2 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i16, align 2
  %11 = alloca i64, align 8
  %12 = alloca i16, align 2
  %13 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #4
  store i16 0, ptr %10, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %12) #4
  %14 = load ptr, ptr %9, align 8, !tbaa !9
  store i16 0, ptr %14, align 2, !tbaa !11
  %15 = load i32, ptr %6, align 4, !tbaa !5
  %16 = ashr i32 %15, 31
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = ashr i32 %17, 31
  %19 = xor i32 %16, %18
  %20 = trunc i32 %19 to i16
  store i16 %20, ptr %10, align 2, !tbaa !11
  %21 = load i32, ptr %7, align 4, !tbaa !5
  %22 = icmp eq i32 %21, 0
  br i1 %22, label %23, label %31

23:                                               ; preds = %4
  %24 = load i16, ptr %10, align 2, !tbaa !11
  %25 = icmp ne i16 %24, 0
  br i1 %25, label %26, label %28

26:                                               ; preds = %23
  %27 = load ptr, ptr %8, align 8, !tbaa !9
  store i32 -2147483648, ptr %27, align 4, !tbaa !5
  br label %30

28:                                               ; preds = %23
  %29 = load ptr, ptr %8, align 8, !tbaa !9
  store i32 2147483647, ptr %29, align 4, !tbaa !5
  br label %30

30:                                               ; preds = %28, %26
  store i32 -4, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %66

31:                                               ; preds = %4
  call void @arm_abs_q31(ptr noundef %6, ptr noundef %6, i32 noundef 1)
  call void @arm_abs_q31(ptr noundef %7, ptr noundef %7, i32 noundef 1)
  %32 = load i32, ptr %6, align 4, !tbaa !5
  %33 = sext i32 %32 to i64
  %34 = shl i64 %33, 31
  %35 = load i32, ptr %7, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = sdiv i64 %34, %36
  store i64 %37, ptr %11, align 8, !tbaa !13
  %38 = load i64, ptr %11, align 8, !tbaa !13
  %39 = ashr i64 %38, 31
  %40 = trunc i64 %39 to i32
  %41 = call zeroext i8 @__CLZ(i32 noundef %40)
  %42 = zext i8 %41 to i32
  %43 = sub nsw i32 32, %42
  %44 = trunc i32 %43 to i16
  store i16 %44, ptr %12, align 2, !tbaa !11
  %45 = load i16, ptr %12, align 2, !tbaa !11
  %46 = sext i16 %45 to i32
  %47 = icmp sgt i32 %46, 0
  br i1 %47, label %48, label %56

48:                                               ; preds = %31
  %49 = load i16, ptr %12, align 2, !tbaa !11
  %50 = load ptr, ptr %9, align 8, !tbaa !9
  store i16 %49, ptr %50, align 2, !tbaa !11
  %51 = load i64, ptr %11, align 8, !tbaa !13
  %52 = load i16, ptr %12, align 2, !tbaa !11
  %53 = sext i16 %52 to i32
  %54 = zext i32 %53 to i64
  %55 = ashr i64 %51, %54
  store i64 %55, ptr %11, align 8, !tbaa !13
  br label %56

56:                                               ; preds = %48, %31
  %57 = load i16, ptr %10, align 2, !tbaa !11
  %58 = icmp ne i16 %57, 0
  br i1 %58, label %59, label %62

59:                                               ; preds = %56
  %60 = load i64, ptr %11, align 8, !tbaa !13
  %61 = sub nsw i64 0, %60
  store i64 %61, ptr %11, align 8, !tbaa !13
  br label %62

62:                                               ; preds = %59, %56
  %63 = load i64, ptr %11, align 8, !tbaa !13
  %64 = trunc i64 %63 to i32
  %65 = load ptr, ptr %8, align 8, !tbaa !9
  store i32 %64, ptr %65, align 4, !tbaa !5
  store i32 0, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %66

66:                                               ; preds = %62, %30
  call void @llvm.lifetime.end.p0(i64 2, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #4
  %67 = load i32, ptr %5, align 4
  ret i32 %67
}

declare void @arm_abs_q31(ptr noundef, ptr noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 -4, 1) i32 @arm_divide_q31(i32 noundef %0, i32 noundef %1, ptr nocapture noundef writeonly %2, ptr nocapture noundef writeonly %3) local_unnamed_addr #1 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i16 0, ptr %3, align 2, !tbaa !9
  %7 = xor i32 %1, %0
  %8 = icmp eq i32 %1, 0
  br i1 %8, label %9, label %10

9:                                                ; preds = %4
  %.not16 = icmp sgt i32 %0, -1
  %. = select i1 %.not16, i32 2147483647, i32 -2147483648
  br label %28

10:                                               ; preds = %4
  call void @arm_abs_q31(ptr noundef nonnull %5, ptr noundef nonnull %5, i32 noundef 1) #3
  call void @arm_abs_q31(ptr noundef nonnull %6, ptr noundef nonnull %6, i32 noundef 1) #3
  %11 = load i32, ptr %5, align 4, !tbaa !5
  %12 = sext i32 %11 to i64
  %13 = shl nsw i64 %12, 31
  %14 = load i32, ptr %6, align 4, !tbaa !5
  %15 = sext i32 %14 to i64
  %16 = sdiv i64 %13, %15
  %17 = lshr i64 %16, 31
  %18 = trunc i64 %17 to i32
  %19 = call zeroext i8 @__CLZ(i32 noundef %18)
  %20 = icmp ult i8 %19, 32
  br i1 %20, label %21, label %25

21:                                               ; preds = %10
  %narrow = sub nuw nsw i8 32, %19
  %22 = zext nneg i8 %narrow to i16
  %23 = zext nneg i8 %narrow to i64
  store i16 %22, ptr %3, align 2, !tbaa !9
  %24 = ashr i64 %16, %23
  br label %25

25:                                               ; preds = %21, %10
  %.014 = phi i64 [ %24, %21 ], [ %16, %10 ]
  %26 = sub nsw i64 0, %.014
  %.not18 = icmp slt i32 %7, 0
  %spec.select = select i1 %.not18, i64 %26, i64 %.014
  %27 = trunc i64 %spec.select to i32
  br label %28

28:                                               ; preds = %25, %9
  %storemerge17 = phi i32 [ %., %9 ], [ %27, %25 ]
  %.0 = phi i32 [ -4, %9 ], [ 0, %25 ]
  store i32 %storemerge17, ptr %2, align 4, !tbaa !5
  ret i32 %.0
}

declare void @arm_abs_q31(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass