; LLVM IR from mitdbg/deneva :: concurrency_control/occ.ll (ZN5OptCC14central_finishE2RCP10TxnManager)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Stats = type { ptr, ptr, i64, i64, i64, i64 }
%class.set_ent = type { i64, ptr, i32, ptr, ptr }
%class.OptCC = type { i8, i64, ptr, ptr, i64, i64, i64, %union.pthread_mutex_t, %union.sem_t }
%union.pthread_mutex_t = type { %struct.__pthread_mutex_s }
%struct.__pthread_mutex_s = type { i32, i32, i32, i32, i32, i16, i16, %struct.__pthread_internal_list }
%struct.__pthread_internal_list = type { ptr, ptr }
%union.sem_t = type { i64, [24 x i8] }
%class.Stats_thd = type { [64 x i8], ptr, ptr, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, i64, double, i64, double, i64, i64, double, double, double, double, double, double, double, double, i64, double, double, double, double, double, double, double, double, i64, i64, double, i64, double, i64, double, double, double, i64, i64, i64, double, double, double, double, double, double, double, double, double, i64, ptr, ptr, double, i64, i64, double, double, double, i64, i64, i64, i64, i64, i64, i64, double, double, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, double, double, double, double, i64, i64, double, double, i64, i64, i64, double, double, i64, i64, double, double, double, double, i64, i64, double, double, double, i64, i64, double, double, double, double, double, i64, double, double, double, double, double, double, double, double, i64, i64, i64, double, i64, double, double, i64, i64, i64, i64, i64, double, i64, i64, double, i64, double, double, i64, i64, i64, i64, i64, double, double, double, %class.StatsArr, %class.StatsArr, %class.StatsArr, %class.StatsArr, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, ptr, [64 x i8] }
%class.StatsArr = type { ptr, i64, i64, i32, %union.pthread_mutex_t }

@simulation = external global ptr, align 8
@stats = external global %class.Stats, align 8
@.str.1 = external hidden unnamed_addr constant [75 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [12 x i8], align 1
@__PRETTY_FUNCTION__._ZN5OptCC14central_finishE2RCP10TxnManager = external hidden unnamed_addr constant [45 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [16 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare noundef i64 @_Z13get_sys_clockv() #1

declare noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96)) #1

declare noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544)) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5OptCC14central_finishE2RCP10TxnManager(ptr noundef nonnull align 8 dereferenceable(128) %0, i32 noundef %1, ptr noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i8, align 1
  %10 = alloca i64, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store ptr %2, ptr %6, align 8, !tbaa !5
  %14 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = call noundef i32 @_ZN5OptCC10get_rw_setEP10TxnManagerRP7set_entS4_(ptr noundef nonnull align 8 dereferenceable(128) %14, ptr noundef %15, ptr noundef nonnull align 8 dereferenceable(8) %8, ptr noundef nonnull align 8 dereferenceable(8) %7)
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #5
  %17 = load ptr, ptr %7, align 8, !tbaa !5
  %18 = getelementptr inbounds %class.set_ent, ptr %17, i32 0, i32 2
  %19 = load i32, ptr %18, align 8, !tbaa !11
  %20 = icmp eq i32 %19, 0
  %21 = zext i1 %20 to i8
  store i8 %21, ptr %9, align 1, !tbaa !15
  %22 = load i8, ptr %9, align 1, !tbaa !15, !range !17, !noundef !18
  %23 = trunc i8 %22 to i1
  br i1 %23, label %126, label %24

24:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #5
  %25 = call noundef i64 @_Z13get_sys_clockv()
  store i64 %25, ptr %10, align 8, !tbaa !19
  %26 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 8
  %27 = call i32 @sem_wait(ptr noundef %26)
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #5
  %28 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 3
  %29 = load ptr, ptr %28, align 8, !tbaa !20
  store ptr %29, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #5
  store ptr null, ptr %12, align 8, !tbaa !5
  br label %30

30:                                               ; preds = %41, %24
  %31 = load ptr, ptr %11, align 8, !tbaa !5
  %32 = icmp ne ptr %31, null
  br i1 %32, label %33, label %39

33:                                               ; preds = %30
  %34 = load ptr, ptr %11, align 8, !tbaa !5
  %35 = getelementptr inbounds %class.set_ent, ptr %34, i32 0, i32 1
  %36 = load ptr, ptr %35, align 8, !tbaa !22
  %37 = load ptr, ptr %6, align 8, !tbaa !5
  %38 = icmp ne ptr %36, %37
  br label %39

39:                                               ; preds = %33, %30
  %40 = phi i1 [ false, %30 ], [ %38, %33 ]
  br i1 %40, label %41, label %46

41:                                               ; preds = %39
  %42 = load ptr, ptr %11, align 8, !tbaa !5
  store ptr %42, ptr %12, align 8, !tbaa !5
  %43 = load ptr, ptr %11, align 8, !tbaa !5
  %44 = getelementptr inbounds %class.set_ent, ptr %43, i32 0, i32 4
  %45 = load ptr, ptr %44, align 8, !tbaa !23
  store ptr %45, ptr %11, align 8, !tbaa !5
  br label %30, !llvm.loop !24

46:                                               ; preds = %39
  %47 = load ptr, ptr %11, align 8, !tbaa !5
  %48 = icmp eq ptr %47, null
  br i1 %48, label %49, label %58

49:                                               ; preds = %46
  %50 = load i32, ptr %5, align 4, !tbaa !9
  %51 = icmp eq i32 %50, 2
  br i1 %51, label %52, label %53

52:                                               ; preds = %49
  br label %55

53:                                               ; preds = %49
  call void @__assert_fail(ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 266, ptr noundef @__PRETTY_FUNCTION__._ZN5OptCC14central_finishE2RCP10TxnManager) #6
  unreachable

54:                                               ; No predecessors!
  br label %55

55:                                               ; preds = %54, %52
  %56 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 8
  %57 = call i32 @sem_post(ptr noundef %56) #5
  store i32 1, ptr %13, align 4
  br label %123

58:                                               ; preds = %46
  %59 = load ptr, ptr %11, align 8, !tbaa !5
  %60 = getelementptr inbounds %class.set_ent, ptr %59, i32 0, i32 1
  %61 = load ptr, ptr %60, align 8, !tbaa !22
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = icmp eq ptr %61, %62
  br i1 %63, label %64, label %65

64:                                               ; preds = %58
  br label %67

65:                                               ; preds = %58
  call void @__assert_fail(ptr noundef @.str.3, ptr noundef @.str.1, i32 noundef 271, ptr noundef @__PRETTY_FUNCTION__._ZN5OptCC14central_finishE2RCP10TxnManager) #6
  unreachable

66:                                               ; No predecessors!
  br label %67

67:                                               ; preds = %66, %64
  %68 = load ptr, ptr %12, align 8, !tbaa !5
  %69 = icmp ne ptr %68, null
  br i1 %69, label %70, label %76

70:                                               ; preds = %67
  %71 = load ptr, ptr %11, align 8, !tbaa !5
  %72 = getelementptr inbounds %class.set_ent, ptr %71, i32 0, i32 4
  %73 = load ptr, ptr %72, align 8, !tbaa !23
  %74 = load ptr, ptr %12, align 8, !tbaa !5
  %75 = getelementptr inbounds %class.set_ent, ptr %74, i32 0, i32 4
  store ptr %73, ptr %75, align 8, !tbaa !23
  br label %81

76:                                               ; preds = %67
  %77 = load ptr, ptr %11, align 8, !tbaa !5
  %78 = getelementptr inbounds %class.set_ent, ptr %77, i32 0, i32 4
  %79 = load ptr, ptr %78, align 8, !tbaa !23
  %80 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 3
  store ptr %79, ptr %80, align 8, !tbaa !20
  br label %81

81:                                               ; preds = %76, %70
  %82 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 5
  %83 = load i64, ptr %82, align 8, !tbaa !26
  %84 = add i64 %83, -1
  store i64 %84, ptr %82, align 8, !tbaa !26
  %85 = load i32, ptr %5, align 4, !tbaa !9
  %86 = icmp eq i32 %85, 0
  br i1 %86, label %87, label %104

87:                                               ; preds = %81
  %88 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 6
  %89 = load volatile i64, ptr %88, align 8, !tbaa !27
  %90 = add i64 %89, 1
  store volatile i64 %90, ptr %88, align 8, !tbaa !27
  %91 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 6
  %92 = load volatile i64, ptr %91, align 8, !tbaa !27
  %93 = load ptr, ptr %7, align 8, !tbaa !5
  %94 = getelementptr inbounds %class.set_ent, ptr %93, i32 0, i32 0
  store i64 %92, ptr %94, align 8, !tbaa !28
  %95 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 2
  %96 = load ptr, ptr %95, align 8, !tbaa !29
  %97 = load ptr, ptr %7, align 8, !tbaa !5
  %98 = getelementptr inbounds %class.set_ent, ptr %97, i32 0, i32 4
  store ptr %96, ptr %98, align 8, !tbaa !23
  %99 = load ptr, ptr %7, align 8, !tbaa !5
  %100 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 2
  store ptr %99, ptr %100, align 8, !tbaa !29
  %101 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 4
  %102 = load i64, ptr %101, align 8, !tbaa !30
  %103 = add i64 %102, 1
  store i64 %103, ptr %101, align 8, !tbaa !30
  br label %104

104:                                              ; preds = %87, %81
  %105 = getelementptr inbounds %class.OptCC, ptr %14, i32 0, i32 8
  %106 = call i32 @sem_post(ptr noundef %105) #5
  %107 = load ptr, ptr @simulation, align 8, !tbaa !5
  %108 = call noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96) %107)
  br i1 %108, label %109, label %122

109:                                              ; preds = %104
  %110 = call noundef i64 @_Z13get_sys_clockv()
  %111 = load i64, ptr %10, align 8, !tbaa !19
  %112 = sub i64 %110, %111
  %113 = uitofp i64 %112 to double
  %114 = load ptr, ptr @stats, align 8, !tbaa !31
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = call noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544) %115)
  %117 = getelementptr inbounds ptr, ptr %114, i64 %116
  %118 = load ptr, ptr %117, align 8, !tbaa !5
  %119 = getelementptr inbounds %class.Stats_thd, ptr %118, i32 0, i32 133
  %120 = load double, ptr %119, align 8, !tbaa !33
  %121 = fadd double %120, %113
  store double %121, ptr %119, align 8, !tbaa !33
  br label %122

122:                                              ; preds = %109, %104
  store i32 0, ptr %13, align 4
  br label %123

123:                                              ; preds = %122, %55
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #5
  %124 = load i32, ptr %13, align 4
  switch i32 %124, label %127 [
    i32 0, label %125
  ]

125:                                              ; preds = %123
  br label %126

126:                                              ; preds = %125, %3
  store i32 0, ptr %13, align 4
  br label %127

127:                                              ; preds = %126, %123
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  %128 = load i32, ptr %13, align 4
  switch i32 %128, label %130 [
    i32 0, label %129
    i32 1, label %129
  ]

129:                                              ; preds = %127, %127
  ret void

130:                                              ; preds = %127
  unreachable
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN5OptCC10get_rw_setEP10TxnManagerRP7set_entS4_(ptr noundef nonnull align 8 dereferenceable(128), ptr noundef, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2 align 2

declare i32 @sem_wait(ptr noundef) #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #3

; Function Attrs: nounwind
declare i32 @sem_post(ptr noundef) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS2RC", !7, i64 0}
!11 = !{!12, !14, i64 16}
!12 = !{!"_ZTS7set_ent", !13, i64 0, !6, i64 8, !14, i64 16, !6, i64 24, !6, i64 32}
!13 = !{!"long", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"bool", !7, i64 0}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = !{!13, !13, i64 0}
!20 = !{!21, !6, i64 24}
!21 = !{!"_ZTS5OptCC", !16, i64 0, !13, i64 8, !6, i64 16, !6, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !7, i64 56, !7, i64 96}
!22 = !{!12, !6, i64 8}
!23 = !{!12, !6, i64 32}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!21, !13, i64 40}
!27 = !{!21, !13, i64 48}
!28 = !{!12, !13, i64 0}
!29 = !{!21, !6, i64 16}
!30 = !{!21, !13, i64 32}
!31 = !{!32, !6, i64 0}
!32 = !{!"_ZTS5Stats", !6, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40}
!33 = !{!34, !35, i64 1120}
!34 = !{!"_ZTS9Stats_thd", !7, i64 0, !6, i64 64, !6, i64 72, !35, i64 80, !13, i64 88, !13, i64 96, !13, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !13, i64 136, !13, i64 144, !13, i64 152, !13, i64 160, !13, i64 168, !13, i64 176, !35, i64 184, !13, i64 192, !35, i64 200, !13, i64 208, !35, i64 216, !13, i64 224, !13, i64 232, !35, i64 240, !35, i64 248, !35, i64 256, !35, i64 264, !35, i64 272, !35, i64 280, !35, i64 288, !35, i64 296, !13, i64 304, !35, i64 312, !35, i64 320, !35, i64 328, !35, i64 336, !35, i64 344, !35, i64 352, !35, i64 360, !35, i64 368, !13, i64 376, !13, i64 384, !35, i64 392, !13, i64 400, !35, i64 408, !13, i64 416, !35, i64 424, !35, i64 432, !35, i64 440, !13, i64 448, !13, i64 456, !13, i64 464, !35, i64 472, !35, i64 480, !35, i64 488, !35, i64 496, !35, i64 504, !35, i64 512, !35, i64 520, !35, i64 528, !35, i64 536, !13, i64 544, !6, i64 552, !6, i64 560, !35, i64 568, !13, i64 576, !13, i64 584, !35, i64 592, !35, i64 600, !35, i64 608, !13, i64 616, !13, i64 624, !13, i64 632, !13, i64 640, !13, i64 648, !13, i64 656, !13, i64 664, !35, i64 672, !35, i64 680, !35, i64 688, !13, i64 696, !13, i64 704, !13, i64 712, !13, i64 720, !13, i64 728, !13, i64 736, !13, i64 744, !13, i64 752, !13, i64 760, !35, i64 768, !35, i64 776, !35, i64 784, !35, i64 792, !35, i64 800, !13, i64 808, !13, i64 816, !35, i64 824, !35, i64 832, !13, i64 840, !13, i64 848, !13, i64 856, !35, i64 864, !35, i64 872, !13, i64 880, !13, i64 888, !35, i64 896, !35, i64 904, !35, i64 912, !35, i64 920, !13, i64 928, !13, i64 936, !35, i64 944, !35, i64 952, !35, i64 960, !13, i64 968, !13, i64 976, !35, i64 984, !35, i64 992, !35, i64 1000, !35, i64 1008, !35, i64 1016, !13, i64 1024, !35, i64 1032, !35, i64 1040, !35, i64 1048, !35, i64 1056, !35, i64 1064, !35, i64 1072, !35, i64 1080, !35, i64 1088, !13, i64 1096, !13, i64 1104, !13, i64 1112, !35, i64 1120, !13, i64 1128, !35, i64 1136, !35, i64 1144, !13, i64 1152, !13, i64 1160, !13, i64 1168, !13, i64 1176, !13, i64 1184, !35, i64 1192, !13, i64 1200, !13, i64 1208, !35, i64 1216, !13, i64 1224, !35, i64 1232, !35, i64 1240, !13, i64 1248, !13, i64 1256, !13, i64 1264, !13, i64 1272, !13, i64 1280, !35, i64 1288, !35, i64 1296, !35, i64 1304, !36, i64 1312, !36, i64 1384, !36, i64 1456, !36, i64 1528, !35, i64 1600, !35, i64 1608, !35, i64 1616, !35, i64 1624, !35, i64 1632, !35, i64 1640, !35, i64 1648, !35, i64 1656, !35, i64 1664, !35, i64 1672, !35, i64 1680, !35, i64 1688, !35, i64 1696, !35, i64 1704, !35, i64 1712, !35, i64 1720, !35, i64 1728, !35, i64 1736, !35, i64 1744, !35, i64 1752, !35, i64 1760, !35, i64 1768, !35, i64 1776, !35, i64 1784, !35, i64 1792, !35, i64 1800, !35, i64 1808, !35, i64 1816, !35, i64 1824, !35, i64 1832, !35, i64 1840, !35, i64 1848, !35, i64 1856, !35, i64 1864, !35, i64 1872, !35, i64 1880, !6, i64 1888, !7, i64 1896}
!35 = !{!"double", !7, i64 0}
!36 = !{!"_ZTS8StatsArr", !6, i64 0, !13, i64 8, !13, i64 16, !37, i64 24, !7, i64 32}
!37 = !{!"_ZTS12StatsArrType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Stats = type { ptr, ptr, i64, i64, i64, i64 }

@simulation = external local_unnamed_addr global ptr, align 8
@stats = external local_unnamed_addr global %class.Stats, align 8
@.str.1 = external hidden unnamed_addr constant [75 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [12 x i8], align 1
@__PRETTY_FUNCTION__._ZN5OptCC14central_finishE2RCP10TxnManager = external hidden unnamed_addr constant [45 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare noundef i64 @_Z13get_sys_clockv() local_unnamed_addr #1

declare noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96)) local_unnamed_addr #1

declare noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544)) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5OptCC14central_finishE2RCP10TxnManager(ptr noundef nonnull align 8 dereferenceable(128) %0, i32 noundef %1, ptr noundef %2) local_unnamed_addr #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #5
  %6 = call noundef i32 @_ZN5OptCC10get_rw_setEP10TxnManagerRP7set_entS4_(ptr noundef nonnull align 8 dereferenceable(128) %0, ptr noundef %2, ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %7 = load ptr, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %7, i64 16
  %9 = load i32, ptr %8, align 8, !tbaa !9
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %59, label %11

11:                                               ; preds = %3
  %12 = call noundef i64 @_Z13get_sys_clockv()
  %13 = getelementptr inbounds i8, ptr %0, i64 96
  %14 = call i32 @sem_wait(ptr noundef nonnull %13)
  %15 = getelementptr inbounds i8, ptr %0, i64 24
  %.02027 = load ptr, ptr %15, align 8, !tbaa !5
  %cond28 = icmp eq ptr %.02027, null
  br i1 %cond28, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %11
  %16 = getelementptr inbounds i8, ptr %.02027, i64 8
  %17 = load ptr, ptr %16, align 8, !tbaa !13
  %.not2237 = icmp eq ptr %17, %2
  br i1 %.not2237, label %.critedge, label %.lr.ph39

.lr.ph:                                           ; preds = %.lr.ph39
  %18 = getelementptr inbounds i8, ptr %.020, i64 8
  %19 = load ptr, ptr %18, align 8, !tbaa !13
  %.not22 = icmp eq ptr %19, %2
  br i1 %.not22, label %.critedge, label %.lr.ph39, !llvm.loop !14

.lr.ph39:                                         ; preds = %.lr.ph.preheader, %.lr.ph
  %.0203038 = phi ptr [ %.020, %.lr.ph ], [ %.02027, %.lr.ph.preheader ]
  %20 = getelementptr inbounds i8, ptr %.0203038, i64 32
  %.020 = load ptr, ptr %20, align 8, !tbaa !5
  %cond = icmp eq ptr %.020, null
  br i1 %cond, label %._crit_edge, label %.lr.ph, !llvm.loop !14

._crit_edge:                                      ; preds = %.lr.ph39, %11
  %21 = icmp eq i32 %1, 2
  br i1 %21, label %23, label %22

22:                                               ; preds = %._crit_edge
  call void @__assert_fail(ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 266, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN5OptCC14central_finishE2RCP10TxnManager) #6
  unreachable

23:                                               ; preds = %._crit_edge
  %24 = call i32 @sem_post(ptr noundef nonnull %13) #5
  br label %59

.critedge:                                        ; preds = %.lr.ph, %.lr.ph.preheader
  %.02030.lcssa = phi ptr [ %.02027, %.lr.ph.preheader ], [ %.020, %.lr.ph ]
  %.01929.lcssa = phi ptr [ null, %.lr.ph.preheader ], [ %.0203038, %.lr.ph ]
  %.not23 = icmp eq ptr %.01929.lcssa, null
  %25 = getelementptr inbounds i8, ptr %.02030.lcssa, i64 32
  %26 = load ptr, ptr %25, align 8, !tbaa !16
  %27 = getelementptr inbounds i8, ptr %.01929.lcssa, i64 32
  %.sink = select i1 %.not23, ptr %15, ptr %27
  store ptr %26, ptr %.sink, align 8, !tbaa !5
  %28 = getelementptr inbounds i8, ptr %0, i64 40
  %29 = load i64, ptr %28, align 8, !tbaa !17
  %30 = add i64 %29, -1
  store i64 %30, ptr %28, align 8, !tbaa !17
  %31 = icmp eq i32 %1, 0
  br i1 %31, label %32, label %44

32:                                               ; preds = %.critedge
  %33 = getelementptr inbounds i8, ptr %0, i64 48
  %34 = load volatile i64, ptr %33, align 8, !tbaa !20
  %35 = add i64 %34, 1
  store volatile i64 %35, ptr %33, align 8, !tbaa !20
  %36 = load volatile i64, ptr %33, align 8, !tbaa !20
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  store i64 %36, ptr %37, align 8, !tbaa !21
  %38 = getelementptr inbounds i8, ptr %0, i64 16
  %39 = load ptr, ptr %38, align 8, !tbaa !22
  %40 = getelementptr inbounds i8, ptr %37, i64 32
  store ptr %39, ptr %40, align 8, !tbaa !16
  store ptr %37, ptr %38, align 8, !tbaa !22
  %41 = getelementptr inbounds i8, ptr %0, i64 32
  %42 = load i64, ptr %41, align 8, !tbaa !23
  %43 = add i64 %42, 1
  store i64 %43, ptr %41, align 8, !tbaa !23
  br label %44

44:                                               ; preds = %32, %.critedge
  %45 = call i32 @sem_post(ptr noundef nonnull %13) #5
  %46 = load ptr, ptr @simulation, align 8, !tbaa !5
  %47 = call noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96) %46)
  br i1 %47, label %48, label %59

48:                                               ; preds = %44
  %49 = call noundef i64 @_Z13get_sys_clockv()
  %50 = sub i64 %49, %12
  %51 = uitofp i64 %50 to double
  %52 = load ptr, ptr @stats, align 8, !tbaa !24
  %53 = call noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544) %2)
  %54 = getelementptr inbounds ptr, ptr %52, i64 %53
  %55 = load ptr, ptr %54, align 8, !tbaa !5
  %56 = getelementptr inbounds i8, ptr %55, i64 1120
  %57 = load double, ptr %56, align 8, !tbaa !26
  %58 = fadd double %57, %51
  store double %58, ptr %56, align 8, !tbaa !26
  br label %59

59:                                               ; preds = %23, %48, %44, %3
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #5
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN5OptCC10get_rw_setEP10TxnManagerRP7set_entS4_(ptr noundef nonnull align 8 dereferenceable(128), ptr noundef, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2 align 2

declare i32 @sem_wait(ptr noundef) local_unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind
declare i32 @sem_post(ptr noundef) local_unnamed_addr #4

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !12, i64 16}
!10 = !{!"_ZTS7set_ent", !11, i64 0, !6, i64 8, !12, i64 16, !6, i64 24, !6, i64 32}
!11 = !{!"long", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !6, i64 8}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = !{!10, !6, i64 32}
!17 = !{!18, !11, i64 40}
!18 = !{!"_ZTS5OptCC", !19, i64 0, !11, i64 8, !6, i64 16, !6, i64 24, !11, i64 32, !11, i64 40, !11, i64 48, !7, i64 56, !7, i64 96}
!19 = !{!"bool", !7, i64 0}
!20 = !{!18, !11, i64 48}
!21 = !{!10, !11, i64 0}
!22 = !{!18, !6, i64 16}
!23 = !{!18, !11, i64 32}
!24 = !{!25, !6, i64 0}
!25 = !{!"_ZTS5Stats", !6, i64 0, !6, i64 8, !11, i64 16, !11, i64 24, !11, i64 32, !11, i64 40}
!26 = !{!27, !28, i64 1120}
!27 = !{!"_ZTS9Stats_thd", !7, i64 0, !6, i64 64, !6, i64 72, !28, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !11, i64 144, !11, i64 152, !11, i64 160, !11, i64 168, !11, i64 176, !28, i64 184, !11, i64 192, !28, i64 200, !11, i64 208, !28, i64 216, !11, i64 224, !11, i64 232, !28, i64 240, !28, i64 248, !28, i64 256, !28, i64 264, !28, i64 272, !28, i64 280, !28, i64 288, !28, i64 296, !11, i64 304, !28, i64 312, !28, i64 320, !28, i64 328, !28, i64 336, !28, i64 344, !28, i64 352, !28, i64 360, !28, i64 368, !11, i64 376, !11, i64 384, !28, i64 392, !11, i64 400, !28, i64 408, !11, i64 416, !28, i64 424, !28, i64 432, !28, i64 440, !11, i64 448, !11, i64 456, !11, i64 464, !28, i64 472, !28, i64 480, !28, i64 488, !28, i64 496, !28, i64 504, !28, i64 512, !28, i64 520, !28, i64 528, !28, i64 536, !11, i64 544, !6, i64 552, !6, i64 560, !28, i64 568, !11, i64 576, !11, i64 584, !28, i64 592, !28, i64 600, !28, i64 608, !11, i64 616, !11, i64 624, !11, i64 632, !11, i64 640, !11, i64 648, !11, i64 656, !11, i64 664, !28, i64 672, !28, i64 680, !28, i64 688, !11, i64 696, !11, i64 704, !11, i64 712, !11, i64 720, !11, i64 728, !11, i64 736, !11, i64 744, !11, i64 752, !11, i64 760, !28, i64 768, !28, i64 776, !28, i64 784, !28, i64 792, !28, i64 800, !11, i64 808, !11, i64 816, !28, i64 824, !28, i64 832, !11, i64 840, !11, i64 848, !11, i64 856, !28, i64 864, !28, i64 872, !11, i64 880, !11, i64 888, !28, i64 896, !28, i64 904, !28, i64 912, !28, i64 920, !11, i64 928, !11, i64 936, !28, i64 944, !28, i64 952, !28, i64 960, !11, i64 968, !11, i64 976, !28, i64 984, !28, i64 992, !28, i64 1000, !28, i64 1008, !28, i64 1016, !11, i64 1024, !28, i64 1032, !28, i64 1040, !28, i64 1048, !28, i64 1056, !28, i64 1064, !28, i64 1072, !28, i64 1080, !28, i64 1088, !11, i64 1096, !11, i64 1104, !11, i64 1112, !28, i64 1120, !11, i64 1128, !28, i64 1136, !28, i64 1144, !11, i64 1152, !11, i64 1160, !11, i64 1168, !11, i64 1176, !11, i64 1184, !28, i64 1192, !11, i64 1200, !11, i64 1208, !28, i64 1216, !11, i64 1224, !28, i64 1232, !28, i64 1240, !11, i64 1248, !11, i64 1256, !11, i64 1264, !11, i64 1272, !11, i64 1280, !28, i64 1288, !28, i64 1296, !28, i64 1304, !29, i64 1312, !29, i64 1384, !29, i64 1456, !29, i64 1528, !28, i64 1600, !28, i64 1608, !28, i64 1616, !28, i64 1624, !28, i64 1632, !28, i64 1640, !28, i64 1648, !28, i64 1656, !28, i64 1664, !28, i64 1672, !28, i64 1680, !28, i64 1688, !28, i64 1696, !28, i64 1704, !28, i64 1712, !28, i64 1720, !28, i64 1728, !28, i64 1736, !28, i64 1744, !28, i64 1752, !28, i64 1760, !28, i64 1768, !28, i64 1776, !28, i64 1784, !28, i64 1792, !28, i64 1800, !28, i64 1808, !28, i64 1816, !28, i64 1824, !28, i64 1832, !28, i64 1840, !28, i64 1848, !28, i64 1856, !28, i64 1864, !28, i64 1872, !28, i64 1880, !6, i64 1888, !7, i64 1896}
!28 = !{!"double", !7, i64 0}
!29 = !{!"_ZTS8StatsArr", !6, i64 0, !11, i64 8, !11, i64 16, !30, i64 24, !7, i64 32}
!30 = !{!"_ZTS12StatsArrType", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass