; LLVM IR from tangjz/acm-icpc :: codeforces/complete (819E)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@n = external dso_local global i32, align 4
@.str.3 = external hidden unnamed_addr constant [3 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiii(i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiiii(i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z8showEdgev() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #3 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  %7 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str.3, ptr noundef @n)
  %8 = load i32, ptr @n, align 4, !tbaa !5
  %9 = and i32 %8, 1
  %10 = icmp ne i32 %9, 0
  br i1 %10, label %11, label %50

11:                                               ; preds = %0
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
  store i32 3, ptr %2, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %46, %11
  %13 = load i32, ptr %2, align 4, !tbaa !5
  %14 = load i32, ptr @n, align 4, !tbaa !5
  %15 = icmp sle i32 %13, %14
  br i1 %15, label %17, label %16

16:                                               ; preds = %12
  store i32 2, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
  br label %49

17:                                               ; preds = %12
  %18 = load i32, ptr %2, align 4, !tbaa !5
  %19 = sub nsw i32 %18, 1
  %20 = load i32, ptr %2, align 4, !tbaa !5
  call void @_Z7addEdgeiii(i32 noundef 1, i32 noundef %19, i32 noundef %20)
  %21 = load i32, ptr %2, align 4, !tbaa !5
  %22 = sub nsw i32 %21, 1
  %23 = load i32, ptr %2, align 4, !tbaa !5
  call void @_Z7addEdgeiii(i32 noundef 1, i32 noundef %22, i32 noundef %23)
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  store i32 3, ptr %4, align 4, !tbaa !5
  br label %24

24:                                               ; preds = %42, %17
  %25 = load i32, ptr %4, align 4, !tbaa !5
  %26 = load i32, ptr %2, align 4, !tbaa !5
  %27 = icmp slt i32 %25, %26
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  store i32 5, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  br label %45

29:                                               ; preds = %24
  %30 = load i32, ptr %4, align 4, !tbaa !5
  %31 = sub nsw i32 %30, 1
  %32 = load i32, ptr %2, align 4, !tbaa !5
  %33 = load i32, ptr %4, align 4, !tbaa !5
  %34 = load i32, ptr %2, align 4, !tbaa !5
  %35 = sub nsw i32 %34, 1
  call void @_Z7addEdgeiiii(i32 noundef %31, i32 noundef %32, i32 noundef %33, i32 noundef %35)
  %36 = load i32, ptr %4, align 4, !tbaa !5
  %37 = sub nsw i32 %36, 1
  %38 = load i32, ptr %2, align 4, !tbaa !5
  %39 = load i32, ptr %4, align 4, !tbaa !5
  %40 = load i32, ptr %2, align 4, !tbaa !5
  %41 = sub nsw i32 %40, 1
  call void @_Z7addEdgeiiii(i32 noundef %37, i32 noundef %38, i32 noundef %39, i32 noundef %41)
  br label %42

42:                                               ; preds = %29
  %43 = load i32, ptr %4, align 4, !tbaa !5
  %44 = add nsw i32 %43, 2
  store i32 %44, ptr %4, align 4, !tbaa !5
  br label %24, !llvm.loop !9

45:                                               ; preds = %28
  br label %46

46:                                               ; preds = %45
  %47 = load i32, ptr %2, align 4, !tbaa !5
  %48 = add nsw i32 %47, 2
  store i32 %48, ptr %2, align 4, !tbaa !5
  br label %12, !llvm.loop !11

49:                                               ; preds = %16
  br label %92

50:                                               ; preds = %0
  call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4)
  call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef 2, i32 noundef 4, i32 noundef 3)
  call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef 3, i32 noundef 2, i32 noundef 4)
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  store i32 6, ptr %5, align 4, !tbaa !5
  br label %51

51:                                               ; preds = %88, %50
  %52 = load i32, ptr %5, align 4, !tbaa !5
  %53 = load i32, ptr @n, align 4, !tbaa !5
  %54 = icmp sle i32 %52, %53
  br i1 %54, label %56, label %55

55:                                               ; preds = %51
  store i32 8, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  br label %91

56:                                               ; preds = %51
  %57 = load i32, ptr %5, align 4, !tbaa !5
  %58 = sub nsw i32 %57, 1
  %59 = load i32, ptr %5, align 4, !tbaa !5
  call void @_Z7addEdgeiii(i32 noundef 1, i32 noundef %58, i32 noundef %59)
  %60 = load i32, ptr %5, align 4, !tbaa !5
  %61 = sub nsw i32 %60, 1
  %62 = load i32, ptr %5, align 4, !tbaa !5
  call void @_Z7addEdgeiii(i32 noundef 2, i32 noundef %61, i32 noundef %62)
  %63 = load i32, ptr %5, align 4, !tbaa !5
  %64 = load i32, ptr %5, align 4, !tbaa !5
  %65 = sub nsw i32 %64, 1
  call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef %63, i32 noundef 2, i32 noundef %65)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  store i32 4, ptr %6, align 4, !tbaa !5
  br label %66

66:                                               ; preds = %84, %56
  %67 = load i32, ptr %6, align 4, !tbaa !5
  %68 = load i32, ptr %5, align 4, !tbaa !5
  %69 = icmp slt i32 %67, %68
  br i1 %69, label %71, label %70

70:                                               ; preds = %66
  store i32 11, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  br label %87

71:                                               ; preds = %66
  %72 = load i32, ptr %6, align 4, !tbaa !5
  %73 = sub nsw i32 %72, 1
  %74 = load i32, ptr %5, align 4, !tbaa !5
  %75 = load i32, ptr %6, align 4, !tbaa !5
  %76 = load i32, ptr %5, align 4, !tbaa !5
  %77 = sub nsw i32 %76, 1
  call void @_Z7addEdgeiiii(i32 noundef %73, i32 noundef %74, i32 noundef %75, i32 noundef %77)
  %78 = load i32, ptr %6, align 4, !tbaa !5
  %79 = sub nsw i32 %78, 1
  %80 = load i32, ptr %5, align 4, !tbaa !5
  %81 = load i32, ptr %6, align 4, !tbaa !5
  %82 = load i32, ptr %5, align 4, !tbaa !5
  %83 = sub nsw i32 %82, 1
  call void @_Z7addEdgeiiii(i32 noundef %79, i32 noundef %80, i32 noundef %81, i32 noundef %83)
  br label %84

84:                                               ; preds = %71
  %85 = load i32, ptr %6, align 4, !tbaa !5
  %86 = add nsw i32 %85, 2
  store i32 %86, ptr %6, align 4, !tbaa !5
  br label %66, !llvm.loop !12

87:                                               ; preds = %70
  br label %88

88:                                               ; preds = %87
  %89 = load i32, ptr %5, align 4, !tbaa !5
  %90 = add nsw i32 %89, 2
  store i32 %90, ptr %5, align 4, !tbaa !5
  br label %51, !llvm.loop !13

91:                                               ; preds = %55
  br label %92

92:                                               ; preds = %91, %49
  call void @_Z8showEdgev()
  ret i32 0
}

declare i32 @__isoc99_scanf(ptr noundef, ...) #4

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@n = external dso_local global i32, align 4
@.str.3 = external hidden unnamed_addr constant [3 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiii(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiiii(i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z8showEdgev() local_unnamed_addr #1

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() local_unnamed_addr #2 {
  %1 = tail call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str.3, ptr noundef nonnull @n)
  %2 = load i32, ptr @n, align 4, !tbaa !5
  %3 = and i32 %2, 1
  %.not = icmp eq i32 %3, 0
  br i1 %.not, label %11, label %.preheader

.preheader:                                       ; preds = %0
  %.not4043 = icmp slt i32 %2, 3
  br i1 %.not4043, label %.loopexit, label %.lr.ph45

.lr.ph45:                                         ; preds = %.preheader, %._crit_edge
  %.03844 = phi i32 [ %6, %._crit_edge ], [ 3, %.preheader ]
  %4 = add nsw i32 %.03844, -1
  tail call void @_Z7addEdgeiii(i32 noundef 1, i32 noundef %4, i32 noundef %.03844)
  tail call void @_Z7addEdgeiii(i32 noundef 1, i32 noundef %4, i32 noundef %.03844)
  %5 = icmp ugt i32 %.03844, 3
  br i1 %5, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %.lr.ph45
  %6 = add nuw nsw i32 %.03844, 2
  %7 = load i32, ptr @n, align 4, !tbaa !5
  %.not40 = icmp sgt i32 %6, %7
  br i1 %.not40, label %.loopexit, label %.lr.ph45, !llvm.loop !9

.lr.ph:                                           ; preds = %.lr.ph45, %.lr.ph
  %.03742 = phi i32 [ %9, %.lr.ph ], [ 3, %.lr.ph45 ]
  %8 = add nsw i32 %.03742, -1
  tail call void @_Z7addEdgeiiii(i32 noundef %8, i32 noundef %.03844, i32 noundef %.03742, i32 noundef %4)
  tail call void @_Z7addEdgeiiii(i32 noundef %8, i32 noundef %.03844, i32 noundef %.03742, i32 noundef %4)
  %9 = add nuw nsw i32 %.03742, 2
  %10 = icmp ult i32 %9, %.03844
  br i1 %10, label %.lr.ph, label %._crit_edge, !llvm.loop !11

11:                                               ; preds = %0
  tail call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4)
  tail call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef 2, i32 noundef 4, i32 noundef 3)
  tail call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef 3, i32 noundef 2, i32 noundef 4)
  %12 = load i32, ptr @n, align 4, !tbaa !5
  %.not3950 = icmp slt i32 %12, 6
  br i1 %.not3950, label %.loopexit, label %.lr.ph48.preheader

.lr.ph48.preheader:                               ; preds = %11, %._crit_edge49
  %.03651 = phi i32 [ %14, %._crit_edge49 ], [ 6, %11 ]
  %13 = add nsw i32 %.03651, -1
  tail call void @_Z7addEdgeiii(i32 noundef 1, i32 noundef %13, i32 noundef %.03651)
  tail call void @_Z7addEdgeiii(i32 noundef 2, i32 noundef %13, i32 noundef %.03651)
  tail call void @_Z7addEdgeiiii(i32 noundef 1, i32 noundef %.03651, i32 noundef 2, i32 noundef %13)
  br label %.lr.ph48

._crit_edge49:                                    ; preds = %.lr.ph48
  %14 = add nuw nsw i32 %.03651, 2
  %15 = load i32, ptr @n, align 4, !tbaa !5
  %.not39 = icmp sgt i32 %14, %15
  br i1 %.not39, label %.loopexit, label %.lr.ph48.preheader, !llvm.loop !12

.lr.ph48:                                         ; preds = %.lr.ph48.preheader, %.lr.ph48
  %.046 = phi i32 [ %17, %.lr.ph48 ], [ 4, %.lr.ph48.preheader ]
  %16 = add nsw i32 %.046, -1
  tail call void @_Z7addEdgeiiii(i32 noundef %16, i32 noundef %.03651, i32 noundef %.046, i32 noundef %13)
  tail call void @_Z7addEdgeiiii(i32 noundef %16, i32 noundef %.03651, i32 noundef %.046, i32 noundef %13)
  %17 = add nuw nsw i32 %.046, 2
  %18 = icmp ult i32 %17, %.03651
  br i1 %18, label %.lr.ph48, label %._crit_edge49, !llvm.loop !13

.loopexit:                                        ; preds = %._crit_edge, %._crit_edge49, %.preheader, %11
  tail call void @_Z8showEdgev()
  ret i32 0
}

; Function Attrs: nofree nounwind
declare noundef i32 @__isoc99_scanf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass