; LLVM IR from Yinxiaoli/iros2015_folding :: src/folding_planner_cmake/project/2dregistration_v2/mesh2d.ll (Z9clearMeshP5SMesh)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SMesh = type <{ %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::map", i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl" }
%"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SVertex *, std::allocator<SVertex *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl" }
%"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SHalfEdge *, std::allocator<SHalfEdge *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl" }
%"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SFace *, std::allocator<SFace *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::map" = type { %"class.std::_Rb_tree" }
%"class.std::_Rb_tree" = type { %"struct.std::_Rb_tree<SVertexPair, std::pair<const SVertexPair, SHalfEdge *>, std::_Select1st<std::pair<const SVertexPair, SHalfEdge *>>, std::less<SVertexPair>>::_Rb_tree_impl" }
%"struct.std::_Rb_tree<SVertexPair, std::pair<const SVertexPair, SHalfEdge *>, std::_Select1st<std::pair<const SVertexPair, SHalfEdge *>>, std::less<SVertexPair>>::_Rb_tree_impl" = type { [8 x i8], %"struct.std::_Rb_tree_header" }
%"struct.std::_Rb_tree_header" = type { %"struct.std::_Rb_tree_node_base", i64 }
%"struct.std::_Rb_tree_node_base" = type { i32, ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z9clearMeshP5SMesh(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8, !tbaa !5
  %7 = getelementptr inbounds %struct.SMesh, ptr %6, i32 0, i32 3
  call void @_ZNSt3mapI11SVertexPairP9SHalfEdgeSt4lessIS0_ESaISt4pairIKS0_S2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48) %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %8

8:                                                ; preds = %26, %1
  %9 = load i32, ptr %3, align 4, !tbaa !9
  %10 = zext i32 %9 to i64
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.SMesh, ptr %11, i32 0, i32 0
  %13 = call noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  %14 = icmp ult i64 %10, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %8
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %29

16:                                               ; preds = %8
  %17 = load ptr, ptr %2, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.SMesh, ptr %17, i32 0, i32 0
  %19 = load i32, ptr %3, align 4, !tbaa !9
  %20 = zext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %20) #3
  %22 = load ptr, ptr %21, align 8, !tbaa !5
  %23 = icmp eq ptr %22, null
  br i1 %23, label %25, label %24

24:                                               ; preds = %16
  call void @_ZdlPvm(ptr noundef %22, i64 noundef 24) #4
  br label %25

25:                                               ; preds = %24, %16
  br label %26

26:                                               ; preds = %25
  %27 = load i32, ptr %3, align 4, !tbaa !9
  %28 = add i32 %27, 1
  store i32 %28, ptr %3, align 4, !tbaa !9
  br label %8, !llvm.loop !11

29:                                               ; preds = %15
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %30

30:                                               ; preds = %48, %29
  %31 = load i32, ptr %4, align 4, !tbaa !9
  %32 = zext i32 %31 to i64
  %33 = load ptr, ptr %2, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.SMesh, ptr %33, i32 0, i32 1
  %35 = call noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %34) #3
  %36 = icmp ult i64 %32, %35
  br i1 %36, label %38, label %37

37:                                               ; preds = %30
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  br label %51

38:                                               ; preds = %30
  %39 = load ptr, ptr %2, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.SMesh, ptr %39, i32 0, i32 1
  %41 = load i32, ptr %4, align 4, !tbaa !9
  %42 = zext i32 %41 to i64
  %43 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %40, i64 noundef %42) #3
  %44 = load ptr, ptr %43, align 8, !tbaa !5
  %45 = icmp eq ptr %44, null
  br i1 %45, label %47, label %46

46:                                               ; preds = %38
  call void @_ZdlPvm(ptr noundef %44, i64 noundef 56) #4
  br label %47

47:                                               ; preds = %46, %38
  br label %48

48:                                               ; preds = %47
  %49 = load i32, ptr %4, align 4, !tbaa !9
  %50 = add i32 %49, 1
  store i32 %50, ptr %4, align 4, !tbaa !9
  br label %30, !llvm.loop !13

51:                                               ; preds = %37
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %52

52:                                               ; preds = %70, %51
  %53 = load i32, ptr %5, align 4, !tbaa !9
  %54 = zext i32 %53 to i64
  %55 = load ptr, ptr %2, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.SMesh, ptr %55, i32 0, i32 2
  %57 = call noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %56) #3
  %58 = icmp ult i64 %54, %57
  br i1 %58, label %60, label %59

59:                                               ; preds = %52
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %73

60:                                               ; preds = %52
  %61 = load ptr, ptr %2, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.SMesh, ptr %61, i32 0, i32 2
  %63 = load i32, ptr %5, align 4, !tbaa !9
  %64 = zext i32 %63 to i64
  %65 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %62, i64 noundef %64) #3
  %66 = load ptr, ptr %65, align 8, !tbaa !5
  %67 = icmp eq ptr %66, null
  br i1 %67, label %69, label %68

68:                                               ; preds = %60
  call void @_ZdlPvm(ptr noundef %66, i64 noundef 16) #4
  br label %69

69:                                               ; preds = %68, %60
  br label %70

70:                                               ; preds = %69
  %71 = load i32, ptr %5, align 4, !tbaa !9
  %72 = add i32 %71, 1
  store i32 %72, ptr %5, align 4, !tbaa !9
  br label %52, !llvm.loop !14

73:                                               ; preds = %59
  %74 = load ptr, ptr %2, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.SMesh, ptr %74, i32 0, i32 0
  call void @_ZNSt6vectorIP7SVertexSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %75) #3
  %76 = load ptr, ptr %2, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.SMesh, ptr %76, i32 0, i32 1
  call void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %77) #3
  %78 = load ptr, ptr %2, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.SMesh, ptr %78, i32 0, i32 2
  call void @_ZNSt6vectorIP5SFaceSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %79) #3
  %80 = load ptr, ptr %2, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.SMesh, ptr %80, i32 0, i32 4
  store i32 0, ptr %81, align 8, !tbaa !15
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt3mapI11SVertexPairP9SHalfEdgeSt4lessIS0_ESaISt4pairIKS0_S2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP7SVertexSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP5SFaceSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = !{!16, !10, i64 120}
!16 = !{!"_ZTS5SMesh", !17, i64 0, !21, i64 24, !25, i64 48, !29, i64 72, !10, i64 120}
!17 = !{!"_ZTSSt6vectorIP7SVertexSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIP7SVertexSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP7SVertexSaIS1_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP7SVertexSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSSt6vectorIP9SHalfEdgeSaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIP9SHalfEdgeSaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIP9SHalfEdgeSaIS1_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIP9SHalfEdgeSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt6vectorIP5SFaceSaIS1_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIP5SFaceSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIP5SFaceSaIS1_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP5SFaceSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!"_ZTSSt3mapI11SVertexPairP9SHalfEdgeSt4lessIS0_ESaISt4pairIKS0_S2_EEE", !30, i64 0}
!30 = !{!"_ZTSSt8_Rb_treeI11SVertexPairSt4pairIKS0_P9SHalfEdgeESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE", !31, i64 0}
!31 = !{!"_ZTSNSt8_Rb_treeI11SVertexPairSt4pairIKS0_P9SHalfEdgeESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE13_Rb_tree_implIS9_Lb1EEE", !32, i64 0, !34, i64 8}
!32 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessI11SVertexPairEE", !33, i64 0}
!33 = !{!"_ZTSSt4lessI11SVertexPairE"}
!34 = !{!"_ZTSSt15_Rb_tree_header", !35, i64 0, !37, i64 32}
!35 = !{!"_ZTSSt18_Rb_tree_node_base", !36, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!36 = !{!"_ZTSSt14_Rb_tree_color", !7, i64 0}
!37 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z9clearMeshP5SMesh(ptr noundef %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 72
  tail call void @_ZNSt3mapI11SVertexPairP9SHalfEdgeSt4lessIS0_ESaISt4pairIKS0_S2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48) %2) #2
  %3 = tail call noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %.preheader27, label %.lr.ph

.preheader27:                                     ; preds = %11, %1
  %4 = getelementptr inbounds i8, ptr %0, i64 24
  %5 = tail call noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #2
  %.not35 = icmp eq i64 %5, 0
  br i1 %.not35, label %.preheader, label %.lr.ph31

.lr.ph:                                           ; preds = %1, %11
  %6 = phi i64 [ %13, %11 ], [ 0, %1 ]
  %.02029 = phi i32 [ %12, %11 ], [ 0, %1 ]
  %7 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %6) #2
  %8 = load ptr, ptr %7, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %11, label %10

10:                                               ; preds = %.lr.ph
  tail call void @_ZdlPvm(ptr noundef nonnull %8, i64 noundef 24) #3
  br label %11

11:                                               ; preds = %.lr.ph, %10
  %12 = add i32 %.02029, 1
  %13 = zext i32 %12 to i64
  %14 = tail call noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %15 = icmp ugt i64 %14, %13
  br i1 %15, label %.lr.ph, label %.preheader27, !llvm.loop !9

.preheader:                                       ; preds = %23, %.preheader27
  %16 = getelementptr inbounds i8, ptr %0, i64 48
  %17 = tail call noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %16) #2
  %.not36 = icmp eq i64 %17, 0
  br i1 %.not36, label %._crit_edge, label %.lr.ph33

.lr.ph31:                                         ; preds = %.preheader27, %23
  %18 = phi i64 [ %25, %23 ], [ 0, %.preheader27 ]
  %.01930 = phi i32 [ %24, %23 ], [ 0, %.preheader27 ]
  %19 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %18) #2
  %20 = load ptr, ptr %19, align 8, !tbaa !5
  %21 = icmp eq ptr %20, null
  br i1 %21, label %23, label %22

22:                                               ; preds = %.lr.ph31
  tail call void @_ZdlPvm(ptr noundef nonnull %20, i64 noundef 56) #3
  br label %23

23:                                               ; preds = %.lr.ph31, %22
  %24 = add i32 %.01930, 1
  %25 = zext i32 %24 to i64
  %26 = tail call noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #2
  %27 = icmp ugt i64 %26, %25
  br i1 %27, label %.lr.ph31, label %.preheader, !llvm.loop !11

._crit_edge:                                      ; preds = %34, %.preheader
  tail call void @_ZNSt6vectorIP7SVertexSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  tail call void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #2
  tail call void @_ZNSt6vectorIP5SFaceSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %16) #2
  %28 = getelementptr inbounds i8, ptr %0, i64 120
  store i32 0, ptr %28, align 8, !tbaa !12
  ret void

.lr.ph33:                                         ; preds = %.preheader, %34
  %29 = phi i64 [ %36, %34 ], [ 0, %.preheader ]
  %.032 = phi i32 [ %35, %34 ], [ 0, %.preheader ]
  %30 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %29) #2
  %31 = load ptr, ptr %30, align 8, !tbaa !5
  %32 = icmp eq ptr %31, null
  br i1 %32, label %34, label %33

33:                                               ; preds = %.lr.ph33
  tail call void @_ZdlPvm(ptr noundef nonnull %31, i64 noundef 16) #3
  br label %34

34:                                               ; preds = %.lr.ph33, %33
  %35 = add i32 %.032, 1
  %36 = zext i32 %35 to i64
  %37 = tail call noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %16) #2
  %38 = icmp ugt i64 %37, %36
  br i1 %38, label %.lr.ph33, label %._crit_edge, !llvm.loop !36
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt3mapI11SVertexPairP9SHalfEdgeSt4lessIS0_ESaISt4pairIKS0_S2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP7SVertexSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP7SVertexSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP9SHalfEdgeSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP9SHalfEdgeSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP5SFaceSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP5SFaceSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP7SVertexSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP9SHalfEdgeSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP5SFaceSaIS1_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }
attributes #3 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = !{!13, !35, i64 120}
!13 = !{!"_ZTS5SMesh", !14, i64 0, !18, i64 24, !22, i64 48, !26, i64 72, !35, i64 120}
!14 = !{!"_ZTSSt6vectorIP7SVertexSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIP7SVertexSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP7SVertexSaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP7SVertexSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIP9SHalfEdgeSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIP9SHalfEdgeSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP9SHalfEdgeSaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP9SHalfEdgeSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIP5SFaceSaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIP5SFaceSaIS1_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIP5SFaceSaIS1_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIP5SFaceSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt3mapI11SVertexPairP9SHalfEdgeSt4lessIS0_ESaISt4pairIKS0_S2_EEE", !27, i64 0}
!27 = !{!"_ZTSSt8_Rb_treeI11SVertexPairSt4pairIKS0_P9SHalfEdgeESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt8_Rb_treeI11SVertexPairSt4pairIKS0_P9SHalfEdgeESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE13_Rb_tree_implIS9_Lb1EEE", !29, i64 0, !31, i64 8}
!29 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessI11SVertexPairEE", !30, i64 0}
!30 = !{!"_ZTSSt4lessI11SVertexPairE"}
!31 = !{!"_ZTSSt15_Rb_tree_header", !32, i64 0, !34, i64 32}
!32 = !{!"_ZTSSt18_Rb_tree_node_base", !33, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!33 = !{!"_ZTSSt14_Rb_tree_color", !7, i64 0}
!34 = !{!"long", !7, i64 0}
!35 = !{!"int", !7, i64 0}
!36 = distinct !{!36, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass