; LLVM IR from jpvt/Computer_Graphics :: Assignment #3/third_party/glm/test/gtc/gtc_bitfield.ll (ZN19bitfieldInterleave54testEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.glm::vec.9" = type { %union.anon.10, %union.anon.11 }
%union.anon.10 = type { i8 }
%union.anon.11 = type { i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN19bitfieldInterleave54testEv() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i64, align 8
  %3 = alloca i32, align 4
  %4 = alloca i64, align 8
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  %7 = alloca %"struct.glm::vec.9", align 1
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #4
  store i32 0, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %2) #4
  store i64 0, ptr %2, align 8, !tbaa !9
  br label %16

16:                                               ; preds = %73, %0
  %17 = load i64, ptr %2, align 8, !tbaa !9
  %18 = icmp ult i64 %17, 256
  br i1 %18, label %20, label %19

19:                                               ; preds = %16
  store i32 2, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %2) #4
  br label %76

20:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #4
  store i64 0, ptr %4, align 8, !tbaa !9
  br label %21

21:                                               ; preds = %69, %20
  %22 = load i64, ptr %4, align 8, !tbaa !9
  %23 = icmp ult i64 %22, 256
  br i1 %23, label %25, label %24

24:                                               ; preds = %21
  store i32 5, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #4
  br label %72

25:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 2, ptr %5) #4
  %26 = load i64, ptr %4, align 8, !tbaa !9
  %27 = trunc i64 %26 to i8
  %28 = load i64, ptr %2, align 8, !tbaa !9
  %29 = trunc i64 %28 to i8
  %30 = call noundef zeroext i16 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec2Ehh(i8 noundef zeroext %27, i8 noundef zeroext %29)
  store i16 %30, ptr %5, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #4
  %31 = load i64, ptr %4, align 8, !tbaa !9
  %32 = trunc i64 %31 to i8
  %33 = load i64, ptr %2, align 8, !tbaa !9
  %34 = trunc i64 %33 to i8
  %35 = call noundef zeroext i16 @_ZN3glm18bitfieldInterleaveEhh(i8 noundef zeroext %32, i8 noundef zeroext %34)
  store i16 %35, ptr %6, align 2, !tbaa !11
  %36 = load i16, ptr %5, align 2, !tbaa !11
  %37 = zext i16 %36 to i32
  %38 = load i16, ptr %6, align 2, !tbaa !11
  %39 = zext i16 %38 to i32
  %40 = icmp eq i32 %37, %39
  %41 = zext i1 %40 to i64
  %42 = select i1 %40, i32 0, i32 1
  %43 = load i32, ptr %1, align 4, !tbaa !5
  %44 = add nsw i32 %43, %42
  store i32 %44, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #4
  %45 = load i16, ptr %5, align 2, !tbaa !11
  %46 = call i16 @_ZN19bitfieldInterleave527bitfieldDeinterleave_u8vec2Et(i16 noundef zeroext %45)
  store i16 %46, ptr %7, align 1
  %47 = getelementptr inbounds %"struct.glm::vec.9", ptr %7, i32 0, i32 0
  %48 = load i8, ptr %47, align 1, !tbaa !13
  %49 = zext i8 %48 to i32
  %50 = load i64, ptr %4, align 8, !tbaa !9
  %51 = trunc i64 %50 to i8
  %52 = zext i8 %51 to i32
  %53 = icmp eq i32 %49, %52
  %54 = zext i1 %53 to i64
  %55 = select i1 %53, i32 0, i32 1
  %56 = load i32, ptr %1, align 4, !tbaa !5
  %57 = add nsw i32 %56, %55
  store i32 %57, ptr %1, align 4, !tbaa !5
  %58 = getelementptr inbounds %"struct.glm::vec.9", ptr %7, i32 0, i32 1
  %59 = load i8, ptr %58, align 1, !tbaa !13
  %60 = zext i8 %59 to i32
  %61 = load i64, ptr %2, align 8, !tbaa !9
  %62 = trunc i64 %61 to i8
  %63 = zext i8 %62 to i32
  %64 = icmp eq i32 %60, %63
  %65 = zext i1 %64 to i64
  %66 = select i1 %64, i32 0, i32 1
  %67 = load i32, ptr %1, align 4, !tbaa !5
  %68 = add nsw i32 %67, %66
  store i32 %68, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %5) #4
  br label %69

69:                                               ; preds = %25
  %70 = load i64, ptr %4, align 8, !tbaa !9
  %71 = add i64 %70, 1
  store i64 %71, ptr %4, align 8, !tbaa !9
  br label %21, !llvm.loop !14

72:                                               ; preds = %24
  br label %73

73:                                               ; preds = %72
  %74 = load i64, ptr %2, align 8, !tbaa !9
  %75 = add i64 %74, 1
  store i64 %75, ptr %2, align 8, !tbaa !9
  br label %16, !llvm.loop !16

76:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  store i64 0, ptr %8, align 8, !tbaa !9
  br label %77

77:                                               ; preds = %116, %76
  %78 = load i64, ptr %8, align 8, !tbaa !9
  %79 = icmp ult i64 %78, 256
  br i1 %79, label %81, label %80

80:                                               ; preds = %77
  store i32 8, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  br label %119

81:                                               ; preds = %77
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  store i64 0, ptr %9, align 8, !tbaa !9
  br label %82

82:                                               ; preds = %112, %81
  %83 = load i64, ptr %9, align 8, !tbaa !9
  %84 = icmp ult i64 %83, 256
  br i1 %84, label %86, label %85

85:                                               ; preds = %82
  store i32 11, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  br label %115

86:                                               ; preds = %82
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  %87 = load i64, ptr %9, align 8, !tbaa !9
  %88 = trunc i64 %87 to i8
  %89 = load i64, ptr %8, align 8, !tbaa !9
  %90 = trunc i64 %89 to i8
  %91 = load i64, ptr %9, align 8, !tbaa !9
  %92 = trunc i64 %91 to i8
  %93 = load i64, ptr %8, align 8, !tbaa !9
  %94 = trunc i64 %93 to i8
  %95 = call noundef i32 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec4Ehhhh(i8 noundef zeroext %88, i8 noundef zeroext %90, i8 noundef zeroext %92, i8 noundef zeroext %94)
  store i32 %95, ptr %10, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %96 = load i64, ptr %9, align 8, !tbaa !9
  %97 = trunc i64 %96 to i8
  %98 = load i64, ptr %8, align 8, !tbaa !9
  %99 = trunc i64 %98 to i8
  %100 = load i64, ptr %9, align 8, !tbaa !9
  %101 = trunc i64 %100 to i8
  %102 = load i64, ptr %8, align 8, !tbaa !9
  %103 = trunc i64 %102 to i8
  %104 = call noundef i32 @_ZN3glm18bitfieldInterleaveEhhhh(i8 noundef zeroext %97, i8 noundef zeroext %99, i8 noundef zeroext %101, i8 noundef zeroext %103)
  store i32 %104, ptr %11, align 4, !tbaa !5
  %105 = load i32, ptr %10, align 4, !tbaa !5
  %106 = load i32, ptr %11, align 4, !tbaa !5
  %107 = icmp eq i32 %105, %106
  %108 = zext i1 %107 to i64
  %109 = select i1 %107, i32 0, i32 1
  %110 = load i32, ptr %1, align 4, !tbaa !5
  %111 = add nsw i32 %110, %109
  store i32 %111, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  br label %112

112:                                              ; preds = %86
  %113 = load i64, ptr %9, align 8, !tbaa !9
  %114 = add i64 %113, 1
  store i64 %114, ptr %9, align 8, !tbaa !9
  br label %82, !llvm.loop !17

115:                                              ; preds = %85
  br label %116

116:                                              ; preds = %115
  %117 = load i64, ptr %8, align 8, !tbaa !9
  %118 = add i64 %117, 1
  store i64 %118, ptr %8, align 8, !tbaa !9
  br label %77, !llvm.loop !18

119:                                              ; preds = %80
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  store i64 0, ptr %12, align 8, !tbaa !9
  br label %120

120:                                              ; preds = %151, %119
  %121 = load i64, ptr %12, align 8, !tbaa !9
  %122 = icmp ult i64 %121, 256
  br i1 %122, label %124, label %123

123:                                              ; preds = %120
  store i32 14, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  br label %154

124:                                              ; preds = %120
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i64 0, ptr %13, align 8, !tbaa !9
  br label %125

125:                                              ; preds = %147, %124
  %126 = load i64, ptr %13, align 8, !tbaa !9
  %127 = icmp ult i64 %126, 256
  br i1 %127, label %129, label %128

128:                                              ; preds = %125
  store i32 17, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %150

129:                                              ; preds = %125
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  %130 = load i64, ptr %13, align 8, !tbaa !9
  %131 = trunc i64 %130 to i16
  %132 = load i64, ptr %12, align 8, !tbaa !9
  %133 = trunc i64 %132 to i16
  %134 = call noundef i32 @_ZN19bitfieldInterleave526bitfieldInterleave_u16vec2Ett(i16 noundef zeroext %131, i16 noundef zeroext %133)
  store i32 %134, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  %135 = load i64, ptr %13, align 8, !tbaa !9
  %136 = trunc i64 %135 to i16
  %137 = load i64, ptr %12, align 8, !tbaa !9
  %138 = trunc i64 %137 to i16
  %139 = call noundef i32 @_ZN3glm18bitfieldInterleaveEtt(i16 noundef zeroext %136, i16 noundef zeroext %138)
  store i32 %139, ptr %15, align 4, !tbaa !5
  %140 = load i32, ptr %14, align 4, !tbaa !5
  %141 = load i32, ptr %15, align 4, !tbaa !5
  %142 = icmp eq i32 %140, %141
  %143 = zext i1 %142 to i64
  %144 = select i1 %142, i32 0, i32 1
  %145 = load i32, ptr %1, align 4, !tbaa !5
  %146 = add nsw i32 %145, %144
  store i32 %146, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  br label %147

147:                                              ; preds = %129
  %148 = load i64, ptr %13, align 8, !tbaa !9
  %149 = add i64 %148, 1
  store i64 %149, ptr %13, align 8, !tbaa !9
  br label %125, !llvm.loop !19

150:                                              ; preds = %128
  br label %151

151:                                              ; preds = %150
  %152 = load i64, ptr %12, align 8, !tbaa !9
  %153 = add i64 %152, 1
  store i64 %153, ptr %12, align 8, !tbaa !9
  br label %120, !llvm.loop !20

154:                                              ; preds = %123
  %155 = load i32, ptr %1, align 4, !tbaa !5
  store i32 1, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #4
  ret i32 %155
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec2Ehh(i8 noundef zeroext, i8 noundef zeroext) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN3glm18bitfieldInterleaveEhh(i8 noundef zeroext, i8 noundef zeroext) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local i16 @_ZN19bitfieldInterleave527bitfieldDeinterleave_u8vec2Et(i16 noundef zeroext) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec4Ehhhh(i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveEhhhh(i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN19bitfieldInterleave526bitfieldInterleave_u16vec2Ett(i16 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveEtt(i16 noundef zeroext, i16 noundef zeroext) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}
!19 = distinct !{!19, !15}
!20 = distinct !{!20, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN19bitfieldInterleave54testEv() local_unnamed_addr #0 {
  br label %.preheader52

.preheader52:                                     ; preds = %0, %2
  %.056 = phi i32 [ 0, %0 ], [ %20, %2 ]
  %.04355 = phi i64 [ 0, %0 ], [ %3, %2 ]
  %1 = trunc nuw i64 %.04355 to i8
  br label %4

2:                                                ; preds = %4
  %3 = add nuw nsw i64 %.04355, 1
  %exitcond67.not = icmp eq i64 %3, 256
  br i1 %exitcond67.not, label %.preheader50, label %.preheader52, !llvm.loop !5

4:                                                ; preds = %.preheader52, %4
  %.154 = phi i32 [ %.056, %.preheader52 ], [ %20, %4 ]
  %.04653 = phi i64 [ 0, %.preheader52 ], [ %21, %4 ]
  %5 = trunc nuw i64 %.04653 to i8
  %6 = tail call noundef zeroext i16 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec2Ehh(i8 noundef zeroext %5, i8 noundef zeroext %1)
  %7 = tail call noundef zeroext i16 @_ZN3glm18bitfieldInterleaveEhh(i8 noundef zeroext %5, i8 noundef zeroext %1)
  %8 = icmp ne i16 %6, %7
  %9 = zext i1 %8 to i32
  %10 = add nsw i32 %.154, %9
  %11 = tail call i16 @_ZN19bitfieldInterleave527bitfieldDeinterleave_u8vec2Et(i16 noundef zeroext %6)
  %.sroa.4.0.extract.shift = lshr i16 %11, 8
  %12 = and i16 %11, 255
  %13 = zext nneg i16 %12 to i64
  %14 = icmp ne i64 %.04653, %13
  %15 = zext i1 %14 to i32
  %16 = add nsw i32 %10, %15
  %17 = zext nneg i16 %.sroa.4.0.extract.shift to i64
  %18 = icmp ne i64 %.04355, %17
  %19 = zext i1 %18 to i32
  %20 = add nsw i32 %16, %19
  %21 = add nuw nsw i64 %.04653, 1
  %exitcond.not = icmp eq i64 %21, 256
  br i1 %exitcond.not, label %2, label %4, !llvm.loop !7

.preheader50:                                     ; preds = %2, %23
  %.260 = phi i32 [ %31, %23 ], [ %20, %2 ]
  %.04859 = phi i64 [ %24, %23 ], [ 0, %2 ]
  %22 = trunc nuw i64 %.04859 to i8
  br label %25

23:                                               ; preds = %25
  %24 = add nuw nsw i64 %.04859, 1
  %exitcond69.not = icmp eq i64 %24, 256
  br i1 %exitcond69.not, label %.preheader, label %.preheader50, !llvm.loop !8

25:                                               ; preds = %.preheader50, %25
  %.358 = phi i32 [ %.260, %.preheader50 ], [ %31, %25 ]
  %.04757 = phi i64 [ 0, %.preheader50 ], [ %32, %25 ]
  %26 = trunc nuw i64 %.04757 to i8
  %27 = tail call noundef i32 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec4Ehhhh(i8 noundef zeroext %26, i8 noundef zeroext %22, i8 noundef zeroext %26, i8 noundef zeroext %22)
  %28 = tail call noundef i32 @_ZN3glm18bitfieldInterleaveEhhhh(i8 noundef zeroext %26, i8 noundef zeroext %22, i8 noundef zeroext %26, i8 noundef zeroext %22)
  %29 = icmp ne i32 %27, %28
  %30 = zext i1 %29 to i32
  %31 = add nsw i32 %.358, %30
  %32 = add nuw nsw i64 %.04757, 1
  %exitcond68.not = icmp eq i64 %32, 256
  br i1 %exitcond68.not, label %23, label %25, !llvm.loop !9

.preheader:                                       ; preds = %23, %35
  %.464 = phi i32 [ %43, %35 ], [ %31, %23 ]
  %.04563 = phi i64 [ %36, %35 ], [ 0, %23 ]
  %33 = trunc nuw nsw i64 %.04563 to i16
  br label %37

34:                                               ; preds = %35
  ret i32 %43

35:                                               ; preds = %37
  %36 = add nuw nsw i64 %.04563, 1
  %exitcond71.not = icmp eq i64 %36, 256
  br i1 %exitcond71.not, label %34, label %.preheader, !llvm.loop !10

37:                                               ; preds = %.preheader, %37
  %.562 = phi i32 [ %.464, %.preheader ], [ %43, %37 ]
  %.04461 = phi i64 [ 0, %.preheader ], [ %44, %37 ]
  %38 = trunc nuw nsw i64 %.04461 to i16
  %39 = tail call noundef i32 @_ZN19bitfieldInterleave526bitfieldInterleave_u16vec2Ett(i16 noundef zeroext %38, i16 noundef zeroext %33)
  %40 = tail call noundef i32 @_ZN3glm18bitfieldInterleaveEtt(i16 noundef zeroext %38, i16 noundef zeroext %33)
  %41 = icmp ne i32 %39, %40
  %42 = zext i1 %41 to i32
  %43 = add nsw i32 %.562, %42
  %44 = add nuw nsw i64 %.04461, 1
  %exitcond70.not = icmp eq i64 %44, 256
  br i1 %exitcond70.not, label %35, label %37, !llvm.loop !11
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec2Ehh(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN3glm18bitfieldInterleaveEhh(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local i16 @_ZN19bitfieldInterleave527bitfieldDeinterleave_u8vec2Et(i16 noundef zeroext) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN19bitfieldInterleave525bitfieldInterleave_u8vec4Ehhhh(i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveEhhhh(i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN19bitfieldInterleave526bitfieldInterleave_u16vec2Ett(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveEtt(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}
!9 = distinct !{!9, !6}
!10 = distinct !{!10, !6}
!11 = distinct !{!11, !6}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass