; LLVM IR from ubaldot/defrecs :: stm32f4x/ADC_Readings/Drivers/CMSIS/DSP/Examples/ARM (main)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.arm_lms_norm_instance_f32 = type { i16, ptr, ptr, float, float, float }
%struct.arm_fir_instance_f32 = type { i16, ptr, ptr }

@lmsNorm_instance = external dso_local global %struct.arm_lms_norm_instance_f32, align 8
@lmsNormCoeff_f32 = external global [32 x float], align 16
@lmsStateF32 = external dso_local global [64 x float], align 16
@LPF_instance = external dso_local global %struct.arm_fir_instance_f32, align 8
@FIRCoeff_f32 = external constant [32 x float], align 16
@firStateF32 = external dso_local global [64 x float], align 16
@testInput_f32 = external global [1536 x float], align 16
@wire1 = external dso_local global [32 x float], align 16
@wire2 = external dso_local global [32 x float], align 16
@wire3 = external dso_local global [32 x float], align 16
@err_signal = external dso_local global [32 x float], align 16

; Function Attrs: nounwind uwtable
define dso_local i32 @main() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca float, align 4
  store i32 0, ptr %1, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @arm_lms_norm_init_f32(ptr noundef @lmsNorm_instance, i16 noundef zeroext 32, ptr noundef @lmsNormCoeff_f32, ptr noundef @lmsStateF32, float noundef 5.000000e-01, i32 noundef 32)
  call void @arm_fir_init_f32(ptr noundef @LPF_instance, i16 noundef zeroext 32, ptr noundef @FIRCoeff_f32, ptr noundef @firStateF32, i32 noundef 32)
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %6

6:                                                ; preds = %14, %0
  %7 = load i32, ptr %2, align 4, !tbaa !5
  %8 = icmp ult i32 %7, 48
  br i1 %8, label %9, label %17

9:                                                ; preds = %6
  %10 = load i32, ptr %2, align 4, !tbaa !5
  %11 = mul i32 %10, 32
  %12 = zext i32 %11 to i64
  %13 = getelementptr inbounds float, ptr @testInput_f32, i64 %12
  call void @arm_copy_f32(ptr noundef %13, ptr noundef @wire1, i32 noundef 32)
  call void @arm_fir_f32(ptr noundef @LPF_instance, ptr noundef @wire1, ptr noundef @wire2, i32 noundef 32)
  call void @arm_lms_norm_f32(ptr noundef @lmsNorm_instance, ptr noundef @wire1, ptr noundef @wire2, ptr noundef @wire3, ptr noundef @err_signal, i32 noundef 32)
  call void @arm_scale_f32(ptr noundef @wire3, float noundef 5.000000e+00, ptr noundef @wire3, i32 noundef 32)
  br label %14

14:                                               ; preds = %9
  %15 = load i32, ptr %2, align 4, !tbaa !5
  %16 = add i32 %15, 1
  store i32 %16, ptr %2, align 4, !tbaa !5
  br label %6, !llvm.loop !9

17:                                               ; preds = %6
  store i32 0, ptr %3, align 4, !tbaa !5
  call void @arm_abs_f32(ptr noundef @err_signal, ptr noundef @err_signal, i32 noundef 32)
  call void @arm_min_f32(ptr noundef @err_signal, i32 noundef 32, ptr noundef %5, ptr noundef %4)
  %18 = load float, ptr %5, align 4, !tbaa !11
  %19 = fcmp ogt float %18, 0x3F1797CC40000000
  br i1 %19, label %20, label %21

20:                                               ; preds = %17
  store i32 -6, ptr %3, align 4, !tbaa !5
  br label %21

21:                                               ; preds = %20, %17
  call void @arm_sub_f32(ptr noundef @FIRCoeff_f32, ptr noundef @lmsNormCoeff_f32, ptr noundef @lmsNormCoeff_f32, i32 noundef 32)
  call void @arm_abs_f32(ptr noundef @lmsNormCoeff_f32, ptr noundef @lmsNormCoeff_f32, i32 noundef 32)
  call void @arm_min_f32(ptr noundef @lmsNormCoeff_f32, i32 noundef 32, ptr noundef %5, ptr noundef %4)
  %22 = load float, ptr %5, align 4, !tbaa !11
  %23 = fcmp ogt float %22, 0x3F1A36E2E0000000
  %24 = zext i1 %23 to i64
  %25 = select i1 %23, i32 -6, i32 0
  store i32 %25, ptr %3, align 4, !tbaa !5
  %26 = load i32, ptr %3, align 4, !tbaa !5
  %27 = icmp ne i32 %26, 0
  br i1 %27, label %28, label %31

28:                                               ; preds = %21
  br label %29

29:                                               ; preds = %30, %28
  br label %30

30:                                               ; preds = %29
  br label %29

31:                                               ; preds = %21
  br label %32

32:                                               ; preds = %33, %31
  br label %33

33:                                               ; preds = %32
  br label %32
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @arm_lms_norm_init_f32(ptr noundef, i16 noundef zeroext, ptr noundef, ptr noundef, float noundef, i32 noundef) #2

declare void @arm_fir_init_f32(ptr noundef, i16 noundef zeroext, ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_copy_f32(ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_fir_f32(ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_lms_norm_f32(ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_scale_f32(ptr noundef, float noundef, ptr noundef, i32 noundef) #2

declare void @arm_abs_f32(ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_min_f32(ptr noundef, i32 noundef, ptr noundef, ptr noundef) #2

declare void @arm_sub_f32(ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"float", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.arm_lms_norm_instance_f32 = type { i16, ptr, ptr, float, float, float }
%struct.arm_fir_instance_f32 = type { i16, ptr, ptr }

@lmsNorm_instance = external dso_local global %struct.arm_lms_norm_instance_f32, align 8
@lmsNormCoeff_f32 = external global [32 x float], align 16
@lmsStateF32 = external dso_local global [64 x float], align 16
@LPF_instance = external dso_local global %struct.arm_fir_instance_f32, align 8
@FIRCoeff_f32 = external constant [32 x float], align 16
@firStateF32 = external dso_local global [64 x float], align 16
@testInput_f32 = external global [1536 x float], align 16
@wire1 = external dso_local global [32 x float], align 16
@wire2 = external dso_local global [32 x float], align 16
@wire3 = external dso_local global [32 x float], align 16
@err_signal = external dso_local global [32 x float], align 16

; Function Attrs: noreturn nounwind uwtable
define dso_local noundef i32 @main() local_unnamed_addr #0 {
  %1 = alloca i32, align 4
  %2 = alloca float, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #3
  tail call void @arm_lms_norm_init_f32(ptr noundef nonnull @lmsNorm_instance, i16 noundef zeroext 32, ptr noundef nonnull @lmsNormCoeff_f32, ptr noundef nonnull @lmsStateF32, float noundef 5.000000e-01, i32 noundef 32) #3
  tail call void @arm_fir_init_f32(ptr noundef nonnull @LPF_instance, i16 noundef zeroext 32, ptr noundef nonnull @FIRCoeff_f32, ptr noundef nonnull @firStateF32, i32 noundef 32) #3
  br label %3

3:                                                ; preds = %0, %3
  %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %3 ]
  %.idx = shl nsw i64 %indvars.iv, 7
  %4 = getelementptr inbounds i8, ptr @testInput_f32, i64 %.idx
  tail call void @arm_copy_f32(ptr noundef nonnull %4, ptr noundef nonnull @wire1, i32 noundef 32) #3
  tail call void @arm_fir_f32(ptr noundef nonnull @LPF_instance, ptr noundef nonnull @wire1, ptr noundef nonnull @wire2, i32 noundef 32) #3
  tail call void @arm_lms_norm_f32(ptr noundef nonnull @lmsNorm_instance, ptr noundef nonnull @wire1, ptr noundef nonnull @wire2, ptr noundef nonnull @wire3, ptr noundef nonnull @err_signal, i32 noundef 32) #3
  tail call void @arm_scale_f32(ptr noundef nonnull @wire3, float noundef 5.000000e+00, ptr noundef nonnull @wire3, i32 noundef 32) #3
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 48
  br i1 %exitcond.not, label %5, label %3, !llvm.loop !5

5:                                                ; preds = %3
  tail call void @arm_abs_f32(ptr noundef nonnull @err_signal, ptr noundef nonnull @err_signal, i32 noundef 32) #3
  call void @arm_min_f32(ptr noundef nonnull @err_signal, i32 noundef 32, ptr noundef nonnull %2, ptr noundef nonnull %1) #3
  call void @arm_sub_f32(ptr noundef nonnull @FIRCoeff_f32, ptr noundef nonnull @lmsNormCoeff_f32, ptr noundef nonnull @lmsNormCoeff_f32, i32 noundef 32) #3
  call void @arm_abs_f32(ptr noundef nonnull @lmsNormCoeff_f32, ptr noundef nonnull @lmsNormCoeff_f32, i32 noundef 32) #3
  call void @arm_min_f32(ptr noundef nonnull @lmsNormCoeff_f32, i32 noundef 32, ptr noundef nonnull %2, ptr noundef nonnull %1) #3
  %6 = load float, ptr %2, align 4, !tbaa !7
  %7 = fcmp ogt float %6, 0x3F1A36E2E0000000
  br i1 %7, label %.preheader, label %.preheader4

.preheader:                                       ; preds = %5, %.preheader
  br label %.preheader

.preheader4:                                      ; preds = %5, %.preheader4
  br label %.preheader4
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @arm_lms_norm_init_f32(ptr noundef, i16 noundef zeroext, ptr noundef, ptr noundef, float noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_fir_init_f32(ptr noundef, i16 noundef zeroext, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_copy_f32(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_fir_f32(ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_lms_norm_f32(ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_scale_f32(ptr noundef, float noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_abs_f32(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_min_f32(ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @arm_sub_f32(ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { noreturn nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"float", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass