; LLVM IR from mitdbg/deneva :: system/txn.ll (ZN10TxnManager8get_lockEP5row_t8access_t)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Stats = type { ptr, ptr, i64, i64, i64, i64 }
%class.TxnManager = type { ptr, ptr, ptr, i8, ptr, i32, i8, i32, i32, i8, i64, i64, i64, i64, ptr, ptr, ptr, i64, i8, i8, ptr, ptr, i64, i64, i64, %class.TxnStats, i32, i32, i32, i8, i32, %class.Array.0, i32, ptr, ptr, i32, %union.sem_t }
%class.TxnStats = type { i64, i64, i64, i64, i64, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, i64, i64, double, double, double, double, double, double, double, double }
%class.Array.0 = type { ptr, i64, i64 }
%union.sem_t = type { i64, [24 x i8] }
%class.Stats_thd = type { [64 x i8], ptr, ptr, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, i64, double, i64, double, i64, i64, double, double, double, double, double, double, double, double, i64, double, double, double, double, double, double, double, double, i64, i64, double, i64, double, i64, double, double, double, i64, i64, i64, double, double, double, double, double, double, double, double, double, i64, ptr, ptr, double, i64, i64, double, double, double, i64, i64, i64, i64, i64, i64, i64, double, double, double, i64, i64, i64, i64, i64, i64, i64, i64, i64, double, double, double, double, double, i64, i64, double, double, i64, i64, i64, double, double, i64, i64, double, double, double, double, i64, i64, double, double, double, i64, i64, double, double, double, double, double, i64, double, double, double, double, double, double, double, double, i64, i64, i64, double, i64, double, double, i64, i64, i64, i64, i64, double, i64, i64, double, i64, double, double, i64, i64, i64, i64, i64, double, double, double, %class.StatsArr, %class.StatsArr, %class.StatsArr, %class.StatsArr, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, ptr, [64 x i8] }
%class.StatsArr = type { ptr, i64, i64, i32, %union.pthread_mutex_t }
%union.pthread_mutex_t = type { %struct.__pthread_mutex_s }
%struct.__pthread_mutex_s = type { i32, i32, i32, i32, i32, i16, i16, %struct.__pthread_internal_list }
%struct.__pthread_internal_list = type { ptr, ptr }

@simulation = external global ptr, align 8
@stats = external global %class.Stats, align 8

declare noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96)) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544)) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN10TxnManager8get_lockEP5row_t8access_t(ptr noundef nonnull align 8 dereferenceable(544) %0, ptr noundef %1, i32 noundef %2) #2 align 2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  %9 = load ptr, ptr %5, align 8
  %10 = getelementptr inbounds %class.TxnManager, ptr %9, i32 0, i32 31
  %11 = load ptr, ptr %6, align 8, !tbaa !5
  %12 = call noundef zeroext i1 @_ZN5ArrayIP5row_tE8containsES1_(ptr noundef nonnull align 8 dereferenceable(24) %10, ptr noundef %11)
  br i1 %12, label %13, label %14

13:                                               ; preds = %3
  store i32 0, ptr %4, align 4
  br label %36

14:                                               ; preds = %3
  %15 = getelementptr inbounds %class.TxnManager, ptr %9, i32 0, i32 31
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_ZN5ArrayIP5row_tE3addES1_(ptr noundef nonnull align 8 dereferenceable(24) %15, ptr noundef %16)
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = call noundef i32 @_ZN5row_t8get_lockE8access_tP10TxnManager(ptr noundef nonnull align 8 dereferenceable(64) %17, i32 noundef %18, ptr noundef %9)
  store i32 %19, ptr %8, align 4, !tbaa !11
  %20 = load i32, ptr %8, align 4, !tbaa !11
  %21 = icmp eq i32 %20, 3
  br i1 %21, label %22, label %34

22:                                               ; preds = %14
  %23 = load ptr, ptr @simulation, align 8, !tbaa !5
  %24 = call noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96) %23)
  br i1 %24, label %25, label %33

25:                                               ; preds = %22
  %26 = load ptr, ptr @stats, align 8, !tbaa !13
  %27 = call noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544) %9)
  %28 = getelementptr inbounds ptr, ptr %26, i64 %27
  %29 = load ptr, ptr %28, align 8, !tbaa !5
  %30 = getelementptr inbounds %class.Stats_thd, ptr %29, i32 0, i32 81
  %31 = load i64, ptr %30, align 8, !tbaa !16
  %32 = add i64 %31, 1
  store i64 %32, ptr %30, align 8, !tbaa !16
  br label %33

33:                                               ; preds = %25, %22
  br label %34

34:                                               ; preds = %33, %14
  %35 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %35, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %36

36:                                               ; preds = %34, %13
  %37 = load i32, ptr %4, align 4
  ret i32 %37
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN5ArrayIP5row_tE8containsES1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5ArrayIP5row_tE3addES1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef) #3 align 2

declare noundef i32 @_ZN5row_t8get_lockE8access_tP10TxnManager(ptr noundef nonnull align 8 dereferenceable(64), i32 noundef, ptr noundef) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS8access_t", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS2RC", !7, i64 0}
!13 = !{!14, !6, i64 0}
!14 = !{!"_ZTS5Stats", !6, i64 0, !6, i64 8, !15, i64 16, !15, i64 24, !15, i64 32, !15, i64 40}
!15 = !{!"long", !7, i64 0}
!16 = !{!17, !15, i64 704}
!17 = !{!"_ZTS9Stats_thd", !7, i64 0, !6, i64 64, !6, i64 72, !18, i64 80, !15, i64 88, !15, i64 96, !15, i64 104, !15, i64 112, !15, i64 120, !15, i64 128, !15, i64 136, !15, i64 144, !15, i64 152, !15, i64 160, !15, i64 168, !15, i64 176, !18, i64 184, !15, i64 192, !18, i64 200, !15, i64 208, !18, i64 216, !15, i64 224, !15, i64 232, !18, i64 240, !18, i64 248, !18, i64 256, !18, i64 264, !18, i64 272, !18, i64 280, !18, i64 288, !18, i64 296, !15, i64 304, !18, i64 312, !18, i64 320, !18, i64 328, !18, i64 336, !18, i64 344, !18, i64 352, !18, i64 360, !18, i64 368, !15, i64 376, !15, i64 384, !18, i64 392, !15, i64 400, !18, i64 408, !15, i64 416, !18, i64 424, !18, i64 432, !18, i64 440, !15, i64 448, !15, i64 456, !15, i64 464, !18, i64 472, !18, i64 480, !18, i64 488, !18, i64 496, !18, i64 504, !18, i64 512, !18, i64 520, !18, i64 528, !18, i64 536, !15, i64 544, !6, i64 552, !6, i64 560, !18, i64 568, !15, i64 576, !15, i64 584, !18, i64 592, !18, i64 600, !18, i64 608, !15, i64 616, !15, i64 624, !15, i64 632, !15, i64 640, !15, i64 648, !15, i64 656, !15, i64 664, !18, i64 672, !18, i64 680, !18, i64 688, !15, i64 696, !15, i64 704, !15, i64 712, !15, i64 720, !15, i64 728, !15, i64 736, !15, i64 744, !15, i64 752, !15, i64 760, !18, i64 768, !18, i64 776, !18, i64 784, !18, i64 792, !18, i64 800, !15, i64 808, !15, i64 816, !18, i64 824, !18, i64 832, !15, i64 840, !15, i64 848, !15, i64 856, !18, i64 864, !18, i64 872, !15, i64 880, !15, i64 888, !18, i64 896, !18, i64 904, !18, i64 912, !18, i64 920, !15, i64 928, !15, i64 936, !18, i64 944, !18, i64 952, !18, i64 960, !15, i64 968, !15, i64 976, !18, i64 984, !18, i64 992, !18, i64 1000, !18, i64 1008, !18, i64 1016, !15, i64 1024, !18, i64 1032, !18, i64 1040, !18, i64 1048, !18, i64 1056, !18, i64 1064, !18, i64 1072, !18, i64 1080, !18, i64 1088, !15, i64 1096, !15, i64 1104, !15, i64 1112, !18, i64 1120, !15, i64 1128, !18, i64 1136, !18, i64 1144, !15, i64 1152, !15, i64 1160, !15, i64 1168, !15, i64 1176, !15, i64 1184, !18, i64 1192, !15, i64 1200, !15, i64 1208, !18, i64 1216, !15, i64 1224, !18, i64 1232, !18, i64 1240, !15, i64 1248, !15, i64 1256, !15, i64 1264, !15, i64 1272, !15, i64 1280, !18, i64 1288, !18, i64 1296, !18, i64 1304, !19, i64 1312, !19, i64 1384, !19, i64 1456, !19, i64 1528, !18, i64 1600, !18, i64 1608, !18, i64 1616, !18, i64 1624, !18, i64 1632, !18, i64 1640, !18, i64 1648, !18, i64 1656, !18, i64 1664, !18, i64 1672, !18, i64 1680, !18, i64 1688, !18, i64 1696, !18, i64 1704, !18, i64 1712, !18, i64 1720, !18, i64 1728, !18, i64 1736, !18, i64 1744, !18, i64 1752, !18, i64 1760, !18, i64 1768, !18, i64 1776, !18, i64 1784, !18, i64 1792, !18, i64 1800, !18, i64 1808, !18, i64 1816, !18, i64 1824, !18, i64 1832, !18, i64 1840, !18, i64 1848, !18, i64 1856, !18, i64 1864, !18, i64 1872, !18, i64 1880, !6, i64 1888, !7, i64 1896}
!18 = !{!"double", !7, i64 0}
!19 = !{!"_ZTS8StatsArr", !6, i64 0, !15, i64 8, !15, i64 16, !20, i64 24, !7, i64 32}
!20 = !{!"_ZTS12StatsArrType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Stats = type { ptr, ptr, i64, i64, i64, i64 }

@simulation = external local_unnamed_addr global ptr, align 8
@stats = external local_unnamed_addr global %class.Stats, align 8

declare noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96)) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN10TxnManager8get_lockEP5row_t8access_t(ptr noundef nonnull align 8 dereferenceable(544) %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #1 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 456
  %5 = tail call noundef zeroext i1 @_ZN5ArrayIP5row_tE8containsES1_(ptr noundef nonnull align 8 dereferenceable(24) %4, ptr noundef %1)
  br i1 %5, label %20, label %6

6:                                                ; preds = %3
  tail call void @_ZN5ArrayIP5row_tE3addES1_(ptr noundef nonnull align 8 dereferenceable(24) %4, ptr noundef %1)
  %7 = tail call noundef i32 @_ZN5row_t8get_lockE8access_tP10TxnManager(ptr noundef nonnull align 8 dereferenceable(64) %1, i32 noundef %2, ptr noundef nonnull %0)
  %8 = icmp eq i32 %7, 3
  br i1 %8, label %9, label %20

9:                                                ; preds = %6
  %10 = load ptr, ptr @simulation, align 8, !tbaa !5
  %11 = tail call noundef zeroext i1 @_ZN10SimManager14is_warmup_doneEv(ptr noundef nonnull align 8 dereferenceable(96) %10)
  br i1 %11, label %12, label %20

12:                                               ; preds = %9
  %13 = load ptr, ptr @stats, align 8, !tbaa !9
  %14 = tail call noundef i64 @_ZN10TxnManager10get_thd_idEv(ptr noundef nonnull align 8 dereferenceable(544) %0)
  %15 = getelementptr inbounds ptr, ptr %13, i64 %14
  %16 = load ptr, ptr %15, align 8, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %16, i64 704
  %18 = load i64, ptr %17, align 8, !tbaa !12
  %19 = add i64 %18, 1
  store i64 %19, ptr %17, align 8, !tbaa !12
  br label %20

20:                                               ; preds = %6, %12, %9, %3
  %.0 = phi i32 [ 0, %3 ], [ 3, %9 ], [ 3, %12 ], [ %7, %6 ]
  ret i32 %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN5ArrayIP5row_tE8containsES1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN5ArrayIP5row_tE3addES1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef) local_unnamed_addr #2 align 2

declare noundef i32 @_ZN5row_t8get_lockE8access_tP10TxnManager(ptr noundef nonnull align 8 dereferenceable(64), i32 noundef, ptr noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTS5Stats", !6, i64 0, !6, i64 8, !11, i64 16, !11, i64 24, !11, i64 32, !11, i64 40}
!11 = !{!"long", !7, i64 0}
!12 = !{!13, !11, i64 704}
!13 = !{!"_ZTS9Stats_thd", !7, i64 0, !6, i64 64, !6, i64 72, !14, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !11, i64 144, !11, i64 152, !11, i64 160, !11, i64 168, !11, i64 176, !14, i64 184, !11, i64 192, !14, i64 200, !11, i64 208, !14, i64 216, !11, i64 224, !11, i64 232, !14, i64 240, !14, i64 248, !14, i64 256, !14, i64 264, !14, i64 272, !14, i64 280, !14, i64 288, !14, i64 296, !11, i64 304, !14, i64 312, !14, i64 320, !14, i64 328, !14, i64 336, !14, i64 344, !14, i64 352, !14, i64 360, !14, i64 368, !11, i64 376, !11, i64 384, !14, i64 392, !11, i64 400, !14, i64 408, !11, i64 416, !14, i64 424, !14, i64 432, !14, i64 440, !11, i64 448, !11, i64 456, !11, i64 464, !14, i64 472, !14, i64 480, !14, i64 488, !14, i64 496, !14, i64 504, !14, i64 512, !14, i64 520, !14, i64 528, !14, i64 536, !11, i64 544, !6, i64 552, !6, i64 560, !14, i64 568, !11, i64 576, !11, i64 584, !14, i64 592, !14, i64 600, !14, i64 608, !11, i64 616, !11, i64 624, !11, i64 632, !11, i64 640, !11, i64 648, !11, i64 656, !11, i64 664, !14, i64 672, !14, i64 680, !14, i64 688, !11, i64 696, !11, i64 704, !11, i64 712, !11, i64 720, !11, i64 728, !11, i64 736, !11, i64 744, !11, i64 752, !11, i64 760, !14, i64 768, !14, i64 776, !14, i64 784, !14, i64 792, !14, i64 800, !11, i64 808, !11, i64 816, !14, i64 824, !14, i64 832, !11, i64 840, !11, i64 848, !11, i64 856, !14, i64 864, !14, i64 872, !11, i64 880, !11, i64 888, !14, i64 896, !14, i64 904, !14, i64 912, !14, i64 920, !11, i64 928, !11, i64 936, !14, i64 944, !14, i64 952, !14, i64 960, !11, i64 968, !11, i64 976, !14, i64 984, !14, i64 992, !14, i64 1000, !14, i64 1008, !14, i64 1016, !11, i64 1024, !14, i64 1032, !14, i64 1040, !14, i64 1048, !14, i64 1056, !14, i64 1064, !14, i64 1072, !14, i64 1080, !14, i64 1088, !11, i64 1096, !11, i64 1104, !11, i64 1112, !14, i64 1120, !11, i64 1128, !14, i64 1136, !14, i64 1144, !11, i64 1152, !11, i64 1160, !11, i64 1168, !11, i64 1176, !11, i64 1184, !14, i64 1192, !11, i64 1200, !11, i64 1208, !14, i64 1216, !11, i64 1224, !14, i64 1232, !14, i64 1240, !11, i64 1248, !11, i64 1256, !11, i64 1264, !11, i64 1272, !11, i64 1280, !14, i64 1288, !14, i64 1296, !14, i64 1304, !15, i64 1312, !15, i64 1384, !15, i64 1456, !15, i64 1528, !14, i64 1600, !14, i64 1608, !14, i64 1616, !14, i64 1624, !14, i64 1632, !14, i64 1640, !14, i64 1648, !14, i64 1656, !14, i64 1664, !14, i64 1672, !14, i64 1680, !14, i64 1688, !14, i64 1696, !14, i64 1704, !14, i64 1712, !14, i64 1720, !14, i64 1728, !14, i64 1736, !14, i64 1744, !14, i64 1752, !14, i64 1760, !14, i64 1768, !14, i64 1776, !14, i64 1784, !14, i64 1792, !14, i64 1800, !14, i64 1808, !14, i64 1816, !14, i64 1824, !14, i64 1832, !14, i64 1840, !14, i64 1848, !14, i64 1856, !14, i64 1864, !14, i64 1872, !14, i64 1880, !6, i64 1888, !7, i64 1896}
!14 = !{!"double", !7, i64 0}
!15 = !{!"_ZTS8StatsArr", !6, i64 0, !11, i64 8, !11, i64 16, !16, i64 24, !7, i64 32}
!16 = !{!"_ZTS12StatsArrType", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass