; LLVM IR from jpvt/Computer_Graphics :: Assignment #3/third_party/glm/test/gtc/gtc_bitfield.ll (ZN18bitfieldInterleave4testEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.glm::vec.9" = type { %union.anon.10, %union.anon.11 }
%union.anon.10 = type { i8 }
%union.anon.11 = type { i8 }
%"struct.glm::vec.12" = type { %union.anon.13, %union.anon.14 }
%union.anon.13 = type { i16 }
%union.anon.14 = type { i16 }
%"struct.glm::vec.15" = type { %union.anon.16, %union.anon.17 }
%union.anon.16 = type { i32 }
%union.anon.17 = type { i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN18bitfieldInterleave4testEv() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i8, align 1
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  %5 = alloca i64, align 8
  %6 = alloca %"struct.glm::vec.9", align 1
  %7 = alloca i64, align 8
  %8 = alloca %"struct.glm::vec.12", align 2
  %9 = alloca i64, align 8
  %10 = alloca %"struct.glm::vec.15", align 4
  %11 = alloca ptr, align 8
  %12 = alloca %"struct.glm::vec.15", align 4
  %13 = alloca i8, align 1
  %14 = alloca i8, align 1
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca i64, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #4
  store i32 0, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %2) #4
  store i8 0, ptr %2, align 1, !tbaa !9
  br label %18

18:                                               ; preds = %81, %0
  %19 = load i8, ptr %2, align 1, !tbaa !9
  %20 = zext i8 %19 to i32
  %21 = icmp slt i32 %20, 127
  br i1 %21, label %23, label %22

22:                                               ; preds = %18
  store i32 2, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %2) #4
  br label %84

23:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #4
  store i8 0, ptr %4, align 1, !tbaa !9
  br label %24

24:                                               ; preds = %77, %23
  %25 = load i8, ptr %4, align 1, !tbaa !9
  %26 = zext i8 %25 to i32
  %27 = icmp slt i32 %26, 127
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  store i32 5, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #4
  br label %80

29:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #4
  %30 = load i8, ptr %4, align 1, !tbaa !9
  %31 = load i8, ptr %2, align 1, !tbaa !9
  call void @_ZN3glm3vecILi2EhLNS_9qualifierE0EEC2Ehh(ptr noundef nonnull align 1 dereferenceable(2) %6, i8 noundef zeroext %30, i8 noundef zeroext %31)
  %32 = call noundef zeroext i16 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EhLNS_9qualifierE0EEE(ptr noundef nonnull align 1 dereferenceable(2) %6)
  %33 = zext i16 %32 to i64
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #4
  store i64 %33, ptr %5, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %34 = load i8, ptr %4, align 1, !tbaa !9
  %35 = load i8, ptr %2, align 1, !tbaa !9
  call void @_ZN3glm3vecILi2EtLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 2 dereferenceable(4) %8, i8 noundef zeroext %34, i8 noundef zeroext %35)
  %36 = call noundef i32 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EtLNS_9qualifierE0EEE(ptr noundef nonnull align 2 dereferenceable(4) %8)
  %37 = zext i32 %36 to i64
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  store i64 %37, ptr %7, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %38 = load i8, ptr %4, align 1, !tbaa !9
  %39 = load i8, ptr %2, align 1, !tbaa !9
  call void @_ZN3glm3vecILi2EjLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 4 dereferenceable(8) %10, i8 noundef zeroext %38, i8 noundef zeroext %39)
  %40 = call noundef i64 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EjLNS_9qualifierE0EEE(ptr noundef nonnull align 4 dereferenceable(8) %10)
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  store i64 %40, ptr %9, align 8, !tbaa !10
  %41 = load i64, ptr %5, align 8, !tbaa !10
  %42 = load i64, ptr %7, align 8, !tbaa !10
  %43 = icmp eq i64 %41, %42
  %44 = zext i1 %43 to i64
  %45 = select i1 %43, i32 0, i32 1
  %46 = load i32, ptr %1, align 4, !tbaa !5
  %47 = add nsw i32 %46, %45
  store i32 %47, ptr %1, align 4, !tbaa !5
  %48 = load i64, ptr %5, align 8, !tbaa !10
  %49 = load i64, ptr %9, align 8, !tbaa !10
  %50 = icmp eq i64 %48, %49
  %51 = zext i1 %50 to i64
  %52 = select i1 %50, i32 0, i32 1
  %53 = load i32, ptr %1, align 4, !tbaa !5
  %54 = add nsw i32 %53, %52
  store i32 %54, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %55 = load i64, ptr %9, align 8, !tbaa !10
  %56 = call i64 @_ZN3glm20bitfieldDeinterleaveEm(i64 noundef %55)
  store i64 %56, ptr %12, align 4
  store ptr %12, ptr %11, align 8, !tbaa !12
  %57 = load ptr, ptr %11, align 8, !tbaa !12
  %58 = getelementptr inbounds %"struct.glm::vec.15", ptr %57, i32 0, i32 0
  %59 = load i32, ptr %58, align 4, !tbaa !9
  %60 = load i8, ptr %4, align 1, !tbaa !9
  %61 = zext i8 %60 to i32
  %62 = icmp eq i32 %59, %61
  %63 = zext i1 %62 to i64
  %64 = select i1 %62, i32 0, i32 1
  %65 = load i32, ptr %1, align 4, !tbaa !5
  %66 = add nsw i32 %65, %64
  store i32 %66, ptr %1, align 4, !tbaa !5
  %67 = load ptr, ptr %11, align 8, !tbaa !12
  %68 = getelementptr inbounds %"struct.glm::vec.15", ptr %67, i32 0, i32 1
  %69 = load i32, ptr %68, align 4, !tbaa !9
  %70 = load i8, ptr %2, align 1, !tbaa !9
  %71 = zext i8 %70 to i32
  %72 = icmp eq i32 %69, %71
  %73 = zext i1 %72 to i64
  %74 = select i1 %72, i32 0, i32 1
  %75 = load i32, ptr %1, align 4, !tbaa !5
  %76 = add nsw i32 %75, %74
  store i32 %76, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  br label %77

77:                                               ; preds = %29
  %78 = load i8, ptr %4, align 1, !tbaa !9
  %79 = add i8 %78, 1
  store i8 %79, ptr %4, align 1, !tbaa !9
  br label %24, !llvm.loop !14

80:                                               ; preds = %28
  br label %81

81:                                               ; preds = %80
  %82 = load i8, ptr %2, align 1, !tbaa !9
  %83 = add i8 %82, 1
  store i8 %83, ptr %2, align 1, !tbaa !9
  br label %18, !llvm.loop !16

84:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #4
  store i8 0, ptr %13, align 1, !tbaa !9
  br label %85

85:                                               ; preds = %130, %84
  %86 = load i8, ptr %13, align 1, !tbaa !9
  %87 = zext i8 %86 to i32
  %88 = icmp slt i32 %87, 127
  br i1 %88, label %90, label %89

89:                                               ; preds = %85
  store i32 8, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #4
  br label %133

90:                                               ; preds = %85
  call void @llvm.lifetime.start.p0(i64 1, ptr %14) #4
  store i8 0, ptr %14, align 1, !tbaa !9
  br label %91

91:                                               ; preds = %126, %90
  %92 = load i8, ptr %14, align 1, !tbaa !9
  %93 = zext i8 %92 to i32
  %94 = icmp slt i32 %93, 127
  br i1 %94, label %96, label %95

95:                                               ; preds = %91
  store i32 11, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #4
  br label %129

96:                                               ; preds = %91
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  %97 = load i8, ptr %14, align 1, !tbaa !9
  %98 = load i8, ptr %13, align 1, !tbaa !9
  %99 = call noundef signext i16 @_ZN3glm18bitfieldInterleaveEaa(i8 noundef signext %97, i8 noundef signext %98)
  %100 = sext i16 %99 to i64
  store i64 %100, ptr %15, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #4
  %101 = load i8, ptr %14, align 1, !tbaa !9
  %102 = zext i8 %101 to i16
  %103 = load i8, ptr %13, align 1, !tbaa !9
  %104 = zext i8 %103 to i16
  %105 = call noundef i32 @_ZN3glm18bitfieldInterleaveEss(i16 noundef signext %102, i16 noundef signext %104)
  %106 = sext i32 %105 to i64
  store i64 %106, ptr %16, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %107 = load i8, ptr %14, align 1, !tbaa !9
  %108 = zext i8 %107 to i32
  %109 = load i8, ptr %13, align 1, !tbaa !9
  %110 = zext i8 %109 to i32
  %111 = call noundef i64 @_ZN3glm18bitfieldInterleaveEii(i32 noundef %108, i32 noundef %110)
  store i64 %111, ptr %17, align 8, !tbaa !10
  %112 = load i64, ptr %15, align 8, !tbaa !10
  %113 = load i64, ptr %16, align 8, !tbaa !10
  %114 = icmp eq i64 %112, %113
  %115 = zext i1 %114 to i64
  %116 = select i1 %114, i32 0, i32 1
  %117 = load i32, ptr %1, align 4, !tbaa !5
  %118 = add nsw i32 %117, %116
  store i32 %118, ptr %1, align 4, !tbaa !5
  %119 = load i64, ptr %15, align 8, !tbaa !10
  %120 = load i64, ptr %17, align 8, !tbaa !10
  %121 = icmp eq i64 %119, %120
  %122 = zext i1 %121 to i64
  %123 = select i1 %121, i32 0, i32 1
  %124 = load i32, ptr %1, align 4, !tbaa !5
  %125 = add nsw i32 %124, %123
  store i32 %125, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  br label %126

126:                                              ; preds = %96
  %127 = load i8, ptr %14, align 1, !tbaa !9
  %128 = add i8 %127, 1
  store i8 %128, ptr %14, align 1, !tbaa !9
  br label %91, !llvm.loop !17

129:                                              ; preds = %95
  br label %130

130:                                              ; preds = %129
  %131 = load i8, ptr %13, align 1, !tbaa !9
  %132 = add i8 %131, 1
  store i8 %132, ptr %13, align 1, !tbaa !9
  br label %85, !llvm.loop !18

133:                                              ; preds = %89
  %134 = load i32, ptr %1, align 4, !tbaa !5
  store i32 1, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #4
  ret i32 %134
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EhLNS_9qualifierE0EEE(ptr noundef nonnull align 1 dereferenceable(2)) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3glm3vecILi2EhLNS_9qualifierE0EEC2Ehh(ptr noundef nonnull align 1 dereferenceable(2), i8 noundef zeroext, i8 noundef zeroext) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EtLNS_9qualifierE0EEE(ptr noundef nonnull align 2 dereferenceable(4)) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3glm3vecILi2EtLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 2 dereferenceable(4), i8 noundef zeroext, i8 noundef zeroext) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i64 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EjLNS_9qualifierE0EEE(ptr noundef nonnull align 4 dereferenceable(8)) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3glm3vecILi2EjLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 4 dereferenceable(8), i8 noundef zeroext, i8 noundef zeroext) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local i64 @_ZN3glm20bitfieldDeinterleaveEm(i64 noundef) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef signext i16 @_ZN3glm18bitfieldInterleaveEaa(i8 noundef signext, i8 noundef signext) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveEss(i16 noundef signext, i16 noundef signext) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i64 @_ZN3glm18bitfieldInterleaveEii(i32 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"long", !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.glm::vec.9" = type { %union.anon.10, %union.anon.11 }
%union.anon.10 = type { i8 }
%union.anon.11 = type { i8 }
%"struct.glm::vec.12" = type { %union.anon.13, %union.anon.14 }
%union.anon.13 = type { i16 }
%union.anon.14 = type { i16 }
%"struct.glm::vec.15" = type { %union.anon.16, %union.anon.17 }
%union.anon.16 = type { i32 }
%union.anon.17 = type { i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN18bitfieldInterleave4testEv() local_unnamed_addr #1 {
  %1 = alloca %"struct.glm::vec.9", align 1
  %2 = alloca %"struct.glm::vec.12", align 2
  %3 = alloca %"struct.glm::vec.15", align 4
  br label %.preheader49

.preheader49:                                     ; preds = %0, %5
  %indvars.iv60 = phi i64 [ 0, %0 ], [ %indvars.iv.next61, %5 ]
  %.053 = phi i32 [ 0, %0 ], [ %25, %5 ]
  %4 = trunc nuw nsw i64 %indvars.iv60 to i8
  br label %6

5:                                                ; preds = %6
  %indvars.iv.next61 = add nuw nsw i64 %indvars.iv60, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next61, 127
  br i1 %exitcond.not, label %.preheader, label %.preheader49, !llvm.loop !5

6:                                                ; preds = %.preheader49, %6
  %indvars.iv = phi i32 [ 0, %.preheader49 ], [ %indvars.iv.next, %6 ]
  %.151 = phi i32 [ %.053, %.preheader49 ], [ %25, %6 ]
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %1) #4
  %7 = trunc nuw nsw i32 %indvars.iv to i8
  call void @_ZN3glm3vecILi2EhLNS_9qualifierE0EEC2Ehh(ptr noundef nonnull align 1 dereferenceable(2) %1, i8 noundef zeroext %7, i8 noundef zeroext %4)
  %8 = call noundef zeroext i16 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EhLNS_9qualifierE0EEE(ptr noundef nonnull align 1 dereferenceable(2) %1)
  %9 = zext i16 %8 to i64
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %1) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #4
  call void @_ZN3glm3vecILi2EtLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 2 dereferenceable(4) %2, i8 noundef zeroext %7, i8 noundef zeroext %4)
  %10 = call noundef i32 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EtLNS_9qualifierE0EEE(ptr noundef nonnull align 2 dereferenceable(4) %2)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #4
  call void @_ZN3glm3vecILi2EjLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 4 dereferenceable(8) %3, i8 noundef zeroext %7, i8 noundef zeroext %4)
  %11 = call noundef i64 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EjLNS_9qualifierE0EEE(ptr noundef nonnull align 4 dereferenceable(8) %3)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #4
  %12 = zext i16 %8 to i32
  %13 = icmp ne i32 %10, %12
  %14 = zext i1 %13 to i32
  %15 = add nsw i32 %.151, %14
  %16 = icmp ne i64 %11, %9
  %17 = zext i1 %16 to i32
  %18 = add nsw i32 %15, %17
  %19 = call i64 @_ZN3glm20bitfieldDeinterleaveEm(i64 noundef %11)
  %.sroa.0.0.extract.trunc = trunc i64 %19 to i32
  %.sroa.4.0.extract.shift = lshr i64 %19, 32
  %20 = icmp ne i32 %indvars.iv, %.sroa.0.0.extract.trunc
  %21 = zext i1 %20 to i32
  %22 = add nsw i32 %18, %21
  %23 = icmp ne i64 %.sroa.4.0.extract.shift, %indvars.iv60
  %24 = zext i1 %23 to i32
  %25 = add nsw i32 %22, %24
  %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
  %.not47 = icmp eq i32 %indvars.iv.next, 127
  br i1 %.not47, label %5, label %6, !llvm.loop !7

.preheader:                                       ; preds = %5, %29
  %indvars.iv66 = phi i32 [ %indvars.iv.next67, %29 ], [ 0, %5 ]
  %.257 = phi i32 [ %43, %29 ], [ %25, %5 ]
  %26 = trunc nuw nsw i32 %indvars.iv66 to i16
  %27 = trunc nuw nsw i32 %indvars.iv66 to i8
  br label %30

28:                                               ; preds = %29
  ret i32 %43

29:                                               ; preds = %30
  %indvars.iv.next67 = add nuw nsw i32 %indvars.iv66, 1
  %exitcond69.not = icmp eq i32 %indvars.iv.next67, 127
  br i1 %exitcond69.not, label %28, label %.preheader, !llvm.loop !8

30:                                               ; preds = %.preheader, %30
  %indvars.iv63 = phi i32 [ 0, %.preheader ], [ %indvars.iv.next64, %30 ]
  %.355 = phi i32 [ %.257, %.preheader ], [ %43, %30 ]
  %31 = trunc nuw nsw i32 %indvars.iv63 to i8
  %32 = call noundef signext i16 @_ZN3glm18bitfieldInterleaveEaa(i8 noundef signext %31, i8 noundef signext %27)
  %33 = sext i16 %32 to i64
  %34 = trunc nuw nsw i32 %indvars.iv63 to i16
  %35 = call noundef i32 @_ZN3glm18bitfieldInterleaveEss(i16 noundef signext %34, i16 noundef signext %26)
  %36 = call noundef i64 @_ZN3glm18bitfieldInterleaveEii(i32 noundef %indvars.iv63, i32 noundef %indvars.iv66)
  %37 = sext i16 %32 to i32
  %38 = icmp ne i32 %35, %37
  %39 = zext i1 %38 to i32
  %40 = add nsw i32 %.355, %39
  %41 = icmp ne i64 %36, %33
  %42 = zext i1 %41 to i32
  %43 = add nsw i32 %40, %42
  %indvars.iv.next64 = add nuw nsw i32 %indvars.iv63, 1
  %.not = icmp eq i32 %indvars.iv.next64, 127
  br i1 %.not, label %29, label %30, !llvm.loop !9
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EhLNS_9qualifierE0EEE(ptr noundef nonnull align 1 dereferenceable(2)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3glm3vecILi2EhLNS_9qualifierE0EEC2Ehh(ptr noundef nonnull align 1 dereferenceable(2), i8 noundef zeroext, i8 noundef zeroext) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EtLNS_9qualifierE0EEE(ptr noundef nonnull align 2 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3glm3vecILi2EtLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 2 dereferenceable(4), i8 noundef zeroext, i8 noundef zeroext) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i64 @_ZN3glm18bitfieldInterleaveERKNS_3vecILi2EjLNS_9qualifierE0EEE(ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3glm3vecILi2EjLNS_9qualifierE0EEC2IhhEET_T0_(ptr noundef nonnull align 4 dereferenceable(8), i8 noundef zeroext, i8 noundef zeroext) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local i64 @_ZN3glm20bitfieldDeinterleaveEm(i64 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef signext i16 @_ZN3glm18bitfieldInterleaveEaa(i8 noundef signext, i8 noundef signext) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN3glm18bitfieldInterleaveEss(i16 noundef signext, i16 noundef signext) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i64 @_ZN3glm18bitfieldInterleaveEii(i32 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}
!9 = distinct !{!9, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass