; LLVM IR from ubaldot/defrecs :: stm32f4x/ADC_Readings/Drivers/CMSIS/DSP/Source/TransformFunctions (q15)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.arm_matrix_instance_q15 = type { i16, i16, ptr }
%struct.arm_mfcc_instance_q15 = type { ptr, ptr, ptr, ptr, ptr, i32, i32, i32, %struct.arm_rfft_instance_q15 }
%struct.arm_rfft_instance_q15 = type { i32, i8, i8, i32, ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SSAT(i32 noundef, i32 noundef) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) #1

declare void @arm_vlog_q31(ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_offset_q31(ptr noundef, i32 noundef, ptr noundef, i32 noundef) #2

declare void @arm_shift_q31(ptr noundef, i8 noundef signext, ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_mfcc_q15(ptr noundef %0, ptr noundef %1, ptr noundef %2, ptr noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i16, align 2
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i64, align 8
  %15 = alloca %struct.arm_matrix_instance_q15, align 8
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  %21 = alloca i16, align 2
  %22 = alloca i16, align 2
  %23 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store ptr %3, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  store i32 0, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %15) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #4
  %24 = load ptr, ptr %9, align 8, !tbaa !5
  store ptr %24, ptr %19, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #4
  store i32 0, ptr %20, align 4, !tbaa !9
  %25 = load ptr, ptr %7, align 8, !tbaa !5
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %26, i32 0, i32 5
  %28 = load i32, ptr %27, align 8, !tbaa !11
  call void @arm_absmax_q15(ptr noundef %25, i32 noundef %28, ptr noundef %10, ptr noundef %11)
  %29 = load i16, ptr %10, align 2, !tbaa !14
  %30 = sext i16 %29 to i32
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %51

32:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 2, ptr %21) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %22) #4
  %33 = load i16, ptr %10, align 2, !tbaa !14
  %34 = call i32 @arm_divide_q15(i16 noundef signext 32767, i16 noundef signext %33, ptr noundef %21, ptr noundef %22)
  store i32 %34, ptr %20, align 4, !tbaa !9
  %35 = load i32, ptr %20, align 4, !tbaa !9
  %36 = icmp ne i32 %35, 0
  br i1 %36, label %37, label %39

37:                                               ; preds = %32
  %38 = load i32, ptr %20, align 4, !tbaa !9
  store i32 %38, ptr %5, align 4
  store i32 1, ptr %23, align 4
  br label %48

39:                                               ; preds = %32
  %40 = load ptr, ptr %7, align 8, !tbaa !5
  %41 = load i16, ptr %21, align 2, !tbaa !14
  %42 = load i16, ptr %22, align 2, !tbaa !14
  %43 = trunc i16 %42 to i8
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %45, i32 0, i32 5
  %47 = load i32, ptr %46, align 8, !tbaa !11
  call void @arm_scale_q15(ptr noundef %40, i16 noundef signext %41, i8 noundef signext %43, ptr noundef %44, i32 noundef %47)
  store i32 0, ptr %23, align 4
  br label %48

48:                                               ; preds = %39, %37
  call void @llvm.lifetime.end.p0(i64 2, ptr %22) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %21) #4
  %49 = load i32, ptr %23, align 4
  switch i32 %49, label %194 [
    i32 0, label %50
  ]

50:                                               ; preds = %48
  br label %51

51:                                               ; preds = %50, %4
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = load ptr, ptr %6, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %53, i32 0, i32 2
  %55 = load ptr, ptr %54, align 8, !tbaa !16
  %56 = load ptr, ptr %7, align 8, !tbaa !5
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %57, i32 0, i32 5
  %59 = load i32, ptr %58, align 8, !tbaa !11
  call void @arm_mult_q15(ptr noundef %52, ptr noundef %55, ptr noundef %56, i32 noundef %59)
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %60, i32 0, i32 5
  %62 = load i32, ptr %61, align 8, !tbaa !11
  %63 = call zeroext i8 @__CLZ(i32 noundef %62)
  %64 = zext i8 %63 to i32
  %65 = sub nsw i32 31, %64
  store i32 %65, ptr %12, align 4, !tbaa !9
  %66 = load ptr, ptr %6, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %66, i32 0, i32 8
  %68 = load ptr, ptr %7, align 8, !tbaa !5
  %69 = load ptr, ptr %19, align 8, !tbaa !5
  call void @arm_rfft_q15(ptr noundef %67, ptr noundef %68, ptr noundef %69)
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %70, i32 0, i32 5
  %72 = load i32, ptr %71, align 8, !tbaa !11
  %73 = lshr i32 %72, 1
  %74 = add i32 1, %73
  store i32 %74, ptr %18, align 4, !tbaa !9
  %75 = load ptr, ptr %19, align 8, !tbaa !5
  %76 = load ptr, ptr %7, align 8, !tbaa !5
  %77 = load i32, ptr %18, align 4, !tbaa !9
  call void @arm_cmplx_mag_q15(ptr noundef %75, ptr noundef %76, i32 noundef %77)
  store i32 0, ptr %17, align 4, !tbaa !9
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %78

78:                                               ; preds = %128, %51
  %79 = load i32, ptr %16, align 4, !tbaa !9
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %80, i32 0, i32 6
  %82 = load i32, ptr %81, align 4, !tbaa !17
  %83 = icmp ult i32 %79, %82
  br i1 %83, label %84, label %131

84:                                               ; preds = %78
  %85 = load ptr, ptr %7, align 8, !tbaa !5
  %86 = load ptr, ptr %6, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %86, i32 0, i32 3
  %88 = load ptr, ptr %87, align 8, !tbaa !18
  %89 = load i32, ptr %16, align 4, !tbaa !9
  %90 = zext i32 %89 to i64
  %91 = getelementptr inbounds i32, ptr %88, i64 %90
  %92 = load i32, ptr %91, align 4, !tbaa !9
  %93 = zext i32 %92 to i64
  %94 = getelementptr inbounds i16, ptr %85, i64 %93
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %95, i32 0, i32 1
  %97 = load ptr, ptr %96, align 8, !tbaa !19
  %98 = load i32, ptr %17, align 4, !tbaa !9
  %99 = zext i32 %98 to i64
  %100 = getelementptr inbounds i16, ptr %97, i64 %99
  %101 = load ptr, ptr %6, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %101, i32 0, i32 4
  %103 = load ptr, ptr %102, align 8, !tbaa !20
  %104 = load i32, ptr %16, align 4, !tbaa !9
  %105 = zext i32 %104 to i64
  %106 = getelementptr inbounds i32, ptr %103, i64 %105
  %107 = load i32, ptr %106, align 4, !tbaa !9
  call void @arm_dot_prod_q15(ptr noundef %94, ptr noundef %100, i32 noundef %107, ptr noundef %14)
  %108 = load ptr, ptr %6, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %108, i32 0, i32 4
  %110 = load ptr, ptr %109, align 8, !tbaa !20
  %111 = load i32, ptr %16, align 4, !tbaa !9
  %112 = zext i32 %111 to i64
  %113 = getelementptr inbounds i32, ptr %110, i64 %112
  %114 = load i32, ptr %113, align 4, !tbaa !9
  %115 = load i32, ptr %17, align 4, !tbaa !9
  %116 = add i32 %115, %114
  store i32 %116, ptr %17, align 4, !tbaa !9
  %117 = load i64, ptr %14, align 8, !tbaa !21
  %118 = add nsw i64 %117, 537
  store i64 %118, ptr %14, align 8, !tbaa !21
  %119 = load i64, ptr %14, align 8, !tbaa !21
  %120 = ashr i64 %119, 10
  store i64 %120, ptr %14, align 8, !tbaa !21
  %121 = load i64, ptr %14, align 8, !tbaa !21
  %122 = trunc i64 %121 to i32
  %123 = call i32 @__SSAT(i32 noundef %122, i32 noundef 31)
  %124 = load ptr, ptr %9, align 8, !tbaa !5
  %125 = load i32, ptr %16, align 4, !tbaa !9
  %126 = zext i32 %125 to i64
  %127 = getelementptr inbounds i32, ptr %124, i64 %126
  store i32 %123, ptr %127, align 4, !tbaa !9
  br label %128

128:                                              ; preds = %84
  %129 = load i32, ptr %16, align 4, !tbaa !9
  %130 = add i32 %129, 1
  store i32 %130, ptr %16, align 4, !tbaa !9
  br label %78, !llvm.loop !23

131:                                              ; preds = %78
  %132 = load ptr, ptr %9, align 8, !tbaa !5
  %133 = load ptr, ptr %9, align 8, !tbaa !5
  %134 = load ptr, ptr %6, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %134, i32 0, i32 6
  %136 = load i32, ptr %135, align 4, !tbaa !17
  call void @arm_vlog_q31(ptr noundef %132, ptr noundef %133, i32 noundef %136)
  %137 = load i32, ptr %12, align 4, !tbaa !9
  %138 = add i32 %137, 2
  %139 = add i32 %138, 10
  store i32 %139, ptr %13, align 4, !tbaa !9
  %140 = load i32, ptr %13, align 4, !tbaa !9
  %141 = mul nsw i32 %140, 46516320
  store i32 %141, ptr %13, align 4, !tbaa !9
  %142 = load ptr, ptr %9, align 8, !tbaa !5
  %143 = load i32, ptr %13, align 4, !tbaa !9
  %144 = load ptr, ptr %9, align 8, !tbaa !5
  %145 = load ptr, ptr %6, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %145, i32 0, i32 6
  %147 = load i32, ptr %146, align 4, !tbaa !17
  call void @arm_offset_q31(ptr noundef %142, i32 noundef %143, ptr noundef %144, i32 noundef %147)
  %148 = load ptr, ptr %9, align 8, !tbaa !5
  %149 = load ptr, ptr %9, align 8, !tbaa !5
  %150 = load ptr, ptr %6, align 8, !tbaa !5
  %151 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %150, i32 0, i32 6
  %152 = load i32, ptr %151, align 4, !tbaa !17
  call void @arm_shift_q31(ptr noundef %148, i8 noundef signext -19, ptr noundef %149, i32 noundef %152)
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %153

153:                                              ; preds = %173, %131
  %154 = load i32, ptr %16, align 4, !tbaa !9
  %155 = load ptr, ptr %6, align 8, !tbaa !5
  %156 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %155, i32 0, i32 6
  %157 = load i32, ptr %156, align 4, !tbaa !17
  %158 = icmp ult i32 %154, %157
  br i1 %158, label %159, label %176

159:                                              ; preds = %153
  %160 = load ptr, ptr %9, align 8, !tbaa !5
  %161 = load i32, ptr %16, align 4, !tbaa !9
  %162 = zext i32 %161 to i64
  %163 = getelementptr inbounds i32, ptr %160, i64 %162
  %164 = load i32, ptr %163, align 4, !tbaa !9
  %165 = trunc i32 %164 to i16
  %166 = sext i16 %165 to i32
  %167 = call i32 @__SSAT(i32 noundef %166, i32 noundef 16)
  %168 = trunc i32 %167 to i16
  %169 = load ptr, ptr %7, align 8, !tbaa !5
  %170 = load i32, ptr %16, align 4, !tbaa !9
  %171 = zext i32 %170 to i64
  %172 = getelementptr inbounds i16, ptr %169, i64 %171
  store i16 %168, ptr %172, align 2, !tbaa !14
  br label %173

173:                                              ; preds = %159
  %174 = load i32, ptr %16, align 4, !tbaa !9
  %175 = add i32 %174, 1
  store i32 %175, ptr %16, align 4, !tbaa !9
  br label %153, !llvm.loop !25

176:                                              ; preds = %153
  %177 = load ptr, ptr %6, align 8, !tbaa !5
  %178 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %177, i32 0, i32 7
  %179 = load i32, ptr %178, align 8, !tbaa !26
  %180 = trunc i32 %179 to i16
  %181 = getelementptr inbounds %struct.arm_matrix_instance_q15, ptr %15, i32 0, i32 0
  store i16 %180, ptr %181, align 8, !tbaa !27
  %182 = load ptr, ptr %6, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %182, i32 0, i32 6
  %184 = load i32, ptr %183, align 4, !tbaa !17
  %185 = trunc i32 %184 to i16
  %186 = getelementptr inbounds %struct.arm_matrix_instance_q15, ptr %15, i32 0, i32 1
  store i16 %185, ptr %186, align 2, !tbaa !29
  %187 = load ptr, ptr %6, align 8, !tbaa !5
  %188 = getelementptr inbounds %struct.arm_mfcc_instance_q15, ptr %187, i32 0, i32 0
  %189 = load ptr, ptr %188, align 8, !tbaa !30
  %190 = getelementptr inbounds %struct.arm_matrix_instance_q15, ptr %15, i32 0, i32 2
  store ptr %189, ptr %190, align 8, !tbaa !31
  %191 = load ptr, ptr %7, align 8, !tbaa !5
  %192 = load ptr, ptr %8, align 8, !tbaa !5
  call void @arm_mat_vec_mult_q15(ptr noundef %15, ptr noundef %191, ptr noundef %192)
  %193 = load i32, ptr %20, align 4, !tbaa !9
  store i32 %193, ptr %5, align 4
  store i32 1, ptr %23, align 4
  br label %194

194:                                              ; preds = %176, %48
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #4
  %195 = load i32, ptr %5, align 4
  ret i32 %195
}

declare void @arm_absmax_q15(ptr noundef, i32 noundef, ptr noundef, ptr noundef) #2

declare i32 @arm_divide_q15(i16 noundef signext, i16 noundef signext, ptr noundef, ptr noundef) #2

declare void @arm_scale_q15(ptr noundef, i16 noundef signext, i8 noundef signext, ptr noundef, i32 noundef) #2

declare void @arm_mult_q15(ptr noundef, ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @arm_rfft_q15(ptr noundef, ptr noundef, ptr noundef) #3

declare void @arm_cmplx_mag_q15(ptr noundef, ptr noundef, i32 noundef) #2

declare void @arm_dot_prod_q15(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

declare void @arm_mat_vec_mult_q15(ptr noundef, ptr noundef, ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 44, !10, i64 48, !13, i64 56}
!13 = !{!"", !10, i64 0, !7, i64 4, !7, i64 5, !10, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!14 = !{!15, !15, i64 0}
!15 = !{!"short", !7, i64 0}
!16 = !{!12, !6, i64 16}
!17 = !{!12, !10, i64 44}
!18 = !{!12, !6, i64 24}
!19 = !{!12, !6, i64 8}
!20 = !{!12, !6, i64 32}
!21 = !{!22, !22, i64 0}
!22 = !{!"long", !7, i64 0}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}
!25 = distinct !{!25, !24}
!26 = !{!12, !10, i64 48}
!27 = !{!28, !15, i64 0}
!28 = !{!"", !15, i64 0, !15, i64 2, !6, i64 8}
!29 = !{!28, !15, i64 2}
!30 = !{!12, !6, i64 0}
!31 = !{!28, !6, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.arm_matrix_instance_q15 = type { i16, i16, ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SSAT(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) local_unnamed_addr #1

declare void @arm_vlog_q31(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_offset_q31(ptr noundef, i32 noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_shift_q31(ptr noundef, i8 noundef signext, ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_mfcc_q15(ptr noundef %0, ptr noundef %1, ptr noundef %2, ptr noundef %3) local_unnamed_addr #3 {
  %5 = alloca i16, align 2
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  %8 = alloca %struct.arm_matrix_instance_q15, align 8
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %7) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %8) #4
  %11 = getelementptr inbounds i8, ptr %0, i64 40
  %12 = load i32, ptr %11, align 8, !tbaa !5
  call void @arm_absmax_q15(ptr noundef %1, i32 noundef %12, ptr noundef nonnull %5, ptr noundef nonnull %6) #4
  %13 = load i16, ptr %5, align 2, !tbaa !12
  %.not = icmp eq i16 %13, 0
  br i1 %.not, label %21, label %14

14:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %9) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %10) #4
  %15 = call i32 @arm_divide_q15(i16 noundef signext 32767, i16 noundef signext %13, ptr noundef nonnull %9, ptr noundef nonnull %10) #4
  %.not67 = icmp eq i32 %15, 0
  br i1 %.not67, label %16, label %.critedge

16:                                               ; preds = %14
  %17 = load i16, ptr %9, align 2, !tbaa !12
  %18 = load i16, ptr %10, align 2, !tbaa !12
  %19 = trunc i16 %18 to i8
  %20 = load i32, ptr %11, align 8, !tbaa !5
  call void @arm_scale_q15(ptr noundef %1, i16 noundef signext %17, i8 noundef signext %19, ptr noundef %1, i32 noundef %20) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %9) #4
  br label %21

21:                                               ; preds = %16, %4
  %22 = getelementptr inbounds i8, ptr %0, i64 16
  %23 = load ptr, ptr %22, align 8, !tbaa !14
  %24 = load i32, ptr %11, align 8, !tbaa !5
  call void @arm_mult_q15(ptr noundef %1, ptr noundef %23, ptr noundef %1, i32 noundef %24) #4
  %25 = load i32, ptr %11, align 8, !tbaa !5
  %26 = call zeroext i8 @__CLZ(i32 noundef %25)
  %27 = zext i8 %26 to i32
  %28 = getelementptr inbounds i8, ptr %0, i64 56
  call void @arm_rfft_q15(ptr noundef nonnull %28, ptr noundef %1, ptr noundef %3)
  %29 = load i32, ptr %11, align 8, !tbaa !5
  %30 = lshr i32 %29, 1
  %31 = add nuw i32 %30, 1
  call void @arm_cmplx_mag_q15(ptr noundef %3, ptr noundef %1, i32 noundef %31) #4
  %32 = getelementptr inbounds i8, ptr %0, i64 44
  %33 = load i32, ptr %32, align 4, !tbaa !15
  %.not77 = icmp eq i32 %33, 0
  br i1 %.not77, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %21
  %34 = getelementptr inbounds i8, ptr %0, i64 24
  %35 = getelementptr inbounds i8, ptr %0, i64 8
  %36 = getelementptr inbounds i8, ptr %0, i64 32
  br label %37

37:                                               ; preds = %.lr.ph, %37
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %37 ]
  %.06371 = phi i32 [ 0, %.lr.ph ], [ %52, %37 ]
  %38 = load ptr, ptr %34, align 8, !tbaa !16
  %39 = getelementptr inbounds i32, ptr %38, i64 %indvars.iv
  %40 = load i32, ptr %39, align 4, !tbaa !17
  %41 = zext i32 %40 to i64
  %42 = getelementptr inbounds i16, ptr %1, i64 %41
  %43 = load ptr, ptr %35, align 8, !tbaa !18
  %44 = zext i32 %.06371 to i64
  %45 = getelementptr inbounds i16, ptr %43, i64 %44
  %46 = load ptr, ptr %36, align 8, !tbaa !19
  %47 = getelementptr inbounds i32, ptr %46, i64 %indvars.iv
  %48 = load i32, ptr %47, align 4, !tbaa !17
  call void @arm_dot_prod_q15(ptr noundef %42, ptr noundef %45, i32 noundef %48, ptr noundef nonnull %7) #4
  %49 = load ptr, ptr %36, align 8, !tbaa !19
  %50 = getelementptr inbounds i32, ptr %49, i64 %indvars.iv
  %51 = load i32, ptr %50, align 4, !tbaa !17
  %52 = add i32 %51, %.06371
  %53 = load i64, ptr %7, align 8, !tbaa !20
  %54 = add nsw i64 %53, 537
  %55 = ashr i64 %54, 10
  store i64 %55, ptr %7, align 8, !tbaa !20
  %56 = trunc i64 %55 to i32
  %57 = call i32 @__SSAT(i32 noundef %56, i32 noundef 31)
  %58 = getelementptr inbounds i32, ptr %3, i64 %indvars.iv
  store i32 %57, ptr %58, align 4, !tbaa !17
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %59 = load i32, ptr %32, align 4, !tbaa !15
  %60 = zext i32 %59 to i64
  %61 = icmp ult i64 %indvars.iv.next, %60
  br i1 %61, label %37, label %._crit_edge, !llvm.loop !22

._crit_edge:                                      ; preds = %37, %21
  %.lcssa68 = phi i32 [ 0, %21 ], [ %59, %37 ]
  call void @arm_vlog_q31(ptr noundef %3, ptr noundef %3, i32 noundef %.lcssa68) #4
  %62 = sub nsw i32 43, %27
  %63 = mul nsw i32 %62, 46516320
  %64 = load i32, ptr %32, align 4, !tbaa !15
  call void @arm_offset_q31(ptr noundef %3, i32 noundef %63, ptr noundef %3, i32 noundef %64) #4
  %65 = load i32, ptr %32, align 4, !tbaa !15
  call void @arm_shift_q31(ptr noundef %3, i8 noundef signext -19, ptr noundef %3, i32 noundef %65) #4
  %66 = load i32, ptr %32, align 4, !tbaa !15
  %.not78 = icmp eq i32 %66, 0
  br i1 %.not78, label %._crit_edge75, label %.lr.ph74

.lr.ph74:                                         ; preds = %._crit_edge, %.lr.ph74
  %indvars.iv82 = phi i64 [ %indvars.iv.next83, %.lr.ph74 ], [ 0, %._crit_edge ]
  %67 = getelementptr inbounds i32, ptr %3, i64 %indvars.iv82
  %68 = load i32, ptr %67, align 4, !tbaa !17
  %sext = shl i32 %68, 16
  %69 = ashr exact i32 %sext, 16
  %70 = call i32 @__SSAT(i32 noundef %69, i32 noundef 16)
  %71 = trunc i32 %70 to i16
  %72 = getelementptr inbounds i16, ptr %1, i64 %indvars.iv82
  store i16 %71, ptr %72, align 2, !tbaa !12
  %indvars.iv.next83 = add nuw nsw i64 %indvars.iv82, 1
  %73 = load i32, ptr %32, align 4, !tbaa !15
  %74 = zext i32 %73 to i64
  %75 = icmp ult i64 %indvars.iv.next83, %74
  br i1 %75, label %.lr.ph74, label %._crit_edge75.loopexit, !llvm.loop !24

._crit_edge75.loopexit:                           ; preds = %.lr.ph74
  %76 = trunc i32 %73 to i16
  br label %._crit_edge75

._crit_edge75:                                    ; preds = %._crit_edge75.loopexit, %._crit_edge
  %.lcssa = phi i16 [ 0, %._crit_edge ], [ %76, %._crit_edge75.loopexit ]
  %77 = getelementptr inbounds i8, ptr %0, i64 48
  %78 = load i32, ptr %77, align 8, !tbaa !25
  %79 = trunc i32 %78 to i16
  store i16 %79, ptr %8, align 8, !tbaa !26
  %80 = getelementptr inbounds i8, ptr %8, i64 2
  store i16 %.lcssa, ptr %80, align 2, !tbaa !28
  %81 = load ptr, ptr %0, align 8, !tbaa !29
  %82 = getelementptr inbounds i8, ptr %8, i64 8
  store ptr %81, ptr %82, align 8, !tbaa !30
  call void @arm_mat_vec_mult_q15(ptr noundef nonnull %8, ptr noundef %1, ptr noundef %2) #4
  br label %83

.critedge:                                        ; preds = %14
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %9) #4
  br label %83

83:                                               ; preds = %.critedge, %._crit_edge75
  %.1 = phi i32 [ 0, %._crit_edge75 ], [ %15, %.critedge ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %5) #4
  ret i32 %.1
}

declare void @arm_absmax_q15(ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

declare i32 @arm_divide_q15(i16 noundef signext, i16 noundef signext, ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @arm_scale_q15(ptr noundef, i16 noundef signext, i8 noundef signext, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_mult_q15(ptr noundef, ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local void @arm_rfft_q15(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #3

declare void @arm_cmplx_mag_q15(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @arm_dot_prod_q15(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

declare void @arm_mat_vec_mult_q15(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 40}
!6 = !{!"", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !10, i64 40, !10, i64 44, !10, i64 48, !11, i64 56}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"", !10, i64 0, !8, i64 4, !8, i64 5, !10, i64 8, !7, i64 16, !7, i64 24, !7, i64 32}
!12 = !{!13, !13, i64 0}
!13 = !{!"short", !8, i64 0}
!14 = !{!6, !7, i64 16}
!15 = !{!6, !10, i64 44}
!16 = !{!6, !7, i64 24}
!17 = !{!10, !10, i64 0}
!18 = !{!6, !7, i64 8}
!19 = !{!6, !7, i64 32}
!20 = !{!21, !21, i64 0}
!21 = !{!"long", !8, i64 0}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}
!24 = distinct !{!24, !23}
!25 = !{!6, !10, i64 48}
!26 = !{!27, !13, i64 0}
!27 = !{!"", !13, i64 0, !13, i64 2, !7, i64 8}
!28 = !{!27, !13, i64 2}
!29 = !{!6, !7, i64 0}
!30 = !{!27, !7, i64 8}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass