; LLVM IR from tangjz/acm-icpc :: leetcode/extra/LCP 81-与非的谜题.ll (Z7segInitiiRSt6vectorIiSaIiEE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Node = type { [2 x i32] }

@seg = external dso_local global [20003 x %struct.Node], align 16

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z7segInitiiRSt6vectorIiSaIiEE(i32 noundef %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %11 = load i32, ptr %4, align 4, !tbaa !5
  %12 = load i32, ptr %5, align 4, !tbaa !5
  %13 = call noundef i32 @_Z6segIdxii(i32 noundef %11, i32 noundef %12)
  store i32 %13, ptr %7, align 4, !tbaa !5
  %14 = load i32, ptr %4, align 4, !tbaa !5
  %15 = load i32, ptr %5, align 4, !tbaa !5
  %16 = icmp eq i32 %14, %15
  br i1 %16, label %17, label %26

17:                                               ; preds = %3
  %18 = load i32, ptr %7, align 4, !tbaa !5
  %19 = sext i32 %18 to i64
  %20 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %19
  %21 = load ptr, ptr %6, align 8, !tbaa !9
  %22 = load i32, ptr %4, align 4, !tbaa !5
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #4
  %25 = load i32, ptr %24, align 4, !tbaa !5
  call void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8) %20, i32 noundef %25)
  br label %49

26:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %27 = load i32, ptr %4, align 4, !tbaa !5
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = add nsw i32 %27, %28
  %30 = ashr i32 %29, 1
  store i32 %30, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %31 = load i32, ptr %4, align 4, !tbaa !5
  %32 = load i32, ptr %8, align 4, !tbaa !5
  %33 = load ptr, ptr %6, align 8, !tbaa !9
  %34 = call noundef i32 @_Z7segInitiiRSt6vectorIiSaIiEE(i32 noundef %31, i32 noundef %32, ptr noundef nonnull align 8 dereferenceable(24) %33)
  store i32 %34, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  %35 = load i32, ptr %8, align 4, !tbaa !5
  %36 = add nsw i32 %35, 1
  %37 = load i32, ptr %5, align 4, !tbaa !5
  %38 = load ptr, ptr %6, align 8, !tbaa !9
  %39 = call noundef i32 @_Z7segInitiiRSt6vectorIiSaIiEE(i32 noundef %36, i32 noundef %37, ptr noundef nonnull align 8 dereferenceable(24) %38)
  store i32 %39, ptr %10, align 4, !tbaa !5
  %40 = load i32, ptr %7, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %41
  %43 = load i32, ptr %9, align 4, !tbaa !5
  %44 = sext i32 %43 to i64
  %45 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %44
  %46 = load i32, ptr %10, align 4, !tbaa !5
  %47 = sext i32 %46 to i64
  %48 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %47
  call void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8) %42, ptr noundef nonnull align 4 dereferenceable(8) %45, ptr noundef nonnull align 4 dereferenceable(8) %48)
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %49

49:                                               ; preds = %26, %17
  %50 = load i32, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  ret i32 %50
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z6segIdxii(i32 noundef, i32 noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8)) #3 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Node = type { [2 x i32] }

@seg = external dso_local global [20003 x %struct.Node], align 16

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z7segInitiiRSt6vectorIiSaIiEE(i32 noundef %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #0 {
  %4 = tail call noundef i32 @_Z6segIdxii(i32 noundef %0, i32 noundef %1)
  %5 = icmp eq i32 %0, %1
  br i1 %5, label %common.ret, label %11

common.ret:                                       ; preds = %3
  %6 = sext i32 %4 to i64
  %7 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %6
  %8 = sext i32 %0 to i64
  %9 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %8) #2
  %10 = load i32, ptr %9, align 4, !tbaa !5
  tail call void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8) %7, i32 noundef %10)
  br label %common.ret19

common.ret19:                                     ; preds = %11, %common.ret
  ret i32 %4

11:                                               ; preds = %3
  %12 = add nsw i32 %1, %0
  %13 = ashr i32 %12, 1
  %14 = tail call noundef i32 @_Z7segInitiiRSt6vectorIiSaIiEE(i32 noundef %0, i32 noundef %13, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %15 = add nsw i32 %13, 1
  %16 = tail call noundef i32 @_Z7segInitiiRSt6vectorIiSaIiEE(i32 noundef %15, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %17 = sext i32 %4 to i64
  %18 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %17
  %19 = sext i32 %14 to i64
  %20 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %19
  %21 = sext i32 %16 to i64
  %22 = getelementptr inbounds [20003 x %struct.Node], ptr @seg, i64 0, i64 %21
  tail call void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8) %18, ptr noundef nonnull align 4 dereferenceable(8) %20, ptr noundef nonnull align 4 dereferenceable(8) %22)
  br label %common.ret19
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z6segIdxii(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node4initEi(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node5mergeERS_S0_(ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: GlobalOptPass,InferFunctionAttrsPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass