; LLVM IR from CRAFT-THU/BSim :: src/neuron/lif/LIFENeuron.ll (ZN10LIFENeuronC2Effffffffff)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.LIFENeuron = type { %class.NeuronBase.base, float, float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>

@_ZTV10LIFENeuron = external dso_local unnamed_addr constant { [19 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN10LIFENeuronC2Effffffffff(ptr noundef nonnull align 8 dereferenceable(144) %0, float noundef %1, float noundef %2, float noundef %3, float noundef %4, float noundef %5, float noundef %6, float noundef %7, float noundef %8, float noundef %9, float noundef %10) unnamed_addr #0 align 2 {
  %12 = alloca ptr, align 8
  %13 = alloca float, align 4
  %14 = alloca float, align 4
  %15 = alloca float, align 4
  %16 = alloca float, align 4
  %17 = alloca float, align 4
  %18 = alloca float, align 4
  %19 = alloca float, align 4
  %20 = alloca float, align 4
  %21 = alloca float, align 4
  %22 = alloca float, align 4
  store ptr %0, ptr %12, align 8, !tbaa !5
  store float %1, ptr %13, align 4, !tbaa !9
  store float %2, ptr %14, align 4, !tbaa !9
  store float %3, ptr %15, align 4, !tbaa !9
  store float %4, ptr %16, align 4, !tbaa !9
  store float %5, ptr %17, align 4, !tbaa !9
  store float %6, ptr %18, align 4, !tbaa !9
  store float %7, ptr %19, align 4, !tbaa !9
  store float %8, ptr %20, align 4, !tbaa !9
  store float %9, ptr %21, align 4, !tbaa !9
  store float %10, ptr %22, align 4, !tbaa !9
  %23 = load ptr, ptr %12, align 8
  call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %23, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 136) ({ [19 x ptr] }, ptr @_ZTV10LIFENeuron, i32 0, i32 0, i32 2), ptr %23, align 8, !tbaa !11
  %24 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 9
  %25 = load float, ptr %21, align 4, !tbaa !9
  store float %25, ptr %24, align 4, !tbaa !13
  %26 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 10
  %27 = load float, ptr %15, align 4, !tbaa !9
  store float %27, ptr %26, align 8, !tbaa !23
  %28 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 14
  %29 = load float, ptr %13, align 4, !tbaa !9
  store float %29, ptr %28, align 8, !tbaa !24
  %30 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 15
  %31 = load float, ptr %14, align 4, !tbaa !9
  store float %31, ptr %30, align 4, !tbaa !25
  %32 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 16
  %33 = load float, ptr %16, align 4, !tbaa !9
  store float %33, ptr %32, align 8, !tbaa !26
  %34 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 17
  %35 = load float, ptr %17, align 4, !tbaa !9
  store float %35, ptr %34, align 4, !tbaa !27
  %36 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 18
  %37 = load float, ptr %18, align 4, !tbaa !9
  store float %37, ptr %36, align 8, !tbaa !28
  %38 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 19
  %39 = load float, ptr %19, align 4, !tbaa !9
  store float %39, ptr %38, align 4, !tbaa !29
  %40 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 20
  %41 = load float, ptr %20, align 4, !tbaa !9
  store float %41, ptr %40, align 8, !tbaa !30
  %42 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 21
  %43 = load float, ptr %22, align 4, !tbaa !9
  store float %43, ptr %42, align 4, !tbaa !31
  %44 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 22
  store float 0.000000e+00, ptr %44, align 8, !tbaa !32
  %45 = getelementptr inbounds %class.LIFENeuron, ptr %23, i32 0, i32 23
  store float 0.000000e+00, ptr %45, align 4, !tbaa !33
  %46 = getelementptr inbounds %class.NeuronBase, ptr %23, i32 0, i32 3
  store i8 0, ptr %46, align 1, !tbaa !34
  ret void
}

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"float", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"vtable pointer", !8, i64 0}
!13 = !{!14, !10, i64 84}
!14 = !{!"_ZTS10LIFENeuron", !15, i64 0, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !17, i64 96, !17, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !10, i64 120, !10, i64 124, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140}
!15 = !{!"_ZTS10NeuronBase", !16, i64 0, !18, i64 16, !22, i64 40, !22, i64 41, !17, i64 44, !10, i64 48}
!16 = !{!"_ZTS4Base", !17, i64 8, !17, i64 12}
!17 = !{!"int", !7, i64 0}
!18 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"bool", !7, i64 0}
!23 = !{!14, !10, i64 88}
!24 = !{!14, !10, i64 104}
!25 = !{!14, !10, i64 108}
!26 = !{!14, !10, i64 112}
!27 = !{!14, !10, i64 116}
!28 = !{!14, !10, i64 120}
!29 = !{!14, !10, i64 124}
!30 = !{!14, !10, i64 128}
!31 = !{!14, !10, i64 132}
!32 = !{!14, !10, i64 136}
!33 = !{!14, !10, i64 140}
!34 = !{!15, !22, i64 41}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV10LIFENeuron = external dso_local unnamed_addr constant { [19 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN10LIFENeuronC2Effffffffff(ptr noundef nonnull align 8 dereferenceable(144) %0, float noundef %1, float noundef %2, float noundef %3, float noundef %4, float noundef %5, float noundef %6, float noundef %7, float noundef %8, float noundef %9, float noundef %10) unnamed_addr #0 align 2 {
  tail call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %0, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 136) (i8, ptr @_ZTV10LIFENeuron, i64 16), ptr %0, align 8, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %0, i64 84
  store float %9, ptr %12, align 4, !tbaa !8
  %13 = getelementptr inbounds i8, ptr %0, i64 88
  store float %3, ptr %13, align 8, !tbaa !21
  %14 = getelementptr inbounds i8, ptr %0, i64 104
  store float %1, ptr %14, align 8, !tbaa !22
  %15 = getelementptr inbounds i8, ptr %0, i64 108
  store float %2, ptr %15, align 4, !tbaa !23
  %16 = getelementptr inbounds i8, ptr %0, i64 112
  store float %4, ptr %16, align 8, !tbaa !24
  %17 = getelementptr inbounds i8, ptr %0, i64 116
  store float %5, ptr %17, align 4, !tbaa !25
  %18 = getelementptr inbounds i8, ptr %0, i64 120
  store float %6, ptr %18, align 8, !tbaa !26
  %19 = getelementptr inbounds i8, ptr %0, i64 124
  store float %7, ptr %19, align 4, !tbaa !27
  %20 = getelementptr inbounds i8, ptr %0, i64 128
  store float %8, ptr %20, align 8, !tbaa !28
  %21 = getelementptr inbounds i8, ptr %0, i64 132
  store float %10, ptr %21, align 4, !tbaa !29
  %22 = getelementptr inbounds i8, ptr %0, i64 136
  store <2 x float> zeroinitializer, ptr %22, align 8, !tbaa !30
  %23 = getelementptr inbounds i8, ptr %0, i64 41
  store i8 0, ptr %23, align 1, !tbaa !31
  ret void
}

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !20, i64 84}
!9 = !{!"_ZTS10LIFENeuron", !10, i64 0, !20, i64 52, !20, i64 56, !20, i64 60, !20, i64 64, !20, i64 68, !20, i64 72, !20, i64 76, !20, i64 80, !20, i64 84, !20, i64 88, !20, i64 92, !12, i64 96, !12, i64 100, !20, i64 104, !20, i64 108, !20, i64 112, !20, i64 116, !20, i64 120, !20, i64 124, !20, i64 128, !20, i64 132, !20, i64 136, !20, i64 140}
!10 = !{!"_ZTS10NeuronBase", !11, i64 0, !14, i64 16, !19, i64 40, !19, i64 41, !12, i64 44, !20, i64 48}
!11 = !{!"_ZTS4Base", !12, i64 8, !12, i64 12}
!12 = !{!"int", !13, i64 0}
!13 = !{!"omnipotent char", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!18 = !{!"any pointer", !13, i64 0}
!19 = !{!"bool", !13, i64 0}
!20 = !{!"float", !13, i64 0}
!21 = !{!9, !20, i64 88}
!22 = !{!9, !20, i64 104}
!23 = !{!9, !20, i64 108}
!24 = !{!9, !20, i64 112}
!25 = !{!9, !20, i64 116}
!26 = !{!9, !20, i64 120}
!27 = !{!9, !20, i64 124}
!28 = !{!9, !20, i64 128}
!29 = !{!9, !20, i64 132}
!30 = !{!20, !20, i64 0}
!31 = !{!10, !19, i64 41}


; Effective O3 passes: InstCombinePass,SLPVectorizerPass,SROAPass,TailCallElimPass