; LLVM IR from CRAFT-THU/BSim :: src/neuron/max/MaxNeuron.ll (ZN9MaxNeuronC2Ei)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.NeuronBase = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float, [4 x i8] }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.MaxNeuron = type <{ %class.NeuronBase.base, [4 x i8], ptr, i32, i32, i32, [4 x i8] }>
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>

@_ZTV9MaxNeuron = external dso_local unnamed_addr constant { [19 x ptr] }, align 8
@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [77 x i8], align 1
@__PRETTY_FUNCTION__._ZN9MaxNeuronC2Ei = external hidden unnamed_addr constant [26 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [22 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9MaxNeuronC2Ei(ptr noundef nonnull align 8 dereferenceable(76) %0, i32 noundef %1) unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %5 = load ptr, ptr %3, align 8
  call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %5, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 136) ({ [19 x ptr] }, ptr @_ZTV9MaxNeuron, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !11
  %6 = getelementptr inbounds %class.NeuronBase, ptr %5, i32 0, i32 2
  store i8 0, ptr %6, align 8, !tbaa !13
  %7 = getelementptr inbounds %class.NeuronBase, ptr %5, i32 0, i32 3
  store i8 0, ptr %7, align 1, !tbaa !22
  %8 = load i32, ptr %4, align 4, !tbaa !9
  %9 = icmp slt i32 %8, 32
  br i1 %9, label %10, label %13

10:                                               ; preds = %2
  %11 = load i32, ptr %4, align 4, !tbaa !9
  %12 = icmp sge i32 %11, 0
  br label %13

13:                                               ; preds = %10, %2
  %14 = phi i1 [ false, %2 ], [ %12, %10 ]
  br i1 %14, label %15, label %16

15:                                               ; preds = %13
  br label %18

16:                                               ; preds = %13
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 20, ptr noundef @__PRETTY_FUNCTION__._ZN9MaxNeuronC2Ei) #5
  unreachable

17:                                               ; No predecessors!
  br label %18

18:                                               ; preds = %17, %15
  %19 = load i32, ptr %4, align 4, !tbaa !9
  %20 = getelementptr inbounds %class.MaxNeuron, ptr %5, i32 0, i32 5
  store i32 %19, ptr %20, align 8, !tbaa !23
  %21 = getelementptr inbounds %class.MaxNeuron, ptr %5, i32 0, i32 3
  store i32 0, ptr %21, align 8, !tbaa !25
  %22 = getelementptr inbounds %class.MaxNeuron, ptr %5, i32 0, i32 4
  store i32 0, ptr %22, align 4, !tbaa !26
  %23 = load i32, ptr %4, align 4, !tbaa !9
  %24 = sext i32 %23 to i64
  %25 = mul i64 4, %24
  %26 = call noalias ptr @malloc(i64 noundef %25) #6
  %27 = getelementptr inbounds %class.MaxNeuron, ptr %5, i32 0, i32 2
  store ptr %26, ptr %27, align 8, !tbaa !27
  %28 = getelementptr inbounds %class.MaxNeuron, ptr %5, i32 0, i32 2
  %29 = load ptr, ptr %28, align 8, !tbaa !27
  %30 = icmp ne ptr %29, null
  br i1 %30, label %31, label %32

31:                                               ; preds = %18
  br label %34

32:                                               ; preds = %18
  call void @__assert_fail(ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 25, ptr noundef @__PRETTY_FUNCTION__._ZN9MaxNeuronC2Ei) #5
  unreachable

33:                                               ; No predecessors!
  br label %34

34:                                               ; preds = %33, %31
  %35 = getelementptr inbounds %class.MaxNeuron, ptr %5, i32 0, i32 2
  %36 = load ptr, ptr %35, align 8, !tbaa !27
  %37 = load i32, ptr %4, align 4, !tbaa !9
  %38 = sext i32 %37 to i64
  %39 = mul i64 4, %38
  call void @llvm.memset.p0.i64(ptr align 4 %36, i8 0, i64 %39, i1 false)
  ret void
}

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: nounwind allocsize(0)
declare noalias ptr @malloc(i64 noundef) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #5 = { noreturn nounwind }
attributes #6 = { nounwind allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"vtable pointer", !8, i64 0}
!13 = !{!14, !20, i64 40}
!14 = !{!"_ZTS10NeuronBase", !15, i64 0, !16, i64 16, !20, i64 40, !20, i64 41, !10, i64 44, !21, i64 48}
!15 = !{!"_ZTS4Base", !10, i64 8, !10, i64 12}
!16 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"float", !7, i64 0}
!22 = !{!14, !20, i64 41}
!23 = !{!24, !10, i64 72}
!24 = !{!"_ZTS9MaxNeuron", !14, i64 0, !6, i64 56, !10, i64 64, !10, i64 68, !10, i64 72}
!25 = !{!24, !10, i64 64}
!26 = !{!24, !10, i64 68}
!27 = !{!24, !6, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV9MaxNeuron = external dso_local unnamed_addr constant { [19 x ptr] }, align 8
@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [77 x i8], align 1
@__PRETTY_FUNCTION__._ZN9MaxNeuronC2Ei = external hidden unnamed_addr constant [26 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [22 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9MaxNeuronC2Ei(ptr noundef nonnull align 8 dereferenceable(76) %0, i32 noundef %1) unnamed_addr #0 align 2 {
  tail call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %0, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 136) (i8, ptr @_ZTV9MaxNeuron, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 40
  store i8 0, ptr %3, align 8, !tbaa !8
  %4 = getelementptr inbounds i8, ptr %0, i64 41
  store i8 0, ptr %4, align 1, !tbaa !20
  %5 = icmp ult i32 %1, 32
  br i1 %5, label %7, label %6

6:                                                ; preds = %2
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 20, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN9MaxNeuronC2Ei) #4
  unreachable

7:                                                ; preds = %2
  %8 = getelementptr inbounds i8, ptr %0, i64 72
  store i32 %1, ptr %8, align 8, !tbaa !21
  %9 = getelementptr inbounds i8, ptr %0, i64 64
  store i32 0, ptr %9, align 8, !tbaa !23
  %10 = getelementptr inbounds i8, ptr %0, i64 68
  store i32 0, ptr %10, align 4, !tbaa !24
  %11 = shl nuw nsw i32 %1, 2
  %12 = zext nneg i32 %11 to i64
  %calloc = tail call ptr @calloc(i64 1, i64 %12)
  %13 = getelementptr inbounds i8, ptr %0, i64 56
  store ptr %calloc, ptr %13, align 8, !tbaa !25
  %.not = icmp eq ptr %calloc, null
  br i1 %.not, label %14, label %15

14:                                               ; preds = %7
  tail call void @__assert_fail(ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 25, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN9MaxNeuronC2Ei) #4
  unreachable

15:                                               ; preds = %7
  ret void
}

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nofree nounwind willreturn allockind("alloc,zeroed") allocsize(0,1) memory(inaccessiblemem: readwrite)
declare noalias noundef ptr @calloc(i64 noundef, i64 noundef) local_unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nofree nounwind willreturn allockind("alloc,zeroed") allocsize(0,1) memory(inaccessiblemem: readwrite) "alloc-family"="malloc" }
attributes #4 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !18, i64 40}
!9 = !{!"_ZTS10NeuronBase", !10, i64 0, !13, i64 16, !18, i64 40, !18, i64 41, !11, i64 44, !19, i64 48}
!10 = !{!"_ZTS4Base", !11, i64 8, !11, i64 12}
!11 = !{!"int", !12, i64 0}
!12 = !{!"omnipotent char", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!17 = !{!"any pointer", !12, i64 0}
!18 = !{!"bool", !12, i64 0}
!19 = !{!"float", !12, i64 0}
!20 = !{!9, !18, i64 41}
!21 = !{!22, !11, i64 72}
!22 = !{!"_ZTS9MaxNeuron", !9, i64 0, !17, i64 56, !11, i64 64, !11, i64 68, !11, i64 72}
!23 = !{!22, !11, i64 64}
!24 = !{!22, !11, i64 68}
!25 = !{!22, !17, i64 56}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass