; LLVM IR from CRAFT-THU/BSim :: src/neuron/tj/TJNeuron.ll (ZN8TJNeuronC2ERKS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.TJNeuron = type { %class.NeuronBase.base, float, float, float, float, float, float, float, float, float, float, i32, i32, ptr }
%class.NeuronBase.base = type <{ %class.Base, %"class.std::vector", i8, i8, [2 x i8], i32, float }>
%class.Base = type { ptr, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl" = type { %"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SynapseBase *, std::allocator<SynapseBase *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTV8TJNeuron = external dso_local unnamed_addr constant { [21 x ptr] }, align 8

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN8TJNeuronC2ERKS_(ptr noundef nonnull align 8 dereferenceable(112) %0, ptr noundef nonnull align 8 dereferenceable(112) %1) unnamed_addr #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %5, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 152) ({ [21 x ptr] }, ptr @_ZTV8TJNeuron, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !9
  %6 = load ptr, ptr %4, align 8, !tbaa !5
  %7 = getelementptr inbounds %class.TJNeuron, ptr %6, i32 0, i32 1
  %8 = load float, ptr %7, align 4, !tbaa !11
  %9 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 1
  store float %8, ptr %9, align 4, !tbaa !11
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = getelementptr inbounds %class.TJNeuron, ptr %10, i32 0, i32 3
  %12 = load float, ptr %11, align 4, !tbaa !22
  %13 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 3
  store float %12, ptr %13, align 4, !tbaa !22
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %class.TJNeuron, ptr %14, i32 0, i32 4
  %16 = load float, ptr %15, align 8, !tbaa !23
  %17 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 4
  store float %16, ptr %17, align 8, !tbaa !23
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %class.TJNeuron, ptr %18, i32 0, i32 5
  %20 = load float, ptr %19, align 4, !tbaa !24
  %21 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 5
  store float %20, ptr %21, align 4, !tbaa !24
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = getelementptr inbounds %class.TJNeuron, ptr %22, i32 0, i32 6
  %24 = load float, ptr %23, align 8, !tbaa !25
  %25 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 6
  store float %24, ptr %25, align 8, !tbaa !25
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %class.TJNeuron, ptr %26, i32 0, i32 7
  %28 = load float, ptr %27, align 4, !tbaa !26
  %29 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 7
  store float %28, ptr %29, align 4, !tbaa !26
  %30 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 8
  store float 0.000000e+00, ptr %30, align 8, !tbaa !27
  %31 = getelementptr inbounds %class.TJNeuron, ptr %5, i32 0, i32 13
  store ptr null, ptr %31, align 8, !tbaa !28
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !21, i64 52}
!12 = !{!"_ZTS8TJNeuron", !13, i64 0, !21, i64 52, !21, i64 56, !21, i64 60, !21, i64 64, !21, i64 68, !21, i64 72, !21, i64 76, !21, i64 80, !21, i64 84, !21, i64 88, !15, i64 92, !15, i64 96, !6, i64 104}
!13 = !{!"_ZTS10NeuronBase", !14, i64 0, !16, i64 16, !20, i64 40, !20, i64 41, !15, i64 44, !21, i64 48}
!14 = !{!"_ZTS4Base", !15, i64 8, !15, i64 12}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"float", !7, i64 0}
!22 = !{!12, !21, i64 60}
!23 = !{!12, !21, i64 64}
!24 = !{!12, !21, i64 68}
!25 = !{!12, !21, i64 72}
!26 = !{!12, !21, i64 76}
!27 = !{!12, !21, i64 80}
!28 = !{!12, !6, i64 104}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV8TJNeuron = external dso_local unnamed_addr constant { [21 x ptr] }, align 8

declare void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN8TJNeuronC2ERKS_(ptr noundef nonnull align 8 dereferenceable(112) %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(112) %1) unnamed_addr #1 align 2 {
  tail call void @_ZN10NeuronBaseC2Ei(ptr noundef nonnull align 8 dereferenceable(52) %0, i32 noundef 0)
  store ptr getelementptr inbounds inrange(-16, 152) (i8, ptr @_ZTV8TJNeuron, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %1, i64 52
  %4 = load float, ptr %3, align 4, !tbaa !8
  %5 = getelementptr inbounds i8, ptr %0, i64 52
  store float %4, ptr %5, align 4, !tbaa !8
  %6 = getelementptr inbounds i8, ptr %1, i64 60
  %7 = getelementptr inbounds i8, ptr %0, i64 60
  %8 = load <4 x float>, ptr %6, align 4, !tbaa !21
  store <4 x float> %8, ptr %7, align 4, !tbaa !21
  %9 = getelementptr inbounds i8, ptr %1, i64 76
  %10 = load float, ptr %9, align 4, !tbaa !22
  %11 = getelementptr inbounds i8, ptr %0, i64 76
  store float %10, ptr %11, align 4, !tbaa !22
  %12 = getelementptr inbounds i8, ptr %0, i64 80
  store float 0.000000e+00, ptr %12, align 8, !tbaa !23
  %13 = getelementptr inbounds i8, ptr %0, i64 104
  store ptr null, ptr %13, align 8, !tbaa !24
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !20, i64 52}
!9 = !{!"_ZTS8TJNeuron", !10, i64 0, !20, i64 52, !20, i64 56, !20, i64 60, !20, i64 64, !20, i64 68, !20, i64 72, !20, i64 76, !20, i64 80, !20, i64 84, !20, i64 88, !12, i64 92, !12, i64 96, !18, i64 104}
!10 = !{!"_ZTS10NeuronBase", !11, i64 0, !14, i64 16, !19, i64 40, !19, i64 41, !12, i64 44, !20, i64 48}
!11 = !{!"_ZTS4Base", !12, i64 8, !12, i64 12}
!12 = !{!"int", !13, i64 0}
!13 = !{!"omnipotent char", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIP11SynapseBaseSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIP11SynapseBaseSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP11SynapseBaseSaIS1_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!18 = !{!"any pointer", !13, i64 0}
!19 = !{!"bool", !13, i64 0}
!20 = !{!"float", !13, i64 0}
!21 = !{!20, !20, i64 0}
!22 = !{!9, !20, i64 76}
!23 = !{!9, !20, i64 80}
!24 = !{!9, !18, i64 104}


; Effective O3 passes: InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,TailCallElimPass