; LLVM IR from tangjz/acm-icpc :: codeforces/gym (101194J)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@N = external dso_local global i32, align 4
@M = external dso_local global i32, align 4
@S = external dso_local global i32, align 4
@T = external dso_local global i32, align 4
@flow = external dso_local global i32, align 4
@cost = external dso_local global i32, align 4
@lnk = external dso_local global [1803 x i32], align 16
@.str = external hidden unnamed_addr constant [3 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [5 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [22 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [14 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiiii(i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z11BellmanFordv() #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #4 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca [1803 x i8], align 16
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #7
  call void @llvm.lifetime.start.p0(i64 1803, ptr %6) #7
  %22 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef %2)
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #7
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %23

23:                                               ; preds = %205, %0
  %24 = load i32, ptr %7, align 4, !tbaa !5
  %25 = load i32, ptr %2, align 4, !tbaa !5
  %26 = icmp sle i32 %24, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %23
  store i32 2, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #7
  br label %208

28:                                               ; preds = %23
  %29 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str.1, ptr noundef %3, ptr noundef %4)
  %30 = load i32, ptr %3, align 4, !tbaa !5
  %31 = load i32, ptr %4, align 4, !tbaa !5
  %32 = mul nsw i32 %30, %31
  %33 = mul nsw i32 %32, 2
  %34 = add nsw i32 %33, 2
  store i32 %34, ptr @N, align 4, !tbaa !5
  %35 = load i32, ptr @N, align 4, !tbaa !5
  %36 = sub nsw i32 %35, 2
  store i32 %36, ptr @S, align 4, !tbaa !5
  %37 = load i32, ptr @N, align 4, !tbaa !5
  %38 = sub nsw i32 %37, 1
  store i32 %38, ptr @T, align 4, !tbaa !5
  store i32 0, ptr @cost, align 4, !tbaa !5
  store i32 0, ptr @flow, align 4, !tbaa !5
  store i32 0, ptr @M, align 4, !tbaa !5
  %39 = load i32, ptr @N, align 4, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = mul i64 %40, 4
  call void @llvm.memset.p0.i64(ptr align 16 @lnk, i8 -1, i64 %41, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #7
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %42

42:                                               ; preds = %82, %28
  %43 = load i32, ptr %9, align 4, !tbaa !5
  %44 = load i32, ptr %3, align 4, !tbaa !5
  %45 = icmp slt i32 %43, %44
  br i1 %45, label %47, label %46

46:                                               ; preds = %42
  store i32 5, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #7
  br label %85

47:                                               ; preds = %42
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #7
  store i32 0, ptr %10, align 4, !tbaa !5
  br label %48

48:                                               ; preds = %78, %47
  %49 = load i32, ptr %10, align 4, !tbaa !5
  %50 = add nsw i32 %49, 1
  %51 = load i32, ptr %4, align 4, !tbaa !5
  %52 = icmp slt i32 %50, %51
  br i1 %52, label %54, label %53

53:                                               ; preds = %48
  store i32 8, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #7
  br label %81

54:                                               ; preds = %48
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #7
  %55 = load i32, ptr %9, align 4, !tbaa !5
  %56 = load i32, ptr %4, align 4, !tbaa !5
  %57 = mul nsw i32 %55, %56
  %58 = load i32, ptr %10, align 4, !tbaa !5
  %59 = add nsw i32 %57, %58
  store i32 %59, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #7
  %60 = load i32, ptr %11, align 4, !tbaa !5
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #7
  %62 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef %13)
  %63 = load i32, ptr %9, align 4, !tbaa !5
  %64 = and i32 %63, 1
  %65 = load i32, ptr %10, align 4, !tbaa !5
  %66 = and i32 %65, 1
  %67 = icmp ne i32 %64, %66
  br i1 %67, label %68, label %69

68:                                               ; preds = %54
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %11, ptr noundef nonnull align 4 dereferenceable(4) %12) #7
  br label %69

69:                                               ; preds = %68, %54
  %70 = load i32, ptr %11, align 4, !tbaa !5
  %71 = shl i32 %70, 1
  %72 = or i32 %71, 0
  %73 = load i32, ptr %12, align 4, !tbaa !5
  %74 = shl i32 %73, 1
  %75 = or i32 %74, 1
  %76 = load i32, ptr %13, align 4, !tbaa !5
  %77 = sub nsw i32 0, %76
  call void @_Z7addEdgeiiii(i32 noundef %72, i32 noundef %75, i32 noundef 1, i32 noundef %77)
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #7
  br label %78

78:                                               ; preds = %69
  %79 = load i32, ptr %10, align 4, !tbaa !5
  %80 = add nsw i32 %79, 1
  store i32 %80, ptr %10, align 4, !tbaa !5
  br label %48, !llvm.loop !9

81:                                               ; preds = %53
  br label %82

82:                                               ; preds = %81
  %83 = load i32, ptr %9, align 4, !tbaa !5
  %84 = add nsw i32 %83, 1
  store i32 %84, ptr %9, align 4, !tbaa !5
  br label %42, !llvm.loop !11

85:                                               ; preds = %46
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #7
  store i32 0, ptr %14, align 4, !tbaa !5
  br label %86

86:                                               ; preds = %127, %85
  %87 = load i32, ptr %14, align 4, !tbaa !5
  %88 = add nsw i32 %87, 1
  %89 = load i32, ptr %3, align 4, !tbaa !5
  %90 = icmp slt i32 %88, %89
  br i1 %90, label %92, label %91

91:                                               ; preds = %86
  store i32 11, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #7
  br label %130

92:                                               ; preds = %86
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #7
  store i32 0, ptr %15, align 4, !tbaa !5
  br label %93

93:                                               ; preds = %123, %92
  %94 = load i32, ptr %15, align 4, !tbaa !5
  %95 = load i32, ptr %4, align 4, !tbaa !5
  %96 = icmp slt i32 %94, %95
  br i1 %96, label %98, label %97

97:                                               ; preds = %93
  store i32 14, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #7
  br label %126

98:                                               ; preds = %93
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #7
  %99 = load i32, ptr %14, align 4, !tbaa !5
  %100 = load i32, ptr %4, align 4, !tbaa !5
  %101 = mul nsw i32 %99, %100
  %102 = load i32, ptr %15, align 4, !tbaa !5
  %103 = add nsw i32 %101, %102
  store i32 %103, ptr %16, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #7
  %104 = load i32, ptr %16, align 4, !tbaa !5
  %105 = load i32, ptr %4, align 4, !tbaa !5
  %106 = add nsw i32 %104, %105
  store i32 %106, ptr %17, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #7
  %107 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef %18)
  %108 = load i32, ptr %14, align 4, !tbaa !5
  %109 = and i32 %108, 1
  %110 = load i32, ptr %15, align 4, !tbaa !5
  %111 = and i32 %110, 1
  %112 = icmp eq i32 %109, %111
  br i1 %112, label %113, label %114

113:                                              ; preds = %98
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %16, ptr noundef nonnull align 4 dereferenceable(4) %17) #7
  br label %114

114:                                              ; preds = %113, %98
  %115 = load i32, ptr %16, align 4, !tbaa !5
  %116 = shl i32 %115, 1
  %117 = or i32 %116, 0
  %118 = load i32, ptr %17, align 4, !tbaa !5
  %119 = shl i32 %118, 1
  %120 = or i32 %119, 1
  %121 = load i32, ptr %18, align 4, !tbaa !5
  %122 = sub nsw i32 0, %121
  call void @_Z7addEdgeiiii(i32 noundef %117, i32 noundef %120, i32 noundef 1, i32 noundef %122)
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #7
  br label %123

123:                                              ; preds = %114
  %124 = load i32, ptr %15, align 4, !tbaa !5
  %125 = add nsw i32 %124, 1
  store i32 %125, ptr %15, align 4, !tbaa !5
  br label %93, !llvm.loop !12

126:                                              ; preds = %97
  br label %127

127:                                              ; preds = %126
  %128 = load i32, ptr %14, align 4, !tbaa !5
  %129 = add nsw i32 %128, 1
  store i32 %129, ptr %14, align 4, !tbaa !5
  br label %86, !llvm.loop !13

130:                                              ; preds = %91
  %131 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef %5)
  %132 = getelementptr inbounds [1803 x i8], ptr %6, i64 0, i64 0
  %133 = load i32, ptr %3, align 4, !tbaa !5
  %134 = load i32, ptr %4, align 4, !tbaa !5
  %135 = mul nsw i32 %133, %134
  %136 = sext i32 %135 to i64
  %137 = mul i64 %136, 1
  call void @llvm.memset.p0.i64(ptr align 16 %132, i8 0, i64 %137, i1 false)
  br label %138

138:                                              ; preds = %142, %130
  %139 = load i32, ptr %5, align 4, !tbaa !5
  %140 = add nsw i32 %139, -1
  store i32 %140, ptr %5, align 4, !tbaa !5
  %141 = icmp ne i32 %139, 0
  br i1 %141, label %142, label %153

142:                                              ; preds = %138
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #7
  %143 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str.1, ptr noundef %19, ptr noundef %20)
  %144 = load i32, ptr %19, align 4, !tbaa !5
  %145 = add nsw i32 %144, -1
  store i32 %145, ptr %19, align 4, !tbaa !5
  %146 = load i32, ptr %4, align 4, !tbaa !5
  %147 = mul nsw i32 %145, %146
  %148 = load i32, ptr %20, align 4, !tbaa !5
  %149 = add nsw i32 %148, -1
  store i32 %149, ptr %20, align 4, !tbaa !5
  %150 = add nsw i32 %147, %149
  %151 = sext i32 %150 to i64
  %152 = getelementptr inbounds [1803 x i8], ptr %6, i64 0, i64 %151
  store i8 1, ptr %152, align 1, !tbaa !14
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #7
  br label %138, !llvm.loop !16

153:                                              ; preds = %138
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #7
  store i32 0, ptr %21, align 4, !tbaa !5
  br label %154

154:                                              ; preds = %183, %153
  %155 = load i32, ptr %21, align 4, !tbaa !5
  %156 = load i32, ptr %3, align 4, !tbaa !5
  %157 = load i32, ptr %4, align 4, !tbaa !5
  %158 = mul nsw i32 %156, %157
  %159 = icmp slt i32 %155, %158
  br i1 %159, label %161, label %160

160:                                              ; preds = %154
  store i32 19, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #7
  br label %186

161:                                              ; preds = %154
  %162 = load i32, ptr @S, align 4, !tbaa !5
  %163 = load i32, ptr %21, align 4, !tbaa !5
  %164 = shl i32 %163, 1
  %165 = or i32 %164, 0
  call void @_Z7addEdgeiiii(i32 noundef %162, i32 noundef %165, i32 noundef 1, i32 noundef 0)
  %166 = load i32, ptr %21, align 4, !tbaa !5
  %167 = shl i32 %166, 1
  %168 = or i32 %167, 1
  %169 = load i32, ptr @T, align 4, !tbaa !5
  call void @_Z7addEdgeiiii(i32 noundef %168, i32 noundef %169, i32 noundef 1, i32 noundef 0)
  %170 = load i32, ptr %21, align 4, !tbaa !5
  %171 = sext i32 %170 to i64
  %172 = getelementptr inbounds [1803 x i8], ptr %6, i64 0, i64 %171
  %173 = load i8, ptr %172, align 1, !tbaa !14, !range !17, !noundef !18
  %174 = trunc i8 %173 to i1
  br i1 %174, label %182, label %175

175:                                              ; preds = %161
  %176 = load i32, ptr %21, align 4, !tbaa !5
  %177 = shl i32 %176, 1
  %178 = or i32 %177, 0
  %179 = load i32, ptr %21, align 4, !tbaa !5
  %180 = shl i32 %179, 1
  %181 = or i32 %180, 1
  call void @_Z7addEdgeiiii(i32 noundef %178, i32 noundef %181, i32 noundef 1, i32 noundef 0)
  br label %182

182:                                              ; preds = %175, %161
  br label %183

183:                                              ; preds = %182
  %184 = load i32, ptr %21, align 4, !tbaa !5
  %185 = add nsw i32 %184, 1
  store i32 %185, ptr %21, align 4, !tbaa !5
  br label %154, !llvm.loop !19

186:                                              ; preds = %160
  br label %187

187:                                              ; preds = %189, %186
  %188 = call noundef zeroext i1 @_Z11BellmanFordv()
  br i1 %188, label %189, label %190

189:                                              ; preds = %187
  br label %187, !llvm.loop !20

190:                                              ; preds = %187
  %191 = load i32, ptr @flow, align 4, !tbaa !5
  %192 = load i32, ptr %3, align 4, !tbaa !5
  %193 = load i32, ptr %4, align 4, !tbaa !5
  %194 = mul nsw i32 %192, %193
  %195 = icmp slt i32 %191, %194
  br i1 %195, label %196, label %199

196:                                              ; preds = %190
  %197 = load i32, ptr %7, align 4, !tbaa !5
  %198 = call i32 (ptr, ...) @printf(ptr noundef @.str.2, i32 noundef %197)
  br label %204

199:                                              ; preds = %190
  %200 = load i32, ptr %7, align 4, !tbaa !5
  %201 = load i32, ptr @cost, align 4, !tbaa !5
  %202 = sub nsw i32 0, %201
  %203 = call i32 (ptr, ...) @printf(ptr noundef @.str.3, i32 noundef %200, i32 noundef %202)
  br label %204

204:                                              ; preds = %199, %196
  br label %205

205:                                              ; preds = %204
  %206 = load i32, ptr %7, align 4, !tbaa !5
  %207 = add nsw i32 %206, 1
  store i32 %207, ptr %7, align 4, !tbaa !5
  br label %23, !llvm.loop !21

208:                                              ; preds = %27
  store i32 0, ptr %1, align 4
  store i32 1, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 1803, ptr %6) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #7
  %209 = load i32, ptr %1, align 4
  ret i32 %209
}

declare i32 @__isoc99_scanf(ptr noundef, ...) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #6

declare i32 @printf(ptr noundef, ...) #5

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = !{!15, !15, i64 0}
!15 = !{!"bool", !7, i64 0}
!16 = distinct !{!16, !10}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = distinct !{!19, !10}
!20 = distinct !{!20, !10}
!21 = distinct !{!21, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@N = external dso_local local_unnamed_addr global i32, align 4
@M = external dso_local local_unnamed_addr global i32, align 4
@S = external dso_local local_unnamed_addr global i32, align 4
@T = external dso_local local_unnamed_addr global i32, align 4
@flow = external dso_local local_unnamed_addr global i32, align 4
@cost = external dso_local local_unnamed_addr global i32, align 4
@lnk = external dso_local local_unnamed_addr global [1803 x i32], align 16
@.str = external hidden unnamed_addr constant [3 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [5 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [22 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [14 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiiii(i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z11BellmanFordv() local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() local_unnamed_addr #4 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca [1803 x i8], align 16
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #7
  call void @llvm.lifetime.start.p0(i64 1803, ptr nonnull %5) #7
  %14 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %1)
  %15 = load i32, ptr %1, align 4, !tbaa !5
  %.not52 = icmp slt i32 %15, 1
  br i1 %.not52, label %._crit_edge56, label %.lr.ph55

._crit_edge56:                                    ; preds = %137, %0
  call void @llvm.lifetime.end.p0(i64 1803, ptr nonnull %5) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1) #7
  ret i32 0

.lr.ph55:                                         ; preds = %0, %137
  %.03253 = phi i32 [ %138, %137 ], [ 1, %0 ]
  %16 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str.1, ptr noundef nonnull %2, ptr noundef nonnull %3)
  %17 = load i32, ptr %2, align 4, !tbaa !5
  %18 = load i32, ptr %3, align 4, !tbaa !5
  %19 = shl i32 %17, 1
  %20 = mul i32 %19, %18
  %21 = add nsw i32 %20, 2
  store i32 %21, ptr @N, align 4, !tbaa !5
  store i32 %20, ptr @S, align 4, !tbaa !5
  %22 = or disjoint i32 %20, 1
  store i32 %22, ptr @T, align 4, !tbaa !5
  store i32 0, ptr @cost, align 4, !tbaa !5
  store i32 0, ptr @flow, align 4, !tbaa !5
  store i32 0, ptr @M, align 4, !tbaa !5
  %23 = sext i32 %21 to i64
  %24 = shl nsw i64 %23, 2
  call void @llvm.memset.p0.i64(ptr nonnull align 16 @lnk, i8 -1, i64 %24, i1 false)
  %25 = icmp sgt i32 %17, 0
  br i1 %25, label %.preheader37.lr.ph, label %._crit_edge46

.preheader37.lr.ph:                               ; preds = %.lr.ph55
  %26 = icmp sgt i32 %18, 1
  br i1 %26, label %.preheader37, label %.preheader40

.preheader40:                                     ; preds = %._crit_edge, %.preheader37.lr.ph
  %27 = phi i32 [ %18, %.preheader37.lr.ph ], [ %35, %._crit_edge ]
  %28 = phi i32 [ %17, %.preheader37.lr.ph ], [ %34, %._crit_edge ]
  %29 = icmp sgt i32 %28, 1
  %30 = icmp sgt i32 %27, 0
  %or.cond = select i1 %29, i1 %30, i1 false
  br i1 %or.cond, label %.preheader, label %._crit_edge46

.preheader37:                                     ; preds = %.preheader37.lr.ph, %._crit_edge
  %31 = phi i32 [ %34, %._crit_edge ], [ %17, %.preheader37.lr.ph ]
  %32 = phi i32 [ %35, %._crit_edge ], [ %18, %.preheader37.lr.ph ]
  %.03142 = phi i32 [ %36, %._crit_edge ], [ 0, %.preheader37.lr.ph ]
  %33 = icmp sgt i32 %32, 1
  br i1 %33, label %.lr.ph, label %._crit_edge

._crit_edge.loopexit:                             ; preds = %47
  %.pre = load i32, ptr %2, align 4, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.preheader37
  %34 = phi i32 [ %.pre, %._crit_edge.loopexit ], [ %31, %.preheader37 ]
  %35 = phi i32 [ %56, %._crit_edge.loopexit ], [ %32, %.preheader37 ]
  %36 = add nuw nsw i32 %.03142, 1
  %37 = icmp slt i32 %36, %34
  br i1 %37, label %.preheader37, label %.preheader40, !llvm.loop !9

.lr.ph:                                           ; preds = %.preheader37, %47
  %38 = phi i32 [ %56, %47 ], [ %32, %.preheader37 ]
  %39 = phi i32 [ %55, %47 ], [ 1, %.preheader37 ]
  %.03041 = phi i32 [ %39, %47 ], [ 0, %.preheader37 ]
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #7
  %40 = mul nsw i32 %38, %.03142
  %41 = add nsw i32 %40, %.03041
  store i32 %41, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #7
  %42 = add nsw i32 %41, 1
  store i32 %42, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %8) #7
  %43 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %8)
  %44 = xor i32 %.03041, %.03142
  %45 = and i32 %44, 1
  %.not36 = icmp eq i32 %45, 0
  br i1 %.not36, label %47, label %46

46:                                               ; preds = %.lr.ph
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %6, ptr noundef nonnull align 4 dereferenceable(4) %7) #7
  br label %47

47:                                               ; preds = %46, %.lr.ph
  %48 = load i32, ptr %6, align 4, !tbaa !5
  %49 = shl i32 %48, 1
  %50 = load i32, ptr %7, align 4, !tbaa !5
  %51 = shl i32 %50, 1
  %52 = or disjoint i32 %51, 1
  %53 = load i32, ptr %8, align 4, !tbaa !5
  %54 = sub nsw i32 0, %53
  call void @_Z7addEdgeiiii(i32 noundef %49, i32 noundef %52, i32 noundef 1, i32 noundef %54)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %8) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #7
  %55 = add nuw nsw i32 %39, 1
  %56 = load i32, ptr %3, align 4, !tbaa !5
  %57 = icmp slt i32 %55, %56
  br i1 %57, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !12

.loopexit.loopexit:                               ; preds = %82
  %.pre60 = load i32, ptr %2, align 4, !tbaa !5
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.loopexit, %.preheader
  %58 = phi i32 [ %.pre60, %.loopexit.loopexit ], [ %62, %.preheader ]
  %59 = phi i32 [ %91, %.loopexit.loopexit ], [ %63, %.preheader ]
  %60 = add nuw nsw i32 %64, 1
  %61 = icmp slt i32 %60, %58
  br i1 %61, label %.preheader, label %._crit_edge46, !llvm.loop !13

.preheader:                                       ; preds = %.preheader40, %.loopexit
  %62 = phi i32 [ %58, %.loopexit ], [ %28, %.preheader40 ]
  %63 = phi i32 [ %59, %.loopexit ], [ %27, %.preheader40 ]
  %64 = phi i32 [ %60, %.loopexit ], [ 1, %.preheader40 ]
  %.02945 = phi i32 [ %64, %.loopexit ], [ 0, %.preheader40 ]
  %65 = icmp sgt i32 %63, 0
  br i1 %65, label %.lr.ph44, label %.loopexit

._crit_edge46:                                    ; preds = %.loopexit, %.lr.ph55, %.preheader40
  %66 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %4)
  %67 = load i32, ptr %2, align 4, !tbaa !5
  %68 = load i32, ptr %3, align 4, !tbaa !5
  %69 = mul nsw i32 %68, %67
  %70 = sext i32 %69 to i64
  call void @llvm.memset.p0.i64(ptr nonnull align 16 %5, i8 0, i64 %70, i1 false)
  %71 = load i32, ptr %4, align 4, !tbaa !5
  %72 = add nsw i32 %71, -1
  store i32 %72, ptr %4, align 4, !tbaa !5
  %.not3547 = icmp eq i32 %71, 0
  br i1 %.not3547, label %.preheader39, label %.lr.ph49

.lr.ph44:                                         ; preds = %.preheader, %82
  %73 = phi i32 [ %91, %82 ], [ %63, %.preheader ]
  %.02843 = phi i32 [ %90, %82 ], [ 0, %.preheader ]
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %9) #7
  %74 = mul nsw i32 %73, %.02945
  %75 = add nsw i32 %74, %.02843
  store i32 %75, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %10) #7
  %76 = add nsw i32 %75, %73
  store i32 %76, ptr %10, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %11) #7
  %77 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %11)
  %78 = xor i32 %.02843, %.02945
  %79 = and i32 %78, 1
  %80 = icmp eq i32 %79, 0
  br i1 %80, label %81, label %82

81:                                               ; preds = %.lr.ph44
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %9, ptr noundef nonnull align 4 dereferenceable(4) %10) #7
  br label %82

82:                                               ; preds = %81, %.lr.ph44
  %83 = load i32, ptr %9, align 4, !tbaa !5
  %84 = shl i32 %83, 1
  %85 = load i32, ptr %10, align 4, !tbaa !5
  %86 = shl i32 %85, 1
  %87 = or disjoint i32 %86, 1
  %88 = load i32, ptr %11, align 4, !tbaa !5
  %89 = sub nsw i32 0, %88
  call void @_Z7addEdgeiiii(i32 noundef %84, i32 noundef %87, i32 noundef 1, i32 noundef %89)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %11) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %10) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %9) #7
  %90 = add nuw nsw i32 %.02843, 1
  %91 = load i32, ptr %3, align 4, !tbaa !5
  %92 = icmp slt i32 %90, %91
  br i1 %92, label %.lr.ph44, label %.loopexit.loopexit, !llvm.loop !14

.preheader39.loopexit:                            ; preds = %.lr.ph49
  %.pre61 = load i32, ptr %2, align 4, !tbaa !5
  %.pre62 = mul nsw i32 %97, %.pre61
  br label %.preheader39

.preheader39:                                     ; preds = %.preheader39.loopexit, %._crit_edge46
  %.pre-phi = phi i32 [ %.pre62, %.preheader39.loopexit ], [ %69, %._crit_edge46 ]
  %93 = icmp sgt i32 %.pre-phi, 0
  br i1 %93, label %.lr.ph51, label %.preheader38.preheader

.lr.ph49:                                         ; preds = %._crit_edge46, %.lr.ph49
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %12) #7
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %13) #7
  %94 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str.1, ptr noundef nonnull %12, ptr noundef nonnull %13)
  %95 = load i32, ptr %12, align 4, !tbaa !5
  %96 = add nsw i32 %95, -1
  %97 = load i32, ptr %3, align 4, !tbaa !5
  %98 = mul nsw i32 %97, %96
  %99 = load i32, ptr %13, align 4, !tbaa !5
  %100 = add nsw i32 %99, -1
  %101 = add nsw i32 %100, %98
  %102 = sext i32 %101 to i64
  %103 = getelementptr inbounds [1803 x i8], ptr %5, i64 0, i64 %102
  store i8 1, ptr %103, align 1, !tbaa !15
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %13) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %12) #7
  %104 = load i32, ptr %4, align 4, !tbaa !5
  %105 = add nsw i32 %104, -1
  store i32 %105, ptr %4, align 4, !tbaa !5
  %.not35 = icmp eq i32 %104, 0
  br i1 %.not35, label %.preheader39.loopexit, label %.lr.ph49, !llvm.loop !17

.lr.ph51:                                         ; preds = %.preheader39, %118
  %indvars.iv = phi i64 [ %indvars.iv.next, %118 ], [ 0, %.preheader39 ]
  %106 = load i32, ptr @S, align 4, !tbaa !5
  %107 = shl nuw i64 %indvars.iv, 1
  %108 = trunc nuw i64 %107 to i32
  call void @_Z7addEdgeiiii(i32 noundef %106, i32 noundef %108, i32 noundef 1, i32 noundef 0)
  %109 = load i32, ptr @T, align 4, !tbaa !5
  %110 = trunc i64 %107 to i32
  %111 = or disjoint i32 %110, 1
  call void @_Z7addEdgeiiii(i32 noundef %111, i32 noundef %109, i32 noundef 1, i32 noundef 0)
  %112 = getelementptr inbounds [1803 x i8], ptr %5, i64 0, i64 %indvars.iv
  %113 = load i8, ptr %112, align 1, !tbaa !15, !range !18, !noundef !19
  %114 = trunc nuw i8 %113 to i1
  br i1 %114, label %118, label %115

115:                                              ; preds = %.lr.ph51
  %indvars59 = trunc i64 %indvars.iv to i32
  %116 = shl nuw i32 %indvars59, 1
  %117 = or disjoint i32 %116, 1
  call void @_Z7addEdgeiiii(i32 noundef %108, i32 noundef %117, i32 noundef 1, i32 noundef 0)
  br label %118

118:                                              ; preds = %.lr.ph51, %115
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %119 = load i32, ptr %2, align 4, !tbaa !5
  %120 = load i32, ptr %3, align 4, !tbaa !5
  %121 = mul nsw i32 %120, %119
  %122 = sext i32 %121 to i64
  %123 = icmp slt i64 %indvars.iv.next, %122
  br i1 %123, label %.lr.ph51, label %.preheader38.preheader, !llvm.loop !20

.preheader38.preheader:                           ; preds = %118, %.preheader39
  br label %.preheader38

.preheader38:                                     ; preds = %.preheader38.preheader, %.preheader38
  %124 = call noundef zeroext i1 @_Z11BellmanFordv()
  br i1 %124, label %.preheader38, label %125, !llvm.loop !21

125:                                              ; preds = %.preheader38
  %126 = load i32, ptr @flow, align 4, !tbaa !5
  %127 = load i32, ptr %2, align 4, !tbaa !5
  %128 = load i32, ptr %3, align 4, !tbaa !5
  %129 = mul nsw i32 %128, %127
  %130 = icmp slt i32 %126, %129
  br i1 %130, label %131, label %133

131:                                              ; preds = %125
  %132 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.2, i32 noundef %.03253)
  br label %137

133:                                              ; preds = %125
  %134 = load i32, ptr @cost, align 4, !tbaa !5
  %135 = sub nsw i32 0, %134
  %136 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.3, i32 noundef %.03253, i32 noundef %135)
  br label %137

137:                                              ; preds = %131, %133
  %138 = add nuw nsw i32 %.03253, 1
  %139 = load i32, ptr %1, align 4, !tbaa !5
  %.not.not = icmp slt i32 %.03253, %139
  br i1 %.not.not, label %.lr.ph55, label %._crit_edge56, !llvm.loop !22
}

; Function Attrs: nofree nounwind
declare noundef i32 @__isoc99_scanf(ptr nocapture noundef readonly, ...) local_unnamed_addr #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #6

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #5

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10, !11}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!"llvm.loop.unswitch.partial.disable"}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10, !11}
!14 = distinct !{!14, !10}
!15 = !{!16, !16, i64 0}
!16 = !{!"bool", !7, i64 0}
!17 = distinct !{!17, !10}
!18 = !{i8 0, i8 2}
!19 = !{}
!20 = distinct !{!20, !10}
!21 = distinct !{!21, !10}
!22 = distinct !{!22, !10}


; Effective O3 passes: BDCEPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass