; LLVM IR from CRAFT-THU/BSim :: src/net/BuildNetworks.ll (ZN12MultiNetwork13buildNetworksEb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.MultiNetwork = type <{ %"class.std::vector", %"class.std::vector", %"class.std::vector.2", %"class.std::vector.7", %"class.std::vector.7", ptr, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::set<NeuronBase *>, std::allocator<std::set<NeuronBase *>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::set<NeuronBase *>, std::allocator<std::set<NeuronBase *>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::set<NeuronBase *>, std::allocator<std::set<NeuronBase *>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::set<NeuronBase *>, std::allocator<std::set<NeuronBase *>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.2" = type { %"struct.std::_Vector_base.3" }
%"struct.std::_Vector_base.3" = type { %"struct.std::_Vector_base<std::map<NeuronBase *, int>, std::allocator<std::map<NeuronBase *, int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::map<NeuronBase *, int>, std::allocator<std::map<NeuronBase *, int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::map<NeuronBase *, int>, std::allocator<std::map<NeuronBase *, int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::map<NeuronBase *, int>, std::allocator<std::map<NeuronBase *, int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.7" = type { %"struct.std::_Vector_base.8" }
%"struct.std::_Vector_base.8" = type { %"struct.std::_Vector_base<std::map<Type, int>, std::allocator<std::map<Type, int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::map<Type, int>, std::allocator<std::map<Type, int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::map<Type, int>, std::allocator<std::map<Type, int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::map<Type, int>, std::allocator<std::map<Type, int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.DistriNetwork = type { i32, i32, i32, float, ptr, ptr }
%struct.GNetwork = type { ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, ptr, i32 }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN12MultiNetwork12countTypeNumEv(ptr noundef nonnull align 8 dereferenceable(132)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN12MultiNetwork11arrangeDataEi(ptr noundef nonnull align 8 dereferenceable(132), i32 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(48) ptr @_ZNSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt3mapIP10NeuronBaseiSt4lessIS1_ESaISt4pairIKS1_iEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(48)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN12MultiNetwork14arrangeConnectEiii(ptr noundef nonnull align 8 dereferenceable(132), i32 noundef, i32 noundef, i32 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN12MultiNetwork19arrangeCrossNodeMapEiii(ptr noundef nonnull align 8 dereferenceable(132), i32 noundef, i32 noundef, i32 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN12MultiNetwork13buildNetworksEb(ptr noundef nonnull align 8 dereferenceable(132) %0, i1 noundef zeroext %1) #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  %11 = zext i1 %1 to i8
  store i8 %11, ptr %4, align 1, !tbaa !9
  %12 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %13 = getelementptr inbounds %class.MultiNetwork, ptr %12, i32 0, i32 6
  %14 = load i32, ptr %13, align 8, !tbaa !11
  %15 = call noundef ptr @_Z13initDistriNeti(i32 noundef %14)
  store ptr %15, ptr %5, align 8, !tbaa !5
  %16 = load i8, ptr %4, align 1, !tbaa !9, !range !26, !noundef !27
  %17 = trunc i8 %16 to i1
  br i1 %17, label %18, label %19

18:                                               ; preds = %2
  call void @_ZN12MultiNetwork12splitNetworkEv(ptr noundef nonnull align 8 dereferenceable(132) %12)
  br label %19

19:                                               ; preds = %18, %2
  call void @_ZN12MultiNetwork12countTypeNumEv(ptr noundef nonnull align 8 dereferenceable(132) %12)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  store i32 0, ptr %6, align 4, !tbaa !28
  br label %20

20:                                               ; preds = %91, %19
  %21 = load i32, ptr %6, align 4, !tbaa !28
  %22 = getelementptr inbounds %class.MultiNetwork, ptr %12, i32 0, i32 6
  %23 = load i32, ptr %22, align 8, !tbaa !11
  %24 = icmp slt i32 %21, %23
  br i1 %24, label %26, label %25

25:                                               ; preds = %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  br label %94

26:                                               ; preds = %20
  %27 = load i32, ptr %6, align 4, !tbaa !28
  %28 = call noundef ptr @_ZN12MultiNetwork11arrangeDataEi(ptr noundef nonnull align 8 dereferenceable(132) %12, i32 noundef %27)
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = load i32, ptr %6, align 4, !tbaa !28
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds %struct.DistriNetwork, ptr %29, i64 %31
  %33 = getelementptr inbounds %struct.DistriNetwork, ptr %32, i32 0, i32 4
  store ptr %28, ptr %33, align 8, !tbaa !29
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = load i32, ptr %6, align 4, !tbaa !28
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds %struct.DistriNetwork, ptr %34, i64 %36
  %38 = getelementptr inbounds %struct.DistriNetwork, ptr %37, i32 0, i32 4
  %39 = load ptr, ptr %38, align 8, !tbaa !29
  %40 = getelementptr inbounds %struct.GNetwork, ptr %39, i32 0, i32 3
  %41 = load ptr, ptr %40, align 8, !tbaa !32
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = load i32, ptr %6, align 4, !tbaa !28
  %44 = sext i32 %43 to i64
  %45 = getelementptr inbounds %struct.DistriNetwork, ptr %42, i64 %44
  %46 = getelementptr inbounds %struct.DistriNetwork, ptr %45, i32 0, i32 4
  %47 = load ptr, ptr %46, align 8, !tbaa !29
  %48 = getelementptr inbounds %struct.GNetwork, ptr %47, i32 0, i32 5
  %49 = load i32, ptr %48, align 8, !tbaa !34
  %50 = sext i32 %49 to i64
  %51 = getelementptr inbounds i32, ptr %41, i64 %50
  %52 = load i32, ptr %51, align 4, !tbaa !28
  %53 = sext i32 %52 to i64
  %54 = getelementptr inbounds %class.MultiNetwork, ptr %12, i32 0, i32 2
  %55 = load i32, ptr %6, align 4, !tbaa !28
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 8 dereferenceable(48) ptr @_ZNSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %54, i64 noundef %56) #4
  %58 = call noundef i64 @_ZNKSt3mapIP10NeuronBaseiSt4lessIS1_ESaISt4pairIKS1_iEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(48) %57) #4
  %59 = add i64 %53, %58
  %60 = trunc i64 %59 to i32
  store i32 %60, ptr %7, align 4, !tbaa !28
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = load i32, ptr %6, align 4, !tbaa !28
  %63 = sext i32 %62 to i64
  %64 = getelementptr inbounds %struct.DistriNetwork, ptr %61, i64 %63
  %65 = getelementptr inbounds %struct.DistriNetwork, ptr %64, i32 0, i32 4
  %66 = load ptr, ptr %65, align 8, !tbaa !29
  %67 = getelementptr inbounds %struct.GNetwork, ptr %66, i32 0, i32 4
  %68 = load ptr, ptr %67, align 8, !tbaa !35
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = load i32, ptr %6, align 4, !tbaa !28
  %71 = sext i32 %70 to i64
  %72 = getelementptr inbounds %struct.DistriNetwork, ptr %69, i64 %71
  %73 = getelementptr inbounds %struct.DistriNetwork, ptr %72, i32 0, i32 4
  %74 = load ptr, ptr %73, align 8, !tbaa !29
  %75 = getelementptr inbounds %struct.GNetwork, ptr %74, i32 0, i32 6
  %76 = load i32, ptr %75, align 4, !tbaa !36
  %77 = sext i32 %76 to i64
  %78 = getelementptr inbounds i32, ptr %68, i64 %77
  %79 = load i32, ptr %78, align 4, !tbaa !28
  store i32 %79, ptr %8, align 4, !tbaa !28
  %80 = load i32, ptr %7, align 4, !tbaa !28
  %81 = load i32, ptr %8, align 4, !tbaa !28
  %82 = load i32, ptr %6, align 4, !tbaa !28
  %83 = call noundef ptr @_ZN12MultiNetwork14arrangeConnectEiii(ptr noundef nonnull align 8 dereferenceable(132) %12, i32 noundef %80, i32 noundef %81, i32 noundef %82)
  %84 = load ptr, ptr %5, align 8, !tbaa !5
  %85 = load i32, ptr %6, align 4, !tbaa !28
  %86 = sext i32 %85 to i64
  %87 = getelementptr inbounds %struct.DistriNetwork, ptr %84, i64 %86
  %88 = getelementptr inbounds %struct.DistriNetwork, ptr %87, i32 0, i32 4
  %89 = load ptr, ptr %88, align 8, !tbaa !29
  %90 = getelementptr inbounds %struct.GNetwork, ptr %89, i32 0, i32 2
  store ptr %83, ptr %90, align 8, !tbaa !37
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %91

91:                                               ; preds = %26
  %92 = load i32, ptr %6, align 4, !tbaa !28
  %93 = add nsw i32 %92, 1
  store i32 %93, ptr %6, align 4, !tbaa !28
  br label %20, !llvm.loop !38

94:                                               ; preds = %25
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  store i32 0, ptr %9, align 4, !tbaa !28
  br label %95

95:                                               ; preds = %139, %94
  %96 = load i32, ptr %9, align 4, !tbaa !28
  %97 = getelementptr inbounds %class.MultiNetwork, ptr %12, i32 0, i32 6
  %98 = load i32, ptr %97, align 8, !tbaa !11
  %99 = icmp slt i32 %96, %98
  br i1 %99, label %101, label %100

100:                                              ; preds = %95
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  br label %142

101:                                              ; preds = %95
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  %102 = load ptr, ptr %5, align 8, !tbaa !5
  %103 = load i32, ptr %9, align 4, !tbaa !28
  %104 = sext i32 %103 to i64
  %105 = getelementptr inbounds %struct.DistriNetwork, ptr %102, i64 %104
  %106 = getelementptr inbounds %struct.DistriNetwork, ptr %105, i32 0, i32 4
  %107 = load ptr, ptr %106, align 8, !tbaa !29
  %108 = getelementptr inbounds %struct.GNetwork, ptr %107, i32 0, i32 3
  %109 = load ptr, ptr %108, align 8, !tbaa !32
  %110 = load ptr, ptr %5, align 8, !tbaa !5
  %111 = load i32, ptr %9, align 4, !tbaa !28
  %112 = sext i32 %111 to i64
  %113 = getelementptr inbounds %struct.DistriNetwork, ptr %110, i64 %112
  %114 = getelementptr inbounds %struct.DistriNetwork, ptr %113, i32 0, i32 4
  %115 = load ptr, ptr %114, align 8, !tbaa !29
  %116 = getelementptr inbounds %struct.GNetwork, ptr %115, i32 0, i32 5
  %117 = load i32, ptr %116, align 8, !tbaa !34
  %118 = sext i32 %117 to i64
  %119 = getelementptr inbounds i32, ptr %109, i64 %118
  %120 = load i32, ptr %119, align 4, !tbaa !28
  %121 = sext i32 %120 to i64
  %122 = getelementptr inbounds %class.MultiNetwork, ptr %12, i32 0, i32 2
  %123 = load i32, ptr %9, align 4, !tbaa !28
  %124 = sext i32 %123 to i64
  %125 = call noundef nonnull align 8 dereferenceable(48) ptr @_ZNSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %122, i64 noundef %124) #4
  %126 = call noundef i64 @_ZNKSt3mapIP10NeuronBaseiSt4lessIS1_ESaISt4pairIKS1_iEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(48) %125) #4
  %127 = add i64 %121, %126
  %128 = trunc i64 %127 to i32
  store i32 %128, ptr %10, align 4, !tbaa !28
  %129 = load i32, ptr %10, align 4, !tbaa !28
  %130 = load i32, ptr %9, align 4, !tbaa !28
  %131 = getelementptr inbounds %class.MultiNetwork, ptr %12, i32 0, i32 6
  %132 = load i32, ptr %131, align 8, !tbaa !11
  %133 = call noundef ptr @_ZN12MultiNetwork19arrangeCrossNodeMapEiii(ptr noundef nonnull align 8 dereferenceable(132) %12, i32 noundef %129, i32 noundef %130, i32 noundef %132)
  %134 = load ptr, ptr %5, align 8, !tbaa !5
  %135 = load i32, ptr %9, align 4, !tbaa !28
  %136 = sext i32 %135 to i64
  %137 = getelementptr inbounds %struct.DistriNetwork, ptr %134, i64 %136
  %138 = getelementptr inbounds %struct.DistriNetwork, ptr %137, i32 0, i32 5
  store ptr %133, ptr %138, align 8, !tbaa !40
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  br label %139

139:                                              ; preds = %101
  %140 = load i32, ptr %9, align 4, !tbaa !28
  %141 = add nsw i32 %140, 1
  store i32 %141, ptr %9, align 4, !tbaa !28
  br label %95, !llvm.loop !41

142:                                              ; preds = %100
  %143 = load ptr, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret ptr %143
}

declare noundef ptr @_Z13initDistriNeti(i32 noundef) #3

declare void @_ZN12MultiNetwork12splitNetworkEv(ptr noundef nonnull align 8 dereferenceable(132)) #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !25, i64 128}
!12 = !{!"_ZTS12MultiNetwork", !13, i64 0, !13, i64 24, !17, i64 48, !21, i64 72, !21, i64 96, !6, i64 120, !25, i64 128}
!13 = !{!"_ZTSSt6vectorISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSSt6vectorISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"int", !7, i64 0}
!26 = !{i8 0, i8 2}
!27 = !{}
!28 = !{!25, !25, i64 0}
!29 = !{!30, !6, i64 16}
!30 = !{!"_ZTS13DistriNetwork", !25, i64 0, !25, i64 4, !25, i64 8, !31, i64 12, !6, i64 16, !6, i64 24}
!31 = !{!"float", !7, i64 0}
!32 = !{!33, !6, i64 24}
!33 = !{!"_ZTS8GNetwork", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !25, i64 40, !25, i64 44, !6, i64 48, !6, i64 56, !25, i64 64}
!34 = !{!33, !25, i64 40}
!35 = !{!33, !6, i64 32}
!36 = !{!33, !25, i64 44}
!37 = !{!33, !6, i64 16}
!38 = distinct !{!38, !39}
!39 = !{!"llvm.loop.mustprogress"}
!40 = !{!30, !6, i64 24}
!41 = distinct !{!41, !39}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.DistriNetwork = type { i32, i32, i32, float, ptr, ptr }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN12MultiNetwork12countTypeNumEv(ptr noundef nonnull align 8 dereferenceable(132)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN12MultiNetwork11arrangeDataEi(ptr noundef nonnull align 8 dereferenceable(132), i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(48) ptr @_ZNSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt3mapIP10NeuronBaseiSt4lessIS1_ESaISt4pairIKS1_iEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN12MultiNetwork14arrangeConnectEiii(ptr noundef nonnull align 8 dereferenceable(132), i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN12MultiNetwork19arrangeCrossNodeMapEiii(ptr noundef nonnull align 8 dereferenceable(132), i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN12MultiNetwork13buildNetworksEb(ptr noundef nonnull align 8 dereferenceable(132) %0, i1 noundef zeroext %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 128
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = tail call noundef ptr @_Z13initDistriNeti(i32 noundef %4)
  br i1 %1, label %6, label %7

6:                                                ; preds = %2
  tail call void @_ZN12MultiNetwork12splitNetworkEv(ptr noundef nonnull align 8 dereferenceable(132) %0)
  br label %7

7:                                                ; preds = %6, %2
  tail call void @_ZN12MultiNetwork12countTypeNumEv(ptr noundef nonnull align 8 dereferenceable(132) %0)
  %8 = load i32, ptr %3, align 8, !tbaa !5
  %9 = icmp sgt i32 %8, 0
  br i1 %9, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %7
  %10 = getelementptr inbounds i8, ptr %0, i64 48
  br label %13

.preheader:                                       ; preds = %13
  %11 = icmp sgt i32 %39, 0
  br i1 %11, label %.lr.ph35, label %._crit_edge

.lr.ph35:                                         ; preds = %.preheader
  %12 = getelementptr inbounds i8, ptr %0, i64 48
  br label %42

13:                                               ; preds = %.lr.ph, %13
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %13 ]
  %14 = trunc nuw nsw i64 %indvars.iv to i32
  %15 = tail call noundef ptr @_ZN12MultiNetwork11arrangeDataEi(ptr noundef nonnull align 8 dereferenceable(132) %0, i32 noundef %14)
  %16 = getelementptr inbounds %struct.DistriNetwork, ptr %5, i64 %indvars.iv, i32 4
  store ptr %15, ptr %16, align 8, !tbaa !23
  %17 = getelementptr inbounds i8, ptr %15, i64 24
  %18 = load ptr, ptr %17, align 8, !tbaa !26
  %19 = getelementptr inbounds i8, ptr %15, i64 40
  %20 = load i32, ptr %19, align 8, !tbaa !28
  %21 = sext i32 %20 to i64
  %22 = getelementptr inbounds i32, ptr %18, i64 %21
  %23 = load i32, ptr %22, align 4, !tbaa !29
  %24 = tail call noundef nonnull align 8 dereferenceable(48) ptr @_ZNSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %indvars.iv) #3
  %25 = tail call noundef i64 @_ZNKSt3mapIP10NeuronBaseiSt4lessIS1_ESaISt4pairIKS1_iEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(48) %24) #3
  %26 = trunc i64 %25 to i32
  %27 = add i32 %23, %26
  %28 = load ptr, ptr %16, align 8, !tbaa !23
  %29 = getelementptr inbounds i8, ptr %28, i64 32
  %30 = load ptr, ptr %29, align 8, !tbaa !30
  %31 = getelementptr inbounds i8, ptr %28, i64 44
  %32 = load i32, ptr %31, align 4, !tbaa !31
  %33 = sext i32 %32 to i64
  %34 = getelementptr inbounds i32, ptr %30, i64 %33
  %35 = load i32, ptr %34, align 4, !tbaa !29
  %36 = tail call noundef ptr @_ZN12MultiNetwork14arrangeConnectEiii(ptr noundef nonnull align 8 dereferenceable(132) %0, i32 noundef %27, i32 noundef %35, i32 noundef %14)
  %37 = load ptr, ptr %16, align 8, !tbaa !23
  %38 = getelementptr inbounds i8, ptr %37, i64 16
  store ptr %36, ptr %38, align 8, !tbaa !32
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %39 = load i32, ptr %3, align 8, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = icmp slt i64 %indvars.iv.next, %40
  br i1 %41, label %13, label %.preheader, !llvm.loop !33

._crit_edge:                                      ; preds = %42, %7, %.preheader
  ret ptr %5

42:                                               ; preds = %.lr.ph35, %42
  %indvars.iv37 = phi i64 [ 0, %.lr.ph35 ], [ %indvars.iv.next38, %42 ]
  %43 = getelementptr inbounds %struct.DistriNetwork, ptr %5, i64 %indvars.iv37
  %44 = getelementptr inbounds i8, ptr %43, i64 16
  %45 = load ptr, ptr %44, align 8, !tbaa !23
  %46 = getelementptr inbounds i8, ptr %45, i64 24
  %47 = load ptr, ptr %46, align 8, !tbaa !26
  %48 = getelementptr inbounds i8, ptr %45, i64 40
  %49 = load i32, ptr %48, align 8, !tbaa !28
  %50 = sext i32 %49 to i64
  %51 = getelementptr inbounds i32, ptr %47, i64 %50
  %52 = load i32, ptr %51, align 4, !tbaa !29
  %53 = tail call noundef nonnull align 8 dereferenceable(48) ptr @_ZNSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %indvars.iv37) #3
  %54 = tail call noundef i64 @_ZNKSt3mapIP10NeuronBaseiSt4lessIS1_ESaISt4pairIKS1_iEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(48) %53) #3
  %55 = trunc i64 %54 to i32
  %56 = add i32 %52, %55
  %57 = load i32, ptr %3, align 8, !tbaa !5
  %58 = trunc nuw nsw i64 %indvars.iv37 to i32
  %59 = tail call noundef ptr @_ZN12MultiNetwork19arrangeCrossNodeMapEiii(ptr noundef nonnull align 8 dereferenceable(132) %0, i32 noundef %56, i32 noundef %58, i32 noundef %57)
  %60 = getelementptr inbounds i8, ptr %43, i64 24
  store ptr %59, ptr %60, align 8, !tbaa !35
  %indvars.iv.next38 = add nuw nsw i64 %indvars.iv37, 1
  %61 = load i32, ptr %3, align 8, !tbaa !5
  %62 = sext i32 %61 to i64
  %63 = icmp slt i64 %indvars.iv.next38, %62
  br i1 %63, label %42, label %._crit_edge, !llvm.loop !36
}

declare noundef ptr @_Z13initDistriNeti(i32 noundef) local_unnamed_addr #2

declare void @_ZN12MultiNetwork12splitNetworkEv(ptr noundef nonnull align 8 dereferenceable(132)) local_unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !22, i64 128}
!6 = !{!"_ZTS12MultiNetwork", !7, i64 0, !7, i64 24, !14, i64 48, !18, i64 72, !18, i64 96, !11, i64 120, !22, i64 128}
!7 = !{!"_ZTSSt6vectorISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseISt3setIP10NeuronBaseSt4lessIS2_ESaIS2_EESaIS6_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt6vectorISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseISt3mapIP10NeuronBaseiSt4lessIS2_ESaISt4pairIKS2_iEEESaIS9_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!18 = !{!"_ZTSSt6vectorISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseISt3mapI4TypeiSt4lessIS1_ESaISt4pairIKS1_iEEESaIS8_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!22 = !{!"int", !12, i64 0}
!23 = !{!24, !11, i64 16}
!24 = !{!"_ZTS13DistriNetwork", !22, i64 0, !22, i64 4, !22, i64 8, !25, i64 12, !11, i64 16, !11, i64 24}
!25 = !{!"float", !12, i64 0}
!26 = !{!27, !11, i64 24}
!27 = !{!"_ZTS8GNetwork", !11, i64 0, !11, i64 8, !11, i64 16, !11, i64 24, !11, i64 32, !22, i64 40, !22, i64 44, !11, i64 48, !11, i64 56, !22, i64 64}
!28 = !{!27, !22, i64 40}
!29 = !{!22, !22, i64 0}
!30 = !{!27, !11, i64 32}
!31 = !{!27, !22, i64 44}
!32 = !{!27, !11, i64 16}
!33 = distinct !{!33, !34}
!34 = !{!"llvm.loop.mustprogress"}
!35 = !{!24, !11, i64 24}
!36 = distinct !{!36, !34}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass