; LLVM IR from Izaron/ACM-ICPC :: Timus Online Judge/Volume 3/1214. Strange Procedure.ll (Z1PRlS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_Z1PRlS_(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef nonnull align 8 dereferenceable(8) %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = load i64, ptr %7, align 8, !tbaa !9
  %9 = icmp sgt i64 %8, 0
  br i1 %9, label %10, label %76

10:                                               ; preds = %2
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = load i64, ptr %11, align 8, !tbaa !9
  %13 = icmp sgt i64 %12, 0
  br i1 %13, label %14, label %76

14:                                               ; preds = %10
  store i32 1, ptr %5, align 4, !tbaa !11
  br label %15

15:                                               ; preds = %72, %14
  %16 = load i32, ptr %5, align 4, !tbaa !11
  %17 = sext i32 %16 to i64
  %18 = load ptr, ptr %3, align 8, !tbaa !5
  %19 = load i64, ptr %18, align 8, !tbaa !9
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = load i64, ptr %20, align 8, !tbaa !9
  %22 = add nsw i64 %19, %21
  %23 = icmp sle i64 %17, %22
  br i1 %23, label %24, label %75

24:                                               ; preds = %15
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  %26 = load i64, ptr %25, align 8, !tbaa !9
  %27 = load ptr, ptr %3, align 8, !tbaa !5
  %28 = load i64, ptr %27, align 8, !tbaa !9
  %29 = mul nsw i64 %26, %28
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = load i64, ptr %30, align 8, !tbaa !9
  %32 = add nsw i64 %29, %31
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  store i64 %32, ptr %33, align 8, !tbaa !9
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = load i64, ptr %34, align 8, !tbaa !9
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = load i64, ptr %36, align 8, !tbaa !9
  %38 = mul nsw i64 %35, %37
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = load i64, ptr %39, align 8, !tbaa !9
  %41 = add nsw i64 %38, %40
  %42 = load ptr, ptr %3, align 8, !tbaa !5
  store i64 %41, ptr %42, align 8, !tbaa !9
  %43 = load ptr, ptr %3, align 8, !tbaa !5
  %44 = load i64, ptr %43, align 8, !tbaa !9
  %45 = sitofp i64 %44 to x86_fp80
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = load i64, ptr %46, align 8, !tbaa !9
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  %49 = load i64, ptr %48, align 8, !tbaa !9
  %50 = call i64 @llvm.abs.i64(i64 %49, i1 true)
  %51 = sdiv i64 %47, %50
  %52 = sitofp i64 %51 to x86_fp80
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  %54 = load i64, ptr %53, align 8, !tbaa !9
  %55 = call i64 @llvm.abs.i64(i64 %54, i1 true)
  %56 = sub nsw i64 0, %55
  %57 = sitofp i64 %56 to x86_fp80
  %58 = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 %52, x86_fp80 %57, x86_fp80 %45)
  %59 = call noundef x86_fp80 @_ZSt4sqrte(x86_fp80 noundef %58)
  %60 = fptosi x86_fp80 %59 to i64
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  store i64 %60, ptr %61, align 8, !tbaa !9
  %62 = load ptr, ptr %3, align 8, !tbaa !5
  %63 = load i64, ptr %62, align 8, !tbaa !9
  %64 = load ptr, ptr %4, align 8, !tbaa !5
  %65 = load i64, ptr %64, align 8, !tbaa !9
  %66 = mul nsw i64 2, %65
  %67 = load ptr, ptr %4, align 8, !tbaa !5
  %68 = load i64, ptr %67, align 8, !tbaa !9
  %69 = mul nsw i64 %66, %68
  %70 = sub nsw i64 %63, %69
  %71 = load ptr, ptr %3, align 8, !tbaa !5
  store i64 %70, ptr %71, align 8, !tbaa !9
  br label %72

72:                                               ; preds = %24
  %73 = load i32, ptr %5, align 4, !tbaa !11
  %74 = add nsw i32 %73, 1
  store i32 %74, ptr %5, align 4, !tbaa !11
  br label %15, !llvm.loop !13

75:                                               ; preds = %15
  br label %76

76:                                               ; preds = %75, %10, %2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef x86_fp80 @_ZSt4sqrte(x86_fp80 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.abs.i64(i64, i1 immarg) #3

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare x86_fp80 @llvm.fmuladd.f80(x86_fp80, x86_fp80, x86_fp80) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z1PRlS_(ptr nocapture noundef nonnull align 8 dereferenceable(8) %0, ptr nocapture noundef nonnull align 8 dereferenceable(8) %1) local_unnamed_addr #0 {
  %3 = load i64, ptr %0, align 8, !tbaa !5
  %4 = icmp sgt i64 %3, 0
  %5 = load i64, ptr %1, align 8
  %6 = icmp sgt i64 %5, 0
  %or.cond = select i1 %4, i1 %6, i1 false
  br i1 %or.cond, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %2, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 1, %2 ]
  %7 = phi i64 [ %28, %.lr.ph ], [ %5, %2 ]
  %8 = phi i64 [ %27, %.lr.ph ], [ %3, %2 ]
  %9 = mul nsw i64 %8, %8
  %10 = add nsw i64 %9, %7
  store i64 %10, ptr %1, align 8, !tbaa !5
  %11 = load i64, ptr %0, align 8, !tbaa !5
  %12 = mul nsw i64 %11, %11
  %13 = add nsw i64 %12, %10
  store i64 %13, ptr %0, align 8, !tbaa !5
  %14 = sitofp i64 %13 to x86_fp80
  %15 = load i64, ptr %1, align 8, !tbaa !5
  %16 = tail call i64 @llvm.abs.i64(i64 %15, i1 true)
  %17 = sdiv i64 %15, %16
  %18 = sitofp i64 %17 to x86_fp80
  %19 = sub nsw i64 0, %16
  %20 = sitofp i64 %19 to x86_fp80
  %21 = tail call x86_fp80 @llvm.fmuladd.f80(x86_fp80 %18, x86_fp80 %20, x86_fp80 %14)
  %22 = tail call noundef x86_fp80 @_ZSt4sqrte(x86_fp80 noundef %21)
  %23 = fptosi x86_fp80 %22 to i64
  store i64 %23, ptr %1, align 8, !tbaa !5
  %24 = load i64, ptr %0, align 8, !tbaa !5
  %25 = shl nsw i64 %23, 1
  %26 = mul nsw i64 %25, %23
  %27 = sub nsw i64 %24, %26
  store i64 %27, ptr %0, align 8, !tbaa !5
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %28 = load i64, ptr %1, align 8, !tbaa !5
  %29 = add nsw i64 %28, %27
  %.not.not = icmp sgt i64 %29, %indvars.iv
  br i1 %.not.not, label %.lr.ph, label %.loopexit, !llvm.loop !9

.loopexit:                                        ; preds = %.lr.ph, %2
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef x86_fp80 @_ZSt4sqrte(x86_fp80 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.abs.i64(i64, i1 immarg) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare x86_fp80 @llvm.fmuladd.f80(x86_fp80, x86_fp80, x86_fp80) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass