; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (SetMPURegion)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.anon = type { i64, i32 }

@region_size = external hidden constant [28 x %struct.anon], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @Xil_SetMPURegion(i64 noundef %0, i64 noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store i64 %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  %13 = load i64, ptr %5, align 8, !tbaa !5
  store i64 %13, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %14 = call i32 @Xil_GetNextMPURegion()
  store i32 %14, ptr %10, align 4, !tbaa !9
  %15 = load i32, ptr %10, align 4, !tbaa !9
  %16 = icmp eq i32 %15, 255
  br i1 %16, label %17, label %18

17:                                               ; preds = %3
  store i32 1, ptr %4, align 4
  store i32 1, ptr %12, align 4
  br label %64

18:                                               ; preds = %3
  call void @Xil_DCacheFlush()
  call void @Xil_ICacheInvalidate()
  %19 = load i32, ptr %10, align 4, !tbaa !9
  call void asm sideeffect "msr XREG_CP15_MPU_MEMORY_REG_NUMBER,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %19) #3, !srcloc !11
  call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !12
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %39, %18
  %21 = load i32, ptr %11, align 4, !tbaa !9
  %22 = zext i32 %21 to i64
  %23 = icmp ult i64 %22, 28
  br i1 %23, label %24, label %42

24:                                               ; preds = %20
  %25 = load i64, ptr %6, align 8, !tbaa !5
  %26 = load i32, ptr %11, align 4, !tbaa !9
  %27 = zext i32 %26 to i64
  %28 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %27
  %29 = getelementptr inbounds %struct.anon, ptr %28, i32 0, i32 0
  %30 = load i64, ptr %29, align 16, !tbaa !13
  %31 = icmp ule i64 %25, %30
  br i1 %31, label %32, label %38

32:                                               ; preds = %24
  %33 = load i32, ptr %11, align 4, !tbaa !9
  %34 = zext i32 %33 to i64
  %35 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %34
  %36 = getelementptr inbounds %struct.anon, ptr %35, i32 0, i32 1
  %37 = load i32, ptr %36, align 8, !tbaa !15
  store i32 %37, ptr %8, align 4, !tbaa !9
  br label %42

38:                                               ; preds = %24
  br label %39

39:                                               ; preds = %38
  %40 = load i32, ptr %11, align 4, !tbaa !9
  %41 = add i32 %40, 1
  store i32 %41, ptr %11, align 4, !tbaa !9
  br label %20, !llvm.loop !16

42:                                               ; preds = %32, %20
  %43 = load i32, ptr %11, align 4, !tbaa !9
  %44 = zext i32 %43 to i64
  %45 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %44
  %46 = getelementptr inbounds %struct.anon, ptr %45, i32 0, i32 0
  %47 = load i64, ptr %46, align 16, !tbaa !13
  %48 = sub i64 %47, 1
  %49 = xor i64 %48, -1
  %50 = load i64, ptr %9, align 8, !tbaa !5
  %51 = and i64 %50, %49
  store i64 %51, ptr %9, align 8, !tbaa !5
  %52 = load i32, ptr %8, align 4, !tbaa !9
  %53 = shl i32 %52, 1
  store i32 %53, ptr %8, align 4, !tbaa !9
  %54 = load i32, ptr %8, align 4, !tbaa !9
  %55 = or i32 %54, 1
  store i32 %55, ptr %8, align 4, !tbaa !9
  call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !18
  %56 = load i64, ptr %9, align 8, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_MPU_REG_BASEADDR,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i64 %56) #3, !srcloc !19
  %57 = load i32, ptr %7, align 4, !tbaa !9
  call void asm sideeffect "msr XREG_CP15_MPU_REG_ACCESS_CTRL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %57) #3, !srcloc !20
  %58 = load i32, ptr %8, align 4, !tbaa !9
  call void asm sideeffect "msr XREG_CP15_MPU_REG_SIZE_EN,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %58) #3, !srcloc !21
  call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !22
  call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !23
  %59 = load i32, ptr %10, align 4, !tbaa !9
  %60 = load i64, ptr %9, align 8, !tbaa !5
  %61 = load i32, ptr %8, align 4, !tbaa !9
  %62 = load i32, ptr %7, align 4, !tbaa !9
  %63 = call i32 @Xil_UpdateMPUConfig(i32 noundef %59, i64 noundef %60, i32 noundef %61, i32 noundef %62)
  store i32 0, ptr %4, align 4
  store i32 1, ptr %12, align 4
  br label %64

64:                                               ; preds = %42, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %65 = load i32, ptr %4, align 4
  ret i32 %65
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @Xil_GetNextMPURegion() #1

declare void @Xil_DCacheFlush() #2

declare void @Xil_ICacheInvalidate() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @Xil_UpdateMPUConfig(i32 noundef, i64 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{i64 2147713749}
!12 = !{i64 2147713862}
!13 = !{!14, !6, i64 0}
!14 = !{!"", !6, i64 0, !10, i64 8}
!15 = !{!14, !10, i64 8}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{i64 2147713905}
!19 = !{i64 2147713936}
!20 = !{i64 2147714030}
!21 = !{i64 2147714124}
!22 = !{i64 2147714218}
!23 = !{i64 2147714250}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.anon = type { i64, i32 }

@region_size = external hidden local_unnamed_addr constant [28 x %struct.anon], align 16

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @Xil_SetMPURegion(i64 noundef %0, i64 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = tail call i32 @Xil_GetNextMPURegion()
  %5 = icmp eq i32 %4, 255
  br i1 %5, label %73, label %6

6:                                                ; preds = %3
  tail call void @Xil_DCacheFlush() #2
  tail call void @Xil_ICacheInvalidate() #2
  tail call void asm sideeffect "msr XREG_CP15_MPU_MEMORY_REG_NUMBER,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %4) #2, !srcloc !5
  tail call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !6
  %7 = load i64, ptr @region_size, align 16, !tbaa !7
  %.not = icmp ult i64 %7, %1
  br i1 %.not, label %8, label %62

8:                                                ; preds = %6
  %9 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 16), align 16, !tbaa !7
  %.not.1 = icmp ult i64 %9, %1
  br i1 %.not.1, label %10, label %62

10:                                               ; preds = %8
  %11 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 32), align 16, !tbaa !7
  %.not.2 = icmp ult i64 %11, %1
  br i1 %.not.2, label %12, label %62

12:                                               ; preds = %10
  %13 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 48), align 16, !tbaa !7
  %.not.3 = icmp ult i64 %13, %1
  br i1 %.not.3, label %14, label %62

14:                                               ; preds = %12
  %15 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 64), align 16, !tbaa !7
  %.not.4 = icmp ult i64 %15, %1
  br i1 %.not.4, label %16, label %62

16:                                               ; preds = %14
  %17 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 80), align 16, !tbaa !7
  %.not.5 = icmp ult i64 %17, %1
  br i1 %.not.5, label %18, label %62

18:                                               ; preds = %16
  %19 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 96), align 16, !tbaa !7
  %.not.6 = icmp ult i64 %19, %1
  br i1 %.not.6, label %20, label %62

20:                                               ; preds = %18
  %21 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 112), align 16, !tbaa !7
  %.not.7 = icmp ult i64 %21, %1
  br i1 %.not.7, label %22, label %62

22:                                               ; preds = %20
  %23 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 128), align 16, !tbaa !7
  %.not.8 = icmp ult i64 %23, %1
  br i1 %.not.8, label %24, label %62

24:                                               ; preds = %22
  %25 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 144), align 16, !tbaa !7
  %.not.9 = icmp ult i64 %25, %1
  br i1 %.not.9, label %26, label %62

26:                                               ; preds = %24
  %27 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 160), align 16, !tbaa !7
  %.not.10 = icmp ult i64 %27, %1
  br i1 %.not.10, label %28, label %62

28:                                               ; preds = %26
  %29 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 176), align 16, !tbaa !7
  %.not.11 = icmp ult i64 %29, %1
  br i1 %.not.11, label %30, label %62

30:                                               ; preds = %28
  %31 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 192), align 16, !tbaa !7
  %.not.12 = icmp ult i64 %31, %1
  br i1 %.not.12, label %32, label %62

32:                                               ; preds = %30
  %33 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 208), align 16, !tbaa !7
  %.not.13 = icmp ult i64 %33, %1
  br i1 %.not.13, label %34, label %62

34:                                               ; preds = %32
  %35 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 224), align 16, !tbaa !7
  %.not.14 = icmp ult i64 %35, %1
  br i1 %.not.14, label %36, label %62

36:                                               ; preds = %34
  %37 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 240), align 16, !tbaa !7
  %.not.15 = icmp ult i64 %37, %1
  br i1 %.not.15, label %38, label %62

38:                                               ; preds = %36
  %39 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 256), align 16, !tbaa !7
  %.not.16 = icmp ult i64 %39, %1
  br i1 %.not.16, label %40, label %62

40:                                               ; preds = %38
  %41 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 272), align 16, !tbaa !7
  %.not.17 = icmp ult i64 %41, %1
  br i1 %.not.17, label %42, label %62

42:                                               ; preds = %40
  %43 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 288), align 16, !tbaa !7
  %.not.18 = icmp ult i64 %43, %1
  br i1 %.not.18, label %44, label %62

44:                                               ; preds = %42
  %45 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 304), align 16, !tbaa !7
  %.not.19 = icmp ult i64 %45, %1
  br i1 %.not.19, label %46, label %62

46:                                               ; preds = %44
  %47 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 320), align 16, !tbaa !7
  %.not.20 = icmp ult i64 %47, %1
  br i1 %.not.20, label %48, label %62

48:                                               ; preds = %46
  %49 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 336), align 16, !tbaa !7
  %.not.21 = icmp ult i64 %49, %1
  br i1 %.not.21, label %50, label %62

50:                                               ; preds = %48
  %51 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 352), align 16, !tbaa !7
  %.not.22 = icmp ult i64 %51, %1
  br i1 %.not.22, label %52, label %62

52:                                               ; preds = %50
  %53 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 368), align 16, !tbaa !7
  %.not.23 = icmp ult i64 %53, %1
  br i1 %.not.23, label %54, label %62

54:                                               ; preds = %52
  %55 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 384), align 16, !tbaa !7
  %.not.24 = icmp ult i64 %55, %1
  br i1 %.not.24, label %56, label %62

56:                                               ; preds = %54
  %57 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 400), align 16, !tbaa !7
  %.not.25 = icmp ult i64 %57, %1
  br i1 %.not.25, label %58, label %62

58:                                               ; preds = %56
  %59 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 416), align 16, !tbaa !7
  %.not.26 = icmp ult i64 %59, %1
  br i1 %.not.26, label %60, label %62

60:                                               ; preds = %58
  %61 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 432), align 16, !tbaa !7
  %.not.27 = icmp ult i64 %61, %1
  br i1 %.not.27, label %.loopexit, label %62

62:                                               ; preds = %60, %58, %56, %54, %52, %50, %48, %46, %44, %42, %40, %38, %36, %34, %32, %30, %28, %26, %24, %22, %20, %18, %16, %14, %12, %10, %8, %6
  %.lcssa28 = phi i64 [ 0, %6 ], [ 1, %8 ], [ 2, %10 ], [ 3, %12 ], [ 4, %14 ], [ 5, %16 ], [ 6, %18 ], [ 7, %20 ], [ 8, %22 ], [ 9, %24 ], [ 10, %26 ], [ 11, %28 ], [ 12, %30 ], [ 13, %32 ], [ 14, %34 ], [ 15, %36 ], [ 16, %38 ], [ 17, %40 ], [ 18, %42 ], [ 19, %44 ], [ 20, %46 ], [ 21, %48 ], [ 22, %50 ], [ 23, %52 ], [ 24, %54 ], [ 25, %56 ], [ 26, %58 ], [ 27, %60 ]
  %.lcssa = phi ptr [ @region_size, %6 ], [ getelementptr inbounds (i8, ptr @region_size, i64 16), %8 ], [ getelementptr inbounds (i8, ptr @region_size, i64 32), %10 ], [ getelementptr inbounds (i8, ptr @region_size, i64 48), %12 ], [ getelementptr inbounds (i8, ptr @region_size, i64 64), %14 ], [ getelementptr inbounds (i8, ptr @region_size, i64 80), %16 ], [ getelementptr inbounds (i8, ptr @region_size, i64 96), %18 ], [ getelementptr inbounds (i8, ptr @region_size, i64 112), %20 ], [ getelementptr inbounds (i8, ptr @region_size, i64 128), %22 ], [ getelementptr inbounds (i8, ptr @region_size, i64 144), %24 ], [ getelementptr inbounds (i8, ptr @region_size, i64 160), %26 ], [ getelementptr inbounds (i8, ptr @region_size, i64 176), %28 ], [ getelementptr inbounds (i8, ptr @region_size, i64 192), %30 ], [ getelementptr inbounds (i8, ptr @region_size, i64 208), %32 ], [ getelementptr inbounds (i8, ptr @region_size, i64 224), %34 ], [ getelementptr inbounds (i8, ptr @region_size, i64 240), %36 ], [ getelementptr inbounds (i8, ptr @region_size, i64 256), %38 ], [ getelementptr inbounds (i8, ptr @region_size, i64 272), %40 ], [ getelementptr inbounds (i8, ptr @region_size, i64 288), %42 ], [ getelementptr inbounds (i8, ptr @region_size, i64 304), %44 ], [ getelementptr inbounds (i8, ptr @region_size, i64 320), %46 ], [ getelementptr inbounds (i8, ptr @region_size, i64 336), %48 ], [ getelementptr inbounds (i8, ptr @region_size, i64 352), %50 ], [ getelementptr inbounds (i8, ptr @region_size, i64 368), %52 ], [ getelementptr inbounds (i8, ptr @region_size, i64 384), %54 ], [ getelementptr inbounds (i8, ptr @region_size, i64 400), %56 ], [ getelementptr inbounds (i8, ptr @region_size, i64 416), %58 ], [ getelementptr inbounds (i8, ptr @region_size, i64 432), %60 ]
  %63 = getelementptr inbounds i8, ptr %.lcssa, i64 8
  %64 = load i32, ptr %63, align 8, !tbaa !13
  %65 = shl i32 %64, 1
  %66 = or disjoint i32 %65, 1
  br label %.loopexit

.loopexit:                                        ; preds = %60, %62
  %67 = phi i64 [ %.lcssa28, %62 ], [ 28, %60 ]
  %.021 = phi i32 [ %66, %62 ], [ 1, %60 ]
  %68 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %67
  %69 = load i64, ptr %68, align 16, !tbaa !7
  %70 = sub i64 0, %69
  %71 = and i64 %70, %0
  tail call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !14
  tail call void asm sideeffect "msr XREG_CP15_MPU_REG_BASEADDR,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i64 %71) #2, !srcloc !15
  tail call void asm sideeffect "msr XREG_CP15_MPU_REG_ACCESS_CTRL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %2) #2, !srcloc !16
  tail call void asm sideeffect "msr XREG_CP15_MPU_REG_SIZE_EN,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %.021) #2, !srcloc !17
  tail call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !18
  tail call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !19
  %72 = tail call i32 @Xil_UpdateMPUConfig(i32 noundef %4, i64 noundef %71, i32 noundef %.021, i32 noundef %2)
  br label %73

73:                                               ; preds = %3, %.loopexit
  %.020 = phi i32 [ 0, %.loopexit ], [ 1, %3 ]
  ret i32 %.020
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @Xil_GetNextMPURegion() local_unnamed_addr #0

declare void @Xil_DCacheFlush() local_unnamed_addr #1

declare void @Xil_ICacheInvalidate() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @Xil_UpdateMPUConfig(i32 noundef, i64 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147713749}
!6 = !{i64 2147713862}
!7 = !{!8, !9, i64 0}
!8 = !{!"", !9, i64 0, !12, i64 8}
!9 = !{!"long", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C/C++ TBAA"}
!12 = !{!"int", !10, i64 0}
!13 = !{!8, !12, i64 8}
!14 = !{i64 2147713905}
!15 = !{i64 2147713936}
!16 = !{i64 2147714030}
!17 = !{i64 2147714124}
!18 = !{i64 2147714218}
!19 = !{i64 2147714250}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass