; LLVM IR from Discngine/fpocket :: src/qhull/src/libqhullcpp/Qhull.ll (ZNK8orgQhull5Qhull13feasiblePointEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.orgQhull::Coordinates" = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.orgQhull::Qhull" = type { ptr, %"class.orgQhull::Coordinates", i8, %"class.orgQhull::Coordinates" }
%struct.qhT = type { i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, double, double, i32, i32, i32, i32, i32, ptr, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, double, double, i32, i32, i32, double, double, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [29 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, double, i32, ptr, ptr, i32, i32, i32, i32, i32, ptr, i32, ptr, i32, [256 x i8], i32, [256 x i8], [512 x i8], i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, double, double, double, double, double, double, double, double, double, double, double, double, double, i32, ptr, double, double, double, double, [6 x i8], [1 x %struct.__jmp_buf_tag], [40 x i8], [1 x %struct.__jmp_buf_tag], [40 x i8], ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i64, i32, i32, i32, i32, ptr, i32, i32, double, i32, double, double, double, i32, i32, i32, i32, double, double, i32, i32, i32, i32, double, double, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, ptr, ptr, i32, i32, i32, ptr, double, double, double, i32, i32, ptr, i32, i32, [1 x %struct.__jmp_buf_tag], [40 x i8], i32, double, ptr, %struct.qhmemT, %struct.qhstatT }
%struct.__jmp_buf_tag = type { [8 x i64], i32, %struct.__sigset_t }
%struct.__sigset_t = type { [16 x i64] }
%struct.qhmemT = type { i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.qhstatT = type { [227 x %union.intrealT], [237 x i8], [227 x ptr], [227 x i16], [227 x i8], [227 x i8], [9 x %union.intrealT], i32, i32, i32, i32, double }
%union.intrealT = type { double }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN8orgQhull11CoordinatesC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN8orgQhull11CoordinatesD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK8orgQhull5Qhull13feasiblePointEv(ptr dead_on_unwind noalias writable sret(%"class.orgQhull::Coordinates") align 8 %0, ptr noundef nonnull align 8 dereferenceable(64) %1) #1 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i1, align 1
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %4, align 8
  store i1 false, ptr %5, align 1
  call void @_ZN8orgQhull11CoordinatesC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0)
  %9 = getelementptr inbounds %"class.orgQhull::Qhull", ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 8, !tbaa !9
  %11 = getelementptr inbounds %struct.qhT, ptr %10, i32 0, i32 101
  %12 = load ptr, ptr %11, align 8, !tbaa !17
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %28

14:                                               ; preds = %2
  %15 = getelementptr inbounds %"class.orgQhull::Qhull", ptr %8, i32 0, i32 0
  %16 = load ptr, ptr %15, align 8, !tbaa !9
  %17 = getelementptr inbounds %struct.qhT, ptr %16, i32 0, i32 104
  %18 = load i32, ptr %17, align 8, !tbaa !25
  %19 = getelementptr inbounds %"class.orgQhull::Qhull", ptr %8, i32 0, i32 0
  %20 = load ptr, ptr %19, align 8, !tbaa !9
  %21 = getelementptr inbounds %struct.qhT, ptr %20, i32 0, i32 101
  %22 = load ptr, ptr %21, align 8, !tbaa !17
  invoke void @_ZN8orgQhull11Coordinates6appendEiPd(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %18, ptr noundef %22)
          to label %23 unwind label %24

23:                                               ; preds = %14
  br label %32

24:                                               ; preds = %28, %14
  %25 = landingpad { ptr, i32 }
          cleanup
  %26 = extractvalue { ptr, i32 } %25, 0
  store ptr %26, ptr %6, align 8
  %27 = extractvalue { ptr, i32 } %25, 1
  store i32 %27, ptr %7, align 4
  call void @_ZN8orgQhull11CoordinatesD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  br label %36

28:                                               ; preds = %2
  %29 = getelementptr inbounds %"class.orgQhull::Qhull", ptr %8, i32 0, i32 3
  %30 = invoke noundef nonnull align 8 dereferenceable(24) ptr @_ZN8orgQhull11CoordinatesaSERKS0_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %29)
          to label %31 unwind label %24

31:                                               ; preds = %28
  br label %32

32:                                               ; preds = %31, %23
  store i1 true, ptr %5, align 1
  %33 = load i1, ptr %5, align 1
  br i1 %33, label %35, label %34

34:                                               ; preds = %32
  call void @_ZN8orgQhull11CoordinatesD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  br label %35

35:                                               ; preds = %34, %32
  ret void

36:                                               ; preds = %24
  %37 = load ptr, ptr %6, align 8
  %38 = load i32, ptr %7, align 4
  %39 = insertvalue { ptr, i32 } poison, ptr %37, 0
  %40 = insertvalue { ptr, i32 } %39, i32 %38, 1
  resume { ptr, i32 } %40
}

declare void @_ZN8orgQhull11Coordinates6appendEiPd(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, ptr noundef) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZN8orgQhull11CoordinatesaSERKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTSN8orgQhull5QhullE", !6, i64 0, !11, i64 8, !16, i64 32, !11, i64 40}
!11 = !{!"_ZTSN8orgQhull11CoordinatesE", !12, i64 0}
!12 = !{!"_ZTSSt6vectorIdSaIdEE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!"bool", !7, i64 0}
!17 = !{!18, !6, i64 608}
!18 = !{!"_ZTS3qhT", !19, i64 0, !19, i64 4, !19, i64 8, !20, i64 16, !19, i64 24, !19, i64 28, !19, i64 32, !19, i64 36, !19, i64 40, !19, i64 44, !19, i64 48, !20, i64 56, !20, i64 64, !19, i64 72, !19, i64 76, !19, i64 80, !19, i64 84, !19, i64 88, !6, i64 96, !19, i64 104, !19, i64 108, !6, i64 112, !19, i64 120, !19, i64 124, !19, i64 128, !19, i64 132, !19, i64 136, !19, i64 140, !19, i64 144, !20, i64 152, !20, i64 160, !19, i64 168, !19, i64 172, !19, i64 176, !20, i64 184, !20, i64 192, !19, i64 200, !20, i64 208, !19, i64 216, !19, i64 220, !19, i64 224, !19, i64 228, !19, i64 232, !19, i64 236, !19, i64 240, !19, i64 244, !19, i64 248, !19, i64 252, !19, i64 256, !19, i64 260, !19, i64 264, !19, i64 268, !19, i64 272, !19, i64 276, !19, i64 280, !19, i64 284, !19, i64 288, !19, i64 292, !7, i64 296, !19, i64 412, !19, i64 416, !19, i64 420, !19, i64 424, !19, i64 428, !19, i64 432, !19, i64 436, !19, i64 440, !19, i64 444, !20, i64 448, !20, i64 456, !20, i64 464, !19, i64 472, !19, i64 476, !19, i64 480, !19, i64 484, !19, i64 488, !19, i64 492, !19, i64 496, !19, i64 500, !19, i64 504, !19, i64 508, !19, i64 512, !19, i64 516, !19, i64 520, !19, i64 524, !19, i64 528, !19, i64 532, !19, i64 536, !19, i64 540, !20, i64 544, !19, i64 552, !19, i64 556, !19, i64 560, !19, i64 564, !19, i64 568, !19, i64 572, !19, i64 576, !19, i64 580, !20, i64 584, !19, i64 592, !6, i64 600, !6, i64 608, !19, i64 616, !19, i64 620, !19, i64 624, !19, i64 628, !19, i64 632, !6, i64 640, !19, i64 648, !6, i64 656, !19, i64 664, !7, i64 668, !19, i64 924, !7, i64 928, !7, i64 1184, !19, i64 1696, !19, i64 1700, !19, i64 1704, !19, i64 1708, !19, i64 1712, !19, i64 1716, !6, i64 1720, !6, i64 1728, !6, i64 1736, !6, i64 1744, !20, i64 1752, !20, i64 1760, !20, i64 1768, !20, i64 1776, !20, i64 1784, !20, i64 1792, !20, i64 1800, !20, i64 1808, !20, i64 1816, !20, i64 1824, !20, i64 1832, !20, i64 1840, !20, i64 1848, !19, i64 1856, !6, i64 1864, !20, i64 1872, !20, i64 1880, !20, i64 1888, !20, i64 1896, !7, i64 1904, !7, i64 1912, !7, i64 2112, !7, i64 2152, !7, i64 2352, !6, i64 2392, !6, i64 2400, !6, i64 2408, !6, i64 2416, !19, i64 2424, !19, i64 2428, !19, i64 2432, !6, i64 2440, !6, i64 2448, !6, i64 2456, !6, i64 2464, !6, i64 2472, !19, i64 2480, !19, i64 2484, !6, i64 2488, !19, i64 2496, !6, i64 2504, !6, i64 2512, !6, i64 2520, !6, i64 2528, !19, i64 2536, !19, i64 2540, !19, i64 2544, !19, i64 2548, !19, i64 2552, !19, i64 2556, !19, i64 2560, !21, i64 2568, !19, i64 2576, !19, i64 2580, !22, i64 2584, !19, i64 2588, !6, i64 2592, !19, i64 2600, !19, i64 2604, !20, i64 2608, !19, i64 2616, !20, i64 2624, !20, i64 2632, !20, i64 2640, !19, i64 2648, !19, i64 2652, !19, i64 2656, !19, i64 2660, !20, i64 2664, !20, i64 2672, !19, i64 2680, !19, i64 2684, !19, i64 2688, !19, i64 2692, !20, i64 2696, !20, i64 2704, !19, i64 2712, !19, i64 2716, !19, i64 2720, !19, i64 2724, !6, i64 2728, !6, i64 2736, !6, i64 2744, !6, i64 2752, !6, i64 2760, !6, i64 2768, !6, i64 2776, !6, i64 2784, !19, i64 2792, !6, i64 2800, !6, i64 2808, !19, i64 2816, !19, i64 2820, !19, i64 2824, !6, i64 2832, !20, i64 2840, !20, i64 2848, !20, i64 2856, !19, i64 2864, !19, i64 2868, !6, i64 2872, !19, i64 2880, !19, i64 2884, !7, i64 2888, !7, i64 3088, !19, i64 3128, !20, i64 3136, !6, i64 3144, !23, i64 3152, !24, i64 3304}
!19 = !{!"int", !7, i64 0}
!20 = !{!"double", !7, i64 0}
!21 = !{!"long", !7, i64 0}
!22 = !{!"_ZTS9qh_CENTER", !7, i64 0}
!23 = !{!"_ZTS6qhmemT", !19, i64 0, !19, i64 4, !19, i64 8, !19, i64 12, !19, i64 16, !19, i64 20, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !19, i64 64, !6, i64 72, !6, i64 80, !19, i64 88, !19, i64 92, !19, i64 96, !19, i64 100, !19, i64 104, !19, i64 108, !19, i64 112, !19, i64 116, !19, i64 120, !19, i64 124, !19, i64 128, !19, i64 132, !19, i64 136, !19, i64 140, !19, i64 144}
!24 = !{!"_ZTS7qhstatT", !7, i64 0, !7, i64 1816, !7, i64 2056, !7, i64 3872, !7, i64 4326, !7, i64 4553, !7, i64 4784, !19, i64 4856, !19, i64 4860, !19, i64 4864, !19, i64 4868, !20, i64 4872}
!25 = !{!18, !19, i64 624}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.orgQhull::Coordinates" = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN8orgQhull11CoordinatesC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN8orgQhull11CoordinatesD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK8orgQhull5Qhull13feasiblePointEv(ptr dead_on_unwind noalias nonnull writable sret(%"class.orgQhull::Coordinates") align 8 %0, ptr noundef nonnull align 8 dereferenceable(64) %1) local_unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN8orgQhull11CoordinatesC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0)
  %3 = load ptr, ptr %1, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %3, i64 608
  %5 = load ptr, ptr %4, align 8, !tbaa !16
  %.not = icmp eq ptr %5, null
  br i1 %.not, label %11, label %6

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %3, i64 624
  %8 = load i32, ptr %7, align 8, !tbaa !24
  invoke void @_ZN8orgQhull11Coordinates6appendEiPd(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %8, ptr noundef nonnull %5)
          to label %14 unwind label %9

9:                                                ; preds = %11, %6
  %10 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZN8orgQhull11CoordinatesD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  resume { ptr, i32 } %10

11:                                               ; preds = %2
  %12 = getelementptr inbounds i8, ptr %1, i64 40
  %13 = invoke noundef nonnull align 8 dereferenceable(24) ptr @_ZN8orgQhull11CoordinatesaSERKS0_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %12)
          to label %14 unwind label %9

14:                                               ; preds = %6, %11
  ret void
}

declare void @_ZN8orgQhull11Coordinates6appendEiPd(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZN8orgQhull11CoordinatesaSERKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN8orgQhull5QhullE", !7, i64 0, !10, i64 8, !15, i64 32, !10, i64 40}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSN8orgQhull11CoordinatesE", !11, i64 0}
!11 = !{!"_ZTSSt6vectorIdSaIdEE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!15 = !{!"bool", !8, i64 0}
!16 = !{!17, !7, i64 608}
!17 = !{!"_ZTS3qhT", !18, i64 0, !18, i64 4, !18, i64 8, !19, i64 16, !18, i64 24, !18, i64 28, !18, i64 32, !18, i64 36, !18, i64 40, !18, i64 44, !18, i64 48, !19, i64 56, !19, i64 64, !18, i64 72, !18, i64 76, !18, i64 80, !18, i64 84, !18, i64 88, !7, i64 96, !18, i64 104, !18, i64 108, !7, i64 112, !18, i64 120, !18, i64 124, !18, i64 128, !18, i64 132, !18, i64 136, !18, i64 140, !18, i64 144, !19, i64 152, !19, i64 160, !18, i64 168, !18, i64 172, !18, i64 176, !19, i64 184, !19, i64 192, !18, i64 200, !19, i64 208, !18, i64 216, !18, i64 220, !18, i64 224, !18, i64 228, !18, i64 232, !18, i64 236, !18, i64 240, !18, i64 244, !18, i64 248, !18, i64 252, !18, i64 256, !18, i64 260, !18, i64 264, !18, i64 268, !18, i64 272, !18, i64 276, !18, i64 280, !18, i64 284, !18, i64 288, !18, i64 292, !8, i64 296, !18, i64 412, !18, i64 416, !18, i64 420, !18, i64 424, !18, i64 428, !18, i64 432, !18, i64 436, !18, i64 440, !18, i64 444, !19, i64 448, !19, i64 456, !19, i64 464, !18, i64 472, !18, i64 476, !18, i64 480, !18, i64 484, !18, i64 488, !18, i64 492, !18, i64 496, !18, i64 500, !18, i64 504, !18, i64 508, !18, i64 512, !18, i64 516, !18, i64 520, !18, i64 524, !18, i64 528, !18, i64 532, !18, i64 536, !18, i64 540, !19, i64 544, !18, i64 552, !18, i64 556, !18, i64 560, !18, i64 564, !18, i64 568, !18, i64 572, !18, i64 576, !18, i64 580, !19, i64 584, !18, i64 592, !7, i64 600, !7, i64 608, !18, i64 616, !18, i64 620, !18, i64 624, !18, i64 628, !18, i64 632, !7, i64 640, !18, i64 648, !7, i64 656, !18, i64 664, !8, i64 668, !18, i64 924, !8, i64 928, !8, i64 1184, !18, i64 1696, !18, i64 1700, !18, i64 1704, !18, i64 1708, !18, i64 1712, !18, i64 1716, !7, i64 1720, !7, i64 1728, !7, i64 1736, !7, i64 1744, !19, i64 1752, !19, i64 1760, !19, i64 1768, !19, i64 1776, !19, i64 1784, !19, i64 1792, !19, i64 1800, !19, i64 1808, !19, i64 1816, !19, i64 1824, !19, i64 1832, !19, i64 1840, !19, i64 1848, !18, i64 1856, !7, i64 1864, !19, i64 1872, !19, i64 1880, !19, i64 1888, !19, i64 1896, !8, i64 1904, !8, i64 1912, !8, i64 2112, !8, i64 2152, !8, i64 2352, !7, i64 2392, !7, i64 2400, !7, i64 2408, !7, i64 2416, !18, i64 2424, !18, i64 2428, !18, i64 2432, !7, i64 2440, !7, i64 2448, !7, i64 2456, !7, i64 2464, !7, i64 2472, !18, i64 2480, !18, i64 2484, !7, i64 2488, !18, i64 2496, !7, i64 2504, !7, i64 2512, !7, i64 2520, !7, i64 2528, !18, i64 2536, !18, i64 2540, !18, i64 2544, !18, i64 2548, !18, i64 2552, !18, i64 2556, !18, i64 2560, !20, i64 2568, !18, i64 2576, !18, i64 2580, !21, i64 2584, !18, i64 2588, !7, i64 2592, !18, i64 2600, !18, i64 2604, !19, i64 2608, !18, i64 2616, !19, i64 2624, !19, i64 2632, !19, i64 2640, !18, i64 2648, !18, i64 2652, !18, i64 2656, !18, i64 2660, !19, i64 2664, !19, i64 2672, !18, i64 2680, !18, i64 2684, !18, i64 2688, !18, i64 2692, !19, i64 2696, !19, i64 2704, !18, i64 2712, !18, i64 2716, !18, i64 2720, !18, i64 2724, !7, i64 2728, !7, i64 2736, !7, i64 2744, !7, i64 2752, !7, i64 2760, !7, i64 2768, !7, i64 2776, !7, i64 2784, !18, i64 2792, !7, i64 2800, !7, i64 2808, !18, i64 2816, !18, i64 2820, !18, i64 2824, !7, i64 2832, !19, i64 2840, !19, i64 2848, !19, i64 2856, !18, i64 2864, !18, i64 2868, !7, i64 2872, !18, i64 2880, !18, i64 2884, !8, i64 2888, !8, i64 3088, !18, i64 3128, !19, i64 3136, !7, i64 3144, !22, i64 3152, !23, i64 3304}
!18 = !{!"int", !8, i64 0}
!19 = !{!"double", !8, i64 0}
!20 = !{!"long", !8, i64 0}
!21 = !{!"_ZTS9qh_CENTER", !8, i64 0}
!22 = !{!"_ZTS6qhmemT", !18, i64 0, !18, i64 4, !18, i64 8, !18, i64 12, !18, i64 16, !18, i64 20, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !18, i64 64, !7, i64 72, !7, i64 80, !18, i64 88, !18, i64 92, !18, i64 96, !18, i64 100, !18, i64 104, !18, i64 108, !18, i64 112, !18, i64 116, !18, i64 120, !18, i64 124, !18, i64 128, !18, i64 132, !18, i64 136, !18, i64 140, !18, i64 144}
!23 = !{!"_ZTS7qhstatT", !8, i64 0, !8, i64 1816, !8, i64 2056, !8, i64 3872, !8, i64 4326, !8, i64 4553, !8, i64 4784, !18, i64 4856, !18, i64 4860, !18, i64 4864, !18, i64 4868, !19, i64 4872}
!24 = !{!17, !18, i64 624}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass