; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (EpDataBufferReceive)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XUsbPs = type { %struct.XUsbPs_SetupData, %struct.XUsbPs_Config, i32, ptr, %struct.XUsbPs_DeviceConfig, ptr, ptr, i32, ptr, i8, ptr }
%struct.XUsbPs_SetupData = type { i8, i8, i16, i16, i16 }
%struct.XUsbPs_Config = type { i16, i32 }
%struct.XUsbPs_DeviceConfig = type { i8, [12 x %struct.XUsbPs_EpConfig], i32, [12 x %struct.XUsbPs_Endpoint], i32 }
%struct.XUsbPs_EpConfig = type { %struct.XUsbPs_EpSetup, %struct.XUsbPs_EpSetup }
%struct.XUsbPs_EpSetup = type { i32, i32, i32, i16 }
%struct.XUsbPs_Endpoint = type { %struct.XUsbPs_EpOut, %struct.XUsbPs_EpIn }
%struct.XUsbPs_EpOut = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i8, i32 }
%struct.XUsbPs_EpIn = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @XUsbPs_EpGetData(ptr noundef, i8 noundef zeroext, i32 noundef) #2

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XUsbPs_EpDataBufferReceive(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2, i32 noundef %3) #2 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i8 %1, ptr %7, align 1, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %15

14:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %16

15:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 623)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %72

16:                                               ; preds = %14
  %17 = load ptr, ptr %8, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %20

19:                                               ; preds = %16
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %21

20:                                               ; preds = %16
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 624)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %72

21:                                               ; preds = %19
  %22 = load i8, ptr %7, align 1, !tbaa !9
  %23 = zext i8 %22 to i32
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XUsbPs, ptr %24, i32 0, i32 4
  %26 = getelementptr inbounds %struct.XUsbPs_DeviceConfig, ptr %25, i32 0, i32 0
  %27 = load i8, ptr %26, align 8, !tbaa !12
  %28 = zext i8 %27 to i32
  %29 = icmp slt i32 %23, %28
  br i1 %29, label %30, label %31

30:                                               ; preds = %21
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %32

31:                                               ; preds = %21
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 625)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %72

32:                                               ; preds = %30
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.XUsbPs, ptr %33, i32 0, i32 4
  %35 = getelementptr inbounds %struct.XUsbPs_DeviceConfig, ptr %34, i32 0, i32 3
  %36 = load i8, ptr %7, align 1, !tbaa !9
  %37 = zext i8 %36 to i64
  %38 = getelementptr inbounds [12 x %struct.XUsbPs_Endpoint], ptr %35, i64 0, i64 %37
  %39 = getelementptr inbounds %struct.XUsbPs_Endpoint, ptr %38, i32 0, i32 0
  store ptr %39, ptr %10, align 8, !tbaa !5
  %40 = load i32, ptr %9, align 4, !tbaa !10
  %41 = load ptr, ptr %10, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.XUsbPs_EpOut, ptr %41, i32 0, i32 7
  store i32 %40, ptr %42, align 8, !tbaa !18
  %43 = load ptr, ptr %10, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.XUsbPs_EpOut, ptr %43, i32 0, i32 8
  store i32 0, ptr %44, align 4, !tbaa !20
  %45 = load ptr, ptr %8, align 8, !tbaa !5
  %46 = load ptr, ptr %10, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.XUsbPs_EpOut, ptr %46, i32 0, i32 9
  store ptr %45, ptr %47, align 8, !tbaa !21
  %48 = load ptr, ptr %10, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.XUsbPs_EpOut, ptr %48, i32 0, i32 10
  store i8 1, ptr %49, align 8, !tbaa !22
  %50 = load ptr, ptr %10, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.XUsbPs_EpOut, ptr %50, i32 0, i32 2
  %52 = load ptr, ptr %51, align 8, !tbaa !23
  %53 = ptrtoint ptr %52 to i32
  %54 = zext i32 %53 to i64
  call void @Xil_DCacheInvalidateRange(i64 noundef %54, i32 noundef 32)
  %55 = load ptr, ptr %10, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.XUsbPs_EpOut, ptr %55, i32 0, i32 2
  %57 = load ptr, ptr %56, align 8, !tbaa !23
  %58 = ptrtoint ptr %57 to i32
  %59 = add i32 %58, 4
  %60 = zext i32 %59 to i64
  %61 = inttoptr i64 %60 to ptr
  %62 = load i32, ptr %61, align 4, !tbaa !10
  %63 = and i32 %62, 128
  %64 = icmp ne i32 %63, 0
  br i1 %64, label %65, label %66

65:                                               ; preds = %32
  br i1 true, label %67, label %68

66:                                               ; preds = %32
  br i1 false, label %67, label %68

67:                                               ; preds = %66, %65
  store i32 1414, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %72

68:                                               ; preds = %66, %65
  %69 = load ptr, ptr %6, align 8, !tbaa !5
  %70 = load i8, ptr %7, align 1, !tbaa !9
  %71 = load i32, ptr %9, align 4, !tbaa !10
  call void @XUsbPs_EpGetData(ptr noundef %69, i8 noundef zeroext %70, i32 noundef %71)
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %72

72:                                               ; preds = %68, %67, %31, %20, %15
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  %73 = load i32, ptr %5, align 4
  ret i32 %73
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !7, i64 32}
!13 = !{!"", !14, i64 0, !16, i64 8, !11, i64 16, !6, i64 24, !17, i64 32, !6, i64 2352, !6, i64 2360, !11, i64 2368, !6, i64 2376, !7, i64 2384, !6, i64 2392}
!14 = !{!"", !7, i64 0, !7, i64 1, !15, i64 2, !15, i64 4, !15, i64 6}
!15 = !{!"short", !7, i64 0}
!16 = !{!"", !15, i64 0, !11, i64 4}
!17 = !{!"", !7, i64 0, !7, i64 4, !11, i64 388, !7, i64 392, !11, i64 2312}
!18 = !{!19, !11, i64 56}
!19 = !{!"", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !11, i64 56, !11, i64 60, !6, i64 64, !7, i64 72, !11, i64 76}
!20 = !{!19, !11, i64 60}
!21 = !{!19, !6, i64 64}
!22 = !{!19, !7, i64 72}
!23 = !{!19, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XUsbPs_Endpoint = type { %struct.XUsbPs_EpOut, %struct.XUsbPs_EpIn }
%struct.XUsbPs_EpOut = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i8, i32 }
%struct.XUsbPs_EpIn = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i32 }

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @XUsbPs_EpGetData(ptr noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #1

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 1415) i32 @XUsbPs_EpDataBufferReceive(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not19 = icmp eq ptr %2, null
  br i1 %.not19, label %11, label %7

6:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 623) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

7:                                                ; preds = %5
  %8 = getelementptr inbounds i8, ptr %0, i64 32
  %9 = load i8, ptr %8, align 8, !tbaa !9
  %10 = icmp ugt i8 %9, %1
  br i1 %10, label %12, label %31

11:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 624) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

12:                                               ; preds = %7
  %13 = getelementptr inbounds i8, ptr %0, i64 424
  %14 = zext i8 %1 to i64
  %15 = getelementptr inbounds [12 x %struct.XUsbPs_Endpoint], ptr %13, i64 0, i64 %14
  %16 = getelementptr inbounds i8, ptr %15, i64 56
  store i32 %3, ptr %16, align 8, !tbaa !16
  %17 = getelementptr inbounds i8, ptr %15, i64 60
  store i32 0, ptr %17, align 4, !tbaa !18
  %18 = getelementptr inbounds i8, ptr %15, i64 64
  store ptr %2, ptr %18, align 8, !tbaa !19
  %19 = getelementptr inbounds i8, ptr %15, i64 72
  store i8 1, ptr %19, align 8, !tbaa !20
  %20 = getelementptr inbounds i8, ptr %15, i64 16
  %21 = load ptr, ptr %20, align 8, !tbaa !21
  %22 = ptrtoint ptr %21 to i64
  %23 = and i64 %22, 4294967295
  tail call void @Xil_DCacheInvalidateRange(i64 noundef %23, i32 noundef 32) #2
  %24 = load ptr, ptr %20, align 8, !tbaa !21
  %25 = ptrtoint ptr %24 to i64
  %26 = add i64 %25, 4
  %27 = and i64 %26, 4294967295
  %28 = inttoptr i64 %27 to ptr
  %29 = load i32, ptr %28, align 4, !tbaa !5
  %30 = and i32 %29, 128
  %.not20 = icmp eq i32 %30, 0
  br i1 %.not20, label %32, label %33

31:                                               ; preds = %7
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 625) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

32:                                               ; preds = %12
  tail call void @XUsbPs_EpGetData(ptr noundef nonnull %0, i8 noundef zeroext %1, i32 noundef %3)
  br label %33

33:                                               ; preds = %12, %32, %31, %11, %6
  %.0 = phi i32 [ 0, %32 ], [ 0, %31 ], [ 0, %11 ], [ 0, %6 ], [ 1414, %12 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !7, i64 32}
!10 = !{!"", !11, i64 0, !13, i64 8, !6, i64 16, !14, i64 24, !15, i64 32, !14, i64 2352, !14, i64 2360, !6, i64 2368, !14, i64 2376, !7, i64 2384, !14, i64 2392}
!11 = !{!"", !7, i64 0, !7, i64 1, !12, i64 2, !12, i64 4, !12, i64 6}
!12 = !{!"short", !7, i64 0}
!13 = !{!"", !12, i64 0, !6, i64 4}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!"", !7, i64 0, !7, i64 4, !6, i64 388, !7, i64 392, !6, i64 2312}
!16 = !{!17, !6, i64 56}
!17 = !{!"", !14, i64 0, !14, i64 8, !14, i64 16, !14, i64 24, !14, i64 32, !14, i64 40, !14, i64 48, !6, i64 56, !6, i64 60, !14, i64 64, !7, i64 72, !6, i64 76}
!18 = !{!17, !6, i64 60}
!19 = !{!17, !14, i64 64}
!20 = !{!17, !7, i64 72}
!21 = !{!17, !14, i64 16}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass