; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (SetupADMA2DescTbl64Bit)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs_Adma2Descriptor64 = type <{ i16, i16, i64 }>
%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

@XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl = external hidden global [32 x %struct.XSdPs_Adma2Descriptor64], align 32

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.XSdPs, ptr %8, i32 0, i32 0
  %10 = getelementptr inbounds %struct.XSdPs_Config, ptr %9, i32 0, i32 1
  %11 = load i32, ptr %10, align 4, !tbaa !11
  %12 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %11, i8 noundef zeroext 4)
  %13 = zext i16 %12 to i32
  %14 = and i32 %13, 4095
  store i32 %14, ptr %7, align 4, !tbaa !9
  %15 = load i32, ptr %4, align 4, !tbaa !9
  %16 = load i32, ptr %7, align 4, !tbaa !9
  %17 = mul i32 %15, %16
  %18 = icmp ult i32 %17, 65536
  br i1 %18, label %19, label %20

19:                                               ; preds = %2
  store i32 1, ptr %5, align 4, !tbaa !9
  br label %34

20:                                               ; preds = %2
  %21 = load i32, ptr %4, align 4, !tbaa !9
  %22 = load i32, ptr %7, align 4, !tbaa !9
  %23 = mul i32 %21, %22
  %24 = udiv i32 %23, 65536
  store i32 %24, ptr %5, align 4, !tbaa !9
  %25 = load i32, ptr %4, align 4, !tbaa !9
  %26 = load i32, ptr %7, align 4, !tbaa !9
  %27 = mul i32 %25, %26
  %28 = urem i32 %27, 65536
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %33

30:                                               ; preds = %20
  %31 = load i32, ptr %5, align 4, !tbaa !9
  %32 = add i32 %31, 1
  store i32 %32, ptr %5, align 4, !tbaa !9
  br label %33

33:                                               ; preds = %30, %20
  br label %34

34:                                               ; preds = %33, %19
  store i64 0, ptr %6, align 8, !tbaa !16
  br label %35

35:                                               ; preds = %57, %34
  %36 = load i64, ptr %6, align 8, !tbaa !16
  %37 = load i32, ptr %5, align 4, !tbaa !9
  %38 = sub i32 %37, 1
  %39 = zext i32 %38 to i64
  %40 = icmp ult i64 %36, %39
  br i1 %40, label %41, label %60

41:                                               ; preds = %35
  %42 = load ptr, ptr %3, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.XSdPs, ptr %42, i32 0, i32 19
  %44 = load i64, ptr %43, align 8, !tbaa !17
  %45 = load i64, ptr %6, align 8, !tbaa !16
  %46 = mul i64 %45, 65536
  %47 = add i64 %44, %46
  %48 = load i64, ptr %6, align 8, !tbaa !16
  %49 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %48
  %50 = getelementptr inbounds %struct.XSdPs_Adma2Descriptor64, ptr %49, i32 0, i32 2
  store i64 %47, ptr %50, align 4, !tbaa !18
  %51 = load i64, ptr %6, align 8, !tbaa !16
  %52 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %51
  %53 = getelementptr inbounds %struct.XSdPs_Adma2Descriptor64, ptr %52, i32 0, i32 0
  store i16 33, ptr %53, align 4, !tbaa !20
  %54 = load i64, ptr %6, align 8, !tbaa !16
  %55 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %54
  %56 = getelementptr inbounds %struct.XSdPs_Adma2Descriptor64, ptr %55, i32 0, i32 1
  store i16 0, ptr %56, align 2, !tbaa !21
  br label %57

57:                                               ; preds = %41
  %58 = load i64, ptr %6, align 8, !tbaa !16
  %59 = add i64 %58, 1
  store i64 %59, ptr %6, align 8, !tbaa !16
  br label %35, !llvm.loop !22

60:                                               ; preds = %35
  %61 = load ptr, ptr %3, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.XSdPs, ptr %61, i32 0, i32 19
  %63 = load i64, ptr %62, align 8, !tbaa !17
  %64 = load i64, ptr %6, align 8, !tbaa !16
  %65 = mul i64 %64, 65536
  %66 = add i64 %63, %65
  %67 = load i32, ptr %5, align 4, !tbaa !9
  %68 = sub i32 %67, 1
  %69 = zext i32 %68 to i64
  %70 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %69
  %71 = getelementptr inbounds %struct.XSdPs_Adma2Descriptor64, ptr %70, i32 0, i32 2
  store i64 %66, ptr %71, align 4, !tbaa !18
  %72 = load i32, ptr %5, align 4, !tbaa !9
  %73 = sub i32 %72, 1
  %74 = zext i32 %73 to i64
  %75 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %74
  %76 = getelementptr inbounds %struct.XSdPs_Adma2Descriptor64, ptr %75, i32 0, i32 0
  store i16 35, ptr %76, align 4, !tbaa !20
  %77 = load i32, ptr %4, align 4, !tbaa !9
  %78 = load i32, ptr %7, align 4, !tbaa !9
  %79 = mul i32 %77, %78
  %80 = load i64, ptr %6, align 8, !tbaa !16
  %81 = mul i64 %80, 65536
  %82 = trunc i64 %81 to i32
  %83 = sub i32 %79, %82
  %84 = trunc i32 %83 to i16
  %85 = load i32, ptr %5, align 4, !tbaa !9
  %86 = sub i32 %85, 1
  %87 = zext i32 %86 to i64
  %88 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %87
  %89 = getelementptr inbounds %struct.XSdPs_Adma2Descriptor64, ptr %88, i32 0, i32 1
  store i16 %84, ptr %89, align 2, !tbaa !21
  %90 = load ptr, ptr %3, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.XSdPs, ptr %90, i32 0, i32 0
  %92 = getelementptr inbounds %struct.XSdPs_Config, ptr %91, i32 0, i32 1
  %93 = load i32, ptr %92, align 4, !tbaa !11
  %94 = add i32 %93, 88
  %95 = zext i32 %94 to i64
  %96 = and i64 ptrtoint (ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl to i64), 4294967295
  %97 = trunc i64 %96 to i32
  call void @Xil_Out32(i64 noundef %95, i32 noundef %97)
  %98 = load ptr, ptr %3, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.XSdPs, ptr %98, i32 0, i32 0
  %100 = getelementptr inbounds %struct.XSdPs_Config, ptr %99, i32 0, i32 8
  %101 = load i8, ptr %100, align 8, !tbaa !24
  %102 = zext i8 %101 to i32
  %103 = icmp eq i32 %102, 0
  br i1 %103, label %104, label %105

104:                                              ; preds = %60
  call void @Xil_DCacheFlushRange(i64 noundef ptrtoint (ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl to i64), i32 noundef 384)
  br label %105

105:                                              ; preds = %104, %60
  %106 = load ptr, ptr %3, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.XSdPs, ptr %106, i32 0, i32 19
  store i64 0, ptr %107, align 8, !tbaa !17
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

declare void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !15, i64 120, !14, i64 128, !10, i64 132, !7, i64 136, !10, i64 140}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!15, !15, i64 0}
!17 = !{!12, !15, i64 120}
!18 = !{!19, !15, i64 4}
!19 = !{!"", !14, i64 0, !14, i64 2, !15, i64 4}
!20 = !{!19, !14, i64 0}
!21 = !{!19, !14, i64 2}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}
!24 = !{!12, !7, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs_Adma2Descriptor64 = type <{ i16, i16, i64 }>

@XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl = external hidden global [32 x %struct.XSdPs_Adma2Descriptor64], align 32

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @XSdPs_SetupADMA2DescTbl64Bit(ptr nocapture noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = getelementptr inbounds i8, ptr %0, i64 4
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %4, i8 noundef zeroext 4)
  %6 = and i16 %5, 4095
  %7 = zext nneg i16 %6 to i32
  %8 = mul i32 %7, %1
  %9 = icmp ult i32 %8, 65536
  br i1 %9, label %.._crit_edge_crit_edge, label %10

10:                                               ; preds = %2
  %11 = lshr i32 %8, 16
  %12 = and i32 %8, 65535
  %.not = icmp ne i32 %12, 0
  %13 = zext i1 %.not to i32
  %spec.select = add nsw i32 %11, -1
  %14 = add nuw nsw i32 %spec.select, %13
  %15 = zext i32 %14 to i64
  %.not30 = icmp eq i32 %14, 0
  br i1 %.not30, label %.._crit_edge_crit_edge, label %.lr.ph

.._crit_edge_crit_edge:                           ; preds = %2, %10
  %.phi.trans.insert = getelementptr inbounds i8, ptr %0, i64 120
  %.pre = load i64, ptr %.phi.trans.insert, align 8, !tbaa !13
  br label %._crit_edge

.lr.ph:                                           ; preds = %10
  %16 = getelementptr inbounds i8, ptr %0, i64 120
  %17 = load i64, ptr %16, align 8, !tbaa !13
  %xtraiter = and i64 %15, 1
  %18 = icmp eq i32 %14, 1
  br i1 %18, label %._crit_edge.loopexit.unr-lcssa, label %.lr.ph.new

.lr.ph.new:                                       ; preds = %.lr.ph
  %unroll_iter = and i64 %15, 4294967294
  br label %19

19:                                               ; preds = %19, %.lr.ph.new
  %.02629 = phi i64 [ 0, %.lr.ph.new ], [ %31, %19 ]
  %niter = phi i64 [ 0, %.lr.ph.new ], [ %niter.next.1, %19 ]
  %20 = shl nuw nsw i64 %.02629, 16
  %21 = add i64 %17, %20
  %22 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %.02629
  %23 = getelementptr inbounds i8, ptr %22, i64 4
  store i64 %21, ptr %23, align 4, !tbaa !14
  store i16 33, ptr %22, align 8, !tbaa !16
  %24 = getelementptr inbounds i8, ptr %22, i64 2
  store i16 0, ptr %24, align 2, !tbaa !17
  %25 = or disjoint i64 %.02629, 1
  %26 = shl nuw nsw i64 %25, 16
  %27 = add i64 %17, %26
  %28 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %25
  %29 = getelementptr inbounds i8, ptr %28, i64 4
  store i64 %27, ptr %29, align 8, !tbaa !14
  store i16 33, ptr %28, align 4, !tbaa !16
  %30 = getelementptr inbounds i8, ptr %28, i64 2
  store i16 0, ptr %30, align 2, !tbaa !17
  %31 = add nuw nsw i64 %.02629, 2
  %niter.next.1 = add i64 %niter, 2
  %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
  br i1 %niter.ncmp.1, label %._crit_edge.loopexit.unr-lcssa, label %19, !llvm.loop !18

._crit_edge.loopexit.unr-lcssa:                   ; preds = %19, %.lr.ph
  %.02629.unr = phi i64 [ 0, %.lr.ph ], [ %31, %19 ]
  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
  br i1 %lcmp.mod.not, label %._crit_edge.loopexit, label %._crit_edge.loopexit.epilog-lcssa

._crit_edge.loopexit.epilog-lcssa:                ; preds = %._crit_edge.loopexit.unr-lcssa
  %32 = shl nuw nsw i64 %.02629.unr, 16
  %33 = add i64 %17, %32
  %34 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %.02629.unr
  %35 = getelementptr inbounds i8, ptr %34, i64 4
  store i64 %33, ptr %35, align 4, !tbaa !14
  store i16 33, ptr %34, align 4, !tbaa !16
  %36 = getelementptr inbounds i8, ptr %34, i64 2
  store i16 0, ptr %36, align 2, !tbaa !17
  br label %._crit_edge.loopexit

._crit_edge.loopexit:                             ; preds = %._crit_edge.loopexit.unr-lcssa, %._crit_edge.loopexit.epilog-lcssa
  %37 = shl nuw nsw i64 %15, 16
  br label %._crit_edge

._crit_edge:                                      ; preds = %.._crit_edge_crit_edge, %._crit_edge.loopexit
  %.033 = phi i64 [ 0, %.._crit_edge_crit_edge ], [ %15, %._crit_edge.loopexit ]
  %38 = phi i64 [ %.pre, %.._crit_edge_crit_edge ], [ %17, %._crit_edge.loopexit ]
  %.026.lcssa = phi i64 [ 0, %.._crit_edge_crit_edge ], [ %37, %._crit_edge.loopexit ]
  %39 = add i64 %38, %.026.lcssa
  %40 = getelementptr inbounds [32 x %struct.XSdPs_Adma2Descriptor64], ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl, i64 0, i64 %.033
  %41 = getelementptr inbounds i8, ptr %40, i64 4
  store i64 %39, ptr %41, align 4, !tbaa !14
  store i16 35, ptr %40, align 4, !tbaa !16
  %42 = trunc i32 %8 to i16
  %43 = getelementptr inbounds i8, ptr %40, i64 2
  store i16 %42, ptr %43, align 2, !tbaa !17
  %44 = load i32, ptr %3, align 4, !tbaa !5
  %45 = add i32 %44, 88
  %46 = zext i32 %45 to i64
  tail call void @Xil_Out32(i64 noundef %46, i32 noundef ptrtoint (ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl to i32))
  %47 = getelementptr inbounds i8, ptr %0, i64 32
  %48 = load i8, ptr %47, align 8, !tbaa !20
  %49 = icmp eq i8 %48, 0
  br i1 %49, label %50, label %51

50:                                               ; preds = %._crit_edge
  tail call void @Xil_DCacheFlushRange(i64 noundef ptrtoint (ptr @XSdPs_SetupADMA2DescTbl64Bit.Adma2_DescrTbl to i64), i32 noundef 384) #3
  br label %51

51:                                               ; preds = %50, %._crit_edge
  %52 = getelementptr inbounds i8, ptr %0, i64 120
  store i64 0, ptr %52, align 8, !tbaa !13
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 4}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = !{!6, !12, i64 120}
!14 = !{!15, !12, i64 4}
!15 = !{!"", !8, i64 0, !8, i64 2, !12, i64 4}
!16 = !{!15, !8, i64 0}
!17 = !{!15, !8, i64 2}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{!6, !9, i64 32}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass