; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (DCacheInvalidateRange)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheInvalidateRange(i64 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i64, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %12 = load i64, ptr %3, align 8, !tbaa !5
  %13 = trunc i64 %12 to i32
  store i32 %13, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !9
  %14 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !11
  store i32 %14, ptr %10, align 4, !tbaa !9
  %15 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %15, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %16 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %16, ptr %9, align 4, !tbaa !9
  %17 = load i32, ptr %9, align 4, !tbaa !9
  %18 = or i32 %17, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %18) #2, !srcloc !12
  %19 = load i32, ptr %4, align 4, !tbaa !9
  %20 = icmp ne i32 %19, 0
  br i1 %20, label %21, label %53

21:                                               ; preds = %2
  %22 = load i32, ptr %7, align 4, !tbaa !9
  %23 = load i32, ptr %4, align 4, !tbaa !9
  %24 = add i32 %22, %23
  store i32 %24, ptr %6, align 4, !tbaa !9
  %25 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %25, ptr %8, align 4, !tbaa !9
  call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #2, !srcloc !13
  %26 = load i32, ptr %7, align 4, !tbaa !9
  %27 = and i32 %26, 31
  %28 = icmp ne i32 %27, 0
  br i1 %28, label %29, label %34

29:                                               ; preds = %21
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = and i32 %30, -32
  store i32 %31, ptr %7, align 4, !tbaa !9
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = zext i32 %32 to i64
  call void @Xil_DCacheFlushLine(i64 noundef %33)
  br label %34

34:                                               ; preds = %29, %21
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = and i32 %35, 31
  %37 = icmp ne i32 %36, 0
  br i1 %37, label %38, label %43

38:                                               ; preds = %34
  %39 = load i32, ptr %8, align 4, !tbaa !9
  %40 = and i32 %39, -32
  store i32 %40, ptr %8, align 4, !tbaa !9
  %41 = load i32, ptr %8, align 4, !tbaa !9
  %42 = zext i32 %41 to i64
  call void @Xil_DCacheFlushLine(i64 noundef %42)
  br label %43

43:                                               ; preds = %38, %34
  br label %44

44:                                               ; preds = %48, %43
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = load i32, ptr %8, align 4, !tbaa !9
  %47 = icmp ult i32 %45, %46
  br i1 %47, label %48, label %52

48:                                               ; preds = %44
  %49 = load i32, ptr %7, align 4, !tbaa !9
  call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 1", "r,~{dirflag},~{fpsr},~{flags}"(i32 %49) #2, !srcloc !14
  %50 = load i32, ptr %7, align 4, !tbaa !9
  %51 = add i32 %50, 32
  store i32 %51, ptr %7, align 4, !tbaa !9
  br label %44, !llvm.loop !15

52:                                               ; preds = %44
  br label %53

53:                                               ; preds = %52, %2
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !17
  %54 = load i32, ptr %9, align 4, !tbaa !9
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %54) #2, !srcloc !18
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushLine(i64 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{i64 2147861239}
!12 = !{i64 2147861335}
!13 = !{i64 2147861431}
!14 = !{i64 2147861546}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = !{i64 2147861661}
!18 = !{i64 2147861711}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheInvalidateRange(i64 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = trunc i64 %0 to i32
  %4 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !5
  %5 = or i32 %4, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %5) #1, !srcloc !6
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %.loopexit, label %6

6:                                                ; preds = %2
  %7 = add i32 %3, %1
  tail call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #1, !srcloc !7
  %8 = and i32 %3, 31
  %.not21 = icmp eq i32 %8, 0
  br i1 %.not21, label %12, label %9

9:                                                ; preds = %6
  %10 = and i32 %3, -32
  %11 = and i64 %0, 4294967264
  tail call void @Xil_DCacheFlushLine(i64 noundef %11)
  br label %12

12:                                               ; preds = %9, %6
  %.0 = phi i32 [ %10, %9 ], [ %3, %6 ]
  %13 = and i32 %7, 31
  %.not22 = icmp eq i32 %13, 0
  br i1 %.not22, label %17, label %14

14:                                               ; preds = %12
  %15 = and i32 %7, -32
  %16 = zext i32 %15 to i64
  tail call void @Xil_DCacheFlushLine(i64 noundef %16)
  br label %17

17:                                               ; preds = %14, %12
  %.019 = phi i32 [ %15, %14 ], [ %7, %12 ]
  %18 = icmp ult i32 %.0, %.019
  br i1 %18, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %17, %.lr.ph
  %.123 = phi i32 [ %19, %.lr.ph ], [ %.0, %17 ]
  tail call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 1", "r,~{dirflag},~{fpsr},~{flags}"(i32 %.123) #1, !srcloc !8
  %19 = add i32 %.123, 32
  %20 = icmp ult i32 %19, %.019
  br i1 %20, label %.lr.ph, label %.loopexit, !llvm.loop !9

.loopexit:                                        ; preds = %.lr.ph, %17, %2
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !11
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %4) #1, !srcloc !12
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushLine(i64 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147861239}
!6 = !{i64 2147861335}
!7 = !{i64 2147861431}
!8 = !{i64 2147861546}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{i64 2147861661}
!12 = !{i64 2147861711}


; Effective O3 passes: GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass