; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (SetDirectionPin)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8, i32 }
%struct.XGpioPs_Config = type { i16, i64 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_SetDirectionPin(ptr noundef %0, i32 noundef %1, i32 noundef %2) #3 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = icmp ne ptr %11, null
  br i1 %12, label %13, label %14

13:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %15

14:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 405)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %76

15:                                               ; preds = %13
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.XGpioPs, ptr %16, i32 0, i32 1
  %18 = load i32, ptr %17, align 8, !tbaa !11
  %19 = icmp eq i32 %18, 286331153
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %22

21:                                               ; preds = %15
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 406)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %76

22:                                               ; preds = %20
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XGpioPs, ptr %24, i32 0, i32 5
  %26 = load i32, ptr %25, align 4, !tbaa !16
  %27 = icmp ult i32 %23, %26
  br i1 %27, label %28, label %29

28:                                               ; preds = %22
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %30

29:                                               ; preds = %22
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 407)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %76

30:                                               ; preds = %28
  %31 = load i32, ptr %6, align 4, !tbaa !9
  %32 = icmp ule i32 %31, 1
  br i1 %32, label %33, label %34

33:                                               ; preds = %30
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %35

34:                                               ; preds = %30
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 408)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %76

35:                                               ; preds = %33
  %36 = load i32, ptr %5, align 4, !tbaa !9
  %37 = trunc i32 %36 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %37, ptr noundef %7, ptr noundef %8)
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.XGpioPs, ptr %38, i32 0, i32 0
  %40 = getelementptr inbounds %struct.XGpioPs_Config, ptr %39, i32 0, i32 1
  %41 = load i64, ptr %40, align 8, !tbaa !17
  %42 = load i8, ptr %7, align 1, !tbaa !18
  %43 = zext i8 %42 to i32
  %44 = mul i32 %43, 64
  %45 = add i32 %44, 516
  %46 = zext i32 %45 to i64
  %47 = add i64 %41, %46
  %48 = call i32 @Xil_In32(i64 noundef %47)
  store i32 %48, ptr %9, align 4, !tbaa !9
  %49 = load i32, ptr %6, align 4, !tbaa !9
  %50 = icmp ne i32 %49, 0
  br i1 %50, label %51, label %57

51:                                               ; preds = %35
  %52 = load i8, ptr %8, align 1, !tbaa !18
  %53 = zext i8 %52 to i32
  %54 = shl i32 1, %53
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = or i32 %55, %54
  store i32 %56, ptr %9, align 4, !tbaa !9
  br label %64

57:                                               ; preds = %35
  %58 = load i8, ptr %8, align 1, !tbaa !18
  %59 = zext i8 %58 to i32
  %60 = shl i32 1, %59
  %61 = xor i32 %60, -1
  %62 = load i32, ptr %9, align 4, !tbaa !9
  %63 = and i32 %62, %61
  store i32 %63, ptr %9, align 4, !tbaa !9
  br label %64

64:                                               ; preds = %57, %51
  %65 = load ptr, ptr %4, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.XGpioPs, ptr %65, i32 0, i32 0
  %67 = getelementptr inbounds %struct.XGpioPs_Config, ptr %66, i32 0, i32 1
  %68 = load i64, ptr %67, align 8, !tbaa !17
  %69 = load i8, ptr %7, align 1, !tbaa !18
  %70 = zext i8 %69 to i32
  %71 = mul i32 %70, 64
  %72 = add i32 %71, 516
  %73 = zext i32 %72 to i64
  %74 = add i64 %68, %73
  %75 = load i32, ptr %9, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %74, i32 noundef %75)
  store i32 0, ptr %10, align 4
  br label %76

76:                                               ; preds = %64, %34, %29, %21, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #4
  %77 = load i32, ptr %10, align 4
  switch i32 %77, label %79 [
    i32 0, label %78
    i32 1, label %78
  ]

78:                                               ; preds = %76, %76
  ret void

79:                                               ; preds = %76
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"", !13, i64 0, !10, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 44, !7, i64 48, !10, i64 52}
!13 = !{!"", !14, i64 0, !15, i64 8}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !10, i64 44}
!17 = !{!12, !15, i64 8}
!18 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_SetDirectionPin(ptr noundef readonly %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #3 {
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #4
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %10, label %6

6:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 16
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp eq i32 %8, 286331153
  br i1 %9, label %11, label %15

10:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 405) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

11:                                               ; preds = %6
  %12 = getelementptr inbounds i8, ptr %0, i64 44
  %13 = load i32, ptr %12, align 4, !tbaa !15
  %14 = icmp ugt i32 %13, %1
  br i1 %14, label %16, label %18

15:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 406) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

16:                                               ; preds = %11
  %17 = icmp ult i32 %2, 2
  br i1 %17, label %19, label %41

18:                                               ; preds = %11
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 407) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

19:                                               ; preds = %16
  %20 = trunc i32 %1 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %20, ptr noundef nonnull %4, ptr noundef nonnull %5)
  %21 = getelementptr inbounds i8, ptr %0, i64 8
  %22 = load i64, ptr %21, align 8, !tbaa !16
  %23 = load i8, ptr %4, align 1, !tbaa !17
  %24 = zext i8 %23 to i64
  %25 = shl nuw nsw i64 %24, 6
  %26 = add i64 %22, 516
  %27 = add i64 %26, %25
  %28 = call i32 @Xil_In32(i64 noundef %27)
  %.not14 = icmp eq i32 %2, 0
  %29 = load i8, ptr %5, align 1, !tbaa !17
  %30 = zext nneg i8 %29 to i32
  %31 = shl nuw i32 1, %30
  %32 = or i32 %31, %28
  %33 = xor i32 %31, -1
  %34 = and i32 %28, %33
  %.0 = select i1 %.not14, i32 %34, i32 %32
  %35 = load i64, ptr %21, align 8, !tbaa !16
  %36 = load i8, ptr %4, align 1, !tbaa !17
  %37 = zext i8 %36 to i64
  %38 = shl nuw nsw i64 %37, 6
  %39 = add i64 %35, 516
  %40 = add i64 %39, %38
  call void @Xil_Out32(i64 noundef %40, i32 noundef %.0)
  br label %42

41:                                               ; preds = %16
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 408) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

42:                                               ; preds = %19, %41, %18, %15, %10
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #4
  ret void
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 16}
!10 = !{!"", !11, i64 0, !6, i64 16, !14, i64 24, !14, i64 32, !6, i64 40, !6, i64 44, !7, i64 48, !6, i64 52}
!11 = !{!"", !12, i64 0, !13, i64 8}
!12 = !{!"short", !7, i64 0}
!13 = !{!"long", !7, i64 0}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!10, !6, i64 44}
!16 = !{!10, !13, i64 8}
!17 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass