; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (MmcCardInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_MmcCardInitialize(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = call i32 @XSdPs_MmcCardEnum(ptr noundef %4)
  store i32 %5, ptr %3, align 4, !tbaa !9
  %6 = load i32, ptr %3, align 4, !tbaa !9
  %7 = sext i32 %6 to i64
  %8 = icmp ne i64 %7, 0
  br i1 %8, label %9, label %10

9:                                                ; preds = %1
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %73

10:                                               ; preds = %1
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.XSdPs, ptr %11, i32 0, i32 5
  %13 = load i8, ptr %12, align 4, !tbaa !11
  %14 = zext i8 %13 to i32
  %15 = icmp eq i32 %14, 2
  br i1 %15, label %16, label %36

16:                                               ; preds = %10
  %17 = load ptr, ptr %2, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.XSdPs, ptr %17, i32 0, i32 6
  %19 = load i8, ptr %18, align 1, !tbaa !16
  %20 = zext i8 %19 to i32
  %21 = icmp ugt i32 %20, 3
  br i1 %21, label %22, label %36

22:                                               ; preds = %16
  %23 = load ptr, ptr %2, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.XSdPs, ptr %23, i32 0, i32 7
  %25 = load i8, ptr %24, align 2, !tbaa !17
  %26 = zext i8 %25 to i32
  %27 = icmp eq i32 %26, 1
  br i1 %27, label %28, label %36

28:                                               ; preds = %22
  %29 = load ptr, ptr %2, align 8, !tbaa !5
  %30 = call i32 @XSdPs_MmcModeInit(ptr noundef %29)
  store i32 %30, ptr %3, align 4, !tbaa !9
  %31 = load i32, ptr %3, align 4, !tbaa !9
  %32 = sext i32 %31 to i64
  %33 = icmp ne i64 %32, 0
  br i1 %33, label %34, label %35

34:                                               ; preds = %28
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %73

35:                                               ; preds = %28
  br label %52

36:                                               ; preds = %22, %16, %10
  %37 = load ptr, ptr %2, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.XSdPs, ptr %37, i32 0, i32 5
  %39 = load i8, ptr %38, align 4, !tbaa !11
  %40 = zext i8 %39 to i32
  %41 = icmp eq i32 %40, 5
  br i1 %41, label %42, label %50

42:                                               ; preds = %36
  %43 = load ptr, ptr %2, align 8, !tbaa !5
  %44 = call i32 @XSdPs_EmmcModeInit(ptr noundef %43)
  store i32 %44, ptr %3, align 4, !tbaa !9
  %45 = load i32, ptr %3, align 4, !tbaa !9
  %46 = sext i32 %45 to i64
  %47 = icmp ne i64 %46, 0
  br i1 %47, label %48, label %49

48:                                               ; preds = %42
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %73

49:                                               ; preds = %42
  br label %51

50:                                               ; preds = %36
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %73

51:                                               ; preds = %49
  br label %52

52:                                               ; preds = %51, %35
  %53 = load ptr, ptr %2, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.XSdPs, ptr %53, i32 0, i32 16
  %55 = load i32, ptr %54, align 4, !tbaa !18
  %56 = icmp ne i32 %55, 4
  br i1 %56, label %57, label %65

57:                                               ; preds = %52
  %58 = load ptr, ptr %2, align 8, !tbaa !5
  %59 = call i32 @XSdPs_SetBlkSize(ptr noundef %58, i16 noundef zeroext 512)
  store i32 %59, ptr %3, align 4, !tbaa !9
  %60 = load i32, ptr %3, align 4, !tbaa !9
  %61 = sext i32 %60 to i64
  %62 = icmp ne i64 %61, 0
  br i1 %62, label %63, label %64

63:                                               ; preds = %57
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %73

64:                                               ; preds = %57
  br label %72

65:                                               ; preds = %52
  %66 = load ptr, ptr %2, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.XSdPs, ptr %66, i32 0, i32 0
  %68 = getelementptr inbounds %struct.XSdPs_Config, ptr %67, i32 0, i32 1
  %69 = load i32, ptr %68, align 4, !tbaa !19
  call void @XSdPs_WriteReg16(i32 noundef %69, i8 noundef zeroext 4, i16 noundef zeroext 512)
  %70 = load ptr, ptr %2, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.XSdPs, ptr %70, i32 0, i32 23
  store i32 512, ptr %71, align 4, !tbaa !20
  br label %72

72:                                               ; preds = %65, %64
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %73

73:                                               ; preds = %72, %63, %50, %48, %34, %9
  %74 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret i32 %74
}

declare i32 @XSdPs_MmcCardEnum(ptr noundef) #3

declare i32 @XSdPs_MmcModeInit(ptr noundef) #3

declare i32 @XSdPs_EmmcModeInit(ptr noundef) #3

declare i32 @XSdPs_SetBlkSize(ptr noundef, i16 noundef zeroext) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 52}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !15, i64 120, !14, i64 128, !10, i64 132, !7, i64 136, !10, i64 140}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !7, i64 53}
!17 = !{!12, !7, i64 54}
!18 = !{!12, !10, i64 108}
!19 = !{!12, !10, i64 4}
!20 = !{!12, !10, i64 140}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_MmcCardInitialize(ptr noundef %0) local_unnamed_addr #1 {
  %2 = tail call i32 @XSdPs_MmcCardEnum(ptr noundef %0) #3
  %.not = icmp eq i32 %2, 0
  br i1 %.not, label %3, label %.thread

3:                                                ; preds = %1
  %4 = getelementptr inbounds i8, ptr %0, i64 52
  %5 = load i8, ptr %4, align 4, !tbaa !5
  switch i8 %5, label %.thread [
    i8 2, label %6
    i8 5, label %16
  ]

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 53
  %8 = load i8, ptr %7, align 1, !tbaa !13
  %9 = icmp ugt i8 %8, 3
  br i1 %9, label %10, label %.thread

10:                                               ; preds = %6
  %11 = getelementptr inbounds i8, ptr %0, i64 54
  %12 = load i8, ptr %11, align 2, !tbaa !14
  %13 = icmp eq i8 %12, 1
  br i1 %13, label %14, label %.thread

14:                                               ; preds = %10
  %15 = tail call i32 @XSdPs_MmcModeInit(ptr noundef nonnull %0) #3
  %.not16 = icmp eq i32 %15, 0
  br i1 %.not16, label %18, label %.thread

16:                                               ; preds = %3
  %17 = tail call i32 @XSdPs_EmmcModeInit(ptr noundef nonnull %0) #3
  %.not15 = icmp eq i32 %17, 0
  br i1 %.not15, label %18, label %.thread

18:                                               ; preds = %16, %14
  %19 = getelementptr inbounds i8, ptr %0, i64 108
  %20 = load i32, ptr %19, align 4, !tbaa !15
  %.not17 = icmp eq i32 %20, 4
  br i1 %.not17, label %23, label %21

21:                                               ; preds = %18
  %22 = tail call i32 @XSdPs_SetBlkSize(ptr noundef nonnull %0, i16 noundef zeroext 512) #3
  %.not18 = icmp eq i32 %22, 0
  br i1 %.not18, label %27, label %.thread

23:                                               ; preds = %18
  %24 = getelementptr inbounds i8, ptr %0, i64 4
  %25 = load i32, ptr %24, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %25, i8 noundef zeroext 4, i16 noundef zeroext 512)
  %26 = getelementptr inbounds i8, ptr %0, i64 140
  store i32 512, ptr %26, align 4, !tbaa !17
  br label %27

27:                                               ; preds = %21, %23
  br label %.thread

.thread:                                          ; preds = %3, %6, %10, %21, %16, %14, %1, %27
  %.0 = phi i32 [ 0, %27 ], [ 1, %1 ], [ 1, %14 ], [ 1, %16 ], [ 1, %21 ], [ 1, %10 ], [ 1, %6 ], [ 1, %3 ]
  ret i32 %.0
}

declare i32 @XSdPs_MmcCardEnum(ptr noundef) local_unnamed_addr #2

declare i32 @XSdPs_MmcModeInit(ptr noundef) local_unnamed_addr #2

declare i32 @XSdPs_EmmcModeInit(ptr noundef) local_unnamed_addr #2

declare i32 @XSdPs_SetBlkSize(ptr noundef, i16 noundef zeroext) local_unnamed_addr #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 52}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = !{!6, !9, i64 53}
!14 = !{!6, !9, i64 54}
!15 = !{!6, !11, i64 108}
!16 = !{!6, !11, i64 4}
!17 = !{!6, !11, i64 140}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass