; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (Status)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [169 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @XSdPs_SetupReadDma(ptr noundef, i16 noundef zeroext, i16 noundef zeroext, ptr noundef) #1

declare i32 @XSdps_CheckTransferDone(ptr noundef) #1

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_Get_Status(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i16, align 2
  %8 = alloca i16, align 2
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #3
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %14

13:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 415)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %70

14:                                               ; preds = %12
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.XSdPs, ptr %15, i32 0, i32 1
  %17 = load i32, ptr %16, align 4, !tbaa !11
  %18 = icmp eq i32 %17, 286331153
  br i1 %18, label %19, label %20

19:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %21

20:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 416)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %70

21:                                               ; preds = %19
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.XSdPs, ptr %23, i32 0, i32 12
  %25 = load i32, ptr %24, align 8, !tbaa !16
  %26 = call i32 @XSdPs_CmdTransfer(ptr noundef %22, i32 noundef 14080, i32 noundef %25, i32 noundef 0)
  store i32 %26, ptr %6, align 4, !tbaa !9
  %27 = load i32, ptr %6, align 4, !tbaa !9
  %28 = sext i32 %27 to i64
  %29 = icmp ne i64 %28, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %21
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %68

31:                                               ; preds = %21
  store i16 1, ptr %7, align 2, !tbaa !17
  store i16 64, ptr %8, align 2, !tbaa !17
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = load i16, ptr %7, align 2, !tbaa !17
  %34 = load i16, ptr %8, align 2, !tbaa !17
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  call void @XSdPs_SetupReadDma(ptr noundef %32, i16 noundef zeroext %33, i16 noundef zeroext %34, ptr noundef %35)
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = load i16, ptr %7, align 2, !tbaa !17
  %38 = zext i16 %37 to i32
  %39 = call i32 @XSdPs_CmdTransfer(ptr noundef %36, i32 noundef 36096, i32 noundef 0, i32 noundef %38)
  store i32 %39, ptr %6, align 4, !tbaa !9
  %40 = load i32, ptr %6, align 4, !tbaa !9
  %41 = sext i32 %40 to i64
  %42 = icmp ne i64 %41, 0
  br i1 %42, label %43, label %44

43:                                               ; preds = %31
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %68

44:                                               ; preds = %31
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  %46 = call i32 @XSdps_CheckTransferDone(ptr noundef %45)
  store i32 %46, ptr %6, align 4, !tbaa !9
  %47 = load i32, ptr %6, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = icmp ne i64 %48, 0
  br i1 %49, label %50, label %51

50:                                               ; preds = %44
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %51

51:                                               ; preds = %50, %44
  %52 = load ptr, ptr %4, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.XSdPs, ptr %52, i32 0, i32 0
  %54 = getelementptr inbounds %struct.XSdPs_Config, ptr %53, i32 0, i32 8
  %55 = load i8, ptr %54, align 8, !tbaa !18
  %56 = zext i8 %55 to i32
  %57 = icmp eq i32 %56, 0
  br i1 %57, label %58, label %67

58:                                               ; preds = %51
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = ptrtoint ptr %59 to i64
  %61 = load i16, ptr %7, align 2, !tbaa !17
  %62 = zext i16 %61 to i64
  %63 = load i16, ptr %8, align 2, !tbaa !17
  %64 = zext i16 %63 to i64
  %65 = mul nsw i64 %62, %64
  %66 = trunc i64 %65 to i32
  call void @Xil_DCacheInvalidateRange(i64 noundef %60, i32 noundef %66)
  br label %67

67:                                               ; preds = %58, %51
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %67, %43, %30
  %69 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %69, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %70

70:                                               ; preds = %68, %20, %13
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %71 = load i32, ptr %3, align 4
  ret i32 %71
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 36}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !15, i64 120, !14, i64 128, !10, i64 132, !7, i64 136, !10, i64 140}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !10, i64 80}
!17 = !{!14, !14, i64 0}
!18 = !{!12, !7, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [169 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @XSdPs_SetupReadDma(ptr noundef, i16 noundef zeroext, i16 noundef zeroext, ptr noundef) local_unnamed_addr #0

declare i32 @XSdps_CheckTransferDone(ptr noundef) local_unnamed_addr #0

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_Get_Status(ptr noundef %0, ptr noundef %1) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 36
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %12

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 415) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %22

8:                                                ; preds = %3
  %9 = getelementptr inbounds i8, ptr %0, i64 80
  %10 = load i32, ptr %9, align 8, !tbaa !14
  %11 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 14080, i32 noundef %10, i32 noundef 0) #2
  %.not21 = icmp eq i32 %11, 0
  br i1 %.not21, label %13, label %22

12:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 416) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %22

13:                                               ; preds = %8
  tail call void @XSdPs_SetupReadDma(ptr noundef nonnull %0, i16 noundef zeroext 1, i16 noundef zeroext 64, ptr noundef %1) #2
  %14 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 36096, i32 noundef 0, i32 noundef 1) #2
  %.not22 = icmp eq i32 %14, 0
  br i1 %.not22, label %15, label %22

15:                                               ; preds = %13
  %16 = tail call i32 @XSdps_CheckTransferDone(ptr noundef nonnull %0) #2
  %17 = getelementptr inbounds i8, ptr %0, i64 32
  %18 = load i8, ptr %17, align 8, !tbaa !15
  %19 = icmp eq i8 %18, 0
  br i1 %19, label %20, label %22

20:                                               ; preds = %15
  %21 = ptrtoint ptr %1 to i64
  tail call void @Xil_DCacheInvalidateRange(i64 noundef %21, i32 noundef 64) #2
  br label %22

22:                                               ; preds = %8, %13, %20, %15, %12, %7
  %.0 = phi i32 [ 0, %12 ], [ 0, %7 ], [ 1, %8 ], [ 1, %13 ], [ 0, %20 ], [ 0, %15 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 36}
!10 = !{!"", !11, i64 0, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !6, i64 56, !7, i64 60, !7, i64 64, !6, i64 80, !7, i64 84, !6, i64 100, !6, i64 104, !6, i64 108, !6, i64 112, !6, i64 116, !13, i64 120, !12, i64 128, !6, i64 132, !7, i64 136, !6, i64 140}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"long", !7, i64 0}
!14 = !{!10, !6, i64 80}
!15 = !{!10, !7, i64 32}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass