; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (DCacheFlush)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheFlush() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  store i32 0, ptr %14, align 4, !tbaa !5
  %20 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !9
  store i32 %20, ptr %14, align 4, !tbaa !5
  %21 = load i32, ptr %14, align 4, !tbaa !5
  store i32 %21, ptr %15, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  %22 = load i32, ptr %15, align 4, !tbaa !5
  store i32 %22, ptr %13, align 4, !tbaa !5
  %23 = load i32, ptr %13, align 4, !tbaa !5
  %24 = or i32 %23, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %24) #2, !srcloc !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  store i32 0, ptr %16, align 4, !tbaa !5
  %25 = call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 1\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !11
  store i32 %25, ptr %16, align 4, !tbaa !5
  %26 = load i32, ptr %16, align 4, !tbaa !5
  store i32 %26, ptr %17, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  %27 = load i32, ptr %17, align 4, !tbaa !5
  %28 = lshr i32 %27, 24
  %29 = and i32 %28, 7
  store i32 %29, ptr %11, align 4, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !5
  store i32 30, ptr %7, align 4, !tbaa !5
  br label %30

30:                                               ; preds = %87, %0
  %31 = load i32, ptr %12, align 4, !tbaa !5
  %32 = load i32, ptr %11, align 4, !tbaa !5
  %33 = icmp ult i32 %31, %32
  br i1 %33, label %34, label %92

34:                                               ; preds = %30
  %35 = load i32, ptr %12, align 4, !tbaa !5
  %36 = shl i32 %35, 1
  %37 = or i32 %36, 0
  call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %37) #2, !srcloc !12
  call void asm sideeffect "isb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #2
  store i32 0, ptr %18, align 4, !tbaa !5
  %38 = call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !14
  store i32 %38, ptr %18, align 4, !tbaa !5
  %39 = load i32, ptr %18, align 4, !tbaa !5
  store i32 %39, ptr %19, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #2
  %40 = load i32, ptr %19, align 4, !tbaa !5
  store i32 %40, ptr %1, align 4, !tbaa !5
  %41 = load i32, ptr %1, align 4, !tbaa !5
  %42 = and i32 %41, 7
  %43 = add i32 %42, 4
  store i32 %43, ptr %3, align 4, !tbaa !5
  %44 = load i32, ptr %1, align 4, !tbaa !5
  %45 = and i32 %44, 8191
  %46 = lshr i32 %45, 3
  store i32 %46, ptr %4, align 4, !tbaa !5
  %47 = load i32, ptr %4, align 4, !tbaa !5
  %48 = add i32 %47, 1
  store i32 %48, ptr %4, align 4, !tbaa !5
  %49 = load i32, ptr %1, align 4, !tbaa !5
  %50 = lshr i32 %49, 13
  %51 = and i32 %50, 32767
  store i32 %51, ptr %10, align 4, !tbaa !5
  %52 = load i32, ptr %10, align 4, !tbaa !5
  %53 = add i32 %52, 1
  store i32 %53, ptr %10, align 4, !tbaa !5
  store i32 0, ptr %5, align 4, !tbaa !5
  store i32 0, ptr %8, align 4, !tbaa !5
  store i32 0, ptr %6, align 4, !tbaa !5
  br label %54

54:                                               ; preds = %83, %34
  %55 = load i32, ptr %6, align 4, !tbaa !5
  %56 = load i32, ptr %4, align 4, !tbaa !5
  %57 = icmp ult i32 %55, %56
  br i1 %57, label %58, label %86

58:                                               ; preds = %54
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %59

59:                                               ; preds = %75, %58
  %60 = load i32, ptr %9, align 4, !tbaa !5
  %61 = load i32, ptr %10, align 4, !tbaa !5
  %62 = icmp ult i32 %60, %61
  br i1 %62, label %63, label %78

63:                                               ; preds = %59
  %64 = load i32, ptr %5, align 4, !tbaa !5
  %65 = load i32, ptr %8, align 4, !tbaa !5
  %66 = or i32 %64, %65
  %67 = load i32, ptr %12, align 4, !tbaa !5
  %68 = shl i32 %67, 1
  %69 = or i32 %66, %68
  store i32 %69, ptr %2, align 4, !tbaa !5
  %70 = load i32, ptr %2, align 4, !tbaa !5
  call void asm sideeffect "mcr p15, 0, $0,  c7, c14, 2\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %70) #2, !srcloc !15
  %71 = load i32, ptr %3, align 4, !tbaa !5
  %72 = shl i32 1, %71
  %73 = load i32, ptr %8, align 4, !tbaa !5
  %74 = add i32 %73, %72
  store i32 %74, ptr %8, align 4, !tbaa !5
  br label %75

75:                                               ; preds = %63
  %76 = load i32, ptr %9, align 4, !tbaa !5
  %77 = add i32 %76, 1
  store i32 %77, ptr %9, align 4, !tbaa !5
  br label %59, !llvm.loop !16

78:                                               ; preds = %59
  store i32 0, ptr %8, align 4, !tbaa !5
  %79 = load i32, ptr %7, align 4, !tbaa !5
  %80 = shl i32 1, %79
  %81 = load i32, ptr %5, align 4, !tbaa !5
  %82 = add i32 %81, %80
  store i32 %82, ptr %5, align 4, !tbaa !5
  br label %83

83:                                               ; preds = %78
  %84 = load i32, ptr %6, align 4, !tbaa !5
  %85 = add i32 %84, 1
  store i32 %85, ptr %6, align 4, !tbaa !5
  br label %54, !llvm.loop !18

86:                                               ; preds = %54
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !19
  br label %87

87:                                               ; preds = %86
  %88 = load i32, ptr %12, align 4, !tbaa !5
  %89 = add i32 %88, 1
  store i32 %89, ptr %12, align 4, !tbaa !5
  %90 = load i32, ptr %7, align 4, !tbaa !5
  %91 = sub i32 %90, 2
  store i32 %91, ptr %7, align 4, !tbaa !5
  br label %30, !llvm.loop !20

92:                                               ; preds = %30
  %93 = load i32, ptr %13, align 4, !tbaa !5
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %93) #2, !srcloc !21
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 2147862940}
!10 = !{i64 2147863036}
!11 = !{i64 2147863159}
!12 = !{i64 2147863301}
!13 = !{i64 2147863441}
!14 = !{i64 2147863515}
!15 = !{i64 2147863657}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = distinct !{!18, !17}
!19 = !{i64 2147863776}
!20 = distinct !{!20, !17}
!21 = !{i64 2147863826}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheFlush() local_unnamed_addr #0 {
  %1 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !5
  %2 = or i32 %1, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %2) #1, !srcloc !6
  %3 = tail call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 1\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !7
  %4 = lshr i32 %3, 24
  %5 = and i32 %4, 7
  %.not44 = icmp eq i32 %5, 0
  br i1 %.not44, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %0, %23
  %.03343 = phi i32 [ %25, %23 ], [ 30, %0 ]
  %.03642 = phi i32 [ %24, %23 ], [ 0, %0 ]
  %6 = shl nuw nsw i32 %.03642, 1
  tail call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %6) #1, !srcloc !8
  tail call void asm sideeffect "isb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !9
  %7 = tail call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !10
  %8 = and i32 %7, 7
  %9 = lshr i32 %7, 3
  %10 = and i32 %9, 1023
  %11 = lshr i32 %7, 13
  %12 = and i32 %11, 32767
  %13 = shl nuw nsw i32 16, %8
  %14 = shl nuw i32 1, %.03343
  br label %.preheader

.preheader:                                       ; preds = %.lr.ph, %20
  %.041 = phi i32 [ 0, %.lr.ph ], [ %21, %20 ]
  %.03240 = phi i32 [ 0, %.lr.ph ], [ %22, %20 ]
  %15 = or i32 %.041, %6
  br label %16

16:                                               ; preds = %.preheader, %16
  %.139 = phi i32 [ 0, %.preheader ], [ %18, %16 ]
  %.03538 = phi i32 [ 0, %.preheader ], [ %19, %16 ]
  %17 = or i32 %15, %.139
  tail call void asm sideeffect "mcr p15, 0, $0,  c7, c14, 2\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %17) #1, !srcloc !11
  %18 = add nuw nsw i32 %.139, %13
  %19 = add nuw nsw i32 %.03538, 1
  %exitcond.not = icmp eq i32 %.03538, %12
  br i1 %exitcond.not, label %20, label %16, !llvm.loop !12

20:                                               ; preds = %16
  %21 = add i32 %.041, %14
  %22 = add nuw nsw i32 %.03240, 1
  %exitcond45.not = icmp eq i32 %.03240, %10
  br i1 %exitcond45.not, label %23, label %.preheader, !llvm.loop !14

23:                                               ; preds = %20
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !15
  %24 = add nuw nsw i32 %.03642, 1
  %25 = add nsw i32 %.03343, -2
  %exitcond46.not = icmp eq i32 %24, %5
  br i1 %exitcond46.not, label %._crit_edge, label %.lr.ph, !llvm.loop !16

._crit_edge:                                      ; preds = %23, %0
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %1) #1, !srcloc !17
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147862940}
!6 = !{i64 2147863036}
!7 = !{i64 2147863159}
!8 = !{i64 2147863301}
!9 = !{i64 2147863441}
!10 = !{i64 2147863515}
!11 = !{i64 2147863657}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}
!15 = !{i64 2147863776}
!16 = distinct !{!16, !13}
!17 = !{i64 2147863826}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass