; LLVM IR from corentinartaud/graphics :: ThirdParty/FreeImage-3170/Source/OpenEXR/IlmImf (ImfSystemSpecific)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Imf_2_2::CpuId" = type { i8, i8, i8, i8, i8, i8, i8 }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7Imf_2_25CpuIdC2Ev(ptr noundef nonnull align 1 dereferenceable(7) %0) unnamed_addr #0 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %9 = load ptr, ptr %2, align 8
  %10 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 0
  store i8 0, ptr %10, align 1, !tbaa !9
  %11 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 1
  store i8 0, ptr %11, align 1, !tbaa !12
  %12 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 2
  store i8 0, ptr %12, align 1, !tbaa !13
  %13 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 3
  store i8 0, ptr %13, align 1, !tbaa !14
  %14 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 4
  store i8 0, ptr %14, align 1, !tbaa !15
  %15 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 5
  store i8 0, ptr %15, align 1, !tbaa !16
  %16 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 6
  store i8 0, ptr %16, align 1, !tbaa !17
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  store i8 0, ptr %3, align 1, !tbaa !18
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !19
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @_ZN7Imf_2_212_GLOBAL__N_15cpuidEiRiS1_S1_S1_(i32 noundef 0, ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %6, ptr noundef nonnull align 4 dereferenceable(4) %7, ptr noundef nonnull align 4 dereferenceable(4) %8)
  %17 = load i32, ptr %4, align 4, !tbaa !19
  %18 = icmp sgt i32 %17, 0
  br i1 %18, label %19, label %73

19:                                               ; preds = %1
  call void @_ZN7Imf_2_212_GLOBAL__N_15cpuidEiRiS1_S1_S1_(i32 noundef 1, ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %6, ptr noundef nonnull align 4 dereferenceable(4) %7, ptr noundef nonnull align 4 dereferenceable(4) %8)
  %20 = load i32, ptr %8, align 4, !tbaa !19
  %21 = and i32 %20, 67108864
  %22 = icmp ne i32 %21, 0
  %23 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 0
  %24 = zext i1 %22 to i8
  store i8 %24, ptr %23, align 1, !tbaa !9
  %25 = load i32, ptr %7, align 4, !tbaa !19
  %26 = and i32 %25, 1
  %27 = icmp ne i32 %26, 0
  %28 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 1
  %29 = zext i1 %27 to i8
  store i8 %29, ptr %28, align 1, !tbaa !12
  %30 = load i32, ptr %7, align 4, !tbaa !19
  %31 = and i32 %30, 512
  %32 = icmp ne i32 %31, 0
  %33 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 2
  %34 = zext i1 %32 to i8
  store i8 %34, ptr %33, align 1, !tbaa !13
  %35 = load i32, ptr %7, align 4, !tbaa !19
  %36 = and i32 %35, 524288
  %37 = icmp ne i32 %36, 0
  %38 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 3
  %39 = zext i1 %37 to i8
  store i8 %39, ptr %38, align 1, !tbaa !14
  %40 = load i32, ptr %7, align 4, !tbaa !19
  %41 = and i32 %40, 1048576
  %42 = icmp ne i32 %41, 0
  %43 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 4
  %44 = zext i1 %42 to i8
  store i8 %44, ptr %43, align 1, !tbaa !15
  %45 = load i32, ptr %7, align 4, !tbaa !19
  %46 = and i32 %45, 134217728
  %47 = icmp ne i32 %46, 0
  %48 = zext i1 %47 to i8
  store i8 %48, ptr %3, align 1, !tbaa !18
  %49 = load i32, ptr %7, align 4, !tbaa !19
  %50 = and i32 %49, 268435456
  %51 = icmp ne i32 %50, 0
  %52 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 5
  %53 = zext i1 %51 to i8
  store i8 %53, ptr %52, align 1, !tbaa !16
  %54 = load i32, ptr %7, align 4, !tbaa !19
  %55 = and i32 %54, 536870912
  %56 = icmp ne i32 %55, 0
  %57 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 6
  %58 = zext i1 %56 to i8
  store i8 %58, ptr %57, align 1, !tbaa !17
  %59 = load i8, ptr %3, align 1, !tbaa !18, !range !21, !noundef !22
  %60 = trunc i8 %59 to i1
  br i1 %60, label %64, label %61

61:                                               ; preds = %19
  %62 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 6
  store i8 0, ptr %62, align 1, !tbaa !17
  %63 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 5
  store i8 0, ptr %63, align 1, !tbaa !16
  br label %72

64:                                               ; preds = %19
  call void @_ZN7Imf_2_212_GLOBAL__N_16xgetbvEiRiS1_(i32 noundef 0, ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %8)
  %65 = load i32, ptr %5, align 4, !tbaa !19
  %66 = and i32 %65, 6
  %67 = icmp ne i32 %66, 6
  br i1 %67, label %68, label %71

68:                                               ; preds = %64
  %69 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 6
  store i8 0, ptr %69, align 1, !tbaa !17
  %70 = getelementptr inbounds %"class.Imf_2_2::CpuId", ptr %9, i32 0, i32 5
  store i8 0, ptr %70, align 1, !tbaa !16
  br label %71

71:                                               ; preds = %68, %64
  br label %72

72:                                               ; preds = %71, %61
  br label %73

73:                                               ; preds = %72, %1
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZN7Imf_2_212_GLOBAL__N_15cpuidEiRiS1_S1_S1_(i32 noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZN7Imf_2_212_GLOBAL__N_16xgetbvEiRiS1_(i32 noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTSN7Imf_2_25CpuIdE", !11, i64 0, !11, i64 1, !11, i64 2, !11, i64 3, !11, i64 4, !11, i64 5, !11, i64 6}
!11 = !{!"bool", !7, i64 0}
!12 = !{!10, !11, i64 1}
!13 = !{!10, !11, i64 2}
!14 = !{!10, !11, i64 3}
!15 = !{!10, !11, i64 4}
!16 = !{!10, !11, i64 5}
!17 = !{!10, !11, i64 6}
!18 = !{!11, !11, i64 0}
!19 = !{!20, !20, i64 0}
!20 = !{!"int", !7, i64 0}
!21 = !{i8 0, i8 2}
!22 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7Imf_2_25CpuIdC2Ev(ptr nocapture noundef nonnull writeonly align 1 dereferenceable(7) %0) unnamed_addr #0 align 2 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = getelementptr inbounds i8, ptr %0, i64 5
  %8 = getelementptr inbounds i8, ptr %0, i64 6
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(7) %0, i8 0, i64 7, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #3
  store i32 0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #3
  call void @_ZN7Imf_2_212_GLOBAL__N_15cpuidEiRiS1_S1_S1_(i32 noundef 0, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %9 = load i32, ptr %2, align 4, !tbaa !5
  %10 = icmp sgt i32 %9, 0
  br i1 %10, label %11, label %42

11:                                               ; preds = %1
  %12 = getelementptr inbounds i8, ptr %0, i64 4
  %13 = getelementptr inbounds i8, ptr %0, i64 3
  %14 = getelementptr inbounds i8, ptr %0, i64 2
  %15 = getelementptr inbounds i8, ptr %0, i64 1
  call void @_ZN7Imf_2_212_GLOBAL__N_15cpuidEiRiS1_S1_S1_(i32 noundef 1, ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %16 = load i32, ptr %6, align 4, !tbaa !5
  %17 = lshr i32 %16, 26
  %18 = trunc nuw nsw i32 %17 to i8
  %19 = and i8 %18, 1
  store i8 %19, ptr %0, align 1, !tbaa !9
  %20 = load i32, ptr %5, align 4, !tbaa !5
  %21 = trunc i32 %20 to i8
  %22 = and i8 %21, 1
  store i8 %22, ptr %15, align 1, !tbaa !12
  %23 = lshr i32 %20, 9
  %24 = trunc i32 %23 to i8
  %25 = and i8 %24, 1
  store i8 %25, ptr %14, align 1, !tbaa !13
  %26 = lshr i32 %20, 19
  %27 = trunc i32 %26 to i8
  %28 = and i8 %27, 1
  store i8 %28, ptr %13, align 1, !tbaa !14
  %29 = lshr i32 %20, 20
  %30 = trunc i32 %29 to i8
  %31 = and i8 %30, 1
  store i8 %31, ptr %12, align 1, !tbaa !15
  %32 = and i32 %20, 134217728
  %.not = icmp eq i32 %32, 0
  %33 = lshr i32 %20, 28
  %34 = trunc nuw nsw i32 %33 to i8
  %35 = and i8 %34, 1
  store i8 %35, ptr %7, align 1, !tbaa !16
  %36 = lshr i32 %20, 29
  %37 = trunc nuw nsw i32 %36 to i8
  %38 = and i8 %37, 1
  store i8 %38, ptr %8, align 1, !tbaa !17
  br i1 %.not, label %.sink.split, label %39

39:                                               ; preds = %11
  call void @_ZN7Imf_2_212_GLOBAL__N_16xgetbvEiRiS1_(i32 noundef 0, ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %40 = load i32, ptr %3, align 4, !tbaa !5
  %41 = and i32 %40, 6
  %.not1 = icmp eq i32 %41, 6
  br i1 %.not1, label %42, label %.sink.split

.sink.split:                                      ; preds = %39, %11
  store i8 0, ptr %8, align 1, !tbaa !17
  store i8 0, ptr %7, align 1, !tbaa !16
  br label %42

42:                                               ; preds = %.sink.split, %39, %1
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZN7Imf_2_212_GLOBAL__N_15cpuidEiRiS1_S1_S1_(i32 noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZN7Imf_2_212_GLOBAL__N_16xgetbvEiRiS1_(i32 noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTSN7Imf_2_25CpuIdE", !11, i64 0, !11, i64 1, !11, i64 2, !11, i64 3, !11, i64 4, !11, i64 5, !11, i64 6}
!11 = !{!"bool", !7, i64 0}
!12 = !{!10, !11, i64 1}
!13 = !{!10, !11, i64 2}
!14 = !{!10, !11, i64 3}
!15 = !{!10, !11, i64 4}
!16 = !{!10, !11, i64 5}
!17 = !{!10, !11, i64 6}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass