; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (CardOpCond)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_CardOpCond(ptr noundef %0) #3 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  br label %6

6:                                                ; preds = %54, %1
  %7 = load ptr, ptr %2, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.XSdPs, ptr %7, i32 0, i32 5
  %9 = load i8, ptr %8, align 4, !tbaa !9
  %10 = zext i8 %9 to i32
  %11 = icmp eq i32 %10, 1
  br i1 %11, label %12, label %38

12:                                               ; preds = %6
  %13 = load ptr, ptr %2, align 8, !tbaa !5
  %14 = call i32 @XSdPs_CmdTransfer(ptr noundef %13, i32 noundef 14080, i32 noundef 0, i32 noundef 0)
  store i32 %14, ptr %4, align 4, !tbaa !15
  %15 = load i32, ptr %4, align 4, !tbaa !15
  %16 = sext i32 %15 to i64
  %17 = icmp ne i64 %16, 0
  br i1 %17, label %18, label %19

18:                                               ; preds = %12
  store i32 1, ptr %4, align 4, !tbaa !15
  br label %80

19:                                               ; preds = %12
  store i32 1090486272, ptr %5, align 4, !tbaa !15
  %20 = load ptr, ptr %2, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.XSdPs, ptr %20, i32 0, i32 7
  %22 = load i8, ptr %21, align 2, !tbaa !16
  %23 = zext i8 %22 to i32
  %24 = icmp eq i32 %23, 2
  br i1 %24, label %25, label %34

25:                                               ; preds = %19
  %26 = load ptr, ptr %2, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.XSdPs, ptr %26, i32 0, i32 0
  %28 = getelementptr inbounds %struct.XSdPs_Config, ptr %27, i32 0, i32 5
  %29 = load i32, ptr %28, align 4, !tbaa !17
  %30 = icmp eq i32 %29, 8
  br i1 %30, label %31, label %34

31:                                               ; preds = %25
  %32 = load i32, ptr %5, align 4, !tbaa !15
  %33 = or i32 %32, 16777216
  store i32 %33, ptr %5, align 4, !tbaa !15
  br label %34

34:                                               ; preds = %31, %25, %19
  %35 = load ptr, ptr %2, align 8, !tbaa !5
  %36 = load i32, ptr %5, align 4, !tbaa !15
  %37 = call i32 @XSdPs_CmdTransfer(ptr noundef %35, i32 noundef 43264, i32 noundef %36, i32 noundef 0)
  store i32 %37, ptr %4, align 4, !tbaa !15
  br label %41

38:                                               ; preds = %6
  %39 = load ptr, ptr %2, align 8, !tbaa !5
  %40 = call i32 @XSdPs_CmdTransfer(ptr noundef %39, i32 noundef 256, i32 noundef 1090486272, i32 noundef 0)
  store i32 %40, ptr %4, align 4, !tbaa !15
  br label %41

41:                                               ; preds = %38, %34
  %42 = load i32, ptr %4, align 4, !tbaa !15
  %43 = sext i32 %42 to i64
  %44 = icmp ne i64 %43, 0
  br i1 %44, label %45, label %46

45:                                               ; preds = %41
  store i32 1, ptr %4, align 4, !tbaa !15
  br label %80

46:                                               ; preds = %41
  %47 = load ptr, ptr %2, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.XSdPs, ptr %47, i32 0, i32 0
  %49 = getelementptr inbounds %struct.XSdPs_Config, ptr %48, i32 0, i32 1
  %50 = load i32, ptr %49, align 4, !tbaa !18
  %51 = add i32 %50, 16
  %52 = zext i32 %51 to i64
  %53 = call i32 @Xil_In32(i64 noundef %52)
  store i32 %53, ptr %3, align 4, !tbaa !15
  br label %54

54:                                               ; preds = %46
  %55 = load i32, ptr %3, align 4, !tbaa !15
  %56 = and i32 %55, -2147483648
  %57 = icmp eq i32 %56, 0
  br i1 %57, label %6, label %58, !llvm.loop !19

58:                                               ; preds = %54
  %59 = load i32, ptr %3, align 4, !tbaa !15
  %60 = and i32 %59, 1073741824
  %61 = icmp ne i32 %60, 0
  br i1 %61, label %62, label %65

62:                                               ; preds = %58
  %63 = load ptr, ptr %2, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.XSdPs, ptr %63, i32 0, i32 4
  store i32 1, ptr %64, align 8, !tbaa !21
  br label %65

65:                                               ; preds = %62, %58
  %66 = load i32, ptr %3, align 4, !tbaa !15
  %67 = and i32 %66, 16777216
  %68 = icmp ne i32 %67, 0
  br i1 %68, label %69, label %79

69:                                               ; preds = %65
  %70 = load ptr, ptr %2, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.XSdPs, ptr %70, i32 0, i32 10
  store i8 1, ptr %71, align 4, !tbaa !22
  %72 = load ptr, ptr %2, align 8, !tbaa !5
  %73 = call i32 @XSdPs_Switch_Voltage(ptr noundef %72)
  store i32 %73, ptr %4, align 4, !tbaa !15
  %74 = load i32, ptr %4, align 4, !tbaa !15
  %75 = sext i32 %74 to i64
  %76 = icmp ne i64 %75, 0
  br i1 %76, label %77, label %78

77:                                               ; preds = %69
  store i32 1, ptr %4, align 4, !tbaa !15
  br label %80

78:                                               ; preds = %69
  br label %79

79:                                               ; preds = %78, %65
  store i32 0, ptr %4, align 4, !tbaa !15
  br label %80

80:                                               ; preds = %79, %77, %45, %18
  %81 = load i32, ptr %4, align 4, !tbaa !15
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret i32 %81
}

declare i32 @XSdPs_Switch_Voltage(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !7, i64 52}
!10 = !{!"", !11, i64 0, !13, i64 36, !13, i64 40, !13, i64 44, !13, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !13, i64 56, !7, i64 60, !7, i64 64, !13, i64 80, !7, i64 84, !13, i64 100, !13, i64 104, !13, i64 108, !13, i64 112, !13, i64 116, !14, i64 120, !12, i64 128, !13, i64 132, !7, i64 136, !13, i64 140}
!11 = !{!"", !12, i64 0, !13, i64 4, !13, i64 8, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"int", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!13, !13, i64 0}
!16 = !{!10, !7, i64 54}
!17 = !{!10, !13, i64 20}
!18 = !{!10, !13, i64 4}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = !{!10, !13, i64 48}
!22 = !{!10, !7, i64 60}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_CardOpCond(ptr noundef %0) local_unnamed_addr #2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 52
  %3 = getelementptr inbounds i8, ptr %0, i64 54
  %4 = getelementptr inbounds i8, ptr %0, i64 20
  %5 = getelementptr inbounds i8, ptr %0, i64 4
  br label %6

6:                                                ; preds = %22, %1
  %7 = load i8, ptr %2, align 4, !tbaa !5
  %8 = icmp eq i8 %7, 1
  br i1 %8, label %9, label %19

9:                                                ; preds = %6
  %10 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 14080, i32 noundef 0, i32 noundef 0) #3
  %.not = icmp eq i32 %10, 0
  br i1 %.not, label %11, label %.loopexit

11:                                               ; preds = %9
  %12 = load i8, ptr %3, align 2, !tbaa !13
  %13 = icmp eq i8 %12, 2
  br i1 %13, label %14, label %17

14:                                               ; preds = %11
  %15 = load i32, ptr %4, align 4, !tbaa !14
  %16 = icmp eq i32 %15, 8
  %spec.select = select i1 %16, i32 1107263488, i32 1090486272
  br label %17

17:                                               ; preds = %14, %11
  %.0 = phi i32 [ 1090486272, %11 ], [ %spec.select, %14 ]
  %18 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 43264, i32 noundef %.0, i32 noundef 0) #3
  br label %21

19:                                               ; preds = %6
  %20 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 256, i32 noundef 1090486272, i32 noundef 0) #3
  br label %21

21:                                               ; preds = %19, %17
  %.018 = phi i32 [ %18, %17 ], [ %20, %19 ]
  %.not19 = icmp eq i32 %.018, 0
  br i1 %.not19, label %22, label %.loopexit

22:                                               ; preds = %21
  %23 = load i32, ptr %5, align 4, !tbaa !15
  %24 = add i32 %23, 16
  %25 = zext i32 %24 to i64
  %26 = tail call i32 @Xil_In32(i64 noundef %25)
  %27 = icmp sgt i32 %26, -1
  br i1 %27, label %6, label %28, !llvm.loop !16

28:                                               ; preds = %22
  %29 = and i32 %26, 1073741824
  %.not20 = icmp eq i32 %29, 0
  br i1 %.not20, label %32, label %30

30:                                               ; preds = %28
  %31 = getelementptr inbounds i8, ptr %0, i64 48
  store i32 1, ptr %31, align 8, !tbaa !18
  br label %32

32:                                               ; preds = %30, %28
  %33 = and i32 %26, 16777216
  %.not21 = icmp eq i32 %33, 0
  br i1 %.not21, label %37, label %34

34:                                               ; preds = %32
  %35 = getelementptr inbounds i8, ptr %0, i64 60
  store i8 1, ptr %35, align 4, !tbaa !19
  %36 = tail call i32 @XSdPs_Switch_Voltage(ptr noundef nonnull %0) #3
  %.not22 = icmp eq i32 %36, 0
  br i1 %.not22, label %37, label %.loopexit

37:                                               ; preds = %34, %32
  br label %.loopexit

.loopexit:                                        ; preds = %21, %9, %34, %37
  %.1 = phi i32 [ 0, %37 ], [ 1, %34 ], [ 1, %9 ], [ 1, %21 ]
  ret i32 %.1
}

declare i32 @XSdPs_Switch_Voltage(ptr noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 52}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = !{!6, !9, i64 54}
!14 = !{!6, !11, i64 20}
!15 = !{!6, !11, i64 4}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{!6, !11, i64 48}
!19 = !{!6, !9, i64 60}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass