; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (SetupReadDma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #0

; Function Attrs: nounwind uwtable
define dso_local void @XSdPs_SetupReadDma(ptr noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, ptr noundef %3) #1 {
  %5 = alloca ptr, align 8
  %6 = alloca i16, align 2
  %7 = alloca i16, align 2
  %8 = alloca ptr, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !9
  store i16 %2, ptr %7, align 2, !tbaa !9
  store ptr %3, ptr %8, align 8, !tbaa !5
  %9 = load i16, ptr %7, align 2, !tbaa !9
  %10 = zext i16 %9 to i32
  %11 = and i32 %10, 4095
  %12 = trunc i32 %11 to i16
  store i16 %12, ptr %7, align 2, !tbaa !9
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.XSdPs, ptr %13, i32 0, i32 0
  %15 = getelementptr inbounds %struct.XSdPs_Config, ptr %14, i32 0, i32 1
  %16 = load i32, ptr %15, align 4, !tbaa !11
  %17 = load i16, ptr %7, align 2, !tbaa !9
  call void @XSdPs_WriteReg16(i32 noundef %16, i8 noundef zeroext 4, i16 noundef zeroext %17)
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XSdPs, ptr %18, i32 0, i32 19
  %20 = load i64, ptr %19, align 8, !tbaa !16
  %21 = icmp uge i64 %20, 4294967296
  br i1 %21, label %22, label %26

22:                                               ; preds = %4
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = load i16, ptr %6, align 2, !tbaa !9
  %25 = zext i16 %24 to i32
  call void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef %23, i32 noundef %25)
  br label %47

26:                                               ; preds = %4
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = load i16, ptr %6, align 2, !tbaa !9
  %29 = zext i16 %28 to i32
  %30 = load ptr, ptr %8, align 8, !tbaa !5
  call void @XSdPs_SetupADMA2DescTbl(ptr noundef %27, i32 noundef %29, ptr noundef %30)
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.XSdPs, ptr %31, i32 0, i32 0
  %33 = getelementptr inbounds %struct.XSdPs_Config, ptr %32, i32 0, i32 8
  %34 = load i8, ptr %33, align 8, !tbaa !17
  %35 = zext i8 %34 to i32
  %36 = icmp eq i32 %35, 0
  br i1 %36, label %37, label %46

37:                                               ; preds = %26
  %38 = load ptr, ptr %8, align 8, !tbaa !5
  %39 = ptrtoint ptr %38 to i64
  %40 = load i16, ptr %6, align 2, !tbaa !9
  %41 = zext i16 %40 to i64
  %42 = load i16, ptr %7, align 2, !tbaa !9
  %43 = zext i16 %42 to i64
  %44 = mul nsw i64 %41, %43
  %45 = trunc i64 %44 to i32
  call void @Xil_DCacheInvalidateRange(i64 noundef %39, i32 noundef %45)
  br label %46

46:                                               ; preds = %37, %26
  br label %47

47:                                               ; preds = %46, %22
  %48 = load i16, ptr %6, align 2, !tbaa !9
  %49 = zext i16 %48 to i32
  %50 = icmp eq i32 %49, 1
  br i1 %50, label %51, label %54

51:                                               ; preds = %47
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.XSdPs, ptr %52, i32 0, i32 20
  store i16 19, ptr %53, align 8, !tbaa !18
  br label %57

54:                                               ; preds = %47
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.XSdPs, ptr %55, i32 0, i32 20
  store i16 55, ptr %56, align 8, !tbaa !18
  br label %57

57:                                               ; preds = %54, %51
  ret void
}

declare void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef, i32 noundef) #2

declare void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) #2

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !14, i64 4}
!12 = !{!"", !13, i64 0, !14, i64 36, !14, i64 40, !14, i64 44, !14, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !14, i64 56, !7, i64 60, !7, i64 64, !14, i64 80, !7, i64 84, !14, i64 100, !14, i64 104, !14, i64 108, !14, i64 112, !14, i64 116, !15, i64 120, !10, i64 128, !14, i64 132, !7, i64 136, !14, i64 140}
!13 = !{!"", !10, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !7, i64 32}
!14 = !{!"int", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !15, i64 120}
!17 = !{!12, !7, i64 32}
!18 = !{!12, !10, i64 128}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @XSdPs_SetupReadDma(ptr noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, ptr noundef %3) local_unnamed_addr #1 {
  %5 = and i16 %2, 4095
  %6 = getelementptr inbounds i8, ptr %0, i64 4
  %7 = load i32, ptr %6, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %7, i8 noundef zeroext 4, i16 noundef zeroext %5)
  %8 = getelementptr inbounds i8, ptr %0, i64 120
  %9 = load i64, ptr %8, align 8, !tbaa !13
  %10 = icmp ugt i64 %9, 4294967295
  %11 = zext i16 %1 to i32
  br i1 %10, label %12, label %13

12:                                               ; preds = %4
  tail call void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef nonnull %0, i32 noundef %11) #3
  br label %21

13:                                               ; preds = %4
  tail call void @XSdPs_SetupADMA2DescTbl(ptr noundef nonnull %0, i32 noundef %11, ptr noundef %3) #3
  %14 = getelementptr inbounds i8, ptr %0, i64 32
  %15 = load i8, ptr %14, align 8, !tbaa !14
  %16 = icmp eq i8 %15, 0
  br i1 %16, label %17, label %21

17:                                               ; preds = %13
  %18 = ptrtoint ptr %3 to i64
  %19 = zext nneg i16 %5 to i32
  %20 = mul nuw nsw i32 %19, %11
  tail call void @Xil_DCacheInvalidateRange(i64 noundef %18, i32 noundef %20) #3
  br label %21

21:                                               ; preds = %13, %17, %12
  %22 = icmp eq i16 %1, 1
  %spec.select = select i1 %22, i16 19, i16 55
  %23 = getelementptr inbounds i8, ptr %0, i64 128
  store i16 %spec.select, ptr %23, align 8
  ret void
}

declare void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 4}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = !{!6, !12, i64 120}
!14 = !{!6, !9, i64 32}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,JumpThreadingPass,MergedLoadStoreMotionPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass