; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (SetUpAnEvent)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.1 = external hidden unnamed_addr constant [24 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @xil_printf(ptr noundef, ...) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @Xpm_SetUpAnEvent(i32 noundef %0) #2 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store i64 0, ptr %7, align 8, !tbaa !9
  %10 = call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_COUNT_ENABLE_SET", "=r,~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !11
  store i64 %10, ptr %7, align 8, !tbaa !9
  %11 = load i64, ptr %7, align 8, !tbaa !9
  store i64 %11, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  %12 = load i64, ptr %8, align 8, !tbaa !9
  %13 = trunc i64 %12 to i32
  store i32 %13, ptr %5, align 4, !tbaa !5
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = and i32 %14, 7
  store i32 %15, ptr %5, align 4, !tbaa !5
  %16 = load i32, ptr %5, align 4, !tbaa !5
  store i32 %16, ptr %4, align 4, !tbaa !5
  %17 = load i32, ptr %4, align 4, !tbaa !5
  %18 = icmp eq i32 %17, 7
  br i1 %18, label %19, label %20

19:                                               ; preds = %1
  call void (ptr, ...) @xil_printf(ptr noundef @.str.1)
  store i32 255, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %44

20:                                               ; preds = %1
  store i32 0, ptr %6, align 4, !tbaa !5
  br label %21

21:                                               ; preds = %32, %20
  %22 = load i32, ptr %6, align 4, !tbaa !5
  %23 = icmp ult i32 %22, 3
  br i1 %23, label %24, label %35

24:                                               ; preds = %21
  %25 = load i32, ptr %4, align 4, !tbaa !5
  %26 = and i32 %25, 1
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %28, label %29

28:                                               ; preds = %24
  br label %35

29:                                               ; preds = %24
  %30 = load i32, ptr %4, align 4, !tbaa !5
  %31 = lshr i32 %30, 1
  store i32 %31, ptr %4, align 4, !tbaa !5
  br label %32

32:                                               ; preds = %29
  %33 = load i32, ptr %6, align 4, !tbaa !5
  %34 = add i32 %33, 1
  store i32 %34, ptr %6, align 4, !tbaa !5
  br label %21, !llvm.loop !12

35:                                               ; preds = %28, %21
  br label %36

36:                                               ; preds = %35
  %37 = load i32, ptr %6, align 4, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_EVENT_CNTR_SEL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %37) #3, !srcloc !14
  %38 = load i32, ptr %3, align 4, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_EVENT_TYPE_SEL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %38) #3, !srcloc !15
  %39 = load i32, ptr %5, align 4, !tbaa !5
  %40 = load i32, ptr %6, align 4, !tbaa !5
  %41 = shl i32 1, %40
  %42 = or i32 %39, %41
  call void asm sideeffect "msr XREG_CP15_COUNT_ENABLE_SET,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %42) #3, !srcloc !16
  %43 = load i32, ptr %6, align 4, !tbaa !5
  store i32 %43, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %44

44:                                               ; preds = %36, %19
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %45 = load i32, ptr %2, align 4
  ret i32 %45
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{i64 2147837568}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = !{i64 2147837692}
!15 = !{i64 2147837780}
!16 = !{i64 2147837870}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.1 = external hidden unnamed_addr constant [24 x i8], align 1

declare void @xil_printf(ptr noundef, ...) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @Xpm_SetUpAnEvent(i32 noundef %0) local_unnamed_addr #1 {
  %2 = tail call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_COUNT_ENABLE_SET", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !5
  %3 = trunc i64 %2 to i32
  %4 = and i32 %3, 7
  %5 = icmp eq i32 %4, 7
  br i1 %5, label %8, label %.preheader

.preheader:                                       ; preds = %1
  %6 = and i32 %3, 1
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %._crit_edge, label %.lr.ph

8:                                                ; preds = %1
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str.1) #2
  br label %15

.lr.ph:                                           ; preds = %.preheader
  %9 = and i32 %3, 2
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %._crit_edge, label %.lr.ph.1, !llvm.loop !6

.lr.ph.1:                                         ; preds = %.lr.ph
  %11 = and i32 %3, 4
  %12 = icmp eq i32 %11, 0
  %spec.select = select i1 %12, i32 2, i32 3
  br label %._crit_edge, !llvm.loop !6

._crit_edge:                                      ; preds = %.lr.ph.1, %.lr.ph, %.preheader
  %.016.lcssa = phi i32 [ 0, %.preheader ], [ 1, %.lr.ph ], [ %spec.select, %.lr.ph.1 ]
  tail call void asm sideeffect "msr XREG_CP15_EVENT_CNTR_SEL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %.016.lcssa) #2, !srcloc !8
  tail call void asm sideeffect "msr XREG_CP15_EVENT_TYPE_SEL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %0) #2, !srcloc !9
  %13 = shl nuw nsw i32 1, %.016.lcssa
  %14 = or i32 %13, %4
  tail call void asm sideeffect "msr XREG_CP15_COUNT_ENABLE_SET,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %14) #2, !srcloc !10
  br label %15

15:                                               ; preds = %._crit_edge, %8
  %.0 = phi i32 [ 255, %8 ], [ %.016.lcssa, %._crit_edge ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147837568}
!6 = distinct !{!6, !7}
!7 = !{!"llvm.loop.mustprogress"}
!8 = !{i64 2147837692}
!9 = !{i64 2147837780}
!10 = !{i64 2147837870}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass