; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (DCacheFlushRange)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2WriteDebugCtrl(i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2CacheSync() #1

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheFlushRange(i64 noundef %0, i32 noundef %1) #2 {
  %3 = alloca i64, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %12 = load i64, ptr %3, align 8, !tbaa !5
  %13 = trunc i64 %12 to i32
  store i32 %13, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 32, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  store ptr inttoptr (i64 4176488432 to ptr), ptr %9, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !9
  %14 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !13
  store i32 %14, ptr %10, align 4, !tbaa !9
  %15 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %15, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %16 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %16, ptr %8, align 4, !tbaa !9
  %17 = load i32, ptr %8, align 4, !tbaa !9
  %18 = or i32 %17, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %18) #3, !srcloc !14
  %19 = load i32, ptr %4, align 4, !tbaa !9
  %20 = icmp ne i32 %19, 0
  br i1 %20, label %21, label %38

21:                                               ; preds = %2
  %22 = load i32, ptr %5, align 4, !tbaa !9
  %23 = load i32, ptr %4, align 4, !tbaa !9
  %24 = add i32 %22, %23
  store i32 %24, ptr %7, align 4, !tbaa !9
  %25 = load i32, ptr %5, align 4, !tbaa !9
  %26 = and i32 %25, -32
  store i32 %26, ptr %5, align 4, !tbaa !9
  call void @Xil_L2WriteDebugCtrl(i32 noundef 3)
  br label %27

27:                                               ; preds = %31, %21
  %28 = load i32, ptr %5, align 4, !tbaa !9
  %29 = load i32, ptr %7, align 4, !tbaa !9
  %30 = icmp ult i32 %28, %29
  br i1 %30, label %31, label %37

31:                                               ; preds = %27
  %32 = load i32, ptr %5, align 4, !tbaa !9
  call void asm sideeffect "mcr p15, 0, $0,  c7, c14, 1", "r,~{dirflag},~{fpsr},~{flags}"(i32 %32) #3, !srcloc !15
  %33 = load i32, ptr %5, align 4, !tbaa !9
  %34 = load ptr, ptr %9, align 8, !tbaa !11
  store volatile i32 %33, ptr %34, align 4, !tbaa !9
  call void @Xil_L2CacheSync()
  %35 = load i32, ptr %5, align 4, !tbaa !9
  %36 = add i32 %35, 32
  store i32 %36, ptr %5, align 4, !tbaa !9
  br label %27, !llvm.loop !16

37:                                               ; preds = %27
  call void @Xil_L2WriteDebugCtrl(i32 noundef 0)
  br label %38

38:                                               ; preds = %37, %2
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !18
  %39 = load i32, ptr %8, align 4, !tbaa !9
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %39) #3, !srcloc !19
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{i64 2147887650}
!14 = !{i64 2147887746}
!15 = !{i64 2147887838}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{i64 2147887963}
!19 = !{i64 2147888013}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2WriteDebugCtrl(i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2CacheSync() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheFlushRange(i64 noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !5
  %4 = or i32 %3, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %4) #2, !srcloc !6
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %12, label %5

5:                                                ; preds = %2
  %6 = trunc i64 %0 to i32
  %7 = add i32 %6, %1
  %8 = and i32 %6, -32
  tail call void @Xil_L2WriteDebugCtrl(i32 noundef 3)
  %9 = icmp ult i32 %8, %7
  br i1 %9, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %5, %.lr.ph
  %.015 = phi i32 [ %10, %.lr.ph ], [ %8, %5 ]
  tail call void asm sideeffect "mcr p15, 0, $0,  c7, c14, 1", "r,~{dirflag},~{fpsr},~{flags}"(i32 %.015) #2, !srcloc !7
  store volatile i32 %.015, ptr inttoptr (i64 4176488432 to ptr), align 16, !tbaa !8
  tail call void @Xil_L2CacheSync()
  %10 = add i32 %.015, 32
  %11 = icmp ult i32 %10, %7
  br i1 %11, label %.lr.ph, label %._crit_edge, !llvm.loop !12

._crit_edge:                                      ; preds = %.lr.ph, %5
  tail call void @Xil_L2WriteDebugCtrl(i32 noundef 0)
  br label %12

12:                                               ; preds = %._crit_edge, %2
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !14
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %3) #2, !srcloc !15
  ret void
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147887650}
!6 = !{i64 2147887746}
!7 = !{i64 2147887838}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C/C++ TBAA"}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = !{i64 2147887963}
!15 = !{i64 2147888013}


; Effective O3 passes: GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass