; LLVM IR from Izaron/ACM-ICPC :: Timus Online Judge/Volume 2/1117. Hierarchy.ll (Z4calcx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z4calcx(i64 noundef %0) #0 {
  %2 = alloca i64, align 8
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i32, align 4
  store i64 %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #2
  store i64 0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #2
  store i64 4, ptr %4, align 8, !tbaa !5
  br label %7

7:                                                ; preds = %25, %1
  br label %8

8:                                                ; preds = %7
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #2
  %9 = load i64, ptr %2, align 8, !tbaa !5
  %10 = sub nsw i64 %9, 1
  %11 = load i64, ptr %4, align 8, !tbaa !5
  %12 = sdiv i64 %10, %11
  store i64 %12, ptr %5, align 8, !tbaa !5
  %13 = load i64, ptr %5, align 8, !tbaa !5
  %14 = mul nsw i64 %13, 2
  %15 = load i64, ptr %3, align 8, !tbaa !5
  %16 = add nsw i64 %15, %14
  store i64 %16, ptr %3, align 8, !tbaa !5
  %17 = load i64, ptr %4, align 8, !tbaa !5
  %18 = mul nsw i64 %17, 2
  store i64 %18, ptr %4, align 8, !tbaa !5
  %19 = load i64, ptr %5, align 8, !tbaa !5
  %20 = icmp eq i64 %19, 0
  br i1 %20, label %21, label %22

21:                                               ; preds = %8
  store i32 3, ptr %6, align 4
  br label %23

22:                                               ; preds = %8
  store i32 0, ptr %6, align 4
  br label %23

23:                                               ; preds = %22, %21
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #2
  %24 = load i32, ptr %6, align 4
  switch i32 %24, label %46 [
    i32 0, label %25
    i32 3, label %26
  ]

25:                                               ; preds = %23
  br label %7, !llvm.loop !9

26:                                               ; preds = %23
  store i64 4, ptr %4, align 8, !tbaa !5
  br label %27

27:                                               ; preds = %43, %26
  br label %28

28:                                               ; preds = %27
  %29 = load i64, ptr %2, align 8, !tbaa !5
  %30 = load i64, ptr %4, align 8, !tbaa !5
  %31 = srem i64 %29, %30
  %32 = icmp eq i64 %31, 0
  br i1 %32, label %33, label %36

33:                                               ; preds = %28
  %34 = load i64, ptr %3, align 8, !tbaa !5
  %35 = add nsw i64 %34, 1
  store i64 %35, ptr %3, align 8, !tbaa !5
  br label %36

36:                                               ; preds = %33, %28
  %37 = load i64, ptr %4, align 8, !tbaa !5
  %38 = mul nsw i64 %37, 2
  store i64 %38, ptr %4, align 8, !tbaa !5
  %39 = load i64, ptr %4, align 8, !tbaa !5
  %40 = load i64, ptr %2, align 8, !tbaa !5
  %41 = icmp sgt i64 %39, %40
  br i1 %41, label %42, label %43

42:                                               ; preds = %36
  br label %44

43:                                               ; preds = %36
  br label %27, !llvm.loop !11

44:                                               ; preds = %42
  %45 = load i64, ptr %3, align 8, !tbaa !5
  store i32 1, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #2
  ret i64 %45

46:                                               ; preds = %23
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local noundef i64 @_Z4calcx(i64 noundef %0) local_unnamed_addr #0 {
  %2 = add nsw i64 %0, -1
  br label %3

3:                                                ; preds = %3, %1
  %.015 = phi i64 [ 4, %1 ], [ %7, %3 ]
  %.014 = phi i64 [ 0, %1 ], [ %6, %3 ]
  %4 = sdiv i64 %2, %.015
  %5 = shl nsw i64 %4, 1
  %6 = add nsw i64 %5, %.014
  %7 = shl nsw i64 %.015, 1
  %8 = icmp eq i64 %4, 0
  br i1 %8, label %.preheader, label %3

.preheader:                                       ; preds = %3, %.preheader
  %.116 = phi i64 [ %13, %.preheader ], [ 4, %3 ]
  %.1 = phi i64 [ %spec.select, %.preheader ], [ %6, %3 ]
  %9 = add nsw i64 %.116, -1
  %10 = and i64 %9, %0
  %11 = icmp eq i64 %10, 0
  %12 = zext i1 %11 to i64
  %spec.select = add nsw i64 %.1, %12
  %13 = shl nsw i64 %.116, 1
  %14 = icmp sgt i64 %13, %0
  br i1 %14, label %15, label %.preheader, !llvm.loop !5

15:                                               ; preds = %.preheader
  ret i64 %spec.select
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass