; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (CmdTransfer)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_CmdTransfer(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  store i32 10000000, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = load i32, ptr %7, align 4, !tbaa !9
  %14 = load i32, ptr %8, align 4, !tbaa !9
  %15 = call i32 @XSdPs_SetupCmd(ptr noundef %12, i32 noundef %13, i32 noundef %14)
  store i32 %15, ptr %11, align 4, !tbaa !9
  %16 = load i32, ptr %11, align 4, !tbaa !9
  %17 = sext i32 %16 to i64
  %18 = icmp ne i64 %17, 0
  br i1 %18, label %19, label %20

19:                                               ; preds = %4
  store i32 1, ptr %11, align 4, !tbaa !9
  br label %93

20:                                               ; preds = %4
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = call i32 @XSdPs_SendCmd(ptr noundef %21, i32 noundef %22)
  store i32 %23, ptr %11, align 4, !tbaa !9
  %24 = load i32, ptr %11, align 4, !tbaa !9
  %25 = sext i32 %24 to i64
  %26 = icmp ne i64 %25, 0
  br i1 %26, label %27, label %28

27:                                               ; preds = %20
  store i32 1, ptr %11, align 4, !tbaa !9
  br label %93

28:                                               ; preds = %20
  br label %29

29:                                               ; preds = %86, %28
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.XSdPs, ptr %30, i32 0, i32 0
  %32 = getelementptr inbounds %struct.XSdPs_Config, ptr %31, i32 0, i32 1
  %33 = load i32, ptr %32, align 4, !tbaa !11
  %34 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %33, i8 noundef zeroext 48)
  %35 = zext i16 %34 to i32
  store i32 %35, ptr %10, align 4, !tbaa !9
  %36 = load i32, ptr %6, align 4, !tbaa !9
  %37 = icmp eq i32 %36, 5376
  br i1 %37, label %41, label %38

38:                                               ; preds = %29
  %39 = load i32, ptr %6, align 4, !tbaa !9
  %40 = icmp eq i32 %39, 4864
  br i1 %40, label %41, label %56

41:                                               ; preds = %38, %29
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.XSdPs, ptr %42, i32 0, i32 0
  %44 = getelementptr inbounds %struct.XSdPs_Config, ptr %43, i32 0, i32 1
  %45 = load i32, ptr %44, align 4, !tbaa !11
  %46 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %45, i8 noundef zeroext 48)
  %47 = zext i16 %46 to i32
  %48 = and i32 %47, 32
  %49 = icmp ne i32 %48, 0
  br i1 %49, label %50, label %55

50:                                               ; preds = %41
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.XSdPs, ptr %51, i32 0, i32 0
  %53 = getelementptr inbounds %struct.XSdPs_Config, ptr %52, i32 0, i32 1
  %54 = load i32, ptr %53, align 4, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %54, i8 noundef zeroext 48, i16 noundef zeroext 32)
  br label %88

55:                                               ; preds = %41
  br label %56

56:                                               ; preds = %55, %38
  %57 = load i32, ptr %10, align 4, !tbaa !9
  %58 = and i32 %57, 32768
  %59 = icmp ne i32 %58, 0
  br i1 %59, label %60, label %76

60:                                               ; preds = %56
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.XSdPs, ptr %61, i32 0, i32 0
  %63 = getelementptr inbounds %struct.XSdPs_Config, ptr %62, i32 0, i32 1
  %64 = load i32, ptr %63, align 4, !tbaa !11
  %65 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %64, i8 noundef zeroext 50)
  %66 = zext i16 %65 to i32
  store i32 %66, ptr %11, align 4, !tbaa !9
  %67 = load i32, ptr %11, align 4, !tbaa !9
  %68 = and i32 %67, -2
  %69 = icmp eq i32 %68, 0
  br i1 %69, label %70, label %71

70:                                               ; preds = %60
  store i32 2, ptr %11, align 4, !tbaa !9
  br label %71

71:                                               ; preds = %70, %60
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.XSdPs, ptr %72, i32 0, i32 0
  %74 = getelementptr inbounds %struct.XSdPs_Config, ptr %73, i32 0, i32 1
  %75 = load i32, ptr %74, align 4, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %75, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %93

76:                                               ; preds = %56
  %77 = load i32, ptr %9, align 4, !tbaa !9
  %78 = sub i32 %77, 1
  store i32 %78, ptr %9, align 4, !tbaa !9
  br label %79

79:                                               ; preds = %76
  %80 = load i32, ptr %10, align 4, !tbaa !9
  %81 = and i32 %80, 1
  %82 = icmp eq i32 %81, 0
  br i1 %82, label %83, label %86

83:                                               ; preds = %79
  %84 = load i32, ptr %9, align 4, !tbaa !9
  %85 = icmp ne i32 %84, 0
  br label %86

86:                                               ; preds = %83, %79
  %87 = phi i1 [ false, %79 ], [ %85, %83 ]
  br i1 %87, label %29, label %88, !llvm.loop !16

88:                                               ; preds = %86, %50
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.XSdPs, ptr %89, i32 0, i32 0
  %91 = getelementptr inbounds %struct.XSdPs_Config, ptr %90, i32 0, i32 1
  %92 = load i32, ptr %91, align 4, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %92, i8 noundef zeroext 48, i16 noundef zeroext 1)
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %93

93:                                               ; preds = %88, %71, %27, %19
  %94 = load i32, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  ret i32 %94
}

declare i32 @XSdPs_SetupCmd(ptr noundef, i32 noundef, i32 noundef) #3

declare i32 @XSdPs_SendCmd(ptr noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !15, i64 120, !14, i64 128, !10, i64 132, !7, i64 136, !10, i64 140}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 65536) i32 @XSdPs_CmdTransfer(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = tail call i32 @XSdPs_SetupCmd(ptr noundef %0, i32 noundef %2, i32 noundef %3) #4
  %.not = icmp eq i32 %5, 0
  br i1 %.not, label %6, label %35

6:                                                ; preds = %4
  %7 = tail call i32 @XSdPs_SendCmd(ptr noundef %0, i32 noundef %1) #4
  %.not23 = icmp eq i32 %7, 0
  br i1 %.not23, label %.preheader, label %35

.preheader:                                       ; preds = %6
  %8 = getelementptr inbounds i8, ptr %0, i64 4
  switch i32 %1, label %.preheader.split [
    i32 5376, label %.preheader.split.us.preheader
    i32 4864, label %.preheader.split.us.preheader
  ]

.preheader.split.us.preheader:                    ; preds = %.preheader, %.preheader
  br label %.preheader.split.us

.preheader.split.us:                              ; preds = %.preheader.split.us.preheader, %15
  %.021.us = phi i32 [ %16, %15 ], [ 10000000, %.preheader.split.us.preheader ]
  %9 = load i32, ptr %8, align 4, !tbaa !5
  %10 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %9, i8 noundef zeroext 48)
  %11 = load i32, ptr %8, align 4, !tbaa !5
  %12 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %11, i8 noundef zeroext 48)
  %13 = and i16 %12, 32
  %.not24.us = icmp eq i16 %13, 0
  br i1 %.not24.us, label %14, label %.split.us

14:                                               ; preds = %.preheader.split.us
  %.not25.us = icmp sgt i16 %10, -1
  br i1 %.not25.us, label %15, label %.split29.us

15:                                               ; preds = %14
  %16 = add nsw i32 %.021.us, -1
  %17 = and i16 %10, 1
  %18 = icmp eq i16 %17, 0
  %19 = icmp ne i32 %16, 0
  %20 = select i1 %18, i1 %19, i1 false
  br i1 %20, label %.preheader.split.us, label %.loopexit, !llvm.loop !13

.preheader.split:                                 ; preds = %.preheader, %28
  %.021 = phi i32 [ %29, %28 ], [ 10000000, %.preheader ]
  %21 = load i32, ptr %8, align 4, !tbaa !5
  %22 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %21, i8 noundef zeroext 48)
  %.not25 = icmp sgt i16 %22, -1
  br i1 %.not25, label %28, label %.split29.us

.split.us:                                        ; preds = %.preheader.split.us
  %23 = load i32, ptr %8, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %23, i8 noundef zeroext 48, i16 noundef zeroext 32)
  br label %.loopexit

.split29.us:                                      ; preds = %14, %.preheader.split
  %24 = load i32, ptr %8, align 4, !tbaa !5
  %25 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %24, i8 noundef zeroext 50)
  %26 = tail call i16 @llvm.umax.i16(i16 %25, i16 2)
  %spec.store.select = zext i16 %26 to i32
  %27 = load i32, ptr %8, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %27, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %35

28:                                               ; preds = %.preheader.split
  %29 = add nsw i32 %.021, -1
  %30 = and i16 %22, 1
  %31 = icmp eq i16 %30, 0
  %32 = icmp ne i32 %29, 0
  %33 = select i1 %31, i1 %32, i1 false
  br i1 %33, label %.preheader.split, label %.loopexit, !llvm.loop !13

.loopexit:                                        ; preds = %15, %28, %.split.us
  %34 = load i32, ptr %8, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %34, i8 noundef zeroext 48, i16 noundef zeroext 1)
  br label %35

35:                                               ; preds = %6, %4, %.loopexit, %.split29.us
  %.0 = phi i32 [ 0, %.loopexit ], [ %spec.store.select, %.split29.us ], [ 1, %4 ], [ 1, %6 ]
  ret i32 %.0
}

declare i32 @XSdPs_SetupCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

declare i32 @XSdPs_SendCmd(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.umax.i16(i16, i16) #3

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 4}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass