; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (SetMPURegionByRegNum)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.anon = type { i64, i32 }
%struct.XMpuConfig = type { i32, i64, i64, i32 }

@region_size = external hidden constant [28 x %struct.anon], align 16
@Mpu_Config = external dso_local global [16 x %struct.XMpuConfig], section ".bootdata", align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_DCacheFlush() #1

declare void @Xil_ICacheInvalidate() #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @Xil_UpdateMPUConfig(i32 noundef, i64 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @Xil_SetMPURegionByRegNum(i32 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3) #2 {
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i64, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store i64 %2, ptr %7, align 8, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  %13 = load i64, ptr %6, align 8, !tbaa !9
  store i64 %13, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = icmp uge i32 %14, 16
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 1, ptr %9, align 4, !tbaa !5
  br label %71

17:                                               ; preds = %4
  %18 = load i32, ptr %5, align 4, !tbaa !5
  %19 = zext i32 %18 to i64
  %20 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %19
  %21 = getelementptr inbounds %struct.XMpuConfig, ptr %20, i32 0, i32 0
  %22 = load i32, ptr %21, align 16, !tbaa !11
  %23 = icmp eq i32 %22, 1
  br i1 %23, label %24, label %25

24:                                               ; preds = %17
  store i32 1, ptr %9, align 4, !tbaa !5
  br label %71

25:                                               ; preds = %17
  call void @Xil_DCacheFlush()
  call void @Xil_ICacheInvalidate()
  %26 = load i32, ptr %5, align 4, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_MPU_MEMORY_REG_NUMBER,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %26) #3, !srcloc !13
  call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !14
  store i32 0, ptr %12, align 4, !tbaa !5
  br label %27

27:                                               ; preds = %46, %25
  %28 = load i32, ptr %12, align 4, !tbaa !5
  %29 = zext i32 %28 to i64
  %30 = icmp ult i64 %29, 28
  br i1 %30, label %31, label %49

31:                                               ; preds = %27
  %32 = load i64, ptr %7, align 8, !tbaa !9
  %33 = load i32, ptr %12, align 4, !tbaa !5
  %34 = zext i32 %33 to i64
  %35 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %34
  %36 = getelementptr inbounds %struct.anon, ptr %35, i32 0, i32 0
  %37 = load i64, ptr %36, align 16, !tbaa !15
  %38 = icmp ule i64 %32, %37
  br i1 %38, label %39, label %45

39:                                               ; preds = %31
  %40 = load i32, ptr %12, align 4, !tbaa !5
  %41 = zext i32 %40 to i64
  %42 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %41
  %43 = getelementptr inbounds %struct.anon, ptr %42, i32 0, i32 1
  %44 = load i32, ptr %43, align 8, !tbaa !17
  store i32 %44, ptr %11, align 4, !tbaa !5
  br label %49

45:                                               ; preds = %31
  br label %46

46:                                               ; preds = %45
  %47 = load i32, ptr %12, align 4, !tbaa !5
  %48 = add i32 %47, 1
  store i32 %48, ptr %12, align 4, !tbaa !5
  br label %27, !llvm.loop !18

49:                                               ; preds = %39, %27
  %50 = load i32, ptr %12, align 4, !tbaa !5
  %51 = zext i32 %50 to i64
  %52 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %51
  %53 = getelementptr inbounds %struct.anon, ptr %52, i32 0, i32 0
  %54 = load i64, ptr %53, align 16, !tbaa !15
  %55 = sub i64 %54, 1
  %56 = xor i64 %55, -1
  %57 = load i64, ptr %10, align 8, !tbaa !9
  %58 = and i64 %57, %56
  store i64 %58, ptr %10, align 8, !tbaa !9
  %59 = load i32, ptr %11, align 4, !tbaa !5
  %60 = shl i32 %59, 1
  store i32 %60, ptr %11, align 4, !tbaa !5
  %61 = load i32, ptr %11, align 4, !tbaa !5
  %62 = or i32 %61, 1
  store i32 %62, ptr %11, align 4, !tbaa !5
  call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !20
  %63 = load i64, ptr %10, align 8, !tbaa !9
  call void asm sideeffect "msr XREG_CP15_MPU_REG_BASEADDR,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i64 %63) #3, !srcloc !21
  %64 = load i32, ptr %8, align 4, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_MPU_REG_ACCESS_CTRL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %64) #3, !srcloc !22
  %65 = load i32, ptr %11, align 4, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_MPU_REG_SIZE_EN,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %65) #3, !srcloc !23
  call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !24
  call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !25
  %66 = load i32, ptr %5, align 4, !tbaa !5
  %67 = load i64, ptr %10, align 8, !tbaa !9
  %68 = load i32, ptr %11, align 4, !tbaa !5
  %69 = load i32, ptr %8, align 4, !tbaa !5
  %70 = call i32 @Xil_UpdateMPUConfig(i32 noundef %66, i64 noundef %67, i32 noundef %68, i32 noundef %69)
  br label %71

71:                                               ; preds = %49, %24, %16
  %72 = load i32, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  ret i32 %72
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"XMpuConfig", !6, i64 0, !10, i64 8, !10, i64 16, !6, i64 24}
!13 = !{i64 2147715760}
!14 = !{i64 2147715858}
!15 = !{!16, !10, i64 0}
!16 = !{!"", !10, i64 0, !6, i64 8}
!17 = !{!16, !6, i64 8}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{i64 2147715901}
!21 = !{i64 2147715932}
!22 = !{i64 2147716026}
!23 = !{i64 2147716120}
!24 = !{i64 2147716214}
!25 = !{i64 2147716246}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.anon = type { i64, i32 }
%struct.XMpuConfig = type { i32, i64, i64, i32 }

@region_size = external hidden local_unnamed_addr constant [28 x %struct.anon], align 16
@Mpu_Config = external dso_local local_unnamed_addr global [16 x %struct.XMpuConfig], section ".bootdata", align 16

declare void @Xil_DCacheFlush() local_unnamed_addr #0

declare void @Xil_ICacheInvalidate() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @Xil_UpdateMPUConfig(i32 noundef, i64 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @Xil_SetMPURegionByRegNum(i32 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = icmp ugt i32 %0, 15
  br i1 %5, label %78, label %6

6:                                                ; preds = %4
  %7 = zext nneg i32 %0 to i64
  %8 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %7
  %9 = load i32, ptr %8, align 16, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %78, label %11

11:                                               ; preds = %6
  tail call void @Xil_DCacheFlush() #2
  tail call void @Xil_ICacheInvalidate() #2
  tail call void asm sideeffect "msr XREG_CP15_MPU_MEMORY_REG_NUMBER,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %0) #2, !srcloc !11
  tail call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !12
  %12 = load i64, ptr @region_size, align 16, !tbaa !13
  %.not = icmp ult i64 %12, %2
  br i1 %.not, label %13, label %67

13:                                               ; preds = %11
  %14 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 16), align 16, !tbaa !13
  %.not.1 = icmp ult i64 %14, %2
  br i1 %.not.1, label %15, label %67

15:                                               ; preds = %13
  %16 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 32), align 16, !tbaa !13
  %.not.2 = icmp ult i64 %16, %2
  br i1 %.not.2, label %17, label %67

17:                                               ; preds = %15
  %18 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 48), align 16, !tbaa !13
  %.not.3 = icmp ult i64 %18, %2
  br i1 %.not.3, label %19, label %67

19:                                               ; preds = %17
  %20 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 64), align 16, !tbaa !13
  %.not.4 = icmp ult i64 %20, %2
  br i1 %.not.4, label %21, label %67

21:                                               ; preds = %19
  %22 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 80), align 16, !tbaa !13
  %.not.5 = icmp ult i64 %22, %2
  br i1 %.not.5, label %23, label %67

23:                                               ; preds = %21
  %24 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 96), align 16, !tbaa !13
  %.not.6 = icmp ult i64 %24, %2
  br i1 %.not.6, label %25, label %67

25:                                               ; preds = %23
  %26 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 112), align 16, !tbaa !13
  %.not.7 = icmp ult i64 %26, %2
  br i1 %.not.7, label %27, label %67

27:                                               ; preds = %25
  %28 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 128), align 16, !tbaa !13
  %.not.8 = icmp ult i64 %28, %2
  br i1 %.not.8, label %29, label %67

29:                                               ; preds = %27
  %30 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 144), align 16, !tbaa !13
  %.not.9 = icmp ult i64 %30, %2
  br i1 %.not.9, label %31, label %67

31:                                               ; preds = %29
  %32 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 160), align 16, !tbaa !13
  %.not.10 = icmp ult i64 %32, %2
  br i1 %.not.10, label %33, label %67

33:                                               ; preds = %31
  %34 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 176), align 16, !tbaa !13
  %.not.11 = icmp ult i64 %34, %2
  br i1 %.not.11, label %35, label %67

35:                                               ; preds = %33
  %36 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 192), align 16, !tbaa !13
  %.not.12 = icmp ult i64 %36, %2
  br i1 %.not.12, label %37, label %67

37:                                               ; preds = %35
  %38 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 208), align 16, !tbaa !13
  %.not.13 = icmp ult i64 %38, %2
  br i1 %.not.13, label %39, label %67

39:                                               ; preds = %37
  %40 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 224), align 16, !tbaa !13
  %.not.14 = icmp ult i64 %40, %2
  br i1 %.not.14, label %41, label %67

41:                                               ; preds = %39
  %42 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 240), align 16, !tbaa !13
  %.not.15 = icmp ult i64 %42, %2
  br i1 %.not.15, label %43, label %67

43:                                               ; preds = %41
  %44 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 256), align 16, !tbaa !13
  %.not.16 = icmp ult i64 %44, %2
  br i1 %.not.16, label %45, label %67

45:                                               ; preds = %43
  %46 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 272), align 16, !tbaa !13
  %.not.17 = icmp ult i64 %46, %2
  br i1 %.not.17, label %47, label %67

47:                                               ; preds = %45
  %48 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 288), align 16, !tbaa !13
  %.not.18 = icmp ult i64 %48, %2
  br i1 %.not.18, label %49, label %67

49:                                               ; preds = %47
  %50 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 304), align 16, !tbaa !13
  %.not.19 = icmp ult i64 %50, %2
  br i1 %.not.19, label %51, label %67

51:                                               ; preds = %49
  %52 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 320), align 16, !tbaa !13
  %.not.20 = icmp ult i64 %52, %2
  br i1 %.not.20, label %53, label %67

53:                                               ; preds = %51
  %54 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 336), align 16, !tbaa !13
  %.not.21 = icmp ult i64 %54, %2
  br i1 %.not.21, label %55, label %67

55:                                               ; preds = %53
  %56 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 352), align 16, !tbaa !13
  %.not.22 = icmp ult i64 %56, %2
  br i1 %.not.22, label %57, label %67

57:                                               ; preds = %55
  %58 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 368), align 16, !tbaa !13
  %.not.23 = icmp ult i64 %58, %2
  br i1 %.not.23, label %59, label %67

59:                                               ; preds = %57
  %60 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 384), align 16, !tbaa !13
  %.not.24 = icmp ult i64 %60, %2
  br i1 %.not.24, label %61, label %67

61:                                               ; preds = %59
  %62 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 400), align 16, !tbaa !13
  %.not.25 = icmp ult i64 %62, %2
  br i1 %.not.25, label %63, label %67

63:                                               ; preds = %61
  %64 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 416), align 16, !tbaa !13
  %.not.26 = icmp ult i64 %64, %2
  br i1 %.not.26, label %65, label %67

65:                                               ; preds = %63
  %66 = load i64, ptr getelementptr inbounds (i8, ptr @region_size, i64 432), align 16, !tbaa !13
  %.not.27 = icmp ult i64 %66, %2
  br i1 %.not.27, label %.loopexit, label %67

67:                                               ; preds = %65, %63, %61, %59, %57, %55, %53, %51, %49, %47, %45, %43, %41, %39, %37, %35, %33, %31, %29, %27, %25, %23, %21, %19, %17, %15, %13, %11
  %.lcssa29 = phi i64 [ 0, %11 ], [ 1, %13 ], [ 2, %15 ], [ 3, %17 ], [ 4, %19 ], [ 5, %21 ], [ 6, %23 ], [ 7, %25 ], [ 8, %27 ], [ 9, %29 ], [ 10, %31 ], [ 11, %33 ], [ 12, %35 ], [ 13, %37 ], [ 14, %39 ], [ 15, %41 ], [ 16, %43 ], [ 17, %45 ], [ 18, %47 ], [ 19, %49 ], [ 20, %51 ], [ 21, %53 ], [ 22, %55 ], [ 23, %57 ], [ 24, %59 ], [ 25, %61 ], [ 26, %63 ], [ 27, %65 ]
  %.lcssa = phi ptr [ @region_size, %11 ], [ getelementptr inbounds (i8, ptr @region_size, i64 16), %13 ], [ getelementptr inbounds (i8, ptr @region_size, i64 32), %15 ], [ getelementptr inbounds (i8, ptr @region_size, i64 48), %17 ], [ getelementptr inbounds (i8, ptr @region_size, i64 64), %19 ], [ getelementptr inbounds (i8, ptr @region_size, i64 80), %21 ], [ getelementptr inbounds (i8, ptr @region_size, i64 96), %23 ], [ getelementptr inbounds (i8, ptr @region_size, i64 112), %25 ], [ getelementptr inbounds (i8, ptr @region_size, i64 128), %27 ], [ getelementptr inbounds (i8, ptr @region_size, i64 144), %29 ], [ getelementptr inbounds (i8, ptr @region_size, i64 160), %31 ], [ getelementptr inbounds (i8, ptr @region_size, i64 176), %33 ], [ getelementptr inbounds (i8, ptr @region_size, i64 192), %35 ], [ getelementptr inbounds (i8, ptr @region_size, i64 208), %37 ], [ getelementptr inbounds (i8, ptr @region_size, i64 224), %39 ], [ getelementptr inbounds (i8, ptr @region_size, i64 240), %41 ], [ getelementptr inbounds (i8, ptr @region_size, i64 256), %43 ], [ getelementptr inbounds (i8, ptr @region_size, i64 272), %45 ], [ getelementptr inbounds (i8, ptr @region_size, i64 288), %47 ], [ getelementptr inbounds (i8, ptr @region_size, i64 304), %49 ], [ getelementptr inbounds (i8, ptr @region_size, i64 320), %51 ], [ getelementptr inbounds (i8, ptr @region_size, i64 336), %53 ], [ getelementptr inbounds (i8, ptr @region_size, i64 352), %55 ], [ getelementptr inbounds (i8, ptr @region_size, i64 368), %57 ], [ getelementptr inbounds (i8, ptr @region_size, i64 384), %59 ], [ getelementptr inbounds (i8, ptr @region_size, i64 400), %61 ], [ getelementptr inbounds (i8, ptr @region_size, i64 416), %63 ], [ getelementptr inbounds (i8, ptr @region_size, i64 432), %65 ]
  %68 = getelementptr inbounds i8, ptr %.lcssa, i64 8
  %69 = load i32, ptr %68, align 8, !tbaa !15
  %70 = shl i32 %69, 1
  %71 = or disjoint i32 %70, 1
  br label %.loopexit

.loopexit:                                        ; preds = %65, %67
  %72 = phi i64 [ %.lcssa29, %67 ], [ 28, %65 ]
  %.021 = phi i32 [ %71, %67 ], [ 1, %65 ]
  %73 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %72
  %74 = load i64, ptr %73, align 16, !tbaa !13
  %75 = sub i64 0, %74
  %76 = and i64 %75, %1
  tail call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !16
  tail call void asm sideeffect "msr XREG_CP15_MPU_REG_BASEADDR,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i64 %76) #2, !srcloc !17
  tail call void asm sideeffect "msr XREG_CP15_MPU_REG_ACCESS_CTRL,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %3) #2, !srcloc !18
  tail call void asm sideeffect "msr XREG_CP15_MPU_REG_SIZE_EN,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %.021) #2, !srcloc !19
  tail call void asm sideeffect "dsb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !20
  tail call void asm sideeffect "isb sy", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !21
  %77 = tail call i32 @Xil_UpdateMPUConfig(i32 noundef %0, i64 noundef %76, i32 noundef %.021, i32 noundef %3)
  br label %78

78:                                               ; preds = %6, %4, %.loopexit
  %.022 = phi i32 [ 0, %.loopexit ], [ 1, %4 ], [ 1, %6 ]
  ret i32 %.022
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"XMpuConfig", !7, i64 0, !10, i64 8, !10, i64 16, !7, i64 24}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"long", !8, i64 0}
!11 = !{i64 2147715760}
!12 = !{i64 2147715858}
!13 = !{!14, !10, i64 0}
!14 = !{!"", !10, i64 0, !7, i64 8}
!15 = !{!14, !7, i64 8}
!16 = !{i64 2147715901}
!17 = !{i64 2147715932}
!18 = !{i64 2147716026}
!19 = !{i64 2147716120}
!20 = !{i64 2147716214}
!21 = !{i64 2147716246}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass