; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (IntrClearPin)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8, i32 }
%struct.XGpioPs_Config = type { i16, i64 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [169 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

declare void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_IntrClearPin(ptr noundef %0, i32 noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = icmp ne ptr %9, null
  br i1 %10, label %11, label %12

11:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %13

12:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 409)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %8, align 4
  br label %58

13:                                               ; preds = %11
  %14 = load ptr, ptr %3, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.XGpioPs, ptr %14, i32 0, i32 1
  %16 = load i32, ptr %15, align 8, !tbaa !11
  %17 = icmp eq i32 %16, 286331153
  br i1 %17, label %18, label %19

18:                                               ; preds = %13
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %20

19:                                               ; preds = %13
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 410)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %8, align 4
  br label %58

20:                                               ; preds = %18
  %21 = load i32, ptr %4, align 4, !tbaa !9
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.XGpioPs, ptr %22, i32 0, i32 5
  %24 = load i32, ptr %23, align 4, !tbaa !16
  %25 = icmp ult i32 %21, %24
  br i1 %25, label %26, label %27

26:                                               ; preds = %20
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %28

27:                                               ; preds = %20
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 411)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %8, align 4
  br label %58

28:                                               ; preds = %26
  %29 = load i32, ptr %4, align 4, !tbaa !9
  %30 = trunc i32 %29 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %30, ptr noundef %5, ptr noundef %6)
  %31 = load ptr, ptr %3, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.XGpioPs, ptr %31, i32 0, i32 0
  %33 = getelementptr inbounds %struct.XGpioPs_Config, ptr %32, i32 0, i32 1
  %34 = load i64, ptr %33, align 8, !tbaa !17
  %35 = load i8, ptr %5, align 1, !tbaa !18
  %36 = zext i8 %35 to i32
  %37 = mul i32 %36, 64
  %38 = add i32 %37, 536
  %39 = zext i32 %38 to i64
  %40 = add i64 %34, %39
  %41 = call i32 @Xil_In32(i64 noundef %40)
  store i32 %41, ptr %7, align 4, !tbaa !9
  %42 = load i8, ptr %6, align 1, !tbaa !18
  %43 = zext i8 %42 to i32
  %44 = shl i32 1, %43
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = and i32 %45, %44
  store i32 %46, ptr %7, align 4, !tbaa !9
  %47 = load ptr, ptr %3, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.XGpioPs, ptr %47, i32 0, i32 0
  %49 = getelementptr inbounds %struct.XGpioPs_Config, ptr %48, i32 0, i32 1
  %50 = load i64, ptr %49, align 8, !tbaa !17
  %51 = load i8, ptr %5, align 1, !tbaa !18
  %52 = zext i8 %51 to i32
  %53 = mul i32 %52, 64
  %54 = add i32 %53, 536
  %55 = zext i32 %54 to i64
  %56 = add i64 %50, %55
  %57 = load i32, ptr %7, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %56, i32 noundef %57)
  store i32 0, ptr %8, align 4
  br label %58

58:                                               ; preds = %28, %27, %19, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  %59 = load i32, ptr %8, align 4
  switch i32 %59, label %61 [
    i32 0, label %60
    i32 1, label %60
  ]

60:                                               ; preds = %58, %58
  ret void

61:                                               ; preds = %58
  unreachable
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"", !13, i64 0, !10, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 44, !7, i64 48, !10, i64 52}
!13 = !{!"", !14, i64 0, !15, i64 8}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !10, i64 44}
!17 = !{!12, !15, i64 8}
!18 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [169 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

declare void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_IntrClearPin(ptr noundef readonly %0, i32 noundef %1) local_unnamed_addr #3 {
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #4
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %9, label %5

5:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 16
  %7 = load i32, ptr %6, align 8, !tbaa !9
  %8 = icmp eq i32 %7, 286331153
  br i1 %8, label %10, label %14

9:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 409) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %36

10:                                               ; preds = %5
  %11 = getelementptr inbounds i8, ptr %0, i64 44
  %12 = load i32, ptr %11, align 4, !tbaa !15
  %13 = icmp ugt i32 %12, %1
  br i1 %13, label %15, label %35

14:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 410) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %36

15:                                               ; preds = %10
  %16 = trunc i32 %1 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %16, ptr noundef nonnull %3, ptr noundef nonnull %4) #4
  %17 = getelementptr inbounds i8, ptr %0, i64 8
  %18 = load i64, ptr %17, align 8, !tbaa !16
  %19 = load i8, ptr %3, align 1, !tbaa !17
  %20 = zext i8 %19 to i64
  %21 = shl nuw nsw i64 %20, 6
  %22 = add i64 %18, 536
  %23 = add i64 %22, %21
  %24 = call i32 @Xil_In32(i64 noundef %23)
  %25 = load i8, ptr %4, align 1, !tbaa !17
  %26 = zext nneg i8 %25 to i32
  %27 = shl nuw i32 1, %26
  %28 = and i32 %27, %24
  %29 = load i64, ptr %17, align 8, !tbaa !16
  %30 = load i8, ptr %3, align 1, !tbaa !17
  %31 = zext i8 %30 to i64
  %32 = shl nuw nsw i64 %31, 6
  %33 = add i64 %29, 536
  %34 = add i64 %33, %32
  call void @Xil_Out32(i64 noundef %34, i32 noundef %28)
  br label %36

35:                                               ; preds = %10
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 411) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %36

36:                                               ; preds = %15, %35, %14, %9
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #4
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 16}
!10 = !{!"", !11, i64 0, !6, i64 16, !14, i64 24, !14, i64 32, !6, i64 40, !6, i64 44, !7, i64 48, !6, i64 52}
!11 = !{!"", !12, i64 0, !13, i64 8}
!12 = !{!"short", !7, i64 0}
!13 = !{!"long", !7, i64 0}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!10, !6, i64 44}
!16 = !{!10, !13, i64 8}
!17 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass