; LLVM IR from Izaron/ACM-ICPC :: Russian Olympiad in Informatics/Final Stage 2017/order.ll (Z2goiiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@vec = external dso_local global %"class.std::vector", align 8
@as = external dso_local global %"class.std::vector", align 8
@bs = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_Z2goiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !5
  store i32 %4, ptr %10, align 4, !tbaa !5
  %14 = load i32, ptr %6, align 4, !tbaa !5
  %15 = icmp slt i32 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %5
  br label %99

17:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %18 = load i32, ptr %7, align 4, !tbaa !5
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vec, i64 noundef %19) #3
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = load i32, ptr %6, align 4, !tbaa !5
  %23 = ashr i32 %21, %22
  %24 = and i32 %23, 1
  store i32 %24, ptr %11, align 4, !tbaa !5
  %25 = load i32, ptr %8, align 4, !tbaa !5
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %58

27:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %28 = load i32, ptr %7, align 4, !tbaa !5
  %29 = sub nsw i32 %28, 1
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vec, i64 noundef %30) #3
  %32 = load i32, ptr %31, align 4, !tbaa !5
  %33 = load i32, ptr %6, align 4, !tbaa !5
  %34 = ashr i32 %32, %33
  %35 = and i32 %34, 1
  store i32 %35, ptr %12, align 4, !tbaa !5
  %36 = load i32, ptr %12, align 4, !tbaa !5
  %37 = load i32, ptr %11, align 4, !tbaa !5
  %38 = icmp ne i32 %36, %37
  br i1 %38, label %39, label %57

39:                                               ; preds = %27
  %40 = load i32, ptr %12, align 4, !tbaa !5
  %41 = icmp eq i32 %40, 0
  br i1 %41, label %42, label %49

42:                                               ; preds = %39
  %43 = load i32, ptr %10, align 4, !tbaa !5
  %44 = load i32, ptr %6, align 4, !tbaa !5
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @as, i64 noundef %45) #3
  %47 = load i32, ptr %46, align 4, !tbaa !5
  %48 = add nsw i32 %47, %43
  store i32 %48, ptr %46, align 4, !tbaa !5
  br label %56

49:                                               ; preds = %39
  %50 = load i32, ptr %10, align 4, !tbaa !5
  %51 = load i32, ptr %6, align 4, !tbaa !5
  %52 = sext i32 %51 to i64
  %53 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @bs, i64 noundef %52) #3
  %54 = load i32, ptr %53, align 4, !tbaa !5
  %55 = add nsw i32 %54, %50
  store i32 %55, ptr %53, align 4, !tbaa !5
  br label %56

56:                                               ; preds = %49, %42
  store i32 0, ptr %8, align 4, !tbaa !5
  br label %57

57:                                               ; preds = %56, %27
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %58

58:                                               ; preds = %57, %17
  %59 = load i32, ptr %9, align 4, !tbaa !5
  %60 = icmp eq i32 %59, 1
  br i1 %60, label %61, label %92

61:                                               ; preds = %58
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %62 = load i32, ptr %7, align 4, !tbaa !5
  %63 = add nsw i32 %62, 1
  %64 = sext i32 %63 to i64
  %65 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vec, i64 noundef %64) #3
  %66 = load i32, ptr %65, align 4, !tbaa !5
  %67 = load i32, ptr %6, align 4, !tbaa !5
  %68 = ashr i32 %66, %67
  %69 = and i32 %68, 1
  store i32 %69, ptr %13, align 4, !tbaa !5
  %70 = load i32, ptr %13, align 4, !tbaa !5
  %71 = load i32, ptr %11, align 4, !tbaa !5
  %72 = icmp ne i32 %70, %71
  br i1 %72, label %73, label %91

73:                                               ; preds = %61
  %74 = load i32, ptr %13, align 4, !tbaa !5
  %75 = icmp eq i32 %74, 0
  br i1 %75, label %76, label %83

76:                                               ; preds = %73
  %77 = load i32, ptr %10, align 4, !tbaa !5
  %78 = load i32, ptr %6, align 4, !tbaa !5
  %79 = sext i32 %78 to i64
  %80 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @bs, i64 noundef %79) #3
  %81 = load i32, ptr %80, align 4, !tbaa !5
  %82 = add nsw i32 %81, %77
  store i32 %82, ptr %80, align 4, !tbaa !5
  br label %90

83:                                               ; preds = %73
  %84 = load i32, ptr %10, align 4, !tbaa !5
  %85 = load i32, ptr %6, align 4, !tbaa !5
  %86 = sext i32 %85 to i64
  %87 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @as, i64 noundef %86) #3
  %88 = load i32, ptr %87, align 4, !tbaa !5
  %89 = add nsw i32 %88, %84
  store i32 %89, ptr %87, align 4, !tbaa !5
  br label %90

90:                                               ; preds = %83, %76
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %91

91:                                               ; preds = %90, %61
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  br label %92

92:                                               ; preds = %91, %58
  %93 = load i32, ptr %6, align 4, !tbaa !5
  %94 = sub nsw i32 %93, 1
  %95 = load i32, ptr %7, align 4, !tbaa !5
  %96 = load i32, ptr %8, align 4, !tbaa !5
  %97 = load i32, ptr %9, align 4, !tbaa !5
  %98 = load i32, ptr %10, align 4, !tbaa !5
  call void @_Z2goiiiii(i32 noundef %94, i32 noundef %95, i32 noundef %96, i32 noundef %97, i32 noundef %98)
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %99

99:                                               ; preds = %92, %16
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@vec = external dso_local global %"class.std::vector", align 8
@as = external dso_local global %"class.std::vector", align 8
@bs = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z2goiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = icmp slt i32 %0, 0
  br i1 %6, label %tailrecurse._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %5
  %7 = sext i32 %1 to i64
  %8 = add nsw i32 %1, -1
  %9 = sext i32 %8 to i64
  %10 = add nsw i32 %1, 1
  %11 = sext i32 %10 to i64
  %12 = zext nneg i32 %0 to i64
  br label %13

13:                                               ; preds = %.lr.ph, %tailrecurse
  %indvars.iv = phi i64 [ %12, %.lr.ph ], [ %indvars.iv.next, %tailrecurse ]
  %.tr4044 = phi i32 [ %3, %.lr.ph ], [ %.129, %tailrecurse ]
  %.tr3943 = phi i32 [ %2, %.lr.ph ], [ %.1, %tailrecurse ]
  %14 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vec, i64 noundef %7) #1
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = trunc nuw nsw i64 %indvars.iv to i32
  %17 = lshr i32 %15, %16
  %18 = and i32 %17, 1
  %19 = icmp eq i32 %.tr3943, 1
  br i1 %19, label %20, label %29

20:                                               ; preds = %13
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vec, i64 noundef %9) #1
  %22 = load i32, ptr %21, align 4, !tbaa !5
  %23 = lshr i32 %22, %16
  %24 = and i32 %23, 1
  %.not = icmp eq i32 %24, %18
  br i1 %.not, label %29, label %.sink.split

.sink.split:                                      ; preds = %20
  %25 = icmp eq i32 %24, 0
  %as.bs = select i1 %25, ptr @as, ptr @bs
  %26 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %as.bs, i64 noundef %indvars.iv) #1
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = add nsw i32 %27, %4
  store i32 %28, ptr %26, align 4, !tbaa !5
  br label %29

29:                                               ; preds = %.sink.split, %20, %13
  %.1 = phi i32 [ %.tr3943, %13 ], [ 1, %20 ], [ 0, %.sink.split ]
  %30 = icmp eq i32 %.tr4044, 1
  br i1 %30, label %31, label %tailrecurse

31:                                               ; preds = %29
  %32 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vec, i64 noundef %11) #1
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = lshr i32 %33, %16
  %35 = and i32 %34, 1
  %.not37 = icmp eq i32 %35, %18
  br i1 %.not37, label %tailrecurse, label %tailrecurse.sink.split

tailrecurse.sink.split:                           ; preds = %31
  %36 = icmp eq i32 %35, 0
  %bs.as = select i1 %36, ptr @bs, ptr @as
  %37 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %bs.as, i64 noundef %indvars.iv) #1
  %38 = load i32, ptr %37, align 4, !tbaa !5
  %39 = add nsw i32 %38, %4
  store i32 %39, ptr %37, align 4, !tbaa !5
  br label %tailrecurse

tailrecurse:                                      ; preds = %tailrecurse.sink.split, %31, %29
  %.129 = phi i32 [ %.tr4044, %29 ], [ 1, %31 ], [ 0, %tailrecurse.sink.split ]
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %40 = icmp slt i64 %indvars.iv, 1
  br i1 %40, label %tailrecurse._crit_edge, label %13

tailrecurse._crit_edge:                           ; preds = %tailrecurse, %5
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass