; LLVM IR from tangjz/acm-icpc :: codechef/OCT13/MAANDI.ll (Z5luckyi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5luckyi(i32 noundef %0) #0 {
  %2 = alloca i1, align 1
  %3 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  br label %4

4:                                                ; preds = %16, %1
  %5 = load i32, ptr %3, align 4, !tbaa !5
  %6 = icmp ne i32 %5, 0
  br i1 %6, label %7, label %19

7:                                                ; preds = %4
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = srem i32 %8, 10
  %10 = icmp eq i32 %9, 4
  br i1 %10, label %15, label %11

11:                                               ; preds = %7
  %12 = load i32, ptr %3, align 4, !tbaa !5
  %13 = srem i32 %12, 10
  %14 = icmp eq i32 %13, 7
  br i1 %14, label %15, label %16

15:                                               ; preds = %11, %7
  store i1 true, ptr %2, align 1
  br label %20

16:                                               ; preds = %11
  %17 = load i32, ptr %3, align 4, !tbaa !5
  %18 = sdiv i32 %17, 10
  store i32 %18, ptr %3, align 4, !tbaa !5
  br label %4, !llvm.loop !9

19:                                               ; preds = %4
  store i1 false, ptr %2, align 1
  br label %20

20:                                               ; preds = %19, %15
  %21 = load i1, ptr %2, align 1
  ret i1 %21
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local noundef zeroext i1 @_Z5luckyi(i32 noundef %0) local_unnamed_addr #0 {
  %.not6.not = icmp eq i32 %0, 0
  br i1 %.not6.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %1, %4
  %.07 = phi i32 [ %3, %4 ], [ %0, %1 ]
  %2 = srem i32 %.07, 10
  %3 = sdiv i32 %.07, 10
  switch i32 %2, label %4 [
    i32 4, label %._crit_edge
    i32 7, label %._crit_edge
  ]

4:                                                ; preds = %.lr.ph
  %5 = add i32 %.07, -10
  %.not = icmp ult i32 %5, -19
  br i1 %.not, label %.lr.ph, label %._crit_edge, !llvm.loop !5

._crit_edge:                                      ; preds = %.lr.ph, %.lr.ph, %4, %1
  %.not.lcssa = phi i1 [ false, %1 ], [ false, %4 ], [ true, %.lr.ph ], [ true, %.lr.ph ]
  ret i1 %.not.lcssa
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DivRemPairsPass,EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass