; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (EpBufferSend)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XUsbPs = type { %struct.XUsbPs_SetupData, %struct.XUsbPs_Config, i32, ptr, %struct.XUsbPs_DeviceConfig, ptr, ptr, i32, ptr, i8, ptr }
%struct.XUsbPs_SetupData = type { i8, i8, i16, i16, i16 }
%struct.XUsbPs_Config = type { i16, i32 }
%struct.XUsbPs_DeviceConfig = type { i8, [12 x %struct.XUsbPs_EpConfig], i32, [12 x %struct.XUsbPs_Endpoint], i32 }
%struct.XUsbPs_EpConfig = type { %struct.XUsbPs_EpSetup, %struct.XUsbPs_EpSetup }
%struct.XUsbPs_EpSetup = type { i32, i32, i32, i16 }
%struct.XUsbPs_Endpoint = type { %struct.XUsbPs_EpOut, %struct.XUsbPs_EpIn }
%struct.XUsbPs_EpOut = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i8, i32 }
%struct.XUsbPs_EpIn = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XUsbPs_EpBufferSend(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i8 %1, ptr %7, align 1, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !10
  %10 = load ptr, ptr %6, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %14

13:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 174)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %31

14:                                               ; preds = %12
  %15 = load i8, ptr %7, align 1, !tbaa !9
  %16 = zext i8 %15 to i32
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.XUsbPs, ptr %17, i32 0, i32 4
  %19 = getelementptr inbounds %struct.XUsbPs_DeviceConfig, ptr %18, i32 0, i32 0
  %20 = load i8, ptr %19, align 8, !tbaa !12
  %21 = zext i8 %20 to i32
  %22 = icmp slt i32 %16, %21
  br i1 %22, label %23, label %24

23:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %25

24:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 175)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %5, align 4
  br label %31

25:                                               ; preds = %23
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = load i8, ptr %7, align 1, !tbaa !9
  %28 = load ptr, ptr %8, align 8, !tbaa !5
  %29 = load i32, ptr %9, align 4, !tbaa !10
  %30 = call i32 @XUsbPs_EpQueueRequest(ptr noundef %26, i8 noundef zeroext %27, ptr noundef %28, i32 noundef %29, i8 noundef zeroext 0)
  store i32 %30, ptr %5, align 4
  br label %31

31:                                               ; preds = %25, %24, %13
  %32 = load i32, ptr %5, align 4
  ret i32 %32
}

; Function Attrs: nounwind uwtable
declare hidden i32 @XUsbPs_EpQueueRequest(ptr noundef, i8 noundef zeroext, ptr noundef, i32 noundef, i8 noundef zeroext) #1

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !7, i64 32}
!13 = !{!"", !14, i64 0, !16, i64 8, !11, i64 16, !6, i64 24, !17, i64 32, !6, i64 2352, !6, i64 2360, !11, i64 2368, !6, i64 2376, !7, i64 2384, !6, i64 2392}
!14 = !{!"", !7, i64 0, !7, i64 1, !15, i64 2, !15, i64 4, !15, i64 6}
!15 = !{!"short", !7, i64 0}
!16 = !{!"", !15, i64 0, !11, i64 4}
!17 = !{!"", !7, i64 0, !7, i64 4, !11, i64 388, !7, i64 392, !11, i64 2312}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XUsbPs_EpBufferSend(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %9, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 32
  %7 = load i8, ptr %6, align 8, !tbaa !9
  %8 = icmp ugt i8 %7, %1
  br i1 %8, label %10, label %12

9:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 174) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %13

10:                                               ; preds = %5
  %11 = tail call i32 @XUsbPs_EpQueueRequest(ptr noundef nonnull %0, i8 noundef zeroext %1, ptr noundef %2, i32 noundef %3, i8 noundef zeroext 0)
  br label %13

12:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 175) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %10, %12, %9
  %.0 = phi i32 [ %11, %10 ], [ 0, %12 ], [ 0, %9 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden i32 @XUsbPs_EpQueueRequest(ptr noundef, i8 noundef zeroext, ptr noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !7, i64 32}
!10 = !{!"", !11, i64 0, !13, i64 8, !6, i64 16, !14, i64 24, !15, i64 32, !14, i64 2352, !14, i64 2360, !6, i64 2368, !14, i64 2376, !7, i64 2384, !14, i64 2392}
!11 = !{!"", !7, i64 0, !7, i64 1, !12, i64 2, !12, i64 4, !12, i64 6}
!12 = !{!"short", !7, i64 0}
!13 = !{!"", !12, i64 0, !6, i64 4}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!"", !7, i64 0, !7, i64 4, !6, i64 388, !7, i64 392, !6, i64 2312}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass