; LLVM IR from tangjz/acm-icpc :: 51nod/1426.ll (Z7seg_queiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Seg = type { i32, i32, i32 }

@seg = external dso_local global [2000003 x %struct.Seg], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7seg_idxii(i32 noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local { i64, i32 } @_Z9seg_mergeRK3SegS1_(ptr noundef nonnull align 4 dereferenceable(12), ptr noundef nonnull align 4 dereferenceable(12)) #3

; Function Attrs: mustprogress uwtable
define dso_local { i64, i32 } @_Z7seg_queiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #4 {
  %5 = alloca %struct.Seg, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca { i64, i32 }, align 8
  %16 = alloca { i64, i32 }, align 8
  %17 = alloca %struct.Seg, align 4
  %18 = alloca { i64, i32 }, align 8
  %19 = alloca %struct.Seg, align 4
  %20 = alloca { i64, i32 }, align 8
  %21 = alloca { i64, i32 }, align 8
  %22 = alloca { i64, i32 }, align 8
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %23 = load i32, ptr %6, align 4, !tbaa !5
  %24 = load i32, ptr %7, align 4, !tbaa !5
  %25 = call noundef i32 @_Z7seg_idxii(i32 noundef %23, i32 noundef %24)
  store i32 %25, ptr %10, align 4, !tbaa !5
  %26 = load i32, ptr %8, align 4, !tbaa !5
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = icmp sle i32 %26, %27
  br i1 %28, label %29, label %37

29:                                               ; preds = %4
  %30 = load i32, ptr %7, align 4, !tbaa !5
  %31 = load i32, ptr %9, align 4, !tbaa !5
  %32 = icmp sle i32 %30, %31
  br i1 %32, label %33, label %37

33:                                               ; preds = %29
  %34 = load i32, ptr %10, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = getelementptr inbounds [2000003 x %struct.Seg], ptr @seg, i64 0, i64 %35
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %5, ptr align 4 %36, i64 12, i1 false), !tbaa.struct !9
  store i32 1, ptr %11, align 4
  br label %83

37:                                               ; preds = %29, %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  %38 = load i32, ptr %6, align 4, !tbaa !5
  %39 = load i32, ptr %7, align 4, !tbaa !5
  %40 = add nsw i32 %38, %39
  %41 = ashr i32 %40, 1
  store i32 %41, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  %42 = load i32, ptr %6, align 4, !tbaa !5
  %43 = load i32, ptr %12, align 4, !tbaa !5
  %44 = call noundef i32 @_Z7seg_idxii(i32 noundef %42, i32 noundef %43)
  store i32 %44, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #5
  %45 = load i32, ptr %12, align 4, !tbaa !5
  %46 = add nsw i32 %45, 1
  %47 = load i32, ptr %7, align 4, !tbaa !5
  %48 = call noundef i32 @_Z7seg_idxii(i32 noundef %46, i32 noundef %47)
  store i32 %48, ptr %14, align 4, !tbaa !5
  %49 = load i32, ptr %9, align 4, !tbaa !5
  %50 = load i32, ptr %12, align 4, !tbaa !5
  %51 = icmp sle i32 %49, %50
  br i1 %51, label %52, label %58

52:                                               ; preds = %37
  %53 = load i32, ptr %6, align 4, !tbaa !5
  %54 = load i32, ptr %12, align 4, !tbaa !5
  %55 = load i32, ptr %8, align 4, !tbaa !5
  %56 = load i32, ptr %9, align 4, !tbaa !5
  %57 = call { i64, i32 } @_Z7seg_queiiii(i32 noundef %53, i32 noundef %54, i32 noundef %55, i32 noundef %56)
  store { i64, i32 } %57, ptr %15, align 8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %5, ptr align 8 %15, i64 12, i1 false)
  store i32 1, ptr %11, align 4
  br label %82

58:                                               ; preds = %37
  %59 = load i32, ptr %8, align 4, !tbaa !5
  %60 = load i32, ptr %12, align 4, !tbaa !5
  %61 = icmp sgt i32 %59, %60
  br i1 %61, label %62, label %69

62:                                               ; preds = %58
  %63 = load i32, ptr %12, align 4, !tbaa !5
  %64 = add nsw i32 %63, 1
  %65 = load i32, ptr %7, align 4, !tbaa !5
  %66 = load i32, ptr %8, align 4, !tbaa !5
  %67 = load i32, ptr %9, align 4, !tbaa !5
  %68 = call { i64, i32 } @_Z7seg_queiiii(i32 noundef %64, i32 noundef %65, i32 noundef %66, i32 noundef %67)
  store { i64, i32 } %68, ptr %16, align 8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %5, ptr align 8 %16, i64 12, i1 false)
  store i32 1, ptr %11, align 4
  br label %82

69:                                               ; preds = %58
  call void @llvm.lifetime.start.p0(i64 12, ptr %17) #5
  %70 = load i32, ptr %6, align 4, !tbaa !5
  %71 = load i32, ptr %12, align 4, !tbaa !5
  %72 = load i32, ptr %8, align 4, !tbaa !5
  %73 = load i32, ptr %9, align 4, !tbaa !5
  %74 = call { i64, i32 } @_Z7seg_queiiii(i32 noundef %70, i32 noundef %71, i32 noundef %72, i32 noundef %73)
  store { i64, i32 } %74, ptr %18, align 8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %17, ptr align 8 %18, i64 12, i1 false)
  call void @llvm.lifetime.start.p0(i64 12, ptr %19) #5
  %75 = load i32, ptr %12, align 4, !tbaa !5
  %76 = add nsw i32 %75, 1
  %77 = load i32, ptr %7, align 4, !tbaa !5
  %78 = load i32, ptr %8, align 4, !tbaa !5
  %79 = load i32, ptr %9, align 4, !tbaa !5
  %80 = call { i64, i32 } @_Z7seg_queiiii(i32 noundef %76, i32 noundef %77, i32 noundef %78, i32 noundef %79)
  store { i64, i32 } %80, ptr %20, align 8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %19, ptr align 8 %20, i64 12, i1 false)
  %81 = call { i64, i32 } @_Z9seg_mergeRK3SegS1_(ptr noundef nonnull align 4 dereferenceable(12) %17, ptr noundef nonnull align 4 dereferenceable(12) %19)
  store { i64, i32 } %81, ptr %21, align 8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %5, ptr align 8 %21, i64 12, i1 false)
  call void @llvm.lifetime.end.p0(i64 12, ptr %19) #5
  call void @llvm.lifetime.end.p0(i64 12, ptr %17) #5
  store i32 1, ptr %11, align 4
  br label %82

82:                                               ; preds = %69, %62, %52
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  br label %83

83:                                               ; preds = %82, %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %22, ptr align 4 %5, i64 12, i1 false)
  %84 = load { i64, i32 }, ptr %22, align 8
  ret { i64, i32 } %84
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i64 0, i64 4, !5, i64 4, i64 4, !5, i64 8, i64 4, !5}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Seg = type { i32, i32, i32 }

@seg = external dso_local local_unnamed_addr global [2000003 x %struct.Seg], align 16

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7seg_idxii(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local { i64, i32 } @_Z9seg_mergeRK3SegS1_(ptr noundef nonnull align 4 dereferenceable(12), ptr noundef nonnull align 4 dereferenceable(12)) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local { i64, i32 } @_Z7seg_queiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #3 {
  %5 = alloca %struct.Seg, align 8
  %6 = alloca %struct.Seg, align 8
  %7 = tail call noundef i32 @_Z7seg_idxii(i32 noundef %0, i32 noundef %1)
  %.not = icmp sgt i32 %2, %0
  %.not56 = icmp sgt i32 %1, %3
  %or.cond = or i1 %.not, %.not56
  br i1 %or.cond, label %11, label %8

8:                                                ; preds = %4
  %9 = sext i32 %7 to i64
  %10 = getelementptr inbounds [2000003 x %struct.Seg], ptr @seg, i64 0, i64 %9
  %.sroa.051.0.copyload = load i64, ptr %10, align 4
  %.sroa.5.0..sroa_idx = getelementptr inbounds i8, ptr %10, i64 8
  %.sroa.5.0.copyload = load i32, ptr %.sroa.5.0..sroa_idx, align 4, !tbaa !5
  br label %28

11:                                               ; preds = %4
  %12 = add nsw i32 %1, %0
  %13 = ashr i32 %12, 1
  %14 = tail call noundef i32 @_Z7seg_idxii(i32 noundef %0, i32 noundef %13)
  %15 = add nsw i32 %13, 1
  %16 = tail call noundef i32 @_Z7seg_idxii(i32 noundef %15, i32 noundef %1)
  %.not57 = icmp slt i32 %13, %3
  br i1 %.not57, label %19, label %17

17:                                               ; preds = %11
  %18 = tail call { i64, i32 } @_Z7seg_queiiii(i32 noundef %0, i32 noundef %13, i32 noundef %2, i32 noundef %3)
  br label %27

19:                                               ; preds = %11
  %20 = icmp slt i32 %13, %2
  br i1 %20, label %21, label %23

21:                                               ; preds = %19
  %22 = tail call { i64, i32 } @_Z7seg_queiiii(i32 noundef %15, i32 noundef %1, i32 noundef %2, i32 noundef %3)
  br label %27

23:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 12, ptr nonnull %5) #4
  %24 = tail call { i64, i32 } @_Z7seg_queiiii(i32 noundef %0, i32 noundef %13, i32 noundef %2, i32 noundef %3)
  %.fca.0.extract7 = extractvalue { i64, i32 } %24, 0
  %.fca.1.extract8 = extractvalue { i64, i32 } %24, 1
  store i64 %.fca.0.extract7, ptr %5, align 8
  %.sroa.210.0..sroa_idx = getelementptr inbounds i8, ptr %5, i64 8
  store i32 %.fca.1.extract8, ptr %.sroa.210.0..sroa_idx, align 8
  call void @llvm.lifetime.start.p0(i64 12, ptr nonnull %6) #4
  %25 = tail call { i64, i32 } @_Z7seg_queiiii(i32 noundef %15, i32 noundef %1, i32 noundef %2, i32 noundef %3)
  %.fca.0.extract3 = extractvalue { i64, i32 } %25, 0
  %.fca.1.extract4 = extractvalue { i64, i32 } %25, 1
  store i64 %.fca.0.extract3, ptr %6, align 8
  %.sroa.26.0..sroa_idx = getelementptr inbounds i8, ptr %6, i64 8
  store i32 %.fca.1.extract4, ptr %.sroa.26.0..sroa_idx, align 8
  %26 = call { i64, i32 } @_Z9seg_mergeRK3SegS1_(ptr noundef nonnull align 4 dereferenceable(12) %5, ptr noundef nonnull align 4 dereferenceable(12) %6)
  call void @llvm.lifetime.end.p0(i64 12, ptr nonnull %6) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr nonnull %5) #4
  br label %27

27:                                               ; preds = %23, %21, %17
  %.pn = phi { i64, i32 } [ %18, %17 ], [ %22, %21 ], [ %26, %23 ]
  %.sroa.5.0 = extractvalue { i64, i32 } %.pn, 1
  %.sroa.051.0 = extractvalue { i64, i32 } %.pn, 0
  br label %28

28:                                               ; preds = %27, %8
  %.sroa.051.1 = phi i64 [ %.sroa.051.0.copyload, %8 ], [ %.sroa.051.0, %27 ]
  %.sroa.5.1 = phi i32 [ %.sroa.5.0.copyload, %8 ], [ %.sroa.5.0, %27 ]
  %.fca.0.insert = insertvalue { i64, i32 } poison, i64 %.sroa.051.1, 0
  %.fca.1.insert = insertvalue { i64, i32 } %.fca.0.insert, i32 %.sroa.5.1, 1
  ret { i64, i32 } %.fca.1.insert
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass