; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (InterruptUnmapFromCpuByDistAddr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_InterruptUnmapFromCpuByDistAddr(i32 noundef %0, i8 noundef zeroext %1, i32 noundef %2) #3 {
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %10 = load i32, ptr %6, align 4, !tbaa !5
  %11 = icmp ult i32 %10, 95
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %14

13:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 742)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %9, align 4
  br label %45

14:                                               ; preds = %12
  %15 = load i32, ptr %4, align 4, !tbaa !5
  %16 = load i32, ptr %6, align 4, !tbaa !5
  %17 = udiv i32 %16, 4
  %18 = mul i32 %17, 4
  %19 = add i32 2048, %18
  %20 = add i32 %15, %19
  %21 = zext i32 %20 to i64
  %22 = call i32 @Xil_In32(i64 noundef %21)
  store i32 %22, ptr %7, align 4, !tbaa !5
  %23 = load i32, ptr %6, align 4, !tbaa !5
  %24 = and i32 %23, 3
  store i32 %24, ptr %8, align 4, !tbaa !5
  %25 = load i8, ptr %5, align 1, !tbaa !9
  %26 = zext i8 %25 to i32
  %27 = shl i32 1, %26
  %28 = trunc i32 %27 to i8
  store i8 %28, ptr %5, align 1, !tbaa !9
  %29 = load i8, ptr %5, align 1, !tbaa !9
  %30 = zext i8 %29 to i32
  %31 = load i32, ptr %8, align 4, !tbaa !5
  %32 = mul i32 %31, 8
  %33 = shl i32 %30, %32
  %34 = xor i32 %33, -1
  %35 = load i32, ptr %7, align 4, !tbaa !5
  %36 = and i32 %35, %34
  store i32 %36, ptr %7, align 4, !tbaa !5
  %37 = load i32, ptr %4, align 4, !tbaa !5
  %38 = load i32, ptr %6, align 4, !tbaa !5
  %39 = udiv i32 %38, 4
  %40 = mul i32 %39, 4
  %41 = add i32 2048, %40
  %42 = add i32 %37, %41
  %43 = zext i32 %42 to i64
  %44 = load i32, ptr %7, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %43, i32 noundef %44)
  store i32 0, ptr %9, align 4
  br label %45

45:                                               ; preds = %14, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  %46 = load i32, ptr %9, align 4
  switch i32 %46, label %48 [
    i32 0, label %47
    i32 1, label %47
  ]

47:                                               ; preds = %45, %45
  ret void

48:                                               ; preds = %45
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_InterruptUnmapFromCpuByDistAddr(i32 noundef %0, i8 noundef zeroext %1, i32 noundef %2) local_unnamed_addr #2 {
  %4 = icmp ult i32 %2, 95
  br i1 %4, label %5, label %19

5:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = and i32 %2, 124
  %7 = add i32 %0, 2048
  %8 = add i32 %7, %6
  %9 = zext i32 %8 to i64
  %10 = tail call i32 @Xil_In32(i64 noundef %9)
  %11 = zext nneg i8 %1 to i32
  %12 = shl nuw i32 1, %11
  %13 = and i32 %12, 255
  %14 = shl nuw nsw i32 %2, 3
  %15 = and i32 %14, 24
  %16 = shl nuw i32 %13, %15
  %17 = xor i32 %16, -1
  %18 = and i32 %10, %17
  tail call void @Xil_Out32(i64 noundef %9, i32 noundef %18)
  br label %20

19:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 742) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

20:                                               ; preds = %5, %19
  ret void
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass