; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (DCacheInvalidate)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_stack_end = external global i32, align 4
@__undef_stack = external global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheInvalidate() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  store i32 ptrtoint (ptr @_stack_end to i32), ptr %15, align 4, !tbaa !5
  store i32 ptrtoint (ptr @__undef_stack to i32), ptr %14, align 4, !tbaa !5
  %23 = load i32, ptr %14, align 4, !tbaa !5
  %24 = load i32, ptr %15, align 4, !tbaa !5
  %25 = sub i32 %23, %24
  store i32 %25, ptr %16, align 4, !tbaa !5
  %26 = load i32, ptr %15, align 4, !tbaa !5
  %27 = zext i32 %26 to i64
  %28 = load i32, ptr %16, align 4, !tbaa !5
  call void @Xil_DCacheFlushRange(i64 noundef %27, i32 noundef %28)
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #2
  store i32 0, ptr %17, align 4, !tbaa !5
  %29 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !9
  store i32 %29, ptr %17, align 4, !tbaa !5
  %30 = load i32, ptr %17, align 4, !tbaa !5
  store i32 %30, ptr %18, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #2
  %31 = load i32, ptr %18, align 4, !tbaa !5
  store i32 %31, ptr %13, align 4, !tbaa !5
  %32 = load i32, ptr %13, align 4, !tbaa !5
  %33 = or i32 %32, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %33) #2, !srcloc !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #2
  store i32 0, ptr %19, align 4, !tbaa !5
  %34 = call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 1\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !11
  store i32 %34, ptr %19, align 4, !tbaa !5
  %35 = load i32, ptr %19, align 4, !tbaa !5
  store i32 %35, ptr %20, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #2
  %36 = load i32, ptr %20, align 4, !tbaa !5
  %37 = lshr i32 %36, 24
  %38 = and i32 %37, 7
  store i32 %38, ptr %11, align 4, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !5
  store i32 30, ptr %7, align 4, !tbaa !5
  br label %39

39:                                               ; preds = %96, %0
  %40 = load i32, ptr %12, align 4, !tbaa !5
  %41 = load i32, ptr %11, align 4, !tbaa !5
  %42 = icmp ult i32 %40, %41
  br i1 %42, label %43, label %101

43:                                               ; preds = %39
  %44 = load i32, ptr %12, align 4, !tbaa !5
  %45 = shl i32 %44, 1
  %46 = or i32 %45, 0
  call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %46) #2, !srcloc !12
  call void asm sideeffect "isb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #2
  store i32 0, ptr %21, align 4, !tbaa !5
  %47 = call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !14
  store i32 %47, ptr %21, align 4, !tbaa !5
  %48 = load i32, ptr %21, align 4, !tbaa !5
  store i32 %48, ptr %22, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #2
  %49 = load i32, ptr %22, align 4, !tbaa !5
  store i32 %49, ptr %1, align 4, !tbaa !5
  %50 = load i32, ptr %1, align 4, !tbaa !5
  %51 = and i32 %50, 7
  %52 = add i32 %51, 4
  store i32 %52, ptr %3, align 4, !tbaa !5
  %53 = load i32, ptr %1, align 4, !tbaa !5
  %54 = and i32 %53, 8191
  %55 = lshr i32 %54, 3
  store i32 %55, ptr %4, align 4, !tbaa !5
  %56 = load i32, ptr %4, align 4, !tbaa !5
  %57 = add i32 %56, 1
  store i32 %57, ptr %4, align 4, !tbaa !5
  %58 = load i32, ptr %1, align 4, !tbaa !5
  %59 = lshr i32 %58, 13
  %60 = and i32 %59, 32767
  store i32 %60, ptr %10, align 4, !tbaa !5
  %61 = load i32, ptr %10, align 4, !tbaa !5
  %62 = add i32 %61, 1
  store i32 %62, ptr %10, align 4, !tbaa !5
  store i32 0, ptr %5, align 4, !tbaa !5
  store i32 0, ptr %8, align 4, !tbaa !5
  store i32 0, ptr %6, align 4, !tbaa !5
  br label %63

63:                                               ; preds = %92, %43
  %64 = load i32, ptr %6, align 4, !tbaa !5
  %65 = load i32, ptr %4, align 4, !tbaa !5
  %66 = icmp ult i32 %64, %65
  br i1 %66, label %67, label %95

67:                                               ; preds = %63
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %68

68:                                               ; preds = %84, %67
  %69 = load i32, ptr %9, align 4, !tbaa !5
  %70 = load i32, ptr %10, align 4, !tbaa !5
  %71 = icmp ult i32 %69, %70
  br i1 %71, label %72, label %87

72:                                               ; preds = %68
  %73 = load i32, ptr %5, align 4, !tbaa !5
  %74 = load i32, ptr %8, align 4, !tbaa !5
  %75 = or i32 %73, %74
  %76 = load i32, ptr %12, align 4, !tbaa !5
  %77 = shl i32 %76, 1
  %78 = or i32 %75, %77
  store i32 %78, ptr %2, align 4, !tbaa !5
  %79 = load i32, ptr %2, align 4, !tbaa !5
  call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 2\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %79) #2, !srcloc !15
  %80 = load i32, ptr %3, align 4, !tbaa !5
  %81 = shl i32 1, %80
  %82 = load i32, ptr %8, align 4, !tbaa !5
  %83 = add i32 %82, %81
  store i32 %83, ptr %8, align 4, !tbaa !5
  br label %84

84:                                               ; preds = %72
  %85 = load i32, ptr %9, align 4, !tbaa !5
  %86 = add i32 %85, 1
  store i32 %86, ptr %9, align 4, !tbaa !5
  br label %68, !llvm.loop !16

87:                                               ; preds = %68
  store i32 0, ptr %8, align 4, !tbaa !5
  %88 = load i32, ptr %7, align 4, !tbaa !5
  %89 = shl i32 1, %88
  %90 = load i32, ptr %5, align 4, !tbaa !5
  %91 = add i32 %90, %89
  store i32 %91, ptr %5, align 4, !tbaa !5
  br label %92

92:                                               ; preds = %87
  %93 = load i32, ptr %6, align 4, !tbaa !5
  %94 = add i32 %93, 1
  store i32 %94, ptr %6, align 4, !tbaa !5
  br label %63, !llvm.loop !18

95:                                               ; preds = %63
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !19
  br label %96

96:                                               ; preds = %95
  %97 = load i32, ptr %12, align 4, !tbaa !5
  %98 = add i32 %97, 1
  store i32 %98, ptr %12, align 4, !tbaa !5
  %99 = load i32, ptr %7, align 4, !tbaa !5
  %100 = sub i32 %99, 2
  store i32 %100, ptr %7, align 4, !tbaa !5
  br label %39, !llvm.loop !20

101:                                              ; preds = %39
  %102 = load i32, ptr %13, align 4, !tbaa !5
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %102) #2, !srcloc !21
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 2147860035}
!10 = !{i64 2147860131}
!11 = !{i64 2147860254}
!12 = !{i64 2147860396}
!13 = !{i64 2147860536}
!14 = !{i64 2147860610}
!15 = !{i64 2147860752}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = distinct !{!18, !17}
!19 = !{i64 2147860871}
!20 = distinct !{!20, !17}
!21 = !{i64 2147860921}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_stack_end = external global i32, align 4
@__undef_stack = external global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheInvalidate() local_unnamed_addr #0 {
  %1 = zext i32 ptrtoint (ptr @_stack_end to i32) to i64
  tail call void @Xil_DCacheFlushRange(i64 noundef %1, i32 noundef sub (i32 ptrtoint (ptr @__undef_stack to i32), i32 ptrtoint (ptr @_stack_end to i32)))
  %2 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !5
  %3 = or i32 %2, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %3) #1, !srcloc !6
  %4 = tail call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 1\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !7
  %5 = lshr i32 %4, 24
  %6 = and i32 %5, 7
  %.not48 = icmp eq i32 %6, 0
  br i1 %.not48, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %0, %24
  %.03747 = phi i32 [ %26, %24 ], [ 30, %0 ]
  %.04046 = phi i32 [ %25, %24 ], [ 0, %0 ]
  %7 = shl nuw nsw i32 %.04046, 1
  tail call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %7) #1, !srcloc !8
  tail call void asm sideeffect "isb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !9
  %8 = tail call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !10
  %9 = and i32 %8, 7
  %10 = lshr i32 %8, 3
  %11 = and i32 %10, 1023
  %12 = lshr i32 %8, 13
  %13 = and i32 %12, 32767
  %14 = shl nuw nsw i32 16, %9
  %15 = shl nuw i32 1, %.03747
  br label %.preheader

.preheader:                                       ; preds = %.lr.ph, %21
  %.045 = phi i32 [ 0, %.lr.ph ], [ %22, %21 ]
  %.03644 = phi i32 [ 0, %.lr.ph ], [ %23, %21 ]
  %16 = or i32 %.045, %7
  br label %17

17:                                               ; preds = %.preheader, %17
  %.143 = phi i32 [ 0, %.preheader ], [ %19, %17 ]
  %.03942 = phi i32 [ 0, %.preheader ], [ %20, %17 ]
  %18 = or i32 %16, %.143
  tail call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 2\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %18) #1, !srcloc !11
  %19 = add nuw nsw i32 %.143, %14
  %20 = add nuw nsw i32 %.03942, 1
  %exitcond.not = icmp eq i32 %.03942, %13
  br i1 %exitcond.not, label %21, label %17, !llvm.loop !12

21:                                               ; preds = %17
  %22 = add i32 %.045, %15
  %23 = add nuw nsw i32 %.03644, 1
  %exitcond49.not = icmp eq i32 %.03644, %11
  br i1 %exitcond49.not, label %24, label %.preheader, !llvm.loop !14

24:                                               ; preds = %21
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !15
  %25 = add nuw nsw i32 %.04046, 1
  %26 = add nsw i32 %.03747, -2
  %exitcond50.not = icmp eq i32 %25, %6
  br i1 %exitcond50.not, label %._crit_edge, label %.lr.ph, !llvm.loop !16

._crit_edge:                                      ; preds = %24, %0
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %2) #1, !srcloc !17
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147860035}
!6 = !{i64 2147860131}
!7 = !{i64 2147860254}
!8 = !{i64 2147860396}
!9 = !{i64 2147860536}
!10 = !{i64 2147860610}
!11 = !{i64 2147860752}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}
!15 = !{i64 2147860871}
!16 = distinct !{!16, !13}
!17 = !{i64 2147860921}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass