; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (BusSpeed)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [169 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local i32 @XSdPs_Change_ClkFreq(ptr noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @usleep(i64 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i8 @XSdPs_ReadReg8(i32 noundef, i8 noundef zeroext) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg8(i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_Change_BusSpeed(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = icmp ne ptr %7, null
  br i1 %8, label %9, label %10

9:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %11

10:                                               ; preds = %1
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 475)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %90

11:                                               ; preds = %9
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.XSdPs, ptr %12, i32 0, i32 1
  %14 = load i32, ptr %13, align 4, !tbaa !11
  %15 = icmp eq i32 %14, 286331153
  br i1 %15, label %16, label %17

16:                                               ; preds = %11
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %18

17:                                               ; preds = %11
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 476)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %90

18:                                               ; preds = %16
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.XSdPs, ptr %19, i32 0, i32 5
  %21 = load i8, ptr %20, align 4, !tbaa !16
  %22 = zext i8 %21 to i32
  %23 = icmp eq i32 %22, 1
  br i1 %23, label %24, label %32

24:                                               ; preds = %18
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  %26 = call i32 @XSdPs_Change_SdBusSpeed(ptr noundef %25)
  store i32 %26, ptr %4, align 4, !tbaa !9
  %27 = load i32, ptr %4, align 4, !tbaa !9
  %28 = sext i32 %27 to i64
  %29 = icmp ne i64 %28, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %24
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %88

31:                                               ; preds = %24
  br label %40

32:                                               ; preds = %18
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = call i32 @XSdPs_Change_MmcBusSpeed(ptr noundef %33)
  store i32 %34, ptr %4, align 4, !tbaa !9
  %35 = load i32, ptr %4, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  %37 = icmp ne i64 %36, 0
  br i1 %37, label %38, label %39

38:                                               ; preds = %32
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %88

39:                                               ; preds = %32
  br label %40

40:                                               ; preds = %39, %31
  %41 = load ptr, ptr %3, align 8, !tbaa !5
  %42 = load ptr, ptr %3, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.XSdPs, ptr %42, i32 0, i32 9
  %44 = load i32, ptr %43, align 8, !tbaa !17
  %45 = call i32 @XSdPs_Change_ClkFreq(ptr noundef %41, i32 noundef %44)
  store i32 %45, ptr %4, align 4, !tbaa !9
  %46 = load i32, ptr %4, align 4, !tbaa !9
  %47 = sext i32 %46 to i64
  %48 = icmp ne i64 %47, 0
  br i1 %48, label %49, label %50

49:                                               ; preds = %40
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %88

50:                                               ; preds = %40
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.XSdPs, ptr %51, i32 0, i32 16
  %53 = load i32, ptr %52, align 4, !tbaa !18
  %54 = icmp eq i32 %53, 7
  br i1 %54, label %65, label %55

55:                                               ; preds = %50
  %56 = load ptr, ptr %3, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.XSdPs, ptr %56, i32 0, i32 16
  %58 = load i32, ptr %57, align 4, !tbaa !18
  %59 = icmp eq i32 %58, 3
  br i1 %59, label %65, label %60

60:                                               ; preds = %55
  %61 = load ptr, ptr %3, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.XSdPs, ptr %61, i32 0, i32 16
  %63 = load i32, ptr %62, align 4, !tbaa !18
  %64 = icmp eq i32 %63, 2
  br i1 %64, label %65, label %73

65:                                               ; preds = %60, %55, %50
  %66 = load ptr, ptr %3, align 8, !tbaa !5
  %67 = call i32 @XSdPs_Execute_Tuning(ptr noundef %66)
  store i32 %67, ptr %4, align 4, !tbaa !9
  %68 = load i32, ptr %4, align 4, !tbaa !9
  %69 = sext i32 %68 to i64
  %70 = icmp ne i64 %69, 0
  br i1 %70, label %71, label %72

71:                                               ; preds = %65
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %88

72:                                               ; preds = %65
  br label %73

73:                                               ; preds = %72, %60
  call void @usleep(i64 noundef 1000)
  %74 = load ptr, ptr %3, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.XSdPs, ptr %74, i32 0, i32 0
  %76 = getelementptr inbounds %struct.XSdPs_Config, ptr %75, i32 0, i32 1
  %77 = load i32, ptr %76, align 4, !tbaa !19
  %78 = call zeroext i8 @XSdPs_ReadReg8(i32 noundef %77, i8 noundef zeroext 40)
  %79 = zext i8 %78 to i32
  store i32 %79, ptr %5, align 4, !tbaa !9
  %80 = load i32, ptr %5, align 4, !tbaa !9
  %81 = or i32 %80, 4
  store i32 %81, ptr %5, align 4, !tbaa !9
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.XSdPs, ptr %82, i32 0, i32 0
  %84 = getelementptr inbounds %struct.XSdPs_Config, ptr %83, i32 0, i32 1
  %85 = load i32, ptr %84, align 4, !tbaa !19
  %86 = load i32, ptr %5, align 4, !tbaa !9
  %87 = trunc i32 %86 to i8
  call void @XSdPs_WriteReg8(i32 noundef %85, i8 noundef zeroext 40, i8 noundef zeroext %87)
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %88

88:                                               ; preds = %73, %71, %49, %38, %30
  %89 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %89, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %90

90:                                               ; preds = %88, %17, %10
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %91 = load i32, ptr %2, align 4
  ret i32 %91
}

declare i32 @XSdPs_Change_SdBusSpeed(ptr noundef) #2

declare i32 @XSdPs_Change_MmcBusSpeed(ptr noundef) #2

declare i32 @XSdPs_Execute_Tuning(ptr noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 36}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !15, i64 120, !14, i64 128, !10, i64 132, !7, i64 136, !10, i64 140}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !7, i64 52}
!17 = !{!12, !10, i64 56}
!18 = !{!12, !10, i64 108}
!19 = !{!12, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [169 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local i32 @XSdPs_Change_ClkFreq(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

declare void @usleep(i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i8 @XSdPs_ReadReg8(i32 noundef, i8 noundef zeroext) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg8(i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_Change_BusSpeed(ptr noundef %0) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %2

2:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 36
  %4 = load i32, ptr %3, align 4, !tbaa !9
  %5 = icmp eq i32 %4, 286331153
  br i1 %5, label %7, label %11

6:                                                ; preds = %1
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 475) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %31

7:                                                ; preds = %2
  %8 = getelementptr inbounds i8, ptr %0, i64 52
  %9 = load i8, ptr %8, align 4, !tbaa !14
  %10 = icmp eq i8 %9, 1
  br i1 %10, label %12, label %14

11:                                               ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 476) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %31

12:                                               ; preds = %7
  %13 = tail call i32 @XSdPs_Change_SdBusSpeed(ptr noundef nonnull %0) #3
  %.not24 = icmp eq i32 %13, 0
  br i1 %.not24, label %16, label %31

14:                                               ; preds = %7
  %15 = tail call i32 @XSdPs_Change_MmcBusSpeed(ptr noundef nonnull %0) #3
  %.not23 = icmp eq i32 %15, 0
  br i1 %.not23, label %16, label %31

16:                                               ; preds = %14, %12
  %17 = getelementptr inbounds i8, ptr %0, i64 56
  %18 = load i32, ptr %17, align 8, !tbaa !15
  %19 = tail call i32 @XSdPs_Change_ClkFreq(ptr noundef nonnull %0, i32 noundef %18)
  %.not25 = icmp eq i32 %19, 0
  br i1 %.not25, label %20, label %31

20:                                               ; preds = %16
  %21 = getelementptr inbounds i8, ptr %0, i64 108
  %22 = load i32, ptr %21, align 4, !tbaa !16
  switch i32 %22, label %25 [
    i32 7, label %23
    i32 3, label %23
    i32 2, label %23
  ]

23:                                               ; preds = %20, %20, %20
  %24 = tail call i32 @XSdPs_Execute_Tuning(ptr noundef nonnull %0) #3
  %.not26 = icmp eq i32 %24, 0
  br i1 %.not26, label %25, label %31

25:                                               ; preds = %20, %23
  tail call void @usleep(i64 noundef 1000) #3
  %26 = getelementptr inbounds i8, ptr %0, i64 4
  %27 = load i32, ptr %26, align 4, !tbaa !17
  %28 = tail call zeroext i8 @XSdPs_ReadReg8(i32 noundef %27, i8 noundef zeroext 40)
  %29 = or i8 %28, 4
  %30 = load i32, ptr %26, align 4, !tbaa !17
  tail call void @XSdPs_WriteReg8(i32 noundef %30, i8 noundef zeroext 40, i8 noundef zeroext %29)
  br label %31

31:                                               ; preds = %25, %12, %14, %16, %23, %11, %6
  %.0 = phi i32 [ 0, %11 ], [ 0, %6 ], [ 0, %25 ], [ 1, %12 ], [ 1, %14 ], [ 1, %16 ], [ 1, %23 ]
  ret i32 %.0
}

declare i32 @XSdPs_Change_SdBusSpeed(ptr noundef) local_unnamed_addr #1

declare i32 @XSdPs_Change_MmcBusSpeed(ptr noundef) local_unnamed_addr #1

declare i32 @XSdPs_Execute_Tuning(ptr noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 36}
!10 = !{!"", !11, i64 0, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !6, i64 56, !7, i64 60, !7, i64 64, !6, i64 80, !7, i64 84, !6, i64 100, !6, i64 104, !6, i64 108, !6, i64 112, !6, i64 116, !13, i64 120, !12, i64 128, !6, i64 132, !7, i64 136, !6, i64 140}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"long", !7, i64 0}
!14 = !{!10, !7, i64 52}
!15 = !{!10, !6, i64 56}
!16 = !{!10, !6, i64 108}
!17 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass