; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (Disable)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1
@CpuId = external hidden global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_Disable(ptr noundef %0, i32 noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #4
  %8 = load i32, ptr @CpuId, align 4, !tbaa !9
  %9 = trunc i32 %8 to i8
  store i8 %9, ptr %6, align 1, !tbaa !11
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %14

13:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 652)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %7, align 4
  br label %45

14:                                               ; preds = %12
  %15 = load i32, ptr %4, align 4, !tbaa !9
  %16 = icmp ult i32 %15, 95
  br i1 %16, label %17, label %18

17:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 653)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %7, align 4
  br label %45

19:                                               ; preds = %17
  %20 = load ptr, ptr %3, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.XScuGic, ptr %20, i32 0, i32 1
  %22 = load i32, ptr %21, align 8, !tbaa !12
  %23 = icmp eq i32 %22, 286331153
  br i1 %23, label %24, label %25

24:                                               ; preds = %19
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %26

25:                                               ; preds = %19
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 654)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %7, align 4
  br label %45

26:                                               ; preds = %24
  %27 = load ptr, ptr %3, align 8, !tbaa !5
  %28 = load i8, ptr %6, align 1, !tbaa !11
  %29 = load i32, ptr %4, align 4, !tbaa !9
  call void @XScuGic_InterruptUnmapFromCpu(ptr noundef %27, i8 noundef zeroext %28, i32 noundef %29)
  %30 = load i32, ptr %4, align 4, !tbaa !9
  %31 = urem i32 %30, 32
  %32 = shl i32 1, %31
  store i32 %32, ptr %5, align 4, !tbaa !9
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.XScuGic, ptr %33, i32 0, i32 0
  %35 = load ptr, ptr %34, align 8, !tbaa !14
  %36 = getelementptr inbounds %struct.XScuGic_Config, ptr %35, i32 0, i32 2
  %37 = load i32, ptr %36, align 8, !tbaa !15
  %38 = load i32, ptr %4, align 4, !tbaa !9
  %39 = udiv i32 %38, 32
  %40 = mul i32 %39, 4
  %41 = add i32 384, %40
  %42 = add i32 %37, %41
  %43 = zext i32 %42 to i64
  %44 = load i32, ptr %5, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %43, i32 noundef %44)
  store i32 0, ptr %7, align 4
  br label %45

45:                                               ; preds = %26, %25, %18, %13
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  %46 = load i32, ptr %7, align 4
  switch i32 %46, label %48 [
    i32 0, label %47
    i32 1, label %47
  ]

47:                                               ; preds = %45, %45
  ret void

48:                                               ; preds = %45
  unreachable
}

; Function Attrs: nounwind uwtable
declare dso_local void @XScuGic_InterruptUnmapFromCpu(ptr noundef, i8 noundef zeroext, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 8}
!13 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!14 = !{!13, !6, i64 0}
!15 = !{!16, !10, i64 8}
!16 = !{!"", !17, i64 0, !10, i64 4, !10, i64 8, !7, i64 16}
!17 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1
@CpuId = external hidden local_unnamed_addr global i32, align 4

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_Disable(ptr noundef %0, i32 noundef %1) local_unnamed_addr #2 {
  %3 = load i32, ptr @CpuId, align 4, !tbaa !5
  %4 = trunc i32 %3 to i8
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %5

5:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = icmp ult i32 %1, 95
  br i1 %6, label %8, label %12

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 652) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %25

8:                                                ; preds = %5
  %9 = getelementptr inbounds i8, ptr %0, i64 8
  %10 = load i32, ptr %9, align 8, !tbaa !9
  %11 = icmp eq i32 %10, 286331153
  br i1 %11, label %13, label %24

12:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 653) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %25

13:                                               ; preds = %8
  tail call void @XScuGic_InterruptUnmapFromCpu(ptr noundef nonnull %0, i8 noundef zeroext %4, i32 noundef %1)
  %14 = and i32 %1, 31
  %15 = shl nuw i32 1, %14
  %16 = load ptr, ptr %0, align 8, !tbaa !12
  %17 = getelementptr inbounds i8, ptr %16, i64 8
  %18 = load i32, ptr %17, align 8, !tbaa !13
  %19 = lshr i32 %1, 3
  %20 = and i32 %19, 12
  %21 = or disjoint i32 %20, 384
  %22 = add i32 %21, %18
  %23 = zext i32 %22 to i64
  tail call void @Xil_Out32(i64 noundef %23, i32 noundef %15)
  br label %25

24:                                               ; preds = %8
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 654) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %25

25:                                               ; preds = %13, %24, %12, %7
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @XScuGic_InterruptUnmapFromCpu(ptr noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{!14, !6, i64 8}
!14 = !{!"", !15, i64 0, !6, i64 4, !6, i64 8, !7, i64 16}
!15 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass