; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc (status)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

@Stat = external hidden global [2 x i8], align 1
@SdInstance = external hidden global [2 x %struct.XSdPs], align 16
@BaseAddress = external hidden global [2 x i32], align 4
@CardDetect = external hidden global [2 x i32], align 4
@WriteProtect = external hidden global [2 x i32], align 4
@HostCntrlrVer = external hidden global [2 x i8], align 1
@SlotType = external hidden global [2 x i32], align 4

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @disk_status(i8 noundef zeroext %0) #0 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  store i8 %0, ptr %3, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #4
  %9 = load i8, ptr %3, align 1, !tbaa !5
  %10 = zext i8 %9 to i64
  %11 = getelementptr inbounds [2 x i8], ptr @Stat, i64 0, i64 %10
  %12 = load i8, ptr %11, align 1, !tbaa !5
  store i8 %12, ptr %4, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  store i32 0, ptr %6, align 4, !tbaa !8
  %13 = load i8, ptr %3, align 1, !tbaa !5
  %14 = zext i8 %13 to i64
  %15 = getelementptr inbounds [2 x %struct.XSdPs], ptr @SdInstance, i64 0, i64 %14
  %16 = getelementptr inbounds %struct.XSdPs, ptr %15, i32 0, i32 0
  %17 = getelementptr inbounds %struct.XSdPs_Config, ptr %16, i32 0, i32 1
  %18 = load i32, ptr %17, align 4, !tbaa !10
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %20, label %88

20:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %21 = load i8, ptr %3, align 1, !tbaa !5
  %22 = zext i8 %21 to i16
  %23 = call ptr @XSdPs_LookupConfig(i16 noundef zeroext %22)
  store ptr %23, ptr %7, align 8, !tbaa !15
  %24 = load ptr, ptr %7, align 8, !tbaa !15
  %25 = icmp eq ptr null, %24
  br i1 %25, label %26, label %32

26:                                               ; preds = %20
  %27 = load i8, ptr %4, align 1, !tbaa !5
  %28 = zext i8 %27 to i32
  %29 = or i32 %28, 1
  %30 = trunc i32 %29 to i8
  store i8 %30, ptr %4, align 1, !tbaa !5
  %31 = load i8, ptr %4, align 1, !tbaa !5
  store i8 %31, ptr %2, align 1
  store i32 1, ptr %8, align 4
  br label %85

32:                                               ; preds = %20
  %33 = load ptr, ptr %7, align 8, !tbaa !15
  %34 = getelementptr inbounds %struct.XSdPs_Config, ptr %33, i32 0, i32 1
  %35 = load i32, ptr %34, align 4, !tbaa !17
  %36 = load i8, ptr %3, align 1, !tbaa !5
  %37 = zext i8 %36 to i64
  %38 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %37
  store i32 %35, ptr %38, align 4, !tbaa !8
  %39 = load ptr, ptr %7, align 8, !tbaa !15
  %40 = getelementptr inbounds %struct.XSdPs_Config, ptr %39, i32 0, i32 3
  %41 = load i32, ptr %40, align 4, !tbaa !18
  %42 = load i8, ptr %3, align 1, !tbaa !5
  %43 = zext i8 %42 to i64
  %44 = getelementptr inbounds [2 x i32], ptr @CardDetect, i64 0, i64 %43
  store i32 %41, ptr %44, align 4, !tbaa !8
  %45 = load ptr, ptr %7, align 8, !tbaa !15
  %46 = getelementptr inbounds %struct.XSdPs_Config, ptr %45, i32 0, i32 4
  %47 = load i32, ptr %46, align 4, !tbaa !19
  %48 = load i8, ptr %3, align 1, !tbaa !5
  %49 = zext i8 %48 to i64
  %50 = getelementptr inbounds [2 x i32], ptr @WriteProtect, i64 0, i64 %49
  store i32 %47, ptr %50, align 4, !tbaa !8
  %51 = load i8, ptr %3, align 1, !tbaa !5
  %52 = zext i8 %51 to i64
  %53 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %52
  %54 = load i32, ptr %53, align 4, !tbaa !8
  %55 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %54, i8 noundef zeroext -2)
  %56 = zext i16 %55 to i32
  %57 = and i32 %56, 255
  %58 = trunc i32 %57 to i8
  %59 = load i8, ptr %3, align 1, !tbaa !5
  %60 = zext i8 %59 to i64
  %61 = getelementptr inbounds [2 x i8], ptr @HostCntrlrVer, i64 0, i64 %60
  store i8 %58, ptr %61, align 1, !tbaa !5
  %62 = load i8, ptr %3, align 1, !tbaa !5
  %63 = zext i8 %62 to i64
  %64 = getelementptr inbounds [2 x i8], ptr @HostCntrlrVer, i64 0, i64 %63
  %65 = load i8, ptr %64, align 1, !tbaa !5
  %66 = zext i8 %65 to i32
  %67 = icmp eq i32 %66, 2
  br i1 %67, label %68, label %80

68:                                               ; preds = %32
  %69 = load i8, ptr %3, align 1, !tbaa !5
  %70 = zext i8 %69 to i64
  %71 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %70
  %72 = load i32, ptr %71, align 4, !tbaa !8
  %73 = add i32 %72, 64
  %74 = zext i32 %73 to i64
  %75 = call i32 @Xil_In32(i64 noundef %74)
  %76 = and i32 %75, -1073741824
  %77 = load i8, ptr %3, align 1, !tbaa !5
  %78 = zext i8 %77 to i64
  %79 = getelementptr inbounds [2 x i32], ptr @SlotType, i64 0, i64 %78
  store i32 %76, ptr %79, align 4, !tbaa !8
  br label %84

80:                                               ; preds = %32
  %81 = load i8, ptr %3, align 1, !tbaa !5
  %82 = zext i8 %81 to i64
  %83 = getelementptr inbounds [2 x i32], ptr @SlotType, i64 0, i64 %82
  store i32 0, ptr %83, align 4, !tbaa !8
  br label %84

84:                                               ; preds = %80, %68
  store i32 0, ptr %8, align 4
  br label %85

85:                                               ; preds = %84, %26
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  %86 = load i32, ptr %8, align 4
  switch i32 %86, label %179 [
    i32 0, label %87
  ]

87:                                               ; preds = %85
  br label %88

88:                                               ; preds = %87, %1
  %89 = load i8, ptr %3, align 1, !tbaa !5
  %90 = zext i8 %89 to i64
  %91 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %90
  %92 = load i32, ptr %91, align 4, !tbaa !8
  %93 = call zeroext i8 @XSdPs_ReadReg8(i32 noundef %92, i8 noundef zeroext 41)
  %94 = zext i8 %93 to i32
  %95 = and i32 %94, 1
  %96 = icmp eq i32 %95, 0
  br i1 %96, label %97, label %102

97:                                               ; preds = %88
  %98 = load i8, ptr %4, align 1, !tbaa !5
  %99 = zext i8 %98 to i32
  %100 = or i32 %99, 1
  %101 = trunc i32 %100 to i8
  store i8 %101, ptr %4, align 1, !tbaa !5
  br label %102

102:                                              ; preds = %97, %88
  %103 = load i8, ptr %3, align 1, !tbaa !5
  %104 = zext i8 %103 to i64
  %105 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %104
  %106 = load i32, ptr %105, align 4, !tbaa !8
  %107 = add i32 %106, 36
  %108 = zext i32 %107 to i64
  %109 = call i32 @Xil_In32(i64 noundef %108)
  store i32 %109, ptr %5, align 4, !tbaa !8
  %110 = load i8, ptr %3, align 1, !tbaa !5
  %111 = zext i8 %110 to i64
  %112 = getelementptr inbounds [2 x i32], ptr @SlotType, i64 0, i64 %111
  %113 = load i32, ptr %112, align 4, !tbaa !8
  %114 = icmp ne i32 %113, 1073741824
  br i1 %114, label %115, label %167

115:                                              ; preds = %102
  %116 = load i8, ptr %3, align 1, !tbaa !5
  %117 = zext i8 %116 to i64
  %118 = getelementptr inbounds [2 x i32], ptr @CardDetect, i64 0, i64 %117
  %119 = load i32, ptr %118, align 4, !tbaa !8
  %120 = icmp ne i32 %119, 0
  br i1 %120, label %121, label %142

121:                                              ; preds = %115
  br label %122

122:                                              ; preds = %140, %121
  %123 = load i32, ptr %5, align 4, !tbaa !8
  %124 = and i32 %123, 65536
  %125 = icmp eq i32 %124, 0
  br i1 %125, label %126, label %141

126:                                              ; preds = %122
  %127 = load i32, ptr %6, align 4, !tbaa !8
  %128 = icmp eq i32 %127, 500
  br i1 %128, label %129, label %130

129:                                              ; preds = %126
  store i8 3, ptr %4, align 1, !tbaa !5
  br label %173

130:                                              ; preds = %126
  call void @usleep(i64 noundef 10000)
  %131 = load i32, ptr %6, align 4, !tbaa !8
  %132 = add i32 %131, 1
  store i32 %132, ptr %6, align 4, !tbaa !8
  %133 = load i8, ptr %3, align 1, !tbaa !5
  %134 = zext i8 %133 to i64
  %135 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %134
  %136 = load i32, ptr %135, align 4, !tbaa !8
  %137 = add i32 %136, 36
  %138 = zext i32 %137 to i64
  %139 = call i32 @Xil_In32(i64 noundef %138)
  store i32 %139, ptr %5, align 4, !tbaa !8
  br label %140

140:                                              ; preds = %130
  br label %122, !llvm.loop !20

141:                                              ; preds = %122
  br label %142

142:                                              ; preds = %141, %115
  %143 = load i8, ptr %4, align 1, !tbaa !5
  %144 = zext i8 %143 to i32
  %145 = and i32 %144, -3
  %146 = trunc i32 %145 to i8
  store i8 %146, ptr %4, align 1, !tbaa !5
  %147 = load i8, ptr %3, align 1, !tbaa !5
  %148 = zext i8 %147 to i64
  %149 = getelementptr inbounds [2 x i32], ptr @WriteProtect, i64 0, i64 %148
  %150 = load i32, ptr %149, align 4, !tbaa !8
  %151 = icmp ne i32 %150, 0
  br i1 %151, label %152, label %162

152:                                              ; preds = %142
  %153 = load i32, ptr %5, align 4, !tbaa !8
  %154 = and i32 %153, 524288
  %155 = icmp eq i32 %154, 0
  br i1 %155, label %156, label %161

156:                                              ; preds = %152
  %157 = load i8, ptr %4, align 1, !tbaa !5
  %158 = zext i8 %157 to i32
  %159 = or i32 %158, 4
  %160 = trunc i32 %159 to i8
  store i8 %160, ptr %4, align 1, !tbaa !5
  br label %173

161:                                              ; preds = %152
  br label %162

162:                                              ; preds = %161, %142
  %163 = load i8, ptr %4, align 1, !tbaa !5
  %164 = zext i8 %163 to i32
  %165 = and i32 %164, -5
  %166 = trunc i32 %165 to i8
  store i8 %166, ptr %4, align 1, !tbaa !5
  br label %172

167:                                              ; preds = %102
  %168 = load i8, ptr %4, align 1, !tbaa !5
  %169 = zext i8 %168 to i32
  %170 = and i32 %169, -7
  %171 = trunc i32 %170 to i8
  store i8 %171, ptr %4, align 1, !tbaa !5
  br label %172

172:                                              ; preds = %167, %162
  br label %173

173:                                              ; preds = %172, %156, %129
  %174 = load i8, ptr %4, align 1, !tbaa !5
  %175 = load i8, ptr %3, align 1, !tbaa !5
  %176 = zext i8 %175 to i64
  %177 = getelementptr inbounds [2 x i8], ptr @Stat, i64 0, i64 %176
  store i8 %174, ptr %177, align 1, !tbaa !5
  %178 = load i8, ptr %4, align 1, !tbaa !5
  store i8 %178, ptr %2, align 1
  store i32 1, ptr %8, align 4
  br label %179

179:                                              ; preds = %173, %85
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #4
  %180 = load i8, ptr %2, align 1
  ret i8 %180
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare ptr @XSdPs_LookupConfig(i16 noundef zeroext) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i8 @XSdPs_ReadReg8(i32 noundef, i8 noundef zeroext) #3

declare void @usleep(i64 noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = !{!11, !9, i64 4}
!11 = !{!"", !12, i64 0, !9, i64 36, !9, i64 40, !9, i64 44, !9, i64 48, !6, i64 52, !6, i64 53, !6, i64 54, !6, i64 55, !9, i64 56, !6, i64 60, !6, i64 64, !9, i64 80, !6, i64 84, !9, i64 100, !9, i64 104, !9, i64 108, !9, i64 112, !9, i64 116, !14, i64 120, !13, i64 128, !9, i64 132, !6, i64 136, !9, i64 140}
!12 = !{!"", !13, i64 0, !9, i64 4, !9, i64 8, !9, i64 12, !9, i64 16, !9, i64 20, !9, i64 24, !9, i64 28, !6, i64 32}
!13 = !{!"short", !6, i64 0}
!14 = !{!"long", !6, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"any pointer", !6, i64 0}
!17 = !{!12, !9, i64 4}
!18 = !{!12, !9, i64 12}
!19 = !{!12, !9, i64 16}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

@Stat = external hidden local_unnamed_addr global [2 x i8], align 1
@SdInstance = external hidden local_unnamed_addr global [2 x %struct.XSdPs], align 16
@BaseAddress = external hidden local_unnamed_addr global [2 x i32], align 4
@CardDetect = external hidden local_unnamed_addr global [2 x i32], align 4
@WriteProtect = external hidden local_unnamed_addr global [2 x i32], align 4
@HostCntrlrVer = external hidden local_unnamed_addr global [2 x i8], align 1
@SlotType = external hidden local_unnamed_addr global [2 x i32], align 4

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @disk_status(i8 noundef zeroext %0) local_unnamed_addr #0 {
  %2 = zext i8 %0 to i64
  %3 = getelementptr inbounds [2 x i8], ptr @Stat, i64 0, i64 %2
  %4 = load i8, ptr %3, align 1, !tbaa !5
  %5 = getelementptr inbounds [2 x %struct.XSdPs], ptr @SdInstance, i64 0, i64 %2, i32 0, i32 1
  %6 = load i32, ptr %5, align 4, !tbaa !8
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %8, label %.thread

8:                                                ; preds = %1
  %9 = zext i8 %0 to i16
  %10 = tail call ptr @XSdPs_LookupConfig(i16 noundef zeroext %9) #3
  %.not = icmp eq ptr %10, null
  br i1 %.not, label %31, label %11

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %10, i64 4
  %13 = load i32, ptr %12, align 4, !tbaa !14
  %14 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %2
  store i32 %13, ptr %14, align 4, !tbaa !15
  %15 = getelementptr inbounds i8, ptr %10, i64 12
  %16 = load i32, ptr %15, align 4, !tbaa !16
  %17 = getelementptr inbounds [2 x i32], ptr @CardDetect, i64 0, i64 %2
  store i32 %16, ptr %17, align 4, !tbaa !15
  %18 = getelementptr inbounds i8, ptr %10, i64 16
  %19 = load i32, ptr %18, align 4, !tbaa !17
  %20 = getelementptr inbounds [2 x i32], ptr @WriteProtect, i64 0, i64 %2
  store i32 %19, ptr %20, align 4, !tbaa !15
  %21 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %13, i8 noundef zeroext -2)
  %22 = trunc i16 %21 to i8
  %23 = getelementptr inbounds [2 x i8], ptr @HostCntrlrVer, i64 0, i64 %2
  store i8 %22, ptr %23, align 1, !tbaa !5
  %.mask = and i16 %21, 255
  %24 = icmp eq i16 %.mask, 2
  br i1 %24, label %25, label %.thread.sink.split

25:                                               ; preds = %11
  %26 = load i32, ptr %14, align 4, !tbaa !15
  %27 = add i32 %26, 64
  %28 = zext i32 %27 to i64
  %29 = tail call i32 @Xil_In32(i64 noundef %28)
  %30 = and i32 %29, -1073741824
  br label %.thread.sink.split

31:                                               ; preds = %8
  %32 = or i8 %4, 1
  br label %67

.thread.sink.split:                               ; preds = %11, %25
  %.sink = phi i32 [ %30, %25 ], [ 0, %11 ]
  %33 = getelementptr inbounds [2 x i32], ptr @SlotType, i64 0, i64 %2
  store i32 %.sink, ptr %33, align 4, !tbaa !15
  br label %.thread

.thread:                                          ; preds = %.thread.sink.split, %1
  %34 = getelementptr inbounds [2 x i32], ptr @BaseAddress, i64 0, i64 %2
  %35 = load i32, ptr %34, align 4, !tbaa !15
  %36 = tail call zeroext i8 @XSdPs_ReadReg8(i32 noundef %35, i8 noundef zeroext 41)
  %37 = and i8 %36, 1
  %38 = xor i8 %37, 1
  %spec.select = or i8 %38, %4
  %39 = load i32, ptr %34, align 4, !tbaa !15
  %40 = add i32 %39, 36
  %41 = zext i32 %40 to i64
  %42 = tail call i32 @Xil_In32(i64 noundef %41)
  %43 = getelementptr inbounds [2 x i32], ptr @SlotType, i64 0, i64 %2
  %44 = load i32, ptr %43, align 4, !tbaa !15
  %.not44 = icmp eq i32 %44, 1073741824
  br i1 %.not44, label %65, label %45

45:                                               ; preds = %.thread
  %46 = getelementptr inbounds [2 x i32], ptr @CardDetect, i64 0, i64 %2
  %47 = load i32, ptr %46, align 4, !tbaa !15
  %.not45 = icmp ne i32 %47, 0
  %48 = and i32 %42, 65536
  %49 = icmp eq i32 %48, 0
  %or.cond55 = select i1 %.not45, i1 %49, i1 false
  br i1 %or.cond55, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %45, %51
  %.03853 = phi i32 [ %52, %51 ], [ 0, %45 ]
  %50 = icmp eq i32 %.03853, 500
  br i1 %50, label %.loopexit51, label %51

51:                                               ; preds = %.lr.ph
  tail call void @usleep(i64 noundef 10000) #3
  %52 = add nuw nsw i32 %.03853, 1
  %53 = load i32, ptr %34, align 4, !tbaa !15
  %54 = add i32 %53, 36
  %55 = zext i32 %54 to i64
  %56 = tail call i32 @Xil_In32(i64 noundef %55)
  %57 = and i32 %56, 65536
  %58 = icmp eq i32 %57, 0
  br i1 %58, label %.lr.ph, label %.loopexit, !llvm.loop !18

.loopexit:                                        ; preds = %51, %45
  %.140 = phi i32 [ %42, %45 ], [ %56, %51 ]
  %59 = and i8 %spec.select, -7
  %60 = getelementptr inbounds [2 x i32], ptr @WriteProtect, i64 0, i64 %2
  %61 = load i32, ptr %60, align 4, !tbaa !15
  %.not46 = icmp ne i32 %61, 0
  %62 = and i32 %.140, 524288
  %63 = icmp eq i32 %62, 0
  %or.cond = select i1 %.not46, i1 %63, i1 false
  %64 = or disjoint i8 %59, 4
  %spec.select50 = select i1 %or.cond, i8 %64, i8 %59
  br label %.loopexit51

65:                                               ; preds = %.thread
  %66 = and i8 %spec.select, -7
  br label %.loopexit51

.loopexit51:                                      ; preds = %.lr.ph, %.loopexit, %65
  %.3 = phi i8 [ %66, %65 ], [ %spec.select50, %.loopexit ], [ 3, %.lr.ph ]
  store i8 %.3, ptr %3, align 1, !tbaa !5
  br label %67

67:                                               ; preds = %31, %.loopexit51
  %.1 = phi i8 [ %.3, %.loopexit51 ], [ %32, %31 ]
  ret i8 %.1
}

declare ptr @XSdPs_LookupConfig(i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i8 @XSdPs_ReadReg8(i32 noundef, i8 noundef zeroext) local_unnamed_addr #2

declare void @usleep(i64 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !12, i64 4}
!9 = !{!"", !10, i64 0, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !6, i64 52, !6, i64 53, !6, i64 54, !6, i64 55, !12, i64 56, !6, i64 60, !6, i64 64, !12, i64 80, !6, i64 84, !12, i64 100, !12, i64 104, !12, i64 108, !12, i64 112, !12, i64 116, !13, i64 120, !11, i64 128, !12, i64 132, !6, i64 136, !12, i64 140}
!10 = !{!"", !11, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !6, i64 32}
!11 = !{!"short", !6, i64 0}
!12 = !{!"int", !6, i64 0}
!13 = !{!"long", !6, i64 0}
!14 = !{!10, !12, i64 4}
!15 = !{!12, !12, i64 0}
!16 = !{!10, !12, i64 12}
!17 = !{!10, !12, i64 16}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass