; LLVM IR from FrancesoM/Bisc8FX :: ip_repo/rtl_ip/PWM_generator_1.0/drivers/PWM_generator_v1_0/src (SelfTest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [33 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [30 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [34 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [34 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [44 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [41 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @PWM_GENERATOR_Reg_SelfTest(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = ptrtoint ptr %9 to i32
  store i32 %10, ptr %4, align 4, !tbaa !9
  call void (ptr, ...) @xil_printf(ptr noundef @.str)
  call void (ptr, ...) @xil_printf(ptr noundef @.str.1)
  call void (ptr, ...) @xil_printf(ptr noundef @.str.2)
  call void (ptr, ...) @xil_printf(ptr noundef @.str.3)
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %11

11:                                               ; preds = %23, %1
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = icmp slt i32 %12, 4
  br i1 %13, label %14, label %26

14:                                               ; preds = %11
  %15 = load i32, ptr %4, align 4, !tbaa !9
  %16 = load i32, ptr %5, align 4, !tbaa !9
  %17 = mul nsw i32 %16, 4
  %18 = add i32 %15, %17
  %19 = zext i32 %18 to i64
  %20 = load i32, ptr %5, align 4, !tbaa !9
  %21 = add nsw i32 %20, 1
  %22 = mul nsw i32 %21, 16
  call void @Xil_Out32(i64 noundef %19, i32 noundef %22)
  br label %23

23:                                               ; preds = %14
  %24 = load i32, ptr %5, align 4, !tbaa !9
  %25 = add nsw i32 %24, 1
  store i32 %25, ptr %5, align 4, !tbaa !9
  br label %11, !llvm.loop !11

26:                                               ; preds = %11
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %27

27:                                               ; preds = %47, %26
  %28 = load i32, ptr %6, align 4, !tbaa !9
  %29 = icmp slt i32 %28, 4
  br i1 %29, label %30, label %50

30:                                               ; preds = %27
  %31 = load i32, ptr %4, align 4, !tbaa !9
  %32 = load i32, ptr %6, align 4, !tbaa !9
  %33 = mul nsw i32 %32, 4
  %34 = add i32 %31, %33
  %35 = zext i32 %34 to i64
  %36 = call i32 @Xil_In32(i64 noundef %35)
  %37 = load i32, ptr %6, align 4, !tbaa !9
  %38 = add nsw i32 %37, 1
  %39 = mul nsw i32 %38, 16
  %40 = icmp ne i32 %36, %39
  br i1 %40, label %41, label %46

41:                                               ; preds = %30
  %42 = load i32, ptr %4, align 4, !tbaa !9
  %43 = load i32, ptr %6, align 4, !tbaa !9
  %44 = mul nsw i32 %43, 4
  %45 = add nsw i32 %42, %44
  call void (ptr, ...) @xil_printf(ptr noundef @.str.4, i32 noundef %45)
  store i32 1, ptr %2, align 4
  store i32 1, ptr %8, align 4
  br label %51

46:                                               ; preds = %30
  br label %47

47:                                               ; preds = %46
  %48 = load i32, ptr %6, align 4, !tbaa !9
  %49 = add nsw i32 %48, 1
  store i32 %49, ptr %6, align 4, !tbaa !9
  br label %27, !llvm.loop !13

50:                                               ; preds = %27
  call void (ptr, ...) @xil_printf(ptr noundef @.str.5)
  store i32 0, ptr %2, align 4
  store i32 1, ptr %8, align 4
  br label %51

51:                                               ; preds = %50, %41
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %52 = load i32, ptr %2, align 4
  ret i32 %52
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @xil_printf(ptr noundef, ...) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [33 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [30 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [34 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [34 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [44 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [41 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @PWM_GENERATOR_Reg_SelfTest(ptr noundef %0) local_unnamed_addr #0 {
.preheader.preheader:
  %1 = ptrtoint ptr %0 to i64
  %2 = trunc i64 %1 to i32
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str) #3
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str.1) #3
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str.2) #3
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str.3) #3
  %3 = and i64 %1, 4294967295
  tail call void @Xil_Out32(i64 noundef %3, i32 noundef 16)
  %4 = add i32 %2, 4
  %5 = zext i32 %4 to i64
  tail call void @Xil_Out32(i64 noundef %5, i32 noundef 32)
  %6 = add i32 %2, 8
  %7 = zext i32 %6 to i64
  tail call void @Xil_Out32(i64 noundef %7, i32 noundef 48)
  %8 = add i32 %2, 12
  %9 = zext i32 %8 to i64
  tail call void @Xil_Out32(i64 noundef %9, i32 noundef 64)
  %10 = tail call i32 @Xil_In32(i64 noundef %3)
  %.not = icmp eq i32 %10, 16
  br i1 %.not, label %.preheader.1, label %14, !llvm.loop !5

.preheader.1:                                     ; preds = %.preheader.preheader
  %11 = tail call i32 @Xil_In32(i64 noundef %5)
  %.not.1 = icmp eq i32 %11, 32
  br i1 %.not.1, label %.preheader.2, label %14, !llvm.loop !5

.preheader.2:                                     ; preds = %.preheader.1
  %12 = tail call i32 @Xil_In32(i64 noundef %7)
  %.not.2 = icmp eq i32 %12, 48
  br i1 %.not.2, label %.preheader.3, label %14, !llvm.loop !5

.preheader.3:                                     ; preds = %.preheader.2
  %13 = tail call i32 @Xil_In32(i64 noundef %9)
  %.not.3 = icmp eq i32 %13, 64
  br i1 %.not.3, label %.preheader.4, label %14, !llvm.loop !5

14:                                               ; preds = %.preheader.3, %.preheader.2, %.preheader.1, %.preheader.preheader
  %.lcssa = phi i32 [ %2, %.preheader.preheader ], [ %4, %.preheader.1 ], [ %6, %.preheader.2 ], [ %8, %.preheader.3 ]
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str.4, i32 noundef %.lcssa) #3
  br label %15

.preheader.4:                                     ; preds = %.preheader.3
  tail call void (ptr, ...) @xil_printf(ptr noundef nonnull @.str.5) #3
  br label %15

15:                                               ; preds = %.preheader.4, %14
  %.0 = phi i32 [ 1, %14 ], [ 0, %.preheader.4 ]
  ret i32 %.0
}

declare void @xil_printf(ptr noundef, ...) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass