; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (AutoTuning)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

declare void @usleep(i64 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_AutoTuning(ptr noundef %0) #3 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i16, align 2
  %5 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  store i16 64, ptr %4, align 2, !tbaa !9
  %6 = load ptr, ptr %2, align 8, !tbaa !5
  %7 = getelementptr inbounds %struct.XSdPs, ptr %6, i32 0, i32 8
  %8 = load i8, ptr %7, align 1, !tbaa !11
  %9 = zext i8 %8 to i32
  %10 = icmp eq i32 %9, 3
  br i1 %10, label %11, label %16

11:                                               ; preds = %1
  %12 = load i16, ptr %4, align 2, !tbaa !9
  %13 = zext i16 %12 to i32
  %14 = mul i32 %13, 2
  %15 = trunc i32 %14 to i16
  store i16 %15, ptr %4, align 2, !tbaa !9
  br label %16

16:                                               ; preds = %11, %1
  %17 = load i16, ptr %4, align 2, !tbaa !9
  %18 = zext i16 %17 to i32
  %19 = and i32 %18, 4095
  %20 = trunc i32 %19 to i16
  store i16 %20, ptr %4, align 2, !tbaa !9
  %21 = load ptr, ptr %2, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.XSdPs, ptr %21, i32 0, i32 0
  %23 = getelementptr inbounds %struct.XSdPs_Config, ptr %22, i32 0, i32 1
  %24 = load i32, ptr %23, align 4, !tbaa !16
  %25 = load i16, ptr %4, align 2, !tbaa !9
  call void @XSdPs_WriteReg16(i32 noundef %24, i8 noundef zeroext 4, i16 noundef zeroext %25)
  %26 = load ptr, ptr %2, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.XSdPs, ptr %26, i32 0, i32 20
  store i16 16, ptr %27, align 8, !tbaa !17
  %28 = load ptr, ptr %2, align 8, !tbaa !5
  call void @XSdPs_SetExecTuning(ptr noundef %28)
  call void @usleep(i64 noundef 1)
  store i8 0, ptr %5, align 1, !tbaa !18
  br label %29

29:                                               ; preds = %61, %16
  %30 = load i8, ptr %5, align 1, !tbaa !18
  %31 = zext i8 %30 to i32
  %32 = icmp ult i32 %31, 40
  br i1 %32, label %33, label %64

33:                                               ; preds = %29
  %34 = load ptr, ptr %2, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.XSdPs, ptr %34, i32 0, i32 5
  %36 = load i8, ptr %35, align 4, !tbaa !19
  %37 = zext i8 %36 to i32
  %38 = icmp eq i32 %37, 1
  br i1 %38, label %39, label %42

39:                                               ; preds = %33
  %40 = load ptr, ptr %2, align 8, !tbaa !5
  %41 = call i32 @XSdPs_CmdTransfer(ptr noundef %40, i32 noundef 4864, i32 noundef 0, i32 noundef 1)
  store i32 %41, ptr %3, align 4, !tbaa !20
  br label %45

42:                                               ; preds = %33
  %43 = load ptr, ptr %2, align 8, !tbaa !5
  %44 = call i32 @XSdPs_CmdTransfer(ptr noundef %43, i32 noundef 5376, i32 noundef 0, i32 noundef 1)
  store i32 %44, ptr %3, align 4, !tbaa !20
  br label %45

45:                                               ; preds = %42, %39
  %46 = load i32, ptr %3, align 4, !tbaa !20
  %47 = sext i32 %46 to i64
  %48 = icmp ne i64 %47, 0
  br i1 %48, label %49, label %50

49:                                               ; preds = %45
  store i32 1, ptr %3, align 4, !tbaa !20
  br label %75

50:                                               ; preds = %45
  %51 = load ptr, ptr %2, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.XSdPs, ptr %51, i32 0, i32 0
  %53 = getelementptr inbounds %struct.XSdPs_Config, ptr %52, i32 0, i32 1
  %54 = load i32, ptr %53, align 4, !tbaa !16
  %55 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %54, i8 noundef zeroext 62)
  %56 = zext i16 %55 to i32
  %57 = and i32 %56, 64
  %58 = icmp eq i32 %57, 0
  br i1 %58, label %59, label %60

59:                                               ; preds = %50
  br label %64

60:                                               ; preds = %50
  br label %61

61:                                               ; preds = %60
  %62 = load i8, ptr %5, align 1, !tbaa !18
  %63 = add i8 %62, 1
  store i8 %63, ptr %5, align 1, !tbaa !18
  br label %29, !llvm.loop !21

64:                                               ; preds = %59, %29
  %65 = load ptr, ptr %2, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.XSdPs, ptr %65, i32 0, i32 0
  %67 = getelementptr inbounds %struct.XSdPs_Config, ptr %66, i32 0, i32 1
  %68 = load i32, ptr %67, align 4, !tbaa !16
  %69 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %68, i8 noundef zeroext 62)
  %70 = zext i16 %69 to i32
  %71 = and i32 %70, 128
  %72 = icmp eq i32 %71, 0
  br i1 %72, label %73, label %74

73:                                               ; preds = %64
  store i32 1, ptr %3, align 4, !tbaa !20
  br label %75

74:                                               ; preds = %64
  call void @usleep(i64 noundef 1)
  store i32 0, ptr %3, align 4, !tbaa !20
  br label %75

75:                                               ; preds = %74, %73, %49
  %76 = load i32, ptr %3, align 4, !tbaa !20
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret i32 %76
}

declare void @XSdPs_SetExecTuning(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !7, i64 55}
!12 = !{!"", !13, i64 0, !14, i64 36, !14, i64 40, !14, i64 44, !14, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !14, i64 56, !7, i64 60, !7, i64 64, !14, i64 80, !7, i64 84, !14, i64 100, !14, i64 104, !14, i64 108, !14, i64 112, !14, i64 116, !15, i64 120, !10, i64 128, !14, i64 132, !7, i64 136, !14, i64 140}
!13 = !{!"", !10, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !7, i64 32}
!14 = !{!"int", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !14, i64 4}
!17 = !{!12, !10, i64 128}
!18 = !{!7, !7, i64 0}
!19 = !{!12, !7, i64 52}
!20 = !{!14, !14, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

declare void @usleep(i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_AutoTuning(ptr noundef %0) local_unnamed_addr #2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 55
  %3 = load i8, ptr %2, align 1, !tbaa !5
  %4 = icmp eq i8 %3, 3
  %spec.select = select i1 %4, i16 128, i16 64
  %5 = getelementptr inbounds i8, ptr %0, i64 4
  %6 = load i32, ptr %5, align 4, !tbaa !13
  tail call void @XSdPs_WriteReg16(i32 noundef %6, i8 noundef zeroext 4, i16 noundef zeroext %spec.select)
  %7 = getelementptr inbounds i8, ptr %0, i64 128
  store i16 16, ptr %7, align 8, !tbaa !14
  tail call void @XSdPs_SetExecTuning(ptr noundef %0) #3
  tail call void @usleep(i64 noundef 1) #3
  %8 = getelementptr inbounds i8, ptr %0, i64 52
  br label %9

9:                                                ; preds = %13, %1
  %.017 = phi i8 [ 0, %1 ], [ %18, %13 ]
  %10 = load i8, ptr %8, align 4, !tbaa !15
  %11 = icmp eq i8 %10, 1
  %. = select i1 %11, i32 4864, i32 5376
  %12 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef %., i32 noundef 0, i32 noundef 1) #3
  %.not = icmp eq i32 %12, 0
  br i1 %.not, label %13, label %.loopexit

13:                                               ; preds = %9
  %14 = load i32, ptr %5, align 4, !tbaa !13
  %15 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %14, i8 noundef zeroext 62)
  %16 = and i16 %15, 64
  %17 = icmp eq i16 %16, 0
  %18 = add nuw nsw i8 %.017, 1
  %exitcond.not = icmp eq i8 %18, 40
  %or.cond = select i1 %17, i1 true, i1 %exitcond.not
  br i1 %or.cond, label %19, label %9, !llvm.loop !16

19:                                               ; preds = %13
  %20 = load i32, ptr %5, align 4, !tbaa !13
  %21 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %20, i8 noundef zeroext 62)
  %22 = and i16 %21, 128
  %23 = icmp eq i16 %22, 0
  br i1 %23, label %.loopexit, label %24

24:                                               ; preds = %19
  tail call void @usleep(i64 noundef 1) #3
  br label %.loopexit

.loopexit:                                        ; preds = %9, %19, %24
  %.1 = phi i32 [ 0, %24 ], [ 1, %19 ], [ 1, %9 ]
  ret i32 %.1
}

declare void @XSdPs_SetExecTuning(ptr noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 55}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = !{!6, !11, i64 4}
!14 = !{!6, !8, i64 128}
!15 = !{!6, !9, i64 52}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass