; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (EnableClock)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #1

declare void @usleep(i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_EnableClock(ptr noundef %0, i16 noundef zeroext %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca i16, align 2
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i16, align 2
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i16 %1, ptr %4, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  store i32 150000, ptr %5, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #4
  %8 = load i16, ptr %4, align 2, !tbaa !9
  %9 = zext i16 %8 to i32
  %10 = or i32 %9, 1
  %11 = trunc i32 %10 to i16
  store i16 %11, ptr %4, align 2, !tbaa !9
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.XSdPs, ptr %12, i32 0, i32 0
  %14 = getelementptr inbounds %struct.XSdPs_Config, ptr %13, i32 0, i32 1
  %15 = load i32, ptr %14, align 4, !tbaa !13
  %16 = load i16, ptr %4, align 2, !tbaa !9
  call void @XSdPs_WriteReg16(i32 noundef %15, i8 noundef zeroext 44, i16 noundef zeroext %16)
  br label %17

17:                                               ; preds = %33, %2
  %18 = load ptr, ptr %3, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XSdPs, ptr %18, i32 0, i32 0
  %20 = getelementptr inbounds %struct.XSdPs_Config, ptr %19, i32 0, i32 1
  %21 = load i32, ptr %20, align 4, !tbaa !13
  %22 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %21, i8 noundef zeroext 44)
  store i16 %22, ptr %7, align 2, !tbaa !9
  %23 = load i32, ptr %5, align 4, !tbaa !11
  %24 = sub i32 %23, 1
  store i32 %24, ptr %5, align 4, !tbaa !11
  call void @usleep(i64 noundef 1)
  br label %25

25:                                               ; preds = %17
  %26 = load i16, ptr %7, align 2, !tbaa !9
  %27 = zext i16 %26 to i32
  %28 = and i32 %27, 2
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %33

30:                                               ; preds = %25
  %31 = load i32, ptr %5, align 4, !tbaa !11
  %32 = icmp ne i32 %31, 0
  br label %33

33:                                               ; preds = %30, %25
  %34 = phi i1 [ false, %25 ], [ %32, %30 ]
  br i1 %34, label %17, label %35, !llvm.loop !17

35:                                               ; preds = %33
  %36 = load i32, ptr %5, align 4, !tbaa !11
  %37 = icmp eq i32 %36, 0
  br i1 %37, label %38, label %39

38:                                               ; preds = %35
  store i32 1, ptr %6, align 4, !tbaa !11
  br label %49

39:                                               ; preds = %35
  %40 = load i16, ptr %4, align 2, !tbaa !9
  %41 = zext i16 %40 to i32
  %42 = or i32 %41, 4
  %43 = trunc i32 %42 to i16
  store i16 %43, ptr %4, align 2, !tbaa !9
  %44 = load ptr, ptr %3, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.XSdPs, ptr %44, i32 0, i32 0
  %46 = getelementptr inbounds %struct.XSdPs_Config, ptr %45, i32 0, i32 1
  %47 = load i32, ptr %46, align 4, !tbaa !13
  %48 = load i16, ptr %4, align 2, !tbaa !9
  call void @XSdPs_WriteReg16(i32 noundef %47, i8 noundef zeroext 44, i16 noundef zeroext %48)
  store i32 0, ptr %6, align 4, !tbaa !11
  br label %49

49:                                               ; preds = %39, %38
  %50 = load i32, ptr %6, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret i32 %50
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 4}
!14 = !{!"", !15, i64 0, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !12, i64 56, !7, i64 60, !7, i64 64, !12, i64 80, !7, i64 84, !12, i64 100, !12, i64 104, !12, i64 108, !12, i64 112, !12, i64 116, !16, i64 120, !10, i64 128, !12, i64 132, !7, i64 136, !12, i64 140}
!15 = !{!"", !10, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !7, i64 32}
!16 = !{!"long", !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

declare void @usleep(i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_EnableClock(ptr nocapture noundef readonly %0, i16 noundef zeroext %1) local_unnamed_addr #2 {
  %3 = or i16 %1, 1
  %4 = getelementptr inbounds i8, ptr %0, i64 4
  %5 = load i32, ptr %4, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %5, i8 noundef zeroext 44, i16 noundef zeroext %3)
  br label %6

6:                                                ; preds = %6, %2
  %.011 = phi i32 [ 150000, %2 ], [ %9, %6 ]
  %7 = load i32, ptr %4, align 4, !tbaa !5
  %8 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %7, i8 noundef zeroext 44)
  %9 = add nsw i32 %.011, -1
  tail call void @usleep(i64 noundef 1) #3
  %10 = and i16 %8, 2
  %11 = icmp eq i16 %10, 0
  %12 = icmp ne i32 %9, 0
  %13 = select i1 %11, i1 %12, i1 false
  br i1 %13, label %6, label %14, !llvm.loop !13

14:                                               ; preds = %6
  %15 = icmp eq i32 %9, 0
  br i1 %15, label %19, label %16

16:                                               ; preds = %14
  %17 = or i16 %1, 5
  %18 = load i32, ptr %4, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %18, i8 noundef zeroext 44, i16 noundef zeroext %17)
  br label %19

19:                                               ; preds = %14, %16
  %.0 = phi i32 [ 0, %16 ], [ 1, %14 ]
  ret i32 %.0
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 4}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass