; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (DeviceReset)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XUsbPs = type { %struct.XUsbPs_SetupData, %struct.XUsbPs_Config, i32, ptr, %struct.XUsbPs_DeviceConfig, ptr, ptr, i32, ptr, i8, ptr }
%struct.XUsbPs_SetupData = type { i8, i8, i16, i16, i16 }
%struct.XUsbPs_Config = type { i16, i32 }
%struct.XUsbPs_DeviceConfig = type { i8, [12 x %struct.XUsbPs_EpConfig], i32, [12 x %struct.XUsbPs_Endpoint], i32 }
%struct.XUsbPs_EpConfig = type { %struct.XUsbPs_EpSetup, %struct.XUsbPs_EpSetup }
%struct.XUsbPs_EpSetup = type { i32, i32, i32, i16 }
%struct.XUsbPs_Endpoint = type { %struct.XUsbPs_EpOut, %struct.XUsbPs_EpIn }
%struct.XUsbPs_EpOut = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i8, i32 }
%struct.XUsbPs_EpIn = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, i32 }

; Function Attrs: nounwind uwtable
define dso_local void @XUsbPs_DeviceReset(ptr noundef %0) #0 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = getelementptr inbounds %struct.XUsbPs, ptr %4, i32 0, i32 1
  %6 = getelementptr inbounds %struct.XUsbPs_Config, ptr %5, i32 0, i32 1
  %7 = load i32, ptr %6, align 4, !tbaa !9
  %8 = add i32 %7, 428
  %9 = zext i32 %8 to i64
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.XUsbPs, ptr %10, i32 0, i32 1
  %12 = getelementptr inbounds %struct.XUsbPs_Config, ptr %11, i32 0, i32 1
  %13 = load i32, ptr %12, align 4, !tbaa !9
  %14 = add i32 %13, 428
  %15 = zext i32 %14 to i64
  %16 = call i32 @Xil_In32(i64 noundef %15)
  call void @Xil_Out32(i64 noundef %9, i32 noundef %16)
  %17 = load ptr, ptr %2, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.XUsbPs, ptr %17, i32 0, i32 1
  %19 = getelementptr inbounds %struct.XUsbPs_Config, ptr %18, i32 0, i32 1
  %20 = load i32, ptr %19, align 4, !tbaa !9
  %21 = add i32 %20, 444
  %22 = zext i32 %21 to i64
  %23 = load ptr, ptr %2, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.XUsbPs, ptr %23, i32 0, i32 1
  %25 = getelementptr inbounds %struct.XUsbPs_Config, ptr %24, i32 0, i32 1
  %26 = load i32, ptr %25, align 4, !tbaa !9
  %27 = add i32 %26, 444
  %28 = zext i32 %27 to i64
  %29 = call i32 @Xil_In32(i64 noundef %28)
  call void @Xil_Out32(i64 noundef %22, i32 noundef %29)
  store i32 1000000, ptr %3, align 4, !tbaa !16
  br label %30

30:                                               ; preds = %46, %1
  %31 = load ptr, ptr %2, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.XUsbPs, ptr %31, i32 0, i32 1
  %33 = getelementptr inbounds %struct.XUsbPs_Config, ptr %32, i32 0, i32 1
  %34 = load i32, ptr %33, align 4, !tbaa !9
  %35 = add i32 %34, 432
  %36 = zext i32 %35 to i64
  %37 = call i32 @Xil_In32(i64 noundef %36)
  %38 = and i32 %37, 268374015
  %39 = icmp ne i32 %38, 0
  br i1 %39, label %40, label %44

40:                                               ; preds = %30
  %41 = load i32, ptr %3, align 4, !tbaa !16
  %42 = add nsw i32 %41, -1
  store i32 %42, ptr %3, align 4, !tbaa !16
  %43 = icmp ne i32 %42, 0
  br label %44

44:                                               ; preds = %40, %30
  %45 = phi i1 [ false, %30 ], [ %43, %40 ]
  br i1 %45, label %46, label %47

46:                                               ; preds = %44
  br label %30, !llvm.loop !17

47:                                               ; preds = %44
  %48 = load ptr, ptr %2, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.XUsbPs, ptr %48, i32 0, i32 1
  %50 = getelementptr inbounds %struct.XUsbPs_Config, ptr %49, i32 0, i32 1
  %51 = load i32, ptr %50, align 4, !tbaa !9
  %52 = add i32 %51, 436
  %53 = zext i32 %52 to i64
  call void @Xil_Out32(i64 noundef %53, i32 noundef -1)
  %54 = load ptr, ptr %2, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.XUsbPs, ptr %54, i32 0, i32 1
  %56 = getelementptr inbounds %struct.XUsbPs_Config, ptr %55, i32 0, i32 1
  %57 = load i32, ptr %56, align 4, !tbaa !9
  %58 = add i32 %57, 320
  %59 = zext i32 %58 to i64
  %60 = load ptr, ptr %2, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.XUsbPs, ptr %60, i32 0, i32 1
  %62 = getelementptr inbounds %struct.XUsbPs_Config, ptr %61, i32 0, i32 1
  %63 = load i32, ptr %62, align 4, !tbaa !9
  %64 = add i32 %63, 320
  %65 = zext i32 %64 to i64
  %66 = call i32 @Xil_In32(i64 noundef %65)
  %67 = and i32 %66, -2
  call void @Xil_Out32(i64 noundef %59, i32 noundef %67)
  %68 = load ptr, ptr %2, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.XUsbPs, ptr %68, i32 0, i32 1
  %70 = getelementptr inbounds %struct.XUsbPs_Config, ptr %69, i32 0, i32 1
  %71 = load i32, ptr %70, align 4, !tbaa !9
  %72 = add i32 %71, 320
  %73 = zext i32 %72 to i64
  %74 = load ptr, ptr %2, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.XUsbPs, ptr %74, i32 0, i32 1
  %76 = getelementptr inbounds %struct.XUsbPs_Config, ptr %75, i32 0, i32 1
  %77 = load i32, ptr %76, align 4, !tbaa !9
  %78 = add i32 %77, 320
  %79 = zext i32 %78 to i64
  %80 = call i32 @Xil_In32(i64 noundef %79)
  %81 = or i32 %80, 2
  call void @Xil_Out32(i64 noundef %73, i32 noundef %81)
  store i32 1000000, ptr %3, align 4, !tbaa !16
  br label %82

82:                                               ; preds = %98, %47
  %83 = load ptr, ptr %2, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.XUsbPs, ptr %83, i32 0, i32 1
  %85 = getelementptr inbounds %struct.XUsbPs_Config, ptr %84, i32 0, i32 1
  %86 = load i32, ptr %85, align 4, !tbaa !9
  %87 = add i32 %86, 320
  %88 = zext i32 %87 to i64
  %89 = call i32 @Xil_In32(i64 noundef %88)
  %90 = and i32 %89, 2
  %91 = icmp ne i32 %90, 0
  br i1 %91, label %92, label %96

92:                                               ; preds = %82
  %93 = load i32, ptr %3, align 4, !tbaa !16
  %94 = add nsw i32 %93, -1
  store i32 %94, ptr %3, align 4, !tbaa !16
  %95 = icmp ne i32 %94, 0
  br label %96

96:                                               ; preds = %92, %82
  %97 = phi i1 [ false, %82 ], [ %95, %92 ]
  br i1 %97, label %98, label %99

98:                                               ; preds = %96
  br label %82, !llvm.loop !19

99:                                               ; preds = %96
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !14, i64 12}
!10 = !{!"", !11, i64 0, !13, i64 8, !14, i64 16, !6, i64 24, !15, i64 32, !6, i64 2352, !6, i64 2360, !14, i64 2368, !6, i64 2376, !7, i64 2384, !6, i64 2392}
!11 = !{!"", !7, i64 0, !7, i64 1, !12, i64 2, !12, i64 4, !12, i64 6}
!12 = !{!"short", !7, i64 0}
!13 = !{!"", !12, i64 0, !14, i64 4}
!14 = !{!"int", !7, i64 0}
!15 = !{!"", !7, i64 0, !7, i64 4, !14, i64 388, !7, i64 392, !14, i64 2312}
!16 = !{!14, !14, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @XUsbPs_DeviceReset(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 12
  %3 = load i32, ptr %2, align 4, !tbaa !5
  %4 = add i32 %3, 428
  %5 = zext i32 %4 to i64
  %6 = tail call i32 @Xil_In32(i64 noundef %5)
  tail call void @Xil_Out32(i64 noundef %5, i32 noundef %6)
  %7 = load i32, ptr %2, align 4, !tbaa !5
  %8 = add i32 %7, 444
  %9 = zext i32 %8 to i64
  %10 = tail call i32 @Xil_In32(i64 noundef %9)
  tail call void @Xil_Out32(i64 noundef %9, i32 noundef %10)
  br label %11

11:                                               ; preds = %11, %1
  %.0 = phi i32 [ 1000000, %1 ], [ %17, %11 ]
  %12 = load i32, ptr %2, align 4, !tbaa !5
  %13 = add i32 %12, 432
  %14 = zext i32 %13 to i64
  %15 = tail call i32 @Xil_In32(i64 noundef %14)
  %16 = and i32 %15, 268374015
  %.not = icmp eq i32 %16, 0
  %17 = add nsw i32 %.0, -1
  %.not16 = icmp eq i32 %17, 0
  %or.cond = select i1 %.not, i1 true, i1 %.not16
  br i1 %or.cond, label %.critedge, label %11, !llvm.loop !15

.critedge:                                        ; preds = %11
  %18 = load i32, ptr %2, align 4, !tbaa !5
  %19 = add i32 %18, 436
  %20 = zext i32 %19 to i64
  tail call void @Xil_Out32(i64 noundef %20, i32 noundef -1)
  %21 = load i32, ptr %2, align 4, !tbaa !5
  %22 = add i32 %21, 320
  %23 = zext i32 %22 to i64
  %24 = tail call i32 @Xil_In32(i64 noundef %23)
  %25 = and i32 %24, -2
  tail call void @Xil_Out32(i64 noundef %23, i32 noundef %25)
  %26 = load i32, ptr %2, align 4, !tbaa !5
  %27 = add i32 %26, 320
  %28 = zext i32 %27 to i64
  %29 = tail call i32 @Xil_In32(i64 noundef %28)
  %30 = or i32 %29, 2
  tail call void @Xil_Out32(i64 noundef %28, i32 noundef %30)
  br label %31

31:                                               ; preds = %31, %.critedge
  %.1 = phi i32 [ 1000000, %.critedge ], [ %37, %31 ]
  %32 = load i32, ptr %2, align 4, !tbaa !5
  %33 = add i32 %32, 320
  %34 = zext i32 %33 to i64
  %35 = tail call i32 @Xil_In32(i64 noundef %34)
  %36 = and i32 %35, 2
  %.not17 = icmp eq i32 %36, 0
  %37 = add nsw i32 %.1, -1
  %.not18 = icmp eq i32 %37, 0
  %or.cond19 = select i1 %.not17, i1 true, i1 %.not18
  br i1 %or.cond19, label %.critedge2, label %31, !llvm.loop !17

.critedge2:                                       ; preds = %31
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 12}
!6 = !{!"", !7, i64 0, !11, i64 8, !12, i64 16, !13, i64 24, !14, i64 32, !13, i64 2352, !13, i64 2360, !12, i64 2368, !13, i64 2376, !8, i64 2384, !13, i64 2392}
!7 = !{!"", !8, i64 0, !8, i64 1, !10, i64 2, !10, i64 4, !10, i64 6}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"short", !8, i64 0}
!11 = !{!"", !10, i64 0, !12, i64 4}
!12 = !{!"int", !8, i64 0}
!13 = !{!"any pointer", !8, i64 0}
!14 = !{!"", !8, i64 0, !8, i64 4, !12, i64 388, !8, i64 392, !12, i64 2312}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass