; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (IdentifyCard)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, i32, i32, i64, i16, i32, i8, i32 }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_IdentifyCard(ptr noundef %0) #3 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = getelementptr inbounds %struct.XSdPs, ptr %4, i32 0, i32 7
  %6 = load i8, ptr %5, align 2, !tbaa !9
  %7 = zext i8 %6 to i32
  %8 = icmp eq i32 %7, 2
  br i1 %8, label %9, label %18

9:                                                ; preds = %1
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.XSdPs, ptr %10, i32 0, i32 2
  %12 = load i32, ptr %11, align 8, !tbaa !15
  %13 = and i32 %12, -1073741824
  %14 = icmp eq i32 %13, 1073741824
  br i1 %14, label %15, label %18

15:                                               ; preds = %9
  %16 = load ptr, ptr %2, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.XSdPs, ptr %16, i32 0, i32 5
  store i8 5, ptr %17, align 4, !tbaa !16
  store i32 0, ptr %3, align 4, !tbaa !17
  br label %53

18:                                               ; preds = %9, %1
  call void @usleep(i64 noundef 10000)
  %19 = load ptr, ptr %2, align 8, !tbaa !5
  %20 = call i32 @XSdPs_CmdTransfer(ptr noundef %19, i32 noundef 0, i32 noundef 0, i32 noundef 0)
  store i32 %20, ptr %3, align 4, !tbaa !17
  %21 = load i32, ptr %3, align 4, !tbaa !17
  %22 = sext i32 %21 to i64
  %23 = icmp ne i64 %22, 0
  br i1 %23, label %24, label %25

24:                                               ; preds = %18
  store i32 1, ptr %3, align 4, !tbaa !17
  br label %53

25:                                               ; preds = %18
  %26 = load ptr, ptr %2, align 8, !tbaa !5
  %27 = call i32 @XSdPs_CmdTransfer(ptr noundef %26, i32 noundef 256, i32 noundef 1090486272, i32 noundef 0)
  store i32 %27, ptr %3, align 4, !tbaa !17
  %28 = load i32, ptr %3, align 4, !tbaa !17
  %29 = sext i32 %28 to i64
  %30 = icmp ne i64 %29, 0
  br i1 %30, label %31, label %34

31:                                               ; preds = %25
  %32 = load ptr, ptr %2, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.XSdPs, ptr %32, i32 0, i32 5
  store i8 1, ptr %33, align 4, !tbaa !16
  br label %37

34:                                               ; preds = %25
  %35 = load ptr, ptr %2, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.XSdPs, ptr %35, i32 0, i32 5
  store i8 2, ptr %36, align 4, !tbaa !16
  br label %37

37:                                               ; preds = %34, %31
  %38 = load ptr, ptr %2, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.XSdPs, ptr %38, i32 0, i32 0
  %40 = getelementptr inbounds %struct.XSdPs_Config, ptr %39, i32 0, i32 1
  %41 = load i32, ptr %40, align 4, !tbaa !18
  call void @XSdPs_WriteReg16(i32 noundef %41, i8 noundef zeroext 48, i16 noundef zeroext -1)
  %42 = load ptr, ptr %2, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.XSdPs, ptr %42, i32 0, i32 0
  %44 = getelementptr inbounds %struct.XSdPs_Config, ptr %43, i32 0, i32 1
  %45 = load i32, ptr %44, align 4, !tbaa !18
  call void @XSdPs_WriteReg16(i32 noundef %45, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  %46 = load ptr, ptr %2, align 8, !tbaa !5
  %47 = call i32 @XSdPs_Reset(ptr noundef %46, i8 noundef zeroext 2)
  store i32 %47, ptr %3, align 4, !tbaa !17
  %48 = load i32, ptr %3, align 4, !tbaa !17
  %49 = sext i32 %48 to i64
  %50 = icmp ne i64 %49, 0
  br i1 %50, label %51, label %52

51:                                               ; preds = %37
  store i32 1, ptr %3, align 4, !tbaa !17
  br label %53

52:                                               ; preds = %37
  store i32 0, ptr %3, align 4, !tbaa !17
  br label %53

53:                                               ; preds = %52, %51, %24, %15
  %54 = load i32, ptr %3, align 4, !tbaa !17
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret i32 %54
}

declare void @usleep(i64 noundef) #1

declare i32 @XSdPs_Reset(ptr noundef, i8 noundef zeroext) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !7, i64 54}
!10 = !{!"", !11, i64 0, !13, i64 36, !13, i64 40, !13, i64 44, !13, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !13, i64 56, !7, i64 60, !7, i64 64, !13, i64 80, !7, i64 84, !13, i64 100, !13, i64 104, !13, i64 108, !13, i64 112, !13, i64 116, !14, i64 120, !12, i64 128, !13, i64 132, !7, i64 136, !13, i64 140}
!11 = !{!"", !12, i64 0, !13, i64 4, !13, i64 8, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"int", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!10, !13, i64 40}
!16 = !{!10, !7, i64 52}
!17 = !{!13, !13, i64 0}
!18 = !{!10, !13, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_IdentifyCard(ptr noundef %0) local_unnamed_addr #2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 54
  %3 = load i8, ptr %2, align 2, !tbaa !5
  %4 = icmp eq i8 %3, 2
  br i1 %4, label %5, label %12

5:                                                ; preds = %1
  %6 = getelementptr inbounds i8, ptr %0, i64 40
  %7 = load i32, ptr %6, align 8, !tbaa !13
  %8 = and i32 %7, -1073741824
  %9 = icmp eq i32 %8, 1073741824
  br i1 %9, label %10, label %12

10:                                               ; preds = %5
  %11 = getelementptr inbounds i8, ptr %0, i64 52
  store i8 5, ptr %11, align 4, !tbaa !14
  br label %21

12:                                               ; preds = %5, %1
  tail call void @usleep(i64 noundef 10000) #3
  %13 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 0, i32 noundef 0, i32 noundef 0) #3
  %.not = icmp eq i32 %13, 0
  br i1 %.not, label %14, label %21

14:                                               ; preds = %12
  %15 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 256, i32 noundef 1090486272, i32 noundef 0) #3
  %.not13 = icmp eq i32 %15, 0
  %spec.select = select i1 %.not13, i8 2, i8 1
  %16 = getelementptr inbounds i8, ptr %0, i64 52
  store i8 %spec.select, ptr %16, align 4
  %17 = getelementptr inbounds i8, ptr %0, i64 4
  %18 = load i32, ptr %17, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %18, i8 noundef zeroext 48, i16 noundef zeroext -1)
  %19 = load i32, ptr %17, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %19, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  %20 = tail call i32 @XSdPs_Reset(ptr noundef nonnull %0, i8 noundef zeroext 2) #3
  %.not14 = icmp ne i32 %20, 0
  %. = zext i1 %.not14 to i32
  br label %21

21:                                               ; preds = %14, %12, %10
  %.0 = phi i32 [ 0, %10 ], [ 1, %12 ], [ %., %14 ]
  ret i32 %.0
}

declare void @usleep(i64 noundef) local_unnamed_addr #0

declare i32 @XSdPs_Reset(ptr noundef, i8 noundef zeroext) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 54}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !12, i64 120, !8, i64 128, !11, i64 132, !9, i64 136, !11, i64 140}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"long", !9, i64 0}
!13 = !{!6, !11, i64 40}
!14 = !{!6, !9, i64 52}
!15 = !{!6, !11, i64 4}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MergedLoadStoreMotionPass,SROAPass,SimplifyCFGPass,TailCallElimPass