; LLVM IR from tangjz/acm-icpc :: 51nod (1479)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@t = external dso_local global i32, align 4
@m = external dso_local global i32, align 4
@a = external dso_local global i32, align 4
@b = external dso_local global i32, align 4
@c = external dso_local global i32, align 4
@pow2 = external dso_local global i32, align 4
@x = external dso_local global i32, align 4
@y = external dso_local global i32, align 4
@z = external dso_local global i32, align 4
@.str = external hidden unnamed_addr constant [3 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [9 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [10 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7mod_powixi(i32 noundef, i64 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #2 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  %14 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef @t)
  br label %15

15:                                               ; preds = %266, %0
  %16 = load i32, ptr @t, align 4, !tbaa !5
  %17 = add nsw i32 %16, -1
  store i32 %17, ptr @t, align 4, !tbaa !5
  %18 = icmp ne i32 %16, 0
  br i1 %18, label %19, label %271

19:                                               ; preds = %15
  store i32 0, ptr @z, align 4, !tbaa !5
  store i32 0, ptr @y, align 4, !tbaa !5
  store i32 0, ptr @x, align 4, !tbaa !5
  %20 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str.1, ptr noundef @m, ptr noundef @a, ptr noundef @b, ptr noundef @c)
  store i32 0, ptr @pow2, align 4, !tbaa !5
  br label %21

21:                                               ; preds = %29, %19
  %22 = load i32, ptr @m, align 4, !tbaa !5
  %23 = load i32, ptr @pow2, align 4, !tbaa !5
  %24 = ashr i32 %22, %23
  %25 = xor i32 %24, -1
  %26 = and i32 %25, 1
  %27 = icmp ne i32 %26, 0
  br i1 %27, label %28, label %32

28:                                               ; preds = %21
  br label %29

29:                                               ; preds = %28
  %30 = load i32, ptr @pow2, align 4, !tbaa !5
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr @pow2, align 4, !tbaa !5
  br label %21, !llvm.loop !9

32:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #6
  %33 = load i32, ptr @m, align 4, !tbaa !5
  %34 = load i32, ptr @pow2, align 4, !tbaa !5
  %35 = ashr i32 %33, %34
  %36 = load i32, ptr @pow2, align 4, !tbaa !5
  %37 = shl i32 1, %36
  call void @_Z5exgcdIiEvT_S0_RS0_S1_(i32 noundef %35, i32 noundef %37, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 4 dereferenceable(4) %3)
  %38 = load i32, ptr @c, align 4, !tbaa !5
  %39 = icmp eq i32 %38, 1
  br i1 %39, label %40, label %41

40:                                               ; preds = %32
  store i32 1, ptr %5, align 4, !tbaa !5
  store i32 1, ptr %4, align 4, !tbaa !5
  store i32 2, ptr %6, align 4, !tbaa !5
  br label %103

41:                                               ; preds = %32
  %42 = load i32, ptr @a, align 4, !tbaa !5
  %43 = icmp eq i32 %42, 1
  br i1 %43, label %44, label %52

44:                                               ; preds = %41
  %45 = load i32, ptr @b, align 4, !tbaa !5
  %46 = icmp eq i32 %45, 1
  br i1 %46, label %47, label %52

47:                                               ; preds = %44
  store i32 2, ptr %4, align 4, !tbaa !5
  %48 = load i32, ptr @m, align 4, !tbaa !5
  %49 = load i32, ptr @pow2, align 4, !tbaa !5
  %50 = ashr i32 %48, %49
  %51 = sub nsw i32 %50, 1
  store i32 %51, ptr %5, align 4, !tbaa !5
  store i32 1, ptr %6, align 4, !tbaa !5
  br label %102

52:                                               ; preds = %44, %41
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #6
  %53 = load i32, ptr @c, align 4, !tbaa !5
  %54 = sext i32 %53 to i64
  %55 = load i32, ptr @a, align 4, !tbaa !5
  %56 = sext i32 %55 to i64
  %57 = load i32, ptr @b, align 4, !tbaa !5
  %58 = sext i32 %57 to i64
  %59 = mul nsw i64 %56, %58
  call void @_Z5exgcdIxEvT_S0_RS0_S1_(i64 noundef %54, i64 noundef %59, ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %60 = load i64, ptr %7, align 8, !tbaa !11
  %61 = icmp slt i64 %60, 0
  br i1 %61, label %62, label %70

62:                                               ; preds = %52
  %63 = load i32, ptr @a, align 4, !tbaa !5
  %64 = sext i32 %63 to i64
  %65 = load i32, ptr @b, align 4, !tbaa !5
  %66 = sext i32 %65 to i64
  %67 = mul nsw i64 %64, %66
  %68 = load i64, ptr %7, align 8, !tbaa !11
  %69 = add nsw i64 %68, %67
  store i64 %69, ptr %7, align 8, !tbaa !11
  br label %70

70:                                               ; preds = %62, %52
  %71 = load i64, ptr %8, align 8, !tbaa !11
  %72 = sub nsw i64 0, %71
  store i64 %72, ptr %8, align 8, !tbaa !11
  %73 = load i64, ptr %8, align 8, !tbaa !11
  %74 = icmp slt i64 %73, 0
  br i1 %74, label %75, label %80

75:                                               ; preds = %70
  %76 = load i32, ptr @c, align 4, !tbaa !5
  %77 = sext i32 %76 to i64
  %78 = load i64, ptr %8, align 8, !tbaa !11
  %79 = add nsw i64 %78, %77
  store i64 %79, ptr %8, align 8, !tbaa !11
  br label %80

80:                                               ; preds = %75, %70
  %81 = load i32, ptr @b, align 4, !tbaa !5
  %82 = sext i32 %81 to i64
  %83 = load i64, ptr %8, align 8, !tbaa !11
  %84 = mul nsw i64 %82, %83
  %85 = load i32, ptr @m, align 4, !tbaa !5
  %86 = load i32, ptr @pow2, align 4, !tbaa !5
  %87 = ashr i32 %85, %86
  %88 = call noundef i32 @_Z7mod_powixi(i32 noundef 2, i64 noundef %84, i32 noundef %87)
  store i32 %88, ptr %4, align 4, !tbaa !5
  %89 = load i32, ptr @a, align 4, !tbaa !5
  %90 = sext i32 %89 to i64
  %91 = load i64, ptr %8, align 8, !tbaa !11
  %92 = mul nsw i64 %90, %91
  %93 = load i32, ptr @m, align 4, !tbaa !5
  %94 = load i32, ptr @pow2, align 4, !tbaa !5
  %95 = ashr i32 %93, %94
  %96 = call noundef i32 @_Z7mod_powixi(i32 noundef 2, i64 noundef %92, i32 noundef %95)
  store i32 %96, ptr %5, align 4, !tbaa !5
  %97 = load i64, ptr %7, align 8, !tbaa !11
  %98 = load i32, ptr @m, align 4, !tbaa !5
  %99 = load i32, ptr @pow2, align 4, !tbaa !5
  %100 = ashr i32 %98, %99
  %101 = call noundef i32 @_Z7mod_powixi(i32 noundef 2, i64 noundef %97, i32 noundef %100)
  store i32 %101, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #6
  br label %102

102:                                              ; preds = %80, %47
  br label %103

103:                                              ; preds = %102, %40
  %104 = load i32, ptr @x, align 4, !tbaa !5
  %105 = sext i32 %104 to i64
  %106 = load i32, ptr @pow2, align 4, !tbaa !5
  %107 = shl i32 1, %106
  %108 = load i32, ptr %3, align 4, !tbaa !5
  %109 = mul nsw i32 %107, %108
  %110 = sext i32 %109 to i64
  %111 = load i32, ptr %4, align 4, !tbaa !5
  %112 = sext i32 %111 to i64
  %113 = mul nsw i64 %110, %112
  %114 = add nsw i64 %105, %113
  %115 = load i32, ptr @m, align 4, !tbaa !5
  %116 = sext i32 %115 to i64
  %117 = srem i64 %114, %116
  %118 = trunc i64 %117 to i32
  store i32 %118, ptr @x, align 4, !tbaa !5
  %119 = load i32, ptr @y, align 4, !tbaa !5
  %120 = sext i32 %119 to i64
  %121 = load i32, ptr @pow2, align 4, !tbaa !5
  %122 = shl i32 1, %121
  %123 = load i32, ptr %3, align 4, !tbaa !5
  %124 = mul nsw i32 %122, %123
  %125 = sext i32 %124 to i64
  %126 = load i32, ptr %5, align 4, !tbaa !5
  %127 = sext i32 %126 to i64
  %128 = mul nsw i64 %125, %127
  %129 = add nsw i64 %120, %128
  %130 = load i32, ptr @m, align 4, !tbaa !5
  %131 = sext i32 %130 to i64
  %132 = srem i64 %129, %131
  %133 = trunc i64 %132 to i32
  store i32 %133, ptr @y, align 4, !tbaa !5
  %134 = load i32, ptr @z, align 4, !tbaa !5
  %135 = sext i32 %134 to i64
  %136 = load i32, ptr @pow2, align 4, !tbaa !5
  %137 = shl i32 1, %136
  %138 = load i32, ptr %3, align 4, !tbaa !5
  %139 = mul nsw i32 %137, %138
  %140 = sext i32 %139 to i64
  %141 = load i32, ptr %6, align 4, !tbaa !5
  %142 = sext i32 %141 to i64
  %143 = mul nsw i64 %140, %142
  %144 = add nsw i64 %135, %143
  %145 = load i32, ptr @m, align 4, !tbaa !5
  %146 = sext i32 %145 to i64
  %147 = srem i64 %144, %146
  %148 = trunc i64 %147 to i32
  store i32 %148, ptr @z, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #6
  %149 = load i32, ptr @pow2, align 4, !tbaa !5
  %150 = icmp ne i32 %149, 0
  br i1 %150, label %151, label %245

151:                                              ; preds = %103
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #6
  %152 = load i32, ptr @m, align 4, !tbaa !5
  %153 = load i32, ptr @pow2, align 4, !tbaa !5
  %154 = ashr i32 %152, %153
  %155 = load i32, ptr @pow2, align 4, !tbaa !5
  %156 = shl i32 1, %155
  call void @_Z5exgcdIiEvT_S0_RS0_S1_(i32 noundef %154, i32 noundef %156, ptr noundef nonnull align 4 dereferenceable(4) %9, ptr noundef nonnull align 4 dereferenceable(4) %10)
  %157 = load i32, ptr @pow2, align 4, !tbaa !5
  %158 = icmp sgt i32 %157, 1
  br i1 %158, label %159, label %195

159:                                              ; preds = %151
  %160 = load i32, ptr @a, align 4, !tbaa !5
  %161 = icmp eq i32 %160, 1
  br i1 %161, label %162, label %169

162:                                              ; preds = %159
  %163 = load i32, ptr @b, align 4, !tbaa !5
  %164 = icmp eq i32 %163, 1
  br i1 %164, label %165, label %169

165:                                              ; preds = %162
  %166 = load i32, ptr @c, align 4, !tbaa !5
  %167 = icmp eq i32 %166, 1
  br i1 %167, label %168, label %169

168:                                              ; preds = %165
  store i32 1, ptr %12, align 4, !tbaa !5
  store i32 1, ptr %11, align 4, !tbaa !5
  store i32 2, ptr %13, align 4, !tbaa !5
  br label %194

169:                                              ; preds = %165, %162, %159
  %170 = load i32, ptr @c, align 4, !tbaa !5
  %171 = icmp eq i32 %170, 1
  br i1 %171, label %172, label %180

172:                                              ; preds = %169
  store i32 1, ptr %13, align 4, !tbaa !5
  store i32 1, ptr %11, align 4, !tbaa !5
  %173 = load i32, ptr @pow2, align 4, !tbaa !5
  %174 = sub nsw i32 %173, 1
  %175 = shl i32 1, %174
  store i32 %175, ptr %12, align 4, !tbaa !5
  %176 = load i32, ptr @b, align 4, !tbaa !5
  %177 = icmp eq i32 %176, 1
  br i1 %177, label %178, label %179

178:                                              ; preds = %172
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %11, ptr noundef nonnull align 4 dereferenceable(4) %12) #6
  br label %179

179:                                              ; preds = %178, %172
  br label %193

180:                                              ; preds = %169
  store i32 1, ptr %11, align 4, !tbaa !5
  %181 = load i32, ptr @pow2, align 4, !tbaa !5
  %182 = shl i32 1, %181
  %183 = sub nsw i32 %182, 1
  store i32 %183, ptr %12, align 4, !tbaa !5
  %184 = load i32, ptr @pow2, align 4, !tbaa !5
  %185 = sub nsw i32 %184, 1
  %186 = shl i32 1, %185
  store i32 %186, ptr %13, align 4, !tbaa !5
  %187 = load i32, ptr @b, align 4, !tbaa !5
  %188 = xor i32 %187, -1
  %189 = and i32 %188, 1
  %190 = icmp ne i32 %189, 0
  br i1 %190, label %191, label %192

191:                                              ; preds = %180
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %11, ptr noundef nonnull align 4 dereferenceable(4) %12) #6
  br label %192

192:                                              ; preds = %191, %180
  br label %193

193:                                              ; preds = %192, %179
  br label %194

194:                                              ; preds = %193, %168
  br label %196

195:                                              ; preds = %151
  store i32 1, ptr %12, align 4, !tbaa !5
  store i32 1, ptr %11, align 4, !tbaa !5
  store i32 0, ptr %13, align 4, !tbaa !5
  br label %196

196:                                              ; preds = %195, %194
  %197 = load i32, ptr @x, align 4, !tbaa !5
  %198 = sext i32 %197 to i64
  %199 = load i32, ptr @m, align 4, !tbaa !5
  %200 = load i32, ptr @pow2, align 4, !tbaa !5
  %201 = ashr i32 %199, %200
  %202 = load i32, ptr %9, align 4, !tbaa !5
  %203 = mul nsw i32 %201, %202
  %204 = sext i32 %203 to i64
  %205 = load i32, ptr %11, align 4, !tbaa !5
  %206 = sext i32 %205 to i64
  %207 = mul nsw i64 %204, %206
  %208 = add nsw i64 %198, %207
  %209 = load i32, ptr @m, align 4, !tbaa !5
  %210 = sext i32 %209 to i64
  %211 = srem i64 %208, %210
  %212 = trunc i64 %211 to i32
  store i32 %212, ptr @x, align 4, !tbaa !5
  %213 = load i32, ptr @y, align 4, !tbaa !5
  %214 = sext i32 %213 to i64
  %215 = load i32, ptr @m, align 4, !tbaa !5
  %216 = load i32, ptr @pow2, align 4, !tbaa !5
  %217 = ashr i32 %215, %216
  %218 = load i32, ptr %9, align 4, !tbaa !5
  %219 = mul nsw i32 %217, %218
  %220 = sext i32 %219 to i64
  %221 = load i32, ptr %12, align 4, !tbaa !5
  %222 = sext i32 %221 to i64
  %223 = mul nsw i64 %220, %222
  %224 = add nsw i64 %214, %223
  %225 = load i32, ptr @m, align 4, !tbaa !5
  %226 = sext i32 %225 to i64
  %227 = srem i64 %224, %226
  %228 = trunc i64 %227 to i32
  store i32 %228, ptr @y, align 4, !tbaa !5
  %229 = load i32, ptr @z, align 4, !tbaa !5
  %230 = sext i32 %229 to i64
  %231 = load i32, ptr @m, align 4, !tbaa !5
  %232 = load i32, ptr @pow2, align 4, !tbaa !5
  %233 = ashr i32 %231, %232
  %234 = load i32, ptr %9, align 4, !tbaa !5
  %235 = mul nsw i32 %233, %234
  %236 = sext i32 %235 to i64
  %237 = load i32, ptr %13, align 4, !tbaa !5
  %238 = sext i32 %237 to i64
  %239 = mul nsw i64 %236, %238
  %240 = add nsw i64 %230, %239
  %241 = load i32, ptr @m, align 4, !tbaa !5
  %242 = sext i32 %241 to i64
  %243 = srem i64 %240, %242
  %244 = trunc i64 %243 to i32
  store i32 %244, ptr @z, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #6
  br label %245

245:                                              ; preds = %196, %103
  %246 = load i32, ptr @x, align 4, !tbaa !5
  %247 = icmp slt i32 %246, 0
  br i1 %247, label %248, label %252

248:                                              ; preds = %245
  %249 = load i32, ptr @m, align 4, !tbaa !5
  %250 = load i32, ptr @x, align 4, !tbaa !5
  %251 = add nsw i32 %250, %249
  store i32 %251, ptr @x, align 4, !tbaa !5
  br label %252

252:                                              ; preds = %248, %245
  %253 = load i32, ptr @y, align 4, !tbaa !5
  %254 = icmp slt i32 %253, 0
  br i1 %254, label %255, label %259

255:                                              ; preds = %252
  %256 = load i32, ptr @m, align 4, !tbaa !5
  %257 = load i32, ptr @y, align 4, !tbaa !5
  %258 = add nsw i32 %257, %256
  store i32 %258, ptr @y, align 4, !tbaa !5
  br label %259

259:                                              ; preds = %255, %252
  %260 = load i32, ptr @z, align 4, !tbaa !5
  %261 = icmp slt i32 %260, 0
  br i1 %261, label %262, label %266

262:                                              ; preds = %259
  %263 = load i32, ptr @m, align 4, !tbaa !5
  %264 = load i32, ptr @z, align 4, !tbaa !5
  %265 = add nsw i32 %264, %263
  store i32 %265, ptr @z, align 4, !tbaa !5
  br label %266

266:                                              ; preds = %262, %259
  %267 = load i32, ptr @x, align 4, !tbaa !5
  %268 = load i32, ptr @y, align 4, !tbaa !5
  %269 = load i32, ptr @z, align 4, !tbaa !5
  %270 = call i32 (ptr, ...) @printf(ptr noundef @.str.2, i32 noundef %267, i32 noundef %268, i32 noundef %269)
  br label %15, !llvm.loop !13

271:                                              ; preds = %15
  ret i32 0
}

declare i32 @__isoc99_scanf(ptr noundef, ...) #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5exgcdIiEvT_S0_RS0_S1_(i32 noundef, i32 noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5exgcdIxEvT_S0_RS0_S1_(i64 noundef, i64 noundef, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #5

declare i32 @printf(ptr noundef, ...) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = distinct !{!13, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@t = external dso_local global i32, align 4
@m = external dso_local global i32, align 4
@a = external dso_local global i32, align 4
@b = external dso_local global i32, align 4
@c = external dso_local global i32, align 4
@pow2 = external dso_local local_unnamed_addr global i32, align 4
@x = external dso_local local_unnamed_addr global i32, align 4
@y = external dso_local local_unnamed_addr global i32, align 4
@z = external dso_local local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [3 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [9 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [10 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7mod_powixi(i32 noundef, i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() local_unnamed_addr #2 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = tail call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull @t)
  %10 = load i32, ptr @t, align 4, !tbaa !5
  %11 = add nsw i32 %10, -1
  store i32 %11, ptr @t, align 4, !tbaa !5
  %.not22 = icmp eq i32 %10, 0
  br i1 %.not22, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %0, %178
  store i32 0, ptr @z, align 4, !tbaa !5
  store i32 0, ptr @y, align 4, !tbaa !5
  store i32 0, ptr @x, align 4, !tbaa !5
  %12 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str.1, ptr noundef nonnull @m, ptr noundef nonnull @a, ptr noundef nonnull @b, ptr noundef nonnull @c)
  %13 = load i32, ptr @m, align 4, !tbaa !5
  br label %14

14:                                               ; preds = %14, %.lr.ph
  %storemerge = phi i32 [ 0, %.lr.ph ], [ %17, %14 ]
  %15 = shl nuw i32 1, %storemerge
  %16 = and i32 %13, %15
  %.not17.not = icmp eq i32 %16, 0
  %17 = add nuw nsw i32 %storemerge, 1
  br i1 %.not17.not, label %14, label %18, !llvm.loop !9

18:                                               ; preds = %14
  store i32 %storemerge, ptr @pow2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #6
  %19 = ashr i32 %13, %storemerge
  call void @_Z5exgcdIiEvT_S0_RS0_S1_(i32 noundef %19, i32 noundef %15, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr noundef nonnull align 4 dereferenceable(4) %2)
  %20 = load i32, ptr @c, align 4, !tbaa !5
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %thread-pre-split, label %22

22:                                               ; preds = %18
  %23 = load i32, ptr @a, align 4, !tbaa !5
  %24 = icmp eq i32 %23, 1
  %25 = load i32, ptr @b, align 4
  %26 = icmp eq i32 %25, 1
  %or.cond = select i1 %24, i1 %26, i1 false
  br i1 %or.cond, label %27, label %32

27:                                               ; preds = %22
  %28 = load i32, ptr @m, align 4, !tbaa !5
  %29 = load i32, ptr @pow2, align 4, !tbaa !5
  %30 = ashr i32 %28, %29
  %31 = add nsw i32 %30, -1
  br label %76

32:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #6
  %33 = sext i32 %20 to i64
  %34 = sext i32 %23 to i64
  %35 = sext i32 %25 to i64
  %36 = mul nsw i64 %35, %34
  call void @_Z5exgcdIxEvT_S0_RS0_S1_(i64 noundef %33, i64 noundef %36, ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %37 = load i64, ptr %3, align 8, !tbaa !11
  %38 = icmp slt i64 %37, 0
  br i1 %38, label %39, label %46

39:                                               ; preds = %32
  %40 = load i32, ptr @a, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = load i32, ptr @b, align 4, !tbaa !5
  %43 = sext i32 %42 to i64
  %44 = mul nsw i64 %43, %41
  %45 = add nsw i64 %44, %37
  store i64 %45, ptr %3, align 8, !tbaa !11
  br label %46

46:                                               ; preds = %39, %32
  %47 = load i64, ptr %4, align 8, !tbaa !11
  %48 = sub nsw i64 0, %47
  store i64 %48, ptr %4, align 8, !tbaa !11
  %49 = icmp sgt i64 %47, 0
  br i1 %49, label %50, label %54

50:                                               ; preds = %46
  %51 = load i32, ptr @c, align 4, !tbaa !5
  %52 = sext i32 %51 to i64
  %53 = sub nsw i64 %52, %47
  store i64 %53, ptr %4, align 8, !tbaa !11
  br label %54

54:                                               ; preds = %50, %46
  %55 = phi i64 [ %53, %50 ], [ %48, %46 ]
  %56 = load i32, ptr @b, align 4, !tbaa !5
  %57 = sext i32 %56 to i64
  %58 = mul nsw i64 %55, %57
  %59 = load i32, ptr @m, align 4, !tbaa !5
  %60 = load i32, ptr @pow2, align 4, !tbaa !5
  %61 = ashr i32 %59, %60
  %62 = call noundef i32 @_Z7mod_powixi(i32 noundef 2, i64 noundef %58, i32 noundef %61)
  %63 = load i32, ptr @a, align 4, !tbaa !5
  %64 = sext i32 %63 to i64
  %65 = load i64, ptr %4, align 8, !tbaa !11
  %66 = mul nsw i64 %65, %64
  %67 = load i32, ptr @m, align 4, !tbaa !5
  %68 = load i32, ptr @pow2, align 4, !tbaa !5
  %69 = ashr i32 %67, %68
  %70 = call noundef i32 @_Z7mod_powixi(i32 noundef 2, i64 noundef %66, i32 noundef %69)
  %71 = load i64, ptr %3, align 8, !tbaa !11
  %72 = load i32, ptr @m, align 4, !tbaa !5
  %73 = load i32, ptr @pow2, align 4, !tbaa !5
  %74 = ashr i32 %72, %73
  %75 = call noundef i32 @_Z7mod_powixi(i32 noundef 2, i64 noundef %71, i32 noundef %74)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #6
  br label %thread-pre-split

thread-pre-split:                                 ; preds = %54, %18
  %.011.ph = phi i32 [ 1, %18 ], [ %62, %54 ]
  %.010.ph = phi i32 [ 1, %18 ], [ %70, %54 ]
  %.09.ph = phi i32 [ 2, %18 ], [ %75, %54 ]
  %.pr = load i32, ptr @pow2, align 4, !tbaa !5
  %.pre = load i32, ptr @m, align 4, !tbaa !5
  br label %76

76:                                               ; preds = %thread-pre-split, %27
  %77 = phi i32 [ %.pre, %thread-pre-split ], [ %28, %27 ]
  %78 = phi i32 [ %.pr, %thread-pre-split ], [ %29, %27 ]
  %.011 = phi i32 [ %.011.ph, %thread-pre-split ], [ 2, %27 ]
  %.010 = phi i32 [ %.010.ph, %thread-pre-split ], [ %31, %27 ]
  %.09 = phi i32 [ %.09.ph, %thread-pre-split ], [ 1, %27 ]
  %79 = load i32, ptr @x, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = load i32, ptr %2, align 4, !tbaa !5
  %82 = shl i32 %81, %78
  %83 = sext i32 %82 to i64
  %84 = sext i32 %.011 to i64
  %85 = mul nsw i64 %83, %84
  %86 = add nsw i64 %85, %80
  %87 = sext i32 %77 to i64
  %88 = srem i64 %86, %87
  %89 = trunc nsw i64 %88 to i32
  store i32 %89, ptr @x, align 4, !tbaa !5
  %90 = load i32, ptr @y, align 4, !tbaa !5
  %91 = sext i32 %90 to i64
  %92 = sext i32 %.010 to i64
  %93 = mul nsw i64 %83, %92
  %94 = add nsw i64 %93, %91
  %95 = srem i64 %94, %87
  %96 = trunc nsw i64 %95 to i32
  store i32 %96, ptr @y, align 4, !tbaa !5
  %97 = load i32, ptr @z, align 4, !tbaa !5
  %98 = sext i32 %97 to i64
  %99 = sext i32 %.09 to i64
  %100 = mul nsw i64 %83, %99
  %101 = add nsw i64 %100, %98
  %102 = srem i64 %101, %87
  %103 = trunc nsw i64 %102 to i32
  store i32 %103, ptr @z, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1) #6
  %.not18 = icmp eq i32 %78, 0
  br i1 %.not18, label %160, label %104

104:                                              ; preds = %76
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %8) #6
  %105 = ashr i32 %77, %78
  %106 = shl nuw i32 1, %78
  call void @_Z5exgcdIiEvT_S0_RS0_S1_(i32 noundef %105, i32 noundef %106, ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %107 = load i32, ptr @pow2, align 4, !tbaa !5
  %108 = icmp sgt i32 %107, 1
  br i1 %108, label %109, label %128

109:                                              ; preds = %104
  %110 = load i32, ptr @a, align 4, !tbaa !5
  %111 = icmp eq i32 %110, 1
  %112 = load i32, ptr @b, align 4
  %113 = icmp eq i32 %112, 1
  %or.cond3 = select i1 %111, i1 %113, i1 false
  %114 = load i32, ptr @c, align 4
  %115 = icmp eq i32 %114, 1
  %or.cond5 = select i1 %or.cond3, i1 %115, i1 false
  br i1 %or.cond5, label %116, label %117

116:                                              ; preds = %109
  store i32 1, ptr %8, align 4, !tbaa !5
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %129

117:                                              ; preds = %109
  store i32 1, ptr %7, align 4, !tbaa !5
  br i1 %115, label %118, label %122

118:                                              ; preds = %117
  %119 = add nsw i32 %107, -1
  %120 = shl nuw i32 1, %119
  store i32 %120, ptr %8, align 4, !tbaa !5
  br i1 %113, label %121, label %129

121:                                              ; preds = %118
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %7, ptr noundef nonnull align 4 dereferenceable(4) %8) #6
  br label %129

122:                                              ; preds = %117
  %notmask = shl nsw i32 -1, %107
  %123 = xor i32 %notmask, -1
  store i32 %123, ptr %8, align 4, !tbaa !5
  %124 = add nsw i32 %107, -1
  %125 = shl nuw i32 1, %124
  %126 = and i32 %112, 1
  %.not19.not = icmp eq i32 %126, 0
  br i1 %.not19.not, label %127, label %129

127:                                              ; preds = %122
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %7, ptr noundef nonnull align 4 dereferenceable(4) %8) #6
  br label %129

128:                                              ; preds = %104
  store i32 1, ptr %8, align 4, !tbaa !5
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %129

129:                                              ; preds = %116, %122, %127, %118, %121, %128
  %.0 = phi i32 [ 2, %116 ], [ 1, %121 ], [ 1, %118 ], [ %125, %127 ], [ %125, %122 ], [ 0, %128 ]
  %130 = load i32, ptr @x, align 4, !tbaa !5
  %131 = sext i32 %130 to i64
  %132 = load i32, ptr @m, align 4, !tbaa !5
  %133 = load i32, ptr @pow2, align 4, !tbaa !5
  %134 = ashr i32 %132, %133
  %135 = load i32, ptr %5, align 4, !tbaa !5
  %136 = mul nsw i32 %134, %135
  %137 = sext i32 %136 to i64
  %138 = load i32, ptr %7, align 4, !tbaa !5
  %139 = sext i32 %138 to i64
  %140 = mul nsw i64 %137, %139
  %141 = add nsw i64 %140, %131
  %142 = sext i32 %132 to i64
  %143 = srem i64 %141, %142
  %144 = trunc nsw i64 %143 to i32
  store i32 %144, ptr @x, align 4, !tbaa !5
  %145 = load i32, ptr @y, align 4, !tbaa !5
  %146 = sext i32 %145 to i64
  %147 = load i32, ptr %8, align 4, !tbaa !5
  %148 = sext i32 %147 to i64
  %149 = mul nsw i64 %148, %137
  %150 = add nsw i64 %149, %146
  %151 = srem i64 %150, %142
  %152 = trunc nsw i64 %151 to i32
  store i32 %152, ptr @y, align 4, !tbaa !5
  %153 = load i32, ptr @z, align 4, !tbaa !5
  %154 = sext i32 %153 to i64
  %155 = sext i32 %.0 to i64
  %156 = mul nsw i64 %137, %155
  %157 = add nsw i64 %156, %154
  %158 = srem i64 %157, %142
  %159 = trunc nsw i64 %158 to i32
  store i32 %159, ptr @z, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %8) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #6
  br label %160

160:                                              ; preds = %129, %76
  %161 = phi i32 [ %159, %129 ], [ %103, %76 ]
  %162 = phi i32 [ %152, %129 ], [ %96, %76 ]
  %163 = phi i32 [ %132, %129 ], [ %77, %76 ]
  %164 = phi i32 [ %144, %129 ], [ %89, %76 ]
  %165 = icmp slt i32 %164, 0
  br i1 %165, label %166, label %168

166:                                              ; preds = %160
  %167 = add nsw i32 %163, %164
  store i32 %167, ptr @x, align 4, !tbaa !5
  br label %168

168:                                              ; preds = %166, %160
  %169 = phi i32 [ %167, %166 ], [ %164, %160 ]
  %170 = icmp slt i32 %162, 0
  br i1 %170, label %171, label %173

171:                                              ; preds = %168
  %172 = add nsw i32 %163, %162
  store i32 %172, ptr @y, align 4, !tbaa !5
  br label %173

173:                                              ; preds = %171, %168
  %174 = phi i32 [ %172, %171 ], [ %162, %168 ]
  %175 = icmp slt i32 %161, 0
  br i1 %175, label %176, label %178

176:                                              ; preds = %173
  %177 = add nsw i32 %163, %161
  store i32 %177, ptr @z, align 4, !tbaa !5
  br label %178

178:                                              ; preds = %176, %173
  %179 = phi i32 [ %177, %176 ], [ %161, %173 ]
  %180 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.2, i32 noundef %169, i32 noundef %174, i32 noundef %179)
  %181 = load i32, ptr @t, align 4, !tbaa !5
  %182 = add nsw i32 %181, -1
  store i32 %182, ptr @t, align 4, !tbaa !5
  %.not = icmp eq i32 %181, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph, !llvm.loop !13

._crit_edge:                                      ; preds = %178, %0
  ret i32 0
}

; Function Attrs: nofree nounwind
declare noundef i32 @__isoc99_scanf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5exgcdIiEvT_S0_RS0_S1_(i32 noundef, i32 noundef, ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #4

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5exgcdIxEvT_S0_RS0_S1_(i64 noundef, i64 noundef, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #5

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = distinct !{!13, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass