; LLVM IR from Izaron/ACM-ICPC :: Timus Online Judge/Volume 2/1158. Censored!.ll (Z3addR6my_intS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.my_int = type { %"class.std::vector.11" }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3addR6my_intS_(ptr dead_on_unwind noalias writable sret(%struct.my_int) align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  store i64 0, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 9, ptr %8, align 4, !tbaa !11
  br label %9

9:                                                ; preds = %42, %3
  %10 = load i32, ptr %8, align 4, !tbaa !11
  %11 = icmp sge i32 %10, 0
  br i1 %11, label %13, label %12

12:                                               ; preds = %9
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %45

13:                                               ; preds = %9
  %14 = getelementptr inbounds %struct.my_int, ptr %2, i32 0, i32 0
  %15 = load i32, ptr %8, align 4, !tbaa !11
  %16 = sext i32 %15 to i64
  %17 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %16) #4
  %18 = load i64, ptr %17, align 8, !tbaa !9
  %19 = load i64, ptr %7, align 8, !tbaa !9
  %20 = add nsw i64 %18, %19
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.my_int, ptr %21, i32 0, i32 0
  %23 = load i32, ptr %8, align 4, !tbaa !11
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %24) #4
  %26 = load i64, ptr %25, align 8, !tbaa !9
  %27 = add nsw i64 %26, %20
  store i64 %27, ptr %25, align 8, !tbaa !9
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.my_int, ptr %28, i32 0, i32 0
  %30 = load i32, ptr %8, align 4, !tbaa !11
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #4
  %33 = load i64, ptr %32, align 8, !tbaa !9
  %34 = sdiv i64 %33, 10000000000
  store i64 %34, ptr %7, align 8, !tbaa !9
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.my_int, ptr %35, i32 0, i32 0
  %37 = load i32, ptr %8, align 4, !tbaa !11
  %38 = sext i32 %37 to i64
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %38) #4
  %40 = load i64, ptr %39, align 8, !tbaa !9
  %41 = srem i64 %40, 10000000000
  store i64 %41, ptr %39, align 8, !tbaa !9
  br label %42

42:                                               ; preds = %13
  %43 = load i32, ptr %8, align 4, !tbaa !11
  %44 = add nsw i32 %43, -1
  store i32 %44, ptr %8, align 4, !tbaa !11
  br label %9, !llvm.loop !13

45:                                               ; preds = %12
  %46 = load ptr, ptr %5, align 8, !tbaa !5
  call void @_ZN6my_intC2ERKS_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %46)
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN6my_intC2ERKS_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.my_int = type { %"class.std::vector.11" }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3addR6my_intS_(ptr dead_on_unwind noalias writable sret(%struct.my_int) align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull %2) local_unnamed_addr #1 {
  %4 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 9) #3
  %5 = load i64, ptr %4, align 8, !tbaa !5
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 9) #3
  %7 = load i64, ptr %6, align 8, !tbaa !5
  %8 = add nsw i64 %5, %7
  store i64 %8, ptr %6, align 8, !tbaa !5
  %9 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 9) #3
  %10 = load i64, ptr %9, align 8, !tbaa !5
  %11 = sdiv i64 %10, 10000000000
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 9) #3
  %13 = load i64, ptr %12, align 8, !tbaa !5
  %14 = srem i64 %13, 10000000000
  store i64 %14, ptr %12, align 8, !tbaa !5
  %15 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 8) #3
  %16 = load i64, ptr %15, align 8, !tbaa !5
  %17 = add nsw i64 %16, %11
  %18 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 8) #3
  %19 = load i64, ptr %18, align 8, !tbaa !5
  %20 = add nsw i64 %17, %19
  store i64 %20, ptr %18, align 8, !tbaa !5
  %21 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 8) #3
  %22 = load i64, ptr %21, align 8, !tbaa !5
  %23 = sdiv i64 %22, 10000000000
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 8) #3
  %25 = load i64, ptr %24, align 8, !tbaa !5
  %26 = srem i64 %25, 10000000000
  store i64 %26, ptr %24, align 8, !tbaa !5
  %27 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 7) #3
  %28 = load i64, ptr %27, align 8, !tbaa !5
  %29 = add nsw i64 %28, %23
  %30 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 7) #3
  %31 = load i64, ptr %30, align 8, !tbaa !5
  %32 = add nsw i64 %29, %31
  store i64 %32, ptr %30, align 8, !tbaa !5
  %33 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 7) #3
  %34 = load i64, ptr %33, align 8, !tbaa !5
  %35 = sdiv i64 %34, 10000000000
  %36 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 7) #3
  %37 = load i64, ptr %36, align 8, !tbaa !5
  %38 = srem i64 %37, 10000000000
  store i64 %38, ptr %36, align 8, !tbaa !5
  %39 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 6) #3
  %40 = load i64, ptr %39, align 8, !tbaa !5
  %41 = add nsw i64 %40, %35
  %42 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 6) #3
  %43 = load i64, ptr %42, align 8, !tbaa !5
  %44 = add nsw i64 %41, %43
  store i64 %44, ptr %42, align 8, !tbaa !5
  %45 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 6) #3
  %46 = load i64, ptr %45, align 8, !tbaa !5
  %47 = sdiv i64 %46, 10000000000
  %48 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 6) #3
  %49 = load i64, ptr %48, align 8, !tbaa !5
  %50 = srem i64 %49, 10000000000
  store i64 %50, ptr %48, align 8, !tbaa !5
  %51 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 5) #3
  %52 = load i64, ptr %51, align 8, !tbaa !5
  %53 = add nsw i64 %52, %47
  %54 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 5) #3
  %55 = load i64, ptr %54, align 8, !tbaa !5
  %56 = add nsw i64 %53, %55
  store i64 %56, ptr %54, align 8, !tbaa !5
  %57 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 5) #3
  %58 = load i64, ptr %57, align 8, !tbaa !5
  %59 = sdiv i64 %58, 10000000000
  %60 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 5) #3
  %61 = load i64, ptr %60, align 8, !tbaa !5
  %62 = srem i64 %61, 10000000000
  store i64 %62, ptr %60, align 8, !tbaa !5
  %63 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 4) #3
  %64 = load i64, ptr %63, align 8, !tbaa !5
  %65 = add nsw i64 %64, %59
  %66 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 4) #3
  %67 = load i64, ptr %66, align 8, !tbaa !5
  %68 = add nsw i64 %65, %67
  store i64 %68, ptr %66, align 8, !tbaa !5
  %69 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 4) #3
  %70 = load i64, ptr %69, align 8, !tbaa !5
  %71 = sdiv i64 %70, 10000000000
  %72 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 4) #3
  %73 = load i64, ptr %72, align 8, !tbaa !5
  %74 = srem i64 %73, 10000000000
  store i64 %74, ptr %72, align 8, !tbaa !5
  %75 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 3) #3
  %76 = load i64, ptr %75, align 8, !tbaa !5
  %77 = add nsw i64 %76, %71
  %78 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 3) #3
  %79 = load i64, ptr %78, align 8, !tbaa !5
  %80 = add nsw i64 %77, %79
  store i64 %80, ptr %78, align 8, !tbaa !5
  %81 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 3) #3
  %82 = load i64, ptr %81, align 8, !tbaa !5
  %83 = sdiv i64 %82, 10000000000
  %84 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 3) #3
  %85 = load i64, ptr %84, align 8, !tbaa !5
  %86 = srem i64 %85, 10000000000
  store i64 %86, ptr %84, align 8, !tbaa !5
  %87 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 2) #3
  %88 = load i64, ptr %87, align 8, !tbaa !5
  %89 = add nsw i64 %88, %83
  %90 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 2) #3
  %91 = load i64, ptr %90, align 8, !tbaa !5
  %92 = add nsw i64 %89, %91
  store i64 %92, ptr %90, align 8, !tbaa !5
  %93 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 2) #3
  %94 = load i64, ptr %93, align 8, !tbaa !5
  %95 = sdiv i64 %94, 10000000000
  %96 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 2) #3
  %97 = load i64, ptr %96, align 8, !tbaa !5
  %98 = srem i64 %97, 10000000000
  store i64 %98, ptr %96, align 8, !tbaa !5
  %99 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 1) #3
  %100 = load i64, ptr %99, align 8, !tbaa !5
  %101 = add nsw i64 %100, %95
  %102 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 1) #3
  %103 = load i64, ptr %102, align 8, !tbaa !5
  %104 = add nsw i64 %101, %103
  store i64 %104, ptr %102, align 8, !tbaa !5
  %105 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 1) #3
  %106 = load i64, ptr %105, align 8, !tbaa !5
  %107 = sdiv i64 %106, 10000000000
  %108 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 1) #3
  %109 = load i64, ptr %108, align 8, !tbaa !5
  %110 = srem i64 %109, 10000000000
  store i64 %110, ptr %108, align 8, !tbaa !5
  %111 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef 0) #3
  %112 = load i64, ptr %111, align 8, !tbaa !5
  %113 = add nsw i64 %112, %107
  %114 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 0) #3
  %115 = load i64, ptr %114, align 8, !tbaa !5
  %116 = add nsw i64 %113, %115
  store i64 %116, ptr %114, align 8, !tbaa !5
  %117 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 0) #3
  %118 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 0) #3
  %119 = load i64, ptr %118, align 8, !tbaa !5
  %120 = srem i64 %119, 10000000000
  store i64 %120, ptr %118, align 8, !tbaa !5
  tail call void @_ZN6my_intC2ERKS_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1)
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN6my_intC2ERKS_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass