; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/zynq_fsbl (qspi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@FlashReadBaseAddress = external global i32, align 4
@LinearBootDeviceFlag = external global i8, align 1
@ReadBuffer = external dso_local global [4101 x i8], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @FlashRead(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @QspiAccess(i32 noundef %0, i32 noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i8, align 1
  %14 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #3
  store i8 1, ptr %13, align 1, !tbaa !9
  %15 = load i8, ptr @LinearBootDeviceFlag, align 1, !tbaa !9
  %16 = zext i8 %15 to i32
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %18, label %39

18:                                               ; preds = %3
  %19 = load i32, ptr %7, align 4, !tbaa !5
  %20 = urem i32 %19, 4
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %28

22:                                               ; preds = %18
  %23 = load i32, ptr %7, align 4, !tbaa !5
  %24 = and i32 %23, 3
  %25 = sub i32 4, %24
  %26 = load i32, ptr %7, align 4, !tbaa !5
  %27 = add i32 %26, %25
  store i32 %27, ptr %7, align 4, !tbaa !5
  br label %28

28:                                               ; preds = %22, %18
  %29 = load i32, ptr %6, align 4, !tbaa !5
  %30 = zext i32 %29 to i64
  %31 = inttoptr i64 %30 to ptr
  %32 = load i32, ptr %5, align 4, !tbaa !5
  %33 = load i32, ptr @FlashReadBaseAddress, align 4, !tbaa !5
  %34 = add i32 %32, %33
  %35 = zext i32 %34 to i64
  %36 = inttoptr i64 %35 to ptr
  %37 = load i32, ptr %7, align 4, !tbaa !5
  %38 = zext i32 %37 to i64
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %31, ptr align 1 %36, i64 %38, i1 false)
  br label %109

39:                                               ; preds = %3
  %40 = load i32, ptr %6, align 4, !tbaa !5
  %41 = zext i32 %40 to i64
  %42 = inttoptr i64 %41 to ptr
  store ptr %42, ptr %8, align 8, !tbaa !10
  br label %43

43:                                               ; preds = %84, %39
  %44 = load i32, ptr %7, align 4, !tbaa !5
  %45 = icmp ugt i32 %44, 0
  br i1 %45, label %46, label %102

46:                                               ; preds = %43
  %47 = load i32, ptr %7, align 4, !tbaa !5
  %48 = icmp ugt i32 %47, 4096
  br i1 %48, label %49, label %50

49:                                               ; preds = %46
  store i32 4096, ptr %9, align 4, !tbaa !5
  br label %52

50:                                               ; preds = %46
  %51 = load i32, ptr %7, align 4, !tbaa !5
  store i32 %51, ptr %9, align 4, !tbaa !5
  br label %52

52:                                               ; preds = %50, %49
  %53 = load i32, ptr %5, align 4, !tbaa !5
  %54 = icmp uge i32 %53, 16777216
  br i1 %54, label %55, label %70

55:                                               ; preds = %52
  %56 = load i8, ptr %13, align 1, !tbaa !9
  %57 = zext i8 %56 to i32
  %58 = icmp eq i32 %57, 1
  br i1 %58, label %59, label %70

59:                                               ; preds = %55
  %60 = load i32, ptr %5, align 4, !tbaa !5
  %61 = udiv i32 %60, 16777216
  store i32 %61, ptr %10, align 4, !tbaa !5
  %62 = load i32, ptr %10, align 4, !tbaa !5
  %63 = trunc i32 %62 to i8
  %64 = call i32 @SendBankSelect(i8 noundef zeroext %63)
  store i32 %64, ptr %12, align 4, !tbaa !5
  %65 = load i32, ptr %12, align 4, !tbaa !5
  %66 = zext i32 %65 to i64
  %67 = icmp ne i64 %66, 0
  br i1 %67, label %68, label %69

68:                                               ; preds = %59
  store i32 1, ptr %4, align 4
  store i32 1, ptr %14, align 4
  br label %110

69:                                               ; preds = %59
  store i8 0, ptr %13, align 1, !tbaa !9
  br label %70

70:                                               ; preds = %69, %55, %52
  %71 = load i32, ptr %5, align 4, !tbaa !5
  %72 = and i32 %71, 251658240
  %73 = load i32, ptr %5, align 4, !tbaa !5
  %74 = load i32, ptr %9, align 4, !tbaa !5
  %75 = add i32 %73, %74
  %76 = and i32 %75, 251658240
  %77 = icmp ne i32 %72, %76
  br i1 %77, label %78, label %84

78:                                               ; preds = %70
  %79 = load i32, ptr %5, align 4, !tbaa !5
  %80 = and i32 %79, 251658240
  %81 = add i32 %80, 16777216
  %82 = load i32, ptr %5, align 4, !tbaa !5
  %83 = sub i32 %81, %82
  store i32 %83, ptr %9, align 4, !tbaa !5
  store i8 1, ptr %13, align 1, !tbaa !9
  br label %84

84:                                               ; preds = %78, %70
  %85 = load i32, ptr %5, align 4, !tbaa !5
  %86 = load i32, ptr %9, align 4, !tbaa !5
  call void @FlashRead(i32 noundef %85, i32 noundef %86)
  %87 = load ptr, ptr %8, align 8, !tbaa !10
  %88 = load i32, ptr %9, align 4, !tbaa !5
  %89 = zext i32 %88 to i64
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %87, ptr align 1 getelementptr inbounds ([4101 x i8], ptr @ReadBuffer, i64 0, i64 5), i64 %89, i1 false)
  %90 = load i32, ptr %9, align 4, !tbaa !5
  %91 = load i32, ptr %7, align 4, !tbaa !5
  %92 = sub i32 %91, %90
  store i32 %92, ptr %7, align 4, !tbaa !5
  %93 = load i32, ptr %9, align 4, !tbaa !5
  %94 = load i32, ptr %5, align 4, !tbaa !5
  %95 = add i32 %94, %93
  store i32 %95, ptr %5, align 4, !tbaa !5
  %96 = load ptr, ptr %8, align 8, !tbaa !10
  %97 = ptrtoint ptr %96 to i32
  %98 = load i32, ptr %9, align 4, !tbaa !5
  %99 = add i32 %97, %98
  %100 = zext i32 %99 to i64
  %101 = inttoptr i64 %100 to ptr
  store ptr %101, ptr %8, align 8, !tbaa !10
  br label %43, !llvm.loop !12

102:                                              ; preds = %43
  %103 = call i32 @SendBankSelect(i8 noundef zeroext 0)
  store i32 %103, ptr %12, align 4, !tbaa !5
  %104 = load i32, ptr %12, align 4, !tbaa !5
  %105 = zext i32 %104 to i64
  %106 = icmp ne i64 %105, 0
  br i1 %106, label %107, label %108

107:                                              ; preds = %102
  store i32 1, ptr %4, align 4
  store i32 1, ptr %14, align 4
  br label %110

108:                                              ; preds = %102
  br label %109

109:                                              ; preds = %108, %28
  store i32 0, ptr %4, align 4
  store i32 1, ptr %14, align 4
  br label %110

110:                                              ; preds = %109, %107, %68
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  %111 = load i32, ptr %4, align 4
  ret i32 %111
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @SendBankSelect(i8 noundef zeroext) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"any pointer", !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@FlashReadBaseAddress = external local_unnamed_addr global i32, align 4
@LinearBootDeviceFlag = external local_unnamed_addr global i8, align 1
@ReadBuffer = external dso_local local_unnamed_addr global [4101 x i8], align 16

; Function Attrs: nounwind uwtable
declare dso_local void @FlashRead(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @QspiAccess(i32 noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = load i8, ptr @LinearBootDeviceFlag, align 1, !tbaa !5
  %5 = icmp eq i8 %4, 1
  br i1 %5, label %6, label %.preheader

.preheader:                                       ; preds = %3
  %.not47 = icmp eq i32 %2, 0
  br i1 %.not47, label %._crit_edge, label %.lr.ph

6:                                                ; preds = %3
  %.biased = add i32 %2, 3
  %.037 = and i32 %.biased, -4
  %7 = zext i32 %1 to i64
  %8 = inttoptr i64 %7 to ptr
  %9 = load i32, ptr @FlashReadBaseAddress, align 4, !tbaa !8
  %10 = add i32 %9, %0
  %11 = zext i32 %10 to i64
  %12 = inttoptr i64 %11 to ptr
  %13 = zext i32 %.037 to i64
  tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 %8, ptr align 1 %12, i64 %13, i1 false)
  br label %30

.lr.ph:                                           ; preds = %.preheader, %20
  %.051 = phi i8 [ %.2, %20 ], [ 1, %.preheader ]
  %.036.in.in50 = phi i32 [ %28, %20 ], [ %1, %.preheader ]
  %.13849 = phi i32 [ %26, %20 ], [ %2, %.preheader ]
  %.03948 = phi i32 [ %27, %20 ], [ %0, %.preheader ]
  %.03652.in = zext i32 %.036.in.in50 to i64
  %.03652 = inttoptr i64 %.03652.in to ptr
  %..138 = tail call i32 @llvm.umin.i32(i32 %.13849, i32 4096)
  %14 = icmp ugt i32 %.03948, 16777215
  %15 = icmp eq i8 %.051, 1
  %or.cond = select i1 %14, i1 %15, i1 false
  br i1 %or.cond, label %16, label %20

16:                                               ; preds = %.lr.ph
  %17 = lshr i32 %.03948, 24
  %18 = trunc nuw i32 %17 to i8
  %19 = tail call i32 @SendBankSelect(i8 noundef zeroext %18)
  %.not42 = icmp eq i32 %19, 0
  br i1 %.not42, label %20, label %.loopexit

20:                                               ; preds = %16, %.lr.ph
  %.1 = phi i8 [ %.051, %.lr.ph ], [ 0, %16 ]
  %21 = and i32 %.03948, 251658240
  %22 = add i32 %..138, %.03948
  %23 = and i32 %22, 251658240
  %.not43 = icmp eq i32 %21, %23
  %reass.sub = sub i32 %21, %.03948
  %24 = add i32 %reass.sub, 16777216
  %.135 = select i1 %.not43, i32 %..138, i32 %24
  %.2 = select i1 %.not43, i8 %.1, i8 1
  tail call void @FlashRead(i32 noundef %.03948, i32 noundef %.135)
  %25 = zext i32 %.135 to i64
  tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 %.03652, ptr nonnull align 1 getelementptr inbounds (i8, ptr @ReadBuffer, i64 5), i64 %25, i1 false)
  %26 = sub i32 %.13849, %.135
  %27 = add i32 %.135, %.03948
  %28 = add i32 %.135, %.036.in.in50
  %.not = icmp eq i32 %26, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph, !llvm.loop !10

._crit_edge:                                      ; preds = %20, %.preheader
  %29 = tail call i32 @SendBankSelect(i8 noundef zeroext 0)
  %.not41 = icmp eq i32 %29, 0
  br i1 %.not41, label %30, label %.loopexit

30:                                               ; preds = %._crit_edge, %6
  br label %.loopexit

.loopexit:                                        ; preds = %16, %._crit_edge, %30
  %.033 = phi i32 [ 0, %30 ], [ 1, %._crit_edge ], [ 1, %16 ]
  ret i32 %.033
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @SendBankSelect(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass