; LLVM IR from FrancesoM/Bisc8FX :: sdk_projects/bisc8_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0_ (InitializeExistingMPURegConfig)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.anon = type { i64, i32 }
%struct.XMpuConfig = type { i32, i64, i64, i32 }

@region_size = external hidden constant [28 x %struct.anon], align 16
@Mpu_Config = external dso_local global [16 x %struct.XMpuConfig], section ".bootdata", align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_InitializeExistingMPURegConfig() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i64, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  store i32 0, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  store i32 0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  br label %13

13:                                               ; preds = %78, %0
  %14 = load i32, ptr %1, align 4, !tbaa !5
  %15 = icmp ult i32 %14, 16
  br i1 %15, label %16, label %81

16:                                               ; preds = %13
  %17 = load i32, ptr %1, align 4, !tbaa !5
  call void asm sideeffect "msr XREG_CP15_MPU_MEMORY_REG_NUMBER,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %17) #2, !srcloc !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  store i64 0, ptr %7, align 8, !tbaa !10
  %18 = call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_MPU_REG_SIZE_EN", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !12
  store i64 %18, ptr %7, align 8, !tbaa !10
  %19 = load i64, ptr %7, align 8, !tbaa !10
  store i64 %19, ptr %8, align 8, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  %20 = load i64, ptr %8, align 8, !tbaa !10
  %21 = trunc i64 %20 to i32
  store i32 %21, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #2
  store i64 0, ptr %9, align 8, !tbaa !10
  %22 = call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_MPU_REG_BASEADDR", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !13
  store i64 %22, ptr %9, align 8, !tbaa !10
  %23 = load i64, ptr %9, align 8, !tbaa !10
  store i64 %23, ptr %10, align 8, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #2
  %24 = load i64, ptr %10, align 8, !tbaa !10
  store i64 %24, ptr %4, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  store i64 0, ptr %11, align 8, !tbaa !10
  %25 = call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_MPU_REG_ACCESS_CTRL", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !14
  store i64 %25, ptr %11, align 8, !tbaa !10
  %26 = load i64, ptr %11, align 8, !tbaa !10
  store i64 %26, ptr %12, align 8, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  %27 = load i64, ptr %12, align 8, !tbaa !10
  %28 = trunc i64 %27 to i32
  store i32 %28, ptr %5, align 4, !tbaa !5
  %29 = load i32, ptr %3, align 4, !tbaa !5
  %30 = and i32 %29, 1
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %78

32:                                               ; preds = %16
  %33 = load i32, ptr %1, align 4, !tbaa !5
  %34 = zext i32 %33 to i64
  %35 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %34
  %36 = getelementptr inbounds %struct.XMpuConfig, ptr %35, i32 0, i32 0
  store i32 1, ptr %36, align 16, !tbaa !15
  %37 = load i64, ptr %4, align 8, !tbaa !10
  %38 = load i32, ptr %1, align 4, !tbaa !5
  %39 = zext i32 %38 to i64
  %40 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %39
  %41 = getelementptr inbounds %struct.XMpuConfig, ptr %40, i32 0, i32 1
  store i64 %37, ptr %41, align 8, !tbaa !17
  %42 = load i32, ptr %5, align 4, !tbaa !5
  %43 = load i32, ptr %1, align 4, !tbaa !5
  %44 = zext i32 %43 to i64
  %45 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %44
  %46 = getelementptr inbounds %struct.XMpuConfig, ptr %45, i32 0, i32 3
  store i32 %42, ptr %46, align 8, !tbaa !18
  %47 = load i32, ptr %3, align 4, !tbaa !5
  %48 = and i32 %47, -2
  store i32 %48, ptr %6, align 4, !tbaa !5
  %49 = load i32, ptr %6, align 4, !tbaa !5
  %50 = lshr i32 %49, 1
  store i32 %50, ptr %6, align 4, !tbaa !5
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %51

51:                                               ; preds = %74, %32
  %52 = load i32, ptr %2, align 4, !tbaa !5
  %53 = zext i32 %52 to i64
  %54 = icmp ult i64 %53, 28
  br i1 %54, label %55, label %77

55:                                               ; preds = %51
  %56 = load i32, ptr %6, align 4, !tbaa !5
  %57 = load i32, ptr %2, align 4, !tbaa !5
  %58 = zext i32 %57 to i64
  %59 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %58
  %60 = getelementptr inbounds %struct.anon, ptr %59, i32 0, i32 1
  %61 = load i32, ptr %60, align 8, !tbaa !19
  %62 = icmp ule i32 %56, %61
  br i1 %62, label %63, label %73

63:                                               ; preds = %55
  %64 = load i32, ptr %2, align 4, !tbaa !5
  %65 = zext i32 %64 to i64
  %66 = getelementptr inbounds [28 x %struct.anon], ptr @region_size, i64 0, i64 %65
  %67 = getelementptr inbounds %struct.anon, ptr %66, i32 0, i32 0
  %68 = load i64, ptr %67, align 16, !tbaa !21
  %69 = load i32, ptr %1, align 4, !tbaa !5
  %70 = zext i32 %69 to i64
  %71 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %70
  %72 = getelementptr inbounds %struct.XMpuConfig, ptr %71, i32 0, i32 2
  store i64 %68, ptr %72, align 16, !tbaa !22
  br label %77

73:                                               ; preds = %55
  br label %74

74:                                               ; preds = %73
  %75 = load i32, ptr %2, align 4, !tbaa !5
  %76 = add i32 %75, 1
  store i32 %76, ptr %2, align 4, !tbaa !5
  br label %51, !llvm.loop !23

77:                                               ; preds = %63, %51
  br label %78

78:                                               ; preds = %77, %16
  %79 = load i32, ptr %1, align 4, !tbaa !5
  %80 = add i32 %79, 1
  store i32 %80, ptr %1, align 4, !tbaa !5
  br label %13, !llvm.loop !25

81:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 2147716281}
!10 = !{!11, !11, i64 0}
!11 = !{!"long", !7, i64 0}
!12 = !{i64 2147716412}
!13 = !{i64 2147716552}
!14 = !{i64 2147716693}
!15 = !{!16, !6, i64 0}
!16 = !{!"XMpuConfig", !6, i64 0, !11, i64 8, !11, i64 16, !6, i64 24}
!17 = !{!16, !11, i64 8}
!18 = !{!16, !6, i64 24}
!19 = !{!20, !6, i64 8}
!20 = !{!"", !11, i64 0, !6, i64 8}
!21 = !{!20, !11, i64 0}
!22 = !{!16, !11, i64 16}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}
!25 = distinct !{!25, !24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.anon = type { i64, i32 }
%struct.XMpuConfig = type { i32, i64, i64, i32 }

@region_size = external hidden local_unnamed_addr constant [28 x %struct.anon], align 16
@Mpu_Config = external dso_local local_unnamed_addr global [16 x %struct.XMpuConfig], section ".bootdata", align 16

; Function Attrs: nounwind uwtable
define dso_local void @Xil_InitializeExistingMPURegConfig() local_unnamed_addr #0 {
  %1 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 8), align 8
  %2 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 24), align 8
  %3 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 40), align 8
  %4 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 56), align 8
  %5 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 72), align 8
  %6 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 88), align 8
  %7 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 104), align 8
  %8 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 120), align 8
  %9 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 136), align 8
  %10 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 152), align 8
  %11 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 168), align 8
  %12 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 184), align 8
  %13 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 200), align 8
  %14 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 216), align 8
  %15 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 232), align 8
  %16 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 248), align 8
  %17 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 264), align 8
  %18 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 280), align 8
  %19 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 296), align 8
  %20 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 312), align 8
  %21 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 328), align 8
  %22 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 344), align 8
  %23 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 360), align 8
  %24 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 376), align 8
  %25 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 392), align 8
  %26 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 408), align 8
  %27 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 424), align 8
  %28 = load i32, ptr getelementptr inbounds (i8, ptr @region_size, i64 440), align 8
  br label %29

29:                                               ; preds = %0, %.loopexit
  %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %.loopexit ]
  %30 = trunc nuw nsw i64 %indvars.iv to i32
  tail call void asm sideeffect "msr XREG_CP15_MPU_MEMORY_REG_NUMBER,${0:x}", "r,~{dirflag},~{fpsr},~{flags}"(i32 %30) #1, !srcloc !5
  %31 = tail call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_MPU_REG_SIZE_EN", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !6
  %32 = trunc i64 %31 to i32
  %33 = tail call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_MPU_REG_BASEADDR", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !7
  %34 = tail call i64 asm sideeffect "mrs ${0:x}, XREG_CP15_MPU_REG_ACCESS_CTRL", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !8
  %35 = and i32 %32, 1
  %.not = icmp eq i32 %35, 0
  br i1 %.not, label %.loopexit, label %36

36:                                               ; preds = %29
  %37 = trunc i64 %34 to i32
  %38 = getelementptr inbounds [16 x %struct.XMpuConfig], ptr @Mpu_Config, i64 0, i64 %indvars.iv
  store i32 1, ptr %38, align 16, !tbaa !9
  %39 = getelementptr inbounds i8, ptr %38, i64 8
  store i64 %33, ptr %39, align 8, !tbaa !15
  %40 = getelementptr inbounds i8, ptr %38, i64 24
  store i32 %37, ptr %40, align 8, !tbaa !16
  %41 = lshr i32 %32, 1
  %.not25 = icmp ugt i32 %41, %1
  br i1 %.not25, label %42, label %69

42:                                               ; preds = %36
  %.not25.1 = icmp ugt i32 %41, %2
  br i1 %.not25.1, label %43, label %69

43:                                               ; preds = %42
  %.not25.2 = icmp ugt i32 %41, %3
  br i1 %.not25.2, label %44, label %69

44:                                               ; preds = %43
  %.not25.3 = icmp ugt i32 %41, %4
  br i1 %.not25.3, label %45, label %69

45:                                               ; preds = %44
  %.not25.4 = icmp ugt i32 %41, %5
  br i1 %.not25.4, label %46, label %69

46:                                               ; preds = %45
  %.not25.5 = icmp ugt i32 %41, %6
  br i1 %.not25.5, label %47, label %69

47:                                               ; preds = %46
  %.not25.6 = icmp ugt i32 %41, %7
  br i1 %.not25.6, label %48, label %69

48:                                               ; preds = %47
  %.not25.7 = icmp ugt i32 %41, %8
  br i1 %.not25.7, label %49, label %69

49:                                               ; preds = %48
  %.not25.8 = icmp ugt i32 %41, %9
  br i1 %.not25.8, label %50, label %69

50:                                               ; preds = %49
  %.not25.9 = icmp ugt i32 %41, %10
  br i1 %.not25.9, label %51, label %69

51:                                               ; preds = %50
  %.not25.10 = icmp ugt i32 %41, %11
  br i1 %.not25.10, label %52, label %69

52:                                               ; preds = %51
  %.not25.11 = icmp ugt i32 %41, %12
  br i1 %.not25.11, label %53, label %69

53:                                               ; preds = %52
  %.not25.12 = icmp ugt i32 %41, %13
  br i1 %.not25.12, label %54, label %69

54:                                               ; preds = %53
  %.not25.13 = icmp ugt i32 %41, %14
  br i1 %.not25.13, label %55, label %69

55:                                               ; preds = %54
  %.not25.14 = icmp ugt i32 %41, %15
  br i1 %.not25.14, label %56, label %69

56:                                               ; preds = %55
  %.not25.15 = icmp ugt i32 %41, %16
  br i1 %.not25.15, label %57, label %69

57:                                               ; preds = %56
  %.not25.16 = icmp ugt i32 %41, %17
  br i1 %.not25.16, label %58, label %69

58:                                               ; preds = %57
  %.not25.17 = icmp ugt i32 %41, %18
  br i1 %.not25.17, label %59, label %69

59:                                               ; preds = %58
  %.not25.18 = icmp ugt i32 %41, %19
  br i1 %.not25.18, label %60, label %69

60:                                               ; preds = %59
  %.not25.19 = icmp ugt i32 %41, %20
  br i1 %.not25.19, label %61, label %69

61:                                               ; preds = %60
  %.not25.20 = icmp ugt i32 %41, %21
  br i1 %.not25.20, label %62, label %69

62:                                               ; preds = %61
  %.not25.21 = icmp ugt i32 %41, %22
  br i1 %.not25.21, label %63, label %69

63:                                               ; preds = %62
  %.not25.22 = icmp ugt i32 %41, %23
  br i1 %.not25.22, label %64, label %69

64:                                               ; preds = %63
  %.not25.23 = icmp ugt i32 %41, %24
  br i1 %.not25.23, label %65, label %69

65:                                               ; preds = %64
  %.not25.24 = icmp ugt i32 %41, %25
  br i1 %.not25.24, label %66, label %69

66:                                               ; preds = %65
  %.not25.25 = icmp ugt i32 %41, %26
  br i1 %.not25.25, label %67, label %69

67:                                               ; preds = %66
  %.not25.26 = icmp ugt i32 %41, %27
  br i1 %.not25.26, label %68, label %69

68:                                               ; preds = %67
  %.not25.27 = icmp ugt i32 %41, %28
  br i1 %.not25.27, label %.loopexit, label %69

69:                                               ; preds = %68, %67, %66, %65, %64, %63, %62, %61, %60, %59, %58, %57, %56, %55, %54, %53, %52, %51, %50, %49, %48, %47, %46, %45, %44, %43, %42, %36
  %.lcssa = phi ptr [ @region_size, %36 ], [ getelementptr inbounds (i8, ptr @region_size, i64 16), %42 ], [ getelementptr inbounds (i8, ptr @region_size, i64 32), %43 ], [ getelementptr inbounds (i8, ptr @region_size, i64 48), %44 ], [ getelementptr inbounds (i8, ptr @region_size, i64 64), %45 ], [ getelementptr inbounds (i8, ptr @region_size, i64 80), %46 ], [ getelementptr inbounds (i8, ptr @region_size, i64 96), %47 ], [ getelementptr inbounds (i8, ptr @region_size, i64 112), %48 ], [ getelementptr inbounds (i8, ptr @region_size, i64 128), %49 ], [ getelementptr inbounds (i8, ptr @region_size, i64 144), %50 ], [ getelementptr inbounds (i8, ptr @region_size, i64 160), %51 ], [ getelementptr inbounds (i8, ptr @region_size, i64 176), %52 ], [ getelementptr inbounds (i8, ptr @region_size, i64 192), %53 ], [ getelementptr inbounds (i8, ptr @region_size, i64 208), %54 ], [ getelementptr inbounds (i8, ptr @region_size, i64 224), %55 ], [ getelementptr inbounds (i8, ptr @region_size, i64 240), %56 ], [ getelementptr inbounds (i8, ptr @region_size, i64 256), %57 ], [ getelementptr inbounds (i8, ptr @region_size, i64 272), %58 ], [ getelementptr inbounds (i8, ptr @region_size, i64 288), %59 ], [ getelementptr inbounds (i8, ptr @region_size, i64 304), %60 ], [ getelementptr inbounds (i8, ptr @region_size, i64 320), %61 ], [ getelementptr inbounds (i8, ptr @region_size, i64 336), %62 ], [ getelementptr inbounds (i8, ptr @region_size, i64 352), %63 ], [ getelementptr inbounds (i8, ptr @region_size, i64 368), %64 ], [ getelementptr inbounds (i8, ptr @region_size, i64 384), %65 ], [ getelementptr inbounds (i8, ptr @region_size, i64 400), %66 ], [ getelementptr inbounds (i8, ptr @region_size, i64 416), %67 ], [ getelementptr inbounds (i8, ptr @region_size, i64 432), %68 ]
  %70 = load i64, ptr %.lcssa, align 16, !tbaa !17
  %71 = getelementptr inbounds i8, ptr %38, i64 16
  store i64 %70, ptr %71, align 16, !tbaa !19
  br label %.loopexit

.loopexit:                                        ; preds = %68, %69, %29
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 16
  br i1 %exitcond.not, label %72, label %29, !llvm.loop !20

72:                                               ; preds = %.loopexit
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147716281}
!6 = !{i64 2147716412}
!7 = !{i64 2147716552}
!8 = !{i64 2147716693}
!9 = !{!10, !11, i64 0}
!10 = !{!"XMpuConfig", !11, i64 0, !14, i64 8, !14, i64 16, !11, i64 24}
!11 = !{!"int", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C/C++ TBAA"}
!14 = !{!"long", !12, i64 0}
!15 = !{!10, !14, i64 8}
!16 = !{!10, !11, i64 24}
!17 = !{!18, !14, i64 0}
!18 = !{!"", !14, i64 0, !11, i64 8}
!19 = !{!10, !14, i64 16}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass